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authorChunfeng Yun <chunfeng.yun@mediatek.com>2018-03-12 08:25:38 +0300
committerKishon Vijay Abraham I <kishon@ti.com>2018-03-16 11:10:42 +0300
commit4036325609abf29f0dfdffb6e598c56645820f4e (patch)
tree3582246d8a24f851bd25f8564bd73fcded261fc9 /drivers/phy/mediatek
parent124380cb0e7a5fb704a81d135e5b7b4904c1ef95 (diff)
downloadlinux-4036325609abf29f0dfdffb6e598c56645820f4e.tar.xz
phy: phy-mtk-tphy: keep default value of mcu_bus_ck_gate_en
The default value of mcu_bus_ck_gate_en is 1, if clear it, will prevent system to enter deep idle mode, so keep its default value and without affecting PCIe function. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'drivers/phy/mediatek')
-rw-r--r--drivers/phy/mediatek/phy-mtk-tphy.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 1e96d0740ef5..6073c25eb3f2 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -688,8 +688,7 @@ static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
u32 tmp;
tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
- tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN |
- P3C_REG_IP_SW_RST);
+ tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);