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author | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-25 04:22:11 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-25 04:22:11 +0300 |
commit | 8ff99ad04c2ebacb272ff9e4f6155c35be136b3d (patch) | |
tree | dcad63e7013852c2fe5efd6c7dae4f7e6fbccb5d /drivers/phy/renesas/r8a779f0-ether-serdes.c | |
parent | 9e6bfd42b14b45737cae8bc84c759f1874949b8b (diff) | |
parent | 3584f6392f09440769246d4936e1fcbff76ac3bc (diff) | |
download | linux-8ff99ad04c2ebacb272ff9e4f6155c35be136b3d.tar.xz |
Merge tag 'phy-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul:
"This features a bunch of new device support, a couple of new drivers,
yaml conversion and updates of a few drivers.
Core support:
- New devm_of_phy_optional_get() API with users and conversion
New hardware support:
- Mediatek MT7986 phy support
- Qualcomm SM8550 UFS, PCIe, combo phy support, SM6115 / SM4250 USB3
phy support, SM6350 combo phy support, SM6125 UFS PHY support amd
SM8350 & SM8450 combo phy support
- Qualcomm SNPS eUSB2 eUSB2 repeater drivers
- Allwinner F1C100s USB PHY support
- Tegra xusb support for Tegra234
Updates:
- Yaml conversion for Qualcomm pcie2 phy and usb-hsic-phy
- G4 mode support in Qualcomm UFS phy and support for various SoCs
- Yaml conversion for Meson usb2 phy
- TI Type C support for usb phy for j721
- Yaml conversion for Tegra xusb binding"
* tag 'phy-for-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (106 commits)
phy: qcom: phy-qcom-snps-eusb2: Add support for eUSB2 repeater
phy: qcom: Add QCOM SNPS eUSB2 repeater driver
dt-bindings: phy: qcom,snps-eusb2-phy: Add phys property for the repeater
dt-bindings: phy: Add qcom,snps-eusb2-repeater schema file
dt-bindings: phy: amlogic,g12a-usb3-pcie-phy: add missing optional phy-supply property
phy: rockchip-typec: Fix unsigned comparison with less than zero
phy: rockchip-typec: fix tcphy_get_mode error case
phy: qcom: snps-eusb2: Add missing headers
phy: qcom-qmp-combo: Add support for SM8550
phy: qcom-qmp: Add v6 DP register offsets
phy: qcom-qmp: pcs-usb: Add v6 register offsets
dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Document SM8550 compatible
phy: qcom: Add QCOM SNPS eUSB2 driver
dt-bindings: phy: Add qcom,snps-eusb2-phy schema file
phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs
phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets
phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsets
phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets
phy: qcom-qmp: pcs-pcie: Add v6 register offsets
phy: qcom-qmp: pcs: Add v6.20 register offsets
...
Diffstat (limited to 'drivers/phy/renesas/r8a779f0-ether-serdes.c')
-rw-r--r-- | drivers/phy/renesas/r8a779f0-ether-serdes.c | 65 |
1 files changed, 30 insertions, 35 deletions
diff --git a/drivers/phy/renesas/r8a779f0-ether-serdes.c b/drivers/phy/renesas/r8a779f0-ether-serdes.c index e7588a940d69..c5206ef9195b 100644 --- a/drivers/phy/renesas/r8a779f0-ether-serdes.c +++ b/drivers/phy/renesas/r8a779f0-ether-serdes.c @@ -18,7 +18,6 @@ #define R8A779F0_ETH_SERDES_BANK_SELECT 0x03fc #define R8A779F0_ETH_SERDES_TIMEOUT_US 100000 #define R8A779F0_ETH_SERDES_NUM_RETRY_LINKUP 3 -#define R8A779F0_ETH_SERDES_NUM_RETRY_INIT 3 struct r8a779f0_eth_serdes_drv_data; struct r8a779f0_eth_serdes_channel { @@ -242,51 +241,46 @@ static int r8a779f0_eth_serdes_hw_init(struct r8a779f0_eth_serdes_channel *chann if (ret) return ret; - ret = r8a779f0_eth_serdes_reg_wait(&dd->channel[0], 0x0000, 0x380, BIT(15), 0); + return r8a779f0_eth_serdes_reg_wait(&dd->channel[0], 0x0000, 0x380, BIT(15), 0); +} + +static int r8a779f0_eth_serdes_init(struct phy *p) +{ + struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p); + int ret; + + ret = r8a779f0_eth_serdes_hw_init(channel); + if (!ret) + channel->dd->initialized = true; + + return ret; +} + +static int r8a779f0_eth_serdes_hw_init_late(struct r8a779f0_eth_serdes_channel +*channel) +{ + int ret; + + ret = r8a779f0_eth_serdes_chan_setting(channel); if (ret) return ret; - for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) { - ret = r8a779f0_eth_serdes_chan_setting(&dd->channel[i]); - if (ret) - return ret; - } - - for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) { - ret = r8a779f0_eth_serdes_chan_speed(&dd->channel[i]); - if (ret) - return ret; - } + ret = r8a779f0_eth_serdes_chan_speed(channel); + if (ret) + return ret; - for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) - r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03c0, 0x380, 0x0000); - for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) - r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03d0, 0x380, 0x0000); + r8a779f0_eth_serdes_write32(channel->addr, 0x03c0, 0x380, 0x0000); - for (i = 0; i < R8A779F0_ETH_SERDES_NUM; i++) { - ret = r8a779f0_eth_serdes_monitor_linkup(&dd->channel[i]); - if (ret) - return ret; - } + r8a779f0_eth_serdes_write32(channel->addr, 0x03d0, 0x380, 0x0000); - return 0; + return r8a779f0_eth_serdes_monitor_linkup(channel); } -static int r8a779f0_eth_serdes_init(struct phy *p) +static int r8a779f0_eth_serdes_power_on(struct phy *p) { struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p); - int i, ret; - for (i = 0; i < R8A779F0_ETH_SERDES_NUM_RETRY_INIT; i++) { - ret = r8a779f0_eth_serdes_hw_init(channel); - if (!ret) { - channel->dd->initialized = true; - break; - } - usleep_range(1000, 2000); - } - - return ret; + return r8a779f0_eth_serdes_hw_init_late(channel); } static int r8a779f0_eth_serdes_set_mode(struct phy *p, enum phy_mode mode, @@ -319,6 +313,7 @@ static int r8a779f0_eth_serdes_set_speed(struct phy *p, int speed) static const struct phy_ops r8a779f0_eth_serdes_ops = { .init = r8a779f0_eth_serdes_init, + .power_on = r8a779f0_eth_serdes_power_on, .set_mode = r8a779f0_eth_serdes_set_mode, .set_speed = r8a779f0_eth_serdes_set_speed, }; |