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authorJohn Hubbard <jhubbard@nvidia.com>2019-01-13 04:29:09 +0300
committerKishon Vijay Abraham I <kishon@ti.com>2019-01-16 15:30:54 +0300
commit4fae92797879bd58bd5d4e39c790b515bce4a1af (patch)
tree6a4421efc0da82028a0cd451858a6f338acb26bb /drivers/phy
parent1138a442a0c5e97594ec63e898098b0c9e781172 (diff)
downloadlinux-4fae92797879bd58bd5d4e39c790b515bce4a1af.tar.xz
phy: fix build breakage: add PHY_MODE_SATA
Commit 49e54187ae0b ("ata: libahci_platform: comply to PHY framework") uses the PHY_MODE_SATA, but that enum had not yet been added. This caused a build failure for me, with today's linux.git. Also, there is a potentially conflicting (mis-named) PHY_MODE_SATA, hiding in the Marvell Berlin SATA PHY driver. Fix the build by: 1) Renaming Marvell's defined value to a more scoped name, in order to avoid any potential conflicts: PHY_BERLIN_MODE_SATA. 2) Adding the missing enum, which was going to be added anyway as part of [1]. [1] https://lkml.kernel.org/r/20190108163124.6409-3-miquel.raynal@bootlin.com Fixes: 49e54187ae0b ("ata: libahci_platform: comply to PHY framework") Cc: Grzegorz Jaszczyk <jaz@semihalf.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Jens Axboe <axboe@kernel.dk> Signed-off-by: John Hubbard <jhubbard@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'drivers/phy')
-rw-r--r--drivers/phy/marvell/phy-berlin-sata.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/phy/marvell/phy-berlin-sata.c b/drivers/phy/marvell/phy-berlin-sata.c
index a91fc67fc4e0..d70ba9bc42d9 100644
--- a/drivers/phy/marvell/phy-berlin-sata.c
+++ b/drivers/phy/marvell/phy-berlin-sata.c
@@ -32,7 +32,7 @@
/* register 0x01 */
#define REF_FREF_SEL_25 BIT(0)
-#define PHY_MODE_SATA (0x0 << 5)
+#define PHY_BERLIN_MODE_SATA (0x0 << 5)
/* register 0x02 */
#define USE_MAX_PLL_RATE BIT(12)
@@ -102,7 +102,8 @@ static int phy_berlin_sata_power_on(struct phy *phy)
/* set PHY mode and ref freq to 25 MHz */
phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,
- 0x00ff, REF_FREF_SEL_25 | PHY_MODE_SATA);
+ 0x00ff,
+ REF_FREF_SEL_25 | PHY_BERLIN_MODE_SATA);
/* set PHY up to 6 Gbps */
phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,