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| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2022-12-19 15:32:29 +0300 |
|---|---|---|
| committer | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2022-12-28 15:20:18 +0300 |
| commit | 203a1c3ecae70076e14a652ca44b7ad9302eecd3 (patch) | |
| tree | 12adf9a1e1fce206e46002f2ce1cc718d7077635 /drivers/pinctrl/intel/pinctrl-intel.c | |
| parent | 346c8364613a9862323386d75f511785696fbe52 (diff) | |
| download | linux-203a1c3ecae70076e14a652ca44b7ad9302eecd3.tar.xz | |
pinctrl: intel: Use same order of bit fields for PADCFG2
PADCFG0 and PADCFG1 are ordered from MSB to LSB, do the same
for PADCFG2 bit fields. No functional changes intended.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'drivers/pinctrl/intel/pinctrl-intel.c')
| -rw-r--r-- | drivers/pinctrl/intel/pinctrl-intel.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index ad32e3cfb4a7..038a5721ae52 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -88,9 +88,9 @@ #define PADCFG1_TERM_800 (BIT(2) | BIT(1) | BIT(0)) #define PADCFG2 0x008 -#define PADCFG2_DEBEN BIT(0) #define PADCFG2_DEBOUNCE_SHIFT 1 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) +#define PADCFG2_DEBEN BIT(0) #define DEBOUNCE_PERIOD_NSEC 31250 |