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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-12-19 15:53:49 +0300 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2023-12-20 15:04:04 +0300 |
| commit | 7d7cd22dc497dc79c2b1ae0e26cada1c5207d5dd (patch) | |
| tree | 0e13f4971b9601e38e9a8b1864f8e1348ffb06dc /drivers/pinctrl/starfive | |
| parent | 00bb152d62825b5f659d9b4ff87d49637e44eea0 (diff) | |
| download | linux-7d7cd22dc497dc79c2b1ae0e26cada1c5207d5dd.tar.xz | |
pinctrl: cy8c95x0: Cache muxed registers
Currently the port specific registers behind the PORTSEL mux aren't
cached in the regmap and thus the typical setup time for a single pin
on cy8c9560 is about 200msec on our system. The hotspot is the IRQ
(un)masking, which causes lots of R/W operations.
Introduce a separate regmap for muxed registers and helper functions
to use the newly introduced regmap for muxed register access under
the i2c lock.
With the new cache in place the typical pin setup time is reduced to
20msec, making it about 10 times faster. As a side effect the system
boot time is also reduced by 50%.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Link: https://lore.kernel.org/r/20231219125350.4031370-1-patrick.rudolph@9elements.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/starfive')
0 files changed, 0 insertions, 0 deletions