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authorUlrich Hecht <uli+renesas@fpond.eu>2021-01-12 19:59:08 +0300
committerGeert Uytterhoeven <geert+renesas@glider.be>2021-01-14 14:06:15 +0300
commit537db25ca330dce0087e7620b6c07c0a9aa766ed (patch)
tree9a2ded95eddcc1c52204ffbf5483bb0e79aa5391 /drivers/pinctrl
parente127ef2ed0a6099ca6ccc55ff11a812514b6aee6 (diff)
downloadlinux-537db25ca330dce0087e7620b6c07c0a9aa766ed.tar.xz
pinctrl: renesas: Add I/O voltage level flag
This patch adds config macros describing the voltage levels available on a pin. The current default (3.3V/1.8V) maps to zero to avoid having to change existing PFC implementations. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20210112165912.30876-3-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/renesas/pinctrl.c16
-rw-r--r--drivers/pinctrl/renesas/sh_pfc.h9
2 files changed, 23 insertions, 2 deletions
diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c
index ac542d278a38..a49f74730272 100644
--- a/drivers/pinctrl/renesas/pinctrl.c
+++ b/drivers/pinctrl/renesas/pinctrl.c
@@ -634,6 +634,9 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
}
case PIN_CONFIG_POWER_SOURCE: {
+ int idx = sh_pfc_get_pin_index(pfc, _pin);
+ const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
+ unsigned int lower_voltage;
u32 pocctrl, val;
int bit;
@@ -648,7 +651,10 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
val = sh_pfc_read(pfc, pocctrl);
spin_unlock_irqrestore(&pfc->lock, flags);
- arg = (val & BIT(bit)) ? 3300 : 1800;
+ lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
+ 2500 : 1800;
+
+ arg = (val & BIT(bit)) ? 3300 : lower_voltage;
break;
}
@@ -702,6 +708,9 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
case PIN_CONFIG_POWER_SOURCE: {
unsigned int mV = pinconf_to_config_argument(configs[i]);
+ int idx = sh_pfc_get_pin_index(pfc, _pin);
+ const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
+ unsigned int lower_voltage;
u32 pocctrl, val;
int bit;
@@ -712,7 +721,10 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
if (WARN(bit < 0, "invalid pin %#x", _pin))
return bit;
- if (mV != 1800 && mV != 3300)
+ lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
+ 2500 : 1800;
+
+ if (mV != lower_voltage && mV != 3300)
return -EINVAL;
spin_lock_irqsave(&pfc->lock, flags);
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index 1404bd897d25..9787dc893a33 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -31,6 +31,15 @@ enum {
SH_PFC_PIN_CFG_PULL_DOWN)
#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
+
+#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
+#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
+
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
+ SH_PFC_PIN_VOLTAGE_18_33)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
+ SH_PFC_PIN_VOLTAGE_25_33)
+
#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
struct sh_pfc_pin {