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authorLinus Torvalds <torvalds@linux-foundation.org>2016-07-29 03:06:51 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2016-07-29 03:06:51 +0300
commitd94ba9e7d8d5c821d0442f13b30b0140c1109c38 (patch)
treedb82a38b7341fc035228d6cd1270cf4468c229c3 /drivers/pinctrl
parent1c88e19b0f6a8471ee50d5062721ba30b8fd4ba9 (diff)
parent9573e7923007961799beff38bc5c5a7635634eef (diff)
downloadlinux-d94ba9e7d8d5c821d0442f13b30b0140c1109c38.tar.xz
Merge tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.8 kernel cycle. Nothing stands out as especially exiting: new drivers, new subdrivers, lots of cleanups and incremental features. Business as usual. New drivers: - New driver for Oxnas pin control and GPIO. This ARM-based chipset is used in a few storage (NAS) type devices. - New driver for the MAX77620/MAX20024 pin controller portions. - New driver for the Intel Merrifield pin controller. New subdrivers: - New subdriver for the Qualcomm MDM9615 - New subdriver for the STM32F746 MCU - New subdriver for the Broadcom NSP SoC. Cleanups: - Demodularization of bool compiled-in drivers. Apart from this there is just regular incremental improvements to a lot of drivers, especially Uniphier and PFC" * tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (131 commits) pinctrl: fix pincontrol definition for marvell pinctrl: xway: fix typo Revert "pinctrl: amd: make it explicitly non-modular" pinctrl: iproc: Add NSP and Stingray GPIO support pinctrl: Update iProc GPIO DT bindings pinctrl: bcm: add OF dependencies pinctrl: ns2: remove redundant dev_err call in ns2_pinmux_probe() pinctrl: Add STM32F746 MCU support pinctrl: intel: Protect set wake flow by spin lock pinctrl: nsp: remove redundant dev_err call in nsp_pinmux_probe() pinctrl: uniphier: add Ethernet pin-mux settings sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the code pinctrl: ns2: fix return value check in ns2_pinmux_probe() pinctrl: qcom: update DT bindings with ebi2 groups pinctrl: qcom: establish proper EBI2 pin groups pinctrl: imx21: Remove the MODULE_DEVICE_TABLE() macro Documentation: dt: Add new compatible to STM32 pinctrl driver bindings includes: dt-bindings: Add STM32F746 pinctrl DT bindings pinctrl: sunxi: fix nand0 function name for sun8i pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11 ...
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/Kconfig26
-rw-r--r--drivers/pinctrl/Makefile4
-rw-r--r--drivers/pinctrl/bcm/Kconfig15
-rw-r--r--drivers/pinctrl/bcm/Makefile1
-rw-r--r--drivers/pinctrl/bcm/pinctrl-iproc-gpio.c118
-rw-r--r--drivers/pinctrl/bcm/pinctrl-ns2-mux.c12
-rw-r--r--drivers/pinctrl/bcm/pinctrl-nsp-gpio.c6
-rw-r--r--drivers/pinctrl/bcm/pinctrl-nsp-mux.c642
-rw-r--r--drivers/pinctrl/core.c25
-rw-r--r--drivers/pinctrl/core.h2
-rw-r--r--drivers/pinctrl/devicetree.c7
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx.c29
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx1-core.c3
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx1.c9
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx21.c9
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx23.c17
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx25.c10
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx27.c10
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx28.c17
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx35.c10
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx50.c9
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx51.c10
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx53.c10
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6dl.c14
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6q.c10
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6sl.c15
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6sx.c14
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx6ul.c14
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx7d.c14
-rw-r--r--drivers/pinctrl/freescale/pinctrl-mxs.c12
-rw-r--r--drivers/pinctrl/freescale/pinctrl-mxs.h1
-rw-r--r--drivers/pinctrl/freescale/pinctrl-vf610.c10
-rw-r--r--drivers/pinctrl/intel/Kconfig11
-rw-r--r--drivers/pinctrl/intel/Makefile1
-rw-r--r--drivers/pinctrl/intel/pinctrl-baytrail.c25
-rw-r--r--drivers/pinctrl/intel/pinctrl-broxton.c43
-rw-r--r--drivers/pinctrl/intel/pinctrl-cherryview.c155
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.c52
-rw-r--r--drivers/pinctrl/intel/pinctrl-merrifield.c911
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common.c4
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson-gxbb.c163
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-kirkwood.c85
-rw-r--r--drivers/pinctrl/nomadik/pinctrl-nomadik.c96
-rw-r--r--drivers/pinctrl/pinconf-generic.c22
-rw-r--r--drivers/pinctrl/pinconf.c8
-rw-r--r--drivers/pinctrl/pinctrl-at91-pio4.c26
-rw-r--r--drivers/pinctrl/pinctrl-at91.c13
-rw-r--r--drivers/pinctrl/pinctrl-digicolor.c16
-rw-r--r--drivers/pinctrl/pinctrl-lpc18xx.c20
-rw-r--r--drivers/pinctrl/pinctrl-max77620.c673
-rw-r--r--drivers/pinctrl/pinctrl-oxnas.c846
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.c4
-rw-r--r--drivers/pinctrl/pinctrl-st.c2
-rw-r--r--drivers/pinctrl/pinctrl-u300.c2
-rw-r--r--drivers/pinctrl/pinctrl-xway.c72
-rw-r--r--drivers/pinctrl/pinctrl-zynq.c13
-rw-r--r--drivers/pinctrl/pinmux.c16
-rw-r--r--drivers/pinctrl/qcom/Kconfig8
-rw-r--r--drivers/pinctrl/qcom/Makefile1
-rw-r--r--drivers/pinctrl/qcom/pinctrl-mdm9615.c483
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.c6
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8660.c114
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm8x74.c43
-rw-r--r--drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c1
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos5440.c1
-rw-r--r--drivers/pinctrl/samsung/pinctrl-samsung.c1
-rw-r--r--drivers/pinctrl/sh-pfc/core.c10
-rw-r--r--drivers/pinctrl/sh-pfc/core.h58
-rw-r--r--drivers/pinctrl/sh-pfc/gpio.c13
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a73a4.c1
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c1
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7778.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c59
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c1
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7795.c327
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7757.c1
-rw-r--r--drivers/pinctrl/sh-pfc/pinctrl.c46
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h55
-rw-r--r--drivers/pinctrl/sirf/pinctrl-atlas7.c4
-rw-r--r--drivers/pinctrl/stm32/Kconfig6
-rw-r--r--drivers/pinctrl/stm32/Makefile1
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32.c31
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32f746.c1681
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c6
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c6
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c6
-rw-r--r--drivers/pinctrl/tegra/pinctrl-tegra.c8
-rw-r--r--drivers/pinctrl/tegra/pinctrl-tegra.h6
-rw-r--r--drivers/pinctrl/tegra/pinctrl-tegra114.c4
-rw-r--r--drivers/pinctrl/tegra/pinctrl-tegra124.c4
-rw-r--r--drivers/pinctrl/tegra/pinctrl-tegra20.c6
-rw-r--r--drivers/pinctrl/tegra/pinctrl-tegra210.c4
-rw-r--r--drivers/pinctrl/tegra/pinctrl-tegra30.c4
-rw-r--r--drivers/pinctrl/uniphier/Kconfig20
-rw-r--r--drivers/pinctrl/uniphier/Makefile2
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-core.c298
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c952
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c1050
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c494
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c609
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c819
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c653
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c603
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c455
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier.h59
105 files changed, 10726 insertions, 2681 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index fb8200b8e8ec..b3fe1d339632 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -35,7 +35,7 @@ config PINCTRL_ADI2
machine and arch are selected to build.
config PINCTRL_AS3722
- bool "Pinctrl and GPIO driver for ams AS3722 PMIC"
+ tristate "Pinctrl and GPIO driver for ams AS3722 PMIC"
depends on MFD_AS3722 && GPIOLIB
select PINMUX
select GENERIC_PINCONF
@@ -129,6 +129,17 @@ config PINCTRL_MESON
select OF_GPIO
select REGMAP_MMIO
+config PINCTRL_OXNAS
+ bool
+ depends on OF
+ select PINMUX
+ select PINCONF
+ select GENERIC_PINCONF
+ select GPIOLIB
+ select OF_GPIO
+ select GPIOLIB_IRQCHIP
+ select MFD_SYSCON
+
config PINCTRL_ROCKCHIP
bool
select PINMUX
@@ -196,8 +207,19 @@ config PINCTRL_COH901
COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
ports of 8 GPIO pins each.
+config PINCTRL_MAX77620
+ tristate "MAX77620/MAX20024 Pincontrol support"
+ depends on MFD_MAX77620
+ select PINMUX
+ select GENERIC_PINCONF
+ help
+ Say Yes here to enable Pin control support for Maxim PMIC MAX77620.
+ This PMIC has 8 GPIO pins that work as GPIO as well as special
+ function in alternate mode. This driver also configure push-pull,
+ open drain, FPS slots etc.
+
config PINCTRL_PALMAS
- bool "Pinctrl driver for the PALMAS Series MFD devices"
+ tristate "Pinctrl driver for the PALMAS Series MFD devices"
depends on OF && MFD_PALMAS
select PINMUX
select GENERIC_PINCONF
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 42a5c1dddfef..8ebd7b8e1621 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,7 +16,9 @@ obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
+obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o
obj-$(CONFIG_PINCTRL_MESON) += meson/
+obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
@@ -35,7 +37,7 @@ obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
-obj-$(CONFIG_ARCH_BCM) += bcm/
+obj-y += bcm/
obj-$(CONFIG_PINCTRL_BERLIN) += berlin/
obj-y += freescale/
obj-$(CONFIG_X86) += intel/
diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig
index c356223e1c9c..63246770bd74 100644
--- a/drivers/pinctrl/bcm/Kconfig
+++ b/drivers/pinctrl/bcm/Kconfig
@@ -60,6 +60,7 @@ config PINCTRL_IPROC_GPIO
config PINCTRL_CYGNUS_MUX
bool "Broadcom Cygnus IOMUX driver"
depends on (ARCH_BCM_CYGNUS || COMPILE_TEST)
+ depends on OF
select PINMUX
select GENERIC_PINCONF
default ARCH_BCM_CYGNUS
@@ -99,3 +100,17 @@ config PINCTRL_NS2_MUX
The Broadcom Northstar2 IOMUX driver supports group based IOMUX
configuration.
+
+config PINCTRL_NSP_MUX
+ bool "Broadcom NSP IOMUX driver"
+ depends on (ARCH_BCM_NSP || COMPILE_TEST)
+ depends on OF
+ select PINMUX
+ select GENERIC_PINCONF
+ default ARCH_BCM_NSP
+ help
+ Say yes here to enable the Broadcom NSP SOC IOMUX driver.
+
+ The Broadcom Northstar Plus IOMUX driver supports pin based IOMUX
+ configuration, with certain individual pins can be overridden
+ to GPIO function.
diff --git a/drivers/pinctrl/bcm/Makefile b/drivers/pinctrl/bcm/Makefile
index 3861a1c1f8ff..2a65111f3c70 100644
--- a/drivers/pinctrl/bcm/Makefile
+++ b/drivers/pinctrl/bcm/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o
obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o
obj-$(CONFIG_PINCTRL_NSP_GPIO) += pinctrl-nsp-gpio.o
obj-$(CONFIG_PINCTRL_NS2_MUX) += pinctrl-ns2-mux.o
+obj-$(CONFIG_PINCTRL_NSP_MUX) += pinctrl-nsp-mux.o
diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
index 3670f5ea7a12..7f7700716398 100644
--- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
+++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
@@ -66,6 +66,14 @@
#define GPIO_DRV_STRENGTH_BITS 3
#define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
+enum iproc_pinconf_param {
+ IPROC_PINCONF_DRIVE_STRENGTH = 0,
+ IPROC_PINCONF_BIAS_DISABLE,
+ IPROC_PINCONF_BIAS_PULL_UP,
+ IPROC_PINCONF_BIAS_PULL_DOWN,
+ IPROC_PINCON_MAX,
+};
+
/*
* Iproc GPIO core
*
@@ -78,6 +86,10 @@
* @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
* @pinmux_is_supported: flag to indicate this GPIO controller contains pins
* that can be individually muxed to GPIO
+ * @pinconf_disable: contains a list of PINCONF parameters that need to be
+ * disabled
+ * @nr_pinconf_disable: total number of PINCONF parameters that need to be
+ * disabled
* @pctl: pointer to pinctrl_dev
* @pctldesc: pinctrl descriptor
*/
@@ -94,6 +106,9 @@ struct iproc_gpio {
bool pinmux_is_supported;
+ enum pin_config_param *pinconf_disable;
+ unsigned int nr_pinconf_disable;
+
struct pinctrl_dev *pctl;
struct pinctrl_desc pctldesc;
};
@@ -360,6 +375,65 @@ static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio)
return !!(readl(chip->base + offset) & BIT(shift));
}
+/*
+ * Mapping of the iProc PINCONF parameters to the generic pin configuration
+ * parameters
+ */
+static const enum pin_config_param iproc_pinconf_disable_map[] = {
+ [IPROC_PINCONF_DRIVE_STRENGTH] = PIN_CONFIG_DRIVE_STRENGTH,
+ [IPROC_PINCONF_BIAS_DISABLE] = PIN_CONFIG_BIAS_DISABLE,
+ [IPROC_PINCONF_BIAS_PULL_UP] = PIN_CONFIG_BIAS_PULL_UP,
+ [IPROC_PINCONF_BIAS_PULL_DOWN] = PIN_CONFIG_BIAS_PULL_DOWN,
+};
+
+static bool iproc_pinconf_param_is_disabled(struct iproc_gpio *chip,
+ enum pin_config_param param)
+{
+ unsigned int i;
+
+ if (!chip->nr_pinconf_disable)
+ return false;
+
+ for (i = 0; i < chip->nr_pinconf_disable; i++)
+ if (chip->pinconf_disable[i] == param)
+ return true;
+
+ return false;
+}
+
+static int iproc_pinconf_disable_map_create(struct iproc_gpio *chip,
+ unsigned long disable_mask)
+{
+ unsigned int map_size = ARRAY_SIZE(iproc_pinconf_disable_map);
+ unsigned int bit, nbits = 0;
+
+ /* figure out total number of PINCONF parameters to disable */
+ for_each_set_bit(bit, &disable_mask, map_size)
+ nbits++;
+
+ if (!nbits)
+ return 0;
+
+ /*
+ * Allocate an array to store PINCONF parameters that need to be
+ * disabled
+ */
+ chip->pinconf_disable = devm_kcalloc(chip->dev, nbits,
+ sizeof(*chip->pinconf_disable),
+ GFP_KERNEL);
+ if (!chip->pinconf_disable)
+ return -ENOMEM;
+
+ chip->nr_pinconf_disable = nbits;
+
+ /* now store these parameters */
+ nbits = 0;
+ for_each_set_bit(bit, &disable_mask, map_size)
+ chip->pinconf_disable[nbits++] = iproc_pinconf_disable_map[bit];
+
+ return 0;
+}
+
static int iproc_get_groups_count(struct pinctrl_dev *pctldev)
{
return 1;
@@ -500,6 +574,9 @@ static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
bool disable, pull_up;
int ret;
+ if (iproc_pinconf_param_is_disabled(chip, param))
+ return -ENOTSUPP;
+
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
@@ -548,6 +625,10 @@ static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
+
+ if (iproc_pinconf_param_is_disabled(chip, param))
+ return -ENOTSUPP;
+
arg = pinconf_to_config_argument(configs[i]);
switch (param) {
@@ -633,11 +714,13 @@ static int iproc_gpio_register_pinconf(struct iproc_gpio *chip)
}
static const struct of_device_id iproc_gpio_of_match[] = {
+ { .compatible = "brcm,iproc-gpio" },
{ .compatible = "brcm,cygnus-ccm-gpio" },
{ .compatible = "brcm,cygnus-asiu-gpio" },
{ .compatible = "brcm,cygnus-crmu-gpio" },
- { .compatible = "brcm,iproc-gpio" },
- { }
+ { .compatible = "brcm,iproc-nsp-gpio" },
+ { .compatible = "brcm,iproc-stingray-gpio" },
+ { /* sentinel */ }
};
static int iproc_gpio_probe(struct platform_device *pdev)
@@ -646,8 +729,17 @@ static int iproc_gpio_probe(struct platform_device *pdev)
struct resource *res;
struct iproc_gpio *chip;
struct gpio_chip *gc;
- u32 ngpios;
+ u32 ngpios, pinconf_disable_mask = 0;
int irq, ret;
+ bool no_pinconf = false;
+
+ /* NSP does not support drive strength config */
+ if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio"))
+ pinconf_disable_mask = BIT(IPROC_PINCONF_DRIVE_STRENGTH);
+ /* Stingray does not support pinconf in this controller */
+ else if (of_device_is_compatible(dev->of_node,
+ "brcm,iproc-stingray-gpio"))
+ no_pinconf = true;
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
if (!chip)
@@ -702,10 +794,22 @@ static int iproc_gpio_probe(struct platform_device *pdev)
return ret;
}
- ret = iproc_gpio_register_pinconf(chip);
- if (ret) {
- dev_err(dev, "unable to register pinconf\n");
- goto err_rm_gpiochip;
+ if (!no_pinconf) {
+ ret = iproc_gpio_register_pinconf(chip);
+ if (ret) {
+ dev_err(dev, "unable to register pinconf\n");
+ goto err_rm_gpiochip;
+ }
+
+ if (pinconf_disable_mask) {
+ ret = iproc_pinconf_disable_map_create(chip,
+ pinconf_disable_mask);
+ if (ret) {
+ dev_err(dev,
+ "unable to create pinconf disable map\n");
+ goto err_rm_gpiochip;
+ }
+ }
}
/* optional GPIO interrupt support */
diff --git a/drivers/pinctrl/bcm/pinctrl-ns2-mux.c b/drivers/pinctrl/bcm/pinctrl-ns2-mux.c
index 3fefd14acc3e..ca817896ed24 100644
--- a/drivers/pinctrl/bcm/pinctrl-ns2-mux.c
+++ b/drivers/pinctrl/bcm/pinctrl-ns2-mux.c
@@ -1044,10 +1044,8 @@ static int ns2_pinmux_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pinctrl->base0 = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(pinctrl->base0)) {
- dev_err(&pdev->dev, "unable to map I/O space\n");
+ if (IS_ERR(pinctrl->base0))
return PTR_ERR(pinctrl->base0);
- }
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
pinctrl->base1 = devm_ioremap_nocache(&pdev->dev, res->start,
@@ -1059,10 +1057,8 @@ static int ns2_pinmux_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
pinctrl->pinconf_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(pinctrl->pinconf_base)) {
- dev_err(&pdev->dev, "unable to map I/O space\n");
+ if (IS_ERR(pinctrl->pinconf_base))
return PTR_ERR(pinctrl->pinconf_base);
- }
ret = ns2_mux_log_init(pinctrl);
if (ret) {
@@ -1089,9 +1085,9 @@ static int ns2_pinmux_probe(struct platform_device *pdev)
pinctrl->pctl = pinctrl_register(&ns2_pinctrl_desc, &pdev->dev,
pinctrl);
- if (!pinctrl->pctl) {
+ if (IS_ERR(pinctrl->pctl)) {
dev_err(&pdev->dev, "unable to register IOMUX pinctrl\n");
- return -EINVAL;
+ return PTR_ERR(pinctrl->pctl);
}
return 0;
diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
index a8b37a9a8230..35783db1c10b 100644
--- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
+++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
@@ -458,13 +458,15 @@ static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
return 0;
}
-int nsp_pin_config_group_get(struct pinctrl_dev *pctldev, unsigned selector,
+static int nsp_pin_config_group_get(struct pinctrl_dev *pctldev,
+ unsigned selector,
unsigned long *config)
{
return 0;
}
-int nsp_pin_config_group_set(struct pinctrl_dev *pctldev, unsigned selector,
+static int nsp_pin_config_group_set(struct pinctrl_dev *pctldev,
+ unsigned selector,
unsigned long *configs, unsigned num_configs)
{
return 0;
diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-mux.c b/drivers/pinctrl/bcm/pinctrl-nsp-mux.c
new file mode 100644
index 000000000000..4149db309c8b
--- /dev/null
+++ b/drivers/pinctrl/bcm/pinctrl-nsp-mux.c
@@ -0,0 +1,642 @@
+/* Copyright (C) 2015 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * This file contains the Northstar plus (NSP) IOMUX driver that supports
+ * group based PINMUX configuration. The Northstar plus IOMUX controller
+ * allows pins to be individually muxed to GPIO function. The NAND and MMC is
+ * a group based selection. The gpio_a 8 - 11 are muxed with gpio_b and pwm.
+ * To select PWM, one need to enable the corresponding gpio_b as well.
+ *
+ * gpio_a (8 - 11)
+ * +----------
+ * |
+ * gpio_a (8-11) | gpio_b (0 - 3)
+ * ------------------------+-------+----------
+ * |
+ * | pwm (0 - 3)
+ * +----------
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+
+#define NSP_MUX_BASE0 0x00
+#define NSP_MUX_BASE1 0x01
+#define NSP_MUX_BASE2 0x02
+/*
+ * nsp IOMUX register description
+ *
+ * @base: base 0 or base 1
+ * @shift: bit shift for mux configuration of a group
+ * @mask: bit mask of the function
+ * @alt: alternate function to set to
+ */
+struct nsp_mux {
+ unsigned int base;
+ unsigned int shift;
+ unsigned int mask;
+ unsigned int alt;
+};
+
+/*
+ * Keep track of nsp IOMUX configuration and prevent double configuration
+ *
+ * @nsp_mux: nsp IOMUX register description
+ * @is_configured: flag to indicate whether a mux setting has already been
+ * configured
+ */
+struct nsp_mux_log {
+ struct nsp_mux mux;
+ bool is_configured;
+};
+
+/*
+ * Group based IOMUX configuration
+ *
+ * @name: name of the group
+ * @pins: array of pins used by this group
+ * @num_pins: total number of pins used by this group
+ * @mux: nsp group based IOMUX configuration
+ */
+struct nsp_pin_group {
+ const char *name;
+ const unsigned int *pins;
+ const unsigned int num_pins;
+ const struct nsp_mux mux;
+};
+
+/*
+ * nsp mux function and supported pin groups
+ *
+ * @name: name of the function
+ * @groups: array of groups that can be supported by this function
+ * @num_groups: total number of groups that can be supported by this function
+ */
+struct nsp_pin_function {
+ const char *name;
+ const char * const *groups;
+ const unsigned int num_groups;
+};
+
+/*
+ * nsp IOMUX pinctrl core
+ *
+ * @pctl: pointer to pinctrl_dev
+ * @dev: pointer to device
+ * @base0: first mux register
+ * @base1: second mux register
+ * @base2: third mux register
+ * @groups: pointer to array of groups
+ * @num_groups: total number of groups
+ * @functions: pointer to array of functions
+ * @num_functions: total number of functions
+ * @mux_log: pointer to the array of mux logs
+ * @lock: lock to protect register access
+ */
+struct nsp_pinctrl {
+ struct pinctrl_dev *pctl;
+ struct device *dev;
+ void __iomem *base0;
+ void __iomem *base1;
+ void __iomem *base2;
+ const struct nsp_pin_group *groups;
+ unsigned int num_groups;
+ const struct nsp_pin_function *functions;
+ unsigned int num_functions;
+ struct nsp_mux_log *mux_log;
+ spinlock_t lock;
+};
+
+/*
+ * Description of a pin in nsp
+ *
+ * @pin: pin number
+ * @name: pin name
+ * @gpio_select: reg data to select GPIO
+ */
+struct nsp_pin {
+ unsigned int pin;
+ char *name;
+ unsigned int gpio_select;
+};
+
+#define NSP_PIN_DESC(p, n, g) \
+{ \
+ .pin = p, \
+ .name = n, \
+ .gpio_select = g, \
+}
+
+/*
+ * List of muxable pins in nsp
+ */
+static struct nsp_pin nsp_pins[] = {
+ NSP_PIN_DESC(0, "spi_clk", 1),
+ NSP_PIN_DESC(1, "spi_ss", 1),
+ NSP_PIN_DESC(2, "spi_mosi", 1),
+ NSP_PIN_DESC(3, "spi_miso", 1),
+ NSP_PIN_DESC(4, "scl", 1),
+ NSP_PIN_DESC(5, "sda", 1),
+ NSP_PIN_DESC(6, "mdc", 1),
+ NSP_PIN_DESC(7, "mdio", 1),
+ NSP_PIN_DESC(8, "pwm0", 1),
+ NSP_PIN_DESC(9, "pwm1", 1),
+ NSP_PIN_DESC(10, "pwm2", 1),
+ NSP_PIN_DESC(11, "pwm3", 1),
+ NSP_PIN_DESC(12, "uart1_rx", 1),
+ NSP_PIN_DESC(13, "uart1_tx", 1),
+ NSP_PIN_DESC(14, "uart1_cts", 1),
+ NSP_PIN_DESC(15, "uart1_rts", 1),
+ NSP_PIN_DESC(16, "uart2_rx", 1),
+ NSP_PIN_DESC(17, "uart2_tx", 1),
+ NSP_PIN_DESC(18, "synce", 0),
+ NSP_PIN_DESC(19, "sata0_led", 0),
+ NSP_PIN_DESC(20, "sata1_led", 0),
+ NSP_PIN_DESC(21, "xtal_out", 1),
+ NSP_PIN_DESC(22, "sdio_pwr", 1),
+ NSP_PIN_DESC(23, "sdio_en_1p8v", 1),
+ NSP_PIN_DESC(24, "gpio_24", 1),
+ NSP_PIN_DESC(25, "gpio_25", 1),
+ NSP_PIN_DESC(26, "p5_led0", 0),
+ NSP_PIN_DESC(27, "p5_led1", 0),
+ NSP_PIN_DESC(28, "gpio_28", 1),
+ NSP_PIN_DESC(29, "gpio_29", 1),
+ NSP_PIN_DESC(30, "gpio_30", 1),
+ NSP_PIN_DESC(31, "gpio_31", 1),
+ NSP_PIN_DESC(32, "nand_ale", 0),
+ NSP_PIN_DESC(33, "nand_ce0", 0),
+ NSP_PIN_DESC(34, "nand_r/b", 0),
+ NSP_PIN_DESC(35, "nand_dq0", 0),
+ NSP_PIN_DESC(36, "nand_dq1", 0),
+ NSP_PIN_DESC(37, "nand_dq2", 0),
+ NSP_PIN_DESC(38, "nand_dq3", 0),
+ NSP_PIN_DESC(39, "nand_dq4", 0),
+ NSP_PIN_DESC(40, "nand_dq5", 0),
+ NSP_PIN_DESC(41, "nand_dq6", 0),
+ NSP_PIN_DESC(42, "nand_dq7", 0),
+};
+
+/*
+ * List of groups of pins
+ */
+
+static const unsigned int spi_pins[] = {0, 1, 2, 3};
+static const unsigned int i2c_pins[] = {4, 5};
+static const unsigned int mdio_pins[] = {6, 7};
+static const unsigned int pwm0_pins[] = {8};
+static const unsigned int gpio_b_0_pins[] = {8};
+static const unsigned int pwm1_pins[] = {9};
+static const unsigned int gpio_b_1_pins[] = {9};
+static const unsigned int pwm2_pins[] = {10};
+static const unsigned int gpio_b_2_pins[] = {10};
+static const unsigned int pwm3_pins[] = {11};
+static const unsigned int gpio_b_3_pins[] = {11};
+static const unsigned int uart1_pins[] = {12, 13, 14, 15};
+static const unsigned int uart2_pins[] = {16, 17};
+static const unsigned int synce_pins[] = {18};
+static const unsigned int sata0_led_pins[] = {19};
+static const unsigned int sata1_led_pins[] = {20};
+static const unsigned int xtal_out_pins[] = {21};
+static const unsigned int sdio_pwr_pins[] = {22};
+static const unsigned int sdio_1p8v_pins[] = {23};
+static const unsigned int switch_p05_led0_pins[] = {26};
+static const unsigned int switch_p05_led1_pins[] = {27};
+static const unsigned int nand_pins[] = {32, 33, 34, 35, 36, 37, 38, 39,
+ 40, 41, 42};
+static const unsigned int emmc_pins[] = {32, 33, 34, 35, 36, 37, 38, 39,
+ 40, 41, 42};
+
+#define NSP_PIN_GROUP(group_name, ba, sh, ma, al) \
+{ \
+ .name = __stringify(group_name) "_grp", \
+ .pins = group_name ## _pins, \
+ .num_pins = ARRAY_SIZE(group_name ## _pins), \
+ .mux = { \
+ .base = ba, \
+ .shift = sh, \
+ .mask = ma, \
+ .alt = al, \
+ } \
+}
+
+/*
+ * List of nsp pin groups
+ */
+static const struct nsp_pin_group nsp_pin_groups[] = {
+ NSP_PIN_GROUP(spi, NSP_MUX_BASE0, 0, 0x0f, 0x00),
+ NSP_PIN_GROUP(i2c, NSP_MUX_BASE0, 3, 0x03, 0x00),
+ NSP_PIN_GROUP(mdio, NSP_MUX_BASE0, 5, 0x03, 0x00),
+ NSP_PIN_GROUP(gpio_b_0, NSP_MUX_BASE0, 7, 0x01, 0x00),
+ NSP_PIN_GROUP(pwm0, NSP_MUX_BASE1, 0, 0x01, 0x01),
+ NSP_PIN_GROUP(gpio_b_1, NSP_MUX_BASE0, 8, 0x01, 0x00),
+ NSP_PIN_GROUP(pwm1, NSP_MUX_BASE1, 1, 0x01, 0x01),
+ NSP_PIN_GROUP(gpio_b_2, NSP_MUX_BASE0, 9, 0x01, 0x00),
+ NSP_PIN_GROUP(pwm2, NSP_MUX_BASE1, 2, 0x01, 0x01),
+ NSP_PIN_GROUP(gpio_b_3, NSP_MUX_BASE0, 10, 0x01, 0x00),
+ NSP_PIN_GROUP(pwm3, NSP_MUX_BASE1, 3, 0x01, 0x01),
+ NSP_PIN_GROUP(uart1, NSP_MUX_BASE0, 11, 0x0f, 0x00),
+ NSP_PIN_GROUP(uart2, NSP_MUX_BASE0, 15, 0x03, 0x00),
+ NSP_PIN_GROUP(synce, NSP_MUX_BASE0, 17, 0x01, 0x01),
+ NSP_PIN_GROUP(sata0_led, NSP_MUX_BASE0, 18, 0x01, 0x01),
+ NSP_PIN_GROUP(sata1_led, NSP_MUX_BASE0, 19, 0x01, 0x01),
+ NSP_PIN_GROUP(xtal_out, NSP_MUX_BASE0, 20, 0x01, 0x00),
+ NSP_PIN_GROUP(sdio_pwr, NSP_MUX_BASE0, 21, 0x01, 0x00),
+ NSP_PIN_GROUP(sdio_1p8v, NSP_MUX_BASE0, 22, 0x01, 0x00),
+ NSP_PIN_GROUP(switch_p05_led0, NSP_MUX_BASE0, 26, 0x01, 0x01),
+ NSP_PIN_GROUP(switch_p05_led1, NSP_MUX_BASE0, 27, 0x01, 0x01),
+ NSP_PIN_GROUP(nand, NSP_MUX_BASE2, 0, 0x01, 0x00),
+ NSP_PIN_GROUP(emmc, NSP_MUX_BASE2, 0, 0x01, 0x01)
+};
+
+/*
+ * List of groups supported by functions
+ */
+
+static const char * const spi_grps[] = {"spi_grp"};
+static const char * const i2c_grps[] = {"i2c_grp"};
+static const char * const mdio_grps[] = {"mdio_grp"};
+static const char * const pwm_grps[] = {"pwm0_grp", "pwm1_grp", "pwm2_grp"
+ , "pwm3_grp"};
+static const char * const gpio_b_grps[] = {"gpio_b_0_grp", "gpio_b_1_grp",
+ "gpio_b_2_grp", "gpio_b_3_grp"};
+static const char * const uart1_grps[] = {"uart1_grp"};
+static const char * const uart2_grps[] = {"uart2_grp"};
+static const char * const synce_grps[] = {"synce_grp"};
+static const char * const sata_led_grps[] = {"sata0_led_grp", "sata1_led_grp"};
+static const char * const xtal_out_grps[] = {"xtal_out_grp"};
+static const char * const sdio_grps[] = {"sdio_pwr_grp", "sdio_1p8v_grp"};
+static const char * const switch_led_grps[] = {"switch_p05_led0_grp",
+ "switch_p05_led1_grp"};
+static const char * const nand_grps[] = {"nand_grp"};
+static const char * const emmc_grps[] = {"emmc_grp"};
+
+#define NSP_PIN_FUNCTION(func) \
+{ \
+ .name = #func, \
+ .groups = func ## _grps, \
+ .num_groups = ARRAY_SIZE(func ## _grps), \
+}
+
+/*
+ * List of supported functions in nsp
+ */
+static const struct nsp_pin_function nsp_pin_functions[] = {
+ NSP_PIN_FUNCTION(spi),
+ NSP_PIN_FUNCTION(i2c),
+ NSP_PIN_FUNCTION(mdio),
+ NSP_PIN_FUNCTION(pwm),
+ NSP_PIN_FUNCTION(gpio_b),
+ NSP_PIN_FUNCTION(uart1),
+ NSP_PIN_FUNCTION(uart2),
+ NSP_PIN_FUNCTION(synce),
+ NSP_PIN_FUNCTION(sata_led),
+ NSP_PIN_FUNCTION(xtal_out),
+ NSP_PIN_FUNCTION(sdio),
+ NSP_PIN_FUNCTION(switch_led),
+ NSP_PIN_FUNCTION(nand),
+ NSP_PIN_FUNCTION(emmc)
+};
+
+static int nsp_get_groups_count(struct pinctrl_dev *pctrl_dev)
+{
+ struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+
+ return pinctrl->num_groups;
+}
+
+static const char *nsp_get_group_name(struct pinctrl_dev *pctrl_dev,
+ unsigned int selector)
+{
+ struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+
+ return pinctrl->groups[selector].name;
+}
+
+static int nsp_get_group_pins(struct pinctrl_dev *pctrl_dev,
+ unsigned int selector, const unsigned int **pins,
+ unsigned int *num_pins)
+{
+ struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+
+ *pins = pinctrl->groups[selector].pins;
+ *num_pins = pinctrl->groups[selector].num_pins;
+
+ return 0;
+}
+
+static void nsp_pin_dbg_show(struct pinctrl_dev *pctrl_dev,
+ struct seq_file *s, unsigned int offset)
+{
+ seq_printf(s, " %s", dev_name(pctrl_dev->dev));
+}
+
+static struct pinctrl_ops nsp_pinctrl_ops = {
+ .get_groups_count = nsp_get_groups_count,
+ .get_group_name = nsp_get_group_name,
+ .get_group_pins = nsp_get_group_pins,
+ .pin_dbg_show = nsp_pin_dbg_show,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
+ .dt_free_map = pinctrl_utils_free_map,
+};
+
+static int nsp_get_functions_count(struct pinctrl_dev *pctrl_dev)
+{
+ struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+
+ return pinctrl->num_functions;
+}
+
+static const char *nsp_get_function_name(struct pinctrl_dev *pctrl_dev,
+ unsigned int selector)
+{
+ struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+
+ return pinctrl->functions[selector].name;
+}
+
+static int nsp_get_function_groups(struct pinctrl_dev *pctrl_dev,
+ unsigned int selector,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+
+ *groups = pinctrl->functions[selector].groups;
+ *num_groups = pinctrl->functions[selector].num_groups;
+
+ return 0;
+}
+
+static int nsp_pinmux_set(struct nsp_pinctrl *pinctrl,
+ const struct nsp_pin_function *func,
+ const struct nsp_pin_group *grp,
+ struct nsp_mux_log *mux_log)
+{
+ const struct nsp_mux *mux = &grp->mux;
+ int i;
+ u32 val, mask;
+ unsigned long flags;
+ void __iomem *base_address;
+
+ for (i = 0; i < pinctrl->num_groups; i++) {
+ if ((mux->shift != mux_log[i].mux.shift) ||
+ (mux->base != mux_log[i].mux.base))
+ continue;
+
+ /* if this is a new configuration, just do it! */
+ if (!mux_log[i].is_configured)
+ break;
+
+ /*
+ * IOMUX has been configured previously and one is trying to
+ * configure it to a different function
+ */
+ if (mux_log[i].mux.alt != mux->alt) {
+ dev_err(pinctrl->dev,
+ "double configuration error detected!\n");
+ dev_err(pinctrl->dev, "func:%s grp:%s\n",
+ func->name, grp->name);
+ return -EINVAL;
+ }
+
+ return 0;
+ }
+ if (i == pinctrl->num_groups)
+ return -EINVAL;
+
+ mask = mux->mask;
+ mux_log[i].mux.alt = mux->alt;
+ mux_log[i].is_configured = true;
+
+ switch (mux->base) {
+ case NSP_MUX_BASE0:
+ base_address = pinctrl->base0;
+ break;
+
+ case NSP_MUX_BASE1:
+ base_address = pinctrl->base1;
+ break;
+
+ case NSP_MUX_BASE2:
+ base_address = pinctrl->base2;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&pinctrl->lock, flags);
+ val = readl(base_address);
+ val &= ~(mask << grp->mux.shift);
+ val |= grp->mux.alt << grp->mux.shift;
+ writel(val, base_address);
+ spin_unlock_irqrestore(&pinctrl->lock, flags);
+
+ return 0;
+}
+
+static int nsp_pinmux_enable(struct pinctrl_dev *pctrl_dev,
+ unsigned int func_select, unsigned int grp_select)
+{
+ struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+ const struct nsp_pin_function *func;
+ const struct nsp_pin_group *grp;
+
+ if (grp_select > pinctrl->num_groups ||
+ func_select > pinctrl->num_functions)
+ return -EINVAL;
+
+ func = &pinctrl->functions[func_select];
+ grp = &pinctrl->groups[grp_select];
+
+ dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",
+ func_select, func->name, grp_select, grp->name);
+
+ dev_dbg(pctrl_dev->dev, "shift:%u alt:%u\n", grp->mux.shift,
+ grp->mux.alt);
+
+ return nsp_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
+}
+
+
+static int nsp_gpio_request_enable(struct pinctrl_dev *pctrl_dev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin)
+{
+ struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+ u32 *gpio_select = pctrl_dev->desc->pins[pin].drv_data;
+ u32 val;
+ unsigned long flags;
+
+ spin_lock_irqsave(&pinctrl->lock, flags);
+ val = readl(pinctrl->base0);
+ if ((val & BIT(pin)) != (*gpio_select << pin)) {
+ val &= ~BIT(pin);
+ val |= *gpio_select << pin;
+ writel(val, pinctrl->base0);
+ }
+ spin_unlock_irqrestore(&pinctrl->lock, flags);
+
+ return 0;
+}
+
+static void nsp_gpio_disable_free(struct pinctrl_dev *pctrl_dev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin)
+{
+ struct nsp_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+ u32 *gpio_select = pctrl_dev->desc->pins[pin].drv_data;
+ u32 val;
+ unsigned long flags;
+
+ spin_lock_irqsave(&pinctrl->lock, flags);
+ val = readl(pinctrl->base0);
+ if ((val & (1 << pin)) == (*gpio_select << pin)) {
+ val &= ~(1 << pin);
+ if (!(*gpio_select))
+ val |= (1 << pin);
+ writel(val, pinctrl->base0);
+ }
+ spin_unlock_irqrestore(&pinctrl->lock, flags);
+}
+
+static struct pinmux_ops nsp_pinmux_ops = {
+ .get_functions_count = nsp_get_functions_count,
+ .get_function_name = nsp_get_function_name,
+ .get_function_groups = nsp_get_function_groups,
+ .set_mux = nsp_pinmux_enable,
+ .gpio_request_enable = nsp_gpio_request_enable,
+ .gpio_disable_free = nsp_gpio_disable_free,
+};
+
+static struct pinctrl_desc nsp_pinctrl_desc = {
+ .name = "nsp-pinmux",
+ .pctlops = &nsp_pinctrl_ops,
+ .pmxops = &nsp_pinmux_ops,
+};
+
+static int nsp_mux_log_init(struct nsp_pinctrl *pinctrl)
+{
+ struct nsp_mux_log *log;
+ unsigned int i;
+ u32 no_of_groups = ARRAY_SIZE(nsp_pin_groups);
+
+ pinctrl->mux_log = devm_kcalloc(pinctrl->dev, no_of_groups,
+ sizeof(struct nsp_mux_log),
+ GFP_KERNEL);
+ if (!pinctrl->mux_log)
+ return -ENOMEM;
+
+ for (i = 0; i < no_of_groups; i++) {
+ log = &pinctrl->mux_log[i];
+ log->mux.base = nsp_pin_groups[i].mux.base;
+ log->mux.shift = nsp_pin_groups[i].mux.shift;
+ log->mux.alt = 0;
+ log->is_configured = false;
+ }
+
+ return 0;
+}
+
+static int nsp_pinmux_probe(struct platform_device *pdev)
+{
+ struct nsp_pinctrl *pinctrl;
+ struct resource *res;
+ int i, ret;
+ struct pinctrl_pin_desc *pins;
+ unsigned int num_pins = ARRAY_SIZE(nsp_pins);
+
+ pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
+ if (!pinctrl)
+ return -ENOMEM;
+ pinctrl->dev = &pdev->dev;
+ platform_set_drvdata(pdev, pinctrl);
+ spin_lock_init(&pinctrl->lock);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pinctrl->base0 = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(pinctrl->base0))
+ return PTR_ERR(pinctrl->base0);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ pinctrl->base1 = devm_ioremap_nocache(&pdev->dev, res->start,
+ resource_size(res));
+ if (!pinctrl->base1) {
+ dev_err(&pdev->dev, "unable to map I/O space\n");
+ return -ENOMEM;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ pinctrl->base2 = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(pinctrl->base2))
+ return PTR_ERR(pinctrl->base2);
+
+ ret = nsp_mux_log_init(pinctrl);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to initialize IOMUX log\n");
+ return ret;
+ }
+
+ pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
+ if (!pins)
+ return -ENOMEM;
+
+ for (i = 0; i < num_pins; i++) {
+ pins[i].number = nsp_pins[i].pin;
+ pins[i].name = nsp_pins[i].name;
+ pins[i].drv_data = &nsp_pins[i].gpio_select;
+ }
+
+ pinctrl->groups = nsp_pin_groups;
+ pinctrl->num_groups = ARRAY_SIZE(nsp_pin_groups);
+ pinctrl->functions = nsp_pin_functions;
+ pinctrl->num_functions = ARRAY_SIZE(nsp_pin_functions);
+ nsp_pinctrl_desc.pins = pins;
+ nsp_pinctrl_desc.npins = num_pins;
+
+ pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &nsp_pinctrl_desc,
+ pinctrl);
+ if (IS_ERR(pinctrl->pctl)) {
+ dev_err(&pdev->dev, "unable to register nsp IOMUX pinctrl\n");
+ return PTR_ERR(pinctrl->pctl);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id nsp_pinmux_of_match[] = {
+ { .compatible = "brcm,nsp-pinmux" },
+ { }
+};
+
+static struct platform_driver nsp_pinmux_driver = {
+ .driver = {
+ .name = "nsp-pinmux",
+ .of_match_table = nsp_pinmux_of_match,
+ },
+ .probe = nsp_pinmux_probe,
+};
+
+static int __init nsp_pinmux_init(void)
+{
+ return platform_driver_register(&nsp_pinmux_driver);
+}
+arch_initcall(nsp_pinmux_init);
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 98d2a1bb44cb..fb38e208f32d 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -225,13 +225,14 @@ static void pinctrl_free_pindescs(struct pinctrl_dev *pctldev,
}
static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev,
- unsigned number, const char *name)
+ const struct pinctrl_pin_desc *pin)
{
struct pin_desc *pindesc;
- pindesc = pin_desc_get(pctldev, number);
+ pindesc = pin_desc_get(pctldev, pin->number);
if (pindesc != NULL) {
- dev_err(pctldev->dev, "pin %d already registered\n", number);
+ dev_err(pctldev->dev, "pin %d already registered\n",
+ pin->number);
return -EINVAL;
}
@@ -245,10 +246,10 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev,
pindesc->pctldev = pctldev;
/* Copy basic pin info */
- if (name) {
- pindesc->name = name;
+ if (pin->name) {
+ pindesc->name = pin->name;
} else {
- pindesc->name = kasprintf(GFP_KERNEL, "PIN%u", number);
+ pindesc->name = kasprintf(GFP_KERNEL, "PIN%u", pin->number);
if (pindesc->name == NULL) {
kfree(pindesc);
return -ENOMEM;
@@ -256,9 +257,11 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev,
pindesc->dynamic_name = true;
}
- radix_tree_insert(&pctldev->pin_desc_tree, number, pindesc);
+ pindesc->drv_data = pin->drv_data;
+
+ radix_tree_insert(&pctldev->pin_desc_tree, pin->number, pindesc);
pr_debug("registered pin %d (%s) on %s\n",
- number, pindesc->name, pctldev->desc->name);
+ pin->number, pindesc->name, pctldev->desc->name);
return 0;
}
@@ -270,8 +273,7 @@ static int pinctrl_register_pins(struct pinctrl_dev *pctldev,
int ret = 0;
for (i = 0; i < num_descs; i++) {
- ret = pinctrl_register_one_pin(pctldev,
- pins[i].number, pins[i].name);
+ ret = pinctrl_register_one_pin(pctldev, &pins[i]);
if (ret)
return ret;
}
@@ -1367,8 +1369,7 @@ static int pinctrl_pins_show(struct seq_file *s, void *what)
if (desc == NULL)
continue;
- seq_printf(s, "pin %d (%s) ", pin,
- desc->name ? desc->name : "unnamed");
+ seq_printf(s, "pin %d (%s) ", pin, desc->name);
/* Driver-specific info per pin */
if (ops->pin_dbg_show)
diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index ca08723b9ee1..747c423c11f3 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -134,6 +134,7 @@ struct pinctrl_setting {
* @name: a name for the pin, e.g. the name of the pin/pad/finger on a
* datasheet or such
* @dynamic_name: if the name of this pin was dynamically allocated
+ * @drv_data: driver-defined per-pin data. pinctrl core does not touch this
* @mux_usecount: If zero, the pin is not claimed, and @owner should be NULL.
* If non-zero, this pin is claimed by @owner. This field is an integer
* rather than a boolean, since pinctrl_get() might process multiple
@@ -148,6 +149,7 @@ struct pin_desc {
struct pinctrl_dev *pctldev;
const char *name;
bool dynamic_name;
+ void *drv_data;
/* These fields only added when supporting pinmux drivers */
#ifdef CONFIG_PINMUX
unsigned mux_usecount;
diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
index fe04e748dfe4..54dad89fc9bf 100644
--- a/drivers/pinctrl/devicetree.c
+++ b/drivers/pinctrl/devicetree.c
@@ -195,8 +195,13 @@ int pinctrl_dt_to_map(struct pinctrl *p)
propname = kasprintf(GFP_KERNEL, "pinctrl-%d", state);
prop = of_find_property(np, propname, &size);
kfree(propname);
- if (!prop)
+ if (!prop) {
+ if (state == 0) {
+ of_node_put(np);
+ return -ENODEV;
+ }
break;
+ }
list = prop->value;
size /= sizeof(*list);
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index eccb47480e1d..71391757938b 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -16,7 +16,6 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
@@ -46,7 +45,7 @@ struct imx_pinctrl {
const struct imx_pinctrl_soc_info *info;
};
-static const inline struct imx_pin_group *imx_pinctrl_find_group_by_name(
+static inline const struct imx_pin_group *imx_pinctrl_find_group_by_name(
const struct imx_pinctrl_soc_info *info,
const char *name)
{
@@ -513,13 +512,6 @@ static const struct pinconf_ops imx_pinconf_ops = {
.pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
};
-static struct pinctrl_desc imx_pinctrl_desc = {
- .pctlops = &imx_pctrl_ops,
- .pmxops = &imx_pmx_ops,
- .confops = &imx_pinconf_ops,
- .owner = THIS_MODULE,
-};
-
/*
* Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
* 1 u32 CONFIG, so 24 types in total for each pin.
@@ -722,6 +714,7 @@ int imx_pinctrl_probe(struct platform_device *pdev,
{
struct regmap_config config = { .name = "gpr" };
struct device_node *dev_np = pdev->dev.of_node;
+ struct pinctrl_desc *imx_pinctrl_desc;
struct device_node *np;
struct imx_pinctrl *ipctl;
struct resource *res;
@@ -776,9 +769,18 @@ int imx_pinctrl_probe(struct platform_device *pdev,
}
}
- imx_pinctrl_desc.name = dev_name(&pdev->dev);
- imx_pinctrl_desc.pins = info->pins;
- imx_pinctrl_desc.npins = info->npins;
+ imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc),
+ GFP_KERNEL);
+ if (!imx_pinctrl_desc)
+ return -ENOMEM;
+
+ imx_pinctrl_desc->name = dev_name(&pdev->dev);
+ imx_pinctrl_desc->pins = info->pins;
+ imx_pinctrl_desc->npins = info->npins;
+ imx_pinctrl_desc->pctlops = &imx_pctrl_ops,
+ imx_pinctrl_desc->pmxops = &imx_pmx_ops,
+ imx_pinctrl_desc->confops = &imx_pinconf_ops,
+ imx_pinctrl_desc->owner = THIS_MODULE,
ret = imx_pinctrl_probe_dt(pdev, info);
if (ret) {
@@ -789,7 +791,8 @@ int imx_pinctrl_probe(struct platform_device *pdev,
ipctl->info = info;
ipctl->dev = info->dev;
platform_set_drvdata(pdev, ipctl);
- ipctl->pctl = devm_pinctrl_register(&pdev->dev, &imx_pinctrl_desc, ipctl);
+ ipctl->pctl = devm_pinctrl_register(&pdev->dev,
+ imx_pinctrl_desc, ipctl);
if (IS_ERR(ipctl->pctl)) {
dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
return PTR_ERR(ipctl->pctl);
diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c
index b4400cb19b61..a4e9f430d452 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c
@@ -19,7 +19,6 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/machine.h>
@@ -157,7 +156,7 @@ static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
return !!(readl(reg) & BIT(offset));
}
-static const inline struct imx1_pin_group *imx1_pinctrl_find_group_by_name(
+static inline const struct imx1_pin_group *imx1_pinctrl_find_group_by_name(
const struct imx1_pinctrl_soc_info *info,
const char *name)
{
diff --git a/drivers/pinctrl/freescale/pinctrl-imx1.c b/drivers/pinctrl/freescale/pinctrl-imx1.c
index 04723455db58..fc8efc748734 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx1.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx1.c
@@ -9,7 +9,7 @@
* (at your option) any later version.
*/
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -262,7 +262,6 @@ static const struct of_device_id imx1_pinctrl_of_match[] = {
{ .compatible = "fsl,imx1-iomuxc", },
{ }
};
-MODULE_DEVICE_TABLE(of, imx1_pinctrl_of_match);
static struct platform_driver imx1_pinctrl_driver = {
.driver = {
@@ -270,8 +269,4 @@ static struct platform_driver imx1_pinctrl_driver = {
.of_match_table = imx1_pinctrl_of_match,
},
};
-module_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe);
-
-MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
-MODULE_DESCRIPTION("Freescale i.MX1 pinctrl driver");
-MODULE_LICENSE("GPL");
+builtin_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe);
diff --git a/drivers/pinctrl/freescale/pinctrl-imx21.c b/drivers/pinctrl/freescale/pinctrl-imx21.c
index aa1221f4dbb7..73e26bc12f09 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx21.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx21.c
@@ -9,7 +9,7 @@
* (at your option) any later version.
*/
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -325,7 +325,6 @@ static const struct of_device_id imx21_pinctrl_of_match[] = {
{ .compatible = "fsl,imx21-iomuxc", },
{ }
};
-MODULE_DEVICE_TABLE(of, imx21_pinctrl_of_match);
static struct platform_driver imx21_pinctrl_driver = {
.driver = {
@@ -333,8 +332,4 @@ static struct platform_driver imx21_pinctrl_driver = {
.of_match_table = imx21_pinctrl_of_match,
},
};
-module_platform_driver_probe(imx21_pinctrl_driver, imx21_pinctrl_probe);
-
-MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
-MODULE_DESCRIPTION("Freescale i.MX21 pinctrl driver");
-MODULE_LICENSE("GPL");
+builtin_platform_driver_probe(imx21_pinctrl_driver, imx21_pinctrl_probe);
diff --git a/drivers/pinctrl/freescale/pinctrl-imx23.c b/drivers/pinctrl/freescale/pinctrl-imx23.c
index 955cbf4f094f..89b4f160138f 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx23.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx23.c
@@ -1,4 +1,7 @@
/*
+ * Freescale i.MX23 pinctrl driver
+ *
+ * Author: Shawn Guo <shawn.guo@linaro.org>
* Copyright 2012 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
@@ -10,7 +13,6 @@
*/
#include <linux/init.h>
-#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mxs.h"
@@ -276,15 +278,14 @@ static const struct of_device_id imx23_pinctrl_of_match[] = {
{ .compatible = "fsl,imx23-pinctrl", },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, imx23_pinctrl_of_match);
static struct platform_driver imx23_pinctrl_driver = {
.driver = {
.name = "imx23-pinctrl",
+ .suppress_bind_attrs = true,
.of_match_table = imx23_pinctrl_of_match,
},
.probe = imx23_pinctrl_probe,
- .remove = mxs_pinctrl_remove,
};
static int __init imx23_pinctrl_init(void)
@@ -292,13 +293,3 @@ static int __init imx23_pinctrl_init(void)
return platform_driver_register(&imx23_pinctrl_driver);
}
postcore_initcall(imx23_pinctrl_init);
-
-static void __exit imx23_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx23_pinctrl_driver);
-}
-module_exit(imx23_pinctrl_exit);
-
-MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
-MODULE_DESCRIPTION("Freescale i.MX23 pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/freescale/pinctrl-imx25.c b/drivers/pinctrl/freescale/pinctrl-imx25.c
index 81ad546d74bb..d7367fabe712 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx25.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx25.c
@@ -18,7 +18,6 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -338,12 +337,3 @@ static int __init imx25_pinctrl_init(void)
return platform_driver_register(&imx25_pinctrl_driver);
}
arch_initcall(imx25_pinctrl_init);
-
-static void __exit imx25_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx25_pinctrl_driver);
-}
-module_exit(imx25_pinctrl_exit);
-MODULE_AUTHOR("Denis Carikli <denis@eukrea.com>");
-MODULE_DESCRIPTION("Freescale IMX25 pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/freescale/pinctrl-imx27.c b/drivers/pinctrl/freescale/pinctrl-imx27.c
index f828fbbba4b9..e5992036fc6c 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx27.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx27.c
@@ -14,7 +14,6 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -412,12 +411,3 @@ static int __init imx27_pinctrl_init(void)
return platform_driver_register(&imx27_pinctrl_driver);
}
arch_initcall(imx27_pinctrl_init);
-
-static void __exit imx27_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx27_pinctrl_driver);
-}
-module_exit(imx27_pinctrl_exit);
-MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>");
-MODULE_DESCRIPTION("Freescale IMX27 pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/freescale/pinctrl-imx28.c b/drivers/pinctrl/freescale/pinctrl-imx28.c
index 5082efec4f72..295236dfb0bc 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx28.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx28.c
@@ -1,4 +1,7 @@
/*
+ * Freescale i.MX28 pinctrl driver
+ *
+ * Author: Shawn Guo <shawn.guo@linaro.org>
* Copyright 2012 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
@@ -10,7 +13,6 @@
*/
#include <linux/init.h>
-#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-mxs.h"
@@ -392,15 +394,14 @@ static const struct of_device_id imx28_pinctrl_of_match[] = {
{ .compatible = "fsl,imx28-pinctrl", },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, imx28_pinctrl_of_match);
static struct platform_driver imx28_pinctrl_driver = {
.driver = {
.name = "imx28-pinctrl",
+ .suppress_bind_attrs = true,
.of_match_table = imx28_pinctrl_of_match,
},
.probe = imx28_pinctrl_probe,
- .remove = mxs_pinctrl_remove,
};
static int __init imx28_pinctrl_init(void)
@@ -408,13 +409,3 @@ static int __init imx28_pinctrl_init(void)
return platform_driver_register(&imx28_pinctrl_driver);
}
postcore_initcall(imx28_pinctrl_init);
-
-static void __exit imx28_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx28_pinctrl_driver);
-}
-module_exit(imx28_pinctrl_exit);
-
-MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
-MODULE_DESCRIPTION("Freescale i.MX28 pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/freescale/pinctrl-imx35.c b/drivers/pinctrl/freescale/pinctrl-imx35.c
index 13eb224a29a9..6315ba6af431 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx35.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx35.c
@@ -16,7 +16,6 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -1028,12 +1027,3 @@ static int __init imx35_pinctrl_init(void)
return platform_driver_register(&imx35_pinctrl_driver);
}
arch_initcall(imx35_pinctrl_init);
-
-static void __exit imx35_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx35_pinctrl_driver);
-}
-module_exit(imx35_pinctrl_exit);
-MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
-MODULE_DESCRIPTION("Freescale IMX35 pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/freescale/pinctrl-imx50.c b/drivers/pinctrl/freescale/pinctrl-imx50.c
index 95a36c88b66a..8e3a17df5c5d 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx50.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx50.c
@@ -14,7 +14,6 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -415,11 +414,3 @@ static int __init imx50_pinctrl_init(void)
return platform_driver_register(&imx50_pinctrl_driver);
}
arch_initcall(imx50_pinctrl_init);
-
-static void __exit imx50_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx50_pinctrl_driver);
-}
-module_exit(imx50_pinctrl_exit);
-MODULE_DESCRIPTION("Freescale IMX50 pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/freescale/pinctrl-imx51.c b/drivers/pinctrl/freescale/pinctrl-imx51.c
index 0863e5279896..eeac64ba2709 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx51.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx51.c
@@ -15,7 +15,6 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -791,12 +790,3 @@ static int __init imx51_pinctrl_init(void)
return platform_driver_register(&imx51_pinctrl_driver);
}
arch_initcall(imx51_pinctrl_init);
-
-static void __exit imx51_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx51_pinctrl_driver);
-}
-module_exit(imx51_pinctrl_exit);
-MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
-MODULE_DESCRIPTION("Freescale IMX51 pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/freescale/pinctrl-imx53.c b/drivers/pinctrl/freescale/pinctrl-imx53.c
index 64c9cbe2a5df..46a9572f3473 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx53.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx53.c
@@ -15,7 +15,6 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -478,12 +477,3 @@ static int __init imx53_pinctrl_init(void)
return platform_driver_register(&imx53_pinctrl_driver);
}
arch_initcall(imx53_pinctrl_init);
-
-static void __exit imx53_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx53_pinctrl_driver);
-}
-module_exit(imx53_pinctrl_exit);
-MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
-MODULE_DESCRIPTION("Freescale IMX53 pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6dl.c b/drivers/pinctrl/freescale/pinctrl-imx6dl.c
index de17bac8ad89..3f25ca5867cc 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6dl.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6dl.c
@@ -1,4 +1,7 @@
/*
+ * Freescale imx6dl pinctrl driver
+ *
+ * Author: Shawn Guo <shawn.guo@linaro.org>
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
@@ -9,7 +12,6 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -484,13 +486,3 @@ static int __init imx6dl_pinctrl_init(void)
return platform_driver_register(&imx6dl_pinctrl_driver);
}
arch_initcall(imx6dl_pinctrl_init);
-
-static void __exit imx6dl_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx6dl_pinctrl_driver);
-}
-module_exit(imx6dl_pinctrl_exit);
-
-MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
-MODULE_DESCRIPTION("Freescale imx6dl pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6q.c b/drivers/pinctrl/freescale/pinctrl-imx6q.c
index 55cd8a0e367d..d61651c40458 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6q.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6q.c
@@ -15,7 +15,6 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -490,12 +489,3 @@ static int __init imx6q_pinctrl_init(void)
return platform_driver_register(&imx6q_pinctrl_driver);
}
arch_initcall(imx6q_pinctrl_init);
-
-static void __exit imx6q_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx6q_pinctrl_driver);
-}
-module_exit(imx6q_pinctrl_exit);
-MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
-MODULE_DESCRIPTION("Freescale IMX6Q pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sl.c b/drivers/pinctrl/freescale/pinctrl-imx6sl.c
index bf455b8e73fc..d023f6b00623 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6sl.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sl.c
@@ -1,4 +1,7 @@
/*
+ * Freescale imx6sl pinctrl driver
+ *
+ * Author: Shawn Guo <shawn.guo@linaro.org>
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
@@ -9,7 +12,6 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -371,7 +373,6 @@ static const struct of_device_id imx6sl_pinctrl_of_match[] = {
{ .compatible = "fsl,imx6sl-iomuxc", },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, imx6sl_pinctrl_of_match);
static int imx6sl_pinctrl_probe(struct platform_device *pdev)
{
@@ -391,13 +392,3 @@ static int __init imx6sl_pinctrl_init(void)
return platform_driver_register(&imx6sl_pinctrl_driver);
}
arch_initcall(imx6sl_pinctrl_init);
-
-static void __exit imx6sl_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx6sl_pinctrl_driver);
-}
-module_exit(imx6sl_pinctrl_exit);
-
-MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
-MODULE_DESCRIPTION("Freescale imx6sl pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sx.c b/drivers/pinctrl/freescale/pinctrl-imx6sx.c
index 84118c388cc5..898b781701e6 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6sx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sx.c
@@ -1,4 +1,7 @@
/*
+ * Freescale imx6sx pinctrl driver
+ *
+ * Author: Anson Huang <Anson.Huang@freescale.com>
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
@@ -9,7 +12,6 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -394,13 +396,3 @@ static int __init imx6sx_pinctrl_init(void)
return platform_driver_register(&imx6sx_pinctrl_driver);
}
arch_initcall(imx6sx_pinctrl_init);
-
-static void __exit imx6sx_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx6sx_pinctrl_driver);
-}
-module_exit(imx6sx_pinctrl_exit);
-
-MODULE_AUTHOR("Anson Huang <Anson.Huang@freescale.com>");
-MODULE_DESCRIPTION("Freescale imx6sx pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6ul.c b/drivers/pinctrl/freescale/pinctrl-imx6ul.c
index c707fdd933ec..1aeb840aae1d 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6ul.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6ul.c
@@ -1,4 +1,7 @@
/*
+ * Freescale imx6ul pinctrl driver
+ *
+ * Author: Anson Huang <Anson.Huang@freescale.com>
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
@@ -9,7 +12,6 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -310,13 +312,3 @@ static int __init imx6ul_pinctrl_init(void)
return platform_driver_register(&imx6ul_pinctrl_driver);
}
arch_initcall(imx6ul_pinctrl_init);
-
-static void __exit imx6ul_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx6ul_pinctrl_driver);
-}
-module_exit(imx6ul_pinctrl_exit);
-
-MODULE_AUTHOR("Anson Huang <Anson.Huang@freescale.com>");
-MODULE_DESCRIPTION("Freescale imx6ul pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index d30d91f80dfd..a465a66c3ef4 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -1,4 +1,7 @@
/*
+ * Freescale imx7d pinctrl driver
+ *
+ * Author: Anson Huang <Anson.Huang@freescale.com>
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
@@ -9,7 +12,6 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -402,13 +404,3 @@ static int __init imx7d_pinctrl_init(void)
return platform_driver_register(&imx7d_pinctrl_driver);
}
arch_initcall(imx7d_pinctrl_init);
-
-static void __exit imx7d_pinctrl_exit(void)
-{
- platform_driver_unregister(&imx7d_pinctrl_driver);
-}
-module_exit(imx7d_pinctrl_exit);
-
-MODULE_AUTHOR("Anson Huang <Anson.Huang@freescale.com>");
-MODULE_DESCRIPTION("Freescale imx7d pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.c b/drivers/pinctrl/freescale/pinctrl-mxs.c
index 6bbda6b4ab50..41b5b07d5a2b 100644
--- a/drivers/pinctrl/freescale/pinctrl-mxs.c
+++ b/drivers/pinctrl/freescale/pinctrl-mxs.c
@@ -12,7 +12,6 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pinctrl/machine.h>
@@ -553,14 +552,3 @@ err:
return ret;
}
EXPORT_SYMBOL_GPL(mxs_pinctrl_probe);
-
-int mxs_pinctrl_remove(struct platform_device *pdev)
-{
- struct mxs_pinctrl_data *d = platform_get_drvdata(pdev);
-
- pinctrl_unregister(d->pctl);
- iounmap(d->base);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(mxs_pinctrl_remove);
diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.h b/drivers/pinctrl/freescale/pinctrl-mxs.h
index fdd88d0bae22..34dbf75208dc 100644
--- a/drivers/pinctrl/freescale/pinctrl-mxs.h
+++ b/drivers/pinctrl/freescale/pinctrl-mxs.h
@@ -86,6 +86,5 @@ struct mxs_pinctrl_soc_data {
int mxs_pinctrl_probe(struct platform_device *pdev,
struct mxs_pinctrl_soc_data *soc);
-int mxs_pinctrl_remove(struct platform_device *pdev);
#endif /* __PINCTRL_MXS_H */
diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c
index 6d81be096bc0..2b1e198e3092 100644
--- a/drivers/pinctrl/freescale/pinctrl-vf610.c
+++ b/drivers/pinctrl/freescale/pinctrl-vf610.c
@@ -12,7 +12,6 @@
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -325,12 +324,3 @@ static int __init vf610_pinctrl_init(void)
return platform_driver_register(&vf610_pinctrl_driver);
}
arch_initcall(vf610_pinctrl_init);
-
-static void __exit vf610_pinctrl_exit(void)
-{
- platform_driver_unregister(&vf610_pinctrl_driver);
-}
-module_exit(vf610_pinctrl_exit);
-
-MODULE_DESCRIPTION("Freescale VF610 pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index 1c74e038b7b0..00fb055a4897 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -29,6 +29,17 @@ config PINCTRL_CHERRYVIEW
Cherryview/Braswell pinctrl driver provides an interface that
allows configuring of SoC pins and using them as GPIOs.
+config PINCTRL_MERRIFIELD
+ tristate "Intel Merrifield pinctrl driver"
+ depends on X86_INTEL_MID
+ select PINMUX
+ select PINCONF
+ select GENERIC_PINCONF
+ help
+ Merrifield Family-Level Interface Shim (FLIS) driver provides an
+ interface that allows configuring of SoC pins and using them as
+ GPIOs.
+
config PINCTRL_INTEL
tristate
select PINMUX
diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile
index 03bc68e3546c..30803078f09e 100644
--- a/drivers/pinctrl/intel/Makefile
+++ b/drivers/pinctrl/intel/Makefile
@@ -2,6 +2,7 @@
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o
+obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o
obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index 7abfd42e8ffd..d22a9fe2e6df 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -15,7 +15,6 @@
*/
#include <linux/kernel.h>
-#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/bitops.h>
@@ -1822,17 +1821,6 @@ static int byt_pinctrl_probe(struct platform_device *pdev)
return 0;
}
-static int byt_pinctrl_remove(struct platform_device *pdev)
-{
- struct byt_gpio *vg = platform_get_drvdata(pdev);
-
- pm_runtime_disable(&pdev->dev);
- gpiochip_remove(&vg->chip);
- pinctrl_unregister(vg->pctl_dev);
-
- return 0;
-}
-
#ifdef CONFIG_PM_SLEEP
static int byt_gpio_suspend(struct device *dev)
{
@@ -1930,10 +1918,11 @@ static const struct dev_pm_ops byt_gpio_pm_ops = {
static struct platform_driver byt_gpio_driver = {
.probe = byt_pinctrl_probe,
- .remove = byt_pinctrl_remove,
.driver = {
- .name = "byt_gpio",
- .pm = &byt_gpio_pm_ops,
+ .name = "byt_gpio",
+ .pm = &byt_gpio_pm_ops,
+ .suppress_bind_attrs = true,
+
.acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
},
};
@@ -1943,9 +1932,3 @@ static int __init byt_gpio_init(void)
return platform_driver_register(&byt_gpio_driver);
}
subsys_initcall(byt_gpio_init);
-
-static void __exit byt_gpio_exit(void)
-{
- platform_driver_unregister(&byt_gpio_driver);
-}
-module_exit(byt_gpio_exit);
diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c
index 5979d38c46b2..59cb7a6fc5be 100644
--- a/drivers/pinctrl/intel/pinctrl-broxton.c
+++ b/drivers/pinctrl/intel/pinctrl-broxton.c
@@ -1,7 +1,7 @@
/*
* Intel Broxton SoC pinctrl/GPIO driver
*
- * Copyright (C) 2015, Intel Corporation
+ * Copyright (C) 2015, 2016 Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
@@ -1003,29 +1003,46 @@ static const struct acpi_device_id bxt_pinctrl_acpi_match[] = {
};
MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match);
+static const struct platform_device_id bxt_pinctrl_platform_ids[] = {
+ { "apl-pinctrl", (kernel_ulong_t)&apl_pinctrl_soc_data },
+ { "broxton-pinctrl", (kernel_ulong_t)&bxt_pinctrl_soc_data },
+ { },
+};
+
static int bxt_pinctrl_probe(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *soc_data = NULL;
const struct intel_pinctrl_soc_data **soc_table;
- const struct acpi_device_id *id;
struct acpi_device *adev;
int i;
adev = ACPI_COMPANION(&pdev->dev);
- if (!adev)
- return -ENODEV;
+ if (adev) {
+ const struct acpi_device_id *id;
- id = acpi_match_device(bxt_pinctrl_acpi_match, &pdev->dev);
- if (!id)
- return -ENODEV;
+ id = acpi_match_device(bxt_pinctrl_acpi_match, &pdev->dev);
+ if (!id)
+ return -ENODEV;
- soc_table = (const struct intel_pinctrl_soc_data **)id->driver_data;
+ soc_table = (const struct intel_pinctrl_soc_data **)
+ id->driver_data;
- for (i = 0; soc_table[i]; i++) {
- if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) {
- soc_data = soc_table[i];
- break;
+ for (i = 0; soc_table[i]; i++) {
+ if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) {
+ soc_data = soc_table[i];
+ break;
+ }
}
+ } else {
+ const struct platform_device_id *pid;
+
+ pid = platform_get_device_id(pdev);
+ if (!pid)
+ return -ENODEV;
+
+ soc_table = (const struct intel_pinctrl_soc_data **)
+ pid->driver_data;
+ soc_data = soc_table[pdev->id];
}
if (!soc_data)
@@ -1047,6 +1064,7 @@ static struct platform_driver bxt_pinctrl_driver = {
.acpi_match_table = bxt_pinctrl_acpi_match,
.pm = &bxt_pinctrl_pm_ops,
},
+ .id_table = bxt_pinctrl_platform_ids,
};
static int __init bxt_pinctrl_init(void)
@@ -1064,3 +1082,4 @@ module_exit(bxt_pinctrl_exit);
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:broxton-pinctrl");
diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c
index ac4f564f1c3e..5749a4eee746 100644
--- a/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@ -160,7 +160,6 @@ struct chv_pin_context {
* @pctldev: Pointer to the pin controller device
* @chip: GPIO chip in this pin controller
* @regs: MMIO registers
- * @lock: Lock to serialize register accesses
* @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
* offset (in GPIO number space)
* @community: Community this pinctrl instance represents
@@ -174,7 +173,6 @@ struct chv_pinctrl {
struct pinctrl_dev *pctldev;
struct gpio_chip chip;
void __iomem *regs;
- raw_spinlock_t lock;
unsigned intr_lines[16];
const struct chv_community *community;
u32 saved_intmask;
@@ -657,6 +655,17 @@ static const struct chv_community *chv_communities[] = {
&southeast_community,
};
+/*
+ * Lock to serialize register accesses
+ *
+ * Due to a silicon issue, a shared lock must be used to prevent
+ * concurrent accesses across the 4 GPIO controllers.
+ *
+ * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
+ * errata #CHT34, for further information.
+ */
+static DEFINE_RAW_SPINLOCK(chv_lock);
+
static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset,
unsigned reg)
{
@@ -718,13 +727,13 @@ static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
u32 ctrl0, ctrl1;
bool locked;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
locked = chv_pad_locked(pctrl, offset);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
seq_puts(s, "GPIO ");
@@ -787,14 +796,14 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
grp = &pctrl->community->groups[group];
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&chv_lock, flags);
/* Check first that the pad is not locked */
for (i = 0; i < grp->npins; i++) {
if (chv_pad_locked(pctrl, grp->pins[i])) {
dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
grp->pins[i]);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EBUSY;
}
}
@@ -837,7 +846,7 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
}
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
@@ -851,13 +860,13 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
void __iomem *reg;
u32 value;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&chv_lock, flags);
if (chv_pad_locked(pctrl, offset)) {
value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
if (!(value & CHV_PADCTRL0_GPIOEN)) {
/* Locked so cannot enable */
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EBUSY;
}
} else {
@@ -897,7 +906,7 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
chv_writel(value, reg);
}
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
@@ -911,13 +920,13 @@ static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
void __iomem *reg;
u32 value;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&chv_lock, flags);
reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
value = readl(reg) & ~CHV_PADCTRL0_GPIOEN;
chv_writel(value, reg);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
}
static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
@@ -929,7 +938,7 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
unsigned long flags;
u32 ctrl0;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
if (input)
@@ -938,7 +947,7 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
chv_writel(ctrl0, reg);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
@@ -963,10 +972,10 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin,
u16 arg = 0;
u32 term;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
@@ -1040,7 +1049,7 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
unsigned long flags;
u32 ctrl0, pull;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = readl(reg);
switch (param) {
@@ -1063,7 +1072,7 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
break;
default:
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EINVAL;
}
@@ -1081,7 +1090,7 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
break;
default:
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EINVAL;
}
@@ -1089,12 +1098,33 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
break;
default:
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
return -EINVAL;
}
chv_writel(ctrl0, reg);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
+
+ return 0;
+}
+
+static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
+ bool enable)
+{
+ void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
+ unsigned long flags;
+ u32 ctrl1;
+
+ raw_spin_lock_irqsave(&chv_lock, flags);
+ ctrl1 = readl(reg);
+
+ if (enable)
+ ctrl1 |= CHV_PADCTRL1_ODEN;
+ else
+ ctrl1 &= ~CHV_PADCTRL1_ODEN;
+
+ chv_writel(ctrl1, reg);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
@@ -1123,6 +1153,18 @@ static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin,
return ret;
break;
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ ret = chv_config_set_oden(pctrl, pin, false);
+ if (ret)
+ return ret;
+ break;
+
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ ret = chv_config_set_oden(pctrl, pin, true);
+ if (ret)
+ return ret;
+ break;
+
default:
return -ENOTSUPP;
}
@@ -1134,10 +1176,52 @@ static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin,
return 0;
}
+static int chv_config_group_get(struct pinctrl_dev *pctldev,
+ unsigned int group,
+ unsigned long *config)
+{
+ const unsigned int *pins;
+ unsigned int npins;
+ int ret;
+
+ ret = chv_get_group_pins(pctldev, group, &pins, &npins);
+ if (ret)
+ return ret;
+
+ ret = chv_config_get(pctldev, pins[0], config);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int chv_config_group_set(struct pinctrl_dev *pctldev,
+ unsigned int group, unsigned long *configs,
+ unsigned int num_configs)
+{
+ const unsigned int *pins;
+ unsigned int npins;
+ int i, ret;
+
+ ret = chv_get_group_pins(pctldev, group, &pins, &npins);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < npins; i++) {
+ ret = chv_config_set(pctldev, pins[i], configs, num_configs);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static const struct pinconf_ops chv_pinconf_ops = {
.is_generic = true,
.pin_config_set = chv_config_set,
.pin_config_get = chv_config_get,
+ .pin_config_group_get = chv_config_group_get,
+ .pin_config_group_set = chv_config_group_set,
};
static struct pinctrl_desc chv_pinctrl_desc = {
@@ -1160,9 +1244,9 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
unsigned long flags;
u32 ctrl0, cfg;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
@@ -1180,7 +1264,7 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
void __iomem *reg;
u32 ctrl0;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&chv_lock, flags);
reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
ctrl0 = readl(reg);
@@ -1192,7 +1276,7 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
chv_writel(ctrl0, reg);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
}
static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
@@ -1202,9 +1286,9 @@ static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
u32 ctrl0, direction;
unsigned long flags;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&chv_lock, flags);
ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
@@ -1242,14 +1326,14 @@ static void chv_gpio_irq_ack(struct irq_data *d)
int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d));
u32 intr_line;
- raw_spin_lock(&pctrl->lock);
+ raw_spin_lock(&chv_lock);
intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
intr_line &= CHV_PADCTRL0_INTSEL_MASK;
intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
- raw_spin_unlock(&pctrl->lock);
+ raw_spin_unlock(&chv_lock);
}
static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
@@ -1260,7 +1344,7 @@ static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
u32 value, intr_line;
unsigned long flags;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&chv_lock, flags);
intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
intr_line &= CHV_PADCTRL0_INTSEL_MASK;
@@ -1273,7 +1357,7 @@ static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
value |= BIT(intr_line);
chv_writel(value, pctrl->regs + CHV_INTMASK);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
}
static void chv_gpio_irq_mask(struct irq_data *d)
@@ -1307,7 +1391,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
unsigned long flags;
u32 intsel, value;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&chv_lock, flags);
intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
intsel &= CHV_PADCTRL0_INTSEL_MASK;
intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
@@ -1322,7 +1406,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
irq_set_handler_locked(d, handler);
pctrl->intr_lines[intsel] = offset;
}
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
}
chv_gpio_irq_unmask(d);
@@ -1338,7 +1422,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
unsigned long flags;
u32 value;
- raw_spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&chv_lock, flags);
/*
* Pins which can be used as shared interrupt are configured in
@@ -1387,7 +1471,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
else if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(d, handle_level_irq);
- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&chv_lock, flags);
return 0;
}
@@ -1499,7 +1583,6 @@ static int chv_pinctrl_probe(struct platform_device *pdev)
if (i == ARRAY_SIZE(chv_communities))
return -ENODEV;
- raw_spin_lock_init(&pctrl->lock);
pctrl->dev = &pdev->dev;
#ifdef CONFIG_PM_SLEEP
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 3584e50fa2c6..257cab129692 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -89,7 +89,7 @@ struct intel_pinctrl_context {
*/
struct intel_pinctrl {
struct device *dev;
- spinlock_t lock;
+ raw_spinlock_t lock;
struct pinctrl_desc pctldesc;
struct pinctrl_dev *pctldev;
struct gpio_chip chip;
@@ -318,7 +318,7 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
unsigned long flags;
int i;
- spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
/*
* All pins in the groups needs to be accessible and writable
@@ -326,7 +326,7 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
*/
for (i = 0; i < grp->npins; i++) {
if (!intel_pad_usable(pctrl, grp->pins[i])) {
- spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return -EBUSY;
}
}
@@ -345,7 +345,7 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
writel(value, padcfg0);
}
- spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
@@ -359,10 +359,10 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
unsigned long flags;
u32 value;
- spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
if (!intel_pad_usable(pctrl, pin)) {
- spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return -EBUSY;
}
@@ -377,7 +377,7 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
value |= PADCFG0_GPIOTXDIS;
writel(value, padcfg0);
- spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
@@ -391,7 +391,7 @@ static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
unsigned long flags;
u32 value;
- spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
@@ -402,7 +402,7 @@ static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
value &= ~PADCFG0_GPIOTXDIS;
writel(value, padcfg0);
- spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
@@ -490,7 +490,7 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
int ret = 0;
u32 value;
- spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
value = readl(padcfg1);
@@ -544,7 +544,7 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
if (!ret)
writel(value, padcfg1);
- spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return ret;
}
@@ -611,14 +611,14 @@ static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
unsigned long flags;
u32 padcfg0;
- spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
padcfg0 = readl(reg);
if (value)
padcfg0 |= PADCFG0_GPIOTXSTATE;
else
padcfg0 &= ~PADCFG0_GPIOTXSTATE;
writel(padcfg0, reg);
- spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
}
@@ -651,7 +651,7 @@ static void intel_gpio_irq_ack(struct irq_data *d)
const struct intel_community *community;
unsigned pin = irqd_to_hwirq(d);
- spin_lock(&pctrl->lock);
+ raw_spin_lock(&pctrl->lock);
community = intel_get_community(pctrl, pin);
if (community) {
@@ -662,7 +662,7 @@ static void intel_gpio_irq_ack(struct irq_data *d)
writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
}
- spin_unlock(&pctrl->lock);
+ raw_spin_unlock(&pctrl->lock);
}
static void intel_gpio_irq_enable(struct irq_data *d)
@@ -673,7 +673,7 @@ static void intel_gpio_irq_enable(struct irq_data *d)
unsigned pin = irqd_to_hwirq(d);
unsigned long flags;
- spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
community = intel_get_community(pctrl, pin);
if (community) {
@@ -691,7 +691,7 @@ static void intel_gpio_irq_enable(struct irq_data *d)
writel(value, community->regs + community->ie_offset + gpp * 4);
}
- spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
@@ -702,7 +702,7 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
unsigned pin = irqd_to_hwirq(d);
unsigned long flags;
- spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
community = intel_get_community(pctrl, pin);
if (community) {
@@ -721,7 +721,7 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
writel(value, reg);
}
- spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
static void intel_gpio_irq_mask(struct irq_data *d)
@@ -757,7 +757,7 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
return -EPERM;
}
- spin_lock_irqsave(&pctrl->lock, flags);
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
value = readl(reg);
@@ -784,7 +784,7 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
else if (type & IRQ_TYPE_LEVEL_MASK)
irq_set_handler_locked(d, handle_level_irq);
- spin_unlock_irqrestore(&pctrl->lock, flags);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
@@ -796,12 +796,15 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
const struct intel_community *community;
unsigned pin = irqd_to_hwirq(d);
unsigned padno, gpp, gpp_offset;
+ unsigned long flags;
u32 gpe_en;
community = intel_get_community(pctrl, pin);
if (!community)
return -EINVAL;
+ raw_spin_lock_irqsave(&pctrl->lock, flags);
+
padno = pin_to_padno(community, pin);
gpp = padno / community->gpp_size;
gpp_offset = padno % community->gpp_size;
@@ -821,6 +824,8 @@ static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
gpe_en &= ~BIT(gpp_offset);
writel(gpe_en, community->regs + GPI_GPE_EN + gpp * 4);
+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
+
dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
return 0;
}
@@ -919,7 +924,8 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
* to the irq directly) because on some platforms several GPIO
* controllers share the same interrupt line.
*/
- ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, IRQF_SHARED,
+ ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
+ IRQF_SHARED | IRQF_NO_THREAD,
dev_name(pctrl->dev), pctrl);
if (ret) {
dev_err(pctrl->dev, "failed to request interrupt\n");
@@ -995,7 +1001,7 @@ int intel_pinctrl_probe(struct platform_device *pdev,
pctrl->dev = &pdev->dev;
pctrl->soc = soc_data;
- spin_lock_init(&pctrl->lock);
+ raw_spin_lock_init(&pctrl->lock);
/*
* Make a copy of the communities which we can use to hold pointers
diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c
new file mode 100644
index 000000000000..eb4990ff26ca
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-merrifield.c
@@ -0,0 +1,911 @@
+/*
+ * Intel Merrifield SoC pinctrl driver
+ *
+ * Copyright (C) 2016, Intel Corporation
+ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "pinctrl-intel.h"
+
+#define MRFLD_FAMILY_NR 64
+#define MRFLD_FAMILY_LEN 0x400
+
+#define SLEW_OFFSET 0x000
+#define BUFCFG_OFFSET 0x100
+#define MISC_OFFSET 0x300
+
+#define BUFCFG_PINMODE_SHIFT 0
+#define BUFCFG_PINMODE_MASK GENMASK(2, 0)
+#define BUFCFG_PINMODE_GPIO 0
+#define BUFCFG_PUPD_VAL_SHIFT 4
+#define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4)
+#define BUFCFG_PUPD_VAL_2K 0
+#define BUFCFG_PUPD_VAL_20K 1
+#define BUFCFG_PUPD_VAL_50K 2
+#define BUFCFG_PUPD_VAL_910 3
+#define BUFCFG_PU_EN BIT(8)
+#define BUFCFG_PD_EN BIT(9)
+#define BUFCFG_Px_EN_MASK GENMASK(9, 8)
+#define BUFCFG_SLEWSEL BIT(10)
+#define BUFCFG_OVINEN BIT(12)
+#define BUFCFG_OVINEN_EN BIT(13)
+#define BUFCFG_OVINEN_MASK GENMASK(13, 12)
+#define BUFCFG_OVOUTEN BIT(14)
+#define BUFCFG_OVOUTEN_EN BIT(15)
+#define BUFCFG_OVOUTEN_MASK GENMASK(15, 14)
+#define BUFCFG_INDATAOV_VAL BIT(16)
+#define BUFCFG_INDATAOV_EN BIT(17)
+#define BUFCFG_INDATAOV_MASK GENMASK(17, 16)
+#define BUFCFG_OUTDATAOV_VAL BIT(18)
+#define BUFCFG_OUTDATAOV_EN BIT(19)
+#define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18)
+#define BUFCFG_OD_EN BIT(21)
+
+/**
+ * struct mrfld_family - Intel pin family description
+ * @barno: MMIO BAR number where registers for this family reside
+ * @pin_base: Starting pin of pins in this family
+ * @npins: Number of pins in this family
+ * @protected: True if family is protected by access
+ * @regs: family specific common registers
+ */
+struct mrfld_family {
+ unsigned int barno;
+ unsigned int pin_base;
+ size_t npins;
+ bool protected;
+ void __iomem *regs;
+};
+
+#define MRFLD_FAMILY(b, s, e) \
+ { \
+ .barno = (b), \
+ .pin_base = (s), \
+ .npins = (e) - (s) + 1, \
+ }
+
+#define MRFLD_FAMILY_PROTECTED(b, s, e) \
+ { \
+ .barno = (b), \
+ .pin_base = (s), \
+ .npins = (e) - (s) + 1, \
+ .protected = true, \
+ }
+
+static const struct pinctrl_pin_desc mrfld_pins[] = {
+ /* Family 0: OCP2SSC (0 pins) */
+ /* Family 1: ULPI (13 pins) */
+ PINCTRL_PIN(0, "ULPI_CLK"),
+ PINCTRL_PIN(1, "ULPI_D0"),
+ PINCTRL_PIN(2, "ULPI_D1"),
+ PINCTRL_PIN(3, "ULPI_D2"),
+ PINCTRL_PIN(4, "ULPI_D3"),
+ PINCTRL_PIN(5, "ULPI_D4"),
+ PINCTRL_PIN(6, "ULPI_D5"),
+ PINCTRL_PIN(7, "ULPI_D6"),
+ PINCTRL_PIN(8, "ULPI_D7"),
+ PINCTRL_PIN(9, "ULPI_DIR"),
+ PINCTRL_PIN(10, "ULPI_NXT"),
+ PINCTRL_PIN(11, "ULPI_REFCLK"),
+ PINCTRL_PIN(12, "ULPI_STP"),
+ /* Family 2: eMMC (24 pins) */
+ PINCTRL_PIN(13, "EMMC_CLK"),
+ PINCTRL_PIN(14, "EMMC_CMD"),
+ PINCTRL_PIN(15, "EMMC_D0"),
+ PINCTRL_PIN(16, "EMMC_D1"),
+ PINCTRL_PIN(17, "EMMC_D2"),
+ PINCTRL_PIN(18, "EMMC_D3"),
+ PINCTRL_PIN(19, "EMMC_D4"),
+ PINCTRL_PIN(20, "EMMC_D5"),
+ PINCTRL_PIN(21, "EMMC_D6"),
+ PINCTRL_PIN(22, "EMMC_D7"),
+ PINCTRL_PIN(23, "EMMC_RST_N"),
+ PINCTRL_PIN(24, "GP154"),
+ PINCTRL_PIN(25, "GP155"),
+ PINCTRL_PIN(26, "GP156"),
+ PINCTRL_PIN(27, "GP157"),
+ PINCTRL_PIN(28, "GP158"),
+ PINCTRL_PIN(29, "GP159"),
+ PINCTRL_PIN(30, "GP160"),
+ PINCTRL_PIN(31, "GP161"),
+ PINCTRL_PIN(32, "GP162"),
+ PINCTRL_PIN(33, "GP163"),
+ PINCTRL_PIN(34, "GP97"),
+ PINCTRL_PIN(35, "GP14"),
+ PINCTRL_PIN(36, "GP15"),
+ /* Family 3: SDIO (20 pins) */
+ PINCTRL_PIN(37, "GP77_SD_CD"),
+ PINCTRL_PIN(38, "GP78_SD_CLK"),
+ PINCTRL_PIN(39, "GP79_SD_CMD"),
+ PINCTRL_PIN(40, "GP80_SD_D0"),
+ PINCTRL_PIN(41, "GP81_SD_D1"),
+ PINCTRL_PIN(42, "GP82_SD_D2"),
+ PINCTRL_PIN(43, "GP83_SD_D3"),
+ PINCTRL_PIN(44, "GP84_SD_LS_CLK_FB"),
+ PINCTRL_PIN(45, "GP85_SD_LS_CMD_DIR"),
+ PINCTRL_PIN(46, "GP86_SD_LVL_D_DIR"),
+ PINCTRL_PIN(47, "GP88_SD_LS_SEL"),
+ PINCTRL_PIN(48, "GP87_SD_PD"),
+ PINCTRL_PIN(49, "GP89_SD_WP"),
+ PINCTRL_PIN(50, "GP90_SDIO_CLK"),
+ PINCTRL_PIN(51, "GP91_SDIO_CMD"),
+ PINCTRL_PIN(52, "GP92_SDIO_D0"),
+ PINCTRL_PIN(53, "GP93_SDIO_D1"),
+ PINCTRL_PIN(54, "GP94_SDIO_D2"),
+ PINCTRL_PIN(55, "GP95_SDIO_D3"),
+ PINCTRL_PIN(56, "GP96_SDIO_PD"),
+ /* Family 4: HSI (8 pins) */
+ PINCTRL_PIN(57, "HSI_ACDATA"),
+ PINCTRL_PIN(58, "HSI_ACFLAG"),
+ PINCTRL_PIN(59, "HSI_ACREADY"),
+ PINCTRL_PIN(60, "HSI_ACWAKE"),
+ PINCTRL_PIN(61, "HSI_CADATA"),
+ PINCTRL_PIN(62, "HSI_CAFLAG"),
+ PINCTRL_PIN(63, "HSI_CAREADY"),
+ PINCTRL_PIN(64, "HSI_CAWAKE"),
+ /* Family 5: SSP Audio (14 pins) */
+ PINCTRL_PIN(65, "GP70"),
+ PINCTRL_PIN(66, "GP71"),
+ PINCTRL_PIN(67, "GP32_I2S_0_CLK"),
+ PINCTRL_PIN(68, "GP33_I2S_0_FS"),
+ PINCTRL_PIN(69, "GP34_I2S_0_RXD"),
+ PINCTRL_PIN(70, "GP35_I2S_0_TXD"),
+ PINCTRL_PIN(71, "GP36_I2S_1_CLK"),
+ PINCTRL_PIN(72, "GP37_I2S_1_FS"),
+ PINCTRL_PIN(73, "GP38_I2S_1_RXD"),
+ PINCTRL_PIN(74, "GP39_I2S_1_TXD"),
+ PINCTRL_PIN(75, "GP40_I2S_2_CLK"),
+ PINCTRL_PIN(76, "GP41_I2S_2_FS"),
+ PINCTRL_PIN(77, "GP42_I2S_2_RXD"),
+ PINCTRL_PIN(78, "GP43_I2S_2_TXD"),
+ /* Family 6: GP SSP (22 pins) */
+ PINCTRL_PIN(79, "GP120_SPI_3_CLK"),
+ PINCTRL_PIN(80, "GP121_SPI_3_SS"),
+ PINCTRL_PIN(81, "GP122_SPI_3_RXD"),
+ PINCTRL_PIN(82, "GP123_SPI_3_TXD"),
+ PINCTRL_PIN(83, "GP102_SPI_4_CLK"),
+ PINCTRL_PIN(84, "GP103_SPI_4_SS_0"),
+ PINCTRL_PIN(85, "GP104_SPI_4_SS_1"),
+ PINCTRL_PIN(86, "GP105_SPI_4_SS_2"),
+ PINCTRL_PIN(87, "GP106_SPI_4_SS_3"),
+ PINCTRL_PIN(88, "GP107_SPI_4_RXD"),
+ PINCTRL_PIN(89, "GP108_SPI_4_TXD"),
+ PINCTRL_PIN(90, "GP109_SPI_5_CLK"),
+ PINCTRL_PIN(91, "GP110_SPI_5_SS_0"),
+ PINCTRL_PIN(92, "GP111_SPI_5_SS_1"),
+ PINCTRL_PIN(93, "GP112_SPI_5_SS_2"),
+ PINCTRL_PIN(94, "GP113_SPI_5_SS_3"),
+ PINCTRL_PIN(95, "GP114_SPI_5_RXD"),
+ PINCTRL_PIN(96, "GP115_SPI_5_TXD"),
+ PINCTRL_PIN(97, "GP116_SPI_6_CLK"),
+ PINCTRL_PIN(98, "GP117_SPI_6_SS"),
+ PINCTRL_PIN(99, "GP118_SPI_6_RXD"),
+ PINCTRL_PIN(100, "GP119_SPI_6_TXD"),
+ /* Family 7: I2C (14 pins) */
+ PINCTRL_PIN(101, "GP19_I2C_1_SCL"),
+ PINCTRL_PIN(102, "GP20_I2C_1_SDA"),
+ PINCTRL_PIN(103, "GP21_I2C_2_SCL"),
+ PINCTRL_PIN(104, "GP22_I2C_2_SDA"),
+ PINCTRL_PIN(105, "GP17_I2C_3_SCL_HDMI"),
+ PINCTRL_PIN(106, "GP18_I2C_3_SDA_HDMI"),
+ PINCTRL_PIN(107, "GP23_I2C_4_SCL"),
+ PINCTRL_PIN(108, "GP24_I2C_4_SDA"),
+ PINCTRL_PIN(109, "GP25_I2C_5_SCL"),
+ PINCTRL_PIN(110, "GP26_I2C_5_SDA"),
+ PINCTRL_PIN(111, "GP27_I2C_6_SCL"),
+ PINCTRL_PIN(112, "GP28_I2C_6_SDA"),
+ PINCTRL_PIN(113, "GP29_I2C_7_SCL"),
+ PINCTRL_PIN(114, "GP30_I2C_7_SDA"),
+ /* Family 8: UART (12 pins) */
+ PINCTRL_PIN(115, "GP124_UART_0_CTS"),
+ PINCTRL_PIN(116, "GP125_UART_0_RTS"),
+ PINCTRL_PIN(117, "GP126_UART_0_RX"),
+ PINCTRL_PIN(118, "GP127_UART_0_TX"),
+ PINCTRL_PIN(119, "GP128_UART_1_CTS"),
+ PINCTRL_PIN(120, "GP129_UART_1_RTS"),
+ PINCTRL_PIN(121, "GP130_UART_1_RX"),
+ PINCTRL_PIN(122, "GP131_UART_1_TX"),
+ PINCTRL_PIN(123, "GP132_UART_2_CTS"),
+ PINCTRL_PIN(124, "GP133_UART_2_RTS"),
+ PINCTRL_PIN(125, "GP134_UART_2_RX"),
+ PINCTRL_PIN(126, "GP135_UART_2_TX"),
+ /* Family 9: GPIO South (19 pins) */
+ PINCTRL_PIN(127, "GP177"),
+ PINCTRL_PIN(128, "GP178"),
+ PINCTRL_PIN(129, "GP179"),
+ PINCTRL_PIN(130, "GP180"),
+ PINCTRL_PIN(131, "GP181"),
+ PINCTRL_PIN(132, "GP182_PWM2"),
+ PINCTRL_PIN(133, "GP183_PWM3"),
+ PINCTRL_PIN(134, "GP184"),
+ PINCTRL_PIN(135, "GP185"),
+ PINCTRL_PIN(136, "GP186"),
+ PINCTRL_PIN(137, "GP187"),
+ PINCTRL_PIN(138, "GP188"),
+ PINCTRL_PIN(139, "GP189"),
+ PINCTRL_PIN(140, "GP64_FAST_INT0"),
+ PINCTRL_PIN(141, "GP65_FAST_INT1"),
+ PINCTRL_PIN(142, "GP66_FAST_INT2"),
+ PINCTRL_PIN(143, "GP67_FAST_INT3"),
+ PINCTRL_PIN(144, "GP12_PWM0"),
+ PINCTRL_PIN(145, "GP13_PWM1"),
+ /* Family 10: Camera Sideband (12 pins) */
+ PINCTRL_PIN(146, "GP0"),
+ PINCTRL_PIN(147, "GP1"),
+ PINCTRL_PIN(148, "GP2"),
+ PINCTRL_PIN(149, "GP3"),
+ PINCTRL_PIN(150, "GP4"),
+ PINCTRL_PIN(151, "GP5"),
+ PINCTRL_PIN(152, "GP6"),
+ PINCTRL_PIN(153, "GP7"),
+ PINCTRL_PIN(154, "GP8"),
+ PINCTRL_PIN(155, "GP9"),
+ PINCTRL_PIN(156, "GP10"),
+ PINCTRL_PIN(157, "GP11"),
+ /* Family 11: Clock (22 pins) */
+ PINCTRL_PIN(158, "GP137"),
+ PINCTRL_PIN(159, "GP138"),
+ PINCTRL_PIN(160, "GP139"),
+ PINCTRL_PIN(161, "GP140"),
+ PINCTRL_PIN(162, "GP141"),
+ PINCTRL_PIN(163, "GP142"),
+ PINCTRL_PIN(164, "GP16_HDMI_HPD"),
+ PINCTRL_PIN(165, "GP68_DSI_A_TE"),
+ PINCTRL_PIN(166, "GP69_DSI_C_TE"),
+ PINCTRL_PIN(167, "OSC_CLK_CTRL0"),
+ PINCTRL_PIN(168, "OSC_CLK_CTRL1"),
+ PINCTRL_PIN(169, "OSC_CLK0"),
+ PINCTRL_PIN(170, "OSC_CLK1"),
+ PINCTRL_PIN(171, "OSC_CLK2"),
+ PINCTRL_PIN(172, "OSC_CLK3"),
+ PINCTRL_PIN(173, "OSC_CLK4"),
+ PINCTRL_PIN(174, "RESETOUT"),
+ PINCTRL_PIN(175, "PMODE"),
+ PINCTRL_PIN(176, "PRDY"),
+ PINCTRL_PIN(177, "PREQ"),
+ PINCTRL_PIN(178, "GP190"),
+ PINCTRL_PIN(179, "GP191"),
+ /* Family 12: MSIC (15 pins) */
+ PINCTRL_PIN(180, "I2C_0_SCL"),
+ PINCTRL_PIN(181, "I2C_0_SDA"),
+ PINCTRL_PIN(182, "IERR"),
+ PINCTRL_PIN(183, "JTAG_TCK"),
+ PINCTRL_PIN(184, "JTAG_TDI"),
+ PINCTRL_PIN(185, "JTAG_TDO"),
+ PINCTRL_PIN(186, "JTAG_TMS"),
+ PINCTRL_PIN(187, "JTAG_TRST"),
+ PINCTRL_PIN(188, "PROCHOT"),
+ PINCTRL_PIN(189, "RTC_CLK"),
+ PINCTRL_PIN(190, "SVID_ALERT"),
+ PINCTRL_PIN(191, "SVID_CLK"),
+ PINCTRL_PIN(192, "SVID_D"),
+ PINCTRL_PIN(193, "THERMTRIP"),
+ PINCTRL_PIN(194, "STANDBY"),
+ /* Family 13: Keyboard (20 pins) */
+ PINCTRL_PIN(195, "GP44"),
+ PINCTRL_PIN(196, "GP45"),
+ PINCTRL_PIN(197, "GP46"),
+ PINCTRL_PIN(198, "GP47"),
+ PINCTRL_PIN(199, "GP48"),
+ PINCTRL_PIN(200, "GP49"),
+ PINCTRL_PIN(201, "GP50"),
+ PINCTRL_PIN(202, "GP51"),
+ PINCTRL_PIN(203, "GP52"),
+ PINCTRL_PIN(204, "GP53"),
+ PINCTRL_PIN(205, "GP54"),
+ PINCTRL_PIN(206, "GP55"),
+ PINCTRL_PIN(207, "GP56"),
+ PINCTRL_PIN(208, "GP57"),
+ PINCTRL_PIN(209, "GP58"),
+ PINCTRL_PIN(210, "GP59"),
+ PINCTRL_PIN(211, "GP60"),
+ PINCTRL_PIN(212, "GP61"),
+ PINCTRL_PIN(213, "GP62"),
+ PINCTRL_PIN(214, "GP63"),
+ /* Family 14: GPIO North (13 pins) */
+ PINCTRL_PIN(215, "GP164"),
+ PINCTRL_PIN(216, "GP165"),
+ PINCTRL_PIN(217, "GP166"),
+ PINCTRL_PIN(218, "GP167"),
+ PINCTRL_PIN(219, "GP168_MJTAG_TCK"),
+ PINCTRL_PIN(220, "GP169_MJTAG_TDI"),
+ PINCTRL_PIN(221, "GP170_MJTAG_TDO"),
+ PINCTRL_PIN(222, "GP171_MJTAG_TMS"),
+ PINCTRL_PIN(223, "GP172_MJTAG_TRST"),
+ PINCTRL_PIN(224, "GP173"),
+ PINCTRL_PIN(225, "GP174"),
+ PINCTRL_PIN(226, "GP175"),
+ PINCTRL_PIN(227, "GP176"),
+ /* Family 15: PTI (5 pins) */
+ PINCTRL_PIN(228, "GP72_PTI_CLK"),
+ PINCTRL_PIN(229, "GP73_PTI_D0"),
+ PINCTRL_PIN(230, "GP74_PTI_D1"),
+ PINCTRL_PIN(231, "GP75_PTI_D2"),
+ PINCTRL_PIN(232, "GP76_PTI_D3"),
+ /* Family 16: USB3 (0 pins) */
+ /* Family 17: HSIC (0 pins) */
+ /* Family 18: Broadcast (0 pins) */
+};
+
+static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 };
+static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 };
+static const unsigned int mrfld_uart0_pins[] = { 124, 125, 126, 127 };
+static const unsigned int mrfld_uart1_pins[] = { 128, 129, 130, 131 };
+static const unsigned int mrfld_uart2_pins[] = { 132, 133, 134, 135 };
+static const unsigned int mrfld_pwm0_pins[] = { 144 };
+static const unsigned int mrfld_pwm1_pins[] = { 145 };
+static const unsigned int mrfld_pwm2_pins[] = { 132 };
+static const unsigned int mrfld_pwm3_pins[] = { 133 };
+
+static const struct intel_pingroup mrfld_groups[] = {
+ PIN_GROUP("sdio_grp", mrfld_sdio_pins, 1),
+ PIN_GROUP("spi5_grp", mrfld_spi5_pins, 1),
+ PIN_GROUP("uart0_grp", mrfld_uart0_pins, 1),
+ PIN_GROUP("uart1_grp", mrfld_uart1_pins, 1),
+ PIN_GROUP("uart2_grp", mrfld_uart2_pins, 1),
+ PIN_GROUP("pwm0_grp", mrfld_pwm0_pins, 1),
+ PIN_GROUP("pwm1_grp", mrfld_pwm1_pins, 1),
+ PIN_GROUP("pwm2_grp", mrfld_pwm2_pins, 1),
+ PIN_GROUP("pwm3_grp", mrfld_pwm3_pins, 1),
+};
+
+static const char * const mrfld_sdio_groups[] = { "sdio_grp" };
+static const char * const mrfld_spi5_groups[] = { "spi5_grp" };
+static const char * const mrfld_uart0_groups[] = { "uart0_grp" };
+static const char * const mrfld_uart1_groups[] = { "uart1_grp" };
+static const char * const mrfld_uart2_groups[] = { "uart2_grp" };
+static const char * const mrfld_pwm0_groups[] = { "pwm0_grp" };
+static const char * const mrfld_pwm1_groups[] = { "pwm1_grp" };
+static const char * const mrfld_pwm2_groups[] = { "pwm2_grp" };
+static const char * const mrfld_pwm3_groups[] = { "pwm3_grp" };
+
+static const struct intel_function mrfld_functions[] = {
+ FUNCTION("sdio", mrfld_sdio_groups),
+ FUNCTION("spi5", mrfld_spi5_groups),
+ FUNCTION("uart0", mrfld_uart0_groups),
+ FUNCTION("uart1", mrfld_uart1_groups),
+ FUNCTION("uart2", mrfld_uart2_groups),
+ FUNCTION("pwm0", mrfld_pwm0_groups),
+ FUNCTION("pwm1", mrfld_pwm1_groups),
+ FUNCTION("pwm2", mrfld_pwm2_groups),
+ FUNCTION("pwm3", mrfld_pwm3_groups),
+};
+
+static const struct mrfld_family mrfld_families[] = {
+ MRFLD_FAMILY(1, 0, 12),
+ MRFLD_FAMILY(2, 13, 36),
+ MRFLD_FAMILY(3, 37, 56),
+ MRFLD_FAMILY(4, 57, 64),
+ MRFLD_FAMILY(5, 65, 78),
+ MRFLD_FAMILY(6, 79, 100),
+ MRFLD_FAMILY_PROTECTED(7, 101, 114),
+ MRFLD_FAMILY(8, 115, 126),
+ MRFLD_FAMILY(9, 127, 145),
+ MRFLD_FAMILY(10, 146, 157),
+ MRFLD_FAMILY(11, 158, 179),
+ MRFLD_FAMILY_PROTECTED(12, 180, 194),
+ MRFLD_FAMILY(13, 195, 214),
+ MRFLD_FAMILY(14, 215, 227),
+ MRFLD_FAMILY(15, 228, 232),
+};
+
+/**
+ * struct mrfld_pinctrl - Intel Merrifield pinctrl private structure
+ * @dev: Pointer to the device structure
+ * @lock: Lock to serialize register access
+ * @pctldesc: Pin controller description
+ * @pctldev: Pointer to the pin controller device
+ * @families: Array of families this pinctrl handles
+ * @nfamilies: Number of families in the array
+ * @functions: Array of functions
+ * @nfunctions: Number of functions in the array
+ * @groups: Array of pin groups
+ * @ngroups: Number of groups in the array
+ * @pins: Array of pins this pinctrl controls
+ * @npins: Number of pins in the array
+ */
+struct mrfld_pinctrl {
+ struct device *dev;
+ raw_spinlock_t lock;
+ struct pinctrl_desc pctldesc;
+ struct pinctrl_dev *pctldev;
+
+ /* Pin controller configuration */
+ const struct mrfld_family *families;
+ size_t nfamilies;
+ const struct intel_function *functions;
+ size_t nfunctions;
+ const struct intel_pingroup *groups;
+ size_t ngroups;
+ const struct pinctrl_pin_desc *pins;
+ size_t npins;
+};
+
+#define pin_to_bufno(f, p) ((p) - (f)->pin_base)
+
+static const struct mrfld_family *mrfld_get_family(struct mrfld_pinctrl *mp,
+ unsigned int pin)
+{
+ const struct mrfld_family *family;
+ unsigned int i;
+
+ for (i = 0; i < mp->nfamilies; i++) {
+ family = &mp->families[i];
+ if (pin >= family->pin_base &&
+ pin < family->pin_base + family->npins)
+ return family;
+ }
+
+ dev_warn(mp->dev, "failed to find family for pin %u\n", pin);
+ return NULL;
+}
+
+static bool mrfld_buf_available(struct mrfld_pinctrl *mp, unsigned int pin)
+{
+ const struct mrfld_family *family;
+
+ family = mrfld_get_family(mp, pin);
+ if (!family)
+ return false;
+
+ return !family->protected;
+}
+
+static void __iomem *mrfld_get_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin)
+{
+ const struct mrfld_family *family;
+ unsigned int bufno;
+
+ family = mrfld_get_family(mp, pin);
+ if (!family)
+ return NULL;
+
+ bufno = pin_to_bufno(family, pin);
+ return family->regs + BUFCFG_OFFSET + bufno * 4;
+}
+
+static int mrfld_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
+
+ return mp->ngroups;
+}
+
+static const char *mrfld_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int group)
+{
+ struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
+
+ return mp->groups[group].name;
+}
+
+static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
+ const unsigned int **pins, unsigned int *npins)
+{
+ struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = mp->groups[group].pins;
+ *npins = mp->groups[group].npins;
+ return 0;
+}
+
+static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+ unsigned int pin)
+{
+ struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
+ void __iomem *bufcfg;
+ u32 value, mode;
+
+ if (!mrfld_buf_available(mp, pin)) {
+ seq_puts(s, "not available");
+ return;
+ }
+
+ bufcfg = mrfld_get_bufcfg(mp, pin);
+ value = readl(bufcfg);
+
+ mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
+ if (!mode)
+ seq_puts(s, "GPIO ");
+ else
+ seq_printf(s, "mode %d ", mode);
+
+ seq_printf(s, "0x%08x", value);
+}
+
+static const struct pinctrl_ops mrfld_pinctrl_ops = {
+ .get_groups_count = mrfld_get_groups_count,
+ .get_group_name = mrfld_get_group_name,
+ .get_group_pins = mrfld_get_group_pins,
+ .pin_dbg_show = mrfld_pin_dbg_show,
+};
+
+static int mrfld_get_functions_count(struct pinctrl_dev *pctldev)
+{
+ struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
+
+ return mp->nfunctions;
+}
+
+static const char *mrfld_get_function_name(struct pinctrl_dev *pctldev,
+ unsigned int function)
+{
+ struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
+
+ return mp->functions[function].name;
+}
+
+static int mrfld_get_function_groups(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ const char * const **groups,
+ unsigned int * const ngroups)
+{
+ struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = mp->functions[function].groups;
+ *ngroups = mp->functions[function].ngroups;
+ return 0;
+}
+
+static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin,
+ u32 bits, u32 mask)
+{
+ void __iomem *bufcfg;
+ u32 value;
+
+ bufcfg = mrfld_get_bufcfg(mp, pin);
+ value = readl(bufcfg);
+
+ value &= ~mask;
+ value |= bits & mask;
+
+ writel(value, bufcfg);
+}
+
+static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ unsigned int group)
+{
+ struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
+ const struct intel_pingroup *grp = &mp->groups[group];
+ u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT;
+ u32 mask = BUFCFG_PINMODE_MASK;
+ unsigned long flags;
+ unsigned int i;
+
+ /*
+ * All pins in the groups needs to be accessible and writable
+ * before we can enable the mux for this group.
+ */
+ for (i = 0; i < grp->npins; i++) {
+ if (!mrfld_buf_available(mp, grp->pins[i]))
+ return -EBUSY;
+ }
+
+ /* Now enable the mux setting for each pin in the group */
+ raw_spin_lock_irqsave(&mp->lock, flags);
+ for (i = 0; i < grp->npins; i++)
+ mrfld_update_bufcfg(mp, grp->pins[i], bits, mask);
+ raw_spin_unlock_irqrestore(&mp->lock, flags);
+
+ return 0;
+}
+
+static int mrfld_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin)
+{
+ struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
+ u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT;
+ u32 mask = BUFCFG_PINMODE_MASK;
+ unsigned long flags;
+
+ if (!mrfld_buf_available(mp, pin))
+ return -EBUSY;
+
+ raw_spin_lock_irqsave(&mp->lock, flags);
+ mrfld_update_bufcfg(mp, pin, bits, mask);
+ raw_spin_unlock_irqrestore(&mp->lock, flags);
+
+ return 0;
+}
+
+static const struct pinmux_ops mrfld_pinmux_ops = {
+ .get_functions_count = mrfld_get_functions_count,
+ .get_function_name = mrfld_get_function_name,
+ .get_function_groups = mrfld_get_function_groups,
+ .set_mux = mrfld_pinmux_set_mux,
+ .gpio_request_enable = mrfld_gpio_request_enable,
+};
+
+static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *config)
+{
+ struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ u32 value, term;
+ u16 arg = 0;
+
+ if (!mrfld_buf_available(mp, pin))
+ return -ENOTSUPP;
+
+ value = readl(mrfld_get_bufcfg(mp, pin));
+ term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (value & BUFCFG_Px_EN_MASK)
+ return -EINVAL;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN)
+ return -EINVAL;
+
+ switch (term) {
+ case BUFCFG_PUPD_VAL_910:
+ arg = 910;
+ break;
+ case BUFCFG_PUPD_VAL_2K:
+ arg = 2000;
+ break;
+ case BUFCFG_PUPD_VAL_20K:
+ arg = 20000;
+ break;
+ case BUFCFG_PUPD_VAL_50K:
+ arg = 50000;
+ break;
+ }
+
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN)
+ return -EINVAL;
+
+ switch (term) {
+ case BUFCFG_PUPD_VAL_910:
+ arg = 910;
+ break;
+ case BUFCFG_PUPD_VAL_2K:
+ arg = 2000;
+ break;
+ case BUFCFG_PUPD_VAL_20K:
+ arg = 20000;
+ break;
+ case BUFCFG_PUPD_VAL_50K:
+ arg = 50000;
+ break;
+ }
+
+ break;
+
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ if (!(value & BUFCFG_OD_EN))
+ return -EINVAL;
+ break;
+
+ case PIN_CONFIG_SLEW_RATE:
+ if (!(value & BUFCFG_SLEWSEL))
+ arg = 0;
+ else
+ arg = 1;
+ break;
+
+ default:
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, arg);
+ return 0;
+}
+
+static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin,
+ unsigned long config)
+{
+ unsigned int param = pinconf_to_config_param(config);
+ unsigned int arg = pinconf_to_config_argument(config);
+ u32 bits = 0, mask = 0;
+ unsigned long flags;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
+ bits |= BUFCFG_PU_EN;
+
+ switch (arg) {
+ case 50000:
+ bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
+ break;
+ case 20000:
+ bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
+ break;
+ case 2000:
+ bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
+ bits |= BUFCFG_PD_EN;
+
+ switch (arg) {
+ case 50000:
+ bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
+ break;
+ case 20000:
+ bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
+ break;
+ case 2000:
+ bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ break;
+
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ mask |= BUFCFG_OD_EN;
+ if (arg)
+ bits |= BUFCFG_OD_EN;
+ break;
+
+ case PIN_CONFIG_SLEW_RATE:
+ mask |= BUFCFG_SLEWSEL;
+ if (arg)
+ bits |= BUFCFG_SLEWSEL;
+ break;
+ }
+
+ raw_spin_lock_irqsave(&mp->lock, flags);
+ mrfld_update_bufcfg(mp, pin, bits, mask);
+ raw_spin_unlock_irqrestore(&mp->lock, flags);
+
+ return 0;
+}
+
+static int mrfld_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *configs, unsigned int nconfigs)
+{
+ struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
+ unsigned int i;
+ int ret;
+
+ for (i = 0; i < nconfigs; i++) {
+ switch (pinconf_to_config_param(configs[i])) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ case PIN_CONFIG_SLEW_RATE:
+ ret = mrfld_config_set_pin(mp, pin, configs[i]);
+ if (ret)
+ return ret;
+ break;
+
+ default:
+ return -ENOTSUPP;
+ }
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops mrfld_pinconf_ops = {
+ .is_generic = true,
+ .pin_config_get = mrfld_config_get,
+ .pin_config_set = mrfld_config_set,
+};
+
+static const struct pinctrl_desc mrfld_pinctrl_desc = {
+ .pctlops = &mrfld_pinctrl_ops,
+ .pmxops = &mrfld_pinmux_ops,
+ .confops = &mrfld_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static int mrfld_pinctrl_probe(struct platform_device *pdev)
+{
+ struct mrfld_family *families;
+ struct mrfld_pinctrl *mp;
+ struct resource *mem;
+ void __iomem *regs;
+ size_t nfamilies;
+ unsigned int i;
+
+ mp = devm_kzalloc(&pdev->dev, sizeof(*mp), GFP_KERNEL);
+ if (!mp)
+ return -ENOMEM;
+
+ mp->dev = &pdev->dev;
+ raw_spin_lock_init(&mp->lock);
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ regs = devm_ioremap_resource(&pdev->dev, mem);
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ /*
+ * Make a copy of the families which we can use to hold pointers
+ * to the registers.
+ */
+ nfamilies = ARRAY_SIZE(mrfld_families),
+ families = devm_kmemdup(&pdev->dev, mrfld_families,
+ nfamilies * sizeof(mrfld_families),
+ GFP_KERNEL);
+ if (!families)
+ return -ENOMEM;
+
+ /* Splice memory resource by chunk per family */
+ for (i = 0; i < nfamilies; i++) {
+ struct mrfld_family *family = &families[i];
+
+ family->regs = regs + family->barno * MRFLD_FAMILY_LEN;
+ }
+
+ mp->families = families;
+ mp->nfamilies = nfamilies;
+ mp->functions = mrfld_functions;
+ mp->nfunctions = ARRAY_SIZE(mrfld_functions);
+ mp->groups = mrfld_groups;
+ mp->ngroups = ARRAY_SIZE(mrfld_groups);
+ mp->pctldesc = mrfld_pinctrl_desc;
+ mp->pctldesc.name = dev_name(&pdev->dev);
+ mp->pctldesc.pins = mrfld_pins;
+ mp->pctldesc.npins = ARRAY_SIZE(mrfld_pins);
+
+ mp->pctldev = devm_pinctrl_register(&pdev->dev, &mp->pctldesc, mp);
+ if (IS_ERR(mp->pctldev)) {
+ dev_err(&pdev->dev, "failed to register pinctrl driver\n");
+ return PTR_ERR(mp->pctldev);
+ }
+
+ platform_set_drvdata(pdev, mp);
+ return 0;
+}
+
+static struct platform_driver mrfld_pinctrl_driver = {
+ .probe = mrfld_pinctrl_probe,
+ .driver = {
+ .name = "pinctrl-merrifield",
+ },
+};
+
+static int __init mrfld_pinctrl_init(void)
+{
+ return platform_driver_register(&mrfld_pinctrl_driver);
+}
+subsys_initcall(mrfld_pinctrl_init);
+
+static void __exit mrfld_pinctrl_exit(void)
+{
+ platform_driver_unregister(&mrfld_pinctrl_driver);
+}
+module_exit(mrfld_pinctrl_exit);
+
+MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
+MODULE_DESCRIPTION("Intel Merrifield SoC pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:pinctrl-merrifield");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index a607655d7830..ce554e0d6979 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -1183,8 +1183,8 @@ static int mtk_eint_resume(struct device *device)
}
const struct dev_pm_ops mtk_eint_pm_ops = {
- .suspend = mtk_eint_suspend,
- .resume = mtk_eint_resume,
+ .suspend_noirq = mtk_eint_suspend,
+ .resume_noirq = mtk_eint_resume,
};
static void mtk_eint_ack(struct irq_data *d)
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index eeabafbbf598..cb4d6ad30530 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -147,6 +147,52 @@ static const struct pinctrl_pin_desc meson_gxbb_periphs_pins[] = {
MESON_PIN(GPIO_TEST_N, EE_OFF),
};
+static const unsigned int emmc_nand_d07_pins[] = {
+ PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF),
+ PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF),
+ PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF),
+};
+static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
+static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
+static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
+
+static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };
+static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };
+static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };
+static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) };
+static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) };
+static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) };
+
+static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) };
+static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) };
+static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_14, EE_OFF) };
+static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_15, EE_OFF) };
+
+static const unsigned int uart_tx_b_pins[] = { PIN(GPIODV_24, EE_OFF) };
+static const unsigned int uart_rx_b_pins[] = { PIN(GPIODV_25, EE_OFF) };
+static const unsigned int uart_cts_b_pins[] = { PIN(GPIODV_26, EE_OFF) };
+static const unsigned int uart_rts_b_pins[] = { PIN(GPIODV_27, EE_OFF) };
+
+static const unsigned int uart_tx_c_pins[] = { PIN(GPIOY_13, EE_OFF) };
+static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_14, EE_OFF) };
+static const unsigned int uart_cts_c_pins[] = { PIN(GPIOX_11, EE_OFF) };
+static const unsigned int uart_rts_c_pins[] = { PIN(GPIOX_12, EE_OFF) };
+
+static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_0, EE_OFF) };
+static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_1, EE_OFF) };
+static const unsigned int eth_clk_rx_clk_pins[] = { PIN(GPIOZ_2, EE_OFF) };
+static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_3, EE_OFF) };
+static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_4, EE_OFF) };
+static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_5, EE_OFF) };
+static const unsigned int eth_rxd2_pins[] = { PIN(GPIOZ_6, EE_OFF) };
+static const unsigned int eth_rxd3_pins[] = { PIN(GPIOZ_7, EE_OFF) };
+static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOZ_8, EE_OFF) };
+static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_9, EE_OFF) };
+static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_10, EE_OFF) };
+static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_11, EE_OFF) };
+static const unsigned int eth_txd2_pins[] = { PIN(GPIOZ_12, EE_OFF) };
+static const unsigned int eth_txd3_pins[] = { PIN(GPIOZ_13, EE_OFF) };
+
static const struct pinctrl_pin_desc meson_gxbb_aobus_pins[] = {
MESON_PIN(GPIOAO_0, 0),
MESON_PIN(GPIOAO_1, 0),
@@ -168,6 +214,16 @@ static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, 0) };
static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, 0) };
static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, 0) };
static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, 0) };
+static const unsigned int uart_tx_ao_b_pins[] = { PIN(GPIOAO_0, 0) };
+static const unsigned int uart_rx_ao_b_pins[] = { PIN(GPIOAO_1, 0),
+ PIN(GPIOAO_5, 0) };
+static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, 0) };
+static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) };
+
+static const unsigned int i2c_sck_ao_pins[] = {PIN(GPIOAO_4, 0) };
+static const unsigned int i2c_sda_ao_pins[] = {PIN(GPIOAO_5, 0) };
+static const unsigned int i2c_slave_sck_ao_pins[] = {PIN(GPIOAO_4, 0) };
+static const unsigned int i2c_slave_sda_ao_pins[] = {PIN(GPIOAO_5, 0) };
static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
GPIO_GROUP(GPIOZ_0, EE_OFF),
@@ -297,6 +353,54 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
GPIO_GROUP(GPIOCLK_3, EE_OFF),
GPIO_GROUP(GPIO_TEST_N, EE_OFF),
+
+ /* Bank X */
+ GROUP(uart_tx_a, 4, 13),
+ GROUP(uart_rx_a, 4, 12),
+ GROUP(uart_cts_a, 4, 11),
+ GROUP(uart_rts_a, 4, 10),
+
+ /* Bank Y */
+ GROUP(uart_cts_c, 1, 19),
+ GROUP(uart_rts_c, 1, 18),
+ GROUP(uart_tx_c, 1, 17),
+ GROUP(uart_rx_c, 1, 16),
+
+ /* Bank Z */
+ GROUP(eth_mdio, 6, 1),
+ GROUP(eth_mdc, 6, 0),
+ GROUP(eth_clk_rx_clk, 6, 13),
+ GROUP(eth_rx_dv, 6, 12),
+ GROUP(eth_rxd0, 6, 11),
+ GROUP(eth_rxd1, 6, 10),
+ GROUP(eth_rxd2, 6, 9),
+ GROUP(eth_rxd3, 6, 8),
+ GROUP(eth_rgmii_tx_clk, 6, 7),
+ GROUP(eth_tx_en, 6, 6),
+ GROUP(eth_txd0, 6, 5),
+ GROUP(eth_txd1, 6, 4),
+ GROUP(eth_txd2, 6, 3),
+ GROUP(eth_txd3, 6, 2),
+
+ /* Bank DV */
+ GROUP(uart_tx_b, 2, 29),
+ GROUP(uart_rx_b, 2, 28),
+ GROUP(uart_cts_b, 2, 27),
+ GROUP(uart_rts_b, 2, 26),
+
+ /* Bank BOOT */
+ GROUP(emmc_nand_d07, 4, 30),
+ GROUP(emmc_clk, 4, 18),
+ GROUP(emmc_cmd, 4, 19),
+ GROUP(emmc_ds, 4, 31),
+
+ /* Bank CARD */
+ GROUP(sdcard_d1, 2, 14),
+ GROUP(sdcard_d0, 2, 15),
+ GROUP(sdcard_d3, 2, 12),
+ GROUP(sdcard_d2, 2, 13),
+ GROUP(sdcard_cmd, 2, 10),
+ GROUP(sdcard_clk, 2, 11),
};
static struct meson_pmx_group meson_gxbb_aobus_groups[] = {
@@ -316,10 +420,18 @@ static struct meson_pmx_group meson_gxbb_aobus_groups[] = {
GPIO_GROUP(GPIOAO_13, 0),
/* bank AO */
+ GROUP(uart_tx_ao_b, 0, 26),
+ GROUP(uart_rx_ao_b, 0, 25),
GROUP(uart_tx_ao_a, 0, 12),
GROUP(uart_rx_ao_a, 0, 11),
GROUP(uart_cts_ao_a, 0, 10),
GROUP(uart_rts_ao_a, 0, 9),
+ GROUP(uart_cts_ao_b, 0, 8),
+ GROUP(uart_rts_ao_b, 0, 7),
+ GROUP(i2c_sck_ao, 0, 6),
+ GROUP(i2c_sda_ao, 0, 5),
+ GROUP(i2c_slave_sck_ao, 0, 2),
+ GROUP(i2c_slave_sda_ao, 0, 1),
};
static const char * const gpio_periphs_groups[] = {
@@ -359,6 +471,34 @@ static const char * const gpio_periphs_groups[] = {
"GPIO_TEST_N",
};
+static const char * const emmc_groups[] = {
+ "emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
+};
+
+static const char * const sdcard_groups[] = {
+ "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
+ "sdcard_cmd", "sdcard_clk",
+};
+
+static const char * const uart_a_groups[] = {
+ "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
+};
+
+static const char * const uart_b_groups[] = {
+ "uart_tx_b", "uart_rx_b", "uart_cts_b", "uart_rts_b",
+};
+
+static const char * const uart_c_groups[] = {
+ "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c",
+};
+
+static const char * const eth_groups[] = {
+ "eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv",
+ "eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3",
+ "eth_rgmii_tx_clk", "eth_tx_en",
+ "eth_txd0", "eth_txd1", "eth_txd2", "eth_txd3",
+};
+
static const char * const gpio_aobus_groups[] = {
"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
@@ -366,16 +506,37 @@ static const char * const gpio_aobus_groups[] = {
};
static const char * const uart_ao_groups[] = {
- "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a"
+ "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a",
+};
+
+static const char * const uart_ao_b_groups[] = {
+ "uart_tx_ao_b", "uart_rx_ao_b", "uart_cts_ao_b", "uart_rts_ao_b",
+};
+
+static const char * const i2c_ao_groups[] = {
+ "i2c_sdk_ao", "i2c_sda_ao",
+};
+
+static const char * const i2c_slave_ao_groups[] = {
+ "i2c_slave_sdk_ao", "i2c_slave_sda_ao",
};
static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
FUNCTION(gpio_periphs),
+ FUNCTION(emmc),
+ FUNCTION(sdcard),
+ FUNCTION(uart_a),
+ FUNCTION(uart_b),
+ FUNCTION(uart_c),
+ FUNCTION(eth),
};
static struct meson_pmx_func meson_gxbb_aobus_functions[] = {
FUNCTION(gpio_aobus),
FUNCTION(uart_ao),
+ FUNCTION(uart_ao_b),
+ FUNCTION(i2c_ao),
+ FUNCTION(i2c_slave_ao),
};
static struct meson_bank meson_gxbb_periphs_banks[] = {
diff --git a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
index a78e9a4997ba..5f89c26f3292 100644
--- a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
+++ b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
@@ -168,87 +168,87 @@ static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "nand", "io1", V(1, 1, 1, 1, 1, 1))),
MPP_MODE(20,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "txd0", V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d0", V(0, 0, 0, 0, 1, 0)),
- MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(1, 0, 0, 0, 0, 0))),
+ MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(0, 0, 0, 0, 0, 0))),
MPP_MODE(21,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "txd1", V(0, 1, 1, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d1", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(22,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "txd2", V(0, 1, 1, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d2", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(23,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "txd3", V(0, 1, 1, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(1, 0, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d3", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(24,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "rxd0", V(0, 1, 1, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(1, 0, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d4", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(25,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "rxd1", V(0, 1, 1, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(1, 0, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d5", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(26,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "rxd2", V(0, 1, 1, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(1, 0, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d6", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(27,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "rxd3", V(0, 1, 1, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(1, 0, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d7", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(28,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "col", V(0, 1, 1, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(1, 0, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d8", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(29,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "txclk", V(0, 1, 1, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 0, 0, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 0, 0, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d9", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(30,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)),
@@ -280,65 +280,65 @@ static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d14", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(35,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)),
MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x3, "ge1", "rxerr", V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d15", V(0, 0, 0, 0, 1, 0)),
- MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(0, 1, 1, 1, 1, 0))),
+ MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(1, 1, 1, 1, 1, 0))),
MPP_MODE(36,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 0, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "twsi1", "sda", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(37,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 0, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "twsi1", "sck", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(38,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 0, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 0, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(1, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d18", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(39,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 0, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 0, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(1, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d19", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(40,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 0, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 0, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(1, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d20", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(41,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 0, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(1, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d21", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(42,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 0, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(1, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d22", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(43,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 0, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 0, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(1, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "d23", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(44,
- MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
+ MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 0, 0, 1, 1, 1)),
MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 0, 1, 1, 0)),
- MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 1, 1, 0)),
+ MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 1, 1, 0)),
MPP_VAR_FUNCTION(0xb, "lcd", "clk", V(0, 0, 0, 0, 1, 0))),
MPP_MODE(45,
MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)),
@@ -371,11 +371,12 @@ static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
};
static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = {
- MPP_FUNC_CTRL(0, 29, NULL, kirkwood_mpp_ctrl),
+ MPP_FUNC_CTRL(0, 44, NULL, kirkwood_mpp_ctrl),
};
static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = {
- MPP_GPIO_RANGE(0, 0, 0, 30),
+ MPP_GPIO_RANGE(0, 0, 0, 20),
+ MPP_GPIO_RANGE(1, 35, 35, 10),
};
static struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = {
diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
index 38faceff2f08..35f62180db4e 100644
--- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c
+++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c
@@ -1033,102 +1033,6 @@ static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
#define nmk_gpio_dbg_show NULL
#endif
-void nmk_gpio_clocks_enable(void)
-{
- int i;
-
- for (i = 0; i < NUM_BANKS; i++) {
- struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
-
- if (!chip)
- continue;
-
- clk_enable(chip->clk);
- }
-}
-
-void nmk_gpio_clocks_disable(void)
-{
- int i;
-
- for (i = 0; i < NUM_BANKS; i++) {
- struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
-
- if (!chip)
- continue;
-
- clk_disable(chip->clk);
- }
-}
-
-/*
- * Called from the suspend/resume path to only keep the real wakeup interrupts
- * (those that have had set_irq_wake() called on them) as wakeup interrupts,
- * and not the rest of the interrupts which we needed to have as wakeups for
- * cpuidle.
- *
- * PM ops are not used since this needs to be done at the end, after all the
- * other drivers are done with their suspend callbacks.
- */
-void nmk_gpio_wakeups_suspend(void)
-{
- int i;
-
- for (i = 0; i < NUM_BANKS; i++) {
- struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
-
- if (!chip)
- break;
-
- clk_enable(chip->clk);
-
- writel(chip->rwimsc & chip->real_wake,
- chip->addr + NMK_GPIO_RWIMSC);
- writel(chip->fwimsc & chip->real_wake,
- chip->addr + NMK_GPIO_FWIMSC);
-
- clk_disable(chip->clk);
- }
-}
-
-void nmk_gpio_wakeups_resume(void)
-{
- int i;
-
- for (i = 0; i < NUM_BANKS; i++) {
- struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
-
- if (!chip)
- break;
-
- clk_enable(chip->clk);
-
- writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
- writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
-
- clk_disable(chip->clk);
- }
-}
-
-/*
- * Read the pull up/pull down status.
- * A bit set in 'pull_up' means that pull up
- * is selected if pull is enabled in PDIS register.
- * Note: only pull up/down set via this driver can
- * be detected due to HW limitations.
- */
-void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
-{
- if (gpio_bank < NUM_BANKS) {
- struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
-
- if (!chip)
- return;
-
- *pull_up = chip->pull_up;
- }
-}
-
/*
* We will allocate memory for the state container using devm* allocators
* binding to the first device reaching this point, it doesn't matter if
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
index d5bf9fae2ddd..5020ae534479 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -53,7 +53,7 @@ static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev,
struct seq_file *s, const char *gname,
unsigned pin,
const struct pin_config_item *items,
- int nitems)
+ int nitems, int *print_sep)
{
int i;
@@ -75,8 +75,10 @@ static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev,
seq_printf(s, "ERROR READING CONFIG SETTING %d ", i);
continue;
}
- /* Space between multiple configs */
- seq_puts(s, " ");
+ /* comma between multiple configs */
+ if (*print_sep)
+ seq_puts(s, ", ");
+ *print_sep = 1;
seq_puts(s, items[i].display);
/* Print unit if available */
if (items[i].has_arg) {
@@ -105,19 +107,21 @@ void pinconf_generic_dump_pins(struct pinctrl_dev *pctldev, struct seq_file *s,
const char *gname, unsigned pin)
{
const struct pinconf_ops *ops = pctldev->desc->confops;
+ int print_sep = 0;
if (!ops->is_generic)
return;
/* generic parameters */
pinconf_generic_dump_one(pctldev, s, gname, pin, conf_items,
- ARRAY_SIZE(conf_items));
+ ARRAY_SIZE(conf_items), &print_sep);
/* driver-specific parameters */
if (pctldev->desc->num_custom_params &&
pctldev->desc->custom_conf_items)
pinconf_generic_dump_one(pctldev, s, gname, pin,
pctldev->desc->custom_conf_items,
- pctldev->desc->num_custom_params);
+ pctldev->desc->num_custom_params,
+ &print_sep);
}
void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
@@ -391,4 +395,12 @@ exit:
}
EXPORT_SYMBOL_GPL(pinconf_generic_dt_node_to_map);
+void pinconf_generic_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map,
+ unsigned num_maps)
+{
+ pinctrl_utils_free_map(pctldev, map, num_maps);
+}
+EXPORT_SYMBOL_GPL(pinconf_generic_dt_free_map);
+
#endif
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index 4dd7722f9935..799048f3c8d4 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -258,8 +258,7 @@ void pinconf_show_setting(struct seq_file *s,
case PIN_MAP_TYPE_CONFIGS_PIN:
desc = pin_desc_get(setting->pctldev,
setting->data.configs.group_or_pin);
- seq_printf(s, "pin %s (%d)",
- desc->name ? desc->name : "unnamed",
+ seq_printf(s, "pin %s (%d)", desc->name,
setting->data.configs.group_or_pin);
break;
case PIN_MAP_TYPE_CONFIGS_GROUP:
@@ -311,8 +310,7 @@ static int pinconf_pins_show(struct seq_file *s, void *what)
if (desc == NULL)
continue;
- seq_printf(s, "pin %d (%s):", pin,
- desc->name ? desc->name : "unnamed");
+ seq_printf(s, "pin %d (%s): ", pin, desc->name);
pinconf_dump_pin(pctldev, s, pin);
@@ -349,7 +347,7 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
while (selector < ngroups) {
const char *gname = pctlops->get_group_name(pctldev, selector);
- seq_printf(s, "%u (%s):", selector, gname);
+ seq_printf(s, "%u (%s): ", selector, gname);
pinconf_dump_group(pctldev, s, selector, gname);
seq_printf(s, "\n");
diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
index a025b40d246b..28bbc1bb9e6c 100644
--- a/drivers/pinctrl/pinctrl-at91-pio4.c
+++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -20,7 +20,7 @@
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/io.h>
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinconf.h>
@@ -421,8 +421,8 @@ static int atmel_pctl_get_group_pins(struct pinctrl_dev *pctldev,
return 0;
}
-struct atmel_group *atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev,
- unsigned pin)
+static struct atmel_group *
+atmel_pctl_find_group_by_pin(struct pinctrl_dev *pctldev, unsigned pin)
{
struct atmel_pioctrl *atmel_pioctrl = pinctrl_dev_get_drvdata(pctldev);
int i;
@@ -879,7 +879,6 @@ static const struct of_device_id atmel_pctrl_of_match[] = {
/* sentinel */
}
};
-MODULE_DEVICE_TABLE(of, atmel_pctrl_of_match);
static int atmel_pinctrl_probe(struct platform_device *pdev)
{
@@ -1074,28 +1073,13 @@ clk_prepare_enable_error:
return ret;
}
-int atmel_pinctrl_remove(struct platform_device *pdev)
-{
- struct atmel_pioctrl *atmel_pioctrl = platform_get_drvdata(pdev);
-
- irq_domain_remove(atmel_pioctrl->irq_domain);
- clk_disable_unprepare(atmel_pioctrl->clk);
- gpiochip_remove(atmel_pioctrl->gpio_chip);
-
- return 0;
-}
-
static struct platform_driver atmel_pinctrl_driver = {
.driver = {
.name = "pinctrl-at91-pio4",
.of_match_table = atmel_pctrl_of_match,
.pm = &atmel_pctrl_pm_ops,
+ .suppress_bind_attrs = true,
},
.probe = atmel_pinctrl_probe,
- .remove = atmel_pinctrl_remove,
};
-module_platform_driver(atmel_pinctrl_driver);
-
-MODULE_AUTHOR(Ludovic Desroches <ludovic.desroches@atmel.com>);
-MODULE_DESCRIPTION("Atmel PIO4 pinctrl driver");
-MODULE_LICENSE("GPL v2");
+builtin_platform_driver(atmel_pinctrl_driver);
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index b7c0d6f7c046..80daead3a5a1 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -9,7 +9,6 @@
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/init.h>
-#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
@@ -189,7 +188,7 @@ struct at91_pinctrl {
struct at91_pinctrl_mux_ops *ops;
};
-static const inline struct at91_pin_group *at91_pinctrl_find_group_by_name(
+static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name(
const struct at91_pinctrl *info,
const char *name)
{
@@ -1818,13 +1817,3 @@ static int __init at91_pinctrl_init(void)
return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
}
arch_initcall(at91_pinctrl_init);
-
-static void __exit at91_pinctrl_exit(void)
-{
- platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
-}
-
-module_exit(at91_pinctrl_exit);
-MODULE_AUTHOR("Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>");
-MODULE_DESCRIPTION("Atmel AT91 pinctrl driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-digicolor.c b/drivers/pinctrl/pinctrl-digicolor.c
index 30ee56427f56..639a57ecc7c2 100644
--- a/drivers/pinctrl/pinctrl-digicolor.c
+++ b/drivers/pinctrl/pinctrl-digicolor.c
@@ -15,7 +15,7 @@
* - Pin pad configuration (pull up/down, strength)
*/
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
@@ -335,27 +335,17 @@ static int dc_pinctrl_probe(struct platform_device *pdev)
return dc_gpiochip_add(pmap, pdev->dev.of_node);
}
-static int dc_pinctrl_remove(struct platform_device *pdev)
-{
- struct dc_pinmap *pmap = platform_get_drvdata(pdev);
-
- gpiochip_remove(&pmap->chip);
-
- return 0;
-}
-
static const struct of_device_id dc_pinctrl_ids[] = {
{ .compatible = "cnxt,cx92755-pinctrl" },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, dc_pinctrl_ids);
static struct platform_driver dc_pinctrl_driver = {
.driver = {
.name = DRIVER_NAME,
.of_match_table = dc_pinctrl_ids,
+ .suppress_bind_attrs = true,
},
.probe = dc_pinctrl_probe,
- .remove = dc_pinctrl_remove,
};
-module_platform_driver(dc_pinctrl_driver);
+builtin_platform_driver(dc_pinctrl_driver);
diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c
index 8a931c7ba2ff..e053f1fa5512 100644
--- a/drivers/pinctrl/pinctrl-lpc18xx.c
+++ b/drivers/pinctrl/pinctrl-lpc18xx.c
@@ -11,7 +11,7 @@
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/io.h>
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -1365,31 +1365,17 @@ static int lpc18xx_scu_probe(struct platform_device *pdev)
return 0;
}
-static int lpc18xx_scu_remove(struct platform_device *pdev)
-{
- struct lpc18xx_scu_data *scu = platform_get_drvdata(pdev);
-
- clk_disable_unprepare(scu->clk);
-
- return 0;
-}
-
static const struct of_device_id lpc18xx_scu_match[] = {
{ .compatible = "nxp,lpc1850-scu" },
{},
};
-MODULE_DEVICE_TABLE(of, lpc18xx_scu_match);
static struct platform_driver lpc18xx_scu_driver = {
.probe = lpc18xx_scu_probe,
- .remove = lpc18xx_scu_remove,
.driver = {
.name = "lpc18xx-scu",
.of_match_table = lpc18xx_scu_match,
+ .suppress_bind_attrs = true,
},
};
-module_platform_driver(lpc18xx_scu_driver);
-
-MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
-MODULE_DESCRIPTION("Pinctrl driver for NXP LPC18xx/43xx SCU");
-MODULE_LICENSE("GPL v2");
+builtin_platform_driver(lpc18xx_scu_driver);
diff --git a/drivers/pinctrl/pinctrl-max77620.c b/drivers/pinctrl/pinctrl-max77620.c
new file mode 100644
index 000000000000..d9ff53e8f715
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-max77620.c
@@ -0,0 +1,673 @@
+/*
+ * MAX77620 pin control driver.
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author:
+ * Chaitanya Bandi <bandik@nvidia.com>
+ * Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#include <linux/mfd/max77620.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include "core.h"
+#include "pinconf.h"
+#include "pinctrl-utils.h"
+
+#define MAX77620_PIN_NUM 8
+
+enum max77620_pin_ppdrv {
+ MAX77620_PIN_UNCONFIG_DRV,
+ MAX77620_PIN_OD_DRV,
+ MAX77620_PIN_PP_DRV,
+};
+
+enum max77620_pinconf_param {
+ MAX77620_ACTIVE_FPS_SOURCE = PIN_CONFIG_END + 1,
+ MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
+ MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
+ MAX77620_SUSPEND_FPS_SOURCE,
+ MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
+ MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
+};
+
+struct max77620_pin_function {
+ const char *name;
+ const char * const *groups;
+ unsigned int ngroups;
+ int mux_option;
+};
+
+static const struct pinconf_generic_params max77620_cfg_params[] = {
+ {
+ .property = "maxim,active-fps-source",
+ .param = MAX77620_ACTIVE_FPS_SOURCE,
+ }, {
+ .property = "maxim,active-fps-power-up-slot",
+ .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
+ }, {
+ .property = "maxim,active-fps-power-down-slot",
+ .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
+ }, {
+ .property = "maxim,suspend-fps-source",
+ .param = MAX77620_SUSPEND_FPS_SOURCE,
+ }, {
+ .property = "maxim,suspend-fps-power-up-slot",
+ .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
+ }, {
+ .property = "maxim,suspend-fps-power-down-slot",
+ .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
+ },
+};
+
+enum max77620_alternate_pinmux_option {
+ MAX77620_PINMUX_GPIO = 0,
+ MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1,
+ MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2,
+ MAX77620_PINMUX_32K_OUT1 = 3,
+ MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4,
+ MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5,
+ MAX77620_PINMUX_REFERENCE_OUT = 6,
+};
+
+struct max77620_pingroup {
+ const char *name;
+ const unsigned int pins[1];
+ unsigned int npins;
+ enum max77620_alternate_pinmux_option alt_option;
+};
+
+struct max77620_pin_info {
+ enum max77620_pin_ppdrv drv_type;
+ int pull_config;
+};
+
+struct max77620_fps_config {
+ int active_fps_src;
+ int active_power_up_slots;
+ int active_power_down_slots;
+ int suspend_fps_src;
+ int suspend_power_up_slots;
+ int suspend_power_down_slots;
+};
+
+struct max77620_pctrl_info {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ struct regmap *rmap;
+ int pins_current_opt[MAX77620_GPIO_NR];
+ const struct max77620_pin_function *functions;
+ unsigned int num_functions;
+ const struct max77620_pingroup *pin_groups;
+ int num_pin_groups;
+ const struct pinctrl_pin_desc *pins;
+ unsigned int num_pins;
+ struct max77620_pin_info pin_info[MAX77620_PIN_NUM];
+ struct max77620_fps_config fps_config[MAX77620_PIN_NUM];
+};
+
+static const struct pinctrl_pin_desc max77620_pins_desc[] = {
+ PINCTRL_PIN(MAX77620_GPIO0, "gpio0"),
+ PINCTRL_PIN(MAX77620_GPIO1, "gpio1"),
+ PINCTRL_PIN(MAX77620_GPIO2, "gpio2"),
+ PINCTRL_PIN(MAX77620_GPIO3, "gpio3"),
+ PINCTRL_PIN(MAX77620_GPIO4, "gpio4"),
+ PINCTRL_PIN(MAX77620_GPIO5, "gpio5"),
+ PINCTRL_PIN(MAX77620_GPIO6, "gpio6"),
+ PINCTRL_PIN(MAX77620_GPIO7, "gpio7"),
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0",
+ "gpio1",
+ "gpio2",
+ "gpio3",
+ "gpio4",
+ "gpio5",
+ "gpio6",
+ "gpio7",
+};
+
+#define FUNCTION_GROUP(fname, mux) \
+ { \
+ .name = fname, \
+ .groups = gpio_groups, \
+ .ngroups = ARRAY_SIZE(gpio_groups), \
+ .mux_option = MAX77620_PINMUX_##mux, \
+ }
+
+static const struct max77620_pin_function max77620_pin_function[] = {
+ FUNCTION_GROUP("gpio", GPIO),
+ FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN),
+ FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT),
+ FUNCTION_GROUP("32k-out1", 32K_OUT1),
+ FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN),
+ FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN),
+ FUNCTION_GROUP("reference-out", REFERENCE_OUT),
+};
+
+#define MAX77620_PINGROUP(pg_name, pin_id, option) \
+ { \
+ .name = #pg_name, \
+ .pins = {MAX77620_##pin_id}, \
+ .npins = 1, \
+ .alt_option = MAX77620_PINMUX_##option, \
+ }
+
+static const struct max77620_pingroup max77620_pingroups[] = {
+ MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN),
+ MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT),
+ MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT),
+ MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT),
+ MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1),
+ MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN),
+ MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN),
+ MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT),
+};
+
+static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ return mpci->num_pin_groups;
+}
+
+static const char *max77620_pinctrl_get_group_name(
+ struct pinctrl_dev *pctldev, unsigned int group)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ return mpci->pin_groups[group].name;
+}
+
+static int max77620_pinctrl_get_group_pins(
+ struct pinctrl_dev *pctldev, unsigned int group,
+ const unsigned int **pins, unsigned int *num_pins)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = mpci->pin_groups[group].pins;
+ *num_pins = mpci->pin_groups[group].npins;
+
+ return 0;
+}
+
+static const struct pinctrl_ops max77620_pinctrl_ops = {
+ .get_groups_count = max77620_pinctrl_get_groups_count,
+ .get_group_name = max77620_pinctrl_get_group_name,
+ .get_group_pins = max77620_pinctrl_get_group_pins,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+ .dt_free_map = pinctrl_utils_free_map,
+};
+
+static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ return mpci->num_functions;
+}
+
+static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned int function)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ return mpci->functions[function].name;
+}
+
+static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ const char * const **groups,
+ unsigned int * const num_groups)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = mpci->functions[function].groups;
+ *num_groups = mpci->functions[function].ngroups;
+
+ return 0;
+}
+
+static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev,
+ unsigned int function, unsigned int group)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+ u8 val;
+ int ret;
+
+ if (function == MAX77620_PINMUX_GPIO) {
+ val = 0;
+ } else if (function == mpci->pin_groups[group].alt_option) {
+ val = 1 << group;
+ } else {
+ dev_err(mpci->dev, "GPIO %u doesn't have function %u\n",
+ group, function);
+ return -EINVAL;
+ }
+ ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO,
+ BIT(group), val);
+ if (ret < 0)
+ dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret);
+
+ return ret;
+}
+
+static const struct pinmux_ops max77620_pinmux_ops = {
+ .get_functions_count = max77620_pinctrl_get_funcs_count,
+ .get_function_name = max77620_pinctrl_get_func_name,
+ .get_function_groups = max77620_pinctrl_get_func_groups,
+ .set_mux = max77620_pinctrl_enable,
+};
+
+static int max77620_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *config)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+ struct device *dev = mpci->dev;
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ unsigned int val;
+ int arg = 0;
+ int ret;
+
+ switch (param) {
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV)
+ arg = 1;
+ break;
+
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV)
+ arg = 1;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val);
+ if (ret < 0) {
+ dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret);
+ return ret;
+ }
+ if (val & BIT(pin))
+ arg = 1;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val);
+ if (ret < 0) {
+ dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret);
+ return ret;
+ }
+ if (val & BIT(pin))
+ arg = 1;
+ break;
+
+ default:
+ dev_err(dev, "Properties not supported\n");
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, (u16)arg);
+
+ return 0;
+}
+
+static int max77620_get_default_fps(struct max77620_pctrl_info *mpci,
+ int addr, int *fps)
+{
+ unsigned int val;
+ int ret;
+
+ ret = regmap_read(mpci->rmap, addr, &val);
+ if (ret < 0) {
+ dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret);
+ return ret;
+ }
+ *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
+
+ return 0;
+}
+
+static int max77620_set_fps_param(struct max77620_pctrl_info *mpci,
+ int pin, int param)
+{
+ struct max77620_fps_config *fps_config = &mpci->fps_config[pin];
+ int addr, ret;
+ int param_val;
+ int mask, shift;
+
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ return 0;
+
+ addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
+ switch (param) {
+ case MAX77620_ACTIVE_FPS_SOURCE:
+ case MAX77620_SUSPEND_FPS_SOURCE:
+ mask = MAX77620_FPS_SRC_MASK;
+ shift = MAX77620_FPS_SRC_SHIFT;
+ param_val = fps_config->active_fps_src;
+ if (param == MAX77620_SUSPEND_FPS_SOURCE)
+ param_val = fps_config->suspend_fps_src;
+ break;
+
+ case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
+ case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
+ mask = MAX77620_FPS_PU_PERIOD_MASK;
+ shift = MAX77620_FPS_PU_PERIOD_SHIFT;
+ param_val = fps_config->active_power_up_slots;
+ if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
+ param_val = fps_config->suspend_power_up_slots;
+ break;
+
+ case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
+ case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
+ mask = MAX77620_FPS_PD_PERIOD_MASK;
+ shift = MAX77620_FPS_PD_PERIOD_SHIFT;
+ param_val = fps_config->active_power_down_slots;
+ if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS)
+ param_val = fps_config->suspend_power_down_slots;
+ break;
+
+ default:
+ dev_err(mpci->dev, "Invalid parameter %d for pin %d\n",
+ param, pin);
+ return -EINVAL;
+ }
+
+ if (param_val < 0)
+ return 0;
+
+ ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift);
+ if (ret < 0)
+ dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret);
+
+ return ret;
+}
+
+static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev);
+ struct device *dev = mpci->dev;
+ struct max77620_fps_config *fps_config;
+ int param;
+ u16 param_val;
+ unsigned int val;
+ unsigned int pu_val;
+ unsigned int pd_val;
+ int addr, ret;
+ int i;
+
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ param_val = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ val = param_val ? 0 : 1;
+ ret = regmap_update_bits(mpci->rmap,
+ MAX77620_REG_GPIO0 + pin,
+ MAX77620_CNFG_GPIO_DRV_MASK,
+ val);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x update failed %d\n",
+ MAX77620_REG_GPIO0 + pin, ret);
+ return ret;
+ }
+ mpci->pin_info[pin].drv_type = val ?
+ MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
+ break;
+
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ val = param_val ? 1 : 0;
+ ret = regmap_update_bits(mpci->rmap,
+ MAX77620_REG_GPIO0 + pin,
+ MAX77620_CNFG_GPIO_DRV_MASK,
+ val);
+ if (ret < 0) {
+ dev_err(dev, "Reg 0x%02x update failed %d\n",
+ MAX77620_REG_GPIO0 + pin, ret);
+ return ret;
+ }
+ mpci->pin_info[pin].drv_type = val ?
+ MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
+ break;
+
+ case MAX77620_ACTIVE_FPS_SOURCE:
+ case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS:
+ case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS:
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ return -EINVAL;
+
+ fps_config = &mpci->fps_config[pin];
+
+ if ((param == MAX77620_ACTIVE_FPS_SOURCE) &&
+ (param_val == MAX77620_FPS_SRC_DEF)) {
+ addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
+ ret = max77620_get_default_fps(
+ mpci, addr,
+ &fps_config->active_fps_src);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+
+ if (param == MAX77620_ACTIVE_FPS_SOURCE)
+ fps_config->active_fps_src = param_val;
+ else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS)
+ fps_config->active_power_up_slots = param_val;
+ else
+ fps_config->active_power_down_slots = param_val;
+
+ ret = max77620_set_fps_param(mpci, pin, param);
+ if (ret < 0)
+ return ret;
+ break;
+
+ case MAX77620_SUSPEND_FPS_SOURCE:
+ case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS:
+ case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS:
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ return -EINVAL;
+
+ fps_config = &mpci->fps_config[pin];
+
+ if ((param == MAX77620_SUSPEND_FPS_SOURCE) &&
+ (param_val == MAX77620_FPS_SRC_DEF)) {
+ addr = MAX77620_REG_FPS_GPIO1 + pin - 1;
+ ret = max77620_get_default_fps(
+ mpci, addr,
+ &fps_config->suspend_fps_src);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+
+ if (param == MAX77620_SUSPEND_FPS_SOURCE)
+ fps_config->suspend_fps_src = param_val;
+ else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS)
+ fps_config->suspend_power_up_slots = param_val;
+ else
+ fps_config->suspend_power_down_slots =
+ param_val;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ?
+ BIT(pin) : 0;
+ pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ?
+ BIT(pin) : 0;
+
+ ret = regmap_update_bits(mpci->rmap,
+ MAX77620_REG_PUE_GPIO,
+ BIT(pin), pu_val);
+ if (ret < 0) {
+ dev_err(dev, "PUE_GPIO update failed: %d\n",
+ ret);
+ return ret;
+ }
+
+ ret = regmap_update_bits(mpci->rmap,
+ MAX77620_REG_PDE_GPIO,
+ BIT(pin), pd_val);
+ if (ret < 0) {
+ dev_err(dev, "PDE_GPIO update failed: %d\n",
+ ret);
+ return ret;
+ }
+ break;
+
+ default:
+ dev_err(dev, "Properties not supported\n");
+ return -ENOTSUPP;
+ }
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops max77620_pinconf_ops = {
+ .pin_config_get = max77620_pinconf_get,
+ .pin_config_set = max77620_pinconf_set,
+};
+
+static struct pinctrl_desc max77620_pinctrl_desc = {
+ .pctlops = &max77620_pinctrl_ops,
+ .pmxops = &max77620_pinmux_ops,
+ .confops = &max77620_pinconf_ops,
+};
+
+static int max77620_pinctrl_probe(struct platform_device *pdev)
+{
+ struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent);
+ struct max77620_pctrl_info *mpci;
+ int i;
+
+ mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL);
+ if (!mpci)
+ return -ENOMEM;
+
+ mpci->dev = &pdev->dev;
+ mpci->dev->of_node = pdev->dev.parent->of_node;
+ mpci->rmap = max77620->rmap;
+
+ mpci->pins = max77620_pins_desc;
+ mpci->num_pins = ARRAY_SIZE(max77620_pins_desc);
+ mpci->functions = max77620_pin_function;
+ mpci->num_functions = ARRAY_SIZE(max77620_pin_function);
+ mpci->pin_groups = max77620_pingroups;
+ mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups);
+ platform_set_drvdata(pdev, mpci);
+
+ max77620_pinctrl_desc.name = dev_name(&pdev->dev);
+ max77620_pinctrl_desc.pins = max77620_pins_desc;
+ max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc);
+ max77620_pinctrl_desc.num_custom_params =
+ ARRAY_SIZE(max77620_cfg_params);
+ max77620_pinctrl_desc.custom_params = max77620_cfg_params;
+
+ for (i = 0; i < MAX77620_PIN_NUM; ++i) {
+ mpci->fps_config[i].active_fps_src = -1;
+ mpci->fps_config[i].active_power_up_slots = -1;
+ mpci->fps_config[i].active_power_down_slots = -1;
+ mpci->fps_config[i].suspend_fps_src = -1;
+ mpci->fps_config[i].suspend_power_up_slots = -1;
+ mpci->fps_config[i].suspend_power_down_slots = -1;
+ }
+
+ mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc,
+ mpci);
+ if (IS_ERR(mpci->pctl)) {
+ dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
+ return PTR_ERR(mpci->pctl);
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int max77620_suspend_fps_param[] = {
+ MAX77620_SUSPEND_FPS_SOURCE,
+ MAX77620_SUSPEND_FPS_POWER_ON_SLOTS,
+ MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS,
+};
+
+static int max77620_active_fps_param[] = {
+ MAX77620_ACTIVE_FPS_SOURCE,
+ MAX77620_ACTIVE_FPS_POWER_ON_SLOTS,
+ MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS,
+};
+
+static int max77620_pinctrl_suspend(struct device *dev)
+{
+ struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
+ int pin, p;
+
+ for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ continue;
+ for (p = 0; p < 3; ++p)
+ max77620_set_fps_param(
+ mpci, pin, max77620_suspend_fps_param[p]);
+ }
+
+ return 0;
+};
+
+static int max77620_pinctrl_resume(struct device *dev)
+{
+ struct max77620_pctrl_info *mpci = dev_get_drvdata(dev);
+ int pin, p;
+
+ for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) {
+ if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3))
+ continue;
+ for (p = 0; p < 3; ++p)
+ max77620_set_fps_param(
+ mpci, pin, max77620_active_fps_param[p]);
+ }
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops max77620_pinctrl_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(
+ max77620_pinctrl_suspend, max77620_pinctrl_resume)
+};
+
+static const struct platform_device_id max77620_pinctrl_devtype[] = {
+ { .name = "max77620-pinctrl", },
+ { .name = "max20024-pinctrl", },
+ {},
+};
+MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype);
+
+static struct platform_driver max77620_pinctrl_driver = {
+ .driver = {
+ .name = "max77620-pinctrl",
+ .pm = &max77620_pinctrl_pm_ops,
+ },
+ .probe = max77620_pinctrl_probe,
+ .id_table = max77620_pinctrl_devtype,
+};
+
+module_platform_driver(max77620_pinctrl_driver);
+
+MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver");
+MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>");
+MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
+MODULE_ALIAS("platform:max77620-pinctrl");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-oxnas.c b/drivers/pinctrl/pinctrl-oxnas.c
new file mode 100644
index 000000000000..917a7d2535d7
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-oxnas.c
@@ -0,0 +1,846 @@
+/*
+ * Oxford Semiconductor OXNAS SoC Family pinctrl driver
+ *
+ * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Based on pinctrl-pic32.c
+ * Joshua Henderson, <joshua.henderson@microchip.com>
+ * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#include <linux/gpio/driver.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+
+#include "pinctrl-utils.h"
+
+#define PINS_PER_BANK 32
+
+#define GPIO_BANK_START(bank) ((bank) * PINS_PER_BANK)
+
+/* Regmap Offsets */
+#define PINMUX_PRIMARY_SEL0 0x0c
+#define PINMUX_SECONDARY_SEL0 0x14
+#define PINMUX_TERTIARY_SEL0 0x8c
+#define PINMUX_PRIMARY_SEL1 0x10
+#define PINMUX_SECONDARY_SEL1 0x18
+#define PINMUX_TERTIARY_SEL1 0x90
+#define PINMUX_PULLUP_CTRL0 0xac
+#define PINMUX_PULLUP_CTRL1 0xb0
+
+/* GPIO Registers */
+#define INPUT_VALUE 0x00
+#define OUTPUT_EN 0x04
+#define IRQ_PENDING 0x0c
+#define OUTPUT_SET 0x14
+#define OUTPUT_CLEAR 0x18
+#define OUTPUT_EN_SET 0x1c
+#define OUTPUT_EN_CLEAR 0x20
+#define RE_IRQ_ENABLE 0x28
+#define FE_IRQ_ENABLE 0x2c
+
+struct oxnas_function {
+ const char *name;
+ const char * const *groups;
+ unsigned int ngroups;
+};
+
+struct oxnas_pin_group {
+ const char *name;
+ unsigned int pin;
+ unsigned int bank;
+ struct oxnas_desc_function *functions;
+};
+
+struct oxnas_desc_function {
+ const char *name;
+ unsigned int fct;
+};
+
+struct oxnas_gpio_bank {
+ void __iomem *reg_base;
+ struct gpio_chip gpio_chip;
+ struct irq_chip irq_chip;
+ unsigned int id;
+};
+
+struct oxnas_pinctrl {
+ struct regmap *regmap;
+ struct device *dev;
+ struct pinctrl_dev *pctldev;
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+ const struct oxnas_function *functions;
+ unsigned int nfunctions;
+ const struct oxnas_pin_group *groups;
+ unsigned int ngroups;
+ struct oxnas_gpio_bank *gpio_banks;
+ unsigned int nbanks;
+};
+
+static const struct pinctrl_pin_desc oxnas_pins[] = {
+ PINCTRL_PIN(0, "gpio0"),
+ PINCTRL_PIN(1, "gpio1"),
+ PINCTRL_PIN(2, "gpio2"),
+ PINCTRL_PIN(3, "gpio3"),
+ PINCTRL_PIN(4, "gpio4"),
+ PINCTRL_PIN(5, "gpio5"),
+ PINCTRL_PIN(6, "gpio6"),
+ PINCTRL_PIN(7, "gpio7"),
+ PINCTRL_PIN(8, "gpio8"),
+ PINCTRL_PIN(9, "gpio9"),
+ PINCTRL_PIN(10, "gpio10"),
+ PINCTRL_PIN(11, "gpio11"),
+ PINCTRL_PIN(12, "gpio12"),
+ PINCTRL_PIN(13, "gpio13"),
+ PINCTRL_PIN(14, "gpio14"),
+ PINCTRL_PIN(15, "gpio15"),
+ PINCTRL_PIN(16, "gpio16"),
+ PINCTRL_PIN(17, "gpio17"),
+ PINCTRL_PIN(18, "gpio18"),
+ PINCTRL_PIN(19, "gpio19"),
+ PINCTRL_PIN(20, "gpio20"),
+ PINCTRL_PIN(21, "gpio21"),
+ PINCTRL_PIN(22, "gpio22"),
+ PINCTRL_PIN(23, "gpio23"),
+ PINCTRL_PIN(24, "gpio24"),
+ PINCTRL_PIN(25, "gpio25"),
+ PINCTRL_PIN(26, "gpio26"),
+ PINCTRL_PIN(27, "gpio27"),
+ PINCTRL_PIN(28, "gpio28"),
+ PINCTRL_PIN(29, "gpio29"),
+ PINCTRL_PIN(30, "gpio30"),
+ PINCTRL_PIN(31, "gpio31"),
+ PINCTRL_PIN(32, "gpio32"),
+ PINCTRL_PIN(33, "gpio33"),
+ PINCTRL_PIN(34, "gpio34"),
+};
+
+static const char * const oxnas_fct0_group[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+ "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14", "gpio15",
+ "gpio16", "gpio17", "gpio18", "gpio19",
+ "gpio20", "gpio21", "gpio22", "gpio23",
+ "gpio24", "gpio25", "gpio26", "gpio27",
+ "gpio28", "gpio29", "gpio30", "gpio31",
+ "gpio32", "gpio33", "gpio34"
+};
+
+static const char * const oxnas_fct3_group[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+ "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9",
+ "gpio20",
+ "gpio22", "gpio23", "gpio24", "gpio25",
+ "gpio26", "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31", "gpio32", "gpio33",
+ "gpio34"
+};
+
+#define FUNCTION(_name, _gr) \
+ { \
+ .name = #_name, \
+ .groups = oxnas_##_gr##_group, \
+ .ngroups = ARRAY_SIZE(oxnas_##_gr##_group), \
+ }
+
+static const struct oxnas_function oxnas_functions[] = {
+ FUNCTION(gpio, fct0),
+ FUNCTION(fct3, fct3),
+};
+
+#define OXNAS_PINCTRL_GROUP(_pin, _name, ...) \
+ { \
+ .name = #_name, \
+ .pin = _pin, \
+ .bank = _pin / PINS_PER_BANK, \
+ .functions = (struct oxnas_desc_function[]){ \
+ __VA_ARGS__, { } }, \
+ }
+
+#define OXNAS_PINCTRL_FUNCTION(_name, _fct) \
+ { \
+ .name = #_name, \
+ .fct = _fct, \
+ }
+
+static const struct oxnas_pin_group oxnas_groups[] = {
+ OXNAS_PINCTRL_GROUP(0, gpio0,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(1, gpio1,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(2, gpio2,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(3, gpio3,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(4, gpio4,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(5, gpio5,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(6, gpio6,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(7, gpio7,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(8, gpio8,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(9, gpio9,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(10, gpio10,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(11, gpio11,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(12, gpio12,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(13, gpio13,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(14, gpio14,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(15, gpio15,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(16, gpio16,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(17, gpio17,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(18, gpio18,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(19, gpio19,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(20, gpio20,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(21, gpio21,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0)),
+ OXNAS_PINCTRL_GROUP(22, gpio22,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(23, gpio23,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(24, gpio24,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(25, gpio25,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(26, gpio26,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(27, gpio27,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(28, gpio28,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(29, gpio29,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(30, gpio30,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(31, gpio31,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(32, gpio32,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(33, gpio33,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+ OXNAS_PINCTRL_GROUP(34, gpio34,
+ OXNAS_PINCTRL_FUNCTION(gpio, 0),
+ OXNAS_PINCTRL_FUNCTION(fct3, 3)),
+};
+
+static inline struct oxnas_gpio_bank *pctl_to_bank(struct oxnas_pinctrl *pctl,
+ unsigned int pin)
+{
+ return &pctl->gpio_banks[pin / PINS_PER_BANK];
+}
+
+static int oxnas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->ngroups;
+}
+
+static const char *oxnas_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int group)
+{
+ struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->groups[group].name;
+}
+
+static int oxnas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned int group,
+ const unsigned int **pins,
+ unsigned int *num_pins)
+{
+ struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = &pctl->groups[group].pin;
+ *num_pins = 1;
+
+ return 0;
+}
+
+static const struct pinctrl_ops oxnas_pinctrl_ops = {
+ .get_groups_count = oxnas_pinctrl_get_groups_count,
+ .get_group_name = oxnas_pinctrl_get_group_name,
+ .get_group_pins = oxnas_pinctrl_get_group_pins,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
+ .dt_free_map = pinctrl_utils_free_map,
+};
+
+static int oxnas_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
+{
+ struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->nfunctions;
+}
+
+static const char *
+oxnas_pinmux_get_function_name(struct pinctrl_dev *pctldev, unsigned int func)
+{
+ struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return pctl->functions[func].name;
+}
+
+static int oxnas_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
+ unsigned int func,
+ const char * const **groups,
+ unsigned int * const num_groups)
+{
+ struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = pctl->functions[func].groups;
+ *num_groups = pctl->functions[func].ngroups;
+
+ return 0;
+}
+
+static int oxnas_pinmux_enable(struct pinctrl_dev *pctldev,
+ unsigned int func, unsigned int group)
+{
+ struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct oxnas_pin_group *pg = &pctl->groups[group];
+ const struct oxnas_function *pf = &pctl->functions[func];
+ const char *fname = pf->name;
+ struct oxnas_desc_function *functions = pg->functions;
+ u32 mask = BIT(pg->pin);
+
+ while (functions->name) {
+ if (!strcmp(functions->name, fname)) {
+ dev_dbg(pctl->dev,
+ "setting function %s bank %d pin %d fct %d mask %x\n",
+ fname, pg->bank, pg->pin,
+ functions->fct, mask);
+
+ regmap_write_bits(pctl->regmap,
+ (pg->bank ?
+ PINMUX_PRIMARY_SEL1 :
+ PINMUX_PRIMARY_SEL0),
+ mask,
+ (functions->fct == 1 ?
+ mask : 0));
+ regmap_write_bits(pctl->regmap,
+ (pg->bank ?
+ PINMUX_SECONDARY_SEL1 :
+ PINMUX_SECONDARY_SEL0),
+ mask,
+ (functions->fct == 2 ?
+ mask : 0));
+ regmap_write_bits(pctl->regmap,
+ (pg->bank ?
+ PINMUX_TERTIARY_SEL1 :
+ PINMUX_TERTIARY_SEL0),
+ mask,
+ (functions->fct == 3 ?
+ mask : 0));
+
+ return 0;
+ }
+
+ functions++;
+ }
+
+ dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
+
+ return -EINVAL;
+}
+
+static int oxnas_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset)
+{
+ struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct oxnas_gpio_bank *bank = gpiochip_get_data(range->gc);
+ u32 mask = BIT(offset - bank->gpio_chip.base);
+
+ dev_dbg(pctl->dev, "requesting gpio %d in bank %d (id %d) with mask 0x%x\n",
+ offset, bank->gpio_chip.base, bank->id, mask);
+
+ regmap_write_bits(pctl->regmap,
+ (bank->id ?
+ PINMUX_PRIMARY_SEL1 :
+ PINMUX_PRIMARY_SEL0),
+ mask, 0);
+ regmap_write_bits(pctl->regmap,
+ (bank->id ?
+ PINMUX_SECONDARY_SEL1 :
+ PINMUX_SECONDARY_SEL0),
+ mask, 0);
+ regmap_write_bits(pctl->regmap,
+ (bank->id ?
+ PINMUX_TERTIARY_SEL1 :
+ PINMUX_TERTIARY_SEL0),
+ mask, 0);
+
+ return 0;
+}
+
+static int oxnas_gpio_get_direction(struct gpio_chip *chip,
+ unsigned int offset)
+{
+ struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
+ u32 mask = BIT(offset);
+
+ return !(readl_relaxed(bank->reg_base + OUTPUT_EN) & mask);
+}
+
+static int oxnas_gpio_direction_input(struct gpio_chip *chip,
+ unsigned int offset)
+{
+ struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
+ u32 mask = BIT(offset);
+
+ writel_relaxed(mask, bank->reg_base + OUTPUT_EN_CLEAR);
+
+ return 0;
+}
+
+static int oxnas_gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+ struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
+ u32 mask = BIT(offset);
+
+ return (readl_relaxed(bank->reg_base + INPUT_VALUE) & mask) != 0;
+}
+
+static void oxnas_gpio_set(struct gpio_chip *chip, unsigned int offset,
+ int value)
+{
+ struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
+ u32 mask = BIT(offset);
+
+ if (value)
+ writel_relaxed(mask, bank->reg_base + OUTPUT_SET);
+ else
+ writel_relaxed(mask, bank->reg_base + OUTPUT_CLEAR);
+}
+
+static int oxnas_gpio_direction_output(struct gpio_chip *chip,
+ unsigned int offset, int value)
+{
+ struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
+ u32 mask = BIT(offset);
+
+ oxnas_gpio_set(chip, offset, value);
+ writel_relaxed(mask, bank->reg_base + OUTPUT_EN_SET);
+
+ return 0;
+}
+
+static int oxnas_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int offset, bool input)
+{
+ struct gpio_chip *chip = range->gc;
+
+ if (input)
+ oxnas_gpio_direction_input(chip, offset);
+ else
+ oxnas_gpio_direction_output(chip, offset, 0);
+
+ return 0;
+}
+
+static const struct pinmux_ops oxnas_pinmux_ops = {
+ .get_functions_count = oxnas_pinmux_get_functions_count,
+ .get_function_name = oxnas_pinmux_get_function_name,
+ .get_function_groups = oxnas_pinmux_get_function_groups,
+ .set_mux = oxnas_pinmux_enable,
+ .gpio_request_enable = oxnas_gpio_request_enable,
+ .gpio_set_direction = oxnas_gpio_set_direction,
+};
+
+static int oxnas_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *config)
+{
+ struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
+ unsigned int param = pinconf_to_config_param(*config);
+ u32 mask = BIT(pin - bank->gpio_chip.base);
+ int ret;
+ u32 arg;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_PULL_UP:
+ ret = regmap_read(pctl->regmap,
+ (bank->id ?
+ PINMUX_PULLUP_CTRL1 :
+ PINMUX_PULLUP_CTRL0),
+ &arg);
+ if (ret)
+ return ret;
+
+ arg = !!(arg & mask);
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, arg);
+
+ return 0;
+}
+
+static int oxnas_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin);
+ unsigned int param;
+ u32 arg;
+ unsigned int i;
+ u32 offset = pin - bank->gpio_chip.base;
+ u32 mask = BIT(offset);
+
+ dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
+ pin, bank->gpio_chip.base, mask);
+
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ arg = pinconf_to_config_argument(configs[i]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_PULL_UP:
+ dev_dbg(pctl->dev, " pullup\n");
+ regmap_write_bits(pctl->regmap,
+ (bank->id ?
+ PINMUX_PULLUP_CTRL1 :
+ PINMUX_PULLUP_CTRL0),
+ mask, mask);
+ break;
+ default:
+ dev_err(pctl->dev, "Property %u not supported\n",
+ param);
+ return -ENOTSUPP;
+ }
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops oxnas_pinconf_ops = {
+ .pin_config_get = oxnas_pinconf_get,
+ .pin_config_set = oxnas_pinconf_set,
+ .is_generic = true,
+};
+
+static struct pinctrl_desc oxnas_pinctrl_desc = {
+ .name = "oxnas-pinctrl",
+ .pctlops = &oxnas_pinctrl_ops,
+ .pmxops = &oxnas_pinmux_ops,
+ .confops = &oxnas_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static void oxnas_gpio_irq_ack(struct irq_data *data)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
+ struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
+ u32 mask = BIT(data->hwirq);
+
+ writel(mask, bank->reg_base + IRQ_PENDING);
+}
+
+static void oxnas_gpio_irq_mask(struct irq_data *data)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
+ struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
+ unsigned int type = irqd_get_trigger_type(data);
+ u32 mask = BIT(data->hwirq);
+
+ if (type & IRQ_TYPE_EDGE_RISING)
+ writel(readl(bank->reg_base + RE_IRQ_ENABLE) & ~mask,
+ bank->reg_base + RE_IRQ_ENABLE);
+
+ if (type & IRQ_TYPE_EDGE_FALLING)
+ writel(readl(bank->reg_base + FE_IRQ_ENABLE) & ~mask,
+ bank->reg_base + FE_IRQ_ENABLE);
+}
+
+static void oxnas_gpio_irq_unmask(struct irq_data *data)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
+ struct oxnas_gpio_bank *bank = gpiochip_get_data(chip);
+ unsigned int type = irqd_get_trigger_type(data);
+ u32 mask = BIT(data->hwirq);
+
+ if (type & IRQ_TYPE_EDGE_RISING)
+ writel(readl(bank->reg_base + RE_IRQ_ENABLE) | mask,
+ bank->reg_base + RE_IRQ_ENABLE);
+
+ if (type & IRQ_TYPE_EDGE_FALLING)
+ writel(readl(bank->reg_base + FE_IRQ_ENABLE) | mask,
+ bank->reg_base + FE_IRQ_ENABLE);
+}
+
+static unsigned int oxnas_gpio_irq_startup(struct irq_data *data)
+{
+ struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
+
+ oxnas_gpio_direction_input(chip, data->hwirq);
+ oxnas_gpio_irq_unmask(data);
+
+ return 0;
+}
+
+static int oxnas_gpio_irq_set_type(struct irq_data *data, unsigned int type)
+{
+ if ((type & (IRQ_TYPE_EDGE_RISING|IRQ_TYPE_EDGE_FALLING)) == 0)
+ return -EINVAL;
+
+ irq_set_handler_locked(data, handle_edge_irq);
+
+ return 0;
+}
+
+static void oxnas_gpio_irq_handler(struct irq_desc *desc)
+{
+ struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+ struct oxnas_gpio_bank *bank = gpiochip_get_data(gc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned long stat;
+ unsigned int pin;
+
+ chained_irq_enter(chip, desc);
+
+ stat = readl(bank->reg_base + IRQ_PENDING);
+
+ for_each_set_bit(pin, &stat, BITS_PER_LONG)
+ generic_handle_irq(irq_linear_revmap(gc->irqdomain, pin));
+
+ chained_irq_exit(chip, desc);
+}
+
+#define GPIO_BANK(_bank) \
+ { \
+ .gpio_chip = { \
+ .label = "GPIO" #_bank, \
+ .request = gpiochip_generic_request, \
+ .free = gpiochip_generic_free, \
+ .get_direction = oxnas_gpio_get_direction, \
+ .direction_input = oxnas_gpio_direction_input, \
+ .direction_output = oxnas_gpio_direction_output, \
+ .get = oxnas_gpio_get, \
+ .set = oxnas_gpio_set, \
+ .ngpio = PINS_PER_BANK, \
+ .base = GPIO_BANK_START(_bank), \
+ .owner = THIS_MODULE, \
+ .can_sleep = 0, \
+ }, \
+ .irq_chip = { \
+ .name = "GPIO" #_bank, \
+ .irq_startup = oxnas_gpio_irq_startup, \
+ .irq_ack = oxnas_gpio_irq_ack, \
+ .irq_mask = oxnas_gpio_irq_mask, \
+ .irq_unmask = oxnas_gpio_irq_unmask, \
+ .irq_set_type = oxnas_gpio_irq_set_type, \
+ }, \
+ }
+
+static struct oxnas_gpio_bank oxnas_gpio_banks[] = {
+ GPIO_BANK(0),
+ GPIO_BANK(1),
+};
+
+static int oxnas_pinctrl_probe(struct platform_device *pdev)
+{
+ struct oxnas_pinctrl *pctl;
+
+ pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
+ if (!pctl)
+ return -ENOMEM;
+ pctl->dev = &pdev->dev;
+ dev_set_drvdata(&pdev->dev, pctl);
+
+ pctl->regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "oxsemi,sys-ctrl");
+ if (IS_ERR(pctl->regmap)) {
+ dev_err(&pdev->dev, "failed to get sys ctrl regmap\n");
+ return -ENODEV;
+ }
+
+ pctl->pins = oxnas_pins;
+ pctl->npins = ARRAY_SIZE(oxnas_pins);
+ pctl->functions = oxnas_functions;
+ pctl->nfunctions = ARRAY_SIZE(oxnas_functions);
+ pctl->groups = oxnas_groups;
+ pctl->ngroups = ARRAY_SIZE(oxnas_groups);
+ pctl->gpio_banks = oxnas_gpio_banks;
+ pctl->nbanks = ARRAY_SIZE(oxnas_gpio_banks);
+
+ oxnas_pinctrl_desc.pins = pctl->pins;
+ oxnas_pinctrl_desc.npins = pctl->npins;
+
+ pctl->pctldev = pinctrl_register(&oxnas_pinctrl_desc,
+ &pdev->dev, pctl);
+ if (IS_ERR(pctl->pctldev)) {
+ dev_err(&pdev->dev, "Failed to register pinctrl device\n");
+ return PTR_ERR(pctl->pctldev);
+ }
+
+ return 0;
+}
+
+static int oxnas_gpio_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct of_phandle_args pinspec;
+ struct oxnas_gpio_bank *bank;
+ unsigned int id, ngpios;
+ int irq, ret;
+ struct resource *res;
+
+ if (of_parse_phandle_with_fixed_args(np, "gpio-ranges",
+ 3, 0, &pinspec)) {
+ dev_err(&pdev->dev, "gpio-ranges property not found\n");
+ return -EINVAL;
+ }
+
+ id = pinspec.args[1] / PINS_PER_BANK;
+ ngpios = pinspec.args[2];
+
+ if (id >= ARRAY_SIZE(oxnas_gpio_banks)) {
+ dev_err(&pdev->dev, "invalid gpio-ranges base arg\n");
+ return -EINVAL;
+ }
+
+ if (ngpios > PINS_PER_BANK) {
+ dev_err(&pdev->dev, "invalid gpio-ranges count arg\n");
+ return -EINVAL;
+ }
+
+ bank = &oxnas_gpio_banks[id];
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ bank->reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(bank->reg_base))
+ return PTR_ERR(bank->reg_base);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "irq get failed\n");
+ return irq;
+ }
+
+ bank->id = id;
+ bank->gpio_chip.parent = &pdev->dev;
+ bank->gpio_chip.of_node = np;
+ bank->gpio_chip.ngpio = ngpios;
+ ret = gpiochip_add_data(&bank->gpio_chip, bank);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to add GPIO chip %u: %d\n",
+ id, ret);
+ return ret;
+ }
+
+ ret = gpiochip_irqchip_add(&bank->gpio_chip, &bank->irq_chip,
+ 0, handle_level_irq, IRQ_TYPE_NONE);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to add IRQ chip %u: %d\n",
+ id, ret);
+ gpiochip_remove(&bank->gpio_chip);
+ return ret;
+ }
+
+ gpiochip_set_chained_irqchip(&bank->gpio_chip, &bank->irq_chip,
+ irq, oxnas_gpio_irq_handler);
+
+ return 0;
+}
+
+static const struct of_device_id oxnas_pinctrl_of_match[] = {
+ { .compatible = "oxsemi,ox810se-pinctrl", },
+ { },
+};
+
+static struct platform_driver oxnas_pinctrl_driver = {
+ .driver = {
+ .name = "oxnas-pinctrl",
+ .of_match_table = oxnas_pinctrl_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = oxnas_pinctrl_probe,
+};
+
+static const struct of_device_id oxnas_gpio_of_match[] = {
+ { .compatible = "oxsemi,ox810se-gpio", },
+ { },
+};
+
+static struct platform_driver oxnas_gpio_driver = {
+ .driver = {
+ .name = "oxnas-gpio",
+ .of_match_table = oxnas_gpio_of_match,
+ .suppress_bind_attrs = true,
+ },
+ .probe = oxnas_gpio_probe,
+};
+
+static int __init oxnas_gpio_register(void)
+{
+ return platform_driver_register(&oxnas_gpio_driver);
+}
+arch_initcall(oxnas_gpio_register);
+
+static int __init oxnas_pinctrl_register(void)
+{
+ return platform_driver_register(&oxnas_pinctrl_driver);
+}
+arch_initcall(oxnas_pinctrl_register);
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index a91026e8cd7c..44902c63f507 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -360,7 +360,7 @@ static struct regmap_config rockchip_regmap_config = {
.reg_stride = 4,
};
-static const inline struct rockchip_pin_group *pinctrl_name_to_group(
+static inline const struct rockchip_pin_group *pinctrl_name_to_group(
const struct rockchip_pinctrl *info,
const char *name)
{
@@ -2007,7 +2007,7 @@ static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
irq_gc_mask_clr_bit(d);
}
-void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
+static void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct rockchip_pin_bank *bank = gc->private;
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index d0ba968af5bb..0de1c67dfb94 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -844,7 +844,7 @@ static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev,
return 0;
}
-static const inline struct st_pctl_group *st_pctl_find_group_by_name(
+static inline const struct st_pctl_group *st_pctl_find_group_by_name(
const struct st_pinctrl *info, const char *name)
{
int i;
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index d1af908a7060..9cc80a500880 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -670,7 +670,7 @@ struct u300_pmx {
* u300_pmx_registers - the array of registers read/written for each pinmux
* shunt setting
*/
-const u32 u300_pmx_registers[] = {
+static const u32 u300_pmx_registers[] = {
U300_SYSCON_PMC1LR,
U300_SYSCON_PMC1HR,
U300_SYSCON_PMC2R,
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
index b9375544dff0..dd85ad1807f5 100644
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -1616,50 +1616,74 @@ struct pinctrl_xway_soc {
/* xway xr9 series (DEPRECATED: Use XWAY xRX100/xRX200 Family) */
static struct pinctrl_xway_soc xr9_pinctrl = {
- XR9_MAX_PIN, xway_mfp,
- xway_grps, ARRAY_SIZE(xway_grps),
- xrx_funcs, ARRAY_SIZE(xrx_funcs),
- xway_exin_pin_map, 6
+ .pin_count = XR9_MAX_PIN,
+ .mfp = xway_mfp,
+ .grps = xway_grps,
+ .num_grps = ARRAY_SIZE(xway_grps),
+ .funcs = xrx_funcs,
+ .num_funcs = ARRAY_SIZE(xrx_funcs),
+ .exin = xway_exin_pin_map,
+ .num_exin = 6
};
/* XWAY AMAZON Family */
static struct pinctrl_xway_soc ase_pinctrl = {
- ASE_MAX_PIN, ase_mfp,
- ase_grps, ARRAY_SIZE(ase_grps),
- ase_funcs, ARRAY_SIZE(ase_funcs),
- ase_exin_pin_map, 3
+ .pin_count = ASE_MAX_PIN,
+ .mfp = ase_mfp,
+ .grps = ase_grps,
+ .num_grps = ARRAY_SIZE(ase_grps),
+ .funcs = ase_funcs,
+ .num_funcs = ARRAY_SIZE(ase_funcs),
+ .exin = ase_exin_pin_map,
+ .num_exin = 3
};
/* XWAY DANUBE Family */
static struct pinctrl_xway_soc danube_pinctrl = {
- DANUBE_MAX_PIN, danube_mfp,
- danube_grps, ARRAY_SIZE(danube_grps),
- danube_funcs, ARRAY_SIZE(danube_funcs),
- danube_exin_pin_map, 3
+ .pin_count = DANUBE_MAX_PIN,
+ .mfp = danube_mfp,
+ .grps = danube_grps,
+ .num_grps = ARRAY_SIZE(danube_grps),
+ .funcs = danube_funcs,
+ .num_funcs = ARRAY_SIZE(danube_funcs),
+ .exin = danube_exin_pin_map,
+ .num_exin = 3
};
/* XWAY xRX100 Family */
static struct pinctrl_xway_soc xrx100_pinctrl = {
- XRX100_MAX_PIN, xrx100_mfp,
- xrx100_grps, ARRAY_SIZE(xrx100_grps),
- xrx100_funcs, ARRAY_SIZE(xrx100_funcs),
- xrx100_exin_pin_map, 6
+ .pin_count = XRX100_MAX_PIN,
+ .mfp = xrx100_mfp,
+ .grps = xrx100_grps,
+ .num_grps = ARRAY_SIZE(xrx100_grps),
+ .funcs = xrx100_funcs,
+ .num_funcs = ARRAY_SIZE(xrx100_funcs),
+ .exin = xrx100_exin_pin_map,
+ .num_exin = 6
};
/* XWAY xRX200 Family */
static struct pinctrl_xway_soc xrx200_pinctrl = {
- XRX200_MAX_PIN, xrx200_mfp,
- xrx200_grps, ARRAY_SIZE(xrx200_grps),
- xrx200_funcs, ARRAY_SIZE(xrx200_funcs),
- xrx200_exin_pin_map, 6
+ .pin_count = XRX200_MAX_PIN,
+ .mfp = xrx200_mfp,
+ .grps = xrx200_grps,
+ .num_grps = ARRAY_SIZE(xrx200_grps),
+ .funcs = xrx200_funcs,
+ .num_funcs = ARRAY_SIZE(xrx200_funcs),
+ .exin = xrx200_exin_pin_map,
+ .num_exin = 6
};
/* XWAY xRX300 Family */
static struct pinctrl_xway_soc xrx300_pinctrl = {
- XRX300_MAX_PIN, xrx300_mfp,
- xrx300_grps, ARRAY_SIZE(xrx300_grps),
- xrx300_funcs, ARRAY_SIZE(xrx300_funcs),
- xrx300_exin_pin_map, 5
+ .pin_count = XRX300_MAX_PIN,
+ .mfp = xrx300_mfp,
+ .grps = xrx300_grps,
+ .num_grps = ARRAY_SIZE(xrx300_grps),
+ .funcs = xrx300_funcs,
+ .num_funcs = ARRAY_SIZE(xrx300_funcs),
+ .exin = xrx300_exin_pin_map,
+ .num_exin = 5
};
static struct pinctrl_gpio_range xway_gpio_range = {
diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c
index 8fdc60c5aeaf..7afdbede6823 100644
--- a/drivers/pinctrl/pinctrl-zynq.c
+++ b/drivers/pinctrl/pinctrl-zynq.c
@@ -20,7 +20,7 @@
*/
#include <linux/io.h>
#include <linux/mfd/syscon.h>
-#include <linux/module.h>
+#include <linux/init.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
@@ -1210,7 +1210,6 @@ static const struct of_device_id zynq_pinctrl_of_match[] = {
{ .compatible = "xlnx,pinctrl-zynq" },
{ }
};
-MODULE_DEVICE_TABLE(of, zynq_pinctrl_of_match);
static struct platform_driver zynq_pinctrl_driver = {
.driver = {
@@ -1225,13 +1224,3 @@ static int __init zynq_pinctrl_init(void)
return platform_driver_register(&zynq_pinctrl_driver);
}
arch_initcall(zynq_pinctrl_init);
-
-static void __exit zynq_pinctrl_exit(void)
-{
- platform_driver_unregister(&zynq_pinctrl_driver);
-}
-module_exit(zynq_pinctrl_exit);
-
-MODULE_AUTHOR("Sören Brinkmann <soren.brinkmann@xilinx.com>");
-MODULE_DESCRIPTION("Xilinx Zynq pinctrl driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index c223a9ef1fe1..ece702881946 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -256,7 +256,7 @@ int pinmux_request_gpio(struct pinctrl_dev *pctldev,
/* Conjure some name stating what chip and pin this is taken by */
owner = kasprintf(GFP_KERNEL, "%s:%d", range->name, gpio);
if (!owner)
- return -EINVAL;
+ return -ENOMEM;
ret = pin_request(pctldev, pin, owner, range);
if (ret < 0)
@@ -606,23 +606,17 @@ static int pinmux_pins_show(struct seq_file *s, void *what)
if (pmxops->strict) {
if (desc->mux_owner)
seq_printf(s, "pin %d (%s): device %s%s",
- pin,
- desc->name ? desc->name : "unnamed",
- desc->mux_owner,
+ pin, desc->name, desc->mux_owner,
is_hog ? " (HOG)" : "");
else if (desc->gpio_owner)
seq_printf(s, "pin %d (%s): GPIO %s",
- pin,
- desc->name ? desc->name : "unnamed",
- desc->gpio_owner);
+ pin, desc->name, desc->gpio_owner);
else
seq_printf(s, "pin %d (%s): UNCLAIMED",
- pin,
- desc->name ? desc->name : "unnamed");
+ pin, desc->name);
} else {
/* For non-strict controllers */
- seq_printf(s, "pin %d (%s): %s %s%s", pin,
- desc->name ? desc->name : "unnamed",
+ seq_printf(s, "pin %d (%s): %s %s%s", pin, desc->name,
desc->mux_owner ? desc->mux_owner
: "(MUX UNCLAIMED)",
desc->gpio_owner ? desc->gpio_owner
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 67bc70dcda64..93ef268d5ccd 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -55,6 +55,14 @@ config PINCTRL_MSM8960
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm 8960 platform.
+config PINCTRL_MDM9615
+ tristate "Qualcomm 9615 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm TLMM block found in the Qualcomm 9615 platform.
+
config PINCTRL_MSM8X74
tristate "Qualcomm 8x74 pin controller driver"
depends on GPIOLIB && OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index c964a2c4b90a..8319e11cecb5 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o
obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o
obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o
+obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
diff --git a/drivers/pinctrl/qcom/pinctrl-mdm9615.c b/drivers/pinctrl/qcom/pinctrl-mdm9615.c
new file mode 100644
index 000000000000..2b8f4521692c
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-mdm9615.c
@@ -0,0 +1,483 @@
+/*
+ * Copyright (c) 2014, Sony Mobile Communications AB.
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author : Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "pinctrl-msm.h"
+
+static const struct pinctrl_pin_desc mdm9615_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+ PINCTRL_PIN(70, "GPIO_70"),
+ PINCTRL_PIN(71, "GPIO_71"),
+ PINCTRL_PIN(72, "GPIO_72"),
+ PINCTRL_PIN(73, "GPIO_73"),
+ PINCTRL_PIN(74, "GPIO_74"),
+ PINCTRL_PIN(75, "GPIO_75"),
+ PINCTRL_PIN(76, "GPIO_76"),
+ PINCTRL_PIN(77, "GPIO_77"),
+ PINCTRL_PIN(78, "GPIO_78"),
+ PINCTRL_PIN(79, "GPIO_79"),
+ PINCTRL_PIN(80, "GPIO_80"),
+ PINCTRL_PIN(81, "GPIO_81"),
+ PINCTRL_PIN(82, "GPIO_82"),
+ PINCTRL_PIN(83, "GPIO_83"),
+ PINCTRL_PIN(84, "GPIO_84"),
+ PINCTRL_PIN(85, "GPIO_85"),
+ PINCTRL_PIN(86, "GPIO_86"),
+ PINCTRL_PIN(87, "GPIO_87"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+DECLARE_MSM_GPIO_PINS(65);
+DECLARE_MSM_GPIO_PINS(66);
+DECLARE_MSM_GPIO_PINS(67);
+DECLARE_MSM_GPIO_PINS(68);
+DECLARE_MSM_GPIO_PINS(69);
+DECLARE_MSM_GPIO_PINS(70);
+DECLARE_MSM_GPIO_PINS(71);
+DECLARE_MSM_GPIO_PINS(72);
+DECLARE_MSM_GPIO_PINS(73);
+DECLARE_MSM_GPIO_PINS(74);
+DECLARE_MSM_GPIO_PINS(75);
+DECLARE_MSM_GPIO_PINS(76);
+DECLARE_MSM_GPIO_PINS(77);
+DECLARE_MSM_GPIO_PINS(78);
+DECLARE_MSM_GPIO_PINS(79);
+DECLARE_MSM_GPIO_PINS(80);
+DECLARE_MSM_GPIO_PINS(81);
+DECLARE_MSM_GPIO_PINS(82);
+DECLARE_MSM_GPIO_PINS(83);
+DECLARE_MSM_GPIO_PINS(84);
+DECLARE_MSM_GPIO_PINS(85);
+DECLARE_MSM_GPIO_PINS(86);
+DECLARE_MSM_GPIO_PINS(87);
+
+#define FUNCTION(fname) \
+ [MSM_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ MSM_MUX_gpio, \
+ MSM_MUX_##f1, \
+ MSM_MUX_##f2, \
+ MSM_MUX_##f3, \
+ MSM_MUX_##f4, \
+ MSM_MUX_##f5, \
+ MSM_MUX_##f6, \
+ MSM_MUX_##f7, \
+ MSM_MUX_##f8, \
+ MSM_MUX_##f9, \
+ MSM_MUX_##f10, \
+ MSM_MUX_##f11 \
+ }, \
+ .nfuncs = 12, \
+ .ctl_reg = 0x1000 + 0x10 * id, \
+ .io_reg = 0x1004 + 0x10 * id, \
+ .intr_cfg_reg = 0x1008 + 0x10 * id, \
+ .intr_status_reg = 0x100c + 0x10 * id, \
+ .intr_target_reg = 0x400 + 0x4 * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_ack_high = 1, \
+ .intr_target_bit = 0, \
+ .intr_target_kpss_val = 4, \
+ .intr_raw_status_bit = 3, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 1, \
+ }
+
+enum mdm9615_functions {
+ MSM_MUX_gpio,
+ MSM_MUX_gsbi2_i2c,
+ MSM_MUX_gsbi3,
+ MSM_MUX_gsbi4,
+ MSM_MUX_gsbi5_i2c,
+ MSM_MUX_gsbi5_uart,
+ MSM_MUX_sdc2,
+ MSM_MUX_ebi2_lcdc,
+ MSM_MUX_ps_hold,
+ MSM_MUX_prim_audio,
+ MSM_MUX_sec_audio,
+ MSM_MUX_cdc_mclk,
+ MSM_MUX_NA,
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
+ "gpio85", "gpio86", "gpio87"
+};
+
+static const char * const gsbi2_i2c_groups[] = {
+ "gpio4", "gpio5"
+};
+
+static const char * const gsbi3_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+
+static const char * const gsbi4_groups[] = {
+ "gpio12", "gpio13", "gpio14", "gpio15"
+};
+
+static const char * const gsbi5_i2c_groups[] = {
+ "gpio16", "gpio17"
+};
+
+static const char * const gsbi5_uart_groups[] = {
+ "gpio18", "gpio19"
+};
+
+static const char * const sdc2_groups[] = {
+ "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", "gpio30",
+};
+
+static const char * const ebi2_lcdc_groups[] = {
+ "gpio21", "gpio22", "gpio24",
+};
+
+static const char * const ps_hold_groups[] = {
+ "gpio83",
+};
+
+static const char * const prim_audio_groups[] = {
+ "gpio20", "gpio21", "gpio22", "gpio23",
+};
+
+static const char * const sec_audio_groups[] = {
+ "gpio25", "gpio26", "gpio27", "gpio28",
+};
+
+static const char * const cdc_mclk_groups[] = {
+ "gpio24",
+};
+
+static const struct msm_function mdm9615_functions[] = {
+ FUNCTION(gpio),
+ FUNCTION(gsbi2_i2c),
+ FUNCTION(gsbi3),
+ FUNCTION(gsbi4),
+ FUNCTION(gsbi5_i2c),
+ FUNCTION(gsbi5_uart),
+ FUNCTION(sdc2),
+ FUNCTION(ebi2_lcdc),
+ FUNCTION(ps_hold),
+ FUNCTION(prim_audio),
+ FUNCTION(sec_audio),
+ FUNCTION(cdc_mclk),
+};
+
+static const struct msm_pingroup mdm9615_groups[] = {
+ PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(4, gsbi2_i2c, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(5, gsbi2_i2c, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(6, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(8, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(9, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(10, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(11, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(12, gsbi4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(13, gsbi4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(14, gsbi4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(15, gsbi4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(16, gsbi5_i2c, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(17, gsbi5_i2c, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(18, gsbi5_uart, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(19, gsbi5_uart, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(20, prim_audio, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(21, prim_audio, ebi2_lcdc, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(22, prim_audio, ebi2_lcdc, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(23, prim_audio, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(24, cdc_mclk, NA, ebi2_lcdc, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(25, sdc2, sec_audio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(26, sdc2, sec_audio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(27, sdc2, sec_audio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(28, sdc2, sec_audio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(29, sdc2, sec_audio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(30, sdc2, sec_audio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(31, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(33, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(34, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(35, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(36, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(37, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(39, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(44, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(45, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(46, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(47, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(48, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(49, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(50, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(51, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(52, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(53, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(54, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(55, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(56, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(57, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(58, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(59, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(60, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(61, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(62, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(63, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(73, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(74, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(82, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(83, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(84, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(85, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+};
+
+#define NUM_GPIO_PINGROUPS 88
+
+static const struct msm_pinctrl_soc_data mdm9615_pinctrl = {
+ .pins = mdm9615_pins,
+ .npins = ARRAY_SIZE(mdm9615_pins),
+ .functions = mdm9615_functions,
+ .nfunctions = ARRAY_SIZE(mdm9615_functions),
+ .groups = mdm9615_groups,
+ .ngroups = ARRAY_SIZE(mdm9615_groups),
+ .ngpios = NUM_GPIO_PINGROUPS,
+};
+
+static int mdm9615_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &mdm9615_pinctrl);
+}
+
+static const struct of_device_id mdm9615_pinctrl_of_match[] = {
+ { .compatible = "qcom,mdm9615-pinctrl", },
+ { },
+};
+
+static struct platform_driver mdm9615_pinctrl_driver = {
+ .driver = {
+ .name = "mdm9615-pinctrl",
+ .of_match_table = mdm9615_pinctrl_of_match,
+ },
+ .probe = mdm9615_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init mdm9615_pinctrl_init(void)
+{
+ return platform_driver_register(&mdm9615_pinctrl_driver);
+}
+arch_initcall(mdm9615_pinctrl_init);
+
+static void __exit mdm9615_pinctrl_exit(void)
+{
+ platform_driver_unregister(&mdm9615_pinctrl_driver);
+}
+module_exit(mdm9615_pinctrl_exit);
+
+MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
+MODULE_DESCRIPTION("Qualcomm MDM9615 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, mdm9615_pinctrl_of_match);
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 1a44e1d03390..51c42d746883 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -29,6 +29,7 @@
#include <linux/spinlock.h>
#include <linux/reboot.h>
#include <linux/pm.h>
+#include <linux/log2.h>
#include "../core.h"
#include "../pinconf.h"
@@ -138,10 +139,11 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct msm_pingroup *g;
unsigned long flags;
- u32 val;
+ u32 val, mask;
int i;
g = &pctrl->soc->groups[group];
+ mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
for (i = 0; i < g->nfuncs; i++) {
if (g->funcs[i] == function)
@@ -154,7 +156,7 @@ static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
spin_lock_irqsave(&pctrl->lock, flags);
val = readl(pctrl->regs + g->ctl_reg);
- val &= ~(0x7 << g->mux_bit);
+ val &= mask;
val |= i << g->mux_bit;
writel(val, pctrl->regs + g->ctl_reg);
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8660.c b/drivers/pinctrl/qcom/pinctrl-msm8660.c
index 3e8f7ac2ac8a..5591d093bf78 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8660.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c
@@ -506,6 +506,8 @@ enum msm8660_functions {
MSM_MUX_usb_fs2_oe_n,
MSM_MUX_vfe,
MSM_MUX_vsens_alarm,
+ MSM_MUX_ebi2cs,
+ MSM_MUX_ebi2,
MSM_MUX__,
};
@@ -696,6 +698,36 @@ static const char * const vfe_groups[] = {
static const char * const vsens_alarm_groups[] = {
"gpio127"
};
+static const char * const ebi2cs_groups[] = {
+ "gpio39", /* CS1A */
+ "gpio40", /* CS2A */
+ "gpio123", /* CS1B */
+ "gpio124", /* CS2B */
+ "gpio131", /* CS5 */
+ "gpio132", /* CS4 */
+ "gpio133", /* CS3 */
+ "gpio134", /* CS0 */
+};
+static const char * const ebi2_groups[] = {
+ /* ADDR9 & ADDR8 */
+ "gpio37", "gpio38",
+ /* ADDR7 - ADDR 0 */
+ "gpio123", "gpio124", "gpio125", "gpio126",
+ "gpio127", "gpio128", "gpio129", "gpio130",
+ /* (muxed address+data) AD15 - AD0 */
+ "gpio135", "gpio136", "gpio137", "gpio138", "gpio139",
+ "gpio140", "gpio141", "gpio142", "gpio143", "gpio144",
+ "gpio145", "gpio146", "gpio147", "gpio148", "gpio149",
+ "gpio150",
+ "gpio151", /* OE output enable */
+ "gpio152", /* clock */
+ "gpio153", /* ADV */
+ "gpio154", /* WAIT (input) */
+ "gpio155", /* UB Upper Byte Enable */
+ "gpio156", /* LB Lower Byte Enable */
+ "gpio157", /* WE Write Enable */
+ "gpio158", /* busy */
+};
static const struct msm_function msm8660_functions[] = {
FUNCTION(gpio),
@@ -749,6 +781,8 @@ static const struct msm_function msm8660_functions[] = {
FUNCTION(usb_fs2_oe_n),
FUNCTION(vfe),
FUNCTION(vsens_alarm),
+ FUNCTION(ebi2cs), /* for EBI2 chip selects */
+ FUNCTION(ebi2), /* for general EBI2 pins */
};
static const struct msm_pingroup msm8660_groups[] = {
@@ -789,10 +823,10 @@ static const struct msm_pingroup msm8660_groups[] = {
PINGROUP(34, gsbi1, _, _, _, _, _, _),
PINGROUP(35, gsbi1, _, _, _, _, _, _),
PINGROUP(36, gsbi1, _, _, _, _, _, _),
- PINGROUP(37, gsbi2, _, _, _, _, _, _),
- PINGROUP(38, gsbi2, _, _, _, _, _, _),
- PINGROUP(39, gsbi2, _, mdp_vsync, _, _, _, _),
- PINGROUP(40, gsbi2, _, _, _, _, _, _),
+ PINGROUP(37, gsbi2, ebi2, _, _, _, _, _),
+ PINGROUP(38, gsbi2, ebi2, _, _, _, _, _),
+ PINGROUP(39, gsbi2, ebi2cs, mdp_vsync, _, _, _, _),
+ PINGROUP(40, gsbi2, ebi2cs, _, _, _, _, _),
PINGROUP(41, gsbi3, mdp_vsync, _, _, _, _, _),
PINGROUP(42, gsbi3, vfe, _, _, _, _, _),
PINGROUP(43, gsbi3, _, _, _, _, _, _),
@@ -875,42 +909,42 @@ static const struct msm_pingroup msm8660_groups[] = {
PINGROUP(120, i2s, _, _, _, _, _, _),
PINGROUP(121, i2s, _, _, _, _, _, _),
PINGROUP(122, i2s, gp_clk_1b, _, _, _, _, _),
- PINGROUP(123, _, gsbi2_spi_cs1_n, _, _, _, _, _),
- PINGROUP(124, _, gsbi2_spi_cs2_n, _, _, _, _, _),
- PINGROUP(125, _, gsbi2_spi_cs3_n, _, _, _, _, _),
- PINGROUP(126, _, _, _, _, _, _, _),
- PINGROUP(127, _, vsens_alarm, _, _, _, _, _),
- PINGROUP(128, _, _, _, _, _, _, _),
- PINGROUP(129, _, _, _, _, _, _, _),
- PINGROUP(130, _, _, _, _, _, _, _),
- PINGROUP(131, _, _, _, _, _, _, _),
- PINGROUP(132, _, _, _, _, _, _, _),
- PINGROUP(133, _, _, _, _, _, _, _),
- PINGROUP(134, _, _, _, _, _, _, _),
- PINGROUP(135, _, _, _, _, _, _, _),
- PINGROUP(136, _, _, _, _, _, _, _),
- PINGROUP(137, _, _, _, _, _, _, _),
- PINGROUP(138, _, _, _, _, _, _, _),
- PINGROUP(139, _, _, _, _, _, _, _),
- PINGROUP(140, _, _, _, _, _, _, _),
- PINGROUP(141, _, _, _, _, _, _, _),
- PINGROUP(142, _, _, _, _, _, _, _),
- PINGROUP(143, _, sdc2, _, _, _, _, _),
- PINGROUP(144, _, sdc2, _, _, _, _, _),
- PINGROUP(145, _, sdc2, _, _, _, _, _),
- PINGROUP(146, _, sdc2, _, _, _, _, _),
- PINGROUP(147, _, sdc2, _, _, _, _, _),
- PINGROUP(148, _, sdc2, _, _, _, _, _),
- PINGROUP(149, _, sdc2, _, _, _, _, _),
- PINGROUP(150, _, sdc2, _, _, _, _, _),
- PINGROUP(151, _, sdc2, _, _, _, _, _),
- PINGROUP(152, _, sdc2, _, _, _, _, _),
- PINGROUP(153, _, _, _, _, _, _, _),
- PINGROUP(154, _, _, _, _, _, _, _),
- PINGROUP(155, _, _, _, _, _, _, _),
- PINGROUP(156, _, _, _, _, _, _, _),
- PINGROUP(157, _, _, _, _, _, _, _),
- PINGROUP(158, _, _, _, _, _, _, _),
+ PINGROUP(123, ebi2, gsbi2_spi_cs1_n, ebi2cs, _, _, _, _),
+ PINGROUP(124, ebi2, gsbi2_spi_cs2_n, ebi2cs, _, _, _, _),
+ PINGROUP(125, ebi2, gsbi2_spi_cs3_n, _, _, _, _, _),
+ PINGROUP(126, ebi2, _, _, _, _, _, _),
+ PINGROUP(127, ebi2, vsens_alarm, _, _, _, _, _),
+ PINGROUP(128, ebi2, _, _, _, _, _, _),
+ PINGROUP(129, ebi2, _, _, _, _, _, _),
+ PINGROUP(130, ebi2, _, _, _, _, _, _),
+ PINGROUP(131, ebi2cs, _, _, _, _, _, _),
+ PINGROUP(132, ebi2cs, _, _, _, _, _, _),
+ PINGROUP(133, ebi2cs, _, _, _, _, _, _),
+ PINGROUP(134, ebi2cs, _, _, _, _, _, _),
+ PINGROUP(135, ebi2, _, _, _, _, _, _),
+ PINGROUP(136, ebi2, _, _, _, _, _, _),
+ PINGROUP(137, ebi2, _, _, _, _, _, _),
+ PINGROUP(138, ebi2, _, _, _, _, _, _),
+ PINGROUP(139, ebi2, _, _, _, _, _, _),
+ PINGROUP(140, ebi2, _, _, _, _, _, _),
+ PINGROUP(141, ebi2, _, _, _, _, _, _),
+ PINGROUP(142, ebi2, _, _, _, _, _, _),
+ PINGROUP(143, ebi2, sdc2, _, _, _, _, _),
+ PINGROUP(144, ebi2, sdc2, _, _, _, _, _),
+ PINGROUP(145, ebi2, sdc2, _, _, _, _, _),
+ PINGROUP(146, ebi2, sdc2, _, _, _, _, _),
+ PINGROUP(147, ebi2, sdc2, _, _, _, _, _),
+ PINGROUP(148, ebi2, sdc2, _, _, _, _, _),
+ PINGROUP(149, ebi2, sdc2, _, _, _, _, _),
+ PINGROUP(150, ebi2, sdc2, _, _, _, _, _),
+ PINGROUP(151, ebi2, sdc2, _, _, _, _, _),
+ PINGROUP(152, ebi2, sdc2, _, _, _, _, _),
+ PINGROUP(153, ebi2, _, _, _, _, _, _),
+ PINGROUP(154, ebi2, _, _, _, _, _, _),
+ PINGROUP(155, ebi2, _, _, _, _, _, _),
+ PINGROUP(156, ebi2, _, _, _, _, _, _),
+ PINGROUP(157, ebi2, _, _, _, _, _, _),
+ PINGROUP(158, ebi2, _, _, _, _, _, _),
PINGROUP(159, sdc1, _, _, _, _, _, _),
PINGROUP(160, sdc1, _, _, _, _, _, _),
PINGROUP(161, sdc1, _, _, _, _, _, _),
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8x74.c b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
index 46fe6ad5f97e..9eb63d3403d4 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
@@ -172,6 +172,8 @@ static const struct pinctrl_pin_desc msm8x74_pins[] = {
PINCTRL_PIN(149, "SDC2_CLK"),
PINCTRL_PIN(150, "SDC2_CMD"),
PINCTRL_PIN(151, "SDC2_DATA"),
+ PINCTRL_PIN(152, "HSIC_STROBE"),
+ PINCTRL_PIN(153, "HSIC_DATA"),
};
#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
@@ -328,6 +330,8 @@ static const unsigned int sdc1_data_pins[] = { 148 };
static const unsigned int sdc2_clk_pins[] = { 149 };
static const unsigned int sdc2_cmd_pins[] = { 150 };
static const unsigned int sdc2_data_pins[] = { 151 };
+static const unsigned int hsic_strobe_pins[] = { 152 };
+static const unsigned int hsic_data_pins[] = { 153 };
#define FUNCTION(fname) \
[MSM_MUX_##fname] = { \
@@ -399,6 +403,37 @@ static const unsigned int sdc2_data_pins[] = { 151 };
.intr_detection_width = -1, \
}
+#define HSIC_PINGROUP(pg_name, ctl) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = ARRAY_SIZE(pg_name##_pins), \
+ .funcs = (int[]){ \
+ MSM_MUX_gpio, \
+ MSM_MUX_hsic_ctl, \
+ }, \
+ .nfuncs = 2, \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = 25, \
+ .pull_bit = -1, \
+ .drv_bit = -1, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_target_kpss_val = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
/*
* TODO: Add the rest of the possible functions and fill out
* the pingroup table below.
@@ -509,6 +544,7 @@ enum msm8x74_functions {
MSM_MUX_fm,
MSM_MUX_wlan,
MSM_MUX_slimbus,
+ MSM_MUX_hsic_ctl,
MSM_MUX_NA,
};
@@ -534,7 +570,8 @@ static const char * const gpio_groups[] = {
"gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
"gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
"gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
- "gpio141", "gpio142", "gpio143", "gpio144", "gpio145"
+ "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "hsic_data",
+ "hsic_strobe",
};
static const char * const blsp_uart1_groups[] = {
@@ -754,6 +791,7 @@ static const char * const wlan_groups[] = {
};
static const char * const slimbus_groups[] = { "gpio70", "gpio71" };
+static const char * const hsic_ctl_groups[] = { "hsic_strobe", "hsic_data" };
static const struct msm_function msm8x74_functions[] = {
FUNCTION(gpio),
@@ -861,6 +899,7 @@ static const struct msm_function msm8x74_functions[] = {
FUNCTION(fm),
FUNCTION(wlan),
FUNCTION(slimbus),
+ FUNCTION(hsic_ctl),
};
static const struct msm_pingroup msm8x74_groups[] = {
@@ -1016,6 +1055,8 @@ static const struct msm_pingroup msm8x74_groups[] = {
SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6),
SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3),
SDC_PINGROUP(sdc2_data, 0x2048, 9, 0),
+ HSIC_PINGROUP(hsic_strobe, 0x2050),
+ HSIC_PINGROUP(hsic_data, 0x2054),
};
#define NUM_GPIO_PINGROUPS 146
diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
index 9191727aff5e..0d1392fc32dd 100644
--- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
+++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
@@ -744,6 +744,7 @@ static int pm8xxx_pin_populate(struct pm8xxx_mpp *pctrl,
static const struct of_device_id pm8xxx_mpp_of_match[] = {
{ .compatible = "qcom,pm8018-mpp" },
{ .compatible = "qcom,pm8038-mpp" },
+ { .compatible = "qcom,pm8058-mpp" },
{ .compatible = "qcom,pm8917-mpp" },
{ .compatible = "qcom,pm8821-mpp" },
{ .compatible = "qcom,pm8921-mpp" },
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
index fb71fc3e5aa0..3000df80709f 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos5440.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
@@ -998,6 +998,7 @@ static struct platform_driver exynos5440_pinctrl_driver = {
.driver = {
.name = "exynos5440-pinctrl",
.of_match_table = exynos5440_pinctrl_dt_match,
+ .suppress_bind_attrs = true,
},
};
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index ed0b70881e19..513fe6b23248 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1274,6 +1274,7 @@ static struct platform_driver samsung_pinctrl_driver = {
.driver = {
.name = "samsung-pinctrl",
.of_match_table = samsung_pinctrl_dt_match,
+ .suppress_bind_attrs = true,
},
};
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 9b9cee06ec59..a3b82041b6a2 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -598,15 +598,6 @@ static int sh_pfc_probe(struct platform_device *pdev)
return 0;
}
-static int sh_pfc_remove(struct platform_device *pdev)
-{
-#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
- sh_pfc_unregister_gpiochip(platform_get_drvdata(pdev));
-#endif
-
- return 0;
-}
-
static const struct platform_device_id sh_pfc_id_table[] = {
#ifdef CONFIG_PINCTRL_PFC_SH7203
{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
@@ -650,7 +641,6 @@ static const struct platform_device_id sh_pfc_id_table[] = {
static struct platform_driver sh_pfc_driver = {
.probe = sh_pfc_probe,
- .remove = sh_pfc_remove,
.id_table = sh_pfc_id_table,
.driver = {
.name = DRV_NAME,
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index dc1b2adb24c5..0bbdea5849f4 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -10,50 +10,16 @@
#ifndef __SH_PFC_CORE_H__
#define __SH_PFC_CORE_H__
-#include <linux/compiler.h>
-#include <linux/spinlock.h>
#include <linux/types.h>
#include "sh_pfc.h"
-struct sh_pfc_window {
- phys_addr_t phys;
- void __iomem *virt;
- unsigned long size;
-};
-
-struct sh_pfc_chip;
-struct sh_pfc_pinctrl;
-
struct sh_pfc_pin_range {
u16 start;
u16 end;
};
-struct sh_pfc {
- struct device *dev;
- const struct sh_pfc_soc_info *info;
- spinlock_t lock;
-
- unsigned int num_windows;
- struct sh_pfc_window *windows;
- unsigned int num_irqs;
- unsigned int *irqs;
-
- struct sh_pfc_pin_range *ranges;
- unsigned int nr_ranges;
-
- unsigned int nr_gpio_pins;
-
- struct sh_pfc_chip *gpio;
-#ifdef CONFIG_SUPERH
- struct sh_pfc_chip *func;
-#endif
-
-};
-
int sh_pfc_register_gpiochip(struct sh_pfc *pfc);
-int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc);
int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
@@ -67,28 +33,4 @@ void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width,
int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
-extern const struct sh_pfc_soc_info emev2_pinmux_info;
-extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
-extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
-extern const struct sh_pfc_soc_info sh7203_pinmux_info;
-extern const struct sh_pfc_soc_info sh7264_pinmux_info;
-extern const struct sh_pfc_soc_info sh7269_pinmux_info;
-extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
-extern const struct sh_pfc_soc_info sh7720_pinmux_info;
-extern const struct sh_pfc_soc_info sh7722_pinmux_info;
-extern const struct sh_pfc_soc_info sh7723_pinmux_info;
-extern const struct sh_pfc_soc_info sh7724_pinmux_info;
-extern const struct sh_pfc_soc_info sh7734_pinmux_info;
-extern const struct sh_pfc_soc_info sh7757_pinmux_info;
-extern const struct sh_pfc_soc_info sh7785_pinmux_info;
-extern const struct sh_pfc_soc_info sh7786_pinmux_info;
-extern const struct sh_pfc_soc_info shx3_pinmux_info;
-
#endif /* __SH_PFC_CORE_H__ */
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 97dff6a09ff0..6b5422766f13 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -318,7 +318,7 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
if (ret < 0)
return ERR_PTR(ret);
- ret = gpiochip_add_data(&chip->gpio_chip, chip);
+ ret = devm_gpiochip_add_data(pfc->dev, &chip->gpio_chip, chip);
if (unlikely(ret < 0))
return ERR_PTR(ret);
@@ -399,18 +399,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
if (IS_ERR(chip))
return PTR_ERR(chip);
-
- pfc->func = chip;
#endif /* CONFIG_SUPERH */
return 0;
}
-
-int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
-{
- gpiochip_remove(&pfc->gpio->gpio_chip);
-#ifdef CONFIG_SUPERH
- gpiochip_remove(&pfc->func->gpio_chip);
-#endif
- return 0;
-}
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index d9d9228b15fa..ff5655dee67e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -21,7 +21,6 @@
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
-#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, pfx, sfx) \
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 7f7c8a6e76e8..35f436bcb849 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -22,7 +22,6 @@
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
-#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, pfx, sfx) \
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 411d0887ba19..18ef7042b3d1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -23,7 +23,7 @@
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/pinctrl/pinconf-generic.h>
-#include "core.h"
+
#include "sh_pfc.h"
#define PORT_GP_PUP_1(bank, pin, fn, sfx) \
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index eed8daa464cc..b769c05480da 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -24,7 +24,6 @@
#include <linux/io.h>
#include <linux/kernel.h>
-#include "core.h"
#include "sh_pfc.h"
/*
@@ -4696,47 +4695,6 @@ static const char * const vin3_groups[] = {
"vin3_clk",
};
-#define IOCTRL6 0x8c
-
-static int r8a7790_get_io_voltage(struct sh_pfc *pfc, unsigned int pin)
-{
- u32 data, mask;
-
- if (WARN(pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31), "invalid pin %#x", pin))
- return -EINVAL;
-
- data = ioread32(pfc->windows->virt + IOCTRL6),
- /* Bits in IOCTRL6 are numbered in opposite order to pins */
- mask = 0x80000000 >> (pin & 0x1f);
-
- return (data & mask) ? 3300 : 1800;
-}
-
-static int r8a7790_set_io_voltage(struct sh_pfc *pfc, unsigned int pin, u16 mV)
-{
- u32 data, mask;
-
- if (WARN(pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31), "invalid pin %#x", pin))
- return -EINVAL;
-
- if (mV != 1800 && mV != 3300)
- return -EINVAL;
-
- data = ioread32(pfc->windows->virt + IOCTRL6);
- /* Bits in IOCTRL6 are numbered in opposite order to pins */
- mask = 0x80000000 >> (pin & 0x1f);
-
- if (mV == 3300)
- data |= mask;
- else
- data &= ~mask;
-
- iowrite32(~data, pfc->windows->virt); /* unlock reg */
- iowrite32(data, pfc->windows->virt + IOCTRL6);
-
- return 0;
-}
-
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
@@ -5736,14 +5694,23 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
-static const struct sh_pfc_soc_operations pinmux_ops = {
- .get_io_voltage = r8a7790_get_io_voltage,
- .set_io_voltage = r8a7790_set_io_voltage,
+static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+{
+ if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
+ return -EINVAL;
+
+ *pocctrl = 0xe606008c;
+
+ return 31 - (pin & 0x1f);
+}
+
+static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
+ .pin_to_pocctrl = r8a7790_pin_to_pocctrl,
};
const struct sh_pfc_soc_info r8a7790_pinmux_info = {
.name = "r8a77900_pfc",
- .ops = &pinmux_ops,
+ .ops = &r8a7790_pinmux_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 01abbd5b4e49..0c1a60c9a844 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -11,7 +11,6 @@
#include <linux/kernel.h>
-#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, sfx) \
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 44632b1a5c97..b74cdd310d83 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -17,8 +17,12 @@
PORT_GP_CFG_16(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_15(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
- PORT_GP_CFG_16(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
- PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \
+ PORT_GP_CFG_1(3, 12, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_1(3, 13, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_1(3, 14, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_1(3, 15, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \
PORT_GP_CFG_26(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_32(6, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_4(7, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
@@ -552,6 +556,9 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(AVS2),
PINMUX_SINGLE(HDMI0_CEC),
PINMUX_SINGLE(HDMI1_CEC),
+ PINMUX_SINGLE(I2C_SEL_0_1),
+ PINMUX_SINGLE(I2C_SEL_3_1),
+ PINMUX_SINGLE(I2C_SEL_5_1),
PINMUX_SINGLE(MSIOF0_RXD),
PINMUX_SINGLE(MSIOF0_SCK),
PINMUX_SINGLE(MSIOF0_TXD),
@@ -1401,11 +1408,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
-
- /* I2C */
- PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
- PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
- PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
};
static const struct sh_pfc_pin pinmux_pins[] = {
@@ -1654,6 +1656,221 @@ static const unsigned int canfd1_data_mux[] = {
CANFD1_TX_MARK, CANFD1_RX_MARK,
};
+/* - DRIF0 --------------------------------------------------------------- */
+static const unsigned int drif0_ctrl_a_pins[] = {
+ /* CLK, SYNC */
+ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
+};
+static const unsigned int drif0_ctrl_a_mux[] = {
+ RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
+};
+static const unsigned int drif0_data0_a_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(6, 10),
+};
+static const unsigned int drif0_data0_a_mux[] = {
+ RIF0_D0_A_MARK,
+};
+static const unsigned int drif0_data1_a_pins[] = {
+ /* D1 */
+ RCAR_GP_PIN(6, 7),
+};
+static const unsigned int drif0_data1_a_mux[] = {
+ RIF0_D1_A_MARK,
+};
+static const unsigned int drif0_ctrl_b_pins[] = {
+ /* CLK, SYNC */
+ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
+};
+static const unsigned int drif0_ctrl_b_mux[] = {
+ RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
+};
+static const unsigned int drif0_data0_b_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(5, 1),
+};
+static const unsigned int drif0_data0_b_mux[] = {
+ RIF0_D0_B_MARK,
+};
+static const unsigned int drif0_data1_b_pins[] = {
+ /* D1 */
+ RCAR_GP_PIN(5, 2),
+};
+static const unsigned int drif0_data1_b_mux[] = {
+ RIF0_D1_B_MARK,
+};
+static const unsigned int drif0_ctrl_c_pins[] = {
+ /* CLK, SYNC */
+ RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
+};
+static const unsigned int drif0_ctrl_c_mux[] = {
+ RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
+};
+static const unsigned int drif0_data0_c_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(5, 13),
+};
+static const unsigned int drif0_data0_c_mux[] = {
+ RIF0_D0_C_MARK,
+};
+static const unsigned int drif0_data1_c_pins[] = {
+ /* D1 */
+ RCAR_GP_PIN(5, 14),
+};
+static const unsigned int drif0_data1_c_mux[] = {
+ RIF0_D1_C_MARK,
+};
+/* - DRIF1 --------------------------------------------------------------- */
+static const unsigned int drif1_ctrl_a_pins[] = {
+ /* CLK, SYNC */
+ RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
+};
+static const unsigned int drif1_ctrl_a_mux[] = {
+ RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
+};
+static const unsigned int drif1_data0_a_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(6, 19),
+};
+static const unsigned int drif1_data0_a_mux[] = {
+ RIF1_D0_A_MARK,
+};
+static const unsigned int drif1_data1_a_pins[] = {
+ /* D1 */
+ RCAR_GP_PIN(6, 20),
+};
+static const unsigned int drif1_data1_a_mux[] = {
+ RIF1_D1_A_MARK,
+};
+static const unsigned int drif1_ctrl_b_pins[] = {
+ /* CLK, SYNC */
+ RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
+};
+static const unsigned int drif1_ctrl_b_mux[] = {
+ RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
+};
+static const unsigned int drif1_data0_b_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(5, 7),
+};
+static const unsigned int drif1_data0_b_mux[] = {
+ RIF1_D0_B_MARK,
+};
+static const unsigned int drif1_data1_b_pins[] = {
+ /* D1 */
+ RCAR_GP_PIN(5, 8),
+};
+static const unsigned int drif1_data1_b_mux[] = {
+ RIF1_D1_B_MARK,
+};
+static const unsigned int drif1_ctrl_c_pins[] = {
+ /* CLK, SYNC */
+ RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
+};
+static const unsigned int drif1_ctrl_c_mux[] = {
+ RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
+};
+static const unsigned int drif1_data0_c_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(5, 6),
+};
+static const unsigned int drif1_data0_c_mux[] = {
+ RIF1_D0_C_MARK,
+};
+static const unsigned int drif1_data1_c_pins[] = {
+ /* D1 */
+ RCAR_GP_PIN(5, 10),
+};
+static const unsigned int drif1_data1_c_mux[] = {
+ RIF1_D1_C_MARK,
+};
+/* - DRIF2 --------------------------------------------------------------- */
+static const unsigned int drif2_ctrl_a_pins[] = {
+ /* CLK, SYNC */
+ RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
+};
+static const unsigned int drif2_ctrl_a_mux[] = {
+ RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
+};
+static const unsigned int drif2_data0_a_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(6, 7),
+};
+static const unsigned int drif2_data0_a_mux[] = {
+ RIF2_D0_A_MARK,
+};
+static const unsigned int drif2_data1_a_pins[] = {
+ /* D1 */
+ RCAR_GP_PIN(6, 10),
+};
+static const unsigned int drif2_data1_a_mux[] = {
+ RIF2_D1_A_MARK,
+};
+static const unsigned int drif2_ctrl_b_pins[] = {
+ /* CLK, SYNC */
+ RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
+};
+static const unsigned int drif2_ctrl_b_mux[] = {
+ RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
+};
+static const unsigned int drif2_data0_b_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(6, 30),
+};
+static const unsigned int drif2_data0_b_mux[] = {
+ RIF2_D0_B_MARK,
+};
+static const unsigned int drif2_data1_b_pins[] = {
+ /* D1 */
+ RCAR_GP_PIN(6, 31),
+};
+static const unsigned int drif2_data1_b_mux[] = {
+ RIF2_D1_B_MARK,
+};
+/* - DRIF3 --------------------------------------------------------------- */
+static const unsigned int drif3_ctrl_a_pins[] = {
+ /* CLK, SYNC */
+ RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
+};
+static const unsigned int drif3_ctrl_a_mux[] = {
+ RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
+};
+static const unsigned int drif3_data0_a_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(6, 19),
+};
+static const unsigned int drif3_data0_a_mux[] = {
+ RIF3_D0_A_MARK,
+};
+static const unsigned int drif3_data1_a_pins[] = {
+ /* D1 */
+ RCAR_GP_PIN(6, 20),
+};
+static const unsigned int drif3_data1_a_mux[] = {
+ RIF3_D1_A_MARK,
+};
+static const unsigned int drif3_ctrl_b_pins[] = {
+ /* CLK, SYNC */
+ RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
+};
+static const unsigned int drif3_ctrl_b_mux[] = {
+ RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
+};
+static const unsigned int drif3_data0_b_pins[] = {
+ /* D0 */
+ RCAR_GP_PIN(6, 28),
+};
+static const unsigned int drif3_data0_b_mux[] = {
+ RIF3_D0_B_MARK,
+};
+static const unsigned int drif3_data1_b_pins[] = {
+ /* D1 */
+ RCAR_GP_PIN(6, 29),
+};
+static const unsigned int drif3_data1_b_mux[] = {
+ RIF3_D1_B_MARK,
+};
+
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
/* RX, TX */
@@ -3346,6 +3563,36 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(canfd0_data_a),
SH_PFC_PIN_GROUP(canfd0_data_b),
SH_PFC_PIN_GROUP(canfd1_data),
+ SH_PFC_PIN_GROUP(drif0_ctrl_a),
+ SH_PFC_PIN_GROUP(drif0_data0_a),
+ SH_PFC_PIN_GROUP(drif0_data1_a),
+ SH_PFC_PIN_GROUP(drif0_ctrl_b),
+ SH_PFC_PIN_GROUP(drif0_data0_b),
+ SH_PFC_PIN_GROUP(drif0_data1_b),
+ SH_PFC_PIN_GROUP(drif0_ctrl_c),
+ SH_PFC_PIN_GROUP(drif0_data0_c),
+ SH_PFC_PIN_GROUP(drif0_data1_c),
+ SH_PFC_PIN_GROUP(drif1_ctrl_a),
+ SH_PFC_PIN_GROUP(drif1_data0_a),
+ SH_PFC_PIN_GROUP(drif1_data1_a),
+ SH_PFC_PIN_GROUP(drif1_ctrl_b),
+ SH_PFC_PIN_GROUP(drif1_data0_b),
+ SH_PFC_PIN_GROUP(drif1_data1_b),
+ SH_PFC_PIN_GROUP(drif1_ctrl_c),
+ SH_PFC_PIN_GROUP(drif1_data0_c),
+ SH_PFC_PIN_GROUP(drif1_data1_c),
+ SH_PFC_PIN_GROUP(drif2_ctrl_a),
+ SH_PFC_PIN_GROUP(drif2_data0_a),
+ SH_PFC_PIN_GROUP(drif2_data1_a),
+ SH_PFC_PIN_GROUP(drif2_ctrl_b),
+ SH_PFC_PIN_GROUP(drif2_data0_b),
+ SH_PFC_PIN_GROUP(drif2_data1_b),
+ SH_PFC_PIN_GROUP(drif3_ctrl_a),
+ SH_PFC_PIN_GROUP(drif3_data0_a),
+ SH_PFC_PIN_GROUP(drif3_data1_a),
+ SH_PFC_PIN_GROUP(drif3_ctrl_b),
+ SH_PFC_PIN_GROUP(drif3_data0_b),
+ SH_PFC_PIN_GROUP(drif3_data1_b),
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(hscif0_ctrl),
@@ -3629,6 +3876,48 @@ static const char * const canfd1_groups[] = {
"canfd1_data",
};
+static const char * const drif0_groups[] = {
+ "drif0_ctrl_a",
+ "drif0_data0_a",
+ "drif0_data1_a",
+ "drif0_ctrl_b",
+ "drif0_data0_b",
+ "drif0_data1_b",
+ "drif0_ctrl_c",
+ "drif0_data0_c",
+ "drif0_data1_c",
+};
+
+static const char * const drif1_groups[] = {
+ "drif1_ctrl_a",
+ "drif1_data0_a",
+ "drif1_data1_a",
+ "drif1_ctrl_b",
+ "drif1_data0_b",
+ "drif1_data1_b",
+ "drif1_ctrl_c",
+ "drif1_data0_c",
+ "drif1_data1_c",
+};
+
+static const char * const drif2_groups[] = {
+ "drif2_ctrl_a",
+ "drif2_data0_a",
+ "drif2_data1_a",
+ "drif2_ctrl_b",
+ "drif2_data0_b",
+ "drif2_data1_b",
+};
+
+static const char * const drif3_groups[] = {
+ "drif3_ctrl_a",
+ "drif3_data0_a",
+ "drif3_data1_a",
+ "drif3_ctrl_b",
+ "drif3_data0_b",
+ "drif3_data1_b",
+};
+
static const char * const hscif0_groups[] = {
"hscif0_data",
"hscif0_clk",
@@ -3972,6 +4261,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
+ SH_PFC_FUNCTION(drif0),
+ SH_PFC_FUNCTION(drif1),
+ SH_PFC_FUNCTION(drif2),
+ SH_PFC_FUNCTION(drif3),
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
@@ -4765,8 +5058,28 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
{ },
};
+static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
+{
+ int bit = -EINVAL;
+
+ *pocctrl = 0xe6060380;
+
+ if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
+ bit = pin & 0x1f;
+
+ if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
+ bit = (pin & 0x1f) + 12;
+
+ return bit;
+}
+
+static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
+ .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
+};
+
const struct sh_pfc_soc_info r8a7795_pinmux_info = {
.name = "r8a77950_pfc",
+ .ops = &r8a7795_pinmux_ops,
.unlock_reg = 0xe6060000, /* PMMR */
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
index 0555a1fe076e..6d8c31caefc1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
@@ -1625,7 +1625,6 @@ static const struct pinmux_func pinmux_func_gpios[] = {
GPIO_FN(VBIOS_CS),
/* PTW (mobule: LBSC, EVC, SCIF) */
- GPIO_FN(A16),
GPIO_FN(A15),
GPIO_FN(A14),
GPIO_FN(A13),
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index fdb445d68b9a..e208ee04a9f4 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -632,19 +632,21 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
}
case PIN_CONFIG_POWER_SOURCE: {
- int ret;
+ u32 pocctrl, val;
+ int bit;
- if (!pfc->info->ops || !pfc->info->ops->get_io_voltage)
+ if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
return -ENOTSUPP;
+ bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
+ if (WARN(bit < 0, "invalid pin %#x", _pin))
+ return bit;
+
spin_lock_irqsave(&pfc->lock, flags);
- ret = pfc->info->ops->get_io_voltage(pfc, _pin);
+ val = sh_pfc_read_reg(pfc, pocctrl, 32);
spin_unlock_irqrestore(&pfc->lock, flags);
- if (ret < 0)
- return ret;
-
- *config = ret;
+ *config = (val & BIT(bit)) ? 3300 : 1800;
break;
}
@@ -696,20 +698,29 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
}
case PIN_CONFIG_POWER_SOURCE: {
- unsigned int arg =
- pinconf_to_config_argument(configs[i]);
- int ret;
+ unsigned int mV = pinconf_to_config_argument(configs[i]);
+ u32 pocctrl, val;
+ int bit;
- if (!pfc->info->ops || !pfc->info->ops->set_io_voltage)
+ if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
return -ENOTSUPP;
+ bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
+ if (WARN(bit < 0, "invalid pin %#x", _pin))
+ return bit;
+
+ if (mV != 1800 && mV != 3300)
+ return -EINVAL;
+
spin_lock_irqsave(&pfc->lock, flags);
- ret = pfc->info->ops->set_io_voltage(pfc, _pin, arg);
+ val = sh_pfc_read_reg(pfc, pocctrl, 32);
+ if (mV == 3300)
+ val |= BIT(bit);
+ else
+ val &= ~BIT(bit);
+ sh_pfc_write_reg(pfc, pocctrl, 32, val);
spin_unlock_irqrestore(&pfc->lock, flags);
- if (ret)
- return ret;
-
break;
}
@@ -803,8 +814,5 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
pmx->pctl_desc.npins = pfc->info->nr_pins;
pmx->pctl = devm_pinctrl_register(pfc->dev, &pmx->pctl_desc, pmx);
- if (IS_ERR(pmx->pctl))
- return PTR_ERR(pmx->pctl);
-
- return 0;
+ return PTR_ERR_OR_ZERO(pmx->pctl);
}
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 656ea32f776c..5e966c09434d 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -13,6 +13,7 @@
#include <linux/bug.h>
#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/spinlock.h>
#include <linux/stringify.h>
enum {
@@ -182,16 +183,38 @@ struct pinmux_range {
u16 force;
};
-struct sh_pfc;
+struct sh_pfc_window {
+ phys_addr_t phys;
+ void __iomem *virt;
+ unsigned long size;
+};
+
+struct sh_pfc_pin_range;
+
+struct sh_pfc {
+ struct device *dev;
+ const struct sh_pfc_soc_info *info;
+ spinlock_t lock;
+
+ unsigned int num_windows;
+ struct sh_pfc_window *windows;
+ unsigned int num_irqs;
+ unsigned int *irqs;
+
+ struct sh_pfc_pin_range *ranges;
+ unsigned int nr_ranges;
+
+ unsigned int nr_gpio_pins;
+
+ struct sh_pfc_chip *gpio;
+};
struct sh_pfc_soc_operations {
int (*init)(struct sh_pfc *pfc);
unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias);
- int (*get_io_voltage)(struct sh_pfc *pfc, unsigned int pin);
- int (*set_io_voltage)(struct sh_pfc *pfc, unsigned int pin,
- u16 voltage_mV);
+ int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
};
struct sh_pfc_soc_info {
@@ -227,6 +250,30 @@ struct sh_pfc_soc_info {
u32 unlock_reg;
};
+extern const struct sh_pfc_soc_info emev2_pinmux_info;
+extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
+extern const struct sh_pfc_soc_info sh7203_pinmux_info;
+extern const struct sh_pfc_soc_info sh7264_pinmux_info;
+extern const struct sh_pfc_soc_info sh7269_pinmux_info;
+extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
+extern const struct sh_pfc_soc_info sh7720_pinmux_info;
+extern const struct sh_pfc_soc_info sh7722_pinmux_info;
+extern const struct sh_pfc_soc_info sh7723_pinmux_info;
+extern const struct sh_pfc_soc_info sh7724_pinmux_info;
+extern const struct sh_pfc_soc_info sh7734_pinmux_info;
+extern const struct sh_pfc_soc_info sh7757_pinmux_info;
+extern const struct sh_pfc_soc_info sh7785_pinmux_info;
+extern const struct sh_pfc_soc_info sh7786_pinmux_info;
+extern const struct sh_pfc_soc_info shx3_pinmux_info;
+
/* -----------------------------------------------------------------------------
* Helper macros to create pin and port lists
*/
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c
index 168c0f5d4079..19952f73fa8c 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas7.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c
@@ -5424,8 +5424,10 @@ static int atlas7_pinmux_probe(struct platform_device *pdev)
if (ret)
return ret;
pmx->sys2pci_base = devm_ioremap_resource(&pdev->dev, &res);
- if (IS_ERR(pmx->sys2pci_base))
+ if (IS_ERR(pmx->sys2pci_base)) {
+ of_node_put(sys2pci_np);
return -ENOMEM;
+ }
pmx->dev = &pdev->dev;
diff --git a/drivers/pinctrl/stm32/Kconfig b/drivers/pinctrl/stm32/Kconfig
index 0f28841b2332..4c40dae384d1 100644
--- a/drivers/pinctrl/stm32/Kconfig
+++ b/drivers/pinctrl/stm32/Kconfig
@@ -13,4 +13,10 @@ config PINCTRL_STM32F429
default MACH_STM32F429
select PINCTRL_STM32
+config PINCTRL_STM32F746
+ bool "STMicroelectronics STM32F746 pin control" if COMPILE_TEST && !MACH_STM32F746
+ depends on OF
+ default MACH_STM32F746
+ select PINCTRL_STM32
+
endif
diff --git a/drivers/pinctrl/stm32/Makefile b/drivers/pinctrl/stm32/Makefile
index fc17d4238845..4a1ee748441f 100644
--- a/drivers/pinctrl/stm32/Makefile
+++ b/drivers/pinctrl/stm32/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_PINCTRL_STM32) += pinctrl-stm32.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_STM32F429) += pinctrl-stm32f429.o
+obj-$(CONFIG_PINCTRL_STM32F746) += pinctrl-stm32f746.o
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index ae9fab82a1b9..4ae596bf19b5 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -638,8 +638,8 @@ static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
return (val >> (offset * 2));
}
-static bool stm32_pconf_input_get(struct stm32_gpio_bank *bank,
- unsigned int offset)
+static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
+ unsigned int offset, bool dir)
{
unsigned long flags;
u32 val;
@@ -647,23 +647,12 @@ static bool stm32_pconf_input_get(struct stm32_gpio_bank *bank,
clk_enable(bank->clk);
spin_lock_irqsave(&bank->lock, flags);
- val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
-
- spin_unlock_irqrestore(&bank->lock, flags);
- clk_disable(bank->clk);
-
- return val;
-}
-
-static bool stm32_pconf_output_get(struct stm32_gpio_bank *bank,
- unsigned int offset)
-{
- unsigned long flags;
- u32 val;
-
- clk_enable(bank->clk);
- spin_lock_irqsave(&bank->lock, flags);
- val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & BIT(offset));
+ if (dir)
+ val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
+ BIT(offset));
+ else
+ val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
+ BIT(offset));
spin_unlock_irqrestore(&bank->lock, flags);
clk_disable(bank->clk);
@@ -772,7 +761,7 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
switch (mode) {
/* input */
case 0:
- val = stm32_pconf_input_get(bank, offset);
+ val = stm32_pconf_get(bank, offset, true);
seq_printf(s, "- %s - %s",
val ? "high" : "low",
biasing[bias]);
@@ -782,7 +771,7 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
case 1:
drive = stm32_pconf_get_driving(bank, offset);
speed = stm32_pconf_get_speed(bank, offset);
- val = stm32_pconf_output_get(bank, offset);
+ val = stm32_pconf_get(bank, offset, false);
seq_printf(s, "- %s - %s - %s - %s %s",
val ? "high" : "low",
drive ? "open drain" : "push pull",
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32f746.c b/drivers/pinctrl/stm32/pinctrl-stm32f746.c
new file mode 100644
index 000000000000..c0b4462ce97e
--- /dev/null
+++ b/drivers/pinctrl/stm32/pinctrl-stm32f746.c
@@ -0,0 +1,1681 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
+ * License terms: GNU General Public License (GPL), version 2
+ */
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-stm32.h"
+
+static const struct stm32_desc_pin stm32f746_pins[] = {
+ STM32_PIN(
+ PINCTRL_PIN(0, "PA0"),
+ STM32_FUNCTION(0, "GPIOA0"),
+ STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
+ STM32_FUNCTION(3, "TIM5_CH1"),
+ STM32_FUNCTION(4, "TIM8_ETR"),
+ STM32_FUNCTION(8, "USART2_CTS"),
+ STM32_FUNCTION(9, "UART4_TX"),
+ STM32_FUNCTION(11, "SAI2_SD_B"),
+ STM32_FUNCTION(12, "ETH_MII_CRS"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(1, "PA1"),
+ STM32_FUNCTION(0, "GPIOA1"),
+ STM32_FUNCTION(2, "TIM2_CH2"),
+ STM32_FUNCTION(3, "TIM5_CH2"),
+ STM32_FUNCTION(8, "USART2_RTS"),
+ STM32_FUNCTION(9, "UART4_RX"),
+ STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
+ STM32_FUNCTION(11, "SAI2_MCLK_B"),
+ STM32_FUNCTION(12, "ETH_MII_RX_CLK ETH_RMII_REF_CLK"),
+ STM32_FUNCTION(15, "LCD_R2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(2, "PA2"),
+ STM32_FUNCTION(0, "GPIOA2"),
+ STM32_FUNCTION(2, "TIM2_CH3"),
+ STM32_FUNCTION(3, "TIM5_CH3"),
+ STM32_FUNCTION(4, "TIM9_CH1"),
+ STM32_FUNCTION(8, "USART2_TX"),
+ STM32_FUNCTION(9, "SAI2_SCK_B"),
+ STM32_FUNCTION(12, "ETH_MDIO"),
+ STM32_FUNCTION(15, "LCD_R1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(3, "PA3"),
+ STM32_FUNCTION(0, "GPIOA3"),
+ STM32_FUNCTION(2, "TIM2_CH4"),
+ STM32_FUNCTION(3, "TIM5_CH4"),
+ STM32_FUNCTION(4, "TIM9_CH2"),
+ STM32_FUNCTION(8, "USART2_RX"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D0"),
+ STM32_FUNCTION(12, "ETH_MII_COL"),
+ STM32_FUNCTION(15, "LCD_B5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(4, "PA4"),
+ STM32_FUNCTION(0, "GPIOA4"),
+ STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
+ STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(8, "USART2_CK"),
+ STM32_FUNCTION(13, "OTG_HS_SOF"),
+ STM32_FUNCTION(14, "DCMI_HSYNC"),
+ STM32_FUNCTION(15, "LCD_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(5, "PA5"),
+ STM32_FUNCTION(0, "GPIOA5"),
+ STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
+ STM32_FUNCTION(4, "TIM8_CH1N"),
+ STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_CK"),
+ STM32_FUNCTION(15, "LCD_R4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(6, "PA6"),
+ STM32_FUNCTION(0, "GPIOA6"),
+ STM32_FUNCTION(2, "TIM1_BKIN"),
+ STM32_FUNCTION(3, "TIM3_CH1"),
+ STM32_FUNCTION(4, "TIM8_BKIN"),
+ STM32_FUNCTION(6, "SPI1_MISO"),
+ STM32_FUNCTION(10, "TIM13_CH1"),
+ STM32_FUNCTION(14, "DCMI_PIXCLK"),
+ STM32_FUNCTION(15, "LCD_G2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(7, "PA7"),
+ STM32_FUNCTION(0, "GPIOA7"),
+ STM32_FUNCTION(2, "TIM1_CH1N"),
+ STM32_FUNCTION(3, "TIM3_CH2"),
+ STM32_FUNCTION(4, "TIM8_CH1N"),
+ STM32_FUNCTION(6, "SPI1_MOSI I2S1_SD"),
+ STM32_FUNCTION(10, "TIM14_CH1"),
+ STM32_FUNCTION(12, "ETH_MII_RX_DV ETH_RMII_CRS_DV"),
+ STM32_FUNCTION(13, "FMC_SDNWE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(8, "PA8"),
+ STM32_FUNCTION(0, "GPIOA8"),
+ STM32_FUNCTION(1, "MCO1"),
+ STM32_FUNCTION(2, "TIM1_CH1"),
+ STM32_FUNCTION(4, "TIM8_BKIN2"),
+ STM32_FUNCTION(5, "I2C3_SCL"),
+ STM32_FUNCTION(8, "USART1_CK"),
+ STM32_FUNCTION(11, "OTG_FS_SOF"),
+ STM32_FUNCTION(15, "LCD_R6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(9, "PA9"),
+ STM32_FUNCTION(0, "GPIOA9"),
+ STM32_FUNCTION(2, "TIM1_CH2"),
+ STM32_FUNCTION(5, "I2C3_SMBA"),
+ STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(8, "USART1_TX"),
+ STM32_FUNCTION(14, "DCMI_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(10, "PA10"),
+ STM32_FUNCTION(0, "GPIOA10"),
+ STM32_FUNCTION(2, "TIM1_CH3"),
+ STM32_FUNCTION(8, "USART1_RX"),
+ STM32_FUNCTION(11, "OTG_FS_ID"),
+ STM32_FUNCTION(14, "DCMI_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(11, "PA11"),
+ STM32_FUNCTION(0, "GPIOA11"),
+ STM32_FUNCTION(2, "TIM1_CH4"),
+ STM32_FUNCTION(8, "USART1_CTS"),
+ STM32_FUNCTION(10, "CAN1_RX"),
+ STM32_FUNCTION(11, "OTG_FS_DM"),
+ STM32_FUNCTION(15, "LCD_R4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(12, "PA12"),
+ STM32_FUNCTION(0, "GPIOA12"),
+ STM32_FUNCTION(2, "TIM1_ETR"),
+ STM32_FUNCTION(8, "USART1_RTS"),
+ STM32_FUNCTION(9, "SAI2_FS_B"),
+ STM32_FUNCTION(10, "CAN1_TX"),
+ STM32_FUNCTION(11, "OTG_FS_DP"),
+ STM32_FUNCTION(15, "LCD_R5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(13, "PA13"),
+ STM32_FUNCTION(0, "GPIOA13"),
+ STM32_FUNCTION(1, "JTMS SWDIO"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(14, "PA14"),
+ STM32_FUNCTION(0, "GPIOA14"),
+ STM32_FUNCTION(1, "JTCK SWCLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(15, "PA15"),
+ STM32_FUNCTION(0, "GPIOA15"),
+ STM32_FUNCTION(1, "JTDI"),
+ STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
+ STM32_FUNCTION(5, "HDMI_CEC"),
+ STM32_FUNCTION(6, "SPI1_NSS I2S1_WS"),
+ STM32_FUNCTION(7, "SPI3_NSS I2S3_WS"),
+ STM32_FUNCTION(9, "UART4_RTS"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(16, "PB0"),
+ STM32_FUNCTION(0, "GPIOB0"),
+ STM32_FUNCTION(2, "TIM1_CH2N"),
+ STM32_FUNCTION(3, "TIM3_CH3"),
+ STM32_FUNCTION(4, "TIM8_CH2N"),
+ STM32_FUNCTION(9, "UART4_CTS"),
+ STM32_FUNCTION(10, "LCD_R3"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D1"),
+ STM32_FUNCTION(12, "ETH_MII_RXD2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(17, "PB1"),
+ STM32_FUNCTION(0, "GPIOB1"),
+ STM32_FUNCTION(2, "TIM1_CH3N"),
+ STM32_FUNCTION(3, "TIM3_CH4"),
+ STM32_FUNCTION(4, "TIM8_CH3N"),
+ STM32_FUNCTION(10, "LCD_R6"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D2"),
+ STM32_FUNCTION(12, "ETH_MII_RXD3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(18, "PB2"),
+ STM32_FUNCTION(0, "GPIOB2"),
+ STM32_FUNCTION(7, "SAI1_SD_A"),
+ STM32_FUNCTION(8, "SPI3_MOSI I2S3_SD"),
+ STM32_FUNCTION(10, "QUADSPI_CLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(19, "PB3"),
+ STM32_FUNCTION(0, "GPIOB3"),
+ STM32_FUNCTION(1, "JTDO TRACESWO"),
+ STM32_FUNCTION(2, "TIM2_CH2"),
+ STM32_FUNCTION(6, "SPI1_SCK I2S1_CK"),
+ STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(20, "PB4"),
+ STM32_FUNCTION(0, "GPIOB4"),
+ STM32_FUNCTION(1, "NJTRST"),
+ STM32_FUNCTION(3, "TIM3_CH1"),
+ STM32_FUNCTION(6, "SPI1_MISO"),
+ STM32_FUNCTION(7, "SPI3_MISO"),
+ STM32_FUNCTION(8, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(21, "PB5"),
+ STM32_FUNCTION(0, "GPIOB5"),
+ STM32_FUNCTION(3, "TIM3_CH2"),
+ STM32_FUNCTION(5, "I2C1_SMBA"),
+ STM32_FUNCTION(6, "SPI1_MOSI I2S1_SD"),
+ STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"),
+ STM32_FUNCTION(10, "CAN2_RX"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D7"),
+ STM32_FUNCTION(12, "ETH_PPS_OUT"),
+ STM32_FUNCTION(13, "FMC_SDCKE1"),
+ STM32_FUNCTION(14, "DCMI_D10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(22, "PB6"),
+ STM32_FUNCTION(0, "GPIOB6"),
+ STM32_FUNCTION(3, "TIM4_CH1"),
+ STM32_FUNCTION(4, "HDMI_CEC"),
+ STM32_FUNCTION(5, "I2C1_SCL"),
+ STM32_FUNCTION(8, "USART1_TX"),
+ STM32_FUNCTION(10, "CAN2_TX"),
+ STM32_FUNCTION(11, "QUADSPI_BK1_NCS"),
+ STM32_FUNCTION(13, "FMC_SDNE1"),
+ STM32_FUNCTION(14, "DCMI_D5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(23, "PB7"),
+ STM32_FUNCTION(0, "GPIOB7"),
+ STM32_FUNCTION(3, "TIM4_CH2"),
+ STM32_FUNCTION(5, "I2C1_SDA"),
+ STM32_FUNCTION(8, "USART1_RX"),
+ STM32_FUNCTION(13, "FMC_NL"),
+ STM32_FUNCTION(14, "DCMI_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(24, "PB8"),
+ STM32_FUNCTION(0, "GPIOB8"),
+ STM32_FUNCTION(3, "TIM4_CH3"),
+ STM32_FUNCTION(4, "TIM10_CH1"),
+ STM32_FUNCTION(5, "I2C1_SCL"),
+ STM32_FUNCTION(10, "CAN1_RX"),
+ STM32_FUNCTION(12, "ETH_MII_TXD3"),
+ STM32_FUNCTION(13, "SDMMC1_D4"),
+ STM32_FUNCTION(14, "DCMI_D6"),
+ STM32_FUNCTION(15, "LCD_B6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(25, "PB9"),
+ STM32_FUNCTION(0, "GPIOB9"),
+ STM32_FUNCTION(3, "TIM4_CH4"),
+ STM32_FUNCTION(4, "TIM11_CH1"),
+ STM32_FUNCTION(5, "I2C1_SDA"),
+ STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(10, "CAN1_TX"),
+ STM32_FUNCTION(13, "SDMMC1_D5"),
+ STM32_FUNCTION(14, "DCMI_D7"),
+ STM32_FUNCTION(15, "LCD_B7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(26, "PB10"),
+ STM32_FUNCTION(0, "GPIOB10"),
+ STM32_FUNCTION(2, "TIM2_CH3"),
+ STM32_FUNCTION(5, "I2C2_SCL"),
+ STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(8, "USART3_TX"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D3"),
+ STM32_FUNCTION(12, "ETH_MII_RX_ER"),
+ STM32_FUNCTION(15, "LCD_G4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(27, "PB11"),
+ STM32_FUNCTION(0, "GPIOB11"),
+ STM32_FUNCTION(2, "TIM2_CH4"),
+ STM32_FUNCTION(5, "I2C2_SDA"),
+ STM32_FUNCTION(8, "USART3_RX"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D4"),
+ STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
+ STM32_FUNCTION(15, "LCD_G5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(28, "PB12"),
+ STM32_FUNCTION(0, "GPIOB12"),
+ STM32_FUNCTION(2, "TIM1_BKIN"),
+ STM32_FUNCTION(5, "I2C2_SMBA"),
+ STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(8, "USART3_CK"),
+ STM32_FUNCTION(10, "CAN2_RX"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D5"),
+ STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
+ STM32_FUNCTION(13, "OTG_HS_ID"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(29, "PB13"),
+ STM32_FUNCTION(0, "GPIOB13"),
+ STM32_FUNCTION(2, "TIM1_CH1N"),
+ STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(8, "USART3_CTS"),
+ STM32_FUNCTION(10, "CAN2_TX"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_D6"),
+ STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(30, "PB14"),
+ STM32_FUNCTION(0, "GPIOB14"),
+ STM32_FUNCTION(2, "TIM1_CH2N"),
+ STM32_FUNCTION(4, "TIM8_CH2N"),
+ STM32_FUNCTION(6, "SPI2_MISO"),
+ STM32_FUNCTION(8, "USART3_RTS"),
+ STM32_FUNCTION(10, "TIM12_CH1"),
+ STM32_FUNCTION(13, "OTG_HS_DM"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(31, "PB15"),
+ STM32_FUNCTION(0, "GPIOB15"),
+ STM32_FUNCTION(1, "RTC_REFIN"),
+ STM32_FUNCTION(2, "TIM1_CH3N"),
+ STM32_FUNCTION(4, "TIM8_CH3N"),
+ STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
+ STM32_FUNCTION(10, "TIM12_CH2"),
+ STM32_FUNCTION(13, "OTG_HS_DP"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(32, "PC0"),
+ STM32_FUNCTION(0, "GPIOC0"),
+ STM32_FUNCTION(9, "SAI2_FS_B"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_STP"),
+ STM32_FUNCTION(13, "FMC_SDNWE"),
+ STM32_FUNCTION(15, "LCD_R5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(33, "PC1"),
+ STM32_FUNCTION(0, "GPIOC1"),
+ STM32_FUNCTION(1, "TRACED0"),
+ STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
+ STM32_FUNCTION(7, "SAI1_SD_A"),
+ STM32_FUNCTION(12, "ETH_MDC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(34, "PC2"),
+ STM32_FUNCTION(0, "GPIOC2"),
+ STM32_FUNCTION(6, "SPI2_MISO"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
+ STM32_FUNCTION(12, "ETH_MII_TXD2"),
+ STM32_FUNCTION(13, "FMC_SDNE0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(35, "PC3"),
+ STM32_FUNCTION(0, "GPIOC3"),
+ STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
+ STM32_FUNCTION(12, "ETH_MII_TX_CLK"),
+ STM32_FUNCTION(13, "FMC_SDCKE0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(36, "PC4"),
+ STM32_FUNCTION(0, "GPIOC4"),
+ STM32_FUNCTION(6, "I2S1_MCK"),
+ STM32_FUNCTION(9, "SPDIFRX_IN2"),
+ STM32_FUNCTION(12, "ETH_MII_RXD0 ETH_RMII_RXD0"),
+ STM32_FUNCTION(13, "FMC_SDNE0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(37, "PC5"),
+ STM32_FUNCTION(0, "GPIOC5"),
+ STM32_FUNCTION(9, "SPDIFRX_IN3"),
+ STM32_FUNCTION(12, "ETH_MII_RXD1 ETH_RMII_RXD1"),
+ STM32_FUNCTION(13, "FMC_SDCKE0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(38, "PC6"),
+ STM32_FUNCTION(0, "GPIOC6"),
+ STM32_FUNCTION(3, "TIM3_CH1"),
+ STM32_FUNCTION(4, "TIM8_CH1"),
+ STM32_FUNCTION(6, "I2S2_MCK"),
+ STM32_FUNCTION(9, "USART6_TX"),
+ STM32_FUNCTION(13, "SDMMC1_D6"),
+ STM32_FUNCTION(14, "DCMI_D0"),
+ STM32_FUNCTION(15, "LCD_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(39, "PC7"),
+ STM32_FUNCTION(0, "GPIOC7"),
+ STM32_FUNCTION(3, "TIM3_CH2"),
+ STM32_FUNCTION(4, "TIM8_CH2"),
+ STM32_FUNCTION(7, "I2S3_MCK"),
+ STM32_FUNCTION(9, "USART6_RX"),
+ STM32_FUNCTION(13, "SDMMC1_D7"),
+ STM32_FUNCTION(14, "DCMI_D1"),
+ STM32_FUNCTION(15, "LCD_G6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(40, "PC8"),
+ STM32_FUNCTION(0, "GPIOC8"),
+ STM32_FUNCTION(1, "TRACED1"),
+ STM32_FUNCTION(3, "TIM3_CH3"),
+ STM32_FUNCTION(4, "TIM8_CH3"),
+ STM32_FUNCTION(8, "UART5_RTS"),
+ STM32_FUNCTION(9, "USART6_CK"),
+ STM32_FUNCTION(13, "SDMMC1_D0"),
+ STM32_FUNCTION(14, "DCMI_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(41, "PC9"),
+ STM32_FUNCTION(0, "GPIOC9"),
+ STM32_FUNCTION(1, "MCO2"),
+ STM32_FUNCTION(3, "TIM3_CH4"),
+ STM32_FUNCTION(4, "TIM8_CH4"),
+ STM32_FUNCTION(5, "I2C3_SDA"),
+ STM32_FUNCTION(6, "I2S_CKIN"),
+ STM32_FUNCTION(8, "UART5_CTS"),
+ STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
+ STM32_FUNCTION(13, "SDMMC1_D1"),
+ STM32_FUNCTION(14, "DCMI_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(42, "PC10"),
+ STM32_FUNCTION(0, "GPIOC10"),
+ STM32_FUNCTION(7, "SPI3_SCK I2S3_CK"),
+ STM32_FUNCTION(8, "USART3_TX"),
+ STM32_FUNCTION(9, "UART4_TX"),
+ STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
+ STM32_FUNCTION(13, "SDMMC1_D2"),
+ STM32_FUNCTION(14, "DCMI_D8"),
+ STM32_FUNCTION(15, "LCD_R2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(43, "PC11"),
+ STM32_FUNCTION(0, "GPIOC11"),
+ STM32_FUNCTION(7, "SPI3_MISO"),
+ STM32_FUNCTION(8, "USART3_RX"),
+ STM32_FUNCTION(9, "UART4_RX"),
+ STM32_FUNCTION(10, "QUADSPI_BK2_NCS"),
+ STM32_FUNCTION(13, "SDMMC1_D3"),
+ STM32_FUNCTION(14, "DCMI_D4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(44, "PC12"),
+ STM32_FUNCTION(0, "GPIOC12"),
+ STM32_FUNCTION(1, "TRACED3"),
+ STM32_FUNCTION(7, "SPI3_MOSI I2S3_SD"),
+ STM32_FUNCTION(8, "USART3_CK"),
+ STM32_FUNCTION(9, "UART5_TX"),
+ STM32_FUNCTION(13, "SDMMC1_CK"),
+ STM32_FUNCTION(14, "DCMI_D9"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(45, "PC13"),
+ STM32_FUNCTION(0, "GPIOC13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(46, "PC14"),
+ STM32_FUNCTION(0, "GPIOC14"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(47, "PC15"),
+ STM32_FUNCTION(0, "GPIOC15"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(48, "PD0"),
+ STM32_FUNCTION(0, "GPIOD0"),
+ STM32_FUNCTION(10, "CAN1_RX"),
+ STM32_FUNCTION(13, "FMC_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(49, "PD1"),
+ STM32_FUNCTION(0, "GPIOD1"),
+ STM32_FUNCTION(10, "CAN1_TX"),
+ STM32_FUNCTION(13, "FMC_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(50, "PD2"),
+ STM32_FUNCTION(0, "GPIOD2"),
+ STM32_FUNCTION(1, "TRACED2"),
+ STM32_FUNCTION(3, "TIM3_ETR"),
+ STM32_FUNCTION(9, "UART5_RX"),
+ STM32_FUNCTION(13, "SDMMC1_CMD"),
+ STM32_FUNCTION(14, "DCMI_D11"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(51, "PD3"),
+ STM32_FUNCTION(0, "GPIOD3"),
+ STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(8, "USART2_CTS"),
+ STM32_FUNCTION(13, "FMC_CLK"),
+ STM32_FUNCTION(14, "DCMI_D5"),
+ STM32_FUNCTION(15, "LCD_G7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(52, "PD4"),
+ STM32_FUNCTION(0, "GPIOD4"),
+ STM32_FUNCTION(8, "USART2_RTS"),
+ STM32_FUNCTION(13, "FMC_NOE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(53, "PD5"),
+ STM32_FUNCTION(0, "GPIOD5"),
+ STM32_FUNCTION(8, "USART2_TX"),
+ STM32_FUNCTION(13, "FMC_NWE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(54, "PD6"),
+ STM32_FUNCTION(0, "GPIOD6"),
+ STM32_FUNCTION(6, "SPI3_MOSI I2S3_SD"),
+ STM32_FUNCTION(7, "SAI1_SD_A"),
+ STM32_FUNCTION(8, "USART2_RX"),
+ STM32_FUNCTION(13, "FMC_NWAIT"),
+ STM32_FUNCTION(14, "DCMI_D10"),
+ STM32_FUNCTION(15, "LCD_B2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(55, "PD7"),
+ STM32_FUNCTION(0, "GPIOD7"),
+ STM32_FUNCTION(8, "USART2_CK"),
+ STM32_FUNCTION(9, "SPDIFRX_IN0"),
+ STM32_FUNCTION(13, "FMC_NE1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(56, "PD8"),
+ STM32_FUNCTION(0, "GPIOD8"),
+ STM32_FUNCTION(8, "USART3_TX"),
+ STM32_FUNCTION(9, "SPDIFRX_IN1"),
+ STM32_FUNCTION(13, "FMC_D13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(57, "PD9"),
+ STM32_FUNCTION(0, "GPIOD9"),
+ STM32_FUNCTION(8, "USART3_RX"),
+ STM32_FUNCTION(13, "FMC_D14"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(58, "PD10"),
+ STM32_FUNCTION(0, "GPIOD10"),
+ STM32_FUNCTION(8, "USART3_CK"),
+ STM32_FUNCTION(13, "FMC_D15"),
+ STM32_FUNCTION(15, "LCD_B3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(59, "PD11"),
+ STM32_FUNCTION(0, "GPIOD11"),
+ STM32_FUNCTION(5, "I2C4_SMBA"),
+ STM32_FUNCTION(8, "USART3_CTS"),
+ STM32_FUNCTION(10, "QUADSPI_BK1_IO0"),
+ STM32_FUNCTION(11, "SAI2_SD_A"),
+ STM32_FUNCTION(13, "FMC_A16 FMC_CLE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(60, "PD12"),
+ STM32_FUNCTION(0, "GPIOD12"),
+ STM32_FUNCTION(3, "TIM4_CH1"),
+ STM32_FUNCTION(4, "LPTIM1_IN1"),
+ STM32_FUNCTION(5, "I2C4_SCL"),
+ STM32_FUNCTION(8, "USART3_RTS"),
+ STM32_FUNCTION(10, "QUADSPI_BK1_IO1"),
+ STM32_FUNCTION(11, "SAI2_FS_A"),
+ STM32_FUNCTION(13, "FMC_A17 FMC_ALE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(61, "PD13"),
+ STM32_FUNCTION(0, "GPIOD13"),
+ STM32_FUNCTION(3, "TIM4_CH2"),
+ STM32_FUNCTION(4, "LPTIM1_OUT"),
+ STM32_FUNCTION(5, "I2C4_SDA"),
+ STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
+ STM32_FUNCTION(11, "SAI2_SCK_A"),
+ STM32_FUNCTION(13, "FMC_A18"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(62, "PD14"),
+ STM32_FUNCTION(0, "GPIOD14"),
+ STM32_FUNCTION(3, "TIM4_CH3"),
+ STM32_FUNCTION(9, "UART8_CTS"),
+ STM32_FUNCTION(13, "FMC_D0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(63, "PD15"),
+ STM32_FUNCTION(0, "GPIOD15"),
+ STM32_FUNCTION(3, "TIM4_CH4"),
+ STM32_FUNCTION(9, "UART8_RTS"),
+ STM32_FUNCTION(13, "FMC_D1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(64, "PE0"),
+ STM32_FUNCTION(0, "GPIOE0"),
+ STM32_FUNCTION(3, "TIM4_ETR"),
+ STM32_FUNCTION(4, "LPTIM1_ETR"),
+ STM32_FUNCTION(9, "UART8_RX"),
+ STM32_FUNCTION(11, "SAI2_MCLK_A"),
+ STM32_FUNCTION(13, "FMC_NBL0"),
+ STM32_FUNCTION(14, "DCMI_D2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(65, "PE1"),
+ STM32_FUNCTION(0, "GPIOE1"),
+ STM32_FUNCTION(4, "LPTIM1_IN2"),
+ STM32_FUNCTION(9, "UART8_TX"),
+ STM32_FUNCTION(13, "FMC_NBL1"),
+ STM32_FUNCTION(14, "DCMI_D3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(66, "PE2"),
+ STM32_FUNCTION(0, "GPIOE2"),
+ STM32_FUNCTION(1, "TRACECLK"),
+ STM32_FUNCTION(6, "SPI4_SCK"),
+ STM32_FUNCTION(7, "SAI1_MCLK_A"),
+ STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
+ STM32_FUNCTION(12, "ETH_MII_TXD3"),
+ STM32_FUNCTION(13, "FMC_A23"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(67, "PE3"),
+ STM32_FUNCTION(0, "GPIOE3"),
+ STM32_FUNCTION(1, "TRACED0"),
+ STM32_FUNCTION(7, "SAI1_SD_B"),
+ STM32_FUNCTION(13, "FMC_A19"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(68, "PE4"),
+ STM32_FUNCTION(0, "GPIOE4"),
+ STM32_FUNCTION(1, "TRACED1"),
+ STM32_FUNCTION(6, "SPI4_NSS"),
+ STM32_FUNCTION(7, "SAI1_FS_A"),
+ STM32_FUNCTION(13, "FMC_A20"),
+ STM32_FUNCTION(14, "DCMI_D4"),
+ STM32_FUNCTION(15, "LCD_B0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(69, "PE5"),
+ STM32_FUNCTION(0, "GPIOE5"),
+ STM32_FUNCTION(1, "TRACED2"),
+ STM32_FUNCTION(4, "TIM9_CH1"),
+ STM32_FUNCTION(6, "SPI4_MISO"),
+ STM32_FUNCTION(7, "SAI1_SCK_A"),
+ STM32_FUNCTION(13, "FMC_A21"),
+ STM32_FUNCTION(14, "DCMI_D6"),
+ STM32_FUNCTION(15, "LCD_G0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(70, "PE6"),
+ STM32_FUNCTION(0, "GPIOE6"),
+ STM32_FUNCTION(1, "TRACED3"),
+ STM32_FUNCTION(2, "TIM1_BKIN2"),
+ STM32_FUNCTION(4, "TIM9_CH2"),
+ STM32_FUNCTION(6, "SPI4_MOSI"),
+ STM32_FUNCTION(7, "SAI1_SD_A"),
+ STM32_FUNCTION(11, "SAI2_MCLK_B"),
+ STM32_FUNCTION(13, "FMC_A22"),
+ STM32_FUNCTION(14, "DCMI_D7"),
+ STM32_FUNCTION(15, "LCD_G1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(71, "PE7"),
+ STM32_FUNCTION(0, "GPIOE7"),
+ STM32_FUNCTION(2, "TIM1_ETR"),
+ STM32_FUNCTION(9, "UART7_RX"),
+ STM32_FUNCTION(11, "QUADSPI_BK2_IO0"),
+ STM32_FUNCTION(13, "FMC_D4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(72, "PE8"),
+ STM32_FUNCTION(0, "GPIOE8"),
+ STM32_FUNCTION(2, "TIM1_CH1N"),
+ STM32_FUNCTION(9, "UART7_TX"),
+ STM32_FUNCTION(11, "QUADSPI_BK2_IO1"),
+ STM32_FUNCTION(13, "FMC_D5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(73, "PE9"),
+ STM32_FUNCTION(0, "GPIOE9"),
+ STM32_FUNCTION(2, "TIM1_CH1"),
+ STM32_FUNCTION(9, "UART7_RTS"),
+ STM32_FUNCTION(11, "QUADSPI_BK2_IO2"),
+ STM32_FUNCTION(13, "FMC_D6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(74, "PE10"),
+ STM32_FUNCTION(0, "GPIOE10"),
+ STM32_FUNCTION(2, "TIM1_CH2N"),
+ STM32_FUNCTION(9, "UART7_CTS"),
+ STM32_FUNCTION(11, "QUADSPI_BK2_IO3"),
+ STM32_FUNCTION(13, "FMC_D7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(75, "PE11"),
+ STM32_FUNCTION(0, "GPIOE11"),
+ STM32_FUNCTION(2, "TIM1_CH2"),
+ STM32_FUNCTION(6, "SPI4_NSS"),
+ STM32_FUNCTION(11, "SAI2_SD_B"),
+ STM32_FUNCTION(13, "FMC_D8"),
+ STM32_FUNCTION(15, "LCD_G3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(76, "PE12"),
+ STM32_FUNCTION(0, "GPIOE12"),
+ STM32_FUNCTION(2, "TIM1_CH3N"),
+ STM32_FUNCTION(6, "SPI4_SCK"),
+ STM32_FUNCTION(11, "SAI2_SCK_B"),
+ STM32_FUNCTION(13, "FMC_D9"),
+ STM32_FUNCTION(15, "LCD_B4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(77, "PE13"),
+ STM32_FUNCTION(0, "GPIOE13"),
+ STM32_FUNCTION(2, "TIM1_CH3"),
+ STM32_FUNCTION(6, "SPI4_MISO"),
+ STM32_FUNCTION(11, "SAI2_FS_B"),
+ STM32_FUNCTION(13, "FMC_D10"),
+ STM32_FUNCTION(15, "LCD_DE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(78, "PE14"),
+ STM32_FUNCTION(0, "GPIOE14"),
+ STM32_FUNCTION(2, "TIM1_CH4"),
+ STM32_FUNCTION(6, "SPI4_MOSI"),
+ STM32_FUNCTION(11, "SAI2_MCLK_B"),
+ STM32_FUNCTION(13, "FMC_D11"),
+ STM32_FUNCTION(15, "LCD_CLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(79, "PE15"),
+ STM32_FUNCTION(0, "GPIOE15"),
+ STM32_FUNCTION(2, "TIM1_BKIN"),
+ STM32_FUNCTION(13, "FMC_D12"),
+ STM32_FUNCTION(15, "LCD_R7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(80, "PF0"),
+ STM32_FUNCTION(0, "GPIOF0"),
+ STM32_FUNCTION(5, "I2C2_SDA"),
+ STM32_FUNCTION(13, "FMC_A0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(81, "PF1"),
+ STM32_FUNCTION(0, "GPIOF1"),
+ STM32_FUNCTION(5, "I2C2_SCL"),
+ STM32_FUNCTION(13, "FMC_A1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(82, "PF2"),
+ STM32_FUNCTION(0, "GPIOF2"),
+ STM32_FUNCTION(5, "I2C2_SMBA"),
+ STM32_FUNCTION(13, "FMC_A2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(83, "PF3"),
+ STM32_FUNCTION(0, "GPIOF3"),
+ STM32_FUNCTION(13, "FMC_A3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(84, "PF4"),
+ STM32_FUNCTION(0, "GPIOF4"),
+ STM32_FUNCTION(13, "FMC_A4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(85, "PF5"),
+ STM32_FUNCTION(0, "GPIOF5"),
+ STM32_FUNCTION(13, "FMC_A5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(86, "PF6"),
+ STM32_FUNCTION(0, "GPIOF6"),
+ STM32_FUNCTION(4, "TIM10_CH1"),
+ STM32_FUNCTION(6, "SPI5_NSS"),
+ STM32_FUNCTION(7, "SAI1_SD_B"),
+ STM32_FUNCTION(9, "UART7_RX"),
+ STM32_FUNCTION(10, "QUADSPI_BK1_IO3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(87, "PF7"),
+ STM32_FUNCTION(0, "GPIOF7"),
+ STM32_FUNCTION(4, "TIM11_CH1"),
+ STM32_FUNCTION(6, "SPI5_SCK"),
+ STM32_FUNCTION(7, "SAI1_MCLK_B"),
+ STM32_FUNCTION(9, "UART7_TX"),
+ STM32_FUNCTION(10, "QUADSPI_BK1_IO2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(88, "PF8"),
+ STM32_FUNCTION(0, "GPIOF8"),
+ STM32_FUNCTION(6, "SPI5_MISO"),
+ STM32_FUNCTION(7, "SAI1_SCK_B"),
+ STM32_FUNCTION(9, "UART7_RTS"),
+ STM32_FUNCTION(10, "TIM13_CH1"),
+ STM32_FUNCTION(11, "QUADSPI_BK1_IO0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(89, "PF9"),
+ STM32_FUNCTION(0, "GPIOF9"),
+ STM32_FUNCTION(6, "SPI5_MOSI"),
+ STM32_FUNCTION(7, "SAI1_FS_B"),
+ STM32_FUNCTION(9, "UART7_CTS"),
+ STM32_FUNCTION(10, "TIM14_CH1"),
+ STM32_FUNCTION(11, "QUADSPI_BK1_IO1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(90, "PF10"),
+ STM32_FUNCTION(0, "GPIOF10"),
+ STM32_FUNCTION(14, "DCMI_D11"),
+ STM32_FUNCTION(15, "LCD_DE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(91, "PF11"),
+ STM32_FUNCTION(0, "GPIOF11"),
+ STM32_FUNCTION(6, "SPI5_MOSI"),
+ STM32_FUNCTION(11, "SAI2_SD_B"),
+ STM32_FUNCTION(13, "FMC_SDNRAS"),
+ STM32_FUNCTION(14, "DCMI_D12"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(92, "PF12"),
+ STM32_FUNCTION(0, "GPIOF12"),
+ STM32_FUNCTION(13, "FMC_A6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(93, "PF13"),
+ STM32_FUNCTION(0, "GPIOF13"),
+ STM32_FUNCTION(5, "I2C4_SMBA"),
+ STM32_FUNCTION(13, "FMC_A7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(94, "PF14"),
+ STM32_FUNCTION(0, "GPIOF14"),
+ STM32_FUNCTION(5, "I2C4_SCL"),
+ STM32_FUNCTION(13, "FMC_A8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(95, "PF15"),
+ STM32_FUNCTION(0, "GPIOF15"),
+ STM32_FUNCTION(5, "I2C4_SDA"),
+ STM32_FUNCTION(13, "FMC_A9"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(96, "PG0"),
+ STM32_FUNCTION(0, "GPIOG0"),
+ STM32_FUNCTION(13, "FMC_A10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(97, "PG1"),
+ STM32_FUNCTION(0, "GPIOG1"),
+ STM32_FUNCTION(13, "FMC_A11"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(98, "PG2"),
+ STM32_FUNCTION(0, "GPIOG2"),
+ STM32_FUNCTION(13, "FMC_A12"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(99, "PG3"),
+ STM32_FUNCTION(0, "GPIOG3"),
+ STM32_FUNCTION(13, "FMC_A13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(100, "PG4"),
+ STM32_FUNCTION(0, "GPIOG4"),
+ STM32_FUNCTION(13, "FMC_A14 FMC_BA0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(101, "PG5"),
+ STM32_FUNCTION(0, "GPIOG5"),
+ STM32_FUNCTION(13, "FMC_A15 FMC_BA1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(102, "PG6"),
+ STM32_FUNCTION(0, "GPIOG6"),
+ STM32_FUNCTION(14, "DCMI_D12"),
+ STM32_FUNCTION(15, "LCD_R7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(103, "PG7"),
+ STM32_FUNCTION(0, "GPIOG7"),
+ STM32_FUNCTION(9, "USART6_CK"),
+ STM32_FUNCTION(13, "FMC_INT"),
+ STM32_FUNCTION(14, "DCMI_D13"),
+ STM32_FUNCTION(15, "LCD_CLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(104, "PG8"),
+ STM32_FUNCTION(0, "GPIOG8"),
+ STM32_FUNCTION(6, "SPI6_NSS"),
+ STM32_FUNCTION(8, "SPDIFRX_IN2"),
+ STM32_FUNCTION(9, "USART6_RTS"),
+ STM32_FUNCTION(12, "ETH_PPS_OUT"),
+ STM32_FUNCTION(13, "FMC_SDCLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(105, "PG9"),
+ STM32_FUNCTION(0, "GPIOG9"),
+ STM32_FUNCTION(8, "SPDIFRX_IN3"),
+ STM32_FUNCTION(9, "USART6_RX"),
+ STM32_FUNCTION(10, "QUADSPI_BK2_IO2"),
+ STM32_FUNCTION(11, "SAI2_FS_B"),
+ STM32_FUNCTION(13, "FMC_NE2 FMC_NCE"),
+ STM32_FUNCTION(14, "DCMI_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(106, "PG10"),
+ STM32_FUNCTION(0, "GPIOG10"),
+ STM32_FUNCTION(10, "LCD_G3"),
+ STM32_FUNCTION(11, "SAI2_SD_B"),
+ STM32_FUNCTION(13, "FMC_NE3"),
+ STM32_FUNCTION(14, "DCMI_D2"),
+ STM32_FUNCTION(15, "LCD_B2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(107, "PG11"),
+ STM32_FUNCTION(0, "GPIOG11"),
+ STM32_FUNCTION(8, "SPDIFRX_IN0"),
+ STM32_FUNCTION(12, "ETH_MII_TX_EN ETH_RMII_TX_EN"),
+ STM32_FUNCTION(14, "DCMI_D3"),
+ STM32_FUNCTION(15, "LCD_B3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(108, "PG12"),
+ STM32_FUNCTION(0, "GPIOG12"),
+ STM32_FUNCTION(4, "LPTIM1_IN1"),
+ STM32_FUNCTION(6, "SPI6_MISO"),
+ STM32_FUNCTION(8, "SPDIFRX_IN1"),
+ STM32_FUNCTION(9, "USART6_RTS"),
+ STM32_FUNCTION(10, "LCD_B4"),
+ STM32_FUNCTION(13, "FMC_NE4"),
+ STM32_FUNCTION(15, "LCD_B1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(109, "PG13"),
+ STM32_FUNCTION(0, "GPIOG13"),
+ STM32_FUNCTION(1, "TRACED0"),
+ STM32_FUNCTION(4, "LPTIM1_OUT"),
+ STM32_FUNCTION(6, "SPI6_SCK"),
+ STM32_FUNCTION(9, "USART6_CTS"),
+ STM32_FUNCTION(12, "ETH_MII_TXD0 ETH_RMII_TXD0"),
+ STM32_FUNCTION(13, "FMC_A24"),
+ STM32_FUNCTION(15, "LCD_R0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(110, "PG14"),
+ STM32_FUNCTION(0, "GPIOG14"),
+ STM32_FUNCTION(1, "TRACED1"),
+ STM32_FUNCTION(4, "LPTIM1_ETR"),
+ STM32_FUNCTION(6, "SPI6_MOSI"),
+ STM32_FUNCTION(9, "USART6_TX"),
+ STM32_FUNCTION(10, "QUADSPI_BK2_IO3"),
+ STM32_FUNCTION(12, "ETH_MII_TXD1 ETH_RMII_TXD1"),
+ STM32_FUNCTION(13, "FMC_A25"),
+ STM32_FUNCTION(15, "LCD_B0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(111, "PG15"),
+ STM32_FUNCTION(0, "GPIOG15"),
+ STM32_FUNCTION(9, "USART6_CTS"),
+ STM32_FUNCTION(13, "FMC_SDNCAS"),
+ STM32_FUNCTION(14, "DCMI_D13"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(112, "PH0"),
+ STM32_FUNCTION(0, "GPIOH0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(113, "PH1"),
+ STM32_FUNCTION(0, "GPIOH1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(114, "PH2"),
+ STM32_FUNCTION(0, "GPIOH2"),
+ STM32_FUNCTION(4, "LPTIM1_IN2"),
+ STM32_FUNCTION(10, "QUADSPI_BK2_IO0"),
+ STM32_FUNCTION(11, "SAI2_SCK_B"),
+ STM32_FUNCTION(12, "ETH_MII_CRS"),
+ STM32_FUNCTION(13, "FMC_SDCKE0"),
+ STM32_FUNCTION(15, "LCD_R0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(115, "PH3"),
+ STM32_FUNCTION(0, "GPIOH3"),
+ STM32_FUNCTION(10, "QUADSPI_BK2_IO1"),
+ STM32_FUNCTION(11, "SAI2_MCLK_B"),
+ STM32_FUNCTION(12, "ETH_MII_COL"),
+ STM32_FUNCTION(13, "FMC_SDNE0"),
+ STM32_FUNCTION(15, "LCD_R1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(116, "PH4"),
+ STM32_FUNCTION(0, "GPIOH4"),
+ STM32_FUNCTION(5, "I2C2_SCL"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_NXT"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(117, "PH5"),
+ STM32_FUNCTION(0, "GPIOH5"),
+ STM32_FUNCTION(5, "I2C2_SDA"),
+ STM32_FUNCTION(6, "SPI5_NSS"),
+ STM32_FUNCTION(13, "FMC_SDNWE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(118, "PH6"),
+ STM32_FUNCTION(0, "GPIOH6"),
+ STM32_FUNCTION(5, "I2C2_SMBA"),
+ STM32_FUNCTION(6, "SPI5_SCK"),
+ STM32_FUNCTION(10, "TIM12_CH1"),
+ STM32_FUNCTION(12, "ETH_MII_RXD2"),
+ STM32_FUNCTION(13, "FMC_SDNE1"),
+ STM32_FUNCTION(14, "DCMI_D8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(119, "PH7"),
+ STM32_FUNCTION(0, "GPIOH7"),
+ STM32_FUNCTION(5, "I2C3_SCL"),
+ STM32_FUNCTION(6, "SPI5_MISO"),
+ STM32_FUNCTION(12, "ETH_MII_RXD3"),
+ STM32_FUNCTION(13, "FMC_SDCKE1"),
+ STM32_FUNCTION(14, "DCMI_D9"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(120, "PH8"),
+ STM32_FUNCTION(0, "GPIOH8"),
+ STM32_FUNCTION(5, "I2C3_SDA"),
+ STM32_FUNCTION(13, "FMC_D16"),
+ STM32_FUNCTION(14, "DCMI_HSYNC"),
+ STM32_FUNCTION(15, "LCD_R2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(121, "PH9"),
+ STM32_FUNCTION(0, "GPIOH9"),
+ STM32_FUNCTION(5, "I2C3_SMBA"),
+ STM32_FUNCTION(10, "TIM12_CH2"),
+ STM32_FUNCTION(13, "FMC_D17"),
+ STM32_FUNCTION(14, "DCMI_D0"),
+ STM32_FUNCTION(15, "LCD_R3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(122, "PH10"),
+ STM32_FUNCTION(0, "GPIOH10"),
+ STM32_FUNCTION(3, "TIM5_CH1"),
+ STM32_FUNCTION(5, "I2C4_SMBA"),
+ STM32_FUNCTION(13, "FMC_D18"),
+ STM32_FUNCTION(14, "DCMI_D1"),
+ STM32_FUNCTION(15, "LCD_R4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(123, "PH11"),
+ STM32_FUNCTION(0, "GPIOH11"),
+ STM32_FUNCTION(3, "TIM5_CH2"),
+ STM32_FUNCTION(5, "I2C4_SCL"),
+ STM32_FUNCTION(13, "FMC_D19"),
+ STM32_FUNCTION(14, "DCMI_D2"),
+ STM32_FUNCTION(15, "LCD_R5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(124, "PH12"),
+ STM32_FUNCTION(0, "GPIOH12"),
+ STM32_FUNCTION(3, "TIM5_CH3"),
+ STM32_FUNCTION(5, "I2C4_SDA"),
+ STM32_FUNCTION(13, "FMC_D20"),
+ STM32_FUNCTION(14, "DCMI_D3"),
+ STM32_FUNCTION(15, "LCD_R6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(125, "PH13"),
+ STM32_FUNCTION(0, "GPIOH13"),
+ STM32_FUNCTION(4, "TIM8_CH1N"),
+ STM32_FUNCTION(10, "CAN1_TX"),
+ STM32_FUNCTION(13, "FMC_D21"),
+ STM32_FUNCTION(15, "LCD_G2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(126, "PH14"),
+ STM32_FUNCTION(0, "GPIOH14"),
+ STM32_FUNCTION(4, "TIM8_CH2N"),
+ STM32_FUNCTION(13, "FMC_D22"),
+ STM32_FUNCTION(14, "DCMI_D4"),
+ STM32_FUNCTION(15, "LCD_G3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(127, "PH15"),
+ STM32_FUNCTION(0, "GPIOH15"),
+ STM32_FUNCTION(4, "TIM8_CH3N"),
+ STM32_FUNCTION(13, "FMC_D23"),
+ STM32_FUNCTION(14, "DCMI_D11"),
+ STM32_FUNCTION(15, "LCD_G4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(128, "PI0"),
+ STM32_FUNCTION(0, "GPIOI0"),
+ STM32_FUNCTION(3, "TIM5_CH4"),
+ STM32_FUNCTION(6, "SPI2_NSS I2S2_WS"),
+ STM32_FUNCTION(13, "FMC_D24"),
+ STM32_FUNCTION(14, "DCMI_D13"),
+ STM32_FUNCTION(15, "LCD_G5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(129, "PI1"),
+ STM32_FUNCTION(0, "GPIOI1"),
+ STM32_FUNCTION(4, "TIM8_BKIN2"),
+ STM32_FUNCTION(6, "SPI2_SCK I2S2_CK"),
+ STM32_FUNCTION(13, "FMC_D25"),
+ STM32_FUNCTION(14, "DCMI_D8"),
+ STM32_FUNCTION(15, "LCD_G6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(130, "PI2"),
+ STM32_FUNCTION(0, "GPIOI2"),
+ STM32_FUNCTION(4, "TIM8_CH4"),
+ STM32_FUNCTION(6, "SPI2_MISO"),
+ STM32_FUNCTION(13, "FMC_D26"),
+ STM32_FUNCTION(14, "DCMI_D9"),
+ STM32_FUNCTION(15, "LCD_G7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(131, "PI3"),
+ STM32_FUNCTION(0, "GPIOI3"),
+ STM32_FUNCTION(4, "TIM8_ETR"),
+ STM32_FUNCTION(6, "SPI2_MOSI I2S2_SD"),
+ STM32_FUNCTION(13, "FMC_D27"),
+ STM32_FUNCTION(14, "DCMI_D10"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(132, "PI4"),
+ STM32_FUNCTION(0, "GPIOI4"),
+ STM32_FUNCTION(4, "TIM8_BKIN"),
+ STM32_FUNCTION(11, "SAI2_MCLK_A"),
+ STM32_FUNCTION(13, "FMC_NBL2"),
+ STM32_FUNCTION(14, "DCMI_D5"),
+ STM32_FUNCTION(15, "LCD_B4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(133, "PI5"),
+ STM32_FUNCTION(0, "GPIOI5"),
+ STM32_FUNCTION(4, "TIM8_CH1"),
+ STM32_FUNCTION(11, "SAI2_SCK_A"),
+ STM32_FUNCTION(13, "FMC_NBL3"),
+ STM32_FUNCTION(14, "DCMI_VSYNC"),
+ STM32_FUNCTION(15, "LCD_B5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(134, "PI6"),
+ STM32_FUNCTION(0, "GPIOI6"),
+ STM32_FUNCTION(4, "TIM8_CH2"),
+ STM32_FUNCTION(11, "SAI2_SD_A"),
+ STM32_FUNCTION(13, "FMC_D28"),
+ STM32_FUNCTION(14, "DCMI_D6"),
+ STM32_FUNCTION(15, "LCD_B6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(135, "PI7"),
+ STM32_FUNCTION(0, "GPIOI7"),
+ STM32_FUNCTION(4, "TIM8_CH3"),
+ STM32_FUNCTION(11, "SAI2_FS_A"),
+ STM32_FUNCTION(13, "FMC_D29"),
+ STM32_FUNCTION(14, "DCMI_D7"),
+ STM32_FUNCTION(15, "LCD_B7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(136, "PI8"),
+ STM32_FUNCTION(0, "GPIOI8"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(137, "PI9"),
+ STM32_FUNCTION(0, "GPIOI9"),
+ STM32_FUNCTION(10, "CAN1_RX"),
+ STM32_FUNCTION(13, "FMC_D30"),
+ STM32_FUNCTION(15, "LCD_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(138, "PI10"),
+ STM32_FUNCTION(0, "GPIOI10"),
+ STM32_FUNCTION(12, "ETH_MII_RX_ER"),
+ STM32_FUNCTION(13, "FMC_D31"),
+ STM32_FUNCTION(15, "LCD_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(139, "PI11"),
+ STM32_FUNCTION(0, "GPIOI11"),
+ STM32_FUNCTION(11, "OTG_HS_ULPI_DIR"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(140, "PI12"),
+ STM32_FUNCTION(0, "GPIOI12"),
+ STM32_FUNCTION(15, "LCD_HSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(141, "PI13"),
+ STM32_FUNCTION(0, "GPIOI13"),
+ STM32_FUNCTION(15, "LCD_VSYNC"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(142, "PI14"),
+ STM32_FUNCTION(0, "GPIOI14"),
+ STM32_FUNCTION(15, "LCD_CLK"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(143, "PI15"),
+ STM32_FUNCTION(0, "GPIOI15"),
+ STM32_FUNCTION(15, "LCD_R0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(144, "PJ0"),
+ STM32_FUNCTION(0, "GPIOJ0"),
+ STM32_FUNCTION(15, "LCD_R1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(145, "PJ1"),
+ STM32_FUNCTION(0, "GPIOJ1"),
+ STM32_FUNCTION(15, "LCD_R2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(146, "PJ2"),
+ STM32_FUNCTION(0, "GPIOJ2"),
+ STM32_FUNCTION(15, "LCD_R3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(147, "PJ3"),
+ STM32_FUNCTION(0, "GPIOJ3"),
+ STM32_FUNCTION(15, "LCD_R4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(148, "PJ4"),
+ STM32_FUNCTION(0, "GPIOJ4"),
+ STM32_FUNCTION(15, "LCD_R5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(149, "PJ5"),
+ STM32_FUNCTION(0, "GPIOJ5"),
+ STM32_FUNCTION(15, "LCD_R6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(150, "PJ6"),
+ STM32_FUNCTION(0, "GPIOJ6"),
+ STM32_FUNCTION(15, "LCD_R7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(151, "PJ7"),
+ STM32_FUNCTION(0, "GPIOJ7"),
+ STM32_FUNCTION(15, "LCD_G0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(152, "PJ8"),
+ STM32_FUNCTION(0, "GPIOJ8"),
+ STM32_FUNCTION(15, "LCD_G1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(153, "PJ9"),
+ STM32_FUNCTION(0, "GPIOJ9"),
+ STM32_FUNCTION(15, "LCD_G2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(154, "PJ10"),
+ STM32_FUNCTION(0, "GPIOJ10"),
+ STM32_FUNCTION(15, "LCD_G3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(155, "PJ11"),
+ STM32_FUNCTION(0, "GPIOJ11"),
+ STM32_FUNCTION(15, "LCD_G4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(156, "PJ12"),
+ STM32_FUNCTION(0, "GPIOJ12"),
+ STM32_FUNCTION(15, "LCD_B0"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(157, "PJ13"),
+ STM32_FUNCTION(0, "GPIOJ13"),
+ STM32_FUNCTION(15, "LCD_B1"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(158, "PJ14"),
+ STM32_FUNCTION(0, "GPIOJ14"),
+ STM32_FUNCTION(15, "LCD_B2"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(159, "PJ15"),
+ STM32_FUNCTION(0, "GPIOJ15"),
+ STM32_FUNCTION(15, "LCD_B3"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(160, "PK0"),
+ STM32_FUNCTION(0, "GPIOK0"),
+ STM32_FUNCTION(15, "LCD_G5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(161, "PK1"),
+ STM32_FUNCTION(0, "GPIOK1"),
+ STM32_FUNCTION(15, "LCD_G6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(162, "PK2"),
+ STM32_FUNCTION(0, "GPIOK2"),
+ STM32_FUNCTION(15, "LCD_G7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(163, "PK3"),
+ STM32_FUNCTION(0, "GPIOK3"),
+ STM32_FUNCTION(15, "LCD_B4"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(164, "PK4"),
+ STM32_FUNCTION(0, "GPIOK4"),
+ STM32_FUNCTION(15, "LCD_B5"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(165, "PK5"),
+ STM32_FUNCTION(0, "GPIOK5"),
+ STM32_FUNCTION(15, "LCD_B6"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(166, "PK6"),
+ STM32_FUNCTION(0, "GPIOK6"),
+ STM32_FUNCTION(15, "LCD_B7"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+ STM32_PIN(
+ PINCTRL_PIN(167, "PK7"),
+ STM32_FUNCTION(0, "GPIOK7"),
+ STM32_FUNCTION(15, "LCD_DE"),
+ STM32_FUNCTION(16, "EVENTOUT"),
+ STM32_FUNCTION(17, "ANALOG")
+ ),
+};
+
+static struct stm32_pinctrl_match_data stm32f746_match_data = {
+ .pins = stm32f746_pins,
+ .npins = ARRAY_SIZE(stm32f746_pins),
+};
+
+static const struct of_device_id stm32f746_pctrl_match[] = {
+ {
+ .compatible = "st,stm32f746-pinctrl",
+ .data = &stm32f746_match_data,
+ },
+ { }
+};
+
+static struct platform_driver stm32f746_pinctrl_driver = {
+ .probe = stm32_pctl_probe,
+ .driver = {
+ .name = "stm32f746-pinctrl",
+ .of_match_table = stm32f746_pctrl_match,
+ },
+};
+builtin_platform_driver(stm32f746_pinctrl_driver);
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
index 55083d278bb1..ce483b03a263 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
@@ -180,17 +180,17 @@ static const struct sunxi_desc_pin sun8i_a23_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "nand"), /* DQS */
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
index 8b381d69df86..3040abe6f73a 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
@@ -140,17 +140,17 @@ static const struct sunxi_desc_pin sun8i_a33_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "nand"), /* DQS */
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
index 11760bbe9d51..26a2ad3b651f 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
@@ -219,17 +219,17 @@ static const struct sunxi_desc_pin sun8i_h3_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "nand"), /* DQS */
+ SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index 6e82b290cb4f..277622b4b6fb 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -632,11 +632,11 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
u32 val;
for (i = 0; i < pmx->soc->ngroups; ++i) {
- if (pmx->soc->groups[i].parked_reg >= 0) {
- g = &pmx->soc->groups[i];
- val = pmx_readl(pmx, g->parked_bank, g->parked_reg);
+ g = &pmx->soc->groups[i];
+ if (g->parked_bit >= 0) {
+ val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
val &= ~(1 << g->parked_bit);
- pmx_writel(pmx, val, g->parked_bank, g->parked_reg);
+ pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
}
}
}
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
index d2ced17382b5..33b17cb1471e 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.h
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
@@ -93,9 +93,7 @@ struct tegra_function {
* @tri_reg: Tri-state register offset.
* @tri_bank: Tri-state register bank.
* @tri_bit: Tri-state register bit.
- * @parked_reg: Parked register offset. -1 if unsupported.
- * @parked_bank: Parked register bank. 0 if unsupported.
- * @parked_bit: Parked register bit. 0 if unsupported.
+ * @parked_bit: Parked register bit. -1 if unsupported.
* @einput_bit: Enable-input register bit.
* @odrain_bit: Open-drain register bit.
* @lock_bit: Lock register bit.
@@ -138,12 +136,10 @@ struct tegra_pingroup {
s16 pupd_reg;
s16 tri_reg;
s16 drv_reg;
- s16 parked_reg;
u32 mux_bank:2;
u32 pupd_bank:2;
u32 tri_bank:2;
u32 drv_bank:2;
- u32 parked_bank:2;
s32 mux_bit:6;
s32 pupd_bit:6;
s32 tri_bit:6;
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra114.c b/drivers/pinctrl/tegra/pinctrl-tegra114.c
index 4851d169f4c7..952132ce5ea0 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra114.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra114.c
@@ -1578,7 +1578,7 @@ static struct tegra_function tegra114_functions[] = {
.lock_bit = 7, \
.ioreset_bit = PINGROUP_BIT_##ior(8), \
.rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
- .parked_reg = -1, \
+ .parked_bit = -1, \
.drv_reg = -1, \
}
@@ -1599,7 +1599,7 @@ static struct tegra_function tegra114_functions[] = {
.rcv_sel_bit = -1, \
.drv_reg = DRV_PINGROUP_REG(r), \
.drv_bank = 0, \
- .parked_reg = -1, \
+ .parked_bit = -1, \
.hsm_bit = hsm_b, \
.schmitt_bit = schmitt_b, \
.lpmd_bit = lpmd_b, \
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra124.c b/drivers/pinctrl/tegra/pinctrl-tegra124.c
index a0ce723a9482..bca239e3ae50 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra124.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra124.c
@@ -1747,7 +1747,7 @@ static struct tegra_function tegra124_functions[] = {
.lock_bit = 7, \
.ioreset_bit = PINGROUP_BIT_##ior(8), \
.rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
- .parked_reg = -1, \
+ .parked_bit = -1, \
.drv_reg = -1, \
}
@@ -1768,7 +1768,7 @@ static struct tegra_function tegra124_functions[] = {
.rcv_sel_bit = -1, \
.drv_reg = DRV_PINGROUP_REG(r), \
.drv_bank = 0, \
- .parked_reg = -1, \
+ .parked_bit = -1, \
.hsm_bit = hsm_b, \
.schmitt_bit = schmitt_b, \
.lpmd_bit = lpmd_b, \
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c
index 09bad6980ad1..ad62451a5a9b 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra20.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c
@@ -1994,7 +1994,7 @@ static struct tegra_function tegra20_functions[] = {
.tri_reg = ((tri_r) - TRISTATE_REG_A), \
.tri_bank = 0, \
.tri_bit = tri_b, \
- .parked_reg = -1, \
+ .parked_bit = -1, \
.einput_bit = -1, \
.odrain_bit = -1, \
.lock_bit = -1, \
@@ -2014,7 +2014,7 @@ static struct tegra_function tegra20_functions[] = {
.pupd_bank = 2, \
.pupd_bit = pupd_b, \
.drv_reg = -1, \
- .parked_reg = -1, \
+ .parked_bit = -1, \
}
/* Pin groups for drive strength registers (configurable version) */
@@ -2030,7 +2030,7 @@ static struct tegra_function tegra20_functions[] = {
.tri_reg = -1, \
.drv_reg = ((r) - PINGROUP_REG_A), \
.drv_bank = 3, \
- .parked_reg = -1, \
+ .parked_bit = -1, \
.hsm_bit = hsm_b, \
.schmitt_bit = schmitt_b, \
.lpmd_bit = lpmd_b, \
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c
index 2d856af389ef..2b70e93da9db 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra210.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c
@@ -1310,8 +1310,6 @@ static struct tegra_function tegra210_functions[] = {
.lock_bit = 7, \
.ioreset_bit = -1, \
.rcv_sel_bit = PINGROUP_BIT_##e_io_hv(10), \
- .parked_reg = PINGROUP_REG(r), \
- .parked_bank = 1, \
.parked_bit = 5, \
.hsm_bit = PINGROUP_BIT_##hsm(9), \
.schmitt_bit = 12, \
@@ -1345,7 +1343,7 @@ static struct tegra_function tegra210_functions[] = {
.rcv_sel_bit = -1, \
.drv_reg = DRV_PINGROUP_REG(r), \
.drv_bank = 0, \
- .parked_reg = -1, \
+ .parked_bit = -1, \
.hsm_bit = -1, \
.schmitt_bit = -1, \
.lpmd_bit = -1, \
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra30.c b/drivers/pinctrl/tegra/pinctrl-tegra30.c
index fb7817fea2d9..474ac6daf513 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra30.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra30.c
@@ -2139,7 +2139,7 @@ static struct tegra_function tegra30_functions[] = {
.lock_bit = 7, \
.ioreset_bit = PINGROUP_BIT_##ior(8), \
.rcv_sel_bit = -1, \
- .parked_reg = -1, \
+ .parked_bit = -1, \
.drv_reg = -1, \
}
@@ -2160,7 +2160,7 @@ static struct tegra_function tegra30_functions[] = {
.rcv_sel_bit = -1, \
.drv_reg = DRV_PINGROUP_REG(r), \
.drv_bank = 0, \
- .parked_reg = -1, \
+ .parked_bit = -1, \
.hsm_bit = hsm_b, \
.schmitt_bit = schmitt_b, \
.lpmd_bit = lpmd_b, \
diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index 0b40ded5738f..e077a9ec23d9 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -10,26 +10,34 @@ if PINCTRL_UNIPHIER
config PINCTRL_UNIPHIER_LD4
tristate "UniPhier PH1-LD4 SoC pinctrl driver"
- default y
+ default ARM
config PINCTRL_UNIPHIER_PRO4
tristate "UniPhier PH1-Pro4 SoC pinctrl driver"
- default y
+ default ARM
config PINCTRL_UNIPHIER_SLD8
tristate "UniPhier PH1-sLD8 SoC pinctrl driver"
- default y
+ default ARM
config PINCTRL_UNIPHIER_PRO5
tristate "UniPhier PH1-Pro5 SoC pinctrl driver"
- default y
+ default ARM
config PINCTRL_UNIPHIER_PXS2
tristate "UniPhier ProXstream2 SoC pinctrl driver"
- default y
+ default ARM
config PINCTRL_UNIPHIER_LD6B
tristate "UniPhier PH1-LD6b SoC pinctrl driver"
- default y
+ default ARM
+
+config PINCTRL_UNIPHIER_LD11
+ tristate "UniPhier PH1-LD11 SoC pinctrl driver"
+ default ARM64
+
+config PINCTRL_UNIPHIER_LD20
+ tristate "UniPhier PH1-LD20 SoC pinctrl driver"
+ default ARM64
endif
diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile
index 3b8f9ee0bb6f..9f4bc8aa6f68 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -6,3 +6,5 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8) += pinctrl-uniphier-sld8.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PRO5) += pinctrl-uniphier-pro5.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PXS2) += pinctrl-uniphier-pxs2.o
obj-$(CONFIG_PINCTRL_UNIPHIER_LD6B) += pinctrl-uniphier-ld6b.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_LD11) += pinctrl-uniphier-ld11.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_LD20) += pinctrl-uniphier-ld20.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index 967400971d45..9b2ee717bccc 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -14,6 +14,7 @@
#include <linux/export.h>
#include <linux/mfd/syscon.h>
+#include <linux/of.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
@@ -26,8 +27,10 @@
#include "pinctrl-uniphier.h"
struct uniphier_pinctrl_priv {
+ struct pinctrl_desc pctldesc;
struct pinctrl_dev *pctldev;
struct regmap *regmap;
+ unsigned int regbase;
struct uniphier_pinctrl_socdata *socdata;
};
@@ -63,16 +66,22 @@ static int uniphier_pctl_get_group_pins(struct pinctrl_dev *pctldev,
static void uniphier_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned offset)
{
- const struct pinctrl_pin_desc *pin = &pctldev->desc->pins[offset];
- const char *pull_dir, *drv_str;
+ const struct pin_desc *desc = pin_desc_get(pctldev, offset);
+ const char *pull_dir, *drv_type;
- switch (uniphier_pin_get_pull_dir(pin->drv_data)) {
+ switch (uniphier_pin_get_pull_dir(desc->drv_data)) {
case UNIPHIER_PIN_PULL_UP:
pull_dir = "UP";
break;
case UNIPHIER_PIN_PULL_DOWN:
pull_dir = "DOWN";
break;
+ case UNIPHIER_PIN_PULL_UP_FIXED:
+ pull_dir = "UP(FIXED)";
+ break;
+ case UNIPHIER_PIN_PULL_DOWN_FIXED:
+ pull_dir = "DOWN(FIXED)";
+ break;
case UNIPHIER_PIN_PULL_NONE:
pull_dir = "NONE";
break;
@@ -80,30 +89,33 @@ static void uniphier_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
BUG();
}
- switch (uniphier_pin_get_drv_str(pin->drv_data)) {
- case UNIPHIER_PIN_DRV_4_8:
- drv_str = "4/8(mA)";
+ switch (uniphier_pin_get_drv_type(desc->drv_data)) {
+ case UNIPHIER_PIN_DRV_1BIT:
+ drv_type = "4/8(mA)";
+ break;
+ case UNIPHIER_PIN_DRV_2BIT:
+ drv_type = "8/12/16/20(mA)";
break;
- case UNIPHIER_PIN_DRV_8_12_16_20:
- drv_str = "8/12/16/20(mA)";
+ case UNIPHIER_PIN_DRV_3BIT:
+ drv_type = "4/5/7/9/11/12/14/16(mA)";
break;
- case UNIPHIER_PIN_DRV_FIXED_4:
- drv_str = "4(mA)";
+ case UNIPHIER_PIN_DRV_FIXED4:
+ drv_type = "4(mA)";
break;
- case UNIPHIER_PIN_DRV_FIXED_5:
- drv_str = "5(mA)";
+ case UNIPHIER_PIN_DRV_FIXED5:
+ drv_type = "5(mA)";
break;
- case UNIPHIER_PIN_DRV_FIXED_8:
- drv_str = "8(mA)";
+ case UNIPHIER_PIN_DRV_FIXED8:
+ drv_type = "8(mA)";
break;
case UNIPHIER_PIN_DRV_NONE:
- drv_str = "NONE";
+ drv_type = "NONE";
break;
default:
BUG();
}
- seq_printf(s, " PULL_DIR=%s DRV_STR=%s", pull_dir, drv_str);
+ seq_printf(s, " PULL_DIR=%s DRV_TYPE=%s", pull_dir, drv_type);
}
#endif
@@ -119,12 +131,12 @@ static const struct pinctrl_ops uniphier_pctlops = {
};
static int uniphier_conf_pin_bias_get(struct pinctrl_dev *pctldev,
- const struct pinctrl_pin_desc *pin,
+ const struct pin_desc *desc,
enum pin_config_param param)
{
struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
enum uniphier_pin_pull_dir pull_dir =
- uniphier_pin_get_pull_dir(pin->drv_data);
+ uniphier_pin_get_pull_dir(desc->drv_data);
unsigned int pupdctrl, reg, shift, val;
unsigned int expected = 1;
int ret;
@@ -154,12 +166,12 @@ static int uniphier_conf_pin_bias_get(struct pinctrl_dev *pctldev,
BUG();
}
- pupdctrl = uniphier_pin_get_pupdctrl(pin->drv_data);
+ pupdctrl = uniphier_pin_get_pupdctrl(desc->drv_data);
reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4;
shift = pupdctrl % 32;
- ret = regmap_read(priv->regmap, reg, &val);
+ ret = regmap_read(priv->regmap, priv->regbase + reg, &val);
if (ret)
return ret;
@@ -169,34 +181,42 @@ static int uniphier_conf_pin_bias_get(struct pinctrl_dev *pctldev,
}
static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev,
- const struct pinctrl_pin_desc *pin,
+ const struct pin_desc *desc,
u16 *strength)
{
struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
- enum uniphier_pin_drv_str drv_str =
- uniphier_pin_get_drv_str(pin->drv_data);
- const unsigned int strength_4_8[] = {4, 8};
- const unsigned int strength_8_12_16_20[] = {8, 12, 16, 20};
+ enum uniphier_pin_drv_type type =
+ uniphier_pin_get_drv_type(desc->drv_data);
+ const unsigned int strength_1bit[] = {4, 8};
+ const unsigned int strength_2bit[] = {8, 12, 16, 20};
+ const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12, 14, 16};
const unsigned int *supported_strength;
unsigned int drvctrl, reg, shift, mask, width, val;
int ret;
- switch (drv_str) {
- case UNIPHIER_PIN_DRV_4_8:
- supported_strength = strength_4_8;
+ switch (type) {
+ case UNIPHIER_PIN_DRV_1BIT:
+ supported_strength = strength_1bit;
+ reg = UNIPHIER_PINCTRL_DRVCTRL_BASE;
width = 1;
break;
- case UNIPHIER_PIN_DRV_8_12_16_20:
- supported_strength = strength_8_12_16_20;
+ case UNIPHIER_PIN_DRV_2BIT:
+ supported_strength = strength_2bit;
+ reg = UNIPHIER_PINCTRL_DRV2CTRL_BASE;
width = 2;
break;
- case UNIPHIER_PIN_DRV_FIXED_4:
+ case UNIPHIER_PIN_DRV_3BIT:
+ supported_strength = strength_3bit;
+ reg = UNIPHIER_PINCTRL_DRV3CTRL_BASE;
+ width = 4;
+ break;
+ case UNIPHIER_PIN_DRV_FIXED4:
*strength = 4;
return 0;
- case UNIPHIER_PIN_DRV_FIXED_5:
+ case UNIPHIER_PIN_DRV_FIXED5:
*strength = 5;
return 0;
- case UNIPHIER_PIN_DRV_FIXED_8:
+ case UNIPHIER_PIN_DRV_FIXED8:
*strength = 8;
return 0;
default:
@@ -204,17 +224,14 @@ static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev,
return -EINVAL;
}
- drvctrl = uniphier_pin_get_drvctrl(pin->drv_data);
+ drvctrl = uniphier_pin_get_drvctrl(desc->drv_data);
drvctrl *= width;
- reg = (width == 2) ? UNIPHIER_PINCTRL_DRV2CTRL_BASE :
- UNIPHIER_PINCTRL_DRVCTRL_BASE;
-
reg += drvctrl / 32 * 4;
shift = drvctrl % 32;
mask = (1U << width) - 1;
- ret = regmap_read(priv->regmap, reg, &val);
+ ret = regmap_read(priv->regmap, priv->regbase + reg, &val);
if (ret)
return ret;
@@ -224,10 +241,10 @@ static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev,
}
static int uniphier_conf_pin_input_enable_get(struct pinctrl_dev *pctldev,
- const struct pinctrl_pin_desc *pin)
+ const struct pin_desc *desc)
{
struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
- unsigned int iectrl = uniphier_pin_get_iectrl(pin->drv_data);
+ unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data);
unsigned int val;
int ret;
@@ -235,7 +252,8 @@ static int uniphier_conf_pin_input_enable_get(struct pinctrl_dev *pctldev,
/* This pin is always input-enabled. */
return 0;
- ret = regmap_read(priv->regmap, UNIPHIER_PINCTRL_IECTRL, &val);
+ ret = regmap_read(priv->regmap,
+ priv->regbase + UNIPHIER_PINCTRL_IECTRL, &val);
if (ret)
return ret;
@@ -246,7 +264,7 @@ static int uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned long *configs)
{
- const struct pinctrl_pin_desc *pin_desc = &pctldev->desc->pins[pin];
+ const struct pin_desc *desc = pin_desc_get(pctldev, pin);
enum pin_config_param param = pinconf_to_config_param(*configs);
bool has_arg = false;
u16 arg;
@@ -256,14 +274,14 @@ static int uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev,
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
- ret = uniphier_conf_pin_bias_get(pctldev, pin_desc, param);
+ ret = uniphier_conf_pin_bias_get(pctldev, desc, param);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
- ret = uniphier_conf_pin_drive_get(pctldev, pin_desc, &arg);
+ ret = uniphier_conf_pin_drive_get(pctldev, desc, &arg);
has_arg = true;
break;
case PIN_CONFIG_INPUT_ENABLE:
- ret = uniphier_conf_pin_input_enable_get(pctldev, pin_desc);
+ ret = uniphier_conf_pin_input_enable_get(pctldev, desc);
break;
default:
/* unsupported parameter */
@@ -278,13 +296,12 @@ static int uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev,
}
static int uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev,
- const struct pinctrl_pin_desc *pin,
- enum pin_config_param param,
- u16 arg)
+ const struct pin_desc *desc,
+ enum pin_config_param param, u16 arg)
{
struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
enum uniphier_pin_pull_dir pull_dir =
- uniphier_pin_get_pull_dir(pin->drv_data);
+ uniphier_pin_get_pull_dir(desc->drv_data);
unsigned int pupdctrl, reg, shift;
unsigned int val = 1;
@@ -295,8 +312,8 @@ static int uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev,
if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED ||
pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED) {
dev_err(pctldev->dev,
- "can not disable pull register for pin %u (%s)\n",
- pin->number, pin->name);
+ "can not disable pull register for pin %s\n",
+ desc->name);
return -EINVAL;
}
val = 0;
@@ -306,8 +323,8 @@ static int uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev,
return 0;
if (pull_dir != UNIPHIER_PIN_PULL_UP) {
dev_err(pctldev->dev,
- "pull-up is unsupported for pin %u (%s)\n",
- pin->number, pin->name);
+ "pull-up is unsupported for pin %s\n",
+ desc->name);
return -EINVAL;
}
if (arg == 0) {
@@ -320,8 +337,8 @@ static int uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev,
return 0;
if (pull_dir != UNIPHIER_PIN_PULL_DOWN) {
dev_err(pctldev->dev,
- "pull-down is unsupported for pin %u (%s)\n",
- pin->number, pin->name);
+ "pull-down is unsupported for pin %s\n",
+ desc->name);
return -EINVAL;
}
if (arg == 0) {
@@ -332,8 +349,8 @@ static int uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev,
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
if (pull_dir == UNIPHIER_PIN_PULL_NONE) {
dev_err(pctldev->dev,
- "pull-up/down is unsupported for pin %u (%s)\n",
- pin->number, pin->name);
+ "pull-up/down is unsupported for pin %s\n",
+ desc->name);
return -EINVAL;
}
@@ -344,39 +361,48 @@ static int uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev,
BUG();
}
- pupdctrl = uniphier_pin_get_pupdctrl(pin->drv_data);
+ pupdctrl = uniphier_pin_get_pupdctrl(desc->drv_data);
reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4;
shift = pupdctrl % 32;
- return regmap_update_bits(priv->regmap, reg, 1 << shift, val << shift);
+ return regmap_update_bits(priv->regmap, priv->regbase + reg,
+ 1 << shift, val << shift);
}
static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev,
- const struct pinctrl_pin_desc *pin,
+ const struct pin_desc *desc,
u16 strength)
{
struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
- enum uniphier_pin_drv_str drv_str =
- uniphier_pin_get_drv_str(pin->drv_data);
- const unsigned int strength_4_8[] = {4, 8, -1};
- const unsigned int strength_8_12_16_20[] = {8, 12, 16, 20, -1};
+ enum uniphier_pin_drv_type type =
+ uniphier_pin_get_drv_type(desc->drv_data);
+ const unsigned int strength_1bit[] = {4, 8, -1};
+ const unsigned int strength_2bit[] = {8, 12, 16, 20, -1};
+ const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12, 14, 16, -1};
const unsigned int *supported_strength;
unsigned int drvctrl, reg, shift, mask, width, val;
- switch (drv_str) {
- case UNIPHIER_PIN_DRV_4_8:
- supported_strength = strength_4_8;
+ switch (type) {
+ case UNIPHIER_PIN_DRV_1BIT:
+ supported_strength = strength_1bit;
+ reg = UNIPHIER_PINCTRL_DRVCTRL_BASE;
width = 1;
break;
- case UNIPHIER_PIN_DRV_8_12_16_20:
- supported_strength = strength_8_12_16_20;
+ case UNIPHIER_PIN_DRV_2BIT:
+ supported_strength = strength_2bit;
+ reg = UNIPHIER_PINCTRL_DRV2CTRL_BASE;
width = 2;
break;
+ case UNIPHIER_PIN_DRV_3BIT:
+ supported_strength = strength_3bit;
+ reg = UNIPHIER_PINCTRL_DRV3CTRL_BASE;
+ width = 4;
+ break;
default:
dev_err(pctldev->dev,
- "cannot change drive strength for pin %u (%s)\n",
- pin->number, pin->name);
+ "cannot change drive strength for pin %s\n",
+ desc->name);
return -EINVAL;
}
@@ -387,49 +413,48 @@ static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev,
if (val == 0) {
dev_err(pctldev->dev,
- "unsupported drive strength %u mA for pin %u (%s)\n",
- strength, pin->number, pin->name);
+ "unsupported drive strength %u mA for pin %s\n",
+ strength, desc->name);
return -EINVAL;
}
val--;
- drvctrl = uniphier_pin_get_drvctrl(pin->drv_data);
+ drvctrl = uniphier_pin_get_drvctrl(desc->drv_data);
drvctrl *= width;
- reg = (width == 2) ? UNIPHIER_PINCTRL_DRV2CTRL_BASE :
- UNIPHIER_PINCTRL_DRVCTRL_BASE;
-
reg += drvctrl / 32 * 4;
shift = drvctrl % 32;
mask = (1U << width) - 1;
- return regmap_update_bits(priv->regmap, reg,
+ return regmap_update_bits(priv->regmap, priv->regbase + reg,
mask << shift, val << shift);
}
static int uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev,
- const struct pinctrl_pin_desc *pin,
+ const struct pin_desc *desc,
u16 enable)
{
struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
- unsigned int iectrl = uniphier_pin_get_iectrl(pin->drv_data);
+ unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data);
+ unsigned int reg, mask;
- if (enable == 0) {
- /*
- * Multiple pins share one input enable, so per-pin disabling
- * is impossible.
- */
- dev_err(pctldev->dev, "unable to disable input\n");
+ /*
+ * Multiple pins share one input enable, per-pin disabling is
+ * impossible.
+ */
+ if (!(priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) &&
+ !enable)
return -EINVAL;
- }
+ /* UNIPHIER_PIN_IECTRL_NONE means the pin is always input-enabled */
if (iectrl == UNIPHIER_PIN_IECTRL_NONE)
- /* This pin is always input-enabled. nothing to do. */
- return 0;
+ return enable ? 0 : -EINVAL;
+
+ reg = priv->regbase + UNIPHIER_PINCTRL_IECTRL + iectrl / 32 * 4;
+ mask = BIT(iectrl % 32);
- return regmap_update_bits(priv->regmap, UNIPHIER_PINCTRL_IECTRL,
- BIT(iectrl), BIT(iectrl));
+ return regmap_update_bits(priv->regmap, reg, mask, enable ? mask : 0);
}
static int uniphier_conf_pin_config_set(struct pinctrl_dev *pctldev,
@@ -437,7 +462,7 @@ static int uniphier_conf_pin_config_set(struct pinctrl_dev *pctldev,
unsigned long *configs,
unsigned num_configs)
{
- const struct pinctrl_pin_desc *pin_desc = &pctldev->desc->pins[pin];
+ const struct pin_desc *desc = pin_desc_get(pctldev, pin);
int i, ret;
for (i = 0; i < num_configs; i++) {
@@ -450,16 +475,15 @@ static int uniphier_conf_pin_config_set(struct pinctrl_dev *pctldev,
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
- ret = uniphier_conf_pin_bias_set(pctldev, pin_desc,
+ ret = uniphier_conf_pin_bias_set(pctldev, desc,
param, arg);
break;
case PIN_CONFIG_DRIVE_STRENGTH:
- ret = uniphier_conf_pin_drive_set(pctldev, pin_desc,
- arg);
+ ret = uniphier_conf_pin_drive_set(pctldev, desc, arg);
break;
case PIN_CONFIG_INPUT_ENABLE:
- ret = uniphier_conf_pin_input_enable(pctldev,
- pin_desc, arg);
+ ret = uniphier_conf_pin_input_enable(pctldev, desc,
+ arg);
break;
default:
dev_err(pctldev->dev,
@@ -531,20 +555,42 @@ static int uniphier_pmx_get_function_groups(struct pinctrl_dev *pctldev,
}
static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin,
- unsigned muxval)
+ int muxval)
{
struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
- unsigned mux_bits = priv->socdata->mux_bits;
- unsigned reg_stride = priv->socdata->reg_stride;
- unsigned reg, reg_end, shift, mask;
+ unsigned int mux_bits, reg_stride, reg, reg_end, shift, mask;
+ bool load_pinctrl;
int ret;
/* some pins need input-enabling */
ret = uniphier_conf_pin_input_enable(pctldev,
- &pctldev->desc->pins[pin], 1);
+ pin_desc_get(pctldev, pin), 1);
if (ret)
return ret;
+ if (muxval < 0)
+ return 0; /* dedicated pin; nothing to do for pin-mux */
+
+ if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
+ /*
+ * Mode reg_offset bit_position
+ * Normal 4 * n shift+3:shift
+ * Debug 4 * n shift+7:shift+4
+ */
+ mux_bits = 4;
+ reg_stride = 8;
+ load_pinctrl = true;
+ } else {
+ /*
+ * Mode reg_offset bit_position
+ * Normal 8 * n shift+3:shift
+ * Debug 8 * n + 4 shift+3:shift
+ */
+ mux_bits = 8;
+ reg_stride = 4;
+ load_pinctrl = false;
+ }
+
reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
reg_end = reg + reg_stride;
shift = pin * mux_bits % 32;
@@ -555,16 +601,17 @@ static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin,
* stored in the offset+4.
*/
for (; reg < reg_end; reg += 4) {
- ret = regmap_update_bits(priv->regmap, reg,
+ ret = regmap_update_bits(priv->regmap, priv->regbase + reg,
mask << shift, muxval << shift);
if (ret)
return ret;
muxval >>= mux_bits;
}
- if (priv->socdata->load_pinctrl) {
+ if (load_pinctrl) {
ret = regmap_write(priv->regmap,
- UNIPHIER_PINCTRL_LOAD_PINMUX, 1);
+ priv->regbase + UNIPHIER_PINCTRL_LOAD_PINMUX,
+ 1);
if (ret)
return ret;
}
@@ -633,19 +680,16 @@ static const struct pinmux_ops uniphier_pmxops = {
};
int uniphier_pinctrl_probe(struct platform_device *pdev,
- struct pinctrl_desc *desc,
struct uniphier_pinctrl_socdata *socdata)
{
struct device *dev = &pdev->dev;
struct uniphier_pinctrl_priv *priv;
+ struct device_node *parent;
if (!socdata ||
- !socdata->groups ||
- !socdata->groups_count ||
- !socdata->functions ||
- !socdata->functions_count ||
- !socdata->mux_bits ||
- !socdata->reg_stride) {
+ !socdata->pins || !socdata->npins ||
+ !socdata->groups || !socdata->groups_count ||
+ !socdata->functions || !socdata->functions_count) {
dev_err(dev, "pinctrl socdata lacks necessary members\n");
return -EINVAL;
}
@@ -654,18 +698,36 @@ int uniphier_pinctrl_probe(struct platform_device *pdev,
if (!priv)
return -ENOMEM;
- priv->regmap = syscon_node_to_regmap(dev->of_node);
+ if (of_device_is_compatible(dev->of_node, "socionext,ph1-ld4-pinctrl") ||
+ of_device_is_compatible(dev->of_node, "socionext,ph1-pro4-pinctrl") ||
+ of_device_is_compatible(dev->of_node, "socionext,ph1-sld8-pinctrl") ||
+ of_device_is_compatible(dev->of_node, "socionext,ph1-pro5-pinctrl") ||
+ of_device_is_compatible(dev->of_node, "socionext,proxstream2-pinctrl") ||
+ of_device_is_compatible(dev->of_node, "socionext,ph1-ld6b-pinctrl")) {
+ /* old binding */
+ priv->regmap = syscon_node_to_regmap(dev->of_node);
+ } else {
+ priv->regbase = 0x1000;
+ parent = of_get_parent(dev->of_node);
+ priv->regmap = syscon_node_to_regmap(parent);
+ of_node_put(parent);
+ }
+
if (IS_ERR(priv->regmap)) {
dev_err(dev, "failed to get regmap\n");
return PTR_ERR(priv->regmap);
}
priv->socdata = socdata;
- desc->pctlops = &uniphier_pctlops;
- desc->pmxops = &uniphier_pmxops;
- desc->confops = &uniphier_confops;
-
- priv->pctldev = devm_pinctrl_register(dev, desc, priv);
+ priv->pctldesc.name = dev->driver->name;
+ priv->pctldesc.pins = socdata->pins;
+ priv->pctldesc.npins = socdata->npins;
+ priv->pctldesc.pctlops = &uniphier_pctlops;
+ priv->pctldesc.pmxops = &uniphier_pmxops;
+ priv->pctldesc.confops = &uniphier_confops;
+ priv->pctldesc.owner = dev->driver->owner;
+
+ priv->pctldev = devm_pinctrl_register(dev, &priv->pctldesc, priv);
if (IS_ERR(priv->pctldev)) {
dev_err(dev, "failed to register UniPhier pinctrl driver\n");
return PTR_ERR(priv->pctldev);
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
new file mode 100644
index 000000000000..77a0236ee781
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -0,0 +1,952 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct pinctrl_pin_desc uniphier_ld11_pins[] = {
+ UNIPHIER_PINCTRL_PIN(0, "XECS1", 0,
+ 0, UNIPHIER_PIN_DRV_1BIT,
+ 0, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(1, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
+ 1, UNIPHIER_PIN_DRV_1BIT,
+ 1, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(2, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
+ 2, UNIPHIER_PIN_DRV_1BIT,
+ 2, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(3, "XNFWP", 3,
+ 3, UNIPHIER_PIN_DRV_1BIT,
+ 3, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(4, "XNFCE0", 4,
+ 4, UNIPHIER_PIN_DRV_1BIT,
+ 4, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(5, "NFRYBY0", 5,
+ 5, UNIPHIER_PIN_DRV_1BIT,
+ 5, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(6, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
+ 6, UNIPHIER_PIN_DRV_1BIT,
+ 6, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(7, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
+ 7, UNIPHIER_PIN_DRV_1BIT,
+ 7, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(8, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
+ 8, UNIPHIER_PIN_DRV_1BIT,
+ 8, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(9, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
+ 9, UNIPHIER_PIN_DRV_1BIT,
+ 9, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(10, "NFD0", 10,
+ 10, UNIPHIER_PIN_DRV_1BIT,
+ 10, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(11, "NFD1", 11,
+ 11, UNIPHIER_PIN_DRV_1BIT,
+ 11, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(12, "NFD2", 12,
+ 12, UNIPHIER_PIN_DRV_1BIT,
+ 12, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(13, "NFD3", 13,
+ 13, UNIPHIER_PIN_DRV_1BIT,
+ 13, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(14, "NFD4", 14,
+ 14, UNIPHIER_PIN_DRV_1BIT,
+ 14, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(15, "NFD5", 15,
+ 15, UNIPHIER_PIN_DRV_1BIT,
+ 15, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(16, "NFD6", 16,
+ 16, UNIPHIER_PIN_DRV_1BIT,
+ 16, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(17, "NFD7", 17,
+ 17, UNIPHIER_PIN_DRV_1BIT,
+ 17, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(18, "XERST", 18,
+ 0, UNIPHIER_PIN_DRV_2BIT,
+ 18, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(19, "MMCCLK", 19,
+ 1, UNIPHIER_PIN_DRV_2BIT,
+ 19, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(20, "MMCCMD", 20,
+ 2, UNIPHIER_PIN_DRV_2BIT,
+ 20, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(21, "MMCDS", 21,
+ 3, UNIPHIER_PIN_DRV_2BIT,
+ 21, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(22, "MMCDAT0", 22,
+ 4, UNIPHIER_PIN_DRV_2BIT,
+ 22, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(23, "MMCDAT1", 23,
+ 5, UNIPHIER_PIN_DRV_2BIT,
+ 23, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(24, "MMCDAT2", 24,
+ 6, UNIPHIER_PIN_DRV_2BIT,
+ 24, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(25, "MMCDAT3", 25,
+ 7, UNIPHIER_PIN_DRV_2BIT,
+ 25, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(26, "MMCDAT4", 26,
+ 8, UNIPHIER_PIN_DRV_2BIT,
+ 26, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(27, "MMCDAT5", 27,
+ 9, UNIPHIER_PIN_DRV_2BIT,
+ 27, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(28, "MMCDAT6", 28,
+ 10, UNIPHIER_PIN_DRV_2BIT,
+ 28, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(29, "MMCDAT7", 29,
+ 11, UNIPHIER_PIN_DRV_2BIT,
+ 29, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(46, "USB0VBUS", 46,
+ 46, UNIPHIER_PIN_DRV_1BIT,
+ 46, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(47, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
+ 47, UNIPHIER_PIN_DRV_1BIT,
+ 47, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(48, "USB1VBUS", 48,
+ 48, UNIPHIER_PIN_DRV_1BIT,
+ 48, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(49, "USB1OD", 49,
+ 49, UNIPHIER_PIN_DRV_1BIT,
+ 49, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(50, "USB2VBUS", 50,
+ 50, UNIPHIER_PIN_DRV_1BIT,
+ 50, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(51, "USB2OD", 51,
+ 51, UNIPHIER_PIN_DRV_1BIT,
+ 51, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(54, "TXD0", 54,
+ 54, UNIPHIER_PIN_DRV_1BIT,
+ 54, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(55, "RXD0", 55,
+ 55, UNIPHIER_PIN_DRV_1BIT,
+ 55, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(56, "SPISYNC0", 56,
+ 56, UNIPHIER_PIN_DRV_1BIT,
+ 56, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(57, "SPISCLK0", 57,
+ 57, UNIPHIER_PIN_DRV_1BIT,
+ 57, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(58, "SPITXD0", 58,
+ 58, UNIPHIER_PIN_DRV_1BIT,
+ 58, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(59, "SPIRXD0", 59,
+ 59, UNIPHIER_PIN_DRV_1BIT,
+ 59, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(60, "AGCI", 60,
+ 60, UNIPHIER_PIN_DRV_1BIT,
+ 60, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(61, "DMDSDA0", 61,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(62, "DMDSCL0", 62,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(63, "SDA0", 63,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(64, "SCL0", 64,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(65, "SDA1", 65,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(66, "SCL1", 66,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(67, "HIN", 67,
+ -1, UNIPHIER_PIN_DRV_FIXED5,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(68, "VIN", 68,
+ -1, UNIPHIER_PIN_DRV_FIXED5,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(69, "PCA00", 69,
+ 69, UNIPHIER_PIN_DRV_1BIT,
+ 69, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(70, "PCA01", 70,
+ 70, UNIPHIER_PIN_DRV_1BIT,
+ 70, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(71, "PCA02", 71,
+ 71, UNIPHIER_PIN_DRV_1BIT,
+ 71, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(72, "PCA03", 72,
+ 72, UNIPHIER_PIN_DRV_1BIT,
+ 72, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(73, "PCA04", 73,
+ 73, UNIPHIER_PIN_DRV_1BIT,
+ 73, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(74, "PCA05", 74,
+ 74, UNIPHIER_PIN_DRV_1BIT,
+ 74, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(75, "PCA06", 75,
+ 75, UNIPHIER_PIN_DRV_1BIT,
+ 75, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(76, "PCA07", 76,
+ 76, UNIPHIER_PIN_DRV_1BIT,
+ 76, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(77, "PCA08", 77,
+ 77, UNIPHIER_PIN_DRV_1BIT,
+ 77, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(78, "PCA09", 78,
+ 78, UNIPHIER_PIN_DRV_1BIT,
+ 78, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(79, "PCA10", 79,
+ 79, UNIPHIER_PIN_DRV_1BIT,
+ 79, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(80, "PCA11", 80,
+ 80, UNIPHIER_PIN_DRV_1BIT,
+ 80, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(81, "PCA12", 81,
+ 81, UNIPHIER_PIN_DRV_1BIT,
+ 81, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(82, "PCA13", 82,
+ 82, UNIPHIER_PIN_DRV_1BIT,
+ 82, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(83, "PCA14", 83,
+ 83, UNIPHIER_PIN_DRV_1BIT,
+ 83, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(84, "PC0READY", 84,
+ 84, UNIPHIER_PIN_DRV_1BIT,
+ 84, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(85, "PC0CD1", 85,
+ 85, UNIPHIER_PIN_DRV_1BIT,
+ 85, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(86, "PC0CD2", 86,
+ 86, UNIPHIER_PIN_DRV_1BIT,
+ 86, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(87, "PC0WAIT", 87,
+ 87, UNIPHIER_PIN_DRV_1BIT,
+ 87, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(88, "PC0RESET", 88,
+ 88, UNIPHIER_PIN_DRV_1BIT,
+ 88, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(89, "PC0CE1", 89,
+ 89, UNIPHIER_PIN_DRV_1BIT,
+ 89, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(90, "PC0WE", 90,
+ 90, UNIPHIER_PIN_DRV_1BIT,
+ 90, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(91, "PC0OE", 91,
+ 91, UNIPHIER_PIN_DRV_1BIT,
+ 91, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(92, "PC0IOWR", 92,
+ 92, UNIPHIER_PIN_DRV_1BIT,
+ 92, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(93, "PC0IORD", 93,
+ 93, UNIPHIER_PIN_DRV_1BIT,
+ 93, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(94, "PCD00", 94,
+ 94, UNIPHIER_PIN_DRV_1BIT,
+ 94, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(95, "PCD01", 95,
+ 95, UNIPHIER_PIN_DRV_1BIT,
+ 95, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(96, "PCD02", 96,
+ 96, UNIPHIER_PIN_DRV_1BIT,
+ 96, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(97, "PCD03", 97,
+ 97, UNIPHIER_PIN_DRV_1BIT,
+ 97, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(98, "PCD04", 98,
+ 98, UNIPHIER_PIN_DRV_1BIT,
+ 98, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(99, "PCD05", 99,
+ 99, UNIPHIER_PIN_DRV_1BIT,
+ 99, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(100, "PCD06", 100,
+ 100, UNIPHIER_PIN_DRV_1BIT,
+ 100, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(101, "PCD07", 101,
+ 101, UNIPHIER_PIN_DRV_1BIT,
+ 101, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(102, "HS0BCLKIN", 102,
+ 102, UNIPHIER_PIN_DRV_1BIT,
+ 102, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(103, "HS0SYNCIN", 103,
+ 103, UNIPHIER_PIN_DRV_1BIT,
+ 103, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(104, "HS0VALIN", 104,
+ 104, UNIPHIER_PIN_DRV_1BIT,
+ 104, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(105, "HS0DIN0", 105,
+ 105, UNIPHIER_PIN_DRV_1BIT,
+ 105, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(106, "HS0DIN1", 106,
+ 106, UNIPHIER_PIN_DRV_1BIT,
+ 106, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(107, "HS0DIN2", 107,
+ 107, UNIPHIER_PIN_DRV_1BIT,
+ 107, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(108, "HS0DIN3", 108,
+ 108, UNIPHIER_PIN_DRV_1BIT,
+ 108, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(109, "HS0DIN4", 109,
+ 109, UNIPHIER_PIN_DRV_1BIT,
+ 109, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(110, "HS0DIN5", 110,
+ 110, UNIPHIER_PIN_DRV_1BIT,
+ 110, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(111, "HS0DIN6", 111,
+ 111, UNIPHIER_PIN_DRV_1BIT,
+ 111, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(112, "HS0DIN7", 112,
+ 112, UNIPHIER_PIN_DRV_1BIT,
+ 112, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(113, "HS0BCLKOUT", 113,
+ 113, UNIPHIER_PIN_DRV_1BIT,
+ 113, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(114, "HS0SYNCOUT", 114,
+ 114, UNIPHIER_PIN_DRV_1BIT,
+ 114, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(115, "HS0VALOUT", 115,
+ 115, UNIPHIER_PIN_DRV_1BIT,
+ 115, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(116, "HS0DOUT0", 116,
+ 116, UNIPHIER_PIN_DRV_1BIT,
+ 116, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(117, "HS0DOUT1", 117,
+ 117, UNIPHIER_PIN_DRV_1BIT,
+ 117, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(118, "HS0DOUT2", 118,
+ 118, UNIPHIER_PIN_DRV_1BIT,
+ 118, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(119, "HS0DOUT3", 119,
+ 119, UNIPHIER_PIN_DRV_1BIT,
+ 119, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(120, "HS0DOUT4", 120,
+ 120, UNIPHIER_PIN_DRV_1BIT,
+ 120, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(121, "HS0DOUT5", 121,
+ 121, UNIPHIER_PIN_DRV_1BIT,
+ 121, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(122, "HS0DOUT6", 122,
+ 122, UNIPHIER_PIN_DRV_1BIT,
+ 122, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(123, "HS0DOUT7", 123,
+ 123, UNIPHIER_PIN_DRV_1BIT,
+ 123, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(124, "HS1BCLKIN", 124,
+ 124, UNIPHIER_PIN_DRV_1BIT,
+ 124, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(125, "HS1SYNCIN", 125,
+ 125, UNIPHIER_PIN_DRV_1BIT,
+ 125, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(126, "HS1VALIN", 126,
+ 126, UNIPHIER_PIN_DRV_1BIT,
+ 126, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(127, "HS1DIN0", 127,
+ 127, UNIPHIER_PIN_DRV_1BIT,
+ 127, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(128, "HS1DIN1", 128,
+ 128, UNIPHIER_PIN_DRV_1BIT,
+ 128, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(129, "HS1DIN2", 129,
+ 129, UNIPHIER_PIN_DRV_1BIT,
+ 129, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(130, "HS1DIN3", 130,
+ 130, UNIPHIER_PIN_DRV_1BIT,
+ 130, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(131, "HS1DIN4", 131,
+ 131, UNIPHIER_PIN_DRV_1BIT,
+ 131, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(132, "HS1DIN5", 132,
+ 132, UNIPHIER_PIN_DRV_1BIT,
+ 132, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(133, "HS1DIN6", 133,
+ 133, UNIPHIER_PIN_DRV_1BIT,
+ 133, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(134, "HS1DIN7", 134,
+ 134, UNIPHIER_PIN_DRV_1BIT,
+ 134, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(135, "AO1IEC", 135,
+ 135, UNIPHIER_PIN_DRV_1BIT,
+ 135, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(136, "AO1ARC", 136,
+ 136, UNIPHIER_PIN_DRV_1BIT,
+ 136, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(137, "AO1DACCK", 137,
+ 137, UNIPHIER_PIN_DRV_1BIT,
+ 137, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(138, "AO1BCK", 138,
+ 138, UNIPHIER_PIN_DRV_1BIT,
+ 138, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(139, "AO1LRCK", 139,
+ 139, UNIPHIER_PIN_DRV_1BIT,
+ 139, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(140, "AO1D0", 140,
+ 140, UNIPHIER_PIN_DRV_1BIT,
+ 140, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(141, "TCON0", 141,
+ 141, UNIPHIER_PIN_DRV_1BIT,
+ 141, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(142, "TCON1", 142,
+ 142, UNIPHIER_PIN_DRV_1BIT,
+ 142, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(143, "TCON2", 143,
+ 143, UNIPHIER_PIN_DRV_1BIT,
+ 143, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(144, "TCON3", 144,
+ 144, UNIPHIER_PIN_DRV_1BIT,
+ 144, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(145, "TCON4", 145,
+ 145, UNIPHIER_PIN_DRV_1BIT,
+ 145, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(146, "TCON5", 146,
+ 146, UNIPHIER_PIN_DRV_1BIT,
+ 146, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(147, "PWMA", 147,
+ 147, UNIPHIER_PIN_DRV_1BIT,
+ 147, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(148, "LR_GOUT", 148,
+ 148, UNIPHIER_PIN_DRV_1BIT,
+ 148, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(149, "XIRQ0", 149,
+ 149, UNIPHIER_PIN_DRV_1BIT,
+ 149, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(150, "XIRQ1", 150,
+ 150, UNIPHIER_PIN_DRV_1BIT,
+ 150, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(151, "XIRQ2", 151,
+ 151, UNIPHIER_PIN_DRV_1BIT,
+ 151, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(152, "XIRQ3", 152,
+ 152, UNIPHIER_PIN_DRV_1BIT,
+ 152, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(153, "XIRQ4", 153,
+ 153, UNIPHIER_PIN_DRV_1BIT,
+ 153, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(154, "XIRQ5", 154,
+ 154, UNIPHIER_PIN_DRV_1BIT,
+ 154, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(155, "XIRQ6", 155,
+ 155, UNIPHIER_PIN_DRV_1BIT,
+ 155, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(156, "XIRQ7", 156,
+ 156, UNIPHIER_PIN_DRV_1BIT,
+ 156, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(157, "XIRQ8", 157,
+ 157, UNIPHIER_PIN_DRV_1BIT,
+ 157, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(158, "AGCBS", 158,
+ 158, UNIPHIER_PIN_DRV_1BIT,
+ 158, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(159, "XIRQ21", 159,
+ 159, UNIPHIER_PIN_DRV_1BIT,
+ 159, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(160, "XIRQ22", 160,
+ 160, UNIPHIER_PIN_DRV_1BIT,
+ 160, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(161, "XIRQ23", 161,
+ 161, UNIPHIER_PIN_DRV_1BIT,
+ 161, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(162, "CH2CLK", 162,
+ 162, UNIPHIER_PIN_DRV_1BIT,
+ 162, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(163, "CH2PSYNC", 163,
+ 163, UNIPHIER_PIN_DRV_1BIT,
+ 163, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(164, "CH2VAL", 164,
+ 164, UNIPHIER_PIN_DRV_1BIT,
+ 164, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(165, "CH2DATA", 165,
+ 165, UNIPHIER_PIN_DRV_1BIT,
+ 165, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(166, "CK25O", 166,
+ 166, UNIPHIER_PIN_DRV_1BIT,
+ 166, UNIPHIER_PIN_PULL_DOWN),
+};
+
+static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25};
+static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
+static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned ether_rmii_pins[] = {6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17};
+static const int ether_rmii_muxvals[] = {4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4};
+static const unsigned i2c0_pins[] = {63, 64};
+static const int i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {65, 66};
+static const int i2c1_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {67, 68};
+static const int i2c3_muxvals[] = {1, 1};
+static const unsigned i2c4_pins[] = {61, 62};
+static const int i2c4_muxvals[] = {1, 1};
+static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
+ 15, 16, 17};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned system_bus_pins[] = {1, 2, 6, 7, 8, 9, 10, 11, 12, 13,
+ 14, 15, 16, 17};
+static const int system_bus_muxvals[] = {0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2};
+static const unsigned system_bus_cs1_pins[] = {0};
+static const int system_bus_cs1_muxvals[] = {0};
+static const unsigned uart0_pins[] = {54, 55};
+static const int uart0_muxvals[] = {0, 0};
+static const unsigned uart1_pins[] = {58, 59};
+static const int uart1_muxvals[] = {1, 1};
+static const unsigned uart2_pins[] = {90, 91};
+static const int uart2_muxvals[] = {1, 1};
+static const unsigned uart3_pins[] = {94, 95};
+static const int uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {46, 47};
+static const int usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {48, 49};
+static const int usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {50, 51};
+static const int usb2_muxvals[] = {0, 0};
+static const unsigned port_range_pins[] = {
+ 159, 160, 161, 162, 163, 164, 165, 166, /* PORT0x */
+ 0, 1, 2, 3, 4, 5, 6, 7, /* PORT1x */
+ 8, 9, 10, 11, 12, 13, 14, 15, /* PORT2x */
+ 16, 17, 18, -1, -1, -1, -1, -1, /* PORT3x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT4x */
+ -1, -1, -1, 46, 47, 48, 49, 50, /* PORT5x */
+ 51, -1, -1, 54, 55, 56, 57, 58, /* PORT6x */
+ 59, 60, 69, 70, 71, 72, 73, 74, /* PORT7x */
+ 75, 76, 77, 78, 79, 80, 81, 82, /* PORT8x */
+ 83, 84, 85, 86, 87, 88, 89, 90, /* PORT9x */
+ 91, 92, 93, 94, 95, 96, 97, 98, /* PORT10x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT11x */
+ 99, 100, 101, 102, 103, 104, 105, 106, /* PORT12x */
+ 107, 108, 109, 110, 111, 112, 113, 114, /* PORT13x */
+ 115, 116, 117, 118, 119, 120, 121, 122, /* PORT14x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT15x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT16x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT17x */
+ 61, 62, 63, 64, 65, 66, 67, 68, /* PORT18x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT19x */
+ 123, 124, 125, 126, 127, 128, 129, 130, /* PORT20x */
+ 131, 132, 133, 134, 135, 136, 137, 138, /* PORT21x */
+ 139, 140, 141, 142, -1, -1, -1, -1, /* PORT22x */
+ 147, 148, 149, 150, 151, 152, 153, 154, /* PORT23x */
+ 155, 156, 157, 143, 144, 145, 146, 158, /* PORT24x */
+};
+static const int port_range_muxvals[] = {
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
+ 15, 15, 15, -1, -1, -1, -1, -1, /* PORT3x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT4x */
+ -1, -1, -1, 15, 15, 15, 15, 15, /* PORT5x */
+ 15, -1, -1, 15, 15, 15, 15, 15, /* PORT6x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT11x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT15x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT16x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT17x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT19x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */
+ 15, 15, 15, 15, -1, -1, -1, -1, /* PORT22x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */
+};
+static const unsigned xirq_pins[] = {
+ 149, 150, 151, 152, 153, 154, 155, 156, /* XIRQ0-7 */
+ 157, 143, 144, 145, 85, 146, 158, 84, /* XIRQ8-15 */
+ 141, 142, 148, 50, 51, 159, 160, 161, /* XIRQ16-23 */
+};
+static const int xirq_muxvals[] = {
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */
+ 14, 14, 14, 14, 13, 14, 14, 13, /* XIRQ8-15 */
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */
+};
+static const unsigned xirq_alternatives_pins[] = {
+ 94, 95, 96, 97, 98, 99, 100, 101, /* XIRQ0-7 */
+ 102, 103, 104, 105, 106, 107, /* XIRQ8-11,13,14 */
+ 108, 109, 110, 111, 112, 113, 114, 115, /* XIRQ16-23 */
+ 9, 10, 11, 12, 13, 14, 15, 16, /* XIRQ4-11 */
+ 17, 0, 1, 2, 3, 4, 5, 6, 7, 8, /* XIRQ13,14,16-23 */
+ 139, 140, 135, 147, /* XIRQ17,18,21,22 */
+};
+static const int xirq_alternatives_muxvals[] = {
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */
+ 14, 14, 14, 14, 14, 14, /* XIRQ8-11,13,14 */
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ4-11 */
+ 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ13,14,16-23 */
+ 14, 14, 14, 14, /* XIRQ17,18,21,22 */
+};
+
+static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(ether_rmii),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(i2c4),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range, 23),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range, 24),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range, 25),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range, 26),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range, 43),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range, 44),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range, 45),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range, 46),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range, 47),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range, 48),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range, 51),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range, 52),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range, 53),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range, 54),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range, 55),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range, 56),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range, 57),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range, 58),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range, 59),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range, 60),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range, 61),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range, 62),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range, 63),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range, 64),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range, 65),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range, 66),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range, 67),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range, 68),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range, 69),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range, 70),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range, 71),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range, 72),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range, 73),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range, 74),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range, 75),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range, 76),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range, 77),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range, 78),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range, 79),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range, 80),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range, 81),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range, 82),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range, 83),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range, 84),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range, 85),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range, 86),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range, 87),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range, 96),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range, 97),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range, 98),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range, 99),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range, 100),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range, 101),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range, 102),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range, 103),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range, 104),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range, 105),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range, 106),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range, 107),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range, 108),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range, 109),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range, 110),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range, 111),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range, 112),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range, 113),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range, 114),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range, 115),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range, 116),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range, 117),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range, 118),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range, 119),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range, 144),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range, 145),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range, 146),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range, 147),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range, 148),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range, 149),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range, 150),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range, 151),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range, 160),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range, 161),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range, 162),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range, 163),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range, 164),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range, 165),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range, 166),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range, 167),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range, 168),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range, 169),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range, 170),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range, 171),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range, 172),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range, 173),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range, 174),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range, 175),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range, 176),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range, 177),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range, 178),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range, 179),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range, 184),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range, 185),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range, 186),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range, 187),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range, 188),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range, 189),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range, 190),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range, 191),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range, 192),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range, 193),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range, 194),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range, 195),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range, 196),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range, 197),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range, 198),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range, 199),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21, xirq, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22, xirq, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23, xirq, 23),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0b, xirq_alternatives, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1b, xirq_alternatives, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2b, xirq_alternatives, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3b, xirq_alternatives, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4b, xirq_alternatives, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5b, xirq_alternatives, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6b, xirq_alternatives, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7b, xirq_alternatives, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8b, xirq_alternatives, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9b, xirq_alternatives, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10b, xirq_alternatives, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11b, xirq_alternatives, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13b, xirq_alternatives, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14b, xirq_alternatives, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16b, xirq_alternatives, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17b, xirq_alternatives, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18b, xirq_alternatives, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19b, xirq_alternatives, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20b, xirq_alternatives, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21b, xirq_alternatives, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22b, xirq_alternatives, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23b, xirq_alternatives, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4c, xirq_alternatives, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5c, xirq_alternatives, 23),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6c, xirq_alternatives, 24),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7c, xirq_alternatives, 25),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8c, xirq_alternatives, 26),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9c, xirq_alternatives, 27),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10c, xirq_alternatives, 28),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11c, xirq_alternatives, 29),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13c, xirq_alternatives, 30),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14c, xirq_alternatives, 31),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16c, xirq_alternatives, 32),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17c, xirq_alternatives, 33),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18c, xirq_alternatives, 34),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19c, xirq_alternatives, 35),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20c, xirq_alternatives, 36),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21c, xirq_alternatives, 37),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22c, xirq_alternatives, 38),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23c, xirq_alternatives, 39),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17d, xirq_alternatives, 40),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18d, xirq_alternatives, 41),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21d, xirq_alternatives, 42),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22d, xirq_alternatives, 43),
+};
+
+static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
+static const char * const ether_rmii_groups[] = {"ether_rmii"};
+static const char * const i2c0_groups[] = {"i2c0"};
+static const char * const i2c1_groups[] = {"i2c1"};
+static const char * const i2c3_groups[] = {"i2c3"};
+static const char * const i2c4_groups[] = {"i2c4"};
+static const char * const nand_groups[] = {"nand"};
+static const char * const system_bus_groups[] = {"system_bus",
+ "system_bus_cs1"};
+static const char * const uart0_groups[] = {"uart0"};
+static const char * const uart1_groups[] = {"uart1"};
+static const char * const uart2_groups[] = {"uart2"};
+static const char * const uart3_groups[] = {"uart3"};
+static const char * const usb0_groups[] = {"usb0"};
+static const char * const usb1_groups[] = {"usb1"};
+static const char * const usb2_groups[] = {"usb2"};
+static const char * const port_groups[] = {
+ "port00", "port01", "port02", "port03",
+ "port04", "port05", "port06", "port07",
+ "port10", "port11", "port12", "port13",
+ "port14", "port15", "port16", "port17",
+ "port20", "port21", "port22", "port23",
+ "port24", "port25", "port26", "port27",
+ "port30", "port31", "port32",
+ /* port33-52 missing */ "port53",
+ "port54", "port55", "port56", "port57",
+ "port60", /* port61-62 missing*/ "port63",
+ "port64", "port65", "port66", "port67",
+ "port70", "port71", "port72", "port73",
+ "port74", "port75", "port76", "port77",
+ "port80", "port81", "port82", "port83",
+ "port84", "port85", "port86", "port87",
+ "port90", "port91", "port92", "port93",
+ "port94", "port95", "port96", "port97",
+ "port100", "port101", "port102", "port103",
+ "port104", "port105", "port106", "port107",
+ /* port110-117 missing */
+ "port120", "port121", "port122", "port123",
+ "port124", "port125", "port126", "port127",
+ "port130", "port131", "port132", "port133",
+ "port134", "port135", "port136", "port137",
+ "port140", "port141", "port142", "port143",
+ "port144", "port145", "port146", "port147",
+ /* port150-177 missing */
+ "port180", "port181", "port182", "port183",
+ "port184", "port185", "port186", "port187",
+ /* port190-197 missing */
+ "port200", "port201", "port202", "port203",
+ "port204", "port205", "port206", "port207",
+ "port210", "port211", "port212", "port213",
+ "port214", "port215", "port216", "port217",
+ "port220", "port221", "port222", "port223",
+ /* port224-227 missing */
+ "port230", "port231", "port232", "port233",
+ "port234", "port235", "port236", "port237",
+ "port240", "port241", "port242", "port243",
+ "port244", "port245", "port246", "port247",
+};
+static const char * const xirq_groups[] = {
+ "xirq0", "xirq1", "xirq2", "xirq3",
+ "xirq4", "xirq5", "xirq6", "xirq7",
+ "xirq8", "xirq9", "xirq10", "xirq11",
+ "xirq12", "xirq13", "xirq14", "xirq15",
+ "xirq16", "xirq17", "xirq18", "xirq19",
+ "xirq20", "xirq21", "xirq22", "xirq23",
+ "xirq0b", "xirq1b", "xirq2b", "xirq3b",
+ "xirq4b", "xirq5b", "xirq6b", "xirq7b",
+ "xirq8b", "xirq9b", "xirq10b", "xirq11b",
+ /* none */ "xirq13b", "xirq14b", /* none */
+ "xirq16b", "xirq17b", "xirq18b", "xirq19b",
+ "xirq20b", "xirq21b", "xirq22b", "xirq23b",
+ "xirq4c", "xirq5c", "xirq6c", "xirq7c",
+ "xirq8c", "xirq9c", "xirq10c", "xirq11c",
+ /* none */ "xirq13c", "xirq14c", /* none */
+ "xirq16c", "xirq17c", "xirq18c", "xirq19c",
+ "xirq20c", "xirq21c", "xirq22c", "xirq23c",
+ "xirq17d", "xirq18d", "xirq21d", "xirq22d",
+};
+
+static const struct uniphier_pinmux_function uniphier_ld11_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(ether_rmii),
+ UNIPHIER_PINMUX_FUNCTION(i2c0),
+ UNIPHIER_PINMUX_FUNCTION(i2c1),
+ UNIPHIER_PINMUX_FUNCTION(i2c3),
+ UNIPHIER_PINMUX_FUNCTION(i2c4),
+ UNIPHIER_PINMUX_FUNCTION(nand),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
+ UNIPHIER_PINMUX_FUNCTION(uart0),
+ UNIPHIER_PINMUX_FUNCTION(uart1),
+ UNIPHIER_PINMUX_FUNCTION(uart2),
+ UNIPHIER_PINMUX_FUNCTION(uart3),
+ UNIPHIER_PINMUX_FUNCTION(usb0),
+ UNIPHIER_PINMUX_FUNCTION(usb1),
+ UNIPHIER_PINMUX_FUNCTION(usb2),
+ UNIPHIER_PINMUX_FUNCTION(port),
+ UNIPHIER_PINMUX_FUNCTION(xirq),
+};
+
+static struct uniphier_pinctrl_socdata uniphier_ld11_pindata = {
+ .pins = uniphier_ld11_pins,
+ .npins = ARRAY_SIZE(uniphier_ld11_pins),
+ .groups = uniphier_ld11_groups,
+ .groups_count = ARRAY_SIZE(uniphier_ld11_groups),
+ .functions = uniphier_ld11_functions,
+ .functions_count = ARRAY_SIZE(uniphier_ld11_functions),
+ .caps = UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL,
+};
+
+static int uniphier_ld11_pinctrl_probe(struct platform_device *pdev)
+{
+ return uniphier_pinctrl_probe(pdev, &uniphier_ld11_pindata);
+}
+
+static const struct of_device_id uniphier_ld11_pinctrl_match[] = {
+ { .compatible = "socionext,uniphier-ld11-pinctrl" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, uniphier_ld11_pinctrl_match);
+
+static struct platform_driver uniphier_ld11_pinctrl_driver = {
+ .probe = uniphier_ld11_pinctrl_probe,
+ .driver = {
+ .name = "uniphier-ld11-pinctrl",
+ .of_match_table = uniphier_ld11_pinctrl_match,
+ },
+};
+module_platform_driver(uniphier_ld11_pinctrl_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PH1-LD11 pinctrl driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
new file mode 100644
index 000000000000..aa8bd9794683
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -0,0 +1,1050 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct pinctrl_pin_desc uniphier_ld20_pins[] = {
+ UNIPHIER_PINCTRL_PIN(0, "XECS1", 0,
+ 0, UNIPHIER_PIN_DRV_3BIT,
+ 0, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(1, "ERXW", 1,
+ 1, UNIPHIER_PIN_DRV_3BIT,
+ 1, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(2, "XERWE1", 2,
+ 2, UNIPHIER_PIN_DRV_3BIT,
+ 2, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(3, "XNFWP", 3,
+ 3, UNIPHIER_PIN_DRV_3BIT,
+ 3, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(4, "XNFCE0", 4,
+ 4, UNIPHIER_PIN_DRV_3BIT,
+ 4, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(5, "NFRYBY0", 5,
+ 5, UNIPHIER_PIN_DRV_3BIT,
+ 5, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(6, "XNFRE", 6,
+ 6, UNIPHIER_PIN_DRV_3BIT,
+ 6, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(7, "XNFWE", 7,
+ 7, UNIPHIER_PIN_DRV_3BIT,
+ 7, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(8, "NFALE", 8,
+ 8, UNIPHIER_PIN_DRV_3BIT,
+ 8, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(9, "NFCLE", 9,
+ 9, UNIPHIER_PIN_DRV_3BIT,
+ 9, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(10, "NFD0", 10,
+ 10, UNIPHIER_PIN_DRV_3BIT,
+ 10, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(11, "NFD1", 11,
+ 11, UNIPHIER_PIN_DRV_3BIT,
+ 11, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(12, "NFD2", 12,
+ 12, UNIPHIER_PIN_DRV_3BIT,
+ 12, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(13, "NFD3", 13,
+ 13, UNIPHIER_PIN_DRV_3BIT,
+ 13, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(14, "NFD4", 14,
+ 14, UNIPHIER_PIN_DRV_3BIT,
+ 14, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(15, "NFD5", 15,
+ 15, UNIPHIER_PIN_DRV_3BIT,
+ 15, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(16, "NFD6", 16,
+ 16, UNIPHIER_PIN_DRV_3BIT,
+ 16, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(17, "NFD7", 17,
+ 17, UNIPHIER_PIN_DRV_3BIT,
+ 17, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(18, "XERST", 18,
+ 0, UNIPHIER_PIN_DRV_2BIT,
+ 18, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(19, "MMCCLK", 19,
+ 1, UNIPHIER_PIN_DRV_2BIT,
+ 19, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(20, "MMCCMD", 20,
+ 2, UNIPHIER_PIN_DRV_2BIT,
+ 20, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(21, "MMCDS", 21,
+ 3, UNIPHIER_PIN_DRV_2BIT,
+ 21, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(22, "MMCDAT0", 22,
+ 4, UNIPHIER_PIN_DRV_2BIT,
+ 22, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(23, "MMCDAT1", 23,
+ 5, UNIPHIER_PIN_DRV_2BIT,
+ 23, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(24, "MMCDAT2", 24,
+ 6, UNIPHIER_PIN_DRV_2BIT,
+ 24, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(25, "MMCDAT3", 25,
+ 7, UNIPHIER_PIN_DRV_2BIT,
+ 25, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(26, "MMCDAT4", 26,
+ 8, UNIPHIER_PIN_DRV_2BIT,
+ 26, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(27, "MMCDAT5", 27,
+ 9, UNIPHIER_PIN_DRV_2BIT,
+ 27, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(28, "MMCDAT6", 28,
+ 10, UNIPHIER_PIN_DRV_2BIT,
+ 28, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(29, "MMCDAT7", 29,
+ 11, UNIPHIER_PIN_DRV_2BIT,
+ 29, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(30, "MDC", 30,
+ 18, UNIPHIER_PIN_DRV_3BIT,
+ 30, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(31, "MDIO", 31,
+ 19, UNIPHIER_PIN_DRV_3BIT,
+ 31, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(32, "MDIO_INTL", 32,
+ 20, UNIPHIER_PIN_DRV_3BIT,
+ 32, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(33, "PHYRSTL", 33,
+ 21, UNIPHIER_PIN_DRV_3BIT,
+ 33, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(34, "RGMII_RXCLK", 34,
+ 22, UNIPHIER_PIN_DRV_3BIT,
+ 34, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(35, "RGMII_RXD0", 35,
+ 23, UNIPHIER_PIN_DRV_3BIT,
+ 35, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(36, "RGMII_RXD1", 36,
+ 24, UNIPHIER_PIN_DRV_3BIT,
+ 36, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(37, "RGMII_RXD2", 37,
+ 25, UNIPHIER_PIN_DRV_3BIT,
+ 37, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(38, "RGMII_RXD3", 38,
+ 26, UNIPHIER_PIN_DRV_3BIT,
+ 38, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(39, "RGMII_RXCTL", 39,
+ 27, UNIPHIER_PIN_DRV_3BIT,
+ 39, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(40, "RGMII_TXCLK", 40,
+ 28, UNIPHIER_PIN_DRV_3BIT,
+ 40, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(41, "RGMII_TXD0", 41,
+ 29, UNIPHIER_PIN_DRV_3BIT,
+ 41, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(42, "RGMII_TXD1", 42,
+ 30, UNIPHIER_PIN_DRV_3BIT,
+ 42, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(43, "RGMII_TXD2", 43,
+ 31, UNIPHIER_PIN_DRV_3BIT,
+ 43, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(44, "RGMII_TXD3", 44,
+ 32, UNIPHIER_PIN_DRV_3BIT,
+ 44, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(45, "RGMII_TXCTL", 45,
+ 33, UNIPHIER_PIN_DRV_3BIT,
+ 45, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(46, "USB0VBUS", 46,
+ 34, UNIPHIER_PIN_DRV_3BIT,
+ 46, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(47, "USB0OD", 47,
+ 35, UNIPHIER_PIN_DRV_3BIT,
+ 47, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(48, "USB1VBUS", 48,
+ 36, UNIPHIER_PIN_DRV_3BIT,
+ 48, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(49, "USB1OD", 49,
+ 37, UNIPHIER_PIN_DRV_3BIT,
+ 49, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(50, "USB2VBUS", 50,
+ 38, UNIPHIER_PIN_DRV_3BIT,
+ 50, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(51, "USB2OD", 51,
+ 39, UNIPHIER_PIN_DRV_3BIT,
+ 51, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(52, "USB3VBUS", 52,
+ 40, UNIPHIER_PIN_DRV_3BIT,
+ 52, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(53, "USB3OD", 53,
+ 41, UNIPHIER_PIN_DRV_3BIT,
+ 53, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(54, "TXD0", 54,
+ 42, UNIPHIER_PIN_DRV_3BIT,
+ 54, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(55, "RXD0", 55,
+ 43, UNIPHIER_PIN_DRV_3BIT,
+ 55, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(56, "SPISYNC0", 56,
+ 44, UNIPHIER_PIN_DRV_3BIT,
+ 56, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(57, "SPISCLK0", 57,
+ 45, UNIPHIER_PIN_DRV_3BIT,
+ 57, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(58, "SPITXD0", 58,
+ 46, UNIPHIER_PIN_DRV_3BIT,
+ 58, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(59, "SPIRXD0", 59,
+ 47, UNIPHIER_PIN_DRV_3BIT,
+ 59, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(60, "AGCI", 60,
+ 48, UNIPHIER_PIN_DRV_3BIT,
+ 60, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(61, "DMDSDA0", 61,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(62, "DMDSCL0", 62,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(63, "SDA0", 63,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(64, "SCL0", 64,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(65, "SDA1", 65,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(66, "SCL1", 66,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(67, "HIN", 67,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(68, "VIN", 68,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(69, "PCA00", 69,
+ 49, UNIPHIER_PIN_DRV_3BIT,
+ 69, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(70, "PCA01", 70,
+ 50, UNIPHIER_PIN_DRV_3BIT,
+ 70, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(71, "PCA02", 71,
+ 51, UNIPHIER_PIN_DRV_3BIT,
+ 71, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(72, "PCA03", 72,
+ 52, UNIPHIER_PIN_DRV_3BIT,
+ 72, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(73, "PCA04", 73,
+ 53, UNIPHIER_PIN_DRV_3BIT,
+ 73, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(74, "PCA05", 74,
+ 54, UNIPHIER_PIN_DRV_3BIT,
+ 74, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(75, "PCA06", 75,
+ 55, UNIPHIER_PIN_DRV_3BIT,
+ 75, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(76, "PCA07", 76,
+ 56, UNIPHIER_PIN_DRV_3BIT,
+ 76, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(77, "PCA08", 77,
+ 57, UNIPHIER_PIN_DRV_3BIT,
+ 77, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(78, "PCA09", 78,
+ 58, UNIPHIER_PIN_DRV_3BIT,
+ 78, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(79, "PCA10", 79,
+ 59, UNIPHIER_PIN_DRV_3BIT,
+ 79, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(80, "PCA11", 80,
+ 60, UNIPHIER_PIN_DRV_3BIT,
+ 80, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(81, "PCA12", 81,
+ 61, UNIPHIER_PIN_DRV_3BIT,
+ 81, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(82, "PCA13", 82,
+ 62, UNIPHIER_PIN_DRV_3BIT,
+ 82, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(83, "PCA14", 83,
+ 63, UNIPHIER_PIN_DRV_3BIT,
+ 83, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(84, "PC0READY", 84,
+ 0, UNIPHIER_PIN_DRV_1BIT,
+ 84, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(85, "PC0CD1", 85,
+ 1, UNIPHIER_PIN_DRV_1BIT,
+ 85, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(86, "PC0CD2", 86,
+ 2, UNIPHIER_PIN_DRV_1BIT,
+ 86, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(87, "PC0WAIT", 87,
+ 3, UNIPHIER_PIN_DRV_1BIT,
+ 87, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(88, "PC0RESET", 88,
+ 4, UNIPHIER_PIN_DRV_1BIT,
+ 88, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(89, "PC0CE1", 89,
+ 5, UNIPHIER_PIN_DRV_1BIT,
+ 89, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(90, "PC0WE", 90,
+ 6, UNIPHIER_PIN_DRV_1BIT,
+ 90, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(91, "PC0OE", 91,
+ 7, UNIPHIER_PIN_DRV_1BIT,
+ 91, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(92, "PC0IOWR", 92,
+ 8, UNIPHIER_PIN_DRV_1BIT,
+ 92, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(93, "PC0IORD", 93,
+ 9, UNIPHIER_PIN_DRV_1BIT,
+ 93, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(94, "PCD00", 94,
+ 10, UNIPHIER_PIN_DRV_1BIT,
+ 94, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(95, "PCD01", 95,
+ 11, UNIPHIER_PIN_DRV_1BIT,
+ 95, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(96, "PCD02", 96,
+ 12, UNIPHIER_PIN_DRV_1BIT,
+ 96, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(97, "PCD03", 97,
+ 13, UNIPHIER_PIN_DRV_1BIT,
+ 97, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(98, "PCD04", 98,
+ 14, UNIPHIER_PIN_DRV_1BIT,
+ 98, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(99, "PCD05", 99,
+ 15, UNIPHIER_PIN_DRV_1BIT,
+ 99, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(100, "PCD06", 100,
+ 16, UNIPHIER_PIN_DRV_1BIT,
+ 100, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(101, "PCD07", 101,
+ 17, UNIPHIER_PIN_DRV_1BIT,
+ 101, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(102, "HS0BCLKIN", 102,
+ 18, UNIPHIER_PIN_DRV_1BIT,
+ 102, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(103, "HS0SYNCIN", 103,
+ 19, UNIPHIER_PIN_DRV_1BIT,
+ 103, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(104, "HS0VALIN", 104,
+ 20, UNIPHIER_PIN_DRV_1BIT,
+ 104, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(105, "HS0DIN0", 105,
+ 21, UNIPHIER_PIN_DRV_1BIT,
+ 105, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(106, "HS0DIN1", 106,
+ 22, UNIPHIER_PIN_DRV_1BIT,
+ 106, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(107, "HS0DIN2", 107,
+ 23, UNIPHIER_PIN_DRV_1BIT,
+ 107, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(108, "HS0DIN3", 108,
+ 24, UNIPHIER_PIN_DRV_1BIT,
+ 108, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(109, "HS0DIN4", 109,
+ 25, UNIPHIER_PIN_DRV_1BIT,
+ 109, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(110, "HS0DIN5", 110,
+ 26, UNIPHIER_PIN_DRV_1BIT,
+ 110, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(111, "HS0DIN6", 111,
+ 27, UNIPHIER_PIN_DRV_1BIT,
+ 111, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(112, "HS0DIN7", 112,
+ 28, UNIPHIER_PIN_DRV_1BIT,
+ 112, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(113, "HS0BCLKOUT", 113,
+ 64, UNIPHIER_PIN_DRV_3BIT,
+ 113, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(114, "HS0SYNCOUT", 114,
+ 65, UNIPHIER_PIN_DRV_3BIT,
+ 114, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(115, "HS0VALOUT", 115,
+ 66, UNIPHIER_PIN_DRV_3BIT,
+ 115, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(116, "HS0DOUT0", 116,
+ 67, UNIPHIER_PIN_DRV_3BIT,
+ 116, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(117, "HS0DOUT1", 117,
+ 68, UNIPHIER_PIN_DRV_3BIT,
+ 117, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(118, "HS0DOUT2", 118,
+ 69, UNIPHIER_PIN_DRV_3BIT,
+ 118, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(119, "HS0DOUT3", 119,
+ 70, UNIPHIER_PIN_DRV_3BIT,
+ 119, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(120, "HS0DOUT4", 120,
+ 71, UNIPHIER_PIN_DRV_3BIT,
+ 120, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(121, "HS0DOUT5", 121,
+ 72, UNIPHIER_PIN_DRV_3BIT,
+ 121, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(122, "HS0DOUT6", 122,
+ 73, UNIPHIER_PIN_DRV_3BIT,
+ 122, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(123, "HS0DOUT7", 123,
+ 74, UNIPHIER_PIN_DRV_3BIT,
+ 123, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(124, "HS1BCLKIN", 124,
+ 75, UNIPHIER_PIN_DRV_3BIT,
+ 124, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(125, "HS1SYNCIN", 125,
+ 76, UNIPHIER_PIN_DRV_3BIT,
+ 125, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(126, "HS1VALIN", 126,
+ 77, UNIPHIER_PIN_DRV_3BIT,
+ 126, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(127, "HS1DIN0", 127,
+ 78, UNIPHIER_PIN_DRV_3BIT,
+ 127, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(128, "HS1DIN1", 128,
+ 79, UNIPHIER_PIN_DRV_3BIT,
+ 128, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(129, "HS1DIN2", 129,
+ 80, UNIPHIER_PIN_DRV_3BIT,
+ 129, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(130, "HS1DIN3", 130,
+ 81, UNIPHIER_PIN_DRV_3BIT,
+ 130, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(131, "HS1DIN4", 131,
+ 82, UNIPHIER_PIN_DRV_3BIT,
+ 131, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(132, "HS1DIN5", 132,
+ 83, UNIPHIER_PIN_DRV_3BIT,
+ 132, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(133, "HS1DIN6", 133,
+ 84, UNIPHIER_PIN_DRV_3BIT,
+ 133, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(134, "HS1DIN7", 134,
+ 85, UNIPHIER_PIN_DRV_3BIT,
+ 134, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(135, "AO1IEC", 135,
+ 86, UNIPHIER_PIN_DRV_3BIT,
+ 135, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(136, "AO1ARC", 136,
+ 87, UNIPHIER_PIN_DRV_3BIT,
+ 136, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(137, "AO1DACCK", 137,
+ 88, UNIPHIER_PIN_DRV_3BIT,
+ 137, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(138, "AO1BCK", 138,
+ 89, UNIPHIER_PIN_DRV_3BIT,
+ 138, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(139, "AO1LRCK", 139,
+ 90, UNIPHIER_PIN_DRV_3BIT,
+ 139, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(140, "AO1D0", 140,
+ 91, UNIPHIER_PIN_DRV_3BIT,
+ 140, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(141, "AO1D1", 141,
+ 92, UNIPHIER_PIN_DRV_3BIT,
+ 141, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(142, "AO1D2", 142,
+ 93, UNIPHIER_PIN_DRV_3BIT,
+ 142, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(143, "HTPDN0", 143,
+ 94, UNIPHIER_PIN_DRV_3BIT,
+ 143, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(144, "LOCKN0", 144,
+ 95, UNIPHIER_PIN_DRV_3BIT,
+ 144, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(145, "HTPDN1", 145,
+ 96, UNIPHIER_PIN_DRV_3BIT,
+ 145, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(146, "LOCKN1", 146,
+ 97, UNIPHIER_PIN_DRV_3BIT,
+ 146, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(147, "PWMA", 147,
+ 98, UNIPHIER_PIN_DRV_3BIT,
+ 147, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(148, "LR_GOUT", 148,
+ 99, UNIPHIER_PIN_DRV_3BIT,
+ 148, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(149, "XIRQ0", 149,
+ 100, UNIPHIER_PIN_DRV_3BIT,
+ 149, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(150, "XIRQ1", 150,
+ 101, UNIPHIER_PIN_DRV_3BIT,
+ 150, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(151, "XIRQ2", 151,
+ 102, UNIPHIER_PIN_DRV_3BIT,
+ 151, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(152, "XIRQ3", 152,
+ 103, UNIPHIER_PIN_DRV_3BIT,
+ 152, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(153, "XIRQ4", 153,
+ 104, UNIPHIER_PIN_DRV_3BIT,
+ 153, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(154, "XIRQ5", 154,
+ 105, UNIPHIER_PIN_DRV_3BIT,
+ 154, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(155, "XIRQ6", 155,
+ 106, UNIPHIER_PIN_DRV_3BIT,
+ 155, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(156, "XIRQ7", 156,
+ 107, UNIPHIER_PIN_DRV_3BIT,
+ 156, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(157, "XIRQ8", 157,
+ 108, UNIPHIER_PIN_DRV_3BIT,
+ 157, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(158, "XIRQ9", 158,
+ 109, UNIPHIER_PIN_DRV_3BIT,
+ 158, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(159, "XIRQ10", 159,
+ 110, UNIPHIER_PIN_DRV_3BIT,
+ 159, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(160, "XIRQ11", 160,
+ 111, UNIPHIER_PIN_DRV_3BIT,
+ 160, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(161, "XIRQ13", 161,
+ 112, UNIPHIER_PIN_DRV_3BIT,
+ 161, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(162, "XIRQ14", 162,
+ 113, UNIPHIER_PIN_DRV_3BIT,
+ 162, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(163, "XIRQ16", 163,
+ 114, UNIPHIER_PIN_DRV_3BIT,
+ 163, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(164, "XIRQ17", 164,
+ 115, UNIPHIER_PIN_DRV_3BIT,
+ 164, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(165, "XIRQ18", 165,
+ 116, UNIPHIER_PIN_DRV_3BIT,
+ 165, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(166, "XIRQ19", 166,
+ 117, UNIPHIER_PIN_DRV_3BIT,
+ 166, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(167, "XIRQ20", 167,
+ 118, UNIPHIER_PIN_DRV_3BIT,
+ 167, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(168, "PORT00", 168,
+ 119, UNIPHIER_PIN_DRV_3BIT,
+ 168, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(169, "PORT01", 169,
+ 120, UNIPHIER_PIN_DRV_3BIT,
+ 169, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(170, "PORT02", 170,
+ 121, UNIPHIER_PIN_DRV_3BIT,
+ 170, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(171, "PORT03", 171,
+ 122, UNIPHIER_PIN_DRV_3BIT,
+ 171, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(172, "PORT04", 172,
+ 123, UNIPHIER_PIN_DRV_3BIT,
+ 172, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(173, "CK27FO", 173,
+ 124, UNIPHIER_PIN_DRV_3BIT,
+ 173, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(174, "PHSYNCO", 174,
+ 125, UNIPHIER_PIN_DRV_3BIT,
+ 174, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(175, "PVSYNCO", 175,
+ 126, UNIPHIER_PIN_DRV_3BIT,
+ 175, UNIPHIER_PIN_PULL_DOWN),
+};
+
+static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25};
+static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
+static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const unsigned ether_rgmii_pins[] = {30, 31, 32, 33, 34, 35, 36, 37, 38,
+ 39, 40, 41, 42, 43, 44, 45};
+static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0};
+static const unsigned ether_rmii_pins[] = {30, 31, 32, 33, 34, 35, 36, 37, 39,
+ 41, 42, 45};
+static const int ether_rmii_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
+static const unsigned i2c0_pins[] = {63, 64};
+static const int i2c0_muxvals[] = {0, 0};
+static const unsigned i2c1_pins[] = {65, 66};
+static const int i2c1_muxvals[] = {0, 0};
+static const unsigned i2c3_pins[] = {67, 68};
+static const int i2c3_muxvals[] = {1, 1};
+static const unsigned i2c4_pins[] = {61, 62};
+static const int i2c4_muxvals[] = {1, 1};
+static const unsigned nand_pins[] = {3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
+ 15, 16, 17};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned sd_pins[] = {10, 11, 12, 13, 14, 15, 16, 17};
+static const int sd_muxvals[] = {3, 3, 3, 3, 3, 3, 3, 3}; /* No SDVOLC */
+static const unsigned system_bus_pins[] = {1, 2, 6, 7, 8, 9, 10, 11, 12, 13,
+ 14, 15, 16, 17};
+static const int system_bus_muxvals[] = {0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2};
+static const unsigned system_bus_cs1_pins[] = {0};
+static const int system_bus_cs1_muxvals[] = {0};
+static const unsigned uart0_pins[] = {54, 55};
+static const int uart0_muxvals[] = {0, 0};
+static const unsigned uart1_pins[] = {58, 59};
+static const int uart1_muxvals[] = {1, 1};
+static const unsigned uart2_pins[] = {90, 91};
+static const int uart2_muxvals[] = {1, 1};
+static const unsigned uart3_pins[] = {94, 95};
+static const int uart3_muxvals[] = {1, 1};
+static const unsigned usb0_pins[] = {46, 47};
+static const int usb0_muxvals[] = {0, 0};
+static const unsigned usb1_pins[] = {48, 49};
+static const int usb1_muxvals[] = {0, 0};
+static const unsigned usb2_pins[] = {50, 51};
+static const int usb2_muxvals[] = {0, 0};
+static const unsigned usb3_pins[] = {52, 53};
+static const int usb3_muxvals[] = {0, 0};
+static const unsigned port_range_pins[] = {
+ 168, 169, 170, 171, 172, 173, 174, 175, /* PORT0x */
+ 0, 1, 2, 3, 4, 5, 6, 7, /* PORT1x */
+ 8, 9, 10, 11, 12, 13, 14, 15, /* PORT2x */
+ 16, 17, 18, 30, 31, 32, 33, 34, /* PORT3x */
+ 35, 36, 37, 38, 39, 40, 41, 42, /* PORT4x */
+ 43, 44, 45, 46, 47, 48, 49, 50, /* PORT5x */
+ 51, 52, 53, 54, 55, 56, 57, 58, /* PORT6x */
+ 59, 60, 69, 70, 71, 72, 73, 74, /* PORT7x */
+ 75, 76, 77, 78, 79, 80, 81, 82, /* PORT8x */
+ 83, 84, 85, 86, 87, 88, 89, 90, /* PORT9x */
+ 91, 92, 93, 94, 95, 96, 97, 98, /* PORT10x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT11x */
+ 99, 100, 101, 102, 103, 104, 105, 106, /* PORT12x */
+ 107, 108, 109, 110, 111, 112, 113, 114, /* PORT13x */
+ 115, 116, 117, 118, 119, 120, 121, 122, /* PORT14x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT15x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT16x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT17x */
+ 61, 62, 63, 64, 65, 66, 67, 68, /* PORT18x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT19x */
+ 123, 124, 125, 126, 127, 128, 129, 130, /* PORT20x */
+ 131, 132, 133, 134, 135, 136, 137, 138, /* PORT21x */
+ 139, 140, 141, 142, 143, 144, 145, 146, /* PORT22x */
+ 147, 148, 149, 150, 151, 152, 153, 154, /* PORT23x */
+ 155, 156, 157, 158, 159, 160, 161, 162, /* PORT24x */
+ 163, 164, 165, 166, 167, /* PORT25x */
+};
+static const int port_range_muxvals[] = {
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT3x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT4x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT5x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT6x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT11x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT15x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT16x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT17x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */
+ -1, -1, -1, -1, -1, -1, -1, -1, /* PORT19x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */
+ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */
+ 15, 15, 15, 15, 15, /* PORT25x */
+};
+static const unsigned xirq_pins[] = {
+ 149, 150, 151, 152, 153, 154, 155, 156, /* XIRQ0-7 */
+ 157, 158, 159, 160, 85, 161, 162, 84, /* XIRQ8-15 */
+ 163, 164, 165, 166, 167, 146, 52, 53, /* XIRQ16-23 */
+};
+static const int xirq_muxvals[] = {
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */
+ 14, 14, 14, 14, 13, 14, 14, 13, /* XIRQ8-15 */
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */
+};
+static const unsigned xirq_alternatives_pins[] = {
+ 94, 95, 96, 97, 98, 99, 100, 101, /* XIRQ0-7 */
+ 102, 103, 104, 105, 106, 107, /* XIRQ8-11,13,14 */
+ 108, 109, 110, 111, 112, 147, 141, 142, /* XIRQ16-23 */
+};
+static const int xirq_alternatives_muxvals[] = {
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */
+ 14, 14, 14, 14, 14, 14, /* XIRQ8-11,13,14 */
+ 14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */
+};
+
+static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(ether_rgmii),
+ UNIPHIER_PINCTRL_GROUP(ether_rmii),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(i2c4),
+ UNIPHIER_PINCTRL_GROUP(nand),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP(usb2),
+ UNIPHIER_PINCTRL_GROUP(usb3),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq),
+ UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range, 23),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range, 24),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range, 25),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range, 26),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range, 27),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range, 28),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range, 29),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range, 30),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range, 31),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range, 32),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range, 33),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range, 34),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range, 35),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range, 36),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range, 37),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range, 38),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range, 39),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range, 40),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range, 41),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range, 42),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range, 43),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range, 44),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range, 45),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range, 46),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range, 47),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range, 48),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range, 49),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range, 50),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range, 51),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range, 52),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range, 53),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range, 54),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range, 55),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range, 56),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range, 57),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range, 58),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range, 59),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range, 60),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range, 61),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range, 62),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range, 63),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range, 64),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range, 65),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range, 66),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range, 67),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range, 68),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range, 69),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range, 70),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range, 71),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range, 72),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range, 73),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range, 74),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range, 75),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range, 76),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range, 77),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range, 78),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range, 79),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range, 80),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range, 81),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range, 82),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range, 83),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range, 84),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range, 85),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range, 86),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range, 87),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range, 96),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range, 97),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range, 98),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range, 99),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range, 100),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range, 101),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range, 102),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range, 103),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range, 104),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range, 105),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range, 106),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range, 107),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range, 108),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range, 109),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range, 110),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range, 111),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range, 112),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range, 113),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range, 114),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range, 115),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range, 116),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range, 117),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range, 118),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range, 119),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range, 144),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range, 145),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range, 146),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range, 147),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range, 148),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range, 149),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range, 150),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range, 151),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range, 160),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range, 161),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range, 162),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range, 163),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range, 164),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range, 165),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range, 166),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range, 167),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range, 168),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range, 169),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range, 170),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range, 171),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range, 172),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range, 173),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range, 174),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range, 175),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range, 176),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range, 177),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range, 178),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range, 179),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range, 180),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range, 181),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range, 182),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range, 183),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range, 184),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range, 185),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range, 186),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range, 187),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range, 188),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range, 189),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range, 190),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range, 191),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range, 192),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range, 193),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range, 194),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range, 195),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range, 196),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range, 197),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range, 198),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range, 199),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range, 200),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range, 201),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range, 202),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range, 203),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range, 204),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3, xirq, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4, xirq, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5, xirq, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6, xirq, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7, xirq, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8, xirq, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9, xirq, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10, xirq, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11, xirq, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq12, xirq, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13, xirq, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14, xirq, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq15, xirq, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16, xirq, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17, xirq, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18, xirq, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19, xirq, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20, xirq, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21, xirq, 21),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22, xirq, 22),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23, xirq, 23),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0b, xirq_alternatives, 0),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1b, xirq_alternatives, 1),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2b, xirq_alternatives, 2),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq3b, xirq_alternatives, 3),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq4b, xirq_alternatives, 4),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq5b, xirq_alternatives, 5),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq6b, xirq_alternatives, 6),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq7b, xirq_alternatives, 7),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq8b, xirq_alternatives, 8),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq9b, xirq_alternatives, 9),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq10b, xirq_alternatives, 10),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq11b, xirq_alternatives, 11),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq13b, xirq_alternatives, 12),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq14b, xirq_alternatives, 13),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq16b, xirq_alternatives, 14),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq17b, xirq_alternatives, 15),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq18b, xirq_alternatives, 16),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq19b, xirq_alternatives, 17),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq20b, xirq_alternatives, 18),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq21b, xirq_alternatives, 19),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq22b, xirq_alternatives, 20),
+ UNIPHIER_PINCTRL_GROUP_SINGLE(xirq23b, xirq_alternatives, 21),
+};
+
+static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
+static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
+static const char * const ether_rmii_groups[] = {"ether_rmii"};
+static const char * const i2c0_groups[] = {"i2c0"};
+static const char * const i2c1_groups[] = {"i2c1"};
+static const char * const i2c3_groups[] = {"i2c3"};
+static const char * const i2c4_groups[] = {"i2c4"};
+static const char * const nand_groups[] = {"nand"};
+static const char * const sd_groups[] = {"sd"};
+static const char * const system_bus_groups[] = {"system_bus",
+ "system_bus_cs1"};
+static const char * const uart0_groups[] = {"uart0"};
+static const char * const uart1_groups[] = {"uart1"};
+static const char * const uart2_groups[] = {"uart2"};
+static const char * const uart3_groups[] = {"uart3"};
+static const char * const usb0_groups[] = {"usb0"};
+static const char * const usb1_groups[] = {"usb1"};
+static const char * const usb2_groups[] = {"usb2"};
+static const char * const usb3_groups[] = {"usb3"};
+static const char * const port_groups[] = {
+ "port00", "port01", "port02", "port03",
+ "port04", "port05", "port06", "port07",
+ "port10", "port11", "port12", "port13",
+ "port14", "port15", "port16", "port17",
+ "port20", "port21", "port22", "port23",
+ "port24", "port25", "port26", "port27",
+ "port30", "port31", "port32", "port33",
+ "port34", "port35", "port36", "port37",
+ "port40", "port41", "port42", "port43",
+ "port44", "port45", "port46", "port47",
+ "port50", "port51", "port52", "port53",
+ "port54", "port55", "port56", "port57",
+ "port60", "port61", "port62", "port63",
+ "port64", "port65", "port66", "port67",
+ "port70", "port71", "port72", "port73",
+ "port74", "port75", "port76", "port77",
+ "port80", "port81", "port82", "port83",
+ "port84", "port85", "port86", "port87",
+ "port90", "port91", "port92", "port93",
+ "port94", "port95", "port96", "port97",
+ "port100", "port101", "port102", "port103",
+ "port104", "port105", "port106", "port107",
+ /* port110-117 missing */
+ "port120", "port121", "port122", "port123",
+ "port124", "port125", "port126", "port127",
+ "port130", "port131", "port132", "port133",
+ "port134", "port135", "port136", "port137",
+ "port140", "port141", "port142", "port143",
+ "port144", "port145", "port146", "port147",
+ /* port150-177 missing */
+ "port180", "port181", "port182", "port183",
+ "port184", "port185", "port186", "port187",
+ /* port190-197 missing */
+ "port200", "port201", "port202", "port203",
+ "port204", "port205", "port206", "port207",
+ "port210", "port211", "port212", "port213",
+ "port214", "port215", "port216", "port217",
+ "port220", "port221", "port222", "port223",
+ "port224", "port225", "port226", "port227",
+ "port230", "port231", "port232", "port233",
+ "port234", "port235", "port236", "port237",
+ "port240", "port241", "port242", "port243",
+ "port244", "port245", "port246", "port247",
+ "port250", "port251", "port252", "port253",
+ "port254",
+};
+static const char * const xirq_groups[] = {
+ "xirq0", "xirq1", "xirq2", "xirq3",
+ "xirq4", "xirq5", "xirq6", "xirq7",
+ "xirq8", "xirq9", "xirq10", "xirq11",
+ "xirq12", "xirq13", "xirq14", "xirq15",
+ "xirq16", "xirq17", "xirq18", "xirq19",
+ "xirq20", "xirq21", "xirq22", "xirq23",
+ "xirq0b", "xirq1b", "xirq2b", "xirq3b",
+ "xirq4b", "xirq5b", "xirq6b", "xirq7b",
+ "xirq8b", "xirq9b", "xirq10b", "xirq11b",
+ /* none */ "xirq13b", "xirq14b", /* none */
+ "xirq16b", "xirq17b", "xirq18b", "xirq19b",
+ "xirq20b", "xirq21b", "xirq22b", "xirq23b",
+};
+
+static const struct uniphier_pinmux_function uniphier_ld20_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
+ UNIPHIER_PINMUX_FUNCTION(ether_rmii),
+ UNIPHIER_PINMUX_FUNCTION(i2c0),
+ UNIPHIER_PINMUX_FUNCTION(i2c1),
+ UNIPHIER_PINMUX_FUNCTION(i2c3),
+ UNIPHIER_PINMUX_FUNCTION(i2c4),
+ UNIPHIER_PINMUX_FUNCTION(nand),
+ UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
+ UNIPHIER_PINMUX_FUNCTION(uart0),
+ UNIPHIER_PINMUX_FUNCTION(uart1),
+ UNIPHIER_PINMUX_FUNCTION(uart2),
+ UNIPHIER_PINMUX_FUNCTION(uart3),
+ UNIPHIER_PINMUX_FUNCTION(usb0),
+ UNIPHIER_PINMUX_FUNCTION(usb1),
+ UNIPHIER_PINMUX_FUNCTION(usb2),
+ UNIPHIER_PINMUX_FUNCTION(usb3),
+ UNIPHIER_PINMUX_FUNCTION(port),
+ UNIPHIER_PINMUX_FUNCTION(xirq),
+};
+
+static struct uniphier_pinctrl_socdata uniphier_ld20_pindata = {
+ .pins = uniphier_ld20_pins,
+ .npins = ARRAY_SIZE(uniphier_ld20_pins),
+ .groups = uniphier_ld20_groups,
+ .groups_count = ARRAY_SIZE(uniphier_ld20_groups),
+ .functions = uniphier_ld20_functions,
+ .functions_count = ARRAY_SIZE(uniphier_ld20_functions),
+ .caps = UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL,
+};
+
+static int uniphier_ld20_pinctrl_probe(struct platform_device *pdev)
+{
+ return uniphier_pinctrl_probe(pdev, &uniphier_ld20_pindata);
+}
+
+static const struct of_device_id uniphier_ld20_pinctrl_match[] = {
+ { .compatible = "socionext,uniphier-ld20-pinctrl" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, uniphier_ld20_pinctrl_match);
+
+static struct platform_driver uniphier_ld20_pinctrl_driver = {
+ .probe = uniphier_ld20_pinctrl_probe,
+ .driver = {
+ .name = "uniphier-ld20-pinctrl",
+ .of_match_table = uniphier_ld20_pinctrl_match,
+ },
+};
+module_platform_driver(uniphier_ld20_pinctrl_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier PH1-LD20 pinctrl driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
index 4a0439c80aa0..3edfb6f9d6df 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c
@@ -19,544 +19,592 @@
#include "pinctrl-uniphier.h"
-#define DRIVER_NAME "ph1-ld4-pinctrl"
-
-static const struct pinctrl_pin_desc ph1_ld4_pins[] = {
+static const struct pinctrl_pin_desc uniphier_ld4_pins[] = {
UNIPHIER_PINCTRL_PIN(0, "EA1", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_4_8,
+ 8, UNIPHIER_PIN_DRV_1BIT,
8, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(1, "EA2", UNIPHIER_PIN_IECTRL_NONE,
- 9, UNIPHIER_PIN_DRV_4_8,
+ 9, UNIPHIER_PIN_DRV_1BIT,
9, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(2, "EA3", UNIPHIER_PIN_IECTRL_NONE,
- 10, UNIPHIER_PIN_DRV_4_8,
+ 10, UNIPHIER_PIN_DRV_1BIT,
10, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(3, "EA4", UNIPHIER_PIN_IECTRL_NONE,
- 11, UNIPHIER_PIN_DRV_4_8,
+ 11, UNIPHIER_PIN_DRV_1BIT,
11, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(4, "EA5", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_4_8,
+ 12, UNIPHIER_PIN_DRV_1BIT,
12, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(5, "EA6", UNIPHIER_PIN_IECTRL_NONE,
- 13, UNIPHIER_PIN_DRV_4_8,
+ 13, UNIPHIER_PIN_DRV_1BIT,
13, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(6, "EA7", UNIPHIER_PIN_IECTRL_NONE,
- 14, UNIPHIER_PIN_DRV_4_8,
+ 14, UNIPHIER_PIN_DRV_1BIT,
14, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(7, "EA8", 0,
- 15, UNIPHIER_PIN_DRV_4_8,
+ 15, UNIPHIER_PIN_DRV_1BIT,
15, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(8, "EA9", 0,
- 16, UNIPHIER_PIN_DRV_4_8,
+ 16, UNIPHIER_PIN_DRV_1BIT,
16, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(9, "EA10", 0,
- 17, UNIPHIER_PIN_DRV_4_8,
+ 17, UNIPHIER_PIN_DRV_1BIT,
17, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(10, "EA11", 0,
- 18, UNIPHIER_PIN_DRV_4_8,
+ 18, UNIPHIER_PIN_DRV_1BIT,
18, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(11, "EA12", 0,
- 19, UNIPHIER_PIN_DRV_4_8,
+ 19, UNIPHIER_PIN_DRV_1BIT,
19, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(12, "EA13", 0,
- 20, UNIPHIER_PIN_DRV_4_8,
+ 20, UNIPHIER_PIN_DRV_1BIT,
20, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(13, "EA14", 0,
- 21, UNIPHIER_PIN_DRV_4_8,
+ 21, UNIPHIER_PIN_DRV_1BIT,
21, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(14, "EA15", 0,
- 22, UNIPHIER_PIN_DRV_4_8,
+ 22, UNIPHIER_PIN_DRV_1BIT,
22, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(15, "ECLK", UNIPHIER_PIN_IECTRL_NONE,
- 23, UNIPHIER_PIN_DRV_4_8,
+ 23, UNIPHIER_PIN_DRV_1BIT,
23, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(16, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
- 24, UNIPHIER_PIN_DRV_4_8,
+ 24, UNIPHIER_PIN_DRV_1BIT,
24, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(17, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
- 25, UNIPHIER_PIN_DRV_4_8,
+ 25, UNIPHIER_PIN_DRV_1BIT,
25, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(18, "ES0", UNIPHIER_PIN_IECTRL_NONE,
- 27, UNIPHIER_PIN_DRV_4_8,
+ 27, UNIPHIER_PIN_DRV_1BIT,
27, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(19, "ES1", UNIPHIER_PIN_IECTRL_NONE,
- 28, UNIPHIER_PIN_DRV_4_8,
+ 28, UNIPHIER_PIN_DRV_1BIT,
28, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(20, "ES2", UNIPHIER_PIN_IECTRL_NONE,
- 29, UNIPHIER_PIN_DRV_4_8,
+ 29, UNIPHIER_PIN_DRV_1BIT,
29, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(21, "XERST", UNIPHIER_PIN_IECTRL_NONE,
- 38, UNIPHIER_PIN_DRV_4_8,
+ 38, UNIPHIER_PIN_DRV_1BIT,
38, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(22, "MMCCLK", UNIPHIER_PIN_IECTRL_NONE,
- 0, UNIPHIER_PIN_DRV_8_12_16_20,
+ 0, UNIPHIER_PIN_DRV_2BIT,
146, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(23, "MMCCMD", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_8_12_16_20,
+ 1, UNIPHIER_PIN_DRV_2BIT,
147, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(24, "MMCDAT0", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_8_12_16_20,
+ 2, UNIPHIER_PIN_DRV_2BIT,
148, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(25, "MMCDAT1", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_8_12_16_20,
+ 3, UNIPHIER_PIN_DRV_2BIT,
149, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(26, "MMCDAT2", UNIPHIER_PIN_IECTRL_NONE,
- 16, UNIPHIER_PIN_DRV_8_12_16_20,
+ 4, UNIPHIER_PIN_DRV_2BIT,
150, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(27, "MMCDAT3", UNIPHIER_PIN_IECTRL_NONE,
- 20, UNIPHIER_PIN_DRV_8_12_16_20,
+ 5, UNIPHIER_PIN_DRV_2BIT,
151, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(28, "MMCDAT4", UNIPHIER_PIN_IECTRL_NONE,
- 24, UNIPHIER_PIN_DRV_8_12_16_20,
+ 6, UNIPHIER_PIN_DRV_2BIT,
152, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(29, "MMCDAT5", UNIPHIER_PIN_IECTRL_NONE,
- 28, UNIPHIER_PIN_DRV_8_12_16_20,
+ 7, UNIPHIER_PIN_DRV_2BIT,
153, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(30, "MMCDAT6", UNIPHIER_PIN_IECTRL_NONE,
- 32, UNIPHIER_PIN_DRV_8_12_16_20,
+ 8, UNIPHIER_PIN_DRV_2BIT,
154, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(31, "MMCDAT7", UNIPHIER_PIN_IECTRL_NONE,
- 36, UNIPHIER_PIN_DRV_8_12_16_20,
+ 9, UNIPHIER_PIN_DRV_2BIT,
155, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(32, "RMII_RXD0", 6,
- 39, UNIPHIER_PIN_DRV_4_8,
+ 39, UNIPHIER_PIN_DRV_1BIT,
39, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(33, "RMII_RXD1", 6,
- 40, UNIPHIER_PIN_DRV_4_8,
+ 40, UNIPHIER_PIN_DRV_1BIT,
40, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(34, "RMII_CRS_DV", 6,
- 41, UNIPHIER_PIN_DRV_4_8,
+ 41, UNIPHIER_PIN_DRV_1BIT,
41, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(35, "RMII_RXER", 6,
- 42, UNIPHIER_PIN_DRV_4_8,
+ 42, UNIPHIER_PIN_DRV_1BIT,
42, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(36, "RMII_REFCLK", 6,
- 43, UNIPHIER_PIN_DRV_4_8,
+ 43, UNIPHIER_PIN_DRV_1BIT,
43, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(37, "RMII_TXD0", 6,
- 44, UNIPHIER_PIN_DRV_4_8,
+ 44, UNIPHIER_PIN_DRV_1BIT,
44, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(38, "RMII_TXD1", 6,
- 45, UNIPHIER_PIN_DRV_4_8,
+ 45, UNIPHIER_PIN_DRV_1BIT,
45, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(39, "RMII_TXEN", 6,
- 46, UNIPHIER_PIN_DRV_4_8,
+ 46, UNIPHIER_PIN_DRV_1BIT,
46, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(40, "MDC", 6,
- 47, UNIPHIER_PIN_DRV_4_8,
+ 47, UNIPHIER_PIN_DRV_1BIT,
47, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(41, "MDIO", 6,
- 48, UNIPHIER_PIN_DRV_4_8,
+ 48, UNIPHIER_PIN_DRV_1BIT,
48, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(42, "MDIO_INTL", 6,
- 49, UNIPHIER_PIN_DRV_4_8,
+ 49, UNIPHIER_PIN_DRV_1BIT,
49, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(43, "PHYRSTL", 6,
- 50, UNIPHIER_PIN_DRV_4_8,
+ 50, UNIPHIER_PIN_DRV_1BIT,
50, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(44, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
- 40, UNIPHIER_PIN_DRV_8_12_16_20,
+ 10, UNIPHIER_PIN_DRV_2BIT,
156, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(45, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
- 44, UNIPHIER_PIN_DRV_8_12_16_20,
+ 11, UNIPHIER_PIN_DRV_2BIT,
157, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(46, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
- 48, UNIPHIER_PIN_DRV_8_12_16_20,
+ 12, UNIPHIER_PIN_DRV_2BIT,
158, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(47, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
- 52, UNIPHIER_PIN_DRV_8_12_16_20,
+ 13, UNIPHIER_PIN_DRV_2BIT,
159, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(48, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
- 56, UNIPHIER_PIN_DRV_8_12_16_20,
+ 14, UNIPHIER_PIN_DRV_2BIT,
160, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(49, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
- 60, UNIPHIER_PIN_DRV_8_12_16_20,
+ 15, UNIPHIER_PIN_DRV_2BIT,
161, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(50, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
- 51, UNIPHIER_PIN_DRV_4_8,
+ 51, UNIPHIER_PIN_DRV_1BIT,
51, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(51, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
- 52, UNIPHIER_PIN_DRV_4_8,
+ 52, UNIPHIER_PIN_DRV_1BIT,
52, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(52, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
- 53, UNIPHIER_PIN_DRV_4_8,
+ 53, UNIPHIER_PIN_DRV_1BIT,
53, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(53, "USB0VBUS", 0,
- 54, UNIPHIER_PIN_DRV_4_8,
+ 54, UNIPHIER_PIN_DRV_1BIT,
54, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(54, "USB0OD", 0,
- 55, UNIPHIER_PIN_DRV_4_8,
+ 55, UNIPHIER_PIN_DRV_1BIT,
55, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(55, "USB1VBUS", 0,
- 56, UNIPHIER_PIN_DRV_4_8,
+ 56, UNIPHIER_PIN_DRV_1BIT,
56, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(56, "USB1OD", 0,
- 57, UNIPHIER_PIN_DRV_4_8,
+ 57, UNIPHIER_PIN_DRV_1BIT,
57, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(57, "PCRESET", 0,
- 58, UNIPHIER_PIN_DRV_4_8,
+ 58, UNIPHIER_PIN_DRV_1BIT,
58, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(58, "PCREG", 0,
- 59, UNIPHIER_PIN_DRV_4_8,
+ 59, UNIPHIER_PIN_DRV_1BIT,
59, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(59, "PCCE2", 0,
- 60, UNIPHIER_PIN_DRV_4_8,
+ 60, UNIPHIER_PIN_DRV_1BIT,
60, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(60, "PCVS1", 0,
- 61, UNIPHIER_PIN_DRV_4_8,
+ 61, UNIPHIER_PIN_DRV_1BIT,
61, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(61, "PCCD2", 0,
- 62, UNIPHIER_PIN_DRV_4_8,
+ 62, UNIPHIER_PIN_DRV_1BIT,
62, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(62, "PCCD1", 0,
- 63, UNIPHIER_PIN_DRV_4_8,
+ 63, UNIPHIER_PIN_DRV_1BIT,
63, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(63, "PCREADY", 0,
- 64, UNIPHIER_PIN_DRV_4_8,
+ 64, UNIPHIER_PIN_DRV_1BIT,
64, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(64, "PCDOE", 0,
- 65, UNIPHIER_PIN_DRV_4_8,
+ 65, UNIPHIER_PIN_DRV_1BIT,
65, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(65, "PCCE1", 0,
- 66, UNIPHIER_PIN_DRV_4_8,
+ 66, UNIPHIER_PIN_DRV_1BIT,
66, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(66, "PCWE", 0,
- 67, UNIPHIER_PIN_DRV_4_8,
+ 67, UNIPHIER_PIN_DRV_1BIT,
67, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(67, "PCOE", 0,
- 68, UNIPHIER_PIN_DRV_4_8,
+ 68, UNIPHIER_PIN_DRV_1BIT,
68, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(68, "PCWAIT", 0,
- 69, UNIPHIER_PIN_DRV_4_8,
+ 69, UNIPHIER_PIN_DRV_1BIT,
69, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(69, "PCIOWR", 0,
- 70, UNIPHIER_PIN_DRV_4_8,
+ 70, UNIPHIER_PIN_DRV_1BIT,
70, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(70, "PCIORD", 0,
- 71, UNIPHIER_PIN_DRV_4_8,
+ 71, UNIPHIER_PIN_DRV_1BIT,
71, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(71, "HS0DIN0", 0,
- 72, UNIPHIER_PIN_DRV_4_8,
+ 72, UNIPHIER_PIN_DRV_1BIT,
72, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(72, "HS0DIN1", 0,
- 73, UNIPHIER_PIN_DRV_4_8,
+ 73, UNIPHIER_PIN_DRV_1BIT,
73, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(73, "HS0DIN2", 0,
- 74, UNIPHIER_PIN_DRV_4_8,
+ 74, UNIPHIER_PIN_DRV_1BIT,
74, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(74, "HS0DIN3", 0,
- 75, UNIPHIER_PIN_DRV_4_8,
+ 75, UNIPHIER_PIN_DRV_1BIT,
75, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(75, "HS0DIN4", 0,
- 76, UNIPHIER_PIN_DRV_4_8,
+ 76, UNIPHIER_PIN_DRV_1BIT,
76, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(76, "HS0DIN5", 0,
- 77, UNIPHIER_PIN_DRV_4_8,
+ 77, UNIPHIER_PIN_DRV_1BIT,
77, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(77, "HS0DIN6", 0,
- 78, UNIPHIER_PIN_DRV_4_8,
+ 78, UNIPHIER_PIN_DRV_1BIT,
78, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(78, "HS0DIN7", 0,
- 79, UNIPHIER_PIN_DRV_4_8,
+ 79, UNIPHIER_PIN_DRV_1BIT,
79, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(79, "HS0BCLKIN", 0,
- 80, UNIPHIER_PIN_DRV_4_8,
+ 80, UNIPHIER_PIN_DRV_1BIT,
80, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(80, "HS0VALIN", 0,
- 81, UNIPHIER_PIN_DRV_4_8,
+ 81, UNIPHIER_PIN_DRV_1BIT,
81, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(81, "HS0SYNCIN", 0,
- 82, UNIPHIER_PIN_DRV_4_8,
+ 82, UNIPHIER_PIN_DRV_1BIT,
82, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(82, "HSDOUT0", 0,
- 83, UNIPHIER_PIN_DRV_4_8,
+ 83, UNIPHIER_PIN_DRV_1BIT,
83, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(83, "HSDOUT1", 0,
- 84, UNIPHIER_PIN_DRV_4_8,
+ 84, UNIPHIER_PIN_DRV_1BIT,
84, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(84, "HSDOUT2", 0,
- 85, UNIPHIER_PIN_DRV_4_8,
+ 85, UNIPHIER_PIN_DRV_1BIT,
85, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(85, "HSDOUT3", 0,
- 86, UNIPHIER_PIN_DRV_4_8,
+ 86, UNIPHIER_PIN_DRV_1BIT,
86, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(86, "HSDOUT4", 0,
- 87, UNIPHIER_PIN_DRV_4_8,
+ 87, UNIPHIER_PIN_DRV_1BIT,
87, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(87, "HSDOUT5", 0,
- 88, UNIPHIER_PIN_DRV_4_8,
+ 88, UNIPHIER_PIN_DRV_1BIT,
88, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(88, "HSDOUT6", 0,
- 89, UNIPHIER_PIN_DRV_4_8,
+ 89, UNIPHIER_PIN_DRV_1BIT,
89, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(89, "HSDOUT7", 0,
- 90, UNIPHIER_PIN_DRV_4_8,
+ 90, UNIPHIER_PIN_DRV_1BIT,
90, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(90, "HSBCLKOUT", 0,
- 91, UNIPHIER_PIN_DRV_4_8,
+ 91, UNIPHIER_PIN_DRV_1BIT,
91, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(91, "HSVALOUT", 0,
- 92, UNIPHIER_PIN_DRV_4_8,
+ 92, UNIPHIER_PIN_DRV_1BIT,
92, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(92, "HSSYNCOUT", 0,
- 93, UNIPHIER_PIN_DRV_4_8,
+ 93, UNIPHIER_PIN_DRV_1BIT,
93, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(93, "AGCI", 3,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
162, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(94, "AGCR", 4,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
163, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(95, "AGCBS", 5,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
164, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(96, "IECOUT", 0,
- 94, UNIPHIER_PIN_DRV_4_8,
+ 94, UNIPHIER_PIN_DRV_1BIT,
94, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(97, "ASMCK", 0,
- 95, UNIPHIER_PIN_DRV_4_8,
+ 95, UNIPHIER_PIN_DRV_1BIT,
95, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(98, "ABCKO", UNIPHIER_PIN_IECTRL_NONE,
- 96, UNIPHIER_PIN_DRV_4_8,
+ 96, UNIPHIER_PIN_DRV_1BIT,
96, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(99, "ALRCKO", UNIPHIER_PIN_IECTRL_NONE,
- 97, UNIPHIER_PIN_DRV_4_8,
+ 97, UNIPHIER_PIN_DRV_1BIT,
97, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(100, "ASDOUT0", UNIPHIER_PIN_IECTRL_NONE,
- 98, UNIPHIER_PIN_DRV_4_8,
+ 98, UNIPHIER_PIN_DRV_1BIT,
98, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(101, "ARCOUT", 0,
- 99, UNIPHIER_PIN_DRV_4_8,
+ 99, UNIPHIER_PIN_DRV_1BIT,
99, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(102, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(103, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(104, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(105, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(106, "DMDSDA0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(107, "DMDSCL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(108, "DMDSDA1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(109, "DMDSCL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(110, "SBO0", UNIPHIER_PIN_IECTRL_NONE,
- 100, UNIPHIER_PIN_DRV_4_8,
+ 100, UNIPHIER_PIN_DRV_1BIT,
100, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(111, "SBI0", UNIPHIER_PIN_IECTRL_NONE,
- 101, UNIPHIER_PIN_DRV_4_8,
+ 101, UNIPHIER_PIN_DRV_1BIT,
101, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(112, "HIN", 1,
- -1, UNIPHIER_PIN_DRV_FIXED_5,
+ -1, UNIPHIER_PIN_DRV_FIXED5,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(113, "VIN", 2,
- -1, UNIPHIER_PIN_DRV_FIXED_5,
+ -1, UNIPHIER_PIN_DRV_FIXED5,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(114, "TCON0", UNIPHIER_PIN_IECTRL_NONE,
- 102, UNIPHIER_PIN_DRV_4_8,
+ 102, UNIPHIER_PIN_DRV_1BIT,
102, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(115, "TCON1", UNIPHIER_PIN_IECTRL_NONE,
- 103, UNIPHIER_PIN_DRV_4_8,
+ 103, UNIPHIER_PIN_DRV_1BIT,
103, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(116, "TCON2", UNIPHIER_PIN_IECTRL_NONE,
- 104, UNIPHIER_PIN_DRV_4_8,
+ 104, UNIPHIER_PIN_DRV_1BIT,
104, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(117, "TCON3", UNIPHIER_PIN_IECTRL_NONE,
- 105, UNIPHIER_PIN_DRV_4_8,
+ 105, UNIPHIER_PIN_DRV_1BIT,
105, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(118, "TCON4", UNIPHIER_PIN_IECTRL_NONE,
- 106, UNIPHIER_PIN_DRV_4_8,
+ 106, UNIPHIER_PIN_DRV_1BIT,
106, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(119, "TCON5", UNIPHIER_PIN_IECTRL_NONE,
- 107, UNIPHIER_PIN_DRV_4_8,
+ 107, UNIPHIER_PIN_DRV_1BIT,
107, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(120, "TCON6", 0,
- 108, UNIPHIER_PIN_DRV_4_8,
+ 108, UNIPHIER_PIN_DRV_1BIT,
108, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(121, "TCON7", 0,
- 109, UNIPHIER_PIN_DRV_4_8,
+ 109, UNIPHIER_PIN_DRV_1BIT,
109, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(122, "PWMA", 0,
- 110, UNIPHIER_PIN_DRV_4_8,
+ 110, UNIPHIER_PIN_DRV_1BIT,
110, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(123, "XIRQ1", 0,
- 111, UNIPHIER_PIN_DRV_4_8,
+ 111, UNIPHIER_PIN_DRV_1BIT,
111, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(124, "XIRQ2", 0,
- 112, UNIPHIER_PIN_DRV_4_8,
+ 112, UNIPHIER_PIN_DRV_1BIT,
112, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(125, "XIRQ3", 0,
- 113, UNIPHIER_PIN_DRV_4_8,
+ 113, UNIPHIER_PIN_DRV_1BIT,
113, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(126, "XIRQ4", 0,
- 114, UNIPHIER_PIN_DRV_4_8,
+ 114, UNIPHIER_PIN_DRV_1BIT,
114, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(127, "XIRQ5", 0,
- 115, UNIPHIER_PIN_DRV_4_8,
+ 115, UNIPHIER_PIN_DRV_1BIT,
115, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(128, "XIRQ6", 0,
- 116, UNIPHIER_PIN_DRV_4_8,
+ 116, UNIPHIER_PIN_DRV_1BIT,
116, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(129, "XIRQ7", 0,
- 117, UNIPHIER_PIN_DRV_4_8,
+ 117, UNIPHIER_PIN_DRV_1BIT,
117, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(130, "XIRQ8", 0,
- 118, UNIPHIER_PIN_DRV_4_8,
+ 118, UNIPHIER_PIN_DRV_1BIT,
118, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(131, "XIRQ9", 0,
- 119, UNIPHIER_PIN_DRV_4_8,
+ 119, UNIPHIER_PIN_DRV_1BIT,
119, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(132, "XIRQ10", 0,
- 120, UNIPHIER_PIN_DRV_4_8,
+ 120, UNIPHIER_PIN_DRV_1BIT,
120, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(133, "XIRQ11", 0,
- 121, UNIPHIER_PIN_DRV_4_8,
+ 121, UNIPHIER_PIN_DRV_1BIT,
121, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(134, "XIRQ14", 0,
- 122, UNIPHIER_PIN_DRV_4_8,
+ 122, UNIPHIER_PIN_DRV_1BIT,
122, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(135, "PORT00", 0,
- 123, UNIPHIER_PIN_DRV_4_8,
+ 123, UNIPHIER_PIN_DRV_1BIT,
123, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(136, "PORT01", 0,
- 124, UNIPHIER_PIN_DRV_4_8,
+ 124, UNIPHIER_PIN_DRV_1BIT,
124, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(137, "PORT02", 0,
- 125, UNIPHIER_PIN_DRV_4_8,
+ 125, UNIPHIER_PIN_DRV_1BIT,
125, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(138, "PORT03", 0,
- 126, UNIPHIER_PIN_DRV_4_8,
+ 126, UNIPHIER_PIN_DRV_1BIT,
126, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(139, "PORT04", 0,
- 127, UNIPHIER_PIN_DRV_4_8,
+ 127, UNIPHIER_PIN_DRV_1BIT,
127, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(140, "PORT05", 0,
- 128, UNIPHIER_PIN_DRV_4_8,
+ 128, UNIPHIER_PIN_DRV_1BIT,
128, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(141, "PORT06", 0,
- 129, UNIPHIER_PIN_DRV_4_8,
+ 129, UNIPHIER_PIN_DRV_1BIT,
129, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(142, "PORT07", 0,
- 130, UNIPHIER_PIN_DRV_4_8,
+ 130, UNIPHIER_PIN_DRV_1BIT,
130, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(143, "PORT10", 0,
- 131, UNIPHIER_PIN_DRV_4_8,
+ 131, UNIPHIER_PIN_DRV_1BIT,
131, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(144, "PORT11", 0,
- 132, UNIPHIER_PIN_DRV_4_8,
+ 132, UNIPHIER_PIN_DRV_1BIT,
132, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(145, "PORT12", 0,
- 133, UNIPHIER_PIN_DRV_4_8,
+ 133, UNIPHIER_PIN_DRV_1BIT,
133, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(146, "PORT13", 0,
- 134, UNIPHIER_PIN_DRV_4_8,
+ 134, UNIPHIER_PIN_DRV_1BIT,
134, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(147, "PORT14", 0,
- 135, UNIPHIER_PIN_DRV_4_8,
+ 135, UNIPHIER_PIN_DRV_1BIT,
135, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(148, "PORT15", 0,
- 136, UNIPHIER_PIN_DRV_4_8,
+ 136, UNIPHIER_PIN_DRV_1BIT,
136, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(149, "PORT16", 0,
- 137, UNIPHIER_PIN_DRV_4_8,
+ 137, UNIPHIER_PIN_DRV_1BIT,
137, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(150, "PORT17", UNIPHIER_PIN_IECTRL_NONE,
- 138, UNIPHIER_PIN_DRV_4_8,
+ 138, UNIPHIER_PIN_DRV_1BIT,
138, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(151, "PORT20", 0,
- 139, UNIPHIER_PIN_DRV_4_8,
+ 139, UNIPHIER_PIN_DRV_1BIT,
139, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(152, "PORT21", 0,
- 140, UNIPHIER_PIN_DRV_4_8,
+ 140, UNIPHIER_PIN_DRV_1BIT,
140, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(153, "PORT22", 0,
- 141, UNIPHIER_PIN_DRV_4_8,
+ 141, UNIPHIER_PIN_DRV_1BIT,
141, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(154, "PORT23", 0,
- 142, UNIPHIER_PIN_DRV_4_8,
+ 142, UNIPHIER_PIN_DRV_1BIT,
142, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(155, "PORT24", UNIPHIER_PIN_IECTRL_NONE,
- 143, UNIPHIER_PIN_DRV_4_8,
+ 143, UNIPHIER_PIN_DRV_1BIT,
143, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(156, "PORT25", 0,
- 144, UNIPHIER_PIN_DRV_4_8,
+ 144, UNIPHIER_PIN_DRV_1BIT,
144, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(157, "PORT26", 0,
- 145, UNIPHIER_PIN_DRV_4_8,
+ 145, UNIPHIER_PIN_DRV_1BIT,
145, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(158, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
- 31, UNIPHIER_PIN_DRV_4_8,
+ 31, UNIPHIER_PIN_DRV_1BIT,
31, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(159, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
- 32, UNIPHIER_PIN_DRV_4_8,
+ 32, UNIPHIER_PIN_DRV_1BIT,
32, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(160, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
- 33, UNIPHIER_PIN_DRV_4_8,
+ 33, UNIPHIER_PIN_DRV_1BIT,
33, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(161, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
- 34, UNIPHIER_PIN_DRV_4_8,
+ 34, UNIPHIER_PIN_DRV_1BIT,
34, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(162, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
- 35, UNIPHIER_PIN_DRV_4_8,
+ 35, UNIPHIER_PIN_DRV_1BIT,
35, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(163, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
- 36, UNIPHIER_PIN_DRV_4_8,
+ 36, UNIPHIER_PIN_DRV_1BIT,
36, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(164, "NANDRYBY0", UNIPHIER_PIN_IECTRL_NONE,
- 37, UNIPHIER_PIN_DRV_4_8,
+ 37, UNIPHIER_PIN_DRV_1BIT,
37, UNIPHIER_PIN_PULL_UP),
+ /* dedicated pins */
+ UNIPHIER_PINCTRL_PIN(165, "ED0", -1,
+ 0, UNIPHIER_PIN_DRV_1BIT,
+ 0, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(166, "ED1", -1,
+ 1, UNIPHIER_PIN_DRV_1BIT,
+ 1, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(167, "ED2", -1,
+ 2, UNIPHIER_PIN_DRV_1BIT,
+ 2, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(168, "ED3", -1,
+ 3, UNIPHIER_PIN_DRV_1BIT,
+ 3, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(169, "ED4", -1,
+ 4, UNIPHIER_PIN_DRV_1BIT,
+ 4, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(170, "ED5", -1,
+ 5, UNIPHIER_PIN_DRV_1BIT,
+ 5, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(171, "ED6", -1,
+ 6, UNIPHIER_PIN_DRV_1BIT,
+ 6, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(172, "ED7", -1,
+ 7, UNIPHIER_PIN_DRV_1BIT,
+ 7, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(173, "ERXW", -1,
+ 26, UNIPHIER_PIN_DRV_1BIT,
+ 26, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(174, "XECS1", -1,
+ 30, UNIPHIER_PIN_DRV_1BIT,
+ 30, UNIPHIER_PIN_PULL_UP),
};
static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
-static const unsigned emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1};
+static const int emmc_muxvals[] = {0, 1, 1, 1, 1, 1, 1};
static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
-static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned ether_mii_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40,
+ 41, 42, 43, 136, 137, 138, 139, 140,
+ 141, 142};
+static const int ether_mii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 4, 4, 4, 4, 4, 4, 4};
+static const unsigned ether_rmii_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40,
+ 41, 42, 43};
+static const int ether_rmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned i2c0_pins[] = {102, 103};
-static const unsigned i2c0_muxvals[] = {0, 0};
+static const int i2c0_muxvals[] = {0, 0};
static const unsigned i2c1_pins[] = {104, 105};
-static const unsigned i2c1_muxvals[] = {0, 0};
+static const int i2c1_muxvals[] = {0, 0};
static const unsigned i2c2_pins[] = {108, 109};
-static const unsigned i2c2_muxvals[] = {2, 2};
+static const int i2c2_muxvals[] = {2, 2};
static const unsigned i2c3_pins[] = {108, 109};
-static const unsigned i2c3_muxvals[] = {3, 3};
+static const int i2c3_muxvals[] = {3, 3};
static const unsigned nand_pins[] = {24, 25, 26, 27, 28, 29, 30, 31, 158, 159,
160, 161, 162, 163, 164};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned nand_cs1_pins[] = {22, 23};
-static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {44, 45, 46, 47, 48, 49, 50, 51, 52};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned system_bus_pins[] = {16, 17, 18, 19, 20, 165, 166, 167,
+ 168, 169, 170, 171, 172, 173};
+static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1};
+static const unsigned system_bus_cs0_pins[] = {155};
+static const int system_bus_cs0_muxvals[] = {1};
+static const unsigned system_bus_cs1_pins[] = {174};
+static const int system_bus_cs1_muxvals[] = {-1};
+static const unsigned system_bus_cs2_pins[] = {64};
+static const int system_bus_cs2_muxvals[] = {1};
+static const unsigned system_bus_cs3_pins[] = {156};
+static const int system_bus_cs3_muxvals[] = {1};
static const unsigned uart0_pins[] = {85, 88};
-static const unsigned uart0_muxvals[] = {1, 1};
+static const int uart0_muxvals[] = {1, 1};
static const unsigned uart1_pins[] = {155, 156};
-static const unsigned uart1_muxvals[] = {13, 13};
+static const int uart1_muxvals[] = {13, 13};
static const unsigned uart1b_pins[] = {69, 70};
-static const unsigned uart1b_muxvals[] = {23, 23};
+static const int uart1b_muxvals[] = {23, 23};
static const unsigned uart2_pins[] = {128, 129};
-static const unsigned uart2_muxvals[] = {13, 13};
+static const int uart2_muxvals[] = {13, 13};
static const unsigned uart3_pins[] = {110, 111};
-static const unsigned uart3_muxvals[] = {1, 1};
+static const int uart3_muxvals[] = {1, 1};
static const unsigned usb0_pins[] = {53, 54};
-static const unsigned usb0_muxvals[] = {0, 0};
+static const int usb0_muxvals[] = {0, 0};
static const unsigned usb1_pins[] = {55, 56};
-static const unsigned usb1_muxvals[] = {0, 0};
+static const int usb1_muxvals[] = {0, 0};
static const unsigned usb2_pins[] = {155, 156};
-static const unsigned usb2_muxvals[] = {4, 4};
+static const int usb2_muxvals[] = {4, 4};
static const unsigned usb2b_pins[] = {67, 68};
-static const unsigned usb2b_muxvals[] = {23, 23};
+static const int usb2b_muxvals[] = {23, 23};
static const unsigned port_range0_pins[] = {
135, 136, 137, 138, 139, 140, 141, 142, /* PORT0x */
143, 144, 145, 146, 147, 148, 149, 150, /* PORT1x */
@@ -574,7 +622,7 @@ static const unsigned port_range0_pins[] = {
98, 99, 100, 6, 101, 114, 115, 116, /* PORT13x */
103, 108, 21, 22, 23, 117, 118, 119, /* PORT14x */
};
-static const unsigned port_range0_muxvals[] = {
+static const int port_range0_muxvals[] = {
0, 0, 0, 0, 0, 0, 0, 0, /* PORT0x */
0, 0, 0, 0, 0, 0, 0, 0, /* PORT1x */
0, 0, 0, 0, 0, 0, 0, 15, /* PORT2x */
@@ -594,27 +642,29 @@ static const unsigned port_range0_muxvals[] = {
static const unsigned port_range1_pins[] = {
7, /* PORT166 */
};
-static const unsigned port_range1_muxvals[] = {
+static const int port_range1_muxvals[] = {
15, /* PORT166 */
};
static const unsigned xirq_range0_pins[] = {
151, 123, 124, 125, 126, 127, 128, 129, /* XIRQ0-7 */
130, 131, 132, 133, 62, /* XIRQ8-12 */
};
-static const unsigned xirq_range0_muxvals[] = {
+static const int xirq_range0_muxvals[] = {
14, 0, 0, 0, 0, 0, 0, 0, /* XIRQ0-7 */
0, 0, 0, 0, 14, /* XIRQ8-12 */
};
static const unsigned xirq_range1_pins[] = {
134, 63, /* XIRQ14-15 */
};
-static const unsigned xirq_range1_muxvals[] = {
+static const int xirq_range1_muxvals[] = {
0, 14, /* XIRQ14-15 */
};
-static const struct uniphier_pinctrl_group ph1_ld4_groups[] = {
+static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = {
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(ether_mii),
+ UNIPHIER_PINCTRL_GROUP(ether_rmii),
UNIPHIER_PINCTRL_GROUP(i2c0),
UNIPHIER_PINCTRL_GROUP(i2c1),
UNIPHIER_PINCTRL_GROUP(i2c2),
@@ -622,6 +672,11 @@ static const struct uniphier_pinctrl_group ph1_ld4_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart1b),
@@ -774,12 +829,19 @@ static const struct uniphier_pinctrl_group ph1_ld4_groups[] = {
};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
+static const char * const ether_mii_groups[] = {"ether_mii"};
+static const char * const ether_rmii_groups[] = {"ether_rmii"};
static const char * const i2c0_groups[] = {"i2c0"};
static const char * const i2c1_groups[] = {"i2c1"};
static const char * const i2c2_groups[] = {"i2c2"};
static const char * const i2c3_groups[] = {"i2c3"};
static const char * const nand_groups[] = {"nand", "nand_cs1"};
static const char * const sd_groups[] = {"sd"};
+static const char * const system_bus_groups[] = {"system_bus",
+ "system_bus_cs0",
+ "system_bus_cs1",
+ "system_bus_cs2",
+ "system_bus_cs3"};
static const char * const uart0_groups[] = {"uart0"};
static const char * const uart1_groups[] = {"uart1", "uart1b"};
static const char * const uart2_groups[] = {"uart2"};
@@ -828,14 +890,17 @@ static const char * const xirq_groups[] = {
"xirq12", /* none*/ "xirq14", "xirq15",
};
-static const struct uniphier_pinmux_function ph1_ld4_functions[] = {
+static const struct uniphier_pinmux_function uniphier_ld4_functions[] = {
UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(ether_mii),
+ UNIPHIER_PINMUX_FUNCTION(ether_rmii),
UNIPHIER_PINMUX_FUNCTION(i2c0),
UNIPHIER_PINMUX_FUNCTION(i2c1),
UNIPHIER_PINMUX_FUNCTION(i2c2),
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION(uart0),
UNIPHIER_PINMUX_FUNCTION(uart1),
UNIPHIER_PINMUX_FUNCTION(uart2),
@@ -847,43 +912,36 @@ static const struct uniphier_pinmux_function ph1_ld4_functions[] = {
UNIPHIER_PINMUX_FUNCTION(xirq),
};
-static struct uniphier_pinctrl_socdata ph1_ld4_pindata = {
- .groups = ph1_ld4_groups,
- .groups_count = ARRAY_SIZE(ph1_ld4_groups),
- .functions = ph1_ld4_functions,
- .functions_count = ARRAY_SIZE(ph1_ld4_functions),
- .mux_bits = 8,
- .reg_stride = 4,
- .load_pinctrl = false,
-};
-
-static struct pinctrl_desc ph1_ld4_pinctrl_desc = {
- .name = DRIVER_NAME,
- .pins = ph1_ld4_pins,
- .npins = ARRAY_SIZE(ph1_ld4_pins),
- .owner = THIS_MODULE,
+static struct uniphier_pinctrl_socdata uniphier_ld4_pindata = {
+ .pins = uniphier_ld4_pins,
+ .npins = ARRAY_SIZE(uniphier_ld4_pins),
+ .groups = uniphier_ld4_groups,
+ .groups_count = ARRAY_SIZE(uniphier_ld4_groups),
+ .functions = uniphier_ld4_functions,
+ .functions_count = ARRAY_SIZE(uniphier_ld4_functions),
+ .caps = 0,
};
-static int ph1_ld4_pinctrl_probe(struct platform_device *pdev)
+static int uniphier_ld4_pinctrl_probe(struct platform_device *pdev)
{
- return uniphier_pinctrl_probe(pdev, &ph1_ld4_pinctrl_desc,
- &ph1_ld4_pindata);
+ return uniphier_pinctrl_probe(pdev, &uniphier_ld4_pindata);
}
-static const struct of_device_id ph1_ld4_pinctrl_match[] = {
+static const struct of_device_id uniphier_ld4_pinctrl_match[] = {
+ { .compatible = "socionext,uniphier-ld4-pinctrl" },
{ .compatible = "socionext,ph1-ld4-pinctrl" },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, ph1_ld4_pinctrl_match);
+MODULE_DEVICE_TABLE(of, uniphier_ld4_pinctrl_match);
-static struct platform_driver ph1_ld4_pinctrl_driver = {
- .probe = ph1_ld4_pinctrl_probe,
+static struct platform_driver uniphier_ld4_pinctrl_driver = {
+ .probe = uniphier_ld4_pinctrl_probe,
.driver = {
- .name = DRIVER_NAME,
- .of_match_table = ph1_ld4_pinctrl_match,
+ .name = "uniphier-ld4-pinctrl",
+ .of_match_table = uniphier_ld4_pinctrl_match,
},
};
-module_platform_driver(ph1_ld4_pinctrl_driver);
+module_platform_driver(uniphier_ld4_pinctrl_driver);
MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
MODULE_DESCRIPTION("UniPhier PH1-LD4 pinctrl driver");
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
index 150d33928df2..708e5100cf34 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c
@@ -19,713 +19,711 @@
#include "pinctrl-uniphier.h"
-#define DRIVER_NAME "ph1-ld6b-pinctrl"
-
-static const struct pinctrl_pin_desc ph1_ld6b_pins[] = {
+static const struct pinctrl_pin_desc uniphier_ld6b_pins[] = {
UNIPHIER_PINCTRL_PIN(0, "ED0", UNIPHIER_PIN_IECTRL_NONE,
- 0, UNIPHIER_PIN_DRV_4_8,
+ 0, UNIPHIER_PIN_DRV_1BIT,
0, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(1, "ED1", UNIPHIER_PIN_IECTRL_NONE,
- 1, UNIPHIER_PIN_DRV_4_8,
+ 1, UNIPHIER_PIN_DRV_1BIT,
1, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(2, "ED2", UNIPHIER_PIN_IECTRL_NONE,
- 2, UNIPHIER_PIN_DRV_4_8,
+ 2, UNIPHIER_PIN_DRV_1BIT,
2, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(3, "ED3", UNIPHIER_PIN_IECTRL_NONE,
- 3, UNIPHIER_PIN_DRV_4_8,
+ 3, UNIPHIER_PIN_DRV_1BIT,
3, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(4, "ED4", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_4_8,
+ 4, UNIPHIER_PIN_DRV_1BIT,
4, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(5, "ED5", UNIPHIER_PIN_IECTRL_NONE,
- 5, UNIPHIER_PIN_DRV_4_8,
+ 5, UNIPHIER_PIN_DRV_1BIT,
5, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(6, "ED6", UNIPHIER_PIN_IECTRL_NONE,
- 6, UNIPHIER_PIN_DRV_4_8,
+ 6, UNIPHIER_PIN_DRV_1BIT,
6, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(7, "ED7", UNIPHIER_PIN_IECTRL_NONE,
- 7, UNIPHIER_PIN_DRV_4_8,
+ 7, UNIPHIER_PIN_DRV_1BIT,
7, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(8, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_4_8,
+ 8, UNIPHIER_PIN_DRV_1BIT,
8, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(9, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
- 9, UNIPHIER_PIN_DRV_4_8,
+ 9, UNIPHIER_PIN_DRV_1BIT,
9, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(10, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
- 10, UNIPHIER_PIN_DRV_4_8,
+ 10, UNIPHIER_PIN_DRV_1BIT,
10, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(11, "ES0", UNIPHIER_PIN_IECTRL_NONE,
- 11, UNIPHIER_PIN_DRV_4_8,
+ 11, UNIPHIER_PIN_DRV_1BIT,
11, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(12, "ES1", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_4_8,
+ 12, UNIPHIER_PIN_DRV_1BIT,
12, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(13, "ES2", UNIPHIER_PIN_IECTRL_NONE,
- 13, UNIPHIER_PIN_DRV_4_8,
+ 13, UNIPHIER_PIN_DRV_1BIT,
13, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(14, "XECS1", UNIPHIER_PIN_IECTRL_NONE,
- 14, UNIPHIER_PIN_DRV_4_8,
+ 14, UNIPHIER_PIN_DRV_1BIT,
14, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(15, "PCA00", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
15, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(16, "PCA01", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
16, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(17, "PCA02", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
17, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(18, "PCA03", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
18, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(19, "PCA04", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
19, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(20, "PCA05", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
20, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(21, "PCA06", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
21, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(22, "PCA07", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
22, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(23, "PCA08", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
23, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(24, "PCA09", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
24, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(25, "PCA10", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
25, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(26, "PCA11", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
26, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(27, "PCA12", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
27, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(28, "PCA13", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
28, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(29, "PCA14", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
29, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(30, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
- 30, UNIPHIER_PIN_DRV_4_8,
+ 30, UNIPHIER_PIN_DRV_1BIT,
30, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(31, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
- 31, UNIPHIER_PIN_DRV_4_8,
+ 31, UNIPHIER_PIN_DRV_1BIT,
31, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(32, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
- 32, UNIPHIER_PIN_DRV_4_8,
+ 32, UNIPHIER_PIN_DRV_1BIT,
32, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(33, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
- 33, UNIPHIER_PIN_DRV_4_8,
+ 33, UNIPHIER_PIN_DRV_1BIT,
33, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(34, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
- 34, UNIPHIER_PIN_DRV_4_8,
+ 34, UNIPHIER_PIN_DRV_1BIT,
34, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(35, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
- 35, UNIPHIER_PIN_DRV_4_8,
+ 35, UNIPHIER_PIN_DRV_1BIT,
35, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(36, "NFRYBY0", UNIPHIER_PIN_IECTRL_NONE,
- 36, UNIPHIER_PIN_DRV_4_8,
+ 36, UNIPHIER_PIN_DRV_1BIT,
36, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(37, "XNFCE1", UNIPHIER_PIN_IECTRL_NONE,
- 37, UNIPHIER_PIN_DRV_4_8,
+ 37, UNIPHIER_PIN_DRV_1BIT,
37, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(38, "NFRYBY1", UNIPHIER_PIN_IECTRL_NONE,
- 38, UNIPHIER_PIN_DRV_4_8,
+ 38, UNIPHIER_PIN_DRV_1BIT,
38, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(39, "NFD0", UNIPHIER_PIN_IECTRL_NONE,
- 39, UNIPHIER_PIN_DRV_4_8,
+ 39, UNIPHIER_PIN_DRV_1BIT,
39, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(40, "NFD1", UNIPHIER_PIN_IECTRL_NONE,
- 40, UNIPHIER_PIN_DRV_4_8,
+ 40, UNIPHIER_PIN_DRV_1BIT,
40, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(41, "NFD2", UNIPHIER_PIN_IECTRL_NONE,
- 41, UNIPHIER_PIN_DRV_4_8,
+ 41, UNIPHIER_PIN_DRV_1BIT,
41, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(42, "NFD3", UNIPHIER_PIN_IECTRL_NONE,
- 42, UNIPHIER_PIN_DRV_4_8,
+ 42, UNIPHIER_PIN_DRV_1BIT,
42, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(43, "NFD4", UNIPHIER_PIN_IECTRL_NONE,
- 43, UNIPHIER_PIN_DRV_4_8,
+ 43, UNIPHIER_PIN_DRV_1BIT,
43, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(44, "NFD5", UNIPHIER_PIN_IECTRL_NONE,
- 44, UNIPHIER_PIN_DRV_4_8,
+ 44, UNIPHIER_PIN_DRV_1BIT,
44, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(45, "NFD6", UNIPHIER_PIN_IECTRL_NONE,
- 45, UNIPHIER_PIN_DRV_4_8,
+ 45, UNIPHIER_PIN_DRV_1BIT,
45, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(46, "NFD7", UNIPHIER_PIN_IECTRL_NONE,
- 46, UNIPHIER_PIN_DRV_4_8,
+ 46, UNIPHIER_PIN_DRV_1BIT,
46, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(47, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
- 0, UNIPHIER_PIN_DRV_8_12_16_20,
+ 0, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(48, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_8_12_16_20,
+ 1, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(49, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_8_12_16_20,
+ 2, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(50, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_8_12_16_20,
+ 3, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(51, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
- 16, UNIPHIER_PIN_DRV_8_12_16_20,
+ 4, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(52, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
- 20, UNIPHIER_PIN_DRV_8_12_16_20,
+ 5, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(53, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
53, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(54, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
54, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(55, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
55, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(56, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
56, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(57, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
57, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(58, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
58, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(59, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
59, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(60, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
60, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(61, "USB2OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
61, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(62, "USB3VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
62, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(63, "USB3OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
63, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(64, "HS0BCLKOUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
64, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(65, "HS0SYNCOUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
65, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(66, "HS0VALOUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
66, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(67, "HS0DOUT0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
67, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(68, "HS0DOUT1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
68, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(69, "HS0DOUT2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
69, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(70, "HS0DOUT3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
70, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(71, "HS0DOUT4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
71, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(72, "HS0DOUT5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
72, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(73, "HS0DOUT6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
73, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(74, "HS0DOUT7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
74, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(75, "HS1BCLKIN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
75, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(76, "HS1SYNCIN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
76, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(77, "HS1VALIN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
77, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(78, "HS1DIN0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
78, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(79, "HS1DIN1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
79, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(80, "HS1DIN2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
80, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(81, "HS1DIN3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
81, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(82, "HS1DIN4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
82, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(83, "HS1DIN5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
83, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(84, "HS1DIN6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
84, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(85, "HS1DIN7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
85, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(86, "HS2BCLKIN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
86, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(87, "HS2SYNCIN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
87, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(88, "HS2VALIN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
88, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(89, "HS2DIN0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
89, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(90, "HS2DIN1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
90, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(91, "HS2DIN2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
91, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(92, "HS2DIN3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
92, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(93, "HS2DIN4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
93, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(94, "HS2DIN5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
94, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(95, "HS2DIN6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
95, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(96, "HS2DIN7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
96, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(97, "AO1IEC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
97, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(98, "AO1DACCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
98, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(99, "AO1BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
99, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(100, "AO1LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
100, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(101, "AO1D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
101, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(102, "AO1D1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
102, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(103, "AO1D2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
103, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(104, "AO1D3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
104, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(105, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
105, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(106, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
106, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(107, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
107, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(108, "AO2D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
108, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(109, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
109, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(110, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
110, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(111, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
111, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(112, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
112, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(113, "SBO0", 0,
- 113, UNIPHIER_PIN_DRV_4_8,
+ 113, UNIPHIER_PIN_DRV_1BIT,
113, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(114, "SBI0", 0,
- 114, UNIPHIER_PIN_DRV_4_8,
+ 114, UNIPHIER_PIN_DRV_1BIT,
114, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(115, "TXD1", 0,
- 115, UNIPHIER_PIN_DRV_4_8,
+ 115, UNIPHIER_PIN_DRV_1BIT,
115, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(116, "RXD1", 0,
- 116, UNIPHIER_PIN_DRV_4_8,
+ 116, UNIPHIER_PIN_DRV_1BIT,
116, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(117, "PWSRA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
117, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(118, "XIRQ0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
118, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(119, "XIRQ1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
119, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(120, "XIRQ2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
120, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(121, "XIRQ3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
121, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(122, "XIRQ4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
122, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(123, "XIRQ5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
123, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(124, "XIRQ6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
124, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(125, "XIRQ7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
125, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(126, "XIRQ8", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
126, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(127, "PORT00", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
127, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(128, "PORT01", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
128, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(129, "PORT02", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
129, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(130, "PORT03", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
130, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(131, "PORT04", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
131, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(132, "PORT05", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
132, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(133, "PORT06", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
133, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(134, "PORT07", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
134, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(135, "PORT10", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
135, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(136, "PORT11", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
136, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(137, "PORT12", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
137, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(138, "PORT13", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
138, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(139, "PORT14", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
139, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(140, "PORT15", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
140, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(141, "PORT16", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
141, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(142, "LPST", UNIPHIER_PIN_IECTRL_NONE,
- 142, UNIPHIER_PIN_DRV_4_8,
+ 142, UNIPHIER_PIN_DRV_1BIT,
142, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(143, "MDC", 0,
- 143, UNIPHIER_PIN_DRV_4_8,
+ 143, UNIPHIER_PIN_DRV_1BIT,
143, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(144, "MDIO", 0,
- 144, UNIPHIER_PIN_DRV_4_8,
+ 144, UNIPHIER_PIN_DRV_1BIT,
144, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(145, "MDIO_INTL", 0,
- 145, UNIPHIER_PIN_DRV_4_8,
+ 145, UNIPHIER_PIN_DRV_1BIT,
145, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(146, "PHYRSTL", 0,
- 146, UNIPHIER_PIN_DRV_4_8,
+ 146, UNIPHIER_PIN_DRV_1BIT,
146, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(147, "RGMII_RXCLK", 0,
- 147, UNIPHIER_PIN_DRV_4_8,
+ 147, UNIPHIER_PIN_DRV_1BIT,
147, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(148, "RGMII_RXD0", 0,
- 148, UNIPHIER_PIN_DRV_4_8,
+ 148, UNIPHIER_PIN_DRV_1BIT,
148, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(149, "RGMII_RXD1", 0,
- 149, UNIPHIER_PIN_DRV_4_8,
+ 149, UNIPHIER_PIN_DRV_1BIT,
149, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(150, "RGMII_RXD2", 0,
- 150, UNIPHIER_PIN_DRV_4_8,
+ 150, UNIPHIER_PIN_DRV_1BIT,
150, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(151, "RGMII_RXD3", 0,
- 151, UNIPHIER_PIN_DRV_4_8,
+ 151, UNIPHIER_PIN_DRV_1BIT,
151, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(152, "RGMII_RXCTL", 0,
- 152, UNIPHIER_PIN_DRV_4_8,
+ 152, UNIPHIER_PIN_DRV_1BIT,
152, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(153, "RGMII_TXCLK", 0,
- 153, UNIPHIER_PIN_DRV_4_8,
+ 153, UNIPHIER_PIN_DRV_1BIT,
153, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(154, "RGMII_TXD0", 0,
- 154, UNIPHIER_PIN_DRV_4_8,
+ 154, UNIPHIER_PIN_DRV_1BIT,
154, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(155, "RGMII_TXD1", 0,
- 155, UNIPHIER_PIN_DRV_4_8,
+ 155, UNIPHIER_PIN_DRV_1BIT,
155, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(156, "RGMII_TXD2", 0,
- 156, UNIPHIER_PIN_DRV_4_8,
+ 156, UNIPHIER_PIN_DRV_1BIT,
156, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(157, "RGMII_TXD3", 0,
- 157, UNIPHIER_PIN_DRV_4_8,
+ 157, UNIPHIER_PIN_DRV_1BIT,
157, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(158, "RGMII_TXCTL", 0,
- 158, UNIPHIER_PIN_DRV_4_8,
+ 158, UNIPHIER_PIN_DRV_1BIT,
158, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(159, "A_D_PCD00OUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
159, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(160, "A_D_PCD01OUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
160, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(161, "A_D_PCD02OUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
161, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(162, "A_D_PCD03OUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
162, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(163, "A_D_PCD04OUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
163, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(164, "A_D_PCD05OUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
164, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(165, "A_D_PCD06OUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
165, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(166, "A_D_PCD07OUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
166, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(167, "A_D_PCD00IN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
167, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(168, "A_D_PCD01IN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
168, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(169, "A_D_PCD02IN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
169, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(170, "A_D_PCD03IN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
170, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(171, "A_D_PCD04IN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
171, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(172, "A_D_PCD05IN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
172, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(173, "A_D_PCD06IN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
173, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(174, "A_D_PCD07IN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
174, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(175, "A_D_PCDNOE", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
175, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(176, "A_D_PC0READY", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
176, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(177, "A_D_PC0CD1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
177, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(178, "A_D_PC0CD2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
178, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(179, "A_D_PC0WAIT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
179, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(180, "A_D_PC0RESET", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
180, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(181, "A_D_PC0CE1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
181, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(182, "A_D_PC0WE", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
182, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(183, "A_D_PC0OE", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
183, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(184, "A_D_PC0IOWR", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
184, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(185, "A_D_PC0IORD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
185, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(186, "A_D_PC0NOE", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
186, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(187, "A_D_HS0BCLKIN", 0,
- 187, UNIPHIER_PIN_DRV_4_8,
+ 187, UNIPHIER_PIN_DRV_1BIT,
187, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(188, "A_D_HS0SYNCIN", 0,
- 188, UNIPHIER_PIN_DRV_4_8,
+ 188, UNIPHIER_PIN_DRV_1BIT,
188, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(189, "A_D_HS0VALIN", 0,
- 189, UNIPHIER_PIN_DRV_4_8,
+ 189, UNIPHIER_PIN_DRV_1BIT,
189, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(190, "A_D_HS0DIN0", 0,
- 190, UNIPHIER_PIN_DRV_4_8,
+ 190, UNIPHIER_PIN_DRV_1BIT,
190, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(191, "A_D_HS0DIN1", 0,
- 191, UNIPHIER_PIN_DRV_4_8,
+ 191, UNIPHIER_PIN_DRV_1BIT,
191, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(192, "A_D_HS0DIN2", 0,
- 192, UNIPHIER_PIN_DRV_4_8,
+ 192, UNIPHIER_PIN_DRV_1BIT,
192, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(193, "A_D_HS0DIN3", 0,
- 193, UNIPHIER_PIN_DRV_4_8,
+ 193, UNIPHIER_PIN_DRV_1BIT,
193, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(194, "A_D_HS0DIN4", 0,
- 194, UNIPHIER_PIN_DRV_4_8,
+ 194, UNIPHIER_PIN_DRV_1BIT,
194, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(195, "A_D_HS0DIN5", 0,
- 195, UNIPHIER_PIN_DRV_4_8,
+ 195, UNIPHIER_PIN_DRV_1BIT,
195, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(196, "A_D_HS0DIN6", 0,
- 196, UNIPHIER_PIN_DRV_4_8,
+ 196, UNIPHIER_PIN_DRV_1BIT,
196, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(197, "A_D_HS0DIN7", 0,
- 197, UNIPHIER_PIN_DRV_4_8,
+ 197, UNIPHIER_PIN_DRV_1BIT,
197, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(198, "A_D_AO1ARC", 0,
- 198, UNIPHIER_PIN_DRV_4_8,
+ 198, UNIPHIER_PIN_DRV_1BIT,
198, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(199, "A_D_SPIXRST", UNIPHIER_PIN_IECTRL_NONE,
- 199, UNIPHIER_PIN_DRV_4_8,
+ 199, UNIPHIER_PIN_DRV_1BIT,
199, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(200, "A_D_SPISCLK0", UNIPHIER_PIN_IECTRL_NONE,
- 200, UNIPHIER_PIN_DRV_4_8,
+ 200, UNIPHIER_PIN_DRV_1BIT,
200, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(201, "A_D_SPITXD0", UNIPHIER_PIN_IECTRL_NONE,
- 201, UNIPHIER_PIN_DRV_4_8,
+ 201, UNIPHIER_PIN_DRV_1BIT,
201, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(202, "A_D_SPIRXD0", UNIPHIER_PIN_IECTRL_NONE,
- 202, UNIPHIER_PIN_DRV_4_8,
+ 202, UNIPHIER_PIN_DRV_1BIT,
202, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(203, "A_D_DMDCLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
203, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(204, "A_D_DMDPSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
204, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(205, "A_D_DMDVAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
205, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(206, "A_D_DMDDATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
206, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(207, "A_D_HDMIRXXIRQ", 0,
- 207, UNIPHIER_PIN_DRV_4_8,
+ 207, UNIPHIER_PIN_DRV_1BIT,
207, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(208, "A_D_VBIXIRQ", 0,
- 208, UNIPHIER_PIN_DRV_4_8,
+ 208, UNIPHIER_PIN_DRV_1BIT,
208, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(209, "A_D_HDMITXXIRQ", 0,
- 209, UNIPHIER_PIN_DRV_4_8,
+ 209, UNIPHIER_PIN_DRV_1BIT,
209, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(210, "A_D_DMDIRQ", UNIPHIER_PIN_IECTRL_NONE,
- 210, UNIPHIER_PIN_DRV_4_8,
+ 210, UNIPHIER_PIN_DRV_1BIT,
210, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(211, "A_D_SPICIRQ", UNIPHIER_PIN_IECTRL_NONE,
- 211, UNIPHIER_PIN_DRV_4_8,
+ 211, UNIPHIER_PIN_DRV_1BIT,
211, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(212, "A_D_SPIBIRQ", UNIPHIER_PIN_IECTRL_NONE,
- 212, UNIPHIER_PIN_DRV_4_8,
+ 212, UNIPHIER_PIN_DRV_1BIT,
212, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(213, "A_D_BESDAOUT", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
213, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(214, "A_D_BESDAIN", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
214, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(215, "A_D_BESCLOUT", UNIPHIER_PIN_IECTRL_NONE,
- 215, UNIPHIER_PIN_DRV_4_8,
+ 215, UNIPHIER_PIN_DRV_1BIT,
215, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(216, "A_D_VDACCLKOUT", 0,
- 216, UNIPHIER_PIN_DRV_4_8,
+ 216, UNIPHIER_PIN_DRV_1BIT,
216, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(217, "A_D_VDACDOUT5", 0,
- 217, UNIPHIER_PIN_DRV_4_8,
+ 217, UNIPHIER_PIN_DRV_1BIT,
217, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(218, "A_D_VDACDOUT6", 0,
- 218, UNIPHIER_PIN_DRV_4_8,
+ 218, UNIPHIER_PIN_DRV_1BIT,
218, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(219, "A_D_VDACDOUT7", 0,
- 219, UNIPHIER_PIN_DRV_4_8,
+ 219, UNIPHIER_PIN_DRV_1BIT,
219, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(220, "A_D_VDACDOUT8", 0,
- 220, UNIPHIER_PIN_DRV_4_8,
+ 220, UNIPHIER_PIN_DRV_1BIT,
220, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(221, "A_D_VDACDOUT9", 0,
- 221, UNIPHIER_PIN_DRV_4_8,
+ 221, UNIPHIER_PIN_DRV_1BIT,
221, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(222, "A_D_SIFBCKIN", 0,
- 222, UNIPHIER_PIN_DRV_4_8,
+ 222, UNIPHIER_PIN_DRV_1BIT,
222, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(223, "A_D_SIFLRCKIN", 0,
- 223, UNIPHIER_PIN_DRV_4_8,
+ 223, UNIPHIER_PIN_DRV_1BIT,
223, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(224, "A_D_SIFDIN", 0,
- 224, UNIPHIER_PIN_DRV_4_8,
+ 224, UNIPHIER_PIN_DRV_1BIT,
224, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(225, "A_D_LIBCKOUT", 0,
- 225, UNIPHIER_PIN_DRV_4_8,
+ 225, UNIPHIER_PIN_DRV_1BIT,
225, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(226, "A_D_LILRCKOUT", 0,
- 226, UNIPHIER_PIN_DRV_4_8,
+ 226, UNIPHIER_PIN_DRV_1BIT,
226, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(227, "A_D_LIDIN", 0,
- 227, UNIPHIER_PIN_DRV_4_8,
+ 227, UNIPHIER_PIN_DRV_1BIT,
227, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(228, "A_D_LODOUT", 0,
- 228, UNIPHIER_PIN_DRV_4_8,
+ 228, UNIPHIER_PIN_DRV_1BIT,
228, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(229, "A_D_HPDOUT", 0,
- 229, UNIPHIER_PIN_DRV_4_8,
+ 229, UNIPHIER_PIN_DRV_1BIT,
229, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(230, "A_D_MCLK", 0,
- 230, UNIPHIER_PIN_DRV_4_8,
+ 230, UNIPHIER_PIN_DRV_1BIT,
230, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(231, "A_D_A2PLLREFOUT", 0,
- 231, UNIPHIER_PIN_DRV_4_8,
+ 231, UNIPHIER_PIN_DRV_1BIT,
231, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(232, "A_D_HDMI3DSDAOUT", 0,
- 232, UNIPHIER_PIN_DRV_4_8,
+ 232, UNIPHIER_PIN_DRV_1BIT,
232, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(233, "A_D_HDMI3DSDAIN", 0,
- 233, UNIPHIER_PIN_DRV_4_8,
+ 233, UNIPHIER_PIN_DRV_1BIT,
233, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(234, "A_D_HDMI3DSCLIN", 0,
- 234, UNIPHIER_PIN_DRV_4_8,
+ 234, UNIPHIER_PIN_DRV_1BIT,
234, UNIPHIER_PIN_PULL_DOWN),
};
@@ -737,52 +735,73 @@ static const unsigned adinter_pins[] = {
215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
229, 230, 231, 232, 233, 234,
};
-static const unsigned adinter_muxvals[] = {
+static const int adinter_muxvals[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0,
};
static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
-static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const int emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
-static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned ether_rgmii_pins[] = {143, 144, 145, 146, 147, 148, 149,
+ 150, 151, 152, 153, 154, 155, 156,
+ 157, 158};
+static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0};
+static const unsigned ether_rmii_pins[] = {143, 144, 145, 146, 147, 148, 149,
+ 150, 152, 154, 155, 158};
+static const int ether_rmii_muxvals[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1};
static const unsigned i2c0_pins[] = {109, 110};
-static const unsigned i2c0_muxvals[] = {0, 0};
+static const int i2c0_muxvals[] = {0, 0};
static const unsigned i2c1_pins[] = {111, 112};
-static const unsigned i2c1_muxvals[] = {0, 0};
+static const int i2c1_muxvals[] = {0, 0};
static const unsigned i2c2_pins[] = {115, 116};
-static const unsigned i2c2_muxvals[] = {1, 1};
+static const int i2c2_muxvals[] = {1, 1};
static const unsigned i2c3_pins[] = {118, 119};
-static const unsigned i2c3_muxvals[] = {1, 1};
+static const int i2c3_muxvals[] = {1, 1};
static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
42, 43, 44, 45, 46};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned nand_cs1_pins[] = {37, 38};
-static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned system_bus_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
+ 11, 12, 13};
+static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0};
+static const unsigned system_bus_cs1_pins[] = {14};
+static const int system_bus_cs1_muxvals[] = {0};
+static const unsigned system_bus_cs2_pins[] = {37};
+static const int system_bus_cs2_muxvals[] = {6};
+static const unsigned system_bus_cs3_pins[] = {38};
+static const int system_bus_cs3_muxvals[] = {6};
+static const unsigned system_bus_cs4_pins[] = {115};
+static const int system_bus_cs4_muxvals[] = {6};
+static const unsigned system_bus_cs5_pins[] = {55};
+static const int system_bus_cs5_muxvals[] = {6};
static const unsigned uart0_pins[] = {135, 136};
-static const unsigned uart0_muxvals[] = {3, 3};
+static const int uart0_muxvals[] = {3, 3};
static const unsigned uart0b_pins[] = {11, 12};
-static const unsigned uart0b_muxvals[] = {2, 2};
+static const int uart0b_muxvals[] = {2, 2};
static const unsigned uart1_pins[] = {115, 116};
-static const unsigned uart1_muxvals[] = {0, 0};
+static const int uart1_muxvals[] = {0, 0};
static const unsigned uart1b_pins[] = {113, 114};
-static const unsigned uart1b_muxvals[] = {1, 1};
+static const int uart1b_muxvals[] = {1, 1};
static const unsigned uart2_pins[] = {113, 114};
-static const unsigned uart2_muxvals[] = {2, 2};
+static const int uart2_muxvals[] = {2, 2};
static const unsigned uart2b_pins[] = {86, 87};
-static const unsigned uart2b_muxvals[] = {1, 1};
+static const int uart2b_muxvals[] = {1, 1};
static const unsigned usb0_pins[] = {56, 57};
-static const unsigned usb0_muxvals[] = {0, 0};
+static const int usb0_muxvals[] = {0, 0};
static const unsigned usb1_pins[] = {58, 59};
-static const unsigned usb1_muxvals[] = {0, 0};
+static const int usb1_muxvals[] = {0, 0};
static const unsigned usb2_pins[] = {60, 61};
-static const unsigned usb2_muxvals[] = {0, 0};
+static const int usb2_muxvals[] = {0, 0};
static const unsigned usb3_pins[] = {62, 63};
-static const unsigned usb3_muxvals[] = {0, 0};
+static const int usb3_muxvals[] = {0, 0};
static const unsigned port_range0_pins[] = {
127, 128, 129, 130, 131, 132, 133, 134, /* PORT0x */
135, 136, 137, 138, 139, 140, 141, 142, /* PORT1x */
@@ -796,7 +815,7 @@ static const unsigned port_range0_pins[] = {
61, 62, 63, 64, 65, 66, 67, 68, /* PORT9x */
69, 70, 71, 76, 77, 78, 79, 80, /* PORT10x */
};
-static const unsigned port_range0_muxvals[] = {
+static const int port_range0_muxvals[] = {
15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
@@ -828,7 +847,7 @@ static const unsigned port_range1_pins[] = {
218, 219, 220, 221, 223, 224, 225, 226, /* PORT27x */
227, 228, 229, 230, 231, 232, 233, 234, /* PORT28x */
};
-static const unsigned port_range1_muxvals[] = {
+static const int port_range1_muxvals[] = {
15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
@@ -852,16 +871,18 @@ static const unsigned xirq_pins[] = {
126, 72, 73, 92, 177, 93, 94, 176, /* XIRQ8-15 */
74, 91, 27, 28, 29, 75, 20, 26, /* XIRQ16-23 */
};
-static const unsigned xirq_muxvals[] = {
+static const int xirq_muxvals[] = {
14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */
14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */
14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */
};
-static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = {
+static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = {
UNIPHIER_PINCTRL_GROUP(adinter),
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(ether_rgmii),
+ UNIPHIER_PINCTRL_GROUP(ether_rmii),
UNIPHIER_PINCTRL_GROUP(i2c0),
UNIPHIER_PINCTRL_GROUP(i2c1),
UNIPHIER_PINCTRL_GROUP(i2c2),
@@ -869,6 +890,12 @@ static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0b),
UNIPHIER_PINCTRL_GROUP(uart1),
@@ -1134,12 +1161,20 @@ static const struct uniphier_pinctrl_group ph1_ld6b_groups[] = {
static const char * const adinter_groups[] = {"adinter"};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
+static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
+static const char * const ether_rmii_groups[] = {"ether_rmii"};
static const char * const i2c0_groups[] = {"i2c0"};
static const char * const i2c1_groups[] = {"i2c1"};
static const char * const i2c2_groups[] = {"i2c2"};
static const char * const i2c3_groups[] = {"i2c3"};
static const char * const nand_groups[] = {"nand", "nand_cs1"};
static const char * const sd_groups[] = {"sd"};
+static const char * const system_bus_groups[] = {"system_bus",
+ "system_bus_cs1",
+ "system_bus_cs2",
+ "system_bus_cs3",
+ "system_bus_cs4",
+ "system_bus_cs5"};
static const char * const uart0_groups[] = {"uart0", "uart0b"};
static const char * const uart1_groups[] = {"uart1", "uart1b"};
static const char * const uart2_groups[] = {"uart2", "uart2b"};
@@ -1215,15 +1250,18 @@ static const char * const xirq_groups[] = {
"xirq20", "xirq21", "xirq22", "xirq23",
};
-static const struct uniphier_pinmux_function ph1_ld6b_functions[] = {
+static const struct uniphier_pinmux_function uniphier_ld6b_functions[] = {
UNIPHIER_PINMUX_FUNCTION(adinter), /* Achip-Dchip interconnect */
UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
+ UNIPHIER_PINMUX_FUNCTION(ether_rmii),
UNIPHIER_PINMUX_FUNCTION(i2c0),
UNIPHIER_PINMUX_FUNCTION(i2c1),
UNIPHIER_PINMUX_FUNCTION(i2c2),
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION(uart0),
UNIPHIER_PINMUX_FUNCTION(uart1),
UNIPHIER_PINMUX_FUNCTION(uart2),
@@ -1235,43 +1273,36 @@ static const struct uniphier_pinmux_function ph1_ld6b_functions[] = {
UNIPHIER_PINMUX_FUNCTION(xirq),
};
-static struct uniphier_pinctrl_socdata ph1_ld6b_pindata = {
- .groups = ph1_ld6b_groups,
- .groups_count = ARRAY_SIZE(ph1_ld6b_groups),
- .functions = ph1_ld6b_functions,
- .functions_count = ARRAY_SIZE(ph1_ld6b_functions),
- .mux_bits = 8,
- .reg_stride = 4,
- .load_pinctrl = false,
-};
-
-static struct pinctrl_desc ph1_ld6b_pinctrl_desc = {
- .name = DRIVER_NAME,
- .pins = ph1_ld6b_pins,
- .npins = ARRAY_SIZE(ph1_ld6b_pins),
- .owner = THIS_MODULE,
+static struct uniphier_pinctrl_socdata uniphier_ld6b_pindata = {
+ .pins = uniphier_ld6b_pins,
+ .npins = ARRAY_SIZE(uniphier_ld6b_pins),
+ .groups = uniphier_ld6b_groups,
+ .groups_count = ARRAY_SIZE(uniphier_ld6b_groups),
+ .functions = uniphier_ld6b_functions,
+ .functions_count = ARRAY_SIZE(uniphier_ld6b_functions),
+ .caps = 0,
};
-static int ph1_ld6b_pinctrl_probe(struct platform_device *pdev)
+static int uniphier_ld6b_pinctrl_probe(struct platform_device *pdev)
{
- return uniphier_pinctrl_probe(pdev, &ph1_ld6b_pinctrl_desc,
- &ph1_ld6b_pindata);
+ return uniphier_pinctrl_probe(pdev, &uniphier_ld6b_pindata);
}
-static const struct of_device_id ph1_ld6b_pinctrl_match[] = {
+static const struct of_device_id uniphier_ld6b_pinctrl_match[] = {
+ { .compatible = "socionext,uniphier-ld6b-pinctrl" },
{ .compatible = "socionext,ph1-ld6b-pinctrl" },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, ph1_ld6b_pinctrl_match);
+MODULE_DEVICE_TABLE(of, uniphier_ld6b_pinctrl_match);
-static struct platform_driver ph1_ld6b_pinctrl_driver = {
- .probe = ph1_ld6b_pinctrl_probe,
+static struct platform_driver uniphier_ld6b_pinctrl_driver = {
+ .probe = uniphier_ld6b_pinctrl_probe,
.driver = {
- .name = DRIVER_NAME,
- .of_match_table = ph1_ld6b_pinctrl_match,
+ .name = "uniphier-ld6b-pinctrl",
+ .of_match_table = uniphier_ld6b_pinctrl_match,
},
};
-module_platform_driver(ph1_ld6b_pinctrl_driver);
+module_platform_driver(uniphier_ld6b_pinctrl_driver);
MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
MODULE_DESCRIPTION("UniPhier PH1-LD6b pinctrl driver");
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
index b1f09e68f90e..c306e844f584 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c
@@ -19,1039 +19,1072 @@
#include "pinctrl-uniphier.h"
-#define DRIVER_NAME "ph1-pro4-pinctrl"
-
-static const struct pinctrl_pin_desc ph1_pro4_pins[] = {
+static const struct pinctrl_pin_desc uniphier_pro4_pins[] = {
UNIPHIER_PINCTRL_PIN(0, "CK24O", UNIPHIER_PIN_IECTRL_NONE,
- 0, UNIPHIER_PIN_DRV_4_8,
+ 0, UNIPHIER_PIN_DRV_1BIT,
0, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(1, "VC27A", UNIPHIER_PIN_IECTRL_NONE,
- 1, UNIPHIER_PIN_DRV_4_8,
+ 1, UNIPHIER_PIN_DRV_1BIT,
1, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(2, "CK27AI", UNIPHIER_PIN_IECTRL_NONE,
- 2, UNIPHIER_PIN_DRV_4_8,
+ 2, UNIPHIER_PIN_DRV_1BIT,
2, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(3, "CK27AO", UNIPHIER_PIN_IECTRL_NONE,
- 3, UNIPHIER_PIN_DRV_4_8,
+ 3, UNIPHIER_PIN_DRV_1BIT,
3, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(4, "CKSEL", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_4_8,
+ 4, UNIPHIER_PIN_DRV_1BIT,
4, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(5, "CK27AV", UNIPHIER_PIN_IECTRL_NONE,
- 5, UNIPHIER_PIN_DRV_4_8,
+ 5, UNIPHIER_PIN_DRV_1BIT,
5, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(6, "AEXCKA", UNIPHIER_PIN_IECTRL_NONE,
- 6, UNIPHIER_PIN_DRV_4_8,
+ 6, UNIPHIER_PIN_DRV_1BIT,
6, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(7, "ASEL", UNIPHIER_PIN_IECTRL_NONE,
- 7, UNIPHIER_PIN_DRV_4_8,
+ 7, UNIPHIER_PIN_DRV_1BIT,
7, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(8, "ARCRESET", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_4_8,
+ 8, UNIPHIER_PIN_DRV_1BIT,
8, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(9, "ARCUNLOCK", UNIPHIER_PIN_IECTRL_NONE,
- 9, UNIPHIER_PIN_DRV_4_8,
+ 9, UNIPHIER_PIN_DRV_1BIT,
9, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(10, "XSRST", UNIPHIER_PIN_IECTRL_NONE,
- 10, UNIPHIER_PIN_DRV_4_8,
+ 10, UNIPHIER_PIN_DRV_1BIT,
10, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(11, "XNMIRQ", UNIPHIER_PIN_IECTRL_NONE,
- 11, UNIPHIER_PIN_DRV_4_8,
+ 11, UNIPHIER_PIN_DRV_1BIT,
11, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(12, "XSCIRQ", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_4_8,
+ 12, UNIPHIER_PIN_DRV_1BIT,
12, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(13, "EXTRG", UNIPHIER_PIN_IECTRL_NONE,
- 13, UNIPHIER_PIN_DRV_4_8,
+ 13, UNIPHIER_PIN_DRV_1BIT,
13, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(14, "TRCCLK", UNIPHIER_PIN_IECTRL_NONE,
- 14, UNIPHIER_PIN_DRV_4_8,
+ 14, UNIPHIER_PIN_DRV_1BIT,
14, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(15, "TRCCTL", UNIPHIER_PIN_IECTRL_NONE,
- 15, UNIPHIER_PIN_DRV_4_8,
+ 15, UNIPHIER_PIN_DRV_1BIT,
15, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(16, "TRCD0", UNIPHIER_PIN_IECTRL_NONE,
- 16, UNIPHIER_PIN_DRV_4_8,
+ 16, UNIPHIER_PIN_DRV_1BIT,
16, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(17, "TRCD1", UNIPHIER_PIN_IECTRL_NONE,
- 17, UNIPHIER_PIN_DRV_4_8,
+ 17, UNIPHIER_PIN_DRV_1BIT,
17, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(18, "TRCD2", UNIPHIER_PIN_IECTRL_NONE,
- 18, UNIPHIER_PIN_DRV_4_8,
+ 18, UNIPHIER_PIN_DRV_1BIT,
18, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(19, "TRCD3", UNIPHIER_PIN_IECTRL_NONE,
- 19, UNIPHIER_PIN_DRV_4_8,
+ 19, UNIPHIER_PIN_DRV_1BIT,
19, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(20, "TRCD4", UNIPHIER_PIN_IECTRL_NONE,
- 20, UNIPHIER_PIN_DRV_4_8,
+ 20, UNIPHIER_PIN_DRV_1BIT,
20, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(21, "TRCD5", UNIPHIER_PIN_IECTRL_NONE,
- 21, UNIPHIER_PIN_DRV_4_8,
+ 21, UNIPHIER_PIN_DRV_1BIT,
21, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(22, "TRCD6", UNIPHIER_PIN_IECTRL_NONE,
- 22, UNIPHIER_PIN_DRV_4_8,
+ 22, UNIPHIER_PIN_DRV_1BIT,
22, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(23, "TRCD7", UNIPHIER_PIN_IECTRL_NONE,
- 23, UNIPHIER_PIN_DRV_4_8,
+ 23, UNIPHIER_PIN_DRV_1BIT,
23, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(24, "XECS1", UNIPHIER_PIN_IECTRL_NONE,
- 24, UNIPHIER_PIN_DRV_4_8,
+ 24, UNIPHIER_PIN_DRV_1BIT,
24, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(25, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
- 25, UNIPHIER_PIN_DRV_4_8,
+ 25, UNIPHIER_PIN_DRV_1BIT,
25, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(26, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
- 26, UNIPHIER_PIN_DRV_4_8,
+ 26, UNIPHIER_PIN_DRV_1BIT,
26, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(27, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
- 27, UNIPHIER_PIN_DRV_4_8,
+ 27, UNIPHIER_PIN_DRV_1BIT,
27, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(28, "ES0", UNIPHIER_PIN_IECTRL_NONE,
- 28, UNIPHIER_PIN_DRV_4_8,
+ 28, UNIPHIER_PIN_DRV_1BIT,
28, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(29, "ES1", UNIPHIER_PIN_IECTRL_NONE,
- 29, UNIPHIER_PIN_DRV_4_8,
+ 29, UNIPHIER_PIN_DRV_1BIT,
29, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(30, "ES2", UNIPHIER_PIN_IECTRL_NONE,
- 30, UNIPHIER_PIN_DRV_4_8,
+ 30, UNIPHIER_PIN_DRV_1BIT,
30, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(31, "ED0", UNIPHIER_PIN_IECTRL_NONE,
- 31, UNIPHIER_PIN_DRV_4_8,
+ 31, UNIPHIER_PIN_DRV_1BIT,
31, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(32, "ED1", UNIPHIER_PIN_IECTRL_NONE,
- 32, UNIPHIER_PIN_DRV_4_8,
+ 32, UNIPHIER_PIN_DRV_1BIT,
32, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(33, "ED2", UNIPHIER_PIN_IECTRL_NONE,
- 33, UNIPHIER_PIN_DRV_4_8,
+ 33, UNIPHIER_PIN_DRV_1BIT,
33, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(34, "ED3", UNIPHIER_PIN_IECTRL_NONE,
- 34, UNIPHIER_PIN_DRV_4_8,
+ 34, UNIPHIER_PIN_DRV_1BIT,
34, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(35, "ED4", UNIPHIER_PIN_IECTRL_NONE,
- 35, UNIPHIER_PIN_DRV_4_8,
+ 35, UNIPHIER_PIN_DRV_1BIT,
35, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(36, "ED5", UNIPHIER_PIN_IECTRL_NONE,
- 36, UNIPHIER_PIN_DRV_4_8,
+ 36, UNIPHIER_PIN_DRV_1BIT,
36, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(37, "ED6", UNIPHIER_PIN_IECTRL_NONE,
- 37, UNIPHIER_PIN_DRV_4_8,
+ 37, UNIPHIER_PIN_DRV_1BIT,
37, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(38, "ED7", UNIPHIER_PIN_IECTRL_NONE,
- 38, UNIPHIER_PIN_DRV_4_8,
+ 38, UNIPHIER_PIN_DRV_1BIT,
38, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(39, "BOOTSWAP", UNIPHIER_PIN_IECTRL_NONE,
- 39, UNIPHIER_PIN_DRV_NONE,
+ -1, UNIPHIER_PIN_DRV_NONE,
39, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(40, "NFD0", UNIPHIER_PIN_IECTRL_NONE,
- 2, UNIPHIER_PIN_DRV_8_12_16_20,
+ 2, UNIPHIER_PIN_DRV_2BIT,
40, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(41, "NFD1", UNIPHIER_PIN_IECTRL_NONE,
- 3, UNIPHIER_PIN_DRV_8_12_16_20,
+ 3, UNIPHIER_PIN_DRV_2BIT,
41, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(42, "NFD2", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_8_12_16_20,
+ 4, UNIPHIER_PIN_DRV_2BIT,
42, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(43, "NFD3", UNIPHIER_PIN_IECTRL_NONE,
- 5, UNIPHIER_PIN_DRV_8_12_16_20,
+ 5, UNIPHIER_PIN_DRV_2BIT,
43, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(44, "NFD4", UNIPHIER_PIN_IECTRL_NONE,
- 6, UNIPHIER_PIN_DRV_8_12_16_20,
+ 6, UNIPHIER_PIN_DRV_2BIT,
44, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(45, "NFD5", UNIPHIER_PIN_IECTRL_NONE,
- 7, UNIPHIER_PIN_DRV_8_12_16_20,
+ 7, UNIPHIER_PIN_DRV_2BIT,
45, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(46, "NFD6", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_8_12_16_20,
+ 8, UNIPHIER_PIN_DRV_2BIT,
46, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(47, "NFD7", UNIPHIER_PIN_IECTRL_NONE,
- 9, UNIPHIER_PIN_DRV_8_12_16_20,
+ 9, UNIPHIER_PIN_DRV_2BIT,
47, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(48, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
- 48, UNIPHIER_PIN_DRV_4_8,
+ 48, UNIPHIER_PIN_DRV_1BIT,
48, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(49, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
- 49, UNIPHIER_PIN_DRV_4_8,
+ 49, UNIPHIER_PIN_DRV_1BIT,
49, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(50, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
- 50, UNIPHIER_PIN_DRV_4_8,
+ 50, UNIPHIER_PIN_DRV_1BIT,
50, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(51, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
- 0, UNIPHIER_PIN_DRV_8_12_16_20,
+ 0, UNIPHIER_PIN_DRV_2BIT,
51, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(52, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
- 52, UNIPHIER_PIN_DRV_4_8,
+ 52, UNIPHIER_PIN_DRV_1BIT,
52, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(53, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
- 1, UNIPHIER_PIN_DRV_8_12_16_20,
+ 1, UNIPHIER_PIN_DRV_2BIT,
53, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(54, "NRYBY0", UNIPHIER_PIN_IECTRL_NONE,
- 54, UNIPHIER_PIN_DRV_4_8,
+ 54, UNIPHIER_PIN_DRV_1BIT,
54, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(55, "DMDSCLTST", UNIPHIER_PIN_IECTRL_NONE,
-1, UNIPHIER_PIN_DRV_NONE,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(56, "DMDSDATST", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(57, "AGCI0", 3,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
55, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(58, "DMDSCL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(59, "DMDSDA0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(60, "AGCBS0", 5,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
56, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(61, "DMDSCL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(62, "DMDSDA1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(63, "ANTSHORT", UNIPHIER_PIN_IECTRL_NONE,
- 57, UNIPHIER_PIN_DRV_4_8,
+ 57, UNIPHIER_PIN_DRV_1BIT,
57, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(64, "CH0CLK", UNIPHIER_PIN_IECTRL_NONE,
- 58, UNIPHIER_PIN_DRV_4_8,
+ 58, UNIPHIER_PIN_DRV_1BIT,
58, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(65, "CH0VAL", UNIPHIER_PIN_IECTRL_NONE,
- 59, UNIPHIER_PIN_DRV_4_8,
+ 59, UNIPHIER_PIN_DRV_1BIT,
59, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(66, "CH0PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 60, UNIPHIER_PIN_DRV_4_8,
+ 60, UNIPHIER_PIN_DRV_1BIT,
60, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(67, "CH0DATA", UNIPHIER_PIN_IECTRL_NONE,
- 61, UNIPHIER_PIN_DRV_4_8,
+ 61, UNIPHIER_PIN_DRV_1BIT,
61, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(68, "CH1CLK", UNIPHIER_PIN_IECTRL_NONE,
- 62, UNIPHIER_PIN_DRV_4_8,
+ 62, UNIPHIER_PIN_DRV_1BIT,
62, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(69, "CH1VAL", UNIPHIER_PIN_IECTRL_NONE,
- 63, UNIPHIER_PIN_DRV_4_8,
+ 63, UNIPHIER_PIN_DRV_1BIT,
63, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(70, "CH1PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 64, UNIPHIER_PIN_DRV_4_8,
+ 64, UNIPHIER_PIN_DRV_1BIT,
64, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(71, "CH1DATA", UNIPHIER_PIN_IECTRL_NONE,
- 65, UNIPHIER_PIN_DRV_4_8,
+ 65, UNIPHIER_PIN_DRV_1BIT,
65, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(72, "CH2CLK", UNIPHIER_PIN_IECTRL_NONE,
- 66, UNIPHIER_PIN_DRV_4_8,
+ 66, UNIPHIER_PIN_DRV_1BIT,
66, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(73, "CH2VAL", UNIPHIER_PIN_IECTRL_NONE,
- 67, UNIPHIER_PIN_DRV_4_8,
+ 67, UNIPHIER_PIN_DRV_1BIT,
67, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(74, "CH2PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 68, UNIPHIER_PIN_DRV_4_8,
+ 68, UNIPHIER_PIN_DRV_1BIT,
68, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(75, "CH2DATA", UNIPHIER_PIN_IECTRL_NONE,
- 69, UNIPHIER_PIN_DRV_4_8,
+ 69, UNIPHIER_PIN_DRV_1BIT,
69, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(76, "CH3CLK", UNIPHIER_PIN_IECTRL_NONE,
- 70, UNIPHIER_PIN_DRV_4_8,
+ 70, UNIPHIER_PIN_DRV_1BIT,
70, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(77, "CH3VAL", UNIPHIER_PIN_IECTRL_NONE,
- 71, UNIPHIER_PIN_DRV_4_8,
+ 71, UNIPHIER_PIN_DRV_1BIT,
71, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(78, "CH3PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 72, UNIPHIER_PIN_DRV_4_8,
+ 72, UNIPHIER_PIN_DRV_1BIT,
72, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(79, "CH3DATA", UNIPHIER_PIN_IECTRL_NONE,
- 73, UNIPHIER_PIN_DRV_4_8,
+ 73, UNIPHIER_PIN_DRV_1BIT,
73, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(80, "CH4CLK", UNIPHIER_PIN_IECTRL_NONE,
- 74, UNIPHIER_PIN_DRV_4_8,
+ 74, UNIPHIER_PIN_DRV_1BIT,
74, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(81, "CH4VAL", UNIPHIER_PIN_IECTRL_NONE,
- 75, UNIPHIER_PIN_DRV_4_8,
+ 75, UNIPHIER_PIN_DRV_1BIT,
75, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(82, "CH4PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 76, UNIPHIER_PIN_DRV_4_8,
+ 76, UNIPHIER_PIN_DRV_1BIT,
76, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(83, "CH4DATA", UNIPHIER_PIN_IECTRL_NONE,
- 77, UNIPHIER_PIN_DRV_4_8,
+ 77, UNIPHIER_PIN_DRV_1BIT,
77, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(84, "CH5CLK", UNIPHIER_PIN_IECTRL_NONE,
- 78, UNIPHIER_PIN_DRV_4_8,
+ 78, UNIPHIER_PIN_DRV_1BIT,
78, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(85, "CH5VAL", UNIPHIER_PIN_IECTRL_NONE,
- 79, UNIPHIER_PIN_DRV_4_8,
+ 79, UNIPHIER_PIN_DRV_1BIT,
79, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(86, "CH5PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 80, UNIPHIER_PIN_DRV_4_8,
+ 80, UNIPHIER_PIN_DRV_1BIT,
80, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(87, "CH5DATA", UNIPHIER_PIN_IECTRL_NONE,
- 81, UNIPHIER_PIN_DRV_4_8,
+ 81, UNIPHIER_PIN_DRV_1BIT,
81, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(88, "CH6CLK", UNIPHIER_PIN_IECTRL_NONE,
- 82, UNIPHIER_PIN_DRV_4_8,
+ 82, UNIPHIER_PIN_DRV_1BIT,
82, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(89, "CH6VAL", UNIPHIER_PIN_IECTRL_NONE,
- 83, UNIPHIER_PIN_DRV_4_8,
+ 83, UNIPHIER_PIN_DRV_1BIT,
83, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(90, "CH6PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 84, UNIPHIER_PIN_DRV_4_8,
+ 84, UNIPHIER_PIN_DRV_1BIT,
84, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(91, "CH6DATA", UNIPHIER_PIN_IECTRL_NONE,
- 85, UNIPHIER_PIN_DRV_4_8,
+ 85, UNIPHIER_PIN_DRV_1BIT,
85, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(92, "CKFEO", UNIPHIER_PIN_IECTRL_NONE,
- 86, UNIPHIER_PIN_DRV_4_8,
+ 86, UNIPHIER_PIN_DRV_1BIT,
86, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(93, "XFERST", UNIPHIER_PIN_IECTRL_NONE,
- 87, UNIPHIER_PIN_DRV_4_8,
+ 87, UNIPHIER_PIN_DRV_1BIT,
87, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(94, "P_FE_ON", UNIPHIER_PIN_IECTRL_NONE,
- 88, UNIPHIER_PIN_DRV_4_8,
+ 88, UNIPHIER_PIN_DRV_1BIT,
88, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(95, "P_TU0_ON", UNIPHIER_PIN_IECTRL_NONE,
- 89, UNIPHIER_PIN_DRV_4_8,
+ 89, UNIPHIER_PIN_DRV_1BIT,
89, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(96, "XFEIRQ0", UNIPHIER_PIN_IECTRL_NONE,
- 90, UNIPHIER_PIN_DRV_4_8,
+ 90, UNIPHIER_PIN_DRV_1BIT,
90, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(97, "XFEIRQ1", UNIPHIER_PIN_IECTRL_NONE,
- 91, UNIPHIER_PIN_DRV_4_8,
+ 91, UNIPHIER_PIN_DRV_1BIT,
91, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(98, "XFEIRQ2", UNIPHIER_PIN_IECTRL_NONE,
- 92, UNIPHIER_PIN_DRV_4_8,
+ 92, UNIPHIER_PIN_DRV_1BIT,
92, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(99, "XFEIRQ3", UNIPHIER_PIN_IECTRL_NONE,
- 93, UNIPHIER_PIN_DRV_4_8,
+ 93, UNIPHIER_PIN_DRV_1BIT,
93, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(100, "XFEIRQ4", UNIPHIER_PIN_IECTRL_NONE,
- 94, UNIPHIER_PIN_DRV_4_8,
+ 94, UNIPHIER_PIN_DRV_1BIT,
94, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(101, "XFEIRQ5", UNIPHIER_PIN_IECTRL_NONE,
- 95, UNIPHIER_PIN_DRV_4_8,
+ 95, UNIPHIER_PIN_DRV_1BIT,
95, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(102, "XFEIRQ6", UNIPHIER_PIN_IECTRL_NONE,
- 96, UNIPHIER_PIN_DRV_4_8,
+ 96, UNIPHIER_PIN_DRV_1BIT,
96, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(103, "SMTCLK0", UNIPHIER_PIN_IECTRL_NONE,
- 97, UNIPHIER_PIN_DRV_4_8,
+ 97, UNIPHIER_PIN_DRV_1BIT,
97, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(104, "SMTRST0", UNIPHIER_PIN_IECTRL_NONE,
- 98, UNIPHIER_PIN_DRV_4_8,
+ 98, UNIPHIER_PIN_DRV_1BIT,
98, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(105, "SMTCMD0", UNIPHIER_PIN_IECTRL_NONE,
- 99, UNIPHIER_PIN_DRV_4_8,
+ 99, UNIPHIER_PIN_DRV_1BIT,
99, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(106, "SMTD0", UNIPHIER_PIN_IECTRL_NONE,
- 100, UNIPHIER_PIN_DRV_4_8,
+ 100, UNIPHIER_PIN_DRV_1BIT,
100, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(107, "SMTSEL0", UNIPHIER_PIN_IECTRL_NONE,
- 101, UNIPHIER_PIN_DRV_4_8,
+ 101, UNIPHIER_PIN_DRV_1BIT,
101, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(108, "SMTDET0", UNIPHIER_PIN_IECTRL_NONE,
- 102, UNIPHIER_PIN_DRV_4_8,
+ 102, UNIPHIER_PIN_DRV_1BIT,
102, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(109, "SMTCLK1", UNIPHIER_PIN_IECTRL_NONE,
- 103, UNIPHIER_PIN_DRV_4_8,
+ 103, UNIPHIER_PIN_DRV_1BIT,
103, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(110, "SMTRST1", UNIPHIER_PIN_IECTRL_NONE,
- 104, UNIPHIER_PIN_DRV_4_8,
+ 104, UNIPHIER_PIN_DRV_1BIT,
104, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(111, "SMTCMD1", UNIPHIER_PIN_IECTRL_NONE,
- 105, UNIPHIER_PIN_DRV_4_8,
+ 105, UNIPHIER_PIN_DRV_1BIT,
105, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(112, "SMTD1", UNIPHIER_PIN_IECTRL_NONE,
- 106, UNIPHIER_PIN_DRV_4_8,
+ 106, UNIPHIER_PIN_DRV_1BIT,
106, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(113, "SMTSEL1", UNIPHIER_PIN_IECTRL_NONE,
- 107, UNIPHIER_PIN_DRV_4_8,
+ 107, UNIPHIER_PIN_DRV_1BIT,
107, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(114, "SMTDET1", UNIPHIER_PIN_IECTRL_NONE,
- 108, UNIPHIER_PIN_DRV_4_8,
+ 108, UNIPHIER_PIN_DRV_1BIT,
108, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(115, "XINTM", UNIPHIER_PIN_IECTRL_NONE,
- 109, UNIPHIER_PIN_DRV_4_8,
+ 109, UNIPHIER_PIN_DRV_1BIT,
109, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(116, "SCLKM", UNIPHIER_PIN_IECTRL_NONE,
- 110, UNIPHIER_PIN_DRV_4_8,
+ 110, UNIPHIER_PIN_DRV_1BIT,
110, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(117, "SBMTP", UNIPHIER_PIN_IECTRL_NONE,
- 111, UNIPHIER_PIN_DRV_4_8,
+ 111, UNIPHIER_PIN_DRV_1BIT,
111, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(118, "SBPTM", UNIPHIER_PIN_IECTRL_NONE,
- 112, UNIPHIER_PIN_DRV_4_8,
+ 112, UNIPHIER_PIN_DRV_1BIT,
112, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(119, "XMPREQ", UNIPHIER_PIN_IECTRL_NONE,
- 113, UNIPHIER_PIN_DRV_4_8,
+ 113, UNIPHIER_PIN_DRV_1BIT,
113, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(120, "XINTP", UNIPHIER_PIN_IECTRL_NONE,
- 114, UNIPHIER_PIN_DRV_4_8,
+ 114, UNIPHIER_PIN_DRV_1BIT,
114, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(121, "LPST", UNIPHIER_PIN_IECTRL_NONE,
- 115, UNIPHIER_PIN_DRV_4_8,
+ 115, UNIPHIER_PIN_DRV_1BIT,
115, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(122, "SDBOOT", UNIPHIER_PIN_IECTRL_NONE,
- 116, UNIPHIER_PIN_DRV_4_8,
+ 116, UNIPHIER_PIN_DRV_1BIT,
116, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(123, "BFAIL", UNIPHIER_PIN_IECTRL_NONE,
- 117, UNIPHIER_PIN_DRV_4_8,
+ 117, UNIPHIER_PIN_DRV_1BIT,
117, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(124, "XFWE", UNIPHIER_PIN_IECTRL_NONE,
- 118, UNIPHIER_PIN_DRV_4_8,
+ 118, UNIPHIER_PIN_DRV_1BIT,
118, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(125, "RF_COM_RDY", UNIPHIER_PIN_IECTRL_NONE,
- 119, UNIPHIER_PIN_DRV_4_8,
+ 119, UNIPHIER_PIN_DRV_1BIT,
119, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(126, "XDIAG0", UNIPHIER_PIN_IECTRL_NONE,
- 120, UNIPHIER_PIN_DRV_4_8,
+ 120, UNIPHIER_PIN_DRV_1BIT,
120, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(127, "RXD0", UNIPHIER_PIN_IECTRL_NONE,
- 121, UNIPHIER_PIN_DRV_4_8,
+ 121, UNIPHIER_PIN_DRV_1BIT,
121, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(128, "TXD0", UNIPHIER_PIN_IECTRL_NONE,
- 122, UNIPHIER_PIN_DRV_4_8,
+ 122, UNIPHIER_PIN_DRV_1BIT,
122, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(129, "RXD1", UNIPHIER_PIN_IECTRL_NONE,
- 123, UNIPHIER_PIN_DRV_4_8,
+ 123, UNIPHIER_PIN_DRV_1BIT,
123, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(130, "TXD1", UNIPHIER_PIN_IECTRL_NONE,
- 124, UNIPHIER_PIN_DRV_4_8,
+ 124, UNIPHIER_PIN_DRV_1BIT,
124, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(131, "RXD2", UNIPHIER_PIN_IECTRL_NONE,
- 125, UNIPHIER_PIN_DRV_4_8,
+ 125, UNIPHIER_PIN_DRV_1BIT,
125, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(132, "TXD2", UNIPHIER_PIN_IECTRL_NONE,
- 126, UNIPHIER_PIN_DRV_4_8,
+ 126, UNIPHIER_PIN_DRV_1BIT,
126, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(133, "SS0CS", UNIPHIER_PIN_IECTRL_NONE,
- 127, UNIPHIER_PIN_DRV_4_8,
+ 127, UNIPHIER_PIN_DRV_1BIT,
127, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(134, "SS0CLK", UNIPHIER_PIN_IECTRL_NONE,
- 128, UNIPHIER_PIN_DRV_4_8,
+ 128, UNIPHIER_PIN_DRV_1BIT,
128, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(135, "SS0DO", UNIPHIER_PIN_IECTRL_NONE,
- 129, UNIPHIER_PIN_DRV_4_8,
+ 129, UNIPHIER_PIN_DRV_1BIT,
129, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(136, "SS0DI", UNIPHIER_PIN_IECTRL_NONE,
- 130, UNIPHIER_PIN_DRV_4_8,
+ 130, UNIPHIER_PIN_DRV_1BIT,
130, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(137, "MS0CS0", UNIPHIER_PIN_IECTRL_NONE,
- 131, UNIPHIER_PIN_DRV_4_8,
+ 131, UNIPHIER_PIN_DRV_1BIT,
131, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(138, "MS0CLK", UNIPHIER_PIN_IECTRL_NONE,
- 132, UNIPHIER_PIN_DRV_4_8,
+ 132, UNIPHIER_PIN_DRV_1BIT,
132, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(139, "MS0DI", UNIPHIER_PIN_IECTRL_NONE,
- 133, UNIPHIER_PIN_DRV_4_8,
+ 133, UNIPHIER_PIN_DRV_1BIT,
133, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(140, "MS0DO", UNIPHIER_PIN_IECTRL_NONE,
- 134, UNIPHIER_PIN_DRV_4_8,
+ 134, UNIPHIER_PIN_DRV_1BIT,
134, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(141, "XMDMRST", UNIPHIER_PIN_IECTRL_NONE,
- 135, UNIPHIER_PIN_DRV_4_8,
+ 135, UNIPHIER_PIN_DRV_1BIT,
135, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(142, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(143, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(144, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(145, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(146, "SCL2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(147, "SDA2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(148, "SCL3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(149, "SDA3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(150, "SD0DAT0", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_8_12_16_20,
+ 12, UNIPHIER_PIN_DRV_2BIT,
136, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(151, "SD0DAT1", UNIPHIER_PIN_IECTRL_NONE,
- 13, UNIPHIER_PIN_DRV_8_12_16_20,
+ 13, UNIPHIER_PIN_DRV_2BIT,
137, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(152, "SD0DAT2", UNIPHIER_PIN_IECTRL_NONE,
- 14, UNIPHIER_PIN_DRV_8_12_16_20,
+ 14, UNIPHIER_PIN_DRV_2BIT,
138, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(153, "SD0DAT3", UNIPHIER_PIN_IECTRL_NONE,
- 15, UNIPHIER_PIN_DRV_8_12_16_20,
+ 15, UNIPHIER_PIN_DRV_2BIT,
139, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(154, "SD0CMD", UNIPHIER_PIN_IECTRL_NONE,
- 11, UNIPHIER_PIN_DRV_8_12_16_20,
+ 11, UNIPHIER_PIN_DRV_2BIT,
141, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(155, "SD0CLK", UNIPHIER_PIN_IECTRL_NONE,
- 10, UNIPHIER_PIN_DRV_8_12_16_20,
+ 10, UNIPHIER_PIN_DRV_2BIT,
140, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(156, "SD0CD", UNIPHIER_PIN_IECTRL_NONE,
- 142, UNIPHIER_PIN_DRV_4_8,
+ 142, UNIPHIER_PIN_DRV_1BIT,
142, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(157, "SD0WP", UNIPHIER_PIN_IECTRL_NONE,
- 143, UNIPHIER_PIN_DRV_4_8,
+ 143, UNIPHIER_PIN_DRV_1BIT,
143, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(158, "SD0VTCG", UNIPHIER_PIN_IECTRL_NONE,
- 144, UNIPHIER_PIN_DRV_4_8,
+ 144, UNIPHIER_PIN_DRV_1BIT,
144, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(159, "CK25O", UNIPHIER_PIN_IECTRL_NONE,
- 145, UNIPHIER_PIN_DRV_4_8,
+ 145, UNIPHIER_PIN_DRV_1BIT,
145, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(160, "RGMII_TXCLK", 6,
- 146, UNIPHIER_PIN_DRV_4_8,
+ 146, UNIPHIER_PIN_DRV_1BIT,
146, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(161, "RGMII_TXD0", 6,
- 147, UNIPHIER_PIN_DRV_4_8,
+ 147, UNIPHIER_PIN_DRV_1BIT,
147, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(162, "RGMII_TXD1", 6,
- 148, UNIPHIER_PIN_DRV_4_8,
+ 148, UNIPHIER_PIN_DRV_1BIT,
148, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(163, "RGMII_TXD2", 6,
- 149, UNIPHIER_PIN_DRV_4_8,
+ 149, UNIPHIER_PIN_DRV_1BIT,
149, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(164, "RGMII_TXD3", 6,
- 150, UNIPHIER_PIN_DRV_4_8,
+ 150, UNIPHIER_PIN_DRV_1BIT,
150, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(165, "RGMII_TXCTL", 6,
- 151, UNIPHIER_PIN_DRV_4_8,
+ 151, UNIPHIER_PIN_DRV_1BIT,
151, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(166, "MII_TXER", UNIPHIER_PIN_IECTRL_NONE,
- 152, UNIPHIER_PIN_DRV_4_8,
+ 152, UNIPHIER_PIN_DRV_1BIT,
152, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(167, "RGMII_RXCLK", 6,
- 153, UNIPHIER_PIN_DRV_4_8,
+ 153, UNIPHIER_PIN_DRV_1BIT,
153, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(168, "RGMII_RXD0", 6,
- 154, UNIPHIER_PIN_DRV_4_8,
+ 154, UNIPHIER_PIN_DRV_1BIT,
154, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(169, "RGMII_RXD1", 6,
- 155, UNIPHIER_PIN_DRV_4_8,
+ 155, UNIPHIER_PIN_DRV_1BIT,
155, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(170, "RGMII_RXD2", 6,
- 156, UNIPHIER_PIN_DRV_4_8,
+ 156, UNIPHIER_PIN_DRV_1BIT,
156, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(171, "RGMII_RXD3", 6,
- 157, UNIPHIER_PIN_DRV_4_8,
+ 157, UNIPHIER_PIN_DRV_1BIT,
157, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(172, "RGMII_RXCTL", 6,
- 158, UNIPHIER_PIN_DRV_4_8,
+ 158, UNIPHIER_PIN_DRV_1BIT,
158, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(173, "MII_RXER", 6,
- 159, UNIPHIER_PIN_DRV_4_8,
+ 159, UNIPHIER_PIN_DRV_1BIT,
159, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(174, "MII_CRS", 6,
- 160, UNIPHIER_PIN_DRV_4_8,
+ 160, UNIPHIER_PIN_DRV_1BIT,
160, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(175, "MII_COL", 6,
- 161, UNIPHIER_PIN_DRV_4_8,
+ 161, UNIPHIER_PIN_DRV_1BIT,
161, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(176, "MDC", 6,
- 162, UNIPHIER_PIN_DRV_4_8,
+ 162, UNIPHIER_PIN_DRV_1BIT,
162, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(177, "MDIO", 6,
- 163, UNIPHIER_PIN_DRV_4_8,
+ 163, UNIPHIER_PIN_DRV_1BIT,
163, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(178, "MDIO_INTL", 6,
- 164, UNIPHIER_PIN_DRV_4_8,
+ 164, UNIPHIER_PIN_DRV_1BIT,
164, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(179, "XETH_RST", 6,
- 165, UNIPHIER_PIN_DRV_4_8,
+ 165, UNIPHIER_PIN_DRV_1BIT,
165, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(180, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
- 166, UNIPHIER_PIN_DRV_4_8,
+ 166, UNIPHIER_PIN_DRV_1BIT,
166, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(181, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
- 167, UNIPHIER_PIN_DRV_4_8,
+ 167, UNIPHIER_PIN_DRV_1BIT,
167, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(182, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
- 168, UNIPHIER_PIN_DRV_4_8,
+ 168, UNIPHIER_PIN_DRV_1BIT,
168, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(183, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
- 169, UNIPHIER_PIN_DRV_4_8,
+ 169, UNIPHIER_PIN_DRV_1BIT,
169, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(184, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE,
- 170, UNIPHIER_PIN_DRV_4_8,
+ 170, UNIPHIER_PIN_DRV_1BIT,
170, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(185, "USB2OD", UNIPHIER_PIN_IECTRL_NONE,
- 171, UNIPHIER_PIN_DRV_4_8,
+ 171, UNIPHIER_PIN_DRV_1BIT,
171, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(186, "USB2ID", UNIPHIER_PIN_IECTRL_NONE,
- 172, UNIPHIER_PIN_DRV_4_8,
+ 172, UNIPHIER_PIN_DRV_1BIT,
172, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(187, "USB3VBUS", UNIPHIER_PIN_IECTRL_NONE,
- 173, UNIPHIER_PIN_DRV_4_8,
+ 173, UNIPHIER_PIN_DRV_1BIT,
173, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(188, "USB3OD", UNIPHIER_PIN_IECTRL_NONE,
- 174, UNIPHIER_PIN_DRV_4_8,
+ 174, UNIPHIER_PIN_DRV_1BIT,
174, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(189, "LINKCLK", UNIPHIER_PIN_IECTRL_NONE,
- 175, UNIPHIER_PIN_DRV_4_8,
+ 175, UNIPHIER_PIN_DRV_1BIT,
175, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(190, "LINKREQ", UNIPHIER_PIN_IECTRL_NONE,
- 176, UNIPHIER_PIN_DRV_4_8,
+ 176, UNIPHIER_PIN_DRV_1BIT,
176, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(191, "LINKCTL0", UNIPHIER_PIN_IECTRL_NONE,
- 177, UNIPHIER_PIN_DRV_4_8,
+ 177, UNIPHIER_PIN_DRV_1BIT,
177, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(192, "LINKCTL1", UNIPHIER_PIN_IECTRL_NONE,
- 178, UNIPHIER_PIN_DRV_4_8,
+ 178, UNIPHIER_PIN_DRV_1BIT,
178, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(193, "LINKDT0", UNIPHIER_PIN_IECTRL_NONE,
- 179, UNIPHIER_PIN_DRV_4_8,
+ 179, UNIPHIER_PIN_DRV_1BIT,
179, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(194, "LINKDT1", UNIPHIER_PIN_IECTRL_NONE,
- 180, UNIPHIER_PIN_DRV_4_8,
+ 180, UNIPHIER_PIN_DRV_1BIT,
180, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(195, "LINKDT2", UNIPHIER_PIN_IECTRL_NONE,
- 181, UNIPHIER_PIN_DRV_4_8,
+ 181, UNIPHIER_PIN_DRV_1BIT,
181, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(196, "LINKDT3", UNIPHIER_PIN_IECTRL_NONE,
- 182, UNIPHIER_PIN_DRV_4_8,
+ 182, UNIPHIER_PIN_DRV_1BIT,
182, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(197, "LINKDT4", UNIPHIER_PIN_IECTRL_NONE,
- 183, UNIPHIER_PIN_DRV_4_8,
+ 183, UNIPHIER_PIN_DRV_1BIT,
183, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(198, "LINKDT5", UNIPHIER_PIN_IECTRL_NONE,
- 184, UNIPHIER_PIN_DRV_4_8,
+ 184, UNIPHIER_PIN_DRV_1BIT,
184, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(199, "LINKDT6", UNIPHIER_PIN_IECTRL_NONE,
- 185, UNIPHIER_PIN_DRV_4_8,
+ 185, UNIPHIER_PIN_DRV_1BIT,
185, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(200, "LINKDT7", UNIPHIER_PIN_IECTRL_NONE,
- 186, UNIPHIER_PIN_DRV_4_8,
+ 186, UNIPHIER_PIN_DRV_1BIT,
186, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(201, "CKDVO", UNIPHIER_PIN_IECTRL_NONE,
- 187, UNIPHIER_PIN_DRV_4_8,
+ 187, UNIPHIER_PIN_DRV_1BIT,
187, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(202, "PHY_PD", UNIPHIER_PIN_IECTRL_NONE,
- 188, UNIPHIER_PIN_DRV_4_8,
+ 188, UNIPHIER_PIN_DRV_1BIT,
188, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(203, "X1394_RST", UNIPHIER_PIN_IECTRL_NONE,
- 189, UNIPHIER_PIN_DRV_4_8,
+ 189, UNIPHIER_PIN_DRV_1BIT,
189, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(204, "VOUT_MUTE_L", UNIPHIER_PIN_IECTRL_NONE,
- 190, UNIPHIER_PIN_DRV_4_8,
+ 190, UNIPHIER_PIN_DRV_1BIT,
190, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(205, "CLK54O", UNIPHIER_PIN_IECTRL_NONE,
- 191, UNIPHIER_PIN_DRV_4_8,
+ 191, UNIPHIER_PIN_DRV_1BIT,
191, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(206, "CLK54I", UNIPHIER_PIN_IECTRL_NONE,
- 192, UNIPHIER_PIN_DRV_NONE,
+ -1, UNIPHIER_PIN_DRV_NONE,
192, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(207, "YIN0", UNIPHIER_PIN_IECTRL_NONE,
- 193, UNIPHIER_PIN_DRV_4_8,
+ 193, UNIPHIER_PIN_DRV_1BIT,
193, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(208, "YIN1", UNIPHIER_PIN_IECTRL_NONE,
- 194, UNIPHIER_PIN_DRV_4_8,
+ 194, UNIPHIER_PIN_DRV_1BIT,
194, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(209, "YIN2", UNIPHIER_PIN_IECTRL_NONE,
- 195, UNIPHIER_PIN_DRV_4_8,
+ 195, UNIPHIER_PIN_DRV_1BIT,
195, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(210, "YIN3", UNIPHIER_PIN_IECTRL_NONE,
- 196, UNIPHIER_PIN_DRV_4_8,
+ 196, UNIPHIER_PIN_DRV_1BIT,
196, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(211, "YIN4", UNIPHIER_PIN_IECTRL_NONE,
- 197, UNIPHIER_PIN_DRV_4_8,
+ 197, UNIPHIER_PIN_DRV_1BIT,
197, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(212, "YIN5", UNIPHIER_PIN_IECTRL_NONE,
- 198, UNIPHIER_PIN_DRV_4_8,
+ 198, UNIPHIER_PIN_DRV_1BIT,
198, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(213, "CIN0", UNIPHIER_PIN_IECTRL_NONE,
- 199, UNIPHIER_PIN_DRV_4_8,
+ 199, UNIPHIER_PIN_DRV_1BIT,
199, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(214, "CIN1", UNIPHIER_PIN_IECTRL_NONE,
- 200, UNIPHIER_PIN_DRV_4_8,
+ 200, UNIPHIER_PIN_DRV_1BIT,
200, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(215, "CIN2", UNIPHIER_PIN_IECTRL_NONE,
- 201, UNIPHIER_PIN_DRV_4_8,
+ 201, UNIPHIER_PIN_DRV_1BIT,
201, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(216, "CIN3", UNIPHIER_PIN_IECTRL_NONE,
- 202, UNIPHIER_PIN_DRV_4_8,
+ 202, UNIPHIER_PIN_DRV_1BIT,
202, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(217, "CIN4", UNIPHIER_PIN_IECTRL_NONE,
- 203, UNIPHIER_PIN_DRV_4_8,
+ 203, UNIPHIER_PIN_DRV_1BIT,
203, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(218, "CIN5", UNIPHIER_PIN_IECTRL_NONE,
- 204, UNIPHIER_PIN_DRV_4_8,
+ 204, UNIPHIER_PIN_DRV_1BIT,
204, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(219, "GCP", UNIPHIER_PIN_IECTRL_NONE,
- 205, UNIPHIER_PIN_DRV_4_8,
+ 205, UNIPHIER_PIN_DRV_1BIT,
205, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(220, "ADFLG", UNIPHIER_PIN_IECTRL_NONE,
- 206, UNIPHIER_PIN_DRV_4_8,
+ 206, UNIPHIER_PIN_DRV_1BIT,
206, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(221, "CK27AIOF", UNIPHIER_PIN_IECTRL_NONE,
- 207, UNIPHIER_PIN_DRV_4_8,
+ 207, UNIPHIER_PIN_DRV_1BIT,
207, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(222, "DACOUT", UNIPHIER_PIN_IECTRL_NONE,
- 208, UNIPHIER_PIN_DRV_4_8,
+ 208, UNIPHIER_PIN_DRV_1BIT,
208, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(223, "DAFLG", UNIPHIER_PIN_IECTRL_NONE,
- 209, UNIPHIER_PIN_DRV_4_8,
+ 209, UNIPHIER_PIN_DRV_1BIT,
209, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(224, "VBIH", UNIPHIER_PIN_IECTRL_NONE,
- 210, UNIPHIER_PIN_DRV_4_8,
+ 210, UNIPHIER_PIN_DRV_1BIT,
210, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(225, "VBIL", UNIPHIER_PIN_IECTRL_NONE,
- 211, UNIPHIER_PIN_DRV_4_8,
+ 211, UNIPHIER_PIN_DRV_1BIT,
211, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(226, "XSUB_RST", UNIPHIER_PIN_IECTRL_NONE,
- 212, UNIPHIER_PIN_DRV_4_8,
+ 212, UNIPHIER_PIN_DRV_1BIT,
212, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(227, "XADC_PD", UNIPHIER_PIN_IECTRL_NONE,
- 213, UNIPHIER_PIN_DRV_4_8,
+ 213, UNIPHIER_PIN_DRV_1BIT,
213, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(228, "AI1ADCCK", UNIPHIER_PIN_IECTRL_NONE,
- 214, UNIPHIER_PIN_DRV_4_8,
+ 214, UNIPHIER_PIN_DRV_1BIT,
214, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(229, "AI1BCK", UNIPHIER_PIN_IECTRL_NONE,
- 215, UNIPHIER_PIN_DRV_4_8,
+ 215, UNIPHIER_PIN_DRV_1BIT,
215, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(230, "AI1LRCK", UNIPHIER_PIN_IECTRL_NONE,
- 216, UNIPHIER_PIN_DRV_4_8,
+ 216, UNIPHIER_PIN_DRV_1BIT,
216, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(231, "AI1DMIX", UNIPHIER_PIN_IECTRL_NONE,
- 217, UNIPHIER_PIN_DRV_4_8,
+ 217, UNIPHIER_PIN_DRV_1BIT,
217, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(232, "CK27HD", UNIPHIER_PIN_IECTRL_NONE,
- 218, UNIPHIER_PIN_DRV_4_8,
+ 218, UNIPHIER_PIN_DRV_1BIT,
218, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(233, "XHD_RST", UNIPHIER_PIN_IECTRL_NONE,
- 219, UNIPHIER_PIN_DRV_4_8,
+ 219, UNIPHIER_PIN_DRV_1BIT,
219, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(234, "INTHD", UNIPHIER_PIN_IECTRL_NONE,
- 220, UNIPHIER_PIN_DRV_4_8,
+ 220, UNIPHIER_PIN_DRV_1BIT,
220, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(235, "VO1HDCK", UNIPHIER_PIN_IECTRL_NONE,
- 221, UNIPHIER_PIN_DRV_4_8,
+ 221, UNIPHIER_PIN_DRV_1BIT,
221, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(236, "VO1HSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 222, UNIPHIER_PIN_DRV_4_8,
+ 222, UNIPHIER_PIN_DRV_1BIT,
222, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(237, "VO1VSYNC", UNIPHIER_PIN_IECTRL_NONE,
- 223, UNIPHIER_PIN_DRV_4_8,
+ 223, UNIPHIER_PIN_DRV_1BIT,
223, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(238, "VO1DE", UNIPHIER_PIN_IECTRL_NONE,
- 224, UNIPHIER_PIN_DRV_4_8,
+ 224, UNIPHIER_PIN_DRV_1BIT,
224, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(239, "VO1Y0", UNIPHIER_PIN_IECTRL_NONE,
- 225, UNIPHIER_PIN_DRV_4_8,
+ 225, UNIPHIER_PIN_DRV_1BIT,
225, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(240, "VO1Y1", UNIPHIER_PIN_IECTRL_NONE,
- 226, UNIPHIER_PIN_DRV_4_8,
+ 226, UNIPHIER_PIN_DRV_1BIT,
226, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(241, "VO1Y2", UNIPHIER_PIN_IECTRL_NONE,
- 227, UNIPHIER_PIN_DRV_4_8,
+ 227, UNIPHIER_PIN_DRV_1BIT,
227, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(242, "VO1Y3", UNIPHIER_PIN_IECTRL_NONE,
- 228, UNIPHIER_PIN_DRV_4_8,
+ 228, UNIPHIER_PIN_DRV_1BIT,
228, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(243, "VO1Y4", UNIPHIER_PIN_IECTRL_NONE,
- 229, UNIPHIER_PIN_DRV_4_8,
+ 229, UNIPHIER_PIN_DRV_1BIT,
229, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(244, "VO1Y5", UNIPHIER_PIN_IECTRL_NONE,
- 230, UNIPHIER_PIN_DRV_4_8,
+ 230, UNIPHIER_PIN_DRV_1BIT,
230, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(245, "VO1Y6", UNIPHIER_PIN_IECTRL_NONE,
- 231, UNIPHIER_PIN_DRV_4_8,
+ 231, UNIPHIER_PIN_DRV_1BIT,
231, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(246, "VO1Y7", UNIPHIER_PIN_IECTRL_NONE,
- 232, UNIPHIER_PIN_DRV_4_8,
+ 232, UNIPHIER_PIN_DRV_1BIT,
232, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(247, "VO1Y8", UNIPHIER_PIN_IECTRL_NONE,
- 233, UNIPHIER_PIN_DRV_4_8,
+ 233, UNIPHIER_PIN_DRV_1BIT,
233, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(248, "VO1Y9", UNIPHIER_PIN_IECTRL_NONE,
- 234, UNIPHIER_PIN_DRV_4_8,
+ 234, UNIPHIER_PIN_DRV_1BIT,
234, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(249, "VO1Y10", UNIPHIER_PIN_IECTRL_NONE,
- 235, UNIPHIER_PIN_DRV_4_8,
+ 235, UNIPHIER_PIN_DRV_1BIT,
235, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(250, "VO1Y11", UNIPHIER_PIN_IECTRL_NONE,
- 236, UNIPHIER_PIN_DRV_4_8,
+ 236, UNIPHIER_PIN_DRV_1BIT,
236, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(251, "VO1CB0", UNIPHIER_PIN_IECTRL_NONE,
- 237, UNIPHIER_PIN_DRV_4_8,
+ 237, UNIPHIER_PIN_DRV_1BIT,
237, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(252, "VO1CB1", UNIPHIER_PIN_IECTRL_NONE,
- 238, UNIPHIER_PIN_DRV_4_8,
+ 238, UNIPHIER_PIN_DRV_1BIT,
238, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(253, "VO1CB2", UNIPHIER_PIN_IECTRL_NONE,
- 239, UNIPHIER_PIN_DRV_4_8,
+ 239, UNIPHIER_PIN_DRV_1BIT,
239, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(254, "VO1CB3", UNIPHIER_PIN_IECTRL_NONE,
- 240, UNIPHIER_PIN_DRV_4_8,
+ 240, UNIPHIER_PIN_DRV_1BIT,
240, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(255, "VO1CB4", UNIPHIER_PIN_IECTRL_NONE,
- 241, UNIPHIER_PIN_DRV_4_8,
+ 241, UNIPHIER_PIN_DRV_1BIT,
241, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(256, "VO1CB5", UNIPHIER_PIN_IECTRL_NONE,
- 242, UNIPHIER_PIN_DRV_4_8,
+ 242, UNIPHIER_PIN_DRV_1BIT,
242, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(257, "VO1CB6", UNIPHIER_PIN_IECTRL_NONE,
- 243, UNIPHIER_PIN_DRV_4_8,
+ 243, UNIPHIER_PIN_DRV_1BIT,
243, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(258, "VO1CB7", UNIPHIER_PIN_IECTRL_NONE,
- 244, UNIPHIER_PIN_DRV_4_8,
+ 244, UNIPHIER_PIN_DRV_1BIT,
244, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(259, "VO1CB8", UNIPHIER_PIN_IECTRL_NONE,
- 245, UNIPHIER_PIN_DRV_4_8,
+ 245, UNIPHIER_PIN_DRV_1BIT,
245, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(260, "VO1CB9", UNIPHIER_PIN_IECTRL_NONE,
- 246, UNIPHIER_PIN_DRV_4_8,
+ 246, UNIPHIER_PIN_DRV_1BIT,
246, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(261, "VO1CB10", UNIPHIER_PIN_IECTRL_NONE,
- 247, UNIPHIER_PIN_DRV_4_8,
+ 247, UNIPHIER_PIN_DRV_1BIT,
247, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(262, "VO1CB11", UNIPHIER_PIN_IECTRL_NONE,
- 248, UNIPHIER_PIN_DRV_4_8,
+ 248, UNIPHIER_PIN_DRV_1BIT,
248, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(263, "VO1CR0", UNIPHIER_PIN_IECTRL_NONE,
- 249, UNIPHIER_PIN_DRV_4_8,
+ 249, UNIPHIER_PIN_DRV_1BIT,
249, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(264, "VO1CR1", UNIPHIER_PIN_IECTRL_NONE,
- 250, UNIPHIER_PIN_DRV_4_8,
+ 250, UNIPHIER_PIN_DRV_1BIT,
250, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(265, "VO1CR2", UNIPHIER_PIN_IECTRL_NONE,
- 251, UNIPHIER_PIN_DRV_4_8,
+ 251, UNIPHIER_PIN_DRV_1BIT,
251, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(266, "VO1CR3", UNIPHIER_PIN_IECTRL_NONE,
- 252, UNIPHIER_PIN_DRV_4_8,
+ 252, UNIPHIER_PIN_DRV_1BIT,
252, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(267, "VO1CR4", UNIPHIER_PIN_IECTRL_NONE,
- 253, UNIPHIER_PIN_DRV_4_8,
+ 253, UNIPHIER_PIN_DRV_1BIT,
253, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(268, "VO1CR5", UNIPHIER_PIN_IECTRL_NONE,
- 254, UNIPHIER_PIN_DRV_4_8,
+ 254, UNIPHIER_PIN_DRV_1BIT,
254, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(269, "VO1CR6", UNIPHIER_PIN_IECTRL_NONE,
- 255, UNIPHIER_PIN_DRV_4_8,
+ 255, UNIPHIER_PIN_DRV_1BIT,
255, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(270, "VO1CR7", UNIPHIER_PIN_IECTRL_NONE,
- 256, UNIPHIER_PIN_DRV_4_8,
+ 256, UNIPHIER_PIN_DRV_1BIT,
256, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(271, "VO1CR8", UNIPHIER_PIN_IECTRL_NONE,
- 257, UNIPHIER_PIN_DRV_4_8,
+ 257, UNIPHIER_PIN_DRV_1BIT,
257, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(272, "VO1CR9", UNIPHIER_PIN_IECTRL_NONE,
- 258, UNIPHIER_PIN_DRV_4_8,
+ 258, UNIPHIER_PIN_DRV_1BIT,
258, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(273, "VO1CR10", UNIPHIER_PIN_IECTRL_NONE,
- 259, UNIPHIER_PIN_DRV_4_8,
+ 259, UNIPHIER_PIN_DRV_1BIT,
259, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(274, "VO1CR11", UNIPHIER_PIN_IECTRL_NONE,
- 260, UNIPHIER_PIN_DRV_4_8,
+ 260, UNIPHIER_PIN_DRV_1BIT,
260, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(275, "VO1EX0", UNIPHIER_PIN_IECTRL_NONE,
- 261, UNIPHIER_PIN_DRV_4_8,
+ 261, UNIPHIER_PIN_DRV_1BIT,
261, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(276, "VO1EX1", UNIPHIER_PIN_IECTRL_NONE,
- 262, UNIPHIER_PIN_DRV_4_8,
+ 262, UNIPHIER_PIN_DRV_1BIT,
262, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(277, "VO1EX2", UNIPHIER_PIN_IECTRL_NONE,
- 263, UNIPHIER_PIN_DRV_4_8,
+ 263, UNIPHIER_PIN_DRV_1BIT,
263, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(278, "VO1EX3", UNIPHIER_PIN_IECTRL_NONE,
- 264, UNIPHIER_PIN_DRV_4_8,
+ 264, UNIPHIER_PIN_DRV_1BIT,
264, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(279, "VEXCKA", UNIPHIER_PIN_IECTRL_NONE,
- 265, UNIPHIER_PIN_DRV_4_8,
+ 265, UNIPHIER_PIN_DRV_1BIT,
265, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(280, "VSEL0", UNIPHIER_PIN_IECTRL_NONE,
- 266, UNIPHIER_PIN_DRV_4_8,
+ 266, UNIPHIER_PIN_DRV_1BIT,
266, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(281, "VSEL1", UNIPHIER_PIN_IECTRL_NONE,
- 267, UNIPHIER_PIN_DRV_4_8,
+ 267, UNIPHIER_PIN_DRV_1BIT,
267, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(282, "AO1DACCK", UNIPHIER_PIN_IECTRL_NONE,
- 268, UNIPHIER_PIN_DRV_4_8,
+ 268, UNIPHIER_PIN_DRV_1BIT,
268, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(283, "AO1BCK", UNIPHIER_PIN_IECTRL_NONE,
- 269, UNIPHIER_PIN_DRV_4_8,
+ 269, UNIPHIER_PIN_DRV_1BIT,
269, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(284, "AO1LRCK", UNIPHIER_PIN_IECTRL_NONE,
- 270, UNIPHIER_PIN_DRV_4_8,
+ 270, UNIPHIER_PIN_DRV_1BIT,
270, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(285, "AO1D0", UNIPHIER_PIN_IECTRL_NONE,
- 271, UNIPHIER_PIN_DRV_4_8,
+ 271, UNIPHIER_PIN_DRV_1BIT,
271, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(286, "AO1D1", UNIPHIER_PIN_IECTRL_NONE,
- 272, UNIPHIER_PIN_DRV_4_8,
+ 272, UNIPHIER_PIN_DRV_1BIT,
272, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(287, "AO1D2", UNIPHIER_PIN_IECTRL_NONE,
- 273, UNIPHIER_PIN_DRV_4_8,
+ 273, UNIPHIER_PIN_DRV_1BIT,
273, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(288, "AO1D3", UNIPHIER_PIN_IECTRL_NONE,
- 274, UNIPHIER_PIN_DRV_4_8,
+ 274, UNIPHIER_PIN_DRV_1BIT,
274, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(289, "AO1IEC", UNIPHIER_PIN_IECTRL_NONE,
- 275, UNIPHIER_PIN_DRV_4_8,
+ 275, UNIPHIER_PIN_DRV_1BIT,
275, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(290, "XDAC_PD", UNIPHIER_PIN_IECTRL_NONE,
- 276, UNIPHIER_PIN_DRV_4_8,
+ 276, UNIPHIER_PIN_DRV_1BIT,
276, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(291, "EX_A_MUTE", UNIPHIER_PIN_IECTRL_NONE,
- 277, UNIPHIER_PIN_DRV_4_8,
+ 277, UNIPHIER_PIN_DRV_1BIT,
277, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(292, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE,
- 278, UNIPHIER_PIN_DRV_4_8,
+ 278, UNIPHIER_PIN_DRV_1BIT,
278, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(293, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE,
- 279, UNIPHIER_PIN_DRV_4_8,
+ 279, UNIPHIER_PIN_DRV_1BIT,
279, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(294, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE,
- 280, UNIPHIER_PIN_DRV_4_8,
+ 280, UNIPHIER_PIN_DRV_1BIT,
280, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(295, "AO2DMIX", UNIPHIER_PIN_IECTRL_NONE,
- 281, UNIPHIER_PIN_DRV_4_8,
+ 281, UNIPHIER_PIN_DRV_1BIT,
281, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(296, "AO2IEC", UNIPHIER_PIN_IECTRL_NONE,
- 282, UNIPHIER_PIN_DRV_4_8,
+ 282, UNIPHIER_PIN_DRV_1BIT,
282, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(297, "HTHPD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_5,
+ -1, UNIPHIER_PIN_DRV_FIXED5,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(298, "HTSCL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_5,
+ -1, UNIPHIER_PIN_DRV_FIXED5,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(299, "HTSDA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_5,
+ -1, UNIPHIER_PIN_DRV_FIXED5,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(300, "PORT00", UNIPHIER_PIN_IECTRL_NONE,
- 284, UNIPHIER_PIN_DRV_4_8,
+ 284, UNIPHIER_PIN_DRV_1BIT,
284, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(301, "PORT01", UNIPHIER_PIN_IECTRL_NONE,
- 285, UNIPHIER_PIN_DRV_4_8,
+ 285, UNIPHIER_PIN_DRV_1BIT,
285, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(302, "PORT02", UNIPHIER_PIN_IECTRL_NONE,
- 286, UNIPHIER_PIN_DRV_4_8,
+ 286, UNIPHIER_PIN_DRV_1BIT,
286, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(303, "PORT03", UNIPHIER_PIN_IECTRL_NONE,
- 287, UNIPHIER_PIN_DRV_4_8,
+ 287, UNIPHIER_PIN_DRV_1BIT,
287, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(304, "PORT04", UNIPHIER_PIN_IECTRL_NONE,
- 288, UNIPHIER_PIN_DRV_4_8,
+ 288, UNIPHIER_PIN_DRV_1BIT,
288, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(305, "PORT05", UNIPHIER_PIN_IECTRL_NONE,
- 289, UNIPHIER_PIN_DRV_4_8,
+ 289, UNIPHIER_PIN_DRV_1BIT,
289, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(306, "PORT06", UNIPHIER_PIN_IECTRL_NONE,
- 290, UNIPHIER_PIN_DRV_4_8,
+ 290, UNIPHIER_PIN_DRV_1BIT,
290, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(307, "PORT07", UNIPHIER_PIN_IECTRL_NONE,
- 291, UNIPHIER_PIN_DRV_4_8,
+ 291, UNIPHIER_PIN_DRV_1BIT,
291, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(308, "PORT10", UNIPHIER_PIN_IECTRL_NONE,
- 292, UNIPHIER_PIN_DRV_4_8,
+ 292, UNIPHIER_PIN_DRV_1BIT,
292, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(309, "PORT11", UNIPHIER_PIN_IECTRL_NONE,
- 293, UNIPHIER_PIN_DRV_4_8,
+ 293, UNIPHIER_PIN_DRV_1BIT,
293, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(310, "PORT12", UNIPHIER_PIN_IECTRL_NONE,
- 294, UNIPHIER_PIN_DRV_4_8,
+ 294, UNIPHIER_PIN_DRV_1BIT,
294, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(311, "PORT13", UNIPHIER_PIN_IECTRL_NONE,
- 295, UNIPHIER_PIN_DRV_4_8,
+ 295, UNIPHIER_PIN_DRV_1BIT,
295, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(312, "PORT14", UNIPHIER_PIN_IECTRL_NONE,
- 296, UNIPHIER_PIN_DRV_4_8,
+ 296, UNIPHIER_PIN_DRV_1BIT,
296, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(313, "PORT15", UNIPHIER_PIN_IECTRL_NONE,
- 297, UNIPHIER_PIN_DRV_4_8,
+ 297, UNIPHIER_PIN_DRV_1BIT,
297, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(314, "PORT16", UNIPHIER_PIN_IECTRL_NONE,
- 298, UNIPHIER_PIN_DRV_4_8,
+ 298, UNIPHIER_PIN_DRV_1BIT,
298, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(315, "PORT17", UNIPHIER_PIN_IECTRL_NONE,
- 299, UNIPHIER_PIN_DRV_4_8,
+ 299, UNIPHIER_PIN_DRV_1BIT,
299, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(316, "PORT20", UNIPHIER_PIN_IECTRL_NONE,
- 300, UNIPHIER_PIN_DRV_4_8,
+ 300, UNIPHIER_PIN_DRV_1BIT,
300, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(317, "PORT21", UNIPHIER_PIN_IECTRL_NONE,
- 301, UNIPHIER_PIN_DRV_4_8,
+ 301, UNIPHIER_PIN_DRV_1BIT,
301, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(318, "PORT22", UNIPHIER_PIN_IECTRL_NONE,
- 302, UNIPHIER_PIN_DRV_4_8,
+ 302, UNIPHIER_PIN_DRV_1BIT,
302, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(319, "SD1DAT0", UNIPHIER_PIN_IECTRL_NONE,
- 303, UNIPHIER_PIN_DRV_4_8,
+ 303, UNIPHIER_PIN_DRV_1BIT,
303, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(320, "SD1DAT1", UNIPHIER_PIN_IECTRL_NONE,
- 304, UNIPHIER_PIN_DRV_4_8,
+ 304, UNIPHIER_PIN_DRV_1BIT,
304, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(321, "SD1DAT2", UNIPHIER_PIN_IECTRL_NONE,
- 305, UNIPHIER_PIN_DRV_4_8,
+ 305, UNIPHIER_PIN_DRV_1BIT,
305, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(322, "SD1DAT3", UNIPHIER_PIN_IECTRL_NONE,
- 306, UNIPHIER_PIN_DRV_4_8,
+ 306, UNIPHIER_PIN_DRV_1BIT,
306, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(323, "SD1CMD", UNIPHIER_PIN_IECTRL_NONE,
- 307, UNIPHIER_PIN_DRV_4_8,
+ 307, UNIPHIER_PIN_DRV_1BIT,
307, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(324, "SD1CLK", UNIPHIER_PIN_IECTRL_NONE,
- 308, UNIPHIER_PIN_DRV_4_8,
+ 308, UNIPHIER_PIN_DRV_1BIT,
308, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(325, "SD1CD", UNIPHIER_PIN_IECTRL_NONE,
- 309, UNIPHIER_PIN_DRV_4_8,
+ 309, UNIPHIER_PIN_DRV_1BIT,
309, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(326, "SD1WP", UNIPHIER_PIN_IECTRL_NONE,
- 310, UNIPHIER_PIN_DRV_4_8,
+ 310, UNIPHIER_PIN_DRV_1BIT,
310, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(327, "SD1VTCG", UNIPHIER_PIN_IECTRL_NONE,
- 311, UNIPHIER_PIN_DRV_4_8,
+ 311, UNIPHIER_PIN_DRV_1BIT,
311, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(328, "DMDISO", UNIPHIER_PIN_IECTRL_NONE,
- 312, UNIPHIER_PIN_DRV_NONE,
+ -1, UNIPHIER_PIN_DRV_NONE,
312, UNIPHIER_PIN_PULL_DOWN),
};
static const unsigned emmc_pins[] = {40, 41, 42, 43, 51, 52, 53};
-static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const int emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
static const unsigned emmc_dat8_pins[] = {44, 45, 46, 47};
-static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned ether_mii_pins[] = {160, 161, 162, 163, 164, 165, 166,
+ 167, 168, 169, 170, 171, 172, 173,
+ 174, 175, 176, 177, 178, 179};
+static const int ether_mii_muxvals[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0};
+static const unsigned ether_rgmii_pins[] = {160, 161, 162, 163, 164, 165, 167,
+ 168, 169, 170, 171, 172, 176, 177,
+ 178, 179};
+static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0};
+static const unsigned ether_rmii_pins[] = {160, 161, 162, 165, 168, 169, 172,
+ 173, 176, 177, 178, 179};
+static const int ether_rmii_muxvals[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned ether_rmiib_pins[] = {161, 162, 165, 167, 168, 169, 172,
+ 173, 176, 177, 178, 179};
+static const int ether_rmiib_muxvals[] = {0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned i2c0_pins[] = {142, 143};
-static const unsigned i2c0_muxvals[] = {0, 0};
+static const int i2c0_muxvals[] = {0, 0};
static const unsigned i2c1_pins[] = {144, 145};
-static const unsigned i2c1_muxvals[] = {0, 0};
+static const int i2c1_muxvals[] = {0, 0};
static const unsigned i2c2_pins[] = {146, 147};
-static const unsigned i2c2_muxvals[] = {0, 0};
+static const int i2c2_muxvals[] = {0, 0};
static const unsigned i2c3_pins[] = {148, 149};
-static const unsigned i2c3_muxvals[] = {0, 0};
+static const int i2c3_muxvals[] = {0, 0};
static const unsigned i2c6_pins[] = {308, 309};
-static const unsigned i2c6_muxvals[] = {6, 6};
+static const int i2c6_muxvals[] = {6, 6};
static const unsigned nand_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
50, 51, 52, 53, 54};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned nand_cs1_pins[] = {131, 132};
-static const unsigned nand_cs1_muxvals[] = {1, 1};
+static const int nand_cs1_muxvals[] = {1, 1};
static const unsigned sd_pins[] = {150, 151, 152, 153, 154, 155, 156, 157, 158};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned sd1_pins[] = {319, 320, 321, 322, 323, 324, 325, 326,
327};
-static const unsigned sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const int sd1_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned system_bus_pins[] = {25, 26, 27, 28, 29, 30, 31, 32, 33,
+ 34, 35, 36, 37, 38};
+static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0};
+static const unsigned system_bus_cs0_pins[] = {318};
+static const int system_bus_cs0_muxvals[] = {5};
+static const unsigned system_bus_cs1_pins[] = {24};
+static const int system_bus_cs1_muxvals[] = {0};
+static const unsigned system_bus_cs2_pins[] = {315};
+static const int system_bus_cs2_muxvals[] = {5};
+static const unsigned system_bus_cs3_pins[] = {313};
+static const int system_bus_cs3_muxvals[] = {5};
+static const unsigned system_bus_cs4_pins[] = {305};
+static const int system_bus_cs4_muxvals[] = {5};
+static const unsigned system_bus_cs5_pins[] = {303};
+static const int system_bus_cs5_muxvals[] = {6};
+static const unsigned system_bus_cs6_pins[] = {307};
+static const int system_bus_cs6_muxvals[] = {6};
+static const unsigned system_bus_cs7_pins[] = {312};
+static const int system_bus_cs7_muxvals[] = {6};
static const unsigned uart0_pins[] = {127, 128};
-static const unsigned uart0_muxvals[] = {0, 0};
+static const int uart0_muxvals[] = {0, 0};
static const unsigned uart1_pins[] = {129, 130};
-static const unsigned uart1_muxvals[] = {0, 0};
+static const int uart1_muxvals[] = {0, 0};
static const unsigned uart2_pins[] = {131, 132};
-static const unsigned uart2_muxvals[] = {0, 0};
+static const int uart2_muxvals[] = {0, 0};
static const unsigned uart3_pins[] = {88, 89};
-static const unsigned uart3_muxvals[] = {2, 2};
+static const int uart3_muxvals[] = {2, 2};
static const unsigned usb0_pins[] = {180, 181};
-static const unsigned usb0_muxvals[] = {0, 0};
+static const int usb0_muxvals[] = {0, 0};
static const unsigned usb1_pins[] = {182, 183};
-static const unsigned usb1_muxvals[] = {0, 0};
+static const int usb1_muxvals[] = {0, 0};
static const unsigned usb2_pins[] = {184, 185};
-static const unsigned usb2_muxvals[] = {0, 0};
+static const int usb2_muxvals[] = {0, 0};
static const unsigned usb3_pins[] = {186, 187};
-static const unsigned usb3_muxvals[] = {0, 0};
+static const int usb3_muxvals[] = {0, 0};
static const unsigned port_range0_pins[] = {
300, 301, 302, 303, 304, 305, 306, 307, /* PORT0x */
308, 309, 310, 311, 312, 313, 314, 315, /* PORT1x */
@@ -1069,7 +1102,7 @@ static const unsigned port_range0_pins[] = {
76, 77, 78, 79, 80, 81, 82, 83, /* PORT13x */
84, 85, 86, 87, 88, 89, 90, 91, /* PORT14x */
};
-static const unsigned port_range0_muxvals[] = {
+static const int port_range0_muxvals[] = {
7, 7, 7, 7, 7, 7, 7, 7, /* PORT0x */
7, 7, 7, 7, 7, 7, 7, 7, /* PORT1x */
7, 7, 7, 7, 7, 7, 7, 7, /* PORT2x */
@@ -1102,7 +1135,7 @@ static const unsigned port_range1_pins[] = {
251, 252, 261, 262, 263, 264, 273, 274, /* PORT29x */
31, 32, 33, 34, 35, 36, 37, 38, /* PORT30x */
};
-static const unsigned port_range1_muxvals[] = {
+static const int port_range1_muxvals[] = {
7, 7, 7, /* PORT175-177 */
7, 7, 7, 7, 7, 7, 7, 7, /* PORT18x */
7, 7, 7, 7, 7, 7, 7, 7, /* PORT19x */
@@ -1123,7 +1156,7 @@ static const unsigned xirq_pins[] = {
234, 186, 99, 100, 101, 102, 184, 301, /* XIRQ8-15 */
302, 303, 304, 305, 306, /* XIRQ16-20 */
};
-static const unsigned xirq_muxvals[] = {
+static const int xirq_muxvals[] = {
7, 7, 7, 7, 7, 7, 7, 7, /* XIRQ0-7 */
7, 7, 7, 7, 7, 7, 2, 2, /* XIRQ8-15 */
2, 2, 2, 2, 2, /* XIRQ16-20 */
@@ -1131,13 +1164,17 @@ static const unsigned xirq_muxvals[] = {
static const unsigned xirq_alternatives_pins[] = {
184, 310, 316,
};
-static const unsigned xirq_alternatives_muxvals[] = {
+static const int xirq_alternatives_muxvals[] = {
2, 2, 2,
};
-static const struct uniphier_pinctrl_group ph1_pro4_groups[] = {
+static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = {
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(ether_mii),
+ UNIPHIER_PINCTRL_GROUP(ether_rgmii),
+ UNIPHIER_PINCTRL_GROUP(ether_rmii),
+ UNIPHIER_PINCTRL_GROUP(ether_rmiib),
UNIPHIER_PINCTRL_GROUP(i2c0),
UNIPHIER_PINCTRL_GROUP(i2c1),
UNIPHIER_PINCTRL_GROUP(i2c2),
@@ -1147,6 +1184,15 @@ static const struct uniphier_pinctrl_group ph1_pro4_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
UNIPHIER_PINCTRL_GROUP(sd1),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs6),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs7),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
@@ -1413,6 +1459,9 @@ static const struct uniphier_pinctrl_group ph1_pro4_groups[] = {
};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
+static const char * const ether_mii_groups[] = {"ether_mii"};
+static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
+static const char * const ether_rmii_groups[] = {"ether_rgmii", "ether_rgmiib"};
static const char * const i2c0_groups[] = {"i2c0"};
static const char * const i2c1_groups[] = {"i2c1"};
static const char * const i2c2_groups[] = {"i2c2"};
@@ -1421,6 +1470,15 @@ static const char * const i2c6_groups[] = {"i2c6"};
static const char * const nand_groups[] = {"nand", "nand_cs1"};
static const char * const sd_groups[] = {"sd"};
static const char * const sd1_groups[] = {"sd1"};
+static const char * const system_bus_groups[] = {"system_bus",
+ "system_bus_cs0",
+ "system_bus_cs1",
+ "system_bus_cs2",
+ "system_bus_cs3",
+ "system_bus_cs4",
+ "system_bus_cs5",
+ "system_bus_cs6",
+ "system_bus_cs7"};
static const char * const uart0_groups[] = {"uart0"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
@@ -1499,8 +1557,11 @@ static const char * const xirq_groups[] = {
"xirq14b", "xirq17b", "xirq18b",
};
-static const struct uniphier_pinmux_function ph1_pro4_functions[] = {
+static const struct uniphier_pinmux_function uniphier_pro4_functions[] = {
UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(ether_mii),
+ UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
+ UNIPHIER_PINMUX_FUNCTION(ether_rmii),
UNIPHIER_PINMUX_FUNCTION(i2c0),
UNIPHIER_PINMUX_FUNCTION(i2c1),
UNIPHIER_PINMUX_FUNCTION(i2c2),
@@ -1509,6 +1570,7 @@ static const struct uniphier_pinmux_function ph1_pro4_functions[] = {
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
UNIPHIER_PINMUX_FUNCTION(sd1),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION(uart0),
UNIPHIER_PINMUX_FUNCTION(uart1),
UNIPHIER_PINMUX_FUNCTION(uart2),
@@ -1521,43 +1583,36 @@ static const struct uniphier_pinmux_function ph1_pro4_functions[] = {
UNIPHIER_PINMUX_FUNCTION(xirq),
};
-static struct uniphier_pinctrl_socdata ph1_pro4_pindata = {
- .groups = ph1_pro4_groups,
- .groups_count = ARRAY_SIZE(ph1_pro4_groups),
- .functions = ph1_pro4_functions,
- .functions_count = ARRAY_SIZE(ph1_pro4_functions),
- .mux_bits = 4,
- .reg_stride = 8,
- .load_pinctrl = true,
-};
-
-static struct pinctrl_desc ph1_pro4_pinctrl_desc = {
- .name = DRIVER_NAME,
- .pins = ph1_pro4_pins,
- .npins = ARRAY_SIZE(ph1_pro4_pins),
- .owner = THIS_MODULE,
+static struct uniphier_pinctrl_socdata uniphier_pro4_pindata = {
+ .pins = uniphier_pro4_pins,
+ .npins = ARRAY_SIZE(uniphier_pro4_pins),
+ .groups = uniphier_pro4_groups,
+ .groups_count = ARRAY_SIZE(uniphier_pro4_groups),
+ .functions = uniphier_pro4_functions,
+ .functions_count = ARRAY_SIZE(uniphier_pro4_functions),
+ .caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE,
};
-static int ph1_pro4_pinctrl_probe(struct platform_device *pdev)
+static int uniphier_pro4_pinctrl_probe(struct platform_device *pdev)
{
- return uniphier_pinctrl_probe(pdev, &ph1_pro4_pinctrl_desc,
- &ph1_pro4_pindata);
+ return uniphier_pinctrl_probe(pdev, &uniphier_pro4_pindata);
}
-static const struct of_device_id ph1_pro4_pinctrl_match[] = {
+static const struct of_device_id uniphier_pro4_pinctrl_match[] = {
+ { .compatible = "socionext,uniphier-pro4-pinctrl" },
{ .compatible = "socionext,ph1-pro4-pinctrl" },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, ph1_pro4_pinctrl_match);
+MODULE_DEVICE_TABLE(of, uniphier_pro4_pinctrl_match);
-static struct platform_driver ph1_pro4_pinctrl_driver = {
- .probe = ph1_pro4_pinctrl_probe,
+static struct platform_driver uniphier_pro4_pinctrl_driver = {
+ .probe = uniphier_pro4_pinctrl_probe,
.driver = {
- .name = DRIVER_NAME,
- .of_match_table = ph1_pro4_pinctrl_match,
+ .name = "uniphier-pro4-pinctrl",
+ .of_match_table = uniphier_pro4_pinctrl_match,
},
};
-module_platform_driver(ph1_pro4_pinctrl_driver);
+module_platform_driver(uniphier_pro4_pinctrl_driver);
MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
MODULE_DESCRIPTION("UniPhier PH1-Pro4 pinctrl driver");
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
index 3087f76752a6..55d4a12282a0 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c
@@ -19,823 +19,840 @@
#include "pinctrl-uniphier.h"
-#define DRIVER_NAME "ph1-pro5-pinctrl"
-
-static const struct pinctrl_pin_desc ph1_pro5_pins[] = {
+static const struct pinctrl_pin_desc uniphier_pro5_pins[] = {
UNIPHIER_PINCTRL_PIN(0, "AEXCKA1", 0,
- 0, UNIPHIER_PIN_DRV_4_8,
+ 0, UNIPHIER_PIN_DRV_1BIT,
0, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(1, "AEXCKA2", 0,
- 1, UNIPHIER_PIN_DRV_4_8,
+ 1, UNIPHIER_PIN_DRV_1BIT,
1, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(2, "CK27EXI", 0,
- 2, UNIPHIER_PIN_DRV_4_8,
+ 2, UNIPHIER_PIN_DRV_1BIT,
2, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(3, "CK54EXI", 0,
- 3, UNIPHIER_PIN_DRV_4_8,
+ 3, UNIPHIER_PIN_DRV_1BIT,
3, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(4, "ED0", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_4_8,
+ 4, UNIPHIER_PIN_DRV_1BIT,
4, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(5, "ED1", UNIPHIER_PIN_IECTRL_NONE,
- 5, UNIPHIER_PIN_DRV_4_8,
+ 5, UNIPHIER_PIN_DRV_1BIT,
5, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(6, "ED2", UNIPHIER_PIN_IECTRL_NONE,
- 6, UNIPHIER_PIN_DRV_4_8,
+ 6, UNIPHIER_PIN_DRV_1BIT,
6, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(7, "ED3", UNIPHIER_PIN_IECTRL_NONE,
- 7, UNIPHIER_PIN_DRV_4_8,
+ 7, UNIPHIER_PIN_DRV_1BIT,
7, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(8, "ED4", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_4_8,
+ 8, UNIPHIER_PIN_DRV_1BIT,
8, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(9, "ED5", UNIPHIER_PIN_IECTRL_NONE,
- 9, UNIPHIER_PIN_DRV_4_8,
+ 9, UNIPHIER_PIN_DRV_1BIT,
9, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(10, "ED6", UNIPHIER_PIN_IECTRL_NONE,
- 10, UNIPHIER_PIN_DRV_4_8,
+ 10, UNIPHIER_PIN_DRV_1BIT,
10, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(11, "ED7", UNIPHIER_PIN_IECTRL_NONE,
- 11, UNIPHIER_PIN_DRV_4_8,
+ 11, UNIPHIER_PIN_DRV_1BIT,
11, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(12, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_4_8,
+ 12, UNIPHIER_PIN_DRV_1BIT,
12, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(13, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
- 13, UNIPHIER_PIN_DRV_4_8,
+ 13, UNIPHIER_PIN_DRV_1BIT,
13, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(14, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
- 14, UNIPHIER_PIN_DRV_4_8,
+ 14, UNIPHIER_PIN_DRV_1BIT,
14, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(15, "ES0", UNIPHIER_PIN_IECTRL_NONE,
- 15, UNIPHIER_PIN_DRV_4_8,
+ 15, UNIPHIER_PIN_DRV_1BIT,
15, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(16, "ES1", UNIPHIER_PIN_IECTRL_NONE,
- 16, UNIPHIER_PIN_DRV_4_8,
+ 16, UNIPHIER_PIN_DRV_1BIT,
16, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(17, "ES2", UNIPHIER_PIN_IECTRL_NONE,
- 17, UNIPHIER_PIN_DRV_4_8,
+ 17, UNIPHIER_PIN_DRV_1BIT,
17, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(18, "XECS1", UNIPHIER_PIN_IECTRL_NONE,
- 18, UNIPHIER_PIN_DRV_4_8,
+ 18, UNIPHIER_PIN_DRV_1BIT,
18, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(19, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
- 19, UNIPHIER_PIN_DRV_4_8,
+ 19, UNIPHIER_PIN_DRV_1BIT,
19, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(20, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
- 20, UNIPHIER_PIN_DRV_4_8,
+ 20, UNIPHIER_PIN_DRV_1BIT,
20, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(21, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
- 21, UNIPHIER_PIN_DRV_4_8,
+ 21, UNIPHIER_PIN_DRV_1BIT,
21, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(22, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
- 22, UNIPHIER_PIN_DRV_4_8,
+ 22, UNIPHIER_PIN_DRV_1BIT,
22, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(23, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
- 23, UNIPHIER_PIN_DRV_4_8,
+ 23, UNIPHIER_PIN_DRV_1BIT,
23, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(24, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
- 24, UNIPHIER_PIN_DRV_4_8,
+ 24, UNIPHIER_PIN_DRV_1BIT,
24, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(25, "NFRYBY0", UNIPHIER_PIN_IECTRL_NONE,
- 25, UNIPHIER_PIN_DRV_4_8,
+ 25, UNIPHIER_PIN_DRV_1BIT,
25, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(26, "XNFCE1", UNIPHIER_PIN_IECTRL_NONE,
- 26, UNIPHIER_PIN_DRV_4_8,
+ 26, UNIPHIER_PIN_DRV_1BIT,
26, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(27, "NFRYBY1", UNIPHIER_PIN_IECTRL_NONE,
- 27, UNIPHIER_PIN_DRV_4_8,
+ 27, UNIPHIER_PIN_DRV_1BIT,
27, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(28, "NFD0", UNIPHIER_PIN_IECTRL_NONE,
- 28, UNIPHIER_PIN_DRV_4_8,
+ 28, UNIPHIER_PIN_DRV_1BIT,
28, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(29, "NFD1", UNIPHIER_PIN_IECTRL_NONE,
- 29, UNIPHIER_PIN_DRV_4_8,
+ 29, UNIPHIER_PIN_DRV_1BIT,
29, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(30, "NFD2", UNIPHIER_PIN_IECTRL_NONE,
- 30, UNIPHIER_PIN_DRV_4_8,
+ 30, UNIPHIER_PIN_DRV_1BIT,
30, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(31, "NFD3", UNIPHIER_PIN_IECTRL_NONE,
- 31, UNIPHIER_PIN_DRV_4_8,
+ 31, UNIPHIER_PIN_DRV_1BIT,
31, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(32, "NFD4", UNIPHIER_PIN_IECTRL_NONE,
- 32, UNIPHIER_PIN_DRV_4_8,
+ 32, UNIPHIER_PIN_DRV_1BIT,
32, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(33, "NFD5", UNIPHIER_PIN_IECTRL_NONE,
- 33, UNIPHIER_PIN_DRV_4_8,
+ 33, UNIPHIER_PIN_DRV_1BIT,
33, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(34, "NFD6", UNIPHIER_PIN_IECTRL_NONE,
- 34, UNIPHIER_PIN_DRV_4_8,
+ 34, UNIPHIER_PIN_DRV_1BIT,
34, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(35, "NFD7", UNIPHIER_PIN_IECTRL_NONE,
- 35, UNIPHIER_PIN_DRV_4_8,
+ 35, UNIPHIER_PIN_DRV_1BIT,
35, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(36, "XERST", UNIPHIER_PIN_IECTRL_NONE,
- 36, UNIPHIER_PIN_DRV_4_8,
+ 36, UNIPHIER_PIN_DRV_1BIT,
36, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(37, "MMCCLK", UNIPHIER_PIN_IECTRL_NONE,
- 37, UNIPHIER_PIN_DRV_4_8,
+ 37, UNIPHIER_PIN_DRV_1BIT,
37, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(38, "MMCCMD", UNIPHIER_PIN_IECTRL_NONE,
- 38, UNIPHIER_PIN_DRV_4_8,
+ 38, UNIPHIER_PIN_DRV_1BIT,
38, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(39, "MMCDAT0", UNIPHIER_PIN_IECTRL_NONE,
- 39, UNIPHIER_PIN_DRV_4_8,
+ 39, UNIPHIER_PIN_DRV_1BIT,
39, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(40, "MMCDAT1", UNIPHIER_PIN_IECTRL_NONE,
- 40, UNIPHIER_PIN_DRV_4_8,
+ 40, UNIPHIER_PIN_DRV_1BIT,
40, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(41, "MMCDAT2", UNIPHIER_PIN_IECTRL_NONE,
- 41, UNIPHIER_PIN_DRV_4_8,
+ 41, UNIPHIER_PIN_DRV_1BIT,
41, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(42, "MMCDAT3", UNIPHIER_PIN_IECTRL_NONE,
- 42, UNIPHIER_PIN_DRV_4_8,
+ 42, UNIPHIER_PIN_DRV_1BIT,
42, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(43, "MMCDAT4", UNIPHIER_PIN_IECTRL_NONE,
- 43, UNIPHIER_PIN_DRV_4_8,
+ 43, UNIPHIER_PIN_DRV_1BIT,
43, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(44, "MMCDAT5", UNIPHIER_PIN_IECTRL_NONE,
- 44, UNIPHIER_PIN_DRV_4_8,
+ 44, UNIPHIER_PIN_DRV_1BIT,
44, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(45, "MMCDAT6", UNIPHIER_PIN_IECTRL_NONE,
- 45, UNIPHIER_PIN_DRV_4_8,
+ 45, UNIPHIER_PIN_DRV_1BIT,
45, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(46, "MMCDAT7", UNIPHIER_PIN_IECTRL_NONE,
- 46, UNIPHIER_PIN_DRV_4_8,
+ 46, UNIPHIER_PIN_DRV_1BIT,
46, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(47, "TXD0", 0,
- 47, UNIPHIER_PIN_DRV_4_8,
+ 47, UNIPHIER_PIN_DRV_1BIT,
47, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(48, "RXD0", 0,
- 48, UNIPHIER_PIN_DRV_4_8,
+ 48, UNIPHIER_PIN_DRV_1BIT,
48, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(49, "TXD1", 0,
- 49, UNIPHIER_PIN_DRV_4_8,
+ 49, UNIPHIER_PIN_DRV_1BIT,
49, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(50, "RXD1", 0,
- 50, UNIPHIER_PIN_DRV_4_8,
+ 50, UNIPHIER_PIN_DRV_1BIT,
50, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(51, "TXD2", UNIPHIER_PIN_IECTRL_NONE,
- 51, UNIPHIER_PIN_DRV_4_8,
+ 51, UNIPHIER_PIN_DRV_1BIT,
51, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(52, "RXD2", UNIPHIER_PIN_IECTRL_NONE,
- 52, UNIPHIER_PIN_DRV_4_8,
+ 52, UNIPHIER_PIN_DRV_1BIT,
52, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(53, "TXD3", 0,
- 53, UNIPHIER_PIN_DRV_4_8,
+ 53, UNIPHIER_PIN_DRV_1BIT,
53, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(54, "RXD3", 0,
- 54, UNIPHIER_PIN_DRV_4_8,
+ 54, UNIPHIER_PIN_DRV_1BIT,
54, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(55, "MS0CS0", 0,
- 55, UNIPHIER_PIN_DRV_4_8,
+ 55, UNIPHIER_PIN_DRV_1BIT,
55, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(56, "MS0DO", 0,
- 56, UNIPHIER_PIN_DRV_4_8,
+ 56, UNIPHIER_PIN_DRV_1BIT,
56, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(57, "MS0DI", 0,
- 57, UNIPHIER_PIN_DRV_4_8,
+ 57, UNIPHIER_PIN_DRV_1BIT,
57, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(58, "MS0CLK", 0,
- 58, UNIPHIER_PIN_DRV_4_8,
+ 58, UNIPHIER_PIN_DRV_1BIT,
58, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(59, "CSCLK", 0,
- 59, UNIPHIER_PIN_DRV_4_8,
+ 59, UNIPHIER_PIN_DRV_1BIT,
59, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(60, "CSBPTM", 0,
- 60, UNIPHIER_PIN_DRV_4_8,
+ 60, UNIPHIER_PIN_DRV_1BIT,
60, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(61, "CSBMTP", 0,
- 61, UNIPHIER_PIN_DRV_4_8,
+ 61, UNIPHIER_PIN_DRV_1BIT,
61, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(62, "XCINTP", 0,
- 62, UNIPHIER_PIN_DRV_4_8,
+ 62, UNIPHIER_PIN_DRV_1BIT,
62, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(63, "XCINTM", 0,
- 63, UNIPHIER_PIN_DRV_4_8,
+ 63, UNIPHIER_PIN_DRV_1BIT,
63, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(64, "XCMPREQ", 0,
- 64, UNIPHIER_PIN_DRV_4_8,
+ 64, UNIPHIER_PIN_DRV_1BIT,
64, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(65, "XSRST", 0,
- 65, UNIPHIER_PIN_DRV_4_8,
+ 65, UNIPHIER_PIN_DRV_1BIT,
65, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(66, "LPST", UNIPHIER_PIN_IECTRL_NONE,
- 66, UNIPHIER_PIN_DRV_4_8,
+ 66, UNIPHIER_PIN_DRV_1BIT,
66, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(67, "PWMA", 0,
- 67, UNIPHIER_PIN_DRV_4_8,
+ 67, UNIPHIER_PIN_DRV_1BIT,
67, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(68, "XIRQ0", 0,
- 68, UNIPHIER_PIN_DRV_4_8,
+ 68, UNIPHIER_PIN_DRV_1BIT,
68, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(69, "XIRQ1", 0,
- 69, UNIPHIER_PIN_DRV_4_8,
+ 69, UNIPHIER_PIN_DRV_1BIT,
69, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(70, "XIRQ2", 0,
- 70, UNIPHIER_PIN_DRV_4_8,
+ 70, UNIPHIER_PIN_DRV_1BIT,
70, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(71, "XIRQ3", 0,
- 71, UNIPHIER_PIN_DRV_4_8,
+ 71, UNIPHIER_PIN_DRV_1BIT,
71, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(72, "XIRQ4", 0,
- 72, UNIPHIER_PIN_DRV_4_8,
+ 72, UNIPHIER_PIN_DRV_1BIT,
72, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(73, "XIRQ5", 0,
- 73, UNIPHIER_PIN_DRV_4_8,
+ 73, UNIPHIER_PIN_DRV_1BIT,
73, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(74, "XIRQ6", 0,
- 74, UNIPHIER_PIN_DRV_4_8,
+ 74, UNIPHIER_PIN_DRV_1BIT,
74, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(75, "XIRQ7", 0,
- 75, UNIPHIER_PIN_DRV_4_8,
+ 75, UNIPHIER_PIN_DRV_1BIT,
75, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(76, "XIRQ8", 0,
- 76, UNIPHIER_PIN_DRV_4_8,
+ 76, UNIPHIER_PIN_DRV_1BIT,
76, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(77, "XIRQ9", 0,
- 77, UNIPHIER_PIN_DRV_4_8,
+ 77, UNIPHIER_PIN_DRV_1BIT,
77, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(78, "XIRQ10", 0,
- 78, UNIPHIER_PIN_DRV_4_8,
+ 78, UNIPHIER_PIN_DRV_1BIT,
78, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(79, "XIRQ11", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
79, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(80, "XIRQ12", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
80, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(81, "XIRQ13", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
81, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(82, "XIRQ14", 0,
- 82, UNIPHIER_PIN_DRV_4_8,
+ 82, UNIPHIER_PIN_DRV_1BIT,
82, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(83, "XIRQ15", 0,
- 83, UNIPHIER_PIN_DRV_4_8,
+ 83, UNIPHIER_PIN_DRV_1BIT,
83, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(84, "XIRQ16", 0,
- 84, UNIPHIER_PIN_DRV_4_8,
+ 84, UNIPHIER_PIN_DRV_1BIT,
84, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(85, "XIRQ17", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
85, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(86, "XIRQ18", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
86, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(87, "XIRQ19", 0,
- 87, UNIPHIER_PIN_DRV_4_8,
+ 87, UNIPHIER_PIN_DRV_1BIT,
87, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(88, "XIRQ20", 0,
- 88, UNIPHIER_PIN_DRV_4_8,
+ 88, UNIPHIER_PIN_DRV_1BIT,
88, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(89, "PORT00", 0,
- 89, UNIPHIER_PIN_DRV_4_8,
+ 89, UNIPHIER_PIN_DRV_1BIT,
89, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(90, "PORT01", 0,
- 90, UNIPHIER_PIN_DRV_4_8,
+ 90, UNIPHIER_PIN_DRV_1BIT,
90, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(91, "PORT02", 0,
- 91, UNIPHIER_PIN_DRV_4_8,
+ 91, UNIPHIER_PIN_DRV_1BIT,
91, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(92, "PORT03", 0,
- 92, UNIPHIER_PIN_DRV_4_8,
+ 92, UNIPHIER_PIN_DRV_1BIT,
92, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(93, "PORT04", 0,
- 93, UNIPHIER_PIN_DRV_4_8,
+ 93, UNIPHIER_PIN_DRV_1BIT,
93, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(94, "PORT05", 0,
- 94, UNIPHIER_PIN_DRV_4_8,
+ 94, UNIPHIER_PIN_DRV_1BIT,
94, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(95, "PORT06", 0,
- 95, UNIPHIER_PIN_DRV_4_8,
+ 95, UNIPHIER_PIN_DRV_1BIT,
95, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(96, "PORT07", 0,
- 96, UNIPHIER_PIN_DRV_4_8,
+ 96, UNIPHIER_PIN_DRV_1BIT,
96, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(97, "PORT10", 0,
- 97, UNIPHIER_PIN_DRV_4_8,
+ 97, UNIPHIER_PIN_DRV_1BIT,
97, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(98, "PORT11", 0,
- 98, UNIPHIER_PIN_DRV_4_8,
+ 98, UNIPHIER_PIN_DRV_1BIT,
98, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(99, "PORT12", 0,
- 99, UNIPHIER_PIN_DRV_4_8,
+ 99, UNIPHIER_PIN_DRV_1BIT,
99, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(100, "PORT13", 0,
- 100, UNIPHIER_PIN_DRV_4_8,
+ 100, UNIPHIER_PIN_DRV_1BIT,
100, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(101, "PORT14", 0,
- 101, UNIPHIER_PIN_DRV_4_8,
+ 101, UNIPHIER_PIN_DRV_1BIT,
101, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(102, "PORT15", 0,
- 102, UNIPHIER_PIN_DRV_4_8,
+ 102, UNIPHIER_PIN_DRV_1BIT,
102, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(103, "PORT16", 0,
- 103, UNIPHIER_PIN_DRV_4_8,
+ 103, UNIPHIER_PIN_DRV_1BIT,
103, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(104, "PORT17", 0,
- 104, UNIPHIER_PIN_DRV_4_8,
+ 104, UNIPHIER_PIN_DRV_1BIT,
104, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(105, "T0HPD", 0,
- 105, UNIPHIER_PIN_DRV_4_8,
+ 105, UNIPHIER_PIN_DRV_1BIT,
105, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(106, "T1HPD", 0,
- 106, UNIPHIER_PIN_DRV_4_8,
+ 106, UNIPHIER_PIN_DRV_1BIT,
106, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(107, "R0HPD", 0,
- 107, UNIPHIER_PIN_DRV_4_8,
+ 107, UNIPHIER_PIN_DRV_1BIT,
107, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(108, "R1HPD", 0,
- 108, UNIPHIER_PIN_DRV_4_8,
+ 108, UNIPHIER_PIN_DRV_1BIT,
108, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(109, "XPERST", 0,
- 109, UNIPHIER_PIN_DRV_4_8,
+ 109, UNIPHIER_PIN_DRV_1BIT,
109, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(110, "XPEWAKE", 0,
- 110, UNIPHIER_PIN_DRV_4_8,
+ 110, UNIPHIER_PIN_DRV_1BIT,
110, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(111, "XPECLKRQ", 0,
- 111, UNIPHIER_PIN_DRV_4_8,
+ 111, UNIPHIER_PIN_DRV_1BIT,
111, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(112, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
112, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(113, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
113, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(114, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
114, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(115, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
115, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(116, "SDA2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
116, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(117, "SCL2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
117, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(118, "SDA3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
118, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(119, "SCL3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
119, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(120, "SPISYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
120, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(121, "SPISCLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
121, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(122, "SPITXD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
122, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(123, "SPIRXD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
123, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(124, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
124, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(125, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
125, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(126, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
126, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(127, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
127, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(128, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
128, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(129, "USB2OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
129, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(130, "SMTRST0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
130, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(131, "SMTCMD0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
131, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(132, "SMTD0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
132, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(133, "SMTSEL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
133, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(134, "SMTCLK0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
134, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(135, "SMTRST1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
135, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(136, "SMTCMD1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
136, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(137, "SMTD1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
137, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(138, "SMTSEL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
138, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(139, "SMTCLK1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
139, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(140, "CH0CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
140, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(141, "CH0PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
141, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(142, "CH0VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
142, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(143, "CH0DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
143, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(144, "CH1CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
144, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(145, "CH1PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
145, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(146, "CH1VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
146, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(147, "CH1DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
147, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(148, "CH2CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
148, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(149, "CH2PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
149, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(150, "CH2VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
150, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(151, "CH2DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
151, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(152, "CH3CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
152, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(153, "CH3PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
153, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(154, "CH3VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
154, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(155, "CH3DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
155, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(156, "CH4CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
156, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(157, "CH4PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
157, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(158, "CH4VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
158, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(159, "CH4DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
159, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(160, "CH5CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
160, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(161, "CH5PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
161, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(162, "CH5VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
162, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(163, "CH5DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
163, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(164, "CH6CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
164, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(165, "CH6PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
165, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(166, "CH6VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
166, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(167, "CH6DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
167, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(168, "CH7CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
168, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(169, "CH7PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
169, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(170, "CH7VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
170, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(171, "CH7DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
171, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(172, "AI1ADCCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
172, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(173, "AI1BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
173, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(174, "AI1LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
174, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(175, "AI1D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
175, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(176, "AI1D1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
176, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(177, "AI1D2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
177, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(178, "AI1D3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
178, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(179, "AI2ADCCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
179, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(180, "AI2BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
180, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(181, "AI2LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
181, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(182, "AI2D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
182, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(183, "AI2D1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
183, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(184, "AI2D2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
184, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(185, "AI2D3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
185, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(186, "AI3ADCCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
186, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(187, "AI3BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
187, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(188, "AI3LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
188, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(189, "AI3D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
189, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(190, "AO1IEC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
190, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(191, "AO1DACCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
191, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(192, "AO1BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
192, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(193, "AO1LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
193, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(194, "AO1D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
194, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(195, "AO1D1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
195, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(196, "AO1D2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
196, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(197, "AO1D3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
197, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(198, "AO2IEC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
198, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(199, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
199, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(200, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
200, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(201, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
201, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(202, "AO2D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
202, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(203, "AO2D1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
203, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(204, "AO2D2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
204, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(205, "AO2D3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
205, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(206, "AO3DACCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
206, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(207, "AO3BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
207, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(208, "AO3LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
208, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(209, "AO3DMIX", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
209, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(210, "AO4DACCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
210, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(211, "AO4BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
211, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(212, "AO4LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
212, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(213, "AO4DMIX", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
213, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(214, "VI1CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
214, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(215, "VI1C0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
215, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(216, "VI1C1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
216, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(217, "VI1C2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
217, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(218, "VI1C3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
218, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(219, "VI1C4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
219, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(220, "VI1C5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
220, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(221, "VI1C6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
221, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(222, "VI1C7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
222, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(223, "VI1C8", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
223, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(224, "VI1C9", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
224, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(225, "VI1Y0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
225, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(226, "VI1Y1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
226, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(227, "VI1Y2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
227, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(228, "VI1Y3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
228, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(229, "VI1Y4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
229, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(230, "VI1Y5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
230, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(231, "VI1Y6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
231, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(232, "VI1Y7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
232, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(233, "VI1Y8", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
233, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(234, "VI1Y9", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
234, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(235, "VI1DE", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
235, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(236, "VI1HSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
236, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(237, "VI1VSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
237, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(238, "VO1CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
238, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(239, "VO1D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
239, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(240, "VO1D1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
240, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(241, "VO1D2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
241, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(242, "VO1D3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
242, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(243, "VO1D4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
243, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(244, "VO1D5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
244, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(245, "VO1D6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
245, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(246, "VO1D7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
246, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(247, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
247, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(248, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
248, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(249, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
249, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(250, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
- 40, UNIPHIER_PIN_DRV_8_12_16_20,
+ 10, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(251, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
- 44, UNIPHIER_PIN_DRV_8_12_16_20,
+ 11, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(252, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
- 48, UNIPHIER_PIN_DRV_8_12_16_20,
+ 12, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(253, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
- 52, UNIPHIER_PIN_DRV_8_12_16_20,
+ 13, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(254, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
- 56, UNIPHIER_PIN_DRV_8_12_16_20,
+ 14, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(255, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
- 60, UNIPHIER_PIN_DRV_8_12_16_20,
+ 15, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
};
static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
-static const unsigned emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
+static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
-static const unsigned emmc_dat8_muxvals[] = {0, 0, 0, 0};
+static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
static const unsigned i2c0_pins[] = {112, 113};
-static const unsigned i2c0_muxvals[] = {0, 0};
+static const int i2c0_muxvals[] = {0, 0};
static const unsigned i2c1_pins[] = {114, 115};
-static const unsigned i2c1_muxvals[] = {0, 0};
+static const int i2c1_muxvals[] = {0, 0};
static const unsigned i2c2_pins[] = {116, 117};
-static const unsigned i2c2_muxvals[] = {0, 0};
+static const int i2c2_muxvals[] = {0, 0};
static const unsigned i2c3_pins[] = {118, 119};
-static const unsigned i2c3_muxvals[] = {0, 0};
+static const int i2c3_muxvals[] = {0, 0};
static const unsigned i2c5_pins[] = {87, 88};
-static const unsigned i2c5_muxvals[] = {2, 2};
+static const int i2c5_muxvals[] = {2, 2};
static const unsigned i2c5b_pins[] = {196, 197};
-static const unsigned i2c5b_muxvals[] = {2, 2};
+static const int i2c5b_muxvals[] = {2, 2};
static const unsigned i2c5c_pins[] = {215, 216};
-static const unsigned i2c5c_muxvals[] = {2, 2};
+static const int i2c5c_muxvals[] = {2, 2};
static const unsigned i2c6_pins[] = {101, 102};
-static const unsigned i2c6_muxvals[] = {2, 2};
+static const int i2c6_muxvals[] = {2, 2};
static const unsigned nand_pins[] = {19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
31, 32, 33, 34, 35};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned nand_cs1_pins[] = {26, 27};
-static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned system_bus_pins[] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
+ 14, 15, 16, 17};
+static const int system_bus_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0};
+static const unsigned system_bus_cs0_pins[] = {105};
+static const int system_bus_cs0_muxvals[] = {1};
+static const unsigned system_bus_cs1_pins[] = {18};
+static const int system_bus_cs1_muxvals[] = {0};
+static const unsigned system_bus_cs2_pins[] = {106};
+static const int system_bus_cs2_muxvals[] = {1};
+static const unsigned system_bus_cs3_pins[] = {100};
+static const int system_bus_cs3_muxvals[] = {1};
+static const unsigned system_bus_cs4_pins[] = {101};
+static const int system_bus_cs4_muxvals[] = {1};
+static const unsigned system_bus_cs5_pins[] = {102};
+static const int system_bus_cs5_muxvals[] = {1};
+static const unsigned system_bus_cs6_pins[] = {69};
+static const int system_bus_cs6_muxvals[] = {5};
+static const unsigned system_bus_cs7_pins[] = {70};
+static const int system_bus_cs7_muxvals[] = {5};
static const unsigned uart0_pins[] = {47, 48};
-static const unsigned uart0_muxvals[] = {0, 0};
+static const int uart0_muxvals[] = {0, 0};
static const unsigned uart0b_pins[] = {227, 228};
-static const unsigned uart0b_muxvals[] = {3, 3};
+static const int uart0b_muxvals[] = {3, 3};
static const unsigned uart1_pins[] = {49, 50};
-static const unsigned uart1_muxvals[] = {0, 0};
+static const int uart1_muxvals[] = {0, 0};
static const unsigned uart2_pins[] = {51, 52};
-static const unsigned uart2_muxvals[] = {0, 0};
+static const int uart2_muxvals[] = {0, 0};
static const unsigned uart3_pins[] = {53, 54};
-static const unsigned uart3_muxvals[] = {0, 0};
+static const int uart3_muxvals[] = {0, 0};
static const unsigned usb0_pins[] = {124, 125};
-static const unsigned usb0_muxvals[] = {0, 0};
+static const int usb0_muxvals[] = {0, 0};
static const unsigned usb1_pins[] = {126, 127};
-static const unsigned usb1_muxvals[] = {0, 0};
+static const int usb1_muxvals[] = {0, 0};
static const unsigned usb2_pins[] = {128, 129};
-static const unsigned usb2_muxvals[] = {0, 0};
+static const int usb2_muxvals[] = {0, 0};
static const unsigned port_range0_pins[] = {
89, 90, 91, 92, 93, 94, 95, 96, /* PORT0x */
97, 98, 99, 100, 101, 102, 103, 104, /* PORT1x */
@@ -853,7 +870,7 @@ static const unsigned port_range0_pins[] = {
179, 180, 181, 182, 186, 187, 188, 189, /* PORT13x */
4, 5, 6, 7, 8, 9, 10, 11, /* PORT14x */
};
-static const unsigned port_range0_muxvals[] = {
+static const int port_range0_muxvals[] = {
15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
@@ -886,7 +903,7 @@ static const unsigned port_range1_pins[] = {
105, 106, 18, 27, 36, 128, 132, 137, /* PORT29x */
183, 184, 185, 84, 47, 48, 51, 52, /* PORT30x */
};
-static const unsigned port_range1_muxvals[] = {
+static const int port_range1_muxvals[] = {
15, 15, 15, /* PORT175-177 */
15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */
15, 15, 15, 15, 15, 15, 15, 15, /* PORT19x */
@@ -907,7 +924,7 @@ static const unsigned xirq_pins[] = {
76, 77, 78, 79, 80, 81, 82, 83, /* XIRQ8-15 */
84, 85, 86, 87, 88, /* XIRQ16-20 */
};
-static const unsigned xirq_muxvals[] = {
+static const int xirq_muxvals[] = {
14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */
14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */
14, 14, 14, 14, 14, /* XIRQ16-20 */
@@ -915,11 +932,11 @@ static const unsigned xirq_muxvals[] = {
static const unsigned xirq_alternatives_pins[] = {
91, 92, 239, 144, 240, 156, 241, 106, 128,
};
-static const unsigned xirq_alternatives_muxvals[] = {
+static const int xirq_alternatives_muxvals[] = {
14, 14, 14, 14, 14, 14, 14, 14, 14,
};
-static const struct uniphier_pinctrl_group ph1_pro5_groups[] = {
+static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(emmc),
@@ -933,6 +950,15 @@ static const struct uniphier_pinctrl_group ph1_pro5_groups[] = {
UNIPHIER_PINCTRL_GROUP(i2c5c),
UNIPHIER_PINCTRL_GROUP(i2c6),
UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs6),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs7),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0b),
UNIPHIER_PINCTRL_GROUP(uart1),
@@ -1213,6 +1239,15 @@ static const char * const i2c5_groups[] = {"i2c5", "i2c5b", "i2c5c"};
static const char * const i2c6_groups[] = {"i2c6"};
static const char * const nand_groups[] = {"nand", "nand_cs1"};
static const char * const sd_groups[] = {"sd"};
+static const char * const system_bus_groups[] = {"system_bus",
+ "system_bus_cs0",
+ "system_bus_cs1",
+ "system_bus_cs2",
+ "system_bus_cs3",
+ "system_bus_cs4",
+ "system_bus_cs5",
+ "system_bus_cs6",
+ "system_bus_cs7"};
static const char * const uart0_groups[] = {"uart0", "uart0b"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
@@ -1291,7 +1326,7 @@ static const char * const xirq_groups[] = {
"xirq18b", "xirq18c", "xirq19b", "xirq20b",
};
-static const struct uniphier_pinmux_function ph1_pro5_functions[] = {
+static const struct uniphier_pinmux_function uniphier_pro5_functions[] = {
UNIPHIER_PINMUX_FUNCTION(emmc),
UNIPHIER_PINMUX_FUNCTION(i2c0),
UNIPHIER_PINMUX_FUNCTION(i2c1),
@@ -1301,6 +1336,7 @@ static const struct uniphier_pinmux_function ph1_pro5_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c6),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION(uart0),
UNIPHIER_PINMUX_FUNCTION(uart1),
UNIPHIER_PINMUX_FUNCTION(uart2),
@@ -1312,43 +1348,36 @@ static const struct uniphier_pinmux_function ph1_pro5_functions[] = {
UNIPHIER_PINMUX_FUNCTION(xirq),
};
-static struct uniphier_pinctrl_socdata ph1_pro5_pindata = {
- .groups = ph1_pro5_groups,
- .groups_count = ARRAY_SIZE(ph1_pro5_groups),
- .functions = ph1_pro5_functions,
- .functions_count = ARRAY_SIZE(ph1_pro5_functions),
- .mux_bits = 4,
- .reg_stride = 8,
- .load_pinctrl = true,
-};
-
-static struct pinctrl_desc ph1_pro5_pinctrl_desc = {
- .name = DRIVER_NAME,
- .pins = ph1_pro5_pins,
- .npins = ARRAY_SIZE(ph1_pro5_pins),
- .owner = THIS_MODULE,
+static struct uniphier_pinctrl_socdata uniphier_pro5_pindata = {
+ .pins = uniphier_pro5_pins,
+ .npins = ARRAY_SIZE(uniphier_pro5_pins),
+ .groups = uniphier_pro5_groups,
+ .groups_count = ARRAY_SIZE(uniphier_pro5_groups),
+ .functions = uniphier_pro5_functions,
+ .functions_count = ARRAY_SIZE(uniphier_pro5_functions),
+ .caps = UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE,
};
-static int ph1_pro5_pinctrl_probe(struct platform_device *pdev)
+static int uniphier_pro5_pinctrl_probe(struct platform_device *pdev)
{
- return uniphier_pinctrl_probe(pdev, &ph1_pro5_pinctrl_desc,
- &ph1_pro5_pindata);
+ return uniphier_pinctrl_probe(pdev, &uniphier_pro5_pindata);
}
-static const struct of_device_id ph1_pro5_pinctrl_match[] = {
+static const struct of_device_id uniphier_pro5_pinctrl_match[] = {
+ { .compatible = "socionext,uniphier-pro5-pinctrl" },
{ .compatible = "socionext,ph1-pro5-pinctrl" },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, ph1_pro5_pinctrl_match);
+MODULE_DEVICE_TABLE(of, uniphier_pro5_pinctrl_match);
-static struct platform_driver ph1_pro5_pinctrl_driver = {
- .probe = ph1_pro5_pinctrl_probe,
+static struct platform_driver uniphier_pro5_pinctrl_driver = {
+ .probe = uniphier_pro5_pinctrl_probe,
.driver = {
- .name = DRIVER_NAME,
- .of_match_table = ph1_pro5_pinctrl_match,
+ .name = "uniphier-pro5-pinctrl",
+ .of_match_table = uniphier_pro5_pinctrl_match,
},
};
-module_platform_driver(ph1_pro5_pinctrl_driver);
+module_platform_driver(uniphier_pro5_pinctrl_driver);
MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
MODULE_DESCRIPTION("UniPhier PH1-Pro5 pinctrl driver");
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
index e868030ff31c..85ca5e2d8a9c 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c
@@ -19,760 +19,776 @@
#include "pinctrl-uniphier.h"
-#define DRIVER_NAME "proxstream2-pinctrl"
-
-static const struct pinctrl_pin_desc proxstream2_pins[] = {
+static const struct pinctrl_pin_desc uniphier_pxs2_pins[] = {
UNIPHIER_PINCTRL_PIN(0, "ED0", UNIPHIER_PIN_IECTRL_NONE,
- 0, UNIPHIER_PIN_DRV_4_8,
+ 0, UNIPHIER_PIN_DRV_1BIT,
0, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(1, "ED1", UNIPHIER_PIN_IECTRL_NONE,
- 1, UNIPHIER_PIN_DRV_4_8,
+ 1, UNIPHIER_PIN_DRV_1BIT,
1, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(2, "ED2", UNIPHIER_PIN_IECTRL_NONE,
- 2, UNIPHIER_PIN_DRV_4_8,
+ 2, UNIPHIER_PIN_DRV_1BIT,
2, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(3, "ED3", UNIPHIER_PIN_IECTRL_NONE,
- 3, UNIPHIER_PIN_DRV_4_8,
+ 3, UNIPHIER_PIN_DRV_1BIT,
3, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(4, "ED4", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_4_8,
+ 4, UNIPHIER_PIN_DRV_1BIT,
4, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(5, "ED5", UNIPHIER_PIN_IECTRL_NONE,
- 5, UNIPHIER_PIN_DRV_4_8,
+ 5, UNIPHIER_PIN_DRV_1BIT,
5, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(6, "ED6", UNIPHIER_PIN_IECTRL_NONE,
- 6, UNIPHIER_PIN_DRV_4_8,
+ 6, UNIPHIER_PIN_DRV_1BIT,
6, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(7, "ED7", UNIPHIER_PIN_IECTRL_NONE,
- 7, UNIPHIER_PIN_DRV_4_8,
+ 7, UNIPHIER_PIN_DRV_1BIT,
7, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(8, "XERWE0", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_4_8,
+ 8, UNIPHIER_PIN_DRV_1BIT,
8, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(9, "XERWE1", UNIPHIER_PIN_IECTRL_NONE,
- 9, UNIPHIER_PIN_DRV_4_8,
+ 9, UNIPHIER_PIN_DRV_1BIT,
9, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(10, "ERXW", UNIPHIER_PIN_IECTRL_NONE,
- 10, UNIPHIER_PIN_DRV_4_8,
+ 10, UNIPHIER_PIN_DRV_1BIT,
10, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(11, "ES0", UNIPHIER_PIN_IECTRL_NONE,
- 11, UNIPHIER_PIN_DRV_4_8,
+ 11, UNIPHIER_PIN_DRV_1BIT,
11, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(12, "ES1", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_4_8,
+ 12, UNIPHIER_PIN_DRV_1BIT,
12, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(13, "ES2", UNIPHIER_PIN_IECTRL_NONE,
- 13, UNIPHIER_PIN_DRV_4_8,
+ 13, UNIPHIER_PIN_DRV_1BIT,
13, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(14, "XECS1", UNIPHIER_PIN_IECTRL_NONE,
- 14, UNIPHIER_PIN_DRV_4_8,
+ 14, UNIPHIER_PIN_DRV_1BIT,
14, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(15, "SMTRST0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
15, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(16, "SMTCMD0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
16, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(17, "SMTD0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
17, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(18, "SMTSEL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
18, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(19, "SMTCLK0CG", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
19, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(20, "SMTDET0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
20, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(21, "SMTRST1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
21, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(22, "SMTCMD1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
22, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(23, "SMTD1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
23, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(24, "SMTSEL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
24, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(25, "SMTCLK1CG", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
25, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(26, "SMTDET1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
26, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(27, "XIRQ18", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
27, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(28, "XIRQ19", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
28, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(29, "XIRQ20", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
29, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(30, "XNFRE", UNIPHIER_PIN_IECTRL_NONE,
- 30, UNIPHIER_PIN_DRV_4_8,
+ 30, UNIPHIER_PIN_DRV_1BIT,
30, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(31, "XNFWE", UNIPHIER_PIN_IECTRL_NONE,
- 31, UNIPHIER_PIN_DRV_4_8,
+ 31, UNIPHIER_PIN_DRV_1BIT,
31, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(32, "NFALE", UNIPHIER_PIN_IECTRL_NONE,
- 32, UNIPHIER_PIN_DRV_4_8,
+ 32, UNIPHIER_PIN_DRV_1BIT,
32, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(33, "NFCLE", UNIPHIER_PIN_IECTRL_NONE,
- 33, UNIPHIER_PIN_DRV_4_8,
+ 33, UNIPHIER_PIN_DRV_1BIT,
33, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(34, "XNFWP", UNIPHIER_PIN_IECTRL_NONE,
- 34, UNIPHIER_PIN_DRV_4_8,
+ 34, UNIPHIER_PIN_DRV_1BIT,
34, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(35, "XNFCE0", UNIPHIER_PIN_IECTRL_NONE,
- 35, UNIPHIER_PIN_DRV_4_8,
+ 35, UNIPHIER_PIN_DRV_1BIT,
35, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(36, "NFRYBY0", UNIPHIER_PIN_IECTRL_NONE,
- 36, UNIPHIER_PIN_DRV_4_8,
+ 36, UNIPHIER_PIN_DRV_1BIT,
36, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(37, "XNFCE1", UNIPHIER_PIN_IECTRL_NONE,
- 37, UNIPHIER_PIN_DRV_4_8,
+ 37, UNIPHIER_PIN_DRV_1BIT,
37, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(38, "NFRYBY1", UNIPHIER_PIN_IECTRL_NONE,
- 38, UNIPHIER_PIN_DRV_4_8,
+ 38, UNIPHIER_PIN_DRV_1BIT,
38, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(39, "NFD0", UNIPHIER_PIN_IECTRL_NONE,
- 39, UNIPHIER_PIN_DRV_4_8,
+ 39, UNIPHIER_PIN_DRV_1BIT,
39, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(40, "NFD1", UNIPHIER_PIN_IECTRL_NONE,
- 40, UNIPHIER_PIN_DRV_4_8,
+ 40, UNIPHIER_PIN_DRV_1BIT,
40, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(41, "NFD2", UNIPHIER_PIN_IECTRL_NONE,
- 41, UNIPHIER_PIN_DRV_4_8,
+ 41, UNIPHIER_PIN_DRV_1BIT,
41, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(42, "NFD3", UNIPHIER_PIN_IECTRL_NONE,
- 42, UNIPHIER_PIN_DRV_4_8,
+ 42, UNIPHIER_PIN_DRV_1BIT,
42, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(43, "NFD4", UNIPHIER_PIN_IECTRL_NONE,
- 43, UNIPHIER_PIN_DRV_4_8,
+ 43, UNIPHIER_PIN_DRV_1BIT,
43, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(44, "NFD5", UNIPHIER_PIN_IECTRL_NONE,
- 44, UNIPHIER_PIN_DRV_4_8,
+ 44, UNIPHIER_PIN_DRV_1BIT,
44, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(45, "NFD6", UNIPHIER_PIN_IECTRL_NONE,
- 45, UNIPHIER_PIN_DRV_4_8,
+ 45, UNIPHIER_PIN_DRV_1BIT,
45, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(46, "NFD7", UNIPHIER_PIN_IECTRL_NONE,
- 46, UNIPHIER_PIN_DRV_4_8,
+ 46, UNIPHIER_PIN_DRV_1BIT,
46, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(47, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
- 0, UNIPHIER_PIN_DRV_8_12_16_20,
+ 0, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(48, "SDCMD", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_8_12_16_20,
+ 1, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(49, "SDDAT0", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_8_12_16_20,
+ 2, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(50, "SDDAT1", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_8_12_16_20,
+ 3, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(51, "SDDAT2", UNIPHIER_PIN_IECTRL_NONE,
- 16, UNIPHIER_PIN_DRV_8_12_16_20,
+ 4, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(52, "SDDAT3", UNIPHIER_PIN_IECTRL_NONE,
- 20, UNIPHIER_PIN_DRV_8_12_16_20,
+ 5, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_UP_FIXED),
UNIPHIER_PINCTRL_PIN(53, "SDCD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
53, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(54, "SDWP", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
54, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(55, "SDVOLC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
55, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(56, "USB0VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
56, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(57, "USB0OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
57, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(58, "USB1VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
58, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(59, "USB1OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
59, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(60, "USB2VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
60, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(61, "USB2OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
61, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(62, "USB3VBUS", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
62, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(63, "USB3OD", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
63, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(64, "CH0CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
64, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(65, "CH0PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
65, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(66, "CH0VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
66, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(67, "CH0DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
67, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(68, "CH1CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
68, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(69, "CH1PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
69, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(70, "CH1VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
70, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(71, "CH1DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
71, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(72, "XIRQ9", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
72, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(73, "XIRQ10", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
73, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(74, "XIRQ16", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
74, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(75, "CH4CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
75, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(76, "CH4PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
76, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(77, "CH4VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
77, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(78, "CH4DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
78, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(79, "CH5CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
79, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(80, "CH5PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
80, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(81, "CH5VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
81, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(82, "CH5DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
82, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(83, "CH6CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
83, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(84, "CH6PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
84, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(85, "CH6VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
85, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(86, "CH6DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
86, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(87, "STS0CLKO", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
87, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(88, "STS0SYNCO", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
88, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(89, "STS0VALO", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
89, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(90, "STS0DATAO", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
90, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(91, "XIRQ17", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
91, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(92, "PORT163", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
92, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(93, "PORT165", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
93, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(94, "PORT166", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
94, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(95, "PORT132", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
95, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(96, "PORT133", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
96, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(97, "AO2IEC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
97, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(98, "AI2ADCCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
98, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(99, "AI2BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
99, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(100, "AI2LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
100, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(101, "AI2D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
101, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(102, "AI2D1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
102, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(103, "AI2D2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
103, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(104, "AI2D3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
104, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(105, "AO3DACCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
105, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(106, "AO3BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
106, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(107, "AO3LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
107, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(108, "AO3DMIX", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
108, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(109, "SDA0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
109, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(110, "SCL0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
110, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(111, "SDA1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
111, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(112, "SCL1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
112, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(113, "TXD2", 0,
- 113, UNIPHIER_PIN_DRV_4_8,
+ 113, UNIPHIER_PIN_DRV_1BIT,
113, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(114, "RXD2", 0,
- 114, UNIPHIER_PIN_DRV_4_8,
+ 114, UNIPHIER_PIN_DRV_1BIT,
114, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(115, "TXD1", 0,
- 115, UNIPHIER_PIN_DRV_4_8,
+ 115, UNIPHIER_PIN_DRV_1BIT,
115, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(116, "RXD1", 0,
- 116, UNIPHIER_PIN_DRV_4_8,
+ 116, UNIPHIER_PIN_DRV_1BIT,
116, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(117, "PORT190", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
117, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(118, "VI1HSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
118, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(119, "VI1VSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
119, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(120, "VI1DE", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
120, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(121, "XIRQ3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
121, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(122, "XIRQ4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
122, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(123, "VI1G2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
123, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(124, "VI1G3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
124, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(125, "VI1G4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
125, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(126, "VI1G5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
126, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(127, "VI1G6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
127, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(128, "VI1G7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
128, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(129, "VI1G8", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
129, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(130, "VI1G9", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
130, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(131, "VI1CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
131, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(132, "PORT05", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
132, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(133, "PORT06", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
133, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(134, "VI1R2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
134, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(135, "VI1R3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
135, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(136, "VI1R4", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
136, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(137, "VI1R5", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
137, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(138, "VI1R6", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
138, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(139, "VI1R7", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
139, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(140, "VI1R8", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
140, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(141, "VI1R9", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
141, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(142, "LPST", UNIPHIER_PIN_IECTRL_NONE,
- 142, UNIPHIER_PIN_DRV_4_8,
+ 142, UNIPHIER_PIN_DRV_1BIT,
142, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(143, "MDC", 0,
- 143, UNIPHIER_PIN_DRV_4_8,
+ 143, UNIPHIER_PIN_DRV_1BIT,
143, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(144, "MDIO", 0,
- 144, UNIPHIER_PIN_DRV_4_8,
+ 144, UNIPHIER_PIN_DRV_1BIT,
144, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(145, "MDIO_INTL", 0,
- 145, UNIPHIER_PIN_DRV_4_8,
+ 145, UNIPHIER_PIN_DRV_1BIT,
145, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(146, "PHYRSTL", 0,
- 146, UNIPHIER_PIN_DRV_4_8,
+ 146, UNIPHIER_PIN_DRV_1BIT,
146, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(147, "RGMII_RXCLK", 0,
- 147, UNIPHIER_PIN_DRV_4_8,
+ 147, UNIPHIER_PIN_DRV_1BIT,
147, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(148, "RGMII_RXD0", 0,
- 148, UNIPHIER_PIN_DRV_4_8,
+ 148, UNIPHIER_PIN_DRV_1BIT,
148, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(149, "RGMII_RXD1", 0,
- 149, UNIPHIER_PIN_DRV_4_8,
+ 149, UNIPHIER_PIN_DRV_1BIT,
149, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(150, "RGMII_RXD2", 0,
- 150, UNIPHIER_PIN_DRV_4_8,
+ 150, UNIPHIER_PIN_DRV_1BIT,
150, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(151, "RGMII_RXD3", 0,
- 151, UNIPHIER_PIN_DRV_4_8,
+ 151, UNIPHIER_PIN_DRV_1BIT,
151, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(152, "RGMII_RXCTL", 0,
- 152, UNIPHIER_PIN_DRV_4_8,
+ 152, UNIPHIER_PIN_DRV_1BIT,
152, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(153, "RGMII_TXCLK", 0,
- 153, UNIPHIER_PIN_DRV_4_8,
+ 153, UNIPHIER_PIN_DRV_1BIT,
153, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(154, "RGMII_TXD0", 0,
- 154, UNIPHIER_PIN_DRV_4_8,
+ 154, UNIPHIER_PIN_DRV_1BIT,
154, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(155, "RGMII_TXD1", 0,
- 155, UNIPHIER_PIN_DRV_4_8,
+ 155, UNIPHIER_PIN_DRV_1BIT,
155, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(156, "RGMII_TXD2", 0,
- 156, UNIPHIER_PIN_DRV_4_8,
+ 156, UNIPHIER_PIN_DRV_1BIT,
156, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(157, "RGMII_TXD3", 0,
- 157, UNIPHIER_PIN_DRV_4_8,
+ 157, UNIPHIER_PIN_DRV_1BIT,
157, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(158, "RGMII_TXCTL", 0,
- 158, UNIPHIER_PIN_DRV_4_8,
+ 158, UNIPHIER_PIN_DRV_1BIT,
158, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(159, "SDA3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
159, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(160, "SCL3", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
160, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(161, "AI1ADCCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
161, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(162, "AI1BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
162, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(163, "CH2CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
163, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(164, "CH2PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
164, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(165, "CH2VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
165, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(166, "CH2DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
166, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(167, "CH3CLK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
167, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(168, "CH3PSYNC", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
168, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(169, "CH3VAL", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
169, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(170, "CH3DATA", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
170, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(171, "SDA2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
171, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(172, "SCL2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
172, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(173, "AI1LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
173, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(174, "AI1D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
174, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(175, "AO2LRCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
175, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(176, "AO2D0", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
176, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(177, "AO2DACCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
177, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(178, "AO2BCK", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
178, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(179, "PORT222", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
179, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(180, "PORT223", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
180, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(181, "PORT224", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
181, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(182, "PORT225", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
182, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(183, "PORT226", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
183, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(184, "PORT227", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
184, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(185, "PORT230", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
185, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(186, "FANPWM", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
186, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(187, "HRDDCSDA0", 0,
- 187, UNIPHIER_PIN_DRV_4_8,
+ 187, UNIPHIER_PIN_DRV_1BIT,
187, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(188, "HRDDCSCL0", 0,
- 188, UNIPHIER_PIN_DRV_4_8,
+ 188, UNIPHIER_PIN_DRV_1BIT,
188, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(189, "HRDDCSDA1", 0,
- 189, UNIPHIER_PIN_DRV_4_8,
+ 189, UNIPHIER_PIN_DRV_1BIT,
189, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(190, "HRDDCSCL1", 0,
- 190, UNIPHIER_PIN_DRV_4_8,
+ 190, UNIPHIER_PIN_DRV_1BIT,
190, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(191, "HTDDCSDA0", 0,
- 191, UNIPHIER_PIN_DRV_4_8,
+ 191, UNIPHIER_PIN_DRV_1BIT,
191, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(192, "HTDDCSCL0", 0,
- 192, UNIPHIER_PIN_DRV_4_8,
+ 192, UNIPHIER_PIN_DRV_1BIT,
192, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(193, "HTDDCSDA1", 0,
- 193, UNIPHIER_PIN_DRV_4_8,
+ 193, UNIPHIER_PIN_DRV_1BIT,
193, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(194, "HTDDCSCL1", 0,
- 194, UNIPHIER_PIN_DRV_4_8,
+ 194, UNIPHIER_PIN_DRV_1BIT,
194, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(195, "PORT241", 0,
- 195, UNIPHIER_PIN_DRV_4_8,
+ 195, UNIPHIER_PIN_DRV_1BIT,
195, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(196, "PORT242", 0,
- 196, UNIPHIER_PIN_DRV_4_8,
+ 196, UNIPHIER_PIN_DRV_1BIT,
196, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(197, "PORT243", 0,
- 197, UNIPHIER_PIN_DRV_4_8,
+ 197, UNIPHIER_PIN_DRV_1BIT,
197, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(198, "MVSYNC", 0,
- 198, UNIPHIER_PIN_DRV_4_8,
+ 198, UNIPHIER_PIN_DRV_1BIT,
198, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(199, "SPISYNC0", UNIPHIER_PIN_IECTRL_NONE,
- 199, UNIPHIER_PIN_DRV_4_8,
+ 199, UNIPHIER_PIN_DRV_1BIT,
199, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(200, "SPISCLK0", UNIPHIER_PIN_IECTRL_NONE,
- 200, UNIPHIER_PIN_DRV_4_8,
+ 200, UNIPHIER_PIN_DRV_1BIT,
200, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(201, "SPITXD0", UNIPHIER_PIN_IECTRL_NONE,
- 201, UNIPHIER_PIN_DRV_4_8,
+ 201, UNIPHIER_PIN_DRV_1BIT,
201, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(202, "SPIRXD0", UNIPHIER_PIN_IECTRL_NONE,
- 202, UNIPHIER_PIN_DRV_4_8,
+ 202, UNIPHIER_PIN_DRV_1BIT,
202, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(203, "CK54EXI", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
203, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(204, "AEXCKA1", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
204, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(205, "AEXCKA2", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
205, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(206, "CK27EXI", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_8,
+ -1, UNIPHIER_PIN_DRV_FIXED8,
206, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(207, "STCDIN", 0,
- 207, UNIPHIER_PIN_DRV_4_8,
+ 207, UNIPHIER_PIN_DRV_1BIT,
207, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(208, "PHSYNI", 0,
- 208, UNIPHIER_PIN_DRV_4_8,
+ 208, UNIPHIER_PIN_DRV_1BIT,
208, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(209, "PVSYNI", 0,
- 209, UNIPHIER_PIN_DRV_4_8,
+ 209, UNIPHIER_PIN_DRV_1BIT,
209, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(210, "MVSYN", UNIPHIER_PIN_IECTRL_NONE,
- 210, UNIPHIER_PIN_DRV_4_8,
+ 210, UNIPHIER_PIN_DRV_1BIT,
210, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(211, "STCV", UNIPHIER_PIN_IECTRL_NONE,
- 211, UNIPHIER_PIN_DRV_4_8,
+ 211, UNIPHIER_PIN_DRV_1BIT,
211, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(212, "PORT262", UNIPHIER_PIN_IECTRL_NONE,
- 212, UNIPHIER_PIN_DRV_4_8,
+ 212, UNIPHIER_PIN_DRV_1BIT,
212, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(213, "USB0VBUS_IRQ", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
213, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(214, "USB1VBUS_IRQ", UNIPHIER_PIN_IECTRL_NONE,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
214, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(215, "PORT265", UNIPHIER_PIN_IECTRL_NONE,
- 215, UNIPHIER_PIN_DRV_4_8,
+ 215, UNIPHIER_PIN_DRV_1BIT,
215, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(216, "CK25O", 0,
- 216, UNIPHIER_PIN_DRV_4_8,
+ 216, UNIPHIER_PIN_DRV_1BIT,
216, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(217, "TXD0", 0,
- 217, UNIPHIER_PIN_DRV_4_8,
+ 217, UNIPHIER_PIN_DRV_1BIT,
217, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(218, "RXD0", 0,
- 218, UNIPHIER_PIN_DRV_4_8,
+ 218, UNIPHIER_PIN_DRV_1BIT,
218, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(219, "TXD3", 0,
- 219, UNIPHIER_PIN_DRV_4_8,
+ 219, UNIPHIER_PIN_DRV_1BIT,
219, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(220, "RXD3", 0,
- 220, UNIPHIER_PIN_DRV_4_8,
+ 220, UNIPHIER_PIN_DRV_1BIT,
220, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(221, "PORT273", 0,
- 221, UNIPHIER_PIN_DRV_4_8,
+ 221, UNIPHIER_PIN_DRV_1BIT,
221, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(222, "STCDOUTC", 0,
- 222, UNIPHIER_PIN_DRV_4_8,
+ 222, UNIPHIER_PIN_DRV_1BIT,
222, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(223, "PORT274", 0,
- 223, UNIPHIER_PIN_DRV_4_8,
+ 223, UNIPHIER_PIN_DRV_1BIT,
223, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(224, "PORT275", 0,
- 224, UNIPHIER_PIN_DRV_4_8,
+ 224, UNIPHIER_PIN_DRV_1BIT,
224, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(225, "PORT276", 0,
- 225, UNIPHIER_PIN_DRV_4_8,
+ 225, UNIPHIER_PIN_DRV_1BIT,
225, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(226, "PORT277", 0,
- 226, UNIPHIER_PIN_DRV_4_8,
+ 226, UNIPHIER_PIN_DRV_1BIT,
226, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(227, "PORT280", 0,
- 227, UNIPHIER_PIN_DRV_4_8,
+ 227, UNIPHIER_PIN_DRV_1BIT,
227, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(228, "PORT281", 0,
- 228, UNIPHIER_PIN_DRV_4_8,
+ 228, UNIPHIER_PIN_DRV_1BIT,
228, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(229, "PORT282", 0,
- 229, UNIPHIER_PIN_DRV_4_8,
+ 229, UNIPHIER_PIN_DRV_1BIT,
229, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(230, "PORT283", 0,
- 230, UNIPHIER_PIN_DRV_4_8,
+ 230, UNIPHIER_PIN_DRV_1BIT,
230, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(231, "PORT284", 0,
- 231, UNIPHIER_PIN_DRV_4_8,
+ 231, UNIPHIER_PIN_DRV_1BIT,
231, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(232, "PORT285", 0,
- 232, UNIPHIER_PIN_DRV_4_8,
+ 232, UNIPHIER_PIN_DRV_1BIT,
232, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(233, "T0HPD", 0,
- 233, UNIPHIER_PIN_DRV_4_8,
+ 233, UNIPHIER_PIN_DRV_1BIT,
233, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(234, "T1HPD", 0,
- 234, UNIPHIER_PIN_DRV_4_8,
+ 234, UNIPHIER_PIN_DRV_1BIT,
234, UNIPHIER_PIN_PULL_DOWN),
};
static const unsigned emmc_pins[] = {36, 37, 38, 39, 40, 41, 42};
-static const unsigned emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9};
+static const int emmc_muxvals[] = {9, 9, 9, 9, 9, 9, 9};
static const unsigned emmc_dat8_pins[] = {43, 44, 45, 46};
-static const unsigned emmc_dat8_muxvals[] = {9, 9, 9, 9};
+static const int emmc_dat8_muxvals[] = {9, 9, 9, 9};
+static const unsigned ether_mii_pins[] = {143, 144, 145, 146, 147, 148, 149,
+ 150, 151, 152, 153, 154, 155, 156,
+ 158, 159, 199, 200, 201, 202};
+static const int ether_mii_muxvals[] = {8, 8, 8, 8, 10, 10, 10, 10, 10, 10, 10,
+ 10, 10, 10, 10, 10, 12, 12, 12, 12};
+static const unsigned ether_rgmii_pins[] = {143, 144, 145, 146, 147, 148, 149,
+ 150, 151, 152, 153, 154, 155, 156,
+ 157, 158};
+static const int ether_rgmii_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8};
+static const unsigned ether_rmii_pins[] = {143, 144, 145, 146, 147, 148, 149,
+ 150, 152, 154, 155, 158};
+static const int ether_rmii_muxvals[] = {8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9};
static const unsigned i2c0_pins[] = {109, 110};
-static const unsigned i2c0_muxvals[] = {8, 8};
+static const int i2c0_muxvals[] = {8, 8};
static const unsigned i2c1_pins[] = {111, 112};
-static const unsigned i2c1_muxvals[] = {8, 8};
+static const int i2c1_muxvals[] = {8, 8};
static const unsigned i2c2_pins[] = {171, 172};
-static const unsigned i2c2_muxvals[] = {8, 8};
+static const int i2c2_muxvals[] = {8, 8};
static const unsigned i2c3_pins[] = {159, 160};
-static const unsigned i2c3_muxvals[] = {8, 8};
+static const int i2c3_muxvals[] = {8, 8};
static const unsigned i2c5_pins[] = {183, 184};
-static const unsigned i2c5_muxvals[] = {11, 11};
+static const int i2c5_muxvals[] = {11, 11};
static const unsigned i2c6_pins[] = {185, 186};
-static const unsigned i2c6_muxvals[] = {11, 11};
+static const int i2c6_muxvals[] = {11, 11};
static const unsigned nand_pins[] = {30, 31, 32, 33, 34, 35, 36, 39, 40, 41,
42, 43, 44, 45, 46};
-static const unsigned nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
- 8, 8};
+static const int nand_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8};
static const unsigned nand_cs1_pins[] = {37, 38};
-static const unsigned nand_cs1_muxvals[] = {8, 8};
+static const int nand_cs1_muxvals[] = {8, 8};
static const unsigned sd_pins[] = {47, 48, 49, 50, 51, 52, 53, 54, 55};
-static const unsigned sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8};
+static const int sd_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8};
+static const unsigned system_bus_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
+ 11, 12, 13};
+static const int system_bus_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8};
+static const unsigned system_bus_cs1_pins[] = {14};
+static const int system_bus_cs1_muxvals[] = {8};
static const unsigned uart0_pins[] = {217, 218};
-static const unsigned uart0_muxvals[] = {8, 8};
+static const int uart0_muxvals[] = {8, 8};
static const unsigned uart0b_pins[] = {179, 180};
-static const unsigned uart0b_muxvals[] = {10, 10};
+static const int uart0b_muxvals[] = {10, 10};
static const unsigned uart1_pins[] = {115, 116};
-static const unsigned uart1_muxvals[] = {8, 8};
+static const int uart1_muxvals[] = {8, 8};
static const unsigned uart2_pins[] = {113, 114};
-static const unsigned uart2_muxvals[] = {8, 8};
+static const int uart2_muxvals[] = {8, 8};
static const unsigned uart3_pins[] = {219, 220};
-static const unsigned uart3_muxvals[] = {8, 8};
+static const int uart3_muxvals[] = {8, 8};
static const unsigned uart3b_pins[] = {181, 182};
-static const unsigned uart3b_muxvals[] = {10, 10};
+static const int uart3b_muxvals[] = {10, 10};
static const unsigned usb0_pins[] = {56, 57};
-static const unsigned usb0_muxvals[] = {8, 8};
+static const int usb0_muxvals[] = {8, 8};
static const unsigned usb1_pins[] = {58, 59};
-static const unsigned usb1_muxvals[] = {8, 8};
+static const int usb1_muxvals[] = {8, 8};
static const unsigned usb2_pins[] = {60, 61};
-static const unsigned usb2_muxvals[] = {8, 8};
+static const int usb2_muxvals[] = {8, 8};
static const unsigned usb3_pins[] = {62, 63};
-static const unsigned usb3_muxvals[] = {8, 8};
+static const int usb3_muxvals[] = {8, 8};
static const unsigned port_range0_pins[] = {
127, 128, 129, 130, 131, 132, 133, 134, /* PORT0x */
135, 136, 137, 138, 139, 140, 141, 142, /* PORT1x */
@@ -786,7 +802,7 @@ static const unsigned port_range0_pins[] = {
61, 62, 63, 64, 65, 66, 67, 68, /* PORT9x */
69, 70, 71, 76, 77, 78, 79, 80, /* PORT10x */
};
-static const unsigned port_range0_muxvals[] = {
+static const int port_range0_muxvals[] = {
15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
@@ -818,7 +834,7 @@ static const unsigned port_range1_pins[] = {
218, 219, 220, 221, 223, 224, 225, 226, /* PORT27x */
227, 228, 229, 230, 231, 232, 233, 234, /* PORT28x */
};
-static const unsigned port_range1_muxvals[] = {
+static const int port_range1_muxvals[] = {
15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */
15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */
15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
@@ -842,15 +858,18 @@ static const unsigned xirq_pins[] = {
126, 72, 73, 92, 177, 93, 94, 176, /* XIRQ8-15 */
74, 91, 27, 28, 29, 75, 20, 26, /* XIRQ16-23 */
};
-static const unsigned xirq_muxvals[] = {
+static const int xirq_muxvals[] = {
14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ0-7 */
14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ8-15 */
14, 14, 14, 14, 14, 14, 14, 14, /* XIRQ16-23 */
};
-static const struct uniphier_pinctrl_group proxstream2_groups[] = {
+static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = {
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(ether_mii),
+ UNIPHIER_PINCTRL_GROUP(ether_rgmii),
+ UNIPHIER_PINCTRL_GROUP(ether_rmii),
UNIPHIER_PINCTRL_GROUP(i2c0),
UNIPHIER_PINCTRL_GROUP(i2c1),
UNIPHIER_PINCTRL_GROUP(i2c2),
@@ -860,6 +879,8 @@ static const struct uniphier_pinctrl_group proxstream2_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart0b),
UNIPHIER_PINCTRL_GROUP(uart1),
@@ -1124,6 +1145,9 @@ static const struct uniphier_pinctrl_group proxstream2_groups[] = {
};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
+static const char * const ether_mii_groups[] = {"ether_mii"};
+static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
+static const char * const ether_rmii_groups[] = {"ether_rmii"};
static const char * const i2c0_groups[] = {"i2c0"};
static const char * const i2c1_groups[] = {"i2c1"};
static const char * const i2c2_groups[] = {"i2c2"};
@@ -1132,6 +1156,8 @@ static const char * const i2c5_groups[] = {"i2c5"};
static const char * const i2c6_groups[] = {"i2c6"};
static const char * const nand_groups[] = {"nand", "nand_cs1"};
static const char * const sd_groups[] = {"sd"};
+static const char * const system_bus_groups[] = {"system_bus",
+ "system_bus_cs1"};
static const char * const uart0_groups[] = {"uart0", "uart0b"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
@@ -1208,8 +1234,11 @@ static const char * const xirq_groups[] = {
"xirq20", "xirq21", "xirq22", "xirq23",
};
-static const struct uniphier_pinmux_function proxstream2_functions[] = {
+static const struct uniphier_pinmux_function uniphier_pxs2_functions[] = {
UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(ether_mii),
+ UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
+ UNIPHIER_PINMUX_FUNCTION(ether_rmii),
UNIPHIER_PINMUX_FUNCTION(i2c0),
UNIPHIER_PINMUX_FUNCTION(i2c1),
UNIPHIER_PINMUX_FUNCTION(i2c2),
@@ -1218,6 +1247,7 @@ static const struct uniphier_pinmux_function proxstream2_functions[] = {
UNIPHIER_PINMUX_FUNCTION(i2c6),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION(uart0),
UNIPHIER_PINMUX_FUNCTION(uart1),
UNIPHIER_PINMUX_FUNCTION(uart2),
@@ -1230,43 +1260,36 @@ static const struct uniphier_pinmux_function proxstream2_functions[] = {
UNIPHIER_PINMUX_FUNCTION(xirq),
};
-static struct uniphier_pinctrl_socdata proxstream2_pindata = {
- .groups = proxstream2_groups,
- .groups_count = ARRAY_SIZE(proxstream2_groups),
- .functions = proxstream2_functions,
- .functions_count = ARRAY_SIZE(proxstream2_functions),
- .mux_bits = 8,
- .reg_stride = 4,
- .load_pinctrl = false,
-};
-
-static struct pinctrl_desc proxstream2_pinctrl_desc = {
- .name = DRIVER_NAME,
- .pins = proxstream2_pins,
- .npins = ARRAY_SIZE(proxstream2_pins),
- .owner = THIS_MODULE,
+static struct uniphier_pinctrl_socdata uniphier_pxs2_pindata = {
+ .pins = uniphier_pxs2_pins,
+ .npins = ARRAY_SIZE(uniphier_pxs2_pins),
+ .groups = uniphier_pxs2_groups,
+ .groups_count = ARRAY_SIZE(uniphier_pxs2_groups),
+ .functions = uniphier_pxs2_functions,
+ .functions_count = ARRAY_SIZE(uniphier_pxs2_functions),
+ .caps = 0,
};
-static int proxstream2_pinctrl_probe(struct platform_device *pdev)
+static int uniphier_pxs2_pinctrl_probe(struct platform_device *pdev)
{
- return uniphier_pinctrl_probe(pdev, &proxstream2_pinctrl_desc,
- &proxstream2_pindata);
+ return uniphier_pinctrl_probe(pdev, &uniphier_pxs2_pindata);
}
-static const struct of_device_id proxstream2_pinctrl_match[] = {
+static const struct of_device_id uniphier_pxs2_pinctrl_match[] = {
+ { .compatible = "socionext,uniphier-pxs2-pinctrl" },
{ .compatible = "socionext,proxstream2-pinctrl" },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, proxstream2_pinctrl_match);
+MODULE_DEVICE_TABLE(of, uniphier_pxs2_pinctrl_match);
-static struct platform_driver proxstream2_pinctrl_driver = {
- .probe = proxstream2_pinctrl_probe,
+static struct platform_driver uniphier_pxs2_pinctrl_driver = {
+ .probe = uniphier_pxs2_pinctrl_probe,
.driver = {
- .name = DRIVER_NAME,
- .of_match_table = proxstream2_pinctrl_match,
+ .name = "uniphier-pxs2-pinctrl",
+ .of_match_table = uniphier_pxs2_pinctrl_match,
},
};
-module_platform_driver(proxstream2_pinctrl_driver);
+module_platform_driver(uniphier_pxs2_pinctrl_driver);
MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
MODULE_DESCRIPTION("UniPhier ProXstream2 pinctrl driver");
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
index ceb7a9899bde..da689d880f46 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c
@@ -19,453 +19,518 @@
#include "pinctrl-uniphier.h"
-#define DRIVER_NAME "ph1-sld8-pinctrl"
-
-static const struct pinctrl_pin_desc ph1_sld8_pins[] = {
+static const struct pinctrl_pin_desc uniphier_sld8_pins[] = {
UNIPHIER_PINCTRL_PIN(0, "PCA00", 0,
- 15, UNIPHIER_PIN_DRV_4_8,
+ 15, UNIPHIER_PIN_DRV_1BIT,
15, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(1, "PCA01", 0,
- 16, UNIPHIER_PIN_DRV_4_8,
+ 16, UNIPHIER_PIN_DRV_1BIT,
16, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(2, "PCA02", 0,
- 17, UNIPHIER_PIN_DRV_4_8,
+ 17, UNIPHIER_PIN_DRV_1BIT,
17, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(3, "PCA03", 0,
- 18, UNIPHIER_PIN_DRV_4_8,
+ 18, UNIPHIER_PIN_DRV_1BIT,
18, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(4, "PCA04", 0,
- 19, UNIPHIER_PIN_DRV_4_8,
+ 19, UNIPHIER_PIN_DRV_1BIT,
19, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(5, "PCA05", 0,
- 20, UNIPHIER_PIN_DRV_4_8,
+ 20, UNIPHIER_PIN_DRV_1BIT,
20, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(6, "PCA06", 0,
- 21, UNIPHIER_PIN_DRV_4_8,
+ 21, UNIPHIER_PIN_DRV_1BIT,
21, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(7, "PCA07", 0,
- 22, UNIPHIER_PIN_DRV_4_8,
+ 22, UNIPHIER_PIN_DRV_1BIT,
22, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(8, "PCA08", 0,
- 23, UNIPHIER_PIN_DRV_4_8,
+ 23, UNIPHIER_PIN_DRV_1BIT,
23, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(9, "PCA09", 0,
- 24, UNIPHIER_PIN_DRV_4_8,
+ 24, UNIPHIER_PIN_DRV_1BIT,
24, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(10, "PCA10", 0,
- 25, UNIPHIER_PIN_DRV_4_8,
+ 25, UNIPHIER_PIN_DRV_1BIT,
25, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(11, "PCA11", 0,
- 26, UNIPHIER_PIN_DRV_4_8,
+ 26, UNIPHIER_PIN_DRV_1BIT,
26, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(12, "PCA12", 0,
- 27, UNIPHIER_PIN_DRV_4_8,
+ 27, UNIPHIER_PIN_DRV_1BIT,
27, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(13, "PCA13", 0,
- 28, UNIPHIER_PIN_DRV_4_8,
+ 28, UNIPHIER_PIN_DRV_1BIT,
28, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(14, "PCA14", 0,
- 29, UNIPHIER_PIN_DRV_4_8,
+ 29, UNIPHIER_PIN_DRV_1BIT,
29, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(15, "XNFRE_GB", UNIPHIER_PIN_IECTRL_NONE,
- 30, UNIPHIER_PIN_DRV_4_8,
+ 30, UNIPHIER_PIN_DRV_1BIT,
30, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(16, "XNFWE_GB", UNIPHIER_PIN_IECTRL_NONE,
- 31, UNIPHIER_PIN_DRV_4_8,
+ 31, UNIPHIER_PIN_DRV_1BIT,
31, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(17, "NFALE_GB", UNIPHIER_PIN_IECTRL_NONE,
- 32, UNIPHIER_PIN_DRV_4_8,
+ 32, UNIPHIER_PIN_DRV_1BIT,
32, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(18, "NFCLE_GB", UNIPHIER_PIN_IECTRL_NONE,
- 33, UNIPHIER_PIN_DRV_4_8,
+ 33, UNIPHIER_PIN_DRV_1BIT,
33, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(19, "XNFWP_GB", UNIPHIER_PIN_IECTRL_NONE,
- 34, UNIPHIER_PIN_DRV_4_8,
+ 34, UNIPHIER_PIN_DRV_1BIT,
34, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(20, "XNFCE0_GB", UNIPHIER_PIN_IECTRL_NONE,
- 35, UNIPHIER_PIN_DRV_4_8,
+ 35, UNIPHIER_PIN_DRV_1BIT,
35, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(21, "NANDRYBY0_GB", UNIPHIER_PIN_IECTRL_NONE,
- 36, UNIPHIER_PIN_DRV_4_8,
+ 36, UNIPHIER_PIN_DRV_1BIT,
36, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(22, "XNFCE1_GB", UNIPHIER_PIN_IECTRL_NONE,
- 0, UNIPHIER_PIN_DRV_8_12_16_20,
+ 0, UNIPHIER_PIN_DRV_2BIT,
119, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(23, "NANDRYBY1_GB", UNIPHIER_PIN_IECTRL_NONE,
- 4, UNIPHIER_PIN_DRV_8_12_16_20,
+ 1, UNIPHIER_PIN_DRV_2BIT,
120, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(24, "NFD0_GB", UNIPHIER_PIN_IECTRL_NONE,
- 8, UNIPHIER_PIN_DRV_8_12_16_20,
+ 2, UNIPHIER_PIN_DRV_2BIT,
121, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(25, "NFD1_GB", UNIPHIER_PIN_IECTRL_NONE,
- 12, UNIPHIER_PIN_DRV_8_12_16_20,
+ 3, UNIPHIER_PIN_DRV_2BIT,
122, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(26, "NFD2_GB", UNIPHIER_PIN_IECTRL_NONE,
- 16, UNIPHIER_PIN_DRV_8_12_16_20,
+ 4, UNIPHIER_PIN_DRV_2BIT,
123, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(27, "NFD3_GB", UNIPHIER_PIN_IECTRL_NONE,
- 20, UNIPHIER_PIN_DRV_8_12_16_20,
+ 5, UNIPHIER_PIN_DRV_2BIT,
124, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(28, "NFD4_GB", UNIPHIER_PIN_IECTRL_NONE,
- 24, UNIPHIER_PIN_DRV_8_12_16_20,
+ 6, UNIPHIER_PIN_DRV_2BIT,
125, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(29, "NFD5_GB", UNIPHIER_PIN_IECTRL_NONE,
- 28, UNIPHIER_PIN_DRV_8_12_16_20,
+ 7, UNIPHIER_PIN_DRV_2BIT,
126, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(30, "NFD6_GB", UNIPHIER_PIN_IECTRL_NONE,
- 32, UNIPHIER_PIN_DRV_8_12_16_20,
+ 8, UNIPHIER_PIN_DRV_2BIT,
127, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(31, "NFD7_GB", UNIPHIER_PIN_IECTRL_NONE,
- 36, UNIPHIER_PIN_DRV_8_12_16_20,
+ 9, UNIPHIER_PIN_DRV_2BIT,
128, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(32, "SDCLK", 8,
- 40, UNIPHIER_PIN_DRV_8_12_16_20,
+ 10, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(33, "SDCMD", 8,
- 44, UNIPHIER_PIN_DRV_8_12_16_20,
+ 11, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(34, "SDDAT0", 8,
- 48, UNIPHIER_PIN_DRV_8_12_16_20,
+ 12, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(35, "SDDAT1", 8,
- 52, UNIPHIER_PIN_DRV_8_12_16_20,
+ 13, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(36, "SDDAT2", 8,
- 56, UNIPHIER_PIN_DRV_8_12_16_20,
+ 14, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(37, "SDDAT3", 8,
- 60, UNIPHIER_PIN_DRV_8_12_16_20,
+ 15, UNIPHIER_PIN_DRV_2BIT,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(38, "SDCD", 8,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
129, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(39, "SDWP", 8,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
130, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(40, "SDVOLC", 9,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
131, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(41, "USB0VBUS", 0,
- 37, UNIPHIER_PIN_DRV_4_8,
+ 37, UNIPHIER_PIN_DRV_1BIT,
37, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(42, "USB0OD", 0,
- 38, UNIPHIER_PIN_DRV_4_8,
+ 38, UNIPHIER_PIN_DRV_1BIT,
38, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(43, "USB1VBUS", 0,
- 39, UNIPHIER_PIN_DRV_4_8,
+ 39, UNIPHIER_PIN_DRV_1BIT,
39, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(44, "USB1OD", 0,
- 40, UNIPHIER_PIN_DRV_4_8,
+ 40, UNIPHIER_PIN_DRV_1BIT,
40, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(45, "PCRESET", 0,
- 41, UNIPHIER_PIN_DRV_4_8,
+ 41, UNIPHIER_PIN_DRV_1BIT,
41, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(46, "PCREG", 0,
- 42, UNIPHIER_PIN_DRV_4_8,
+ 42, UNIPHIER_PIN_DRV_1BIT,
42, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(47, "PCCE2", 0,
- 43, UNIPHIER_PIN_DRV_4_8,
+ 43, UNIPHIER_PIN_DRV_1BIT,
43, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(48, "PCVS1", 0,
- 44, UNIPHIER_PIN_DRV_4_8,
+ 44, UNIPHIER_PIN_DRV_1BIT,
44, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(49, "PCCD2", 0,
- 45, UNIPHIER_PIN_DRV_4_8,
+ 45, UNIPHIER_PIN_DRV_1BIT,
45, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(50, "PCCD1", 0,
- 46, UNIPHIER_PIN_DRV_4_8,
+ 46, UNIPHIER_PIN_DRV_1BIT,
46, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(51, "PCREADY", 0,
- 47, UNIPHIER_PIN_DRV_4_8,
+ 47, UNIPHIER_PIN_DRV_1BIT,
47, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(52, "PCDOE", 0,
- 48, UNIPHIER_PIN_DRV_4_8,
+ 48, UNIPHIER_PIN_DRV_1BIT,
48, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(53, "PCCE1", 0,
- 49, UNIPHIER_PIN_DRV_4_8,
+ 49, UNIPHIER_PIN_DRV_1BIT,
49, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(54, "PCWE", 0,
- 50, UNIPHIER_PIN_DRV_4_8,
+ 50, UNIPHIER_PIN_DRV_1BIT,
50, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(55, "PCOE", 0,
- 51, UNIPHIER_PIN_DRV_4_8,
+ 51, UNIPHIER_PIN_DRV_1BIT,
51, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(56, "PCWAIT", 0,
- 52, UNIPHIER_PIN_DRV_4_8,
+ 52, UNIPHIER_PIN_DRV_1BIT,
52, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(57, "PCIOWR", 0,
- 53, UNIPHIER_PIN_DRV_4_8,
+ 53, UNIPHIER_PIN_DRV_1BIT,
53, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(58, "PCIORD", 0,
- 54, UNIPHIER_PIN_DRV_4_8,
+ 54, UNIPHIER_PIN_DRV_1BIT,
54, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(59, "HS0DIN0", 0,
- 55, UNIPHIER_PIN_DRV_4_8,
+ 55, UNIPHIER_PIN_DRV_1BIT,
55, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(60, "HS0DIN1", 0,
- 56, UNIPHIER_PIN_DRV_4_8,
+ 56, UNIPHIER_PIN_DRV_1BIT,
56, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(61, "HS0DIN2", 0,
- 57, UNIPHIER_PIN_DRV_4_8,
+ 57, UNIPHIER_PIN_DRV_1BIT,
57, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(62, "HS0DIN3", 0,
- 58, UNIPHIER_PIN_DRV_4_8,
+ 58, UNIPHIER_PIN_DRV_1BIT,
58, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(63, "HS0DIN4", 0,
- 59, UNIPHIER_PIN_DRV_4_8,
+ 59, UNIPHIER_PIN_DRV_1BIT,
59, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(64, "HS0DIN5", 0,
- 60, UNIPHIER_PIN_DRV_4_8,
+ 60, UNIPHIER_PIN_DRV_1BIT,
60, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(65, "HS0DIN6", 0,
- 61, UNIPHIER_PIN_DRV_4_8,
+ 61, UNIPHIER_PIN_DRV_1BIT,
61, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(66, "HS0DIN7", 0,
- 62, UNIPHIER_PIN_DRV_4_8,
+ 62, UNIPHIER_PIN_DRV_1BIT,
62, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(67, "HS0BCLKIN", 0,
- 63, UNIPHIER_PIN_DRV_4_8,
+ 63, UNIPHIER_PIN_DRV_1BIT,
63, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(68, "HS0VALIN", 0,
- 64, UNIPHIER_PIN_DRV_4_8,
+ 64, UNIPHIER_PIN_DRV_1BIT,
64, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(69, "HS0SYNCIN", 0,
- 65, UNIPHIER_PIN_DRV_4_8,
+ 65, UNIPHIER_PIN_DRV_1BIT,
65, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(70, "HSDOUT0", 0,
- 66, UNIPHIER_PIN_DRV_4_8,
+ 66, UNIPHIER_PIN_DRV_1BIT,
66, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(71, "HSDOUT1", 0,
- 67, UNIPHIER_PIN_DRV_4_8,
+ 67, UNIPHIER_PIN_DRV_1BIT,
67, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(72, "HSDOUT2", 0,
- 68, UNIPHIER_PIN_DRV_4_8,
+ 68, UNIPHIER_PIN_DRV_1BIT,
68, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(73, "HSDOUT3", 0,
- 69, UNIPHIER_PIN_DRV_4_8,
+ 69, UNIPHIER_PIN_DRV_1BIT,
69, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(74, "HSDOUT4", 0,
- 70, UNIPHIER_PIN_DRV_4_8,
+ 70, UNIPHIER_PIN_DRV_1BIT,
70, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(75, "HSDOUT5", 0,
- 71, UNIPHIER_PIN_DRV_4_8,
+ 71, UNIPHIER_PIN_DRV_1BIT,
71, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(76, "HSDOUT6", 0,
- 72, UNIPHIER_PIN_DRV_4_8,
+ 72, UNIPHIER_PIN_DRV_1BIT,
72, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(77, "HSDOUT7", 0,
- 73, UNIPHIER_PIN_DRV_4_8,
+ 73, UNIPHIER_PIN_DRV_1BIT,
73, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(78, "HSBCLKOUT", 0,
- 74, UNIPHIER_PIN_DRV_4_8,
+ 74, UNIPHIER_PIN_DRV_1BIT,
74, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(79, "HSVALOUT", 0,
- 75, UNIPHIER_PIN_DRV_4_8,
+ 75, UNIPHIER_PIN_DRV_1BIT,
75, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(80, "HSSYNCOUT", 0,
- 76, UNIPHIER_PIN_DRV_4_8,
+ 76, UNIPHIER_PIN_DRV_1BIT,
76, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(81, "HS1DIN0", 0,
- 77, UNIPHIER_PIN_DRV_4_8,
+ 77, UNIPHIER_PIN_DRV_1BIT,
77, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(82, "HS1DIN1", 0,
- 78, UNIPHIER_PIN_DRV_4_8,
+ 78, UNIPHIER_PIN_DRV_1BIT,
78, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(83, "HS1DIN2", 0,
- 79, UNIPHIER_PIN_DRV_4_8,
+ 79, UNIPHIER_PIN_DRV_1BIT,
79, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(84, "HS1DIN3", 0,
- 80, UNIPHIER_PIN_DRV_4_8,
+ 80, UNIPHIER_PIN_DRV_1BIT,
80, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(85, "HS1DIN4", 0,
- 81, UNIPHIER_PIN_DRV_4_8,
+ 81, UNIPHIER_PIN_DRV_1BIT,
81, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(86, "HS1DIN5", 0,
- 82, UNIPHIER_PIN_DRV_4_8,
+ 82, UNIPHIER_PIN_DRV_1BIT,
82, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(87, "HS1DIN6", 0,
- 83, UNIPHIER_PIN_DRV_4_8,
+ 83, UNIPHIER_PIN_DRV_1BIT,
83, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(88, "HS1DIN7", 0,
- 84, UNIPHIER_PIN_DRV_4_8,
+ 84, UNIPHIER_PIN_DRV_1BIT,
84, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(89, "HS1BCLKIN", 0,
- 85, UNIPHIER_PIN_DRV_4_8,
+ 85, UNIPHIER_PIN_DRV_1BIT,
85, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(90, "HS1VALIN", 0,
- 86, UNIPHIER_PIN_DRV_4_8,
+ 86, UNIPHIER_PIN_DRV_1BIT,
86, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(91, "HS1SYNCIN", 0,
- 87, UNIPHIER_PIN_DRV_4_8,
+ 87, UNIPHIER_PIN_DRV_1BIT,
87, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(92, "AGCI", 3,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
132, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(93, "AGCR", 4,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
133, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(94, "AGCBS", 5,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
134, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(95, "IECOUT", 0,
- 88, UNIPHIER_PIN_DRV_4_8,
+ 88, UNIPHIER_PIN_DRV_1BIT,
88, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(96, "ASMCK", 0,
- 89, UNIPHIER_PIN_DRV_4_8,
+ 89, UNIPHIER_PIN_DRV_1BIT,
89, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(97, "ABCKO", UNIPHIER_PIN_IECTRL_NONE,
- 90, UNIPHIER_PIN_DRV_4_8,
+ 90, UNIPHIER_PIN_DRV_1BIT,
90, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(98, "ALRCKO", UNIPHIER_PIN_IECTRL_NONE,
- 91, UNIPHIER_PIN_DRV_4_8,
+ 91, UNIPHIER_PIN_DRV_1BIT,
91, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(99, "ASDOUT0", UNIPHIER_PIN_IECTRL_NONE,
- 92, UNIPHIER_PIN_DRV_4_8,
+ 92, UNIPHIER_PIN_DRV_1BIT,
92, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(100, "ASDOUT1", UNIPHIER_PIN_IECTRL_NONE,
- 93, UNIPHIER_PIN_DRV_4_8,
+ 93, UNIPHIER_PIN_DRV_1BIT,
93, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(101, "ARCOUT", 0,
- 94, UNIPHIER_PIN_DRV_4_8,
+ 94, UNIPHIER_PIN_DRV_1BIT,
94, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(102, "SDA0", 10,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(103, "SCL0", 10,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(104, "SDA1", 11,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(105, "SCL1", 11,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(106, "DMDSDA0", 12,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(107, "DMDSCL0", 12,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(108, "DMDSDA1", 13,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(109, "DMDSCL1", 13,
- -1, UNIPHIER_PIN_DRV_FIXED_4,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(110, "SBO0", UNIPHIER_PIN_IECTRL_NONE,
- 95, UNIPHIER_PIN_DRV_4_8,
+ 95, UNIPHIER_PIN_DRV_1BIT,
95, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(111, "SBI0", UNIPHIER_PIN_IECTRL_NONE,
- 96, UNIPHIER_PIN_DRV_4_8,
+ 96, UNIPHIER_PIN_DRV_1BIT,
96, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(112, "SBO1", 0,
- 97, UNIPHIER_PIN_DRV_4_8,
+ 97, UNIPHIER_PIN_DRV_1BIT,
97, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(113, "SBI1", 0,
- 98, UNIPHIER_PIN_DRV_4_8,
+ 98, UNIPHIER_PIN_DRV_1BIT,
98, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(114, "TXD1", 0,
- 99, UNIPHIER_PIN_DRV_4_8,
+ 99, UNIPHIER_PIN_DRV_1BIT,
99, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(115, "RXD1", 0,
- 100, UNIPHIER_PIN_DRV_4_8,
+ 100, UNIPHIER_PIN_DRV_1BIT,
100, UNIPHIER_PIN_PULL_UP),
UNIPHIER_PINCTRL_PIN(116, "HIN", 1,
- -1, UNIPHIER_PIN_DRV_FIXED_5,
+ -1, UNIPHIER_PIN_DRV_FIXED5,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(117, "VIN", 2,
- -1, UNIPHIER_PIN_DRV_FIXED_5,
+ -1, UNIPHIER_PIN_DRV_FIXED5,
-1, UNIPHIER_PIN_PULL_NONE),
UNIPHIER_PINCTRL_PIN(118, "TCON0", 0,
- 101, UNIPHIER_PIN_DRV_4_8,
+ 101, UNIPHIER_PIN_DRV_1BIT,
101, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(119, "TCON1", 0,
- 102, UNIPHIER_PIN_DRV_4_8,
+ 102, UNIPHIER_PIN_DRV_1BIT,
102, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(120, "TCON2", 0,
- 103, UNIPHIER_PIN_DRV_4_8,
+ 103, UNIPHIER_PIN_DRV_1BIT,
103, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(121, "TCON3", 0,
- 104, UNIPHIER_PIN_DRV_4_8,
+ 104, UNIPHIER_PIN_DRV_1BIT,
104, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(122, "TCON4", 0,
- 105, UNIPHIER_PIN_DRV_4_8,
+ 105, UNIPHIER_PIN_DRV_1BIT,
105, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(123, "TCON5", 0,
- 106, UNIPHIER_PIN_DRV_4_8,
+ 106, UNIPHIER_PIN_DRV_1BIT,
106, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(124, "TCON6", 0,
- 107, UNIPHIER_PIN_DRV_4_8,
+ 107, UNIPHIER_PIN_DRV_1BIT,
107, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(125, "TCON7", 0,
- 108, UNIPHIER_PIN_DRV_4_8,
+ 108, UNIPHIER_PIN_DRV_1BIT,
108, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(126, "TCON8", 0,
- 109, UNIPHIER_PIN_DRV_4_8,
+ 109, UNIPHIER_PIN_DRV_1BIT,
109, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(127, "PWMA", 0,
- 110, UNIPHIER_PIN_DRV_4_8,
+ 110, UNIPHIER_PIN_DRV_1BIT,
110, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(128, "XIRQ0", 0,
- 111, UNIPHIER_PIN_DRV_4_8,
+ 111, UNIPHIER_PIN_DRV_1BIT,
111, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(129, "XIRQ1", 0,
- 112, UNIPHIER_PIN_DRV_4_8,
+ 112, UNIPHIER_PIN_DRV_1BIT,
112, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(130, "XIRQ2", 0,
- 113, UNIPHIER_PIN_DRV_4_8,
+ 113, UNIPHIER_PIN_DRV_1BIT,
113, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(131, "XIRQ3", 0,
- 114, UNIPHIER_PIN_DRV_4_8,
+ 114, UNIPHIER_PIN_DRV_1BIT,
114, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(132, "XIRQ4", 0,
- 115, UNIPHIER_PIN_DRV_4_8,
+ 115, UNIPHIER_PIN_DRV_1BIT,
115, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(133, "XIRQ5", 0,
- 116, UNIPHIER_PIN_DRV_4_8,
+ 116, UNIPHIER_PIN_DRV_1BIT,
116, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(134, "XIRQ6", 0,
- 117, UNIPHIER_PIN_DRV_4_8,
+ 117, UNIPHIER_PIN_DRV_1BIT,
117, UNIPHIER_PIN_PULL_DOWN),
UNIPHIER_PINCTRL_PIN(135, "XIRQ7", 0,
- 118, UNIPHIER_PIN_DRV_4_8,
+ 118, UNIPHIER_PIN_DRV_1BIT,
118, UNIPHIER_PIN_PULL_DOWN),
+ /* dedicated pins */
+ UNIPHIER_PINCTRL_PIN(136, "ED0", -1,
+ 0, UNIPHIER_PIN_DRV_1BIT,
+ 0, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(137, "ED1", -1,
+ 1, UNIPHIER_PIN_DRV_1BIT,
+ 1, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(138, "ED2", -1,
+ 2, UNIPHIER_PIN_DRV_1BIT,
+ 2, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(139, "ED3", -1,
+ 3, UNIPHIER_PIN_DRV_1BIT,
+ 3, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(140, "ED4", -1,
+ 4, UNIPHIER_PIN_DRV_1BIT,
+ 4, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(141, "ED5", -1,
+ 5, UNIPHIER_PIN_DRV_1BIT,
+ 5, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(142, "ED6", -1,
+ 6, UNIPHIER_PIN_DRV_1BIT,
+ 6, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(143, "ED7", -1,
+ 7, UNIPHIER_PIN_DRV_1BIT,
+ 7, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(144, "XERWE0", -1,
+ 8, UNIPHIER_PIN_DRV_1BIT,
+ 8, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(145, "XERWE1", -1,
+ 9, UNIPHIER_PIN_DRV_1BIT,
+ 9, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(146, "ERXW", -1,
+ 10, UNIPHIER_PIN_DRV_1BIT,
+ 10, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(147, "ES0", -1,
+ 11, UNIPHIER_PIN_DRV_1BIT,
+ 11, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(148, "ES1", -1,
+ 12, UNIPHIER_PIN_DRV_1BIT,
+ 12, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(149, "ES2", -1,
+ 13, UNIPHIER_PIN_DRV_1BIT,
+ 13, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(150, "XECS1", -1,
+ 14, UNIPHIER_PIN_DRV_1BIT,
+ 14, UNIPHIER_PIN_PULL_DOWN),
};
static const unsigned emmc_pins[] = {21, 22, 23, 24, 25, 26, 27};
-static const unsigned emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const int emmc_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
static const unsigned emmc_dat8_pins[] = {28, 29, 30, 31};
-static const unsigned emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const int emmc_dat8_muxvals[] = {1, 1, 1, 1};
+static const unsigned ether_mii_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 14,
+ 61, 63, 64, 65, 66, 67, 68};
+static const int ether_mii_muxvals[] = {13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
+ 13, 13, 27, 27, 27, 27, 27, 27, 27};
+static const unsigned ether_rmii_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 13,
+ 14};
+static const int ether_rmii_muxvals[] = {13, 13, 13, 13, 13, 13, 13, 13, 13,
+ 13, 13, 13};
static const unsigned i2c0_pins[] = {102, 103};
-static const unsigned i2c0_muxvals[] = {0, 0};
+static const int i2c0_muxvals[] = {0, 0};
static const unsigned i2c1_pins[] = {104, 105};
-static const unsigned i2c1_muxvals[] = {0, 0};
+static const int i2c1_muxvals[] = {0, 0};
static const unsigned i2c2_pins[] = {108, 109};
-static const unsigned i2c2_muxvals[] = {2, 2};
+static const int i2c2_muxvals[] = {2, 2};
static const unsigned i2c3_pins[] = {108, 109};
-static const unsigned i2c3_muxvals[] = {3, 3};
+static const int i2c3_muxvals[] = {3, 3};
static const unsigned nand_pins[] = {15, 16, 17, 18, 19, 20, 21, 24, 25, 26,
27, 28, 29, 30, 31};
-static const unsigned nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0};
+static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static const unsigned nand_cs1_pins[] = {22, 23};
-static const unsigned nand_cs1_muxvals[] = {0, 0};
+static const int nand_cs1_muxvals[] = {0, 0};
static const unsigned sd_pins[] = {32, 33, 34, 35, 36, 37, 38, 39, 40};
-static const unsigned sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned system_bus_pins[] = {136, 137, 138, 139, 140, 141, 142,
+ 143, 144, 145, 146, 147, 148, 149};
+static const int system_bus_muxvals[] = {-1, -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1};
+static const unsigned system_bus_cs1_pins[] = {150};
+static const int system_bus_cs1_muxvals[] = {-1};
+static const unsigned system_bus_cs2_pins[] = {10};
+static const int system_bus_cs2_muxvals[] = {1};
+static const unsigned system_bus_cs3_pins[] = {11};
+static const int system_bus_cs3_muxvals[] = {1};
+static const unsigned system_bus_cs4_pins[] = {12};
+static const int system_bus_cs4_muxvals[] = {1};
+static const unsigned system_bus_cs5_pins[] = {13};
+static const int system_bus_cs5_muxvals[] = {1};
static const unsigned uart0_pins[] = {70, 71};
-static const unsigned uart0_muxvals[] = {3, 3};
+static const int uart0_muxvals[] = {3, 3};
static const unsigned uart1_pins[] = {114, 115};
-static const unsigned uart1_muxvals[] = {0, 0};
+static const int uart1_muxvals[] = {0, 0};
static const unsigned uart2_pins[] = {112, 113};
-static const unsigned uart2_muxvals[] = {1, 1};
+static const int uart2_muxvals[] = {1, 1};
static const unsigned uart3_pins[] = {110, 111};
-static const unsigned uart3_muxvals[] = {1, 1};
+static const int uart3_muxvals[] = {1, 1};
static const unsigned usb0_pins[] = {41, 42};
-static const unsigned usb0_muxvals[] = {0, 0};
+static const int usb0_muxvals[] = {0, 0};
static const unsigned usb1_pins[] = {43, 44};
-static const unsigned usb1_muxvals[] = {0, 0};
+static const int usb1_muxvals[] = {0, 0};
static const unsigned usb2_pins[] = {114, 115};
-static const unsigned usb2_muxvals[] = {1, 1};
+static const int usb2_muxvals[] = {1, 1};
static const unsigned port_range0_pins[] = {
0, 1, 2, 3, 4, 5, 6, 7, /* PORT0x */
8, 9, 10, 11, 12, 13, 14, 15, /* PORT1x */
@@ -481,7 +546,7 @@ static const unsigned port_range0_pins[] = {
48, 49, 46, 45, 123, 124, 125, 126, /* PORT11x */
47, 127, 20, 56, 22, /* PORT120-124 */
};
-static const unsigned port_range0_muxvals[] = {
+static const int port_range0_muxvals[] = {
15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */
15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */
15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */
@@ -499,39 +564,41 @@ static const unsigned port_range0_muxvals[] = {
static const unsigned port_range1_pins[] = {
116, 117, /* PORT130-131 */
};
-static const unsigned port_range1_muxvals[] = {
+static const int port_range1_muxvals[] = {
15, 15, /* PORT130-131 */
};
static const unsigned port_range2_pins[] = {
102, 103, 104, 105, 106, 107, 108, 109, /* PORT14x */
};
-static const unsigned port_range2_muxvals[] = {
+static const int port_range2_muxvals[] = {
15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */
};
static const unsigned port_range3_pins[] = {
23, /* PORT166 */
};
-static const unsigned port_range3_muxvals[] = {
+static const int port_range3_muxvals[] = {
15, /* PORT166 */
};
static const unsigned xirq_range0_pins[] = {
128, 129, 130, 131, 132, 133, 134, 135, /* XIRQ0-7 */
82, 87, 88, 50, 51, /* XIRQ8-12 */
};
-static const unsigned xirq_range0_muxvals[] = {
+static const int xirq_range0_muxvals[] = {
0, 0, 0, 0, 0, 0, 0, 0, /* XIRQ0-7 */
14, 14, 14, 14, 14, /* XIRQ8-12 */
};
static const unsigned xirq_range1_pins[] = {
52, 58, /* XIRQ14-15 */
};
-static const unsigned xirq_range1_muxvals[] = {
+static const int xirq_range1_muxvals[] = {
14, 14, /* XIRQ14-15 */
};
-static const struct uniphier_pinctrl_group ph1_sld8_groups[] = {
+static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = {
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(ether_mii),
+ UNIPHIER_PINCTRL_GROUP(ether_rmii),
UNIPHIER_PINCTRL_GROUP(i2c0),
UNIPHIER_PINCTRL_GROUP(i2c1),
UNIPHIER_PINCTRL_GROUP(i2c2),
@@ -539,6 +606,12 @@ static const struct uniphier_pinctrl_group ph1_sld8_groups[] = {
UNIPHIER_PINCTRL_GROUP(nand),
UNIPHIER_PINCTRL_GROUP(nand_cs1),
UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(system_bus),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
+ UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
UNIPHIER_PINCTRL_GROUP(uart0),
UNIPHIER_PINCTRL_GROUP(uart1),
UNIPHIER_PINCTRL_GROUP(uart2),
@@ -682,12 +755,20 @@ static const struct uniphier_pinctrl_group ph1_sld8_groups[] = {
};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
+static const char * const ether_mii_groups[] = {"ether_mii"};
+static const char * const ether_rmii_groups[] = {"ether_rmii"};
static const char * const i2c0_groups[] = {"i2c0"};
static const char * const i2c1_groups[] = {"i2c1"};
static const char * const i2c2_groups[] = {"i2c2"};
static const char * const i2c3_groups[] = {"i2c3"};
static const char * const nand_groups[] = {"nand", "nand_cs1"};
static const char * const sd_groups[] = {"sd"};
+static const char * const system_bus_groups[] = {"system_bus",
+ "system_bus_cs1",
+ "system_bus_cs2",
+ "system_bus_cs3",
+ "system_bus_cs4",
+ "system_bus_cs5"};
static const char * const uart0_groups[] = {"uart0"};
static const char * const uart1_groups[] = {"uart1"};
static const char * const uart2_groups[] = {"uart2"};
@@ -736,14 +817,17 @@ static const char * const xirq_groups[] = {
"xirq12", /* none*/ "xirq14", "xirq15",
};
-static const struct uniphier_pinmux_function ph1_sld8_functions[] = {
+static const struct uniphier_pinmux_function uniphier_sld8_functions[] = {
UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(ether_mii),
+ UNIPHIER_PINMUX_FUNCTION(ether_rmii),
UNIPHIER_PINMUX_FUNCTION(i2c0),
UNIPHIER_PINMUX_FUNCTION(i2c1),
UNIPHIER_PINMUX_FUNCTION(i2c2),
UNIPHIER_PINMUX_FUNCTION(i2c3),
UNIPHIER_PINMUX_FUNCTION(nand),
UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(system_bus),
UNIPHIER_PINMUX_FUNCTION(uart0),
UNIPHIER_PINMUX_FUNCTION(uart1),
UNIPHIER_PINMUX_FUNCTION(uart2),
@@ -755,43 +839,36 @@ static const struct uniphier_pinmux_function ph1_sld8_functions[] = {
UNIPHIER_PINMUX_FUNCTION(xirq),
};
-static struct uniphier_pinctrl_socdata ph1_sld8_pindata = {
- .groups = ph1_sld8_groups,
- .groups_count = ARRAY_SIZE(ph1_sld8_groups),
- .functions = ph1_sld8_functions,
- .functions_count = ARRAY_SIZE(ph1_sld8_functions),
- .mux_bits = 8,
- .reg_stride = 4,
- .load_pinctrl = false,
-};
-
-static struct pinctrl_desc ph1_sld8_pinctrl_desc = {
- .name = DRIVER_NAME,
- .pins = ph1_sld8_pins,
- .npins = ARRAY_SIZE(ph1_sld8_pins),
- .owner = THIS_MODULE,
+static struct uniphier_pinctrl_socdata uniphier_sld8_pindata = {
+ .pins = uniphier_sld8_pins,
+ .npins = ARRAY_SIZE(uniphier_sld8_pins),
+ .groups = uniphier_sld8_groups,
+ .groups_count = ARRAY_SIZE(uniphier_sld8_groups),
+ .functions = uniphier_sld8_functions,
+ .functions_count = ARRAY_SIZE(uniphier_sld8_functions),
+ .caps = 0,
};
-static int ph1_sld8_pinctrl_probe(struct platform_device *pdev)
+static int uniphier_sld8_pinctrl_probe(struct platform_device *pdev)
{
- return uniphier_pinctrl_probe(pdev, &ph1_sld8_pinctrl_desc,
- &ph1_sld8_pindata);
+ return uniphier_pinctrl_probe(pdev, &uniphier_sld8_pindata);
}
-static const struct of_device_id ph1_sld8_pinctrl_match[] = {
+static const struct of_device_id uniphier_sld8_pinctrl_match[] = {
+ { .compatible = "socionext,uniphier-sld8-pinctrl" },
{ .compatible = "socionext,ph1-sld8-pinctrl" },
{ /* sentinel */ }
};
-MODULE_DEVICE_TABLE(of, ph1_sld8_pinctrl_match);
+MODULE_DEVICE_TABLE(of, uniphier_sld8_pinctrl_match);
-static struct platform_driver ph1_sld8_pinctrl_driver = {
- .probe = ph1_sld8_pinctrl_probe,
+static struct platform_driver uniphier_sld8_pinctrl_driver = {
+ .probe = uniphier_sld8_pinctrl_probe,
.driver = {
- .name = DRIVER_NAME,
- .of_match_table = ph1_sld8_pinctrl_match,
+ .name = "uniphier-sld8-pinctrl",
+ .of_match_table = uniphier_sld8_pinctrl_match,
},
};
-module_platform_driver(ph1_sld8_pinctrl_driver);
+module_platform_driver(uniphier_sld8_pinctrl_driver);
MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
MODULE_DESCRIPTION("UniPhier PH1-sLD8 pinctrl driver");
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
index a21154f4b453..923f36cb245d 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h
@@ -15,14 +15,18 @@
#ifndef __PINCTRL_UNIPHIER_H__
#define __PINCTRL_UNIPHIER_H__
+#include <linux/bitops.h>
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/types.h>
+struct platform_device;
+
#define UNIPHIER_PINCTRL_PINMUX_BASE 0x0
#define UNIPHIER_PINCTRL_LOAD_PINMUX 0x700
#define UNIPHIER_PINCTRL_DRVCTRL_BASE 0x800
#define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x900
+#define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x980
#define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0xa00
#define UNIPHIER_PINCTRL_IECTRL 0xd00
@@ -39,16 +43,16 @@
#define UNIPHIER_PIN_DRVCTRL_MASK ((1UL << (UNIPHIER_PIN_DRVCTRL_BITS)) \
- 1)
-/* supported drive strength (mA) */
-#define UNIPHIER_PIN_DRV_STR_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \
+/* drive control type */
+#define UNIPHIER_PIN_DRV_TYPE_SHIFT ((UNIPHIER_PIN_DRVCTRL_SHIFT) + \
(UNIPHIER_PIN_DRVCTRL_BITS))
-#define UNIPHIER_PIN_DRV_STR_BITS 3
-#define UNIPHIER_PIN_DRV_STR_MASK ((1UL << (UNIPHIER_PIN_DRV_STR_BITS)) \
+#define UNIPHIER_PIN_DRV_TYPE_BITS 3
+#define UNIPHIER_PIN_DRV_TYPE_MASK ((1UL << (UNIPHIER_PIN_DRV_TYPE_BITS)) \
- 1)
/* pull-up / pull-down register number */
-#define UNIPHIER_PIN_PUPDCTRL_SHIFT ((UNIPHIER_PIN_DRV_STR_SHIFT) + \
- (UNIPHIER_PIN_DRV_STR_BITS))
+#define UNIPHIER_PIN_PUPDCTRL_SHIFT ((UNIPHIER_PIN_DRV_TYPE_SHIFT) + \
+ (UNIPHIER_PIN_DRV_TYPE_BITS))
#define UNIPHIER_PIN_PUPDCTRL_BITS 9
#define UNIPHIER_PIN_PUPDCTRL_MASK ((1UL << (UNIPHIER_PIN_PUPDCTRL_BITS))\
- 1)
@@ -66,13 +70,14 @@
#define UNIPHIER_PIN_IECTRL_NONE (UNIPHIER_PIN_IECTRL_MASK)
-/* selectable drive strength */
-enum uniphier_pin_drv_str {
- UNIPHIER_PIN_DRV_4_8, /* 2 level control: 4/8 mA */
- UNIPHIER_PIN_DRV_8_12_16_20, /* 4 level control: 8/12/16/20 mA */
- UNIPHIER_PIN_DRV_FIXED_4, /* fixed to 4mA */
- UNIPHIER_PIN_DRV_FIXED_5, /* fixed to 5mA */
- UNIPHIER_PIN_DRV_FIXED_8, /* fixed to 8mA */
+/* drive control type */
+enum uniphier_pin_drv_type {
+ UNIPHIER_PIN_DRV_1BIT, /* 2 level control: 4/8 mA */
+ UNIPHIER_PIN_DRV_2BIT, /* 4 level control: 8/12/16/20 mA */
+ UNIPHIER_PIN_DRV_3BIT, /* 8 level control: 4/5/7/9/11/12/14/16 mA */
+ UNIPHIER_PIN_DRV_FIXED4, /* fixed to 4mA */
+ UNIPHIER_PIN_DRV_FIXED5, /* fixed to 5mA */
+ UNIPHIER_PIN_DRV_FIXED8, /* fixed to 8mA */
UNIPHIER_PIN_DRV_NONE, /* no support (input only pin) */
};
@@ -89,17 +94,17 @@ enum uniphier_pin_pull_dir {
(((x) & (UNIPHIER_PIN_IECTRL_MASK)) << (UNIPHIER_PIN_IECTRL_SHIFT))
#define UNIPHIER_PIN_DRVCTRL(x) \
(((x) & (UNIPHIER_PIN_DRVCTRL_MASK)) << (UNIPHIER_PIN_DRVCTRL_SHIFT))
-#define UNIPHIER_PIN_DRV_STR(x) \
- (((x) & (UNIPHIER_PIN_DRV_STR_MASK)) << (UNIPHIER_PIN_DRV_STR_SHIFT))
+#define UNIPHIER_PIN_DRV_TYPE(x) \
+ (((x) & (UNIPHIER_PIN_DRV_TYPE_MASK)) << (UNIPHIER_PIN_DRV_TYPE_SHIFT))
#define UNIPHIER_PIN_PUPDCTRL(x) \
(((x) & (UNIPHIER_PIN_PUPDCTRL_MASK)) << (UNIPHIER_PIN_PUPDCTRL_SHIFT))
#define UNIPHIER_PIN_PULL_DIR(x) \
(((x) & (UNIPHIER_PIN_PULL_DIR_MASK)) << (UNIPHIER_PIN_PULL_DIR_SHIFT))
-#define UNIPHIER_PIN_ATTR_PACKED(iectrl, drvctrl, drv_str, pupdctrl, pull_dir)\
+#define UNIPHIER_PIN_ATTR_PACKED(iectrl, drvctrl, drv_type, pupdctrl, pull_dir)\
(UNIPHIER_PIN_IECTRL(iectrl) | \
UNIPHIER_PIN_DRVCTRL(drvctrl) | \
- UNIPHIER_PIN_DRV_STR(drv_str) | \
+ UNIPHIER_PIN_DRV_TYPE(drv_type) | \
UNIPHIER_PIN_PUPDCTRL(pupdctrl) | \
UNIPHIER_PIN_PULL_DIR(pull_dir))
@@ -115,10 +120,10 @@ static inline unsigned int uniphier_pin_get_drvctrl(void *drv_data)
UNIPHIER_PIN_DRVCTRL_MASK;
}
-static inline unsigned int uniphier_pin_get_drv_str(void *drv_data)
+static inline unsigned int uniphier_pin_get_drv_type(void *drv_data)
{
- return ((unsigned long)drv_data >> UNIPHIER_PIN_DRV_STR_SHIFT) &
- UNIPHIER_PIN_DRV_STR_MASK;
+ return ((unsigned long)drv_data >> UNIPHIER_PIN_DRV_TYPE_SHIFT) &
+ UNIPHIER_PIN_DRV_TYPE_MASK;
}
static inline unsigned int uniphier_pin_get_pupdctrl(void *drv_data)
@@ -143,7 +148,7 @@ struct uniphier_pinctrl_group {
const char *name;
const unsigned *pins;
unsigned num_pins;
- const unsigned *muxvals;
+ const int *muxvals;
enum uniphier_pinmux_gpio_range_type range_type;
};
@@ -154,13 +159,15 @@ struct uniphier_pinmux_function {
};
struct uniphier_pinctrl_socdata {
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
const struct uniphier_pinctrl_group *groups;
int groups_count;
const struct uniphier_pinmux_function *functions;
int functions_count;
- unsigned mux_bits;
- unsigned reg_stride;
- bool load_pinctrl;
+ unsigned int caps;
+#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(1)
+#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0)
};
#define UNIPHIER_PINCTRL_PIN(a, b, c, d, e, f, g) \
@@ -205,11 +212,7 @@ struct uniphier_pinctrl_socdata {
.num_groups = ARRAY_SIZE(func##_groups), \
}
-struct platform_device;
-struct pinctrl_desc;
-
int uniphier_pinctrl_probe(struct platform_device *pdev,
- struct pinctrl_desc *desc,
struct uniphier_pinctrl_socdata *socdata);
#endif /* __PINCTRL_UNIPHIER_H__ */