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| author | Dmitry Osipenko <digetx@gmail.com> | 2019-07-25 18:18:31 +0300 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-29 16:02:59 +0300 |
| commit | 496747e7d907b01bd2507d61bdd6874b987c9629 (patch) | |
| tree | 9dce7cfdd794925e1f3b209927353c53b0a735be /drivers/soc/tegra/Makefile | |
| parent | c7ccfccabb0f819eae1a191ccd94269f577e4523 (diff) | |
| download | linux-496747e7d907b01bd2507d61bdd6874b987c9629.tar.xz | |
soc/tegra: regulators: Add regulators coupler for Tegra20
Add regulators coupler for Tegra20 SoCs that performs voltage balancing
of a coupled regulators and thus provides voltage scaling functionality.
There are 3 coupled regulators on all Tegra20 SoCs: CORE, RTC and CPU.
The CORE and RTC voltages shall be in range of 170mV from each other and
they both shall be higher than the CPU voltage by at least 120mV. This
sounds like it could be handle by a generic voltage balancer, but the CORE
voltage scaling isn't implemented in any of the upstream drivers yet.
It will take quite some time and effort to hook up voltage scaling for
all of the drivers, hence we will use a custom coupler that will manage
the CPU voltage scaling for the starter.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/soc/tegra/Makefile')
| -rw-r--r-- | drivers/soc/tegra/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/soc/tegra/Makefile b/drivers/soc/tegra/Makefile index 902759fe5f4d..9f0bdd53bef8 100644 --- a/drivers/soc/tegra/Makefile +++ b/drivers/soc/tegra/Makefile @@ -5,3 +5,4 @@ obj-y += common.o obj-$(CONFIG_SOC_TEGRA_FLOWCTRL) += flowctrl.o obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o obj-$(CONFIG_SOC_TEGRA_POWERGATE_BPMP) += powergate-bpmp.o +obj-$(CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER) += regulators-tegra20.o |