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authorJarkko Nikula <jarkko.nikula@linux.intel.com>2015-10-22 16:44:42 +0300
committerMark Brown <broonie@kernel.org>2015-10-23 02:56:05 +0300
commit0e8972187971ac6c29a9e5899fa6c555c739237c (patch)
tree2067ce59b0f5ecee77427f9a3f378ede11d90489 /drivers/spi
parent3b8b6d05942ef5dd952674e7420600f762166e22 (diff)
downloadlinux-0e8972187971ac6c29a9e5899fa6c555c739237c.tar.xz
spi: pxa2xx: Save other reg_cs_ctrl bits when configuring chip select
Upcoming Intel platforms use LPSS SPI_CS_CONTROL register bits 15:12 for configuring the chip select polarities. Touch only chip select SW mode and state bits when enabling the software chip select control in order to not clear any other bits in the register. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/spi-pxa2xx.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index db9016bbd904..4dc5660d4e33 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -249,7 +249,9 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
drv_data->lpss_base = drv_data->ioaddr + config->offset;
/* Enable software chip select control */
- value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
+ value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
+ value &= ~(SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH);
+ value |= SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
/* Enable multiblock DMA transfers */