summaryrefslogtreecommitdiff
path: root/drivers/staging/goldfish
diff options
context:
space:
mode:
authorShraddha Barke <shraddha.6596@gmail.com>2016-01-21 00:08:53 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-01-29 10:56:47 +0300
commit3e2fbc7feec4426feba609b94aa89a147e02c67e (patch)
tree2ea3ade31fb994c0efcdb815bd0c4740761d1f26 /drivers/staging/goldfish
parentd62f324b0ac80c3923ebbf897735c7c24ba887b8 (diff)
downloadlinux-3e2fbc7feec4426feba609b94aa89a147e02c67e.tar.xz
Staging: goldfish: goldfish_nand: Add DMA Support using dmam_alloc_coherent
Function nand_setup_cmd_params has 2 goals- -Initialize the cmd_params field so that it can be used to send and read commands from the device. -Get a bus address for the allocated memory to transfer to the device. Replace the combination of devm_kzalloc and _pa() with dmam_alloc_coherent. Coherent mapping guarantees that the device and CPU are in sync. Signed-off-by: Shraddha Barke <shraddha.6596@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/goldfish')
-rw-r--r--drivers/staging/goldfish/goldfish_nand.c20
1 files changed, 11 insertions, 9 deletions
diff --git a/drivers/staging/goldfish/goldfish_nand.c b/drivers/staging/goldfish/goldfish_nand.c
index 623353db5a08..f223b3a5a428 100644
--- a/drivers/staging/goldfish/goldfish_nand.c
+++ b/drivers/staging/goldfish/goldfish_nand.c
@@ -27,6 +27,7 @@
#include <linux/mutex.h>
#include <linux/goldfish.h>
#include <asm/div64.h>
+#include <linux/dma-mapping.h>
#include "goldfish_nand_reg.h"
@@ -284,17 +285,18 @@ invalid_arg:
static int nand_setup_cmd_params(struct platform_device *pdev,
struct goldfish_nand *nand)
{
- u64 paddr;
+ dma_addr_t dma_handle;
unsigned char __iomem *base = nand->base;
- nand->cmd_params = devm_kzalloc(&pdev->dev,
- sizeof(struct cmd_params), GFP_KERNEL);
- if (!nand->cmd_params)
- return -1;
-
- paddr = __pa(nand->cmd_params);
- writel((u32)(paddr >> 32), base + NAND_CMD_PARAMS_ADDR_HIGH);
- writel((u32)paddr, base + NAND_CMD_PARAMS_ADDR_LOW);
+ nand->cmd_params = dmam_alloc_coherent(&pdev->dev,
+ sizeof(struct cmd_params),
+ &dma_handle, GFP_KERNEL);
+ if (!nand->cmd_params) {
+ dev_err(&pdev->dev, "allocate buffer failed\n");
+ return -ENOMEM;
+ }
+ writel((u32)((u64)dma_handle >> 32), base + NAND_CMD_PARAMS_ADDR_HIGH);
+ writel((u32)dma_handle, base + NAND_CMD_PARAMS_ADDR_LOW);
return 0;
}