diff options
| author | Gil Fine <gil.fine@intel.com> | 2022-09-29 12:49:48 +0300 |
|---|---|---|
| committer | Mika Westerberg <mika.westerberg@linux.intel.com> | 2023-06-16 09:53:28 +0300 |
| commit | 6e19d48ea0d8aeee5688e5718cf2143d281864f3 (patch) | |
| tree | d72c64c3b5923c8bdde45dd1bd0adfa2d71066e3 /drivers/thunderbolt/tb_regs.h | |
| parent | 14200a2631dd1f041201985e2a757d2d06ba2524 (diff) | |
| download | linux-6e19d48ea0d8aeee5688e5718cf2143d281864f3.tar.xz | |
thunderbolt: Enable USB4 v2 PCIe TLP/DLLP extended encapsulation
USB4 v2 spec introduces modified encapsulation of PCIe TLP and DLLP
packets. This improves the PCIe tunneled traffic usage by reducing
overhead. Enable this if both sides of the link support it.
Signed-off-by: Gil Fine <gil.fine@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'drivers/thunderbolt/tb_regs.h')
| -rw-r--r-- | drivers/thunderbolt/tb_regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h index c8e40ef09903..549cc79c7313 100644 --- a/drivers/thunderbolt/tb_regs.h +++ b/drivers/thunderbolt/tb_regs.h @@ -451,6 +451,8 @@ struct tb_regs_port_header { /* PCIe adapter registers */ #define ADP_PCIE_CS_0 0x00 #define ADP_PCIE_CS_0_PE BIT(31) +#define ADP_PCIE_CS_1 0x01 +#define ADP_PCIE_CS_1_EE BIT(0) /* USB adapter registers */ #define ADP_USB3_CS_0 0x00 |