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author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-07-04 12:07:15 +0400 |
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committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2015-02-04 13:32:05 +0300 |
commit | be40eecf8dea217a3f3b9df5c2d7235e91e25fb0 (patch) | |
tree | 8628c8250df6f76c3cba5ba209ed7f85defb133b /drivers/video/fbdev/omap2/dss/dss.h | |
parent | 6d817880cdfd0456ccf5f2b705d7078957ea09cb (diff) | |
download | linux-be40eecf8dea217a3f3b9df5c2d7235e91e25fb0.tar.xz |
OMAPDSS: Add functions for external control of PLL
Add functions which configure the control module register
CTRL_CORE_DSS_PLL_CONTROL found in DRA7xx SoCs. This register configures
whether the PLL registers are accessed internally by DSS, or externally
using OCP2SCP interface. They also configure muxes which route the PLL
output to a particular LCD overlay manager within DSS.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/video/fbdev/omap2/dss/dss.h')
-rw-r--r-- | drivers/video/fbdev/omap2/dss/dss.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/video/fbdev/omap2/dss/dss.h b/drivers/video/fbdev/omap2/dss/dss.h index 4bca36a591ca..76a6eb1da090 100644 --- a/drivers/video/fbdev/omap2/dss/dss.h +++ b/drivers/video/fbdev/omap2/dss/dss.h @@ -274,6 +274,10 @@ u32 dss_of_port_get_port_number(struct device_node *port); void dss_debug_dump_clocks(struct seq_file *s); #endif +void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable); +void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id, + enum omap_channel channel); + void dss_sdi_init(int datapairs); int dss_sdi_enable(void); void dss_sdi_disable(void); |