diff options
| author | Heiner Kallweit <hkallweit1@gmail.com> | 2024-02-14 23:18:02 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2024-02-17 21:45:06 +0300 |
| commit | b63584c86edbaf7477c3569cec331672bb7714d5 (patch) | |
| tree | 2e8d8fd4678dcc3deeaa0a32d6833b44e39a4077 /drivers | |
| parent | ef6ee3a31bdc699391f2db4eff407fdb06895809 (diff) | |
| download | linux-b63584c86edbaf7477c3569cec331672bb7714d5.tar.xz | |
net: phy: c45: add and use genphy_c45_read_eee_cap2
Add and use genphy_c45_read_eee_cap2(), complementing
genphy_c45_read_eee_cap1().
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/phy/phy-c45.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c index 46c87a903efd..5a245f0cc8b1 100644 --- a/drivers/net/phy/phy-c45.c +++ b/drivers/net/phy/phy-c45.c @@ -831,6 +831,30 @@ static int genphy_c45_read_eee_cap1(struct phy_device *phydev) } /** + * genphy_c45_read_eee_cap2 - read supported EEE link modes from register 3.21 + * @phydev: target phy_device struct + */ +static int genphy_c45_read_eee_cap2(struct phy_device *phydev) +{ + int val; + + /* IEEE 802.3-2022 45.2.3.11 EEE control and capability 2 + * (Register 3.21) + */ + val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE2); + if (val < 0) + return val; + + /* IEEE 802.3-2022 45.2.3.11 says 9 bits are reserved. */ + if (val == 0xffff) + return 0; + + mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val); + + return 0; +} + +/** * genphy_c45_read_eee_abilities - read supported EEE link modes * @phydev: target phy_device struct */ @@ -848,6 +872,13 @@ int genphy_c45_read_eee_abilities(struct phy_device *phydev) return val; } + /* Same for cap2 (3.21) */ + if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) { + val = genphy_c45_read_eee_cap2(phydev); + if (val) + return val; + } + if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, phydev->supported)) { /* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register |