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authorPaul Mundt <lethal@linux-sh.org>2007-12-10 09:50:28 +0300
committerPaul Mundt <lethal@linux-sh.org>2008-01-28 07:18:59 +0300
commitcd01204b82933754a7276838656420477f64d4b8 (patch)
treef9e3b11574bec04cda78c549cdc5c37c3c75c4a5 /include/asm-sh/auxvec.h
parentc8c0a1aba9fa8f816dc8fb477ff816a5b700f0ea (diff)
downloadlinux-cd01204b82933754a7276838656420477f64d4b8.tar.xz
sh: Encode L1/L2 cache shape in auxvt.
This adds in the L1I/L1D/L2 cache shape support to their respective entries in the ELF auxvt, based on the Alpha implementation. We use this on the userspace libc side for calculating a tightly packed SHMLBA amongst other things. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/auxvec.h')
-rw-r--r--include/asm-sh/auxvec.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/include/asm-sh/auxvec.h b/include/asm-sh/auxvec.h
index 1b6916e63e90..4069858f8131 100644
--- a/include/asm-sh/auxvec.h
+++ b/include/asm-sh/auxvec.h
@@ -15,4 +15,16 @@
#define AT_SYSINFO_EHDR 33
#endif
+/*
+ * More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the
+ * value is -1, then the cache doesn't exist. Otherwise:
+ *
+ * bit 0-3: Cache set-associativity; 0 means fully associative.
+ * bit 4-7: Log2 of cacheline size.
+ * bit 8-31: Size of the entire cache >> 8.
+ */
+#define AT_L1I_CACHESHAPE 34
+#define AT_L1D_CACHESHAPE 35
+#define AT_L2_CACHESHAPE 36
+
#endif /* __ASM_SH_AUXVEC_H */