diff options
author | Stephen Boyd <sboyd@kernel.org> | 2022-08-31 00:36:24 +0300 |
---|---|---|
committer | Stephen Boyd <sboyd@kernel.org> | 2022-08-31 00:36:24 +0300 |
commit | 37eceb69205b2a98e67c48710c1e9ad5e78f21e9 (patch) | |
tree | 3cbead10a8ca0b61a576d302fc9f2be965911de5 /include/dt-bindings/clock | |
parent | 568035b01cfb107af8d2e4bd2fb9aea22cf5b868 (diff) | |
parent | ef96c458888fa2a329b14efc7991530f645fbddb (diff) | |
download | linux-37eceb69205b2a98e67c48710c1e9ad5e78f21e9.tar.xz |
Merge tag 'samsung-clk-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung clk driverd updates from Krzysztof Kozlowski:
- Exynos7885: add FSYS, TREX and MFC clock controllers.
- Exynos850: add IS and AUD (audio) clock controllers with bindings.
- ExynosAutov9: add FSYS clock controllers with bindings.
- ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock
controllers, due to duplicated entries. This is an acceptable ABI
break: recently developed/added platform so without legacies, acked
by known users/developers.
- ExynosAutov9: add few missing Peric 0/1 gates.
- ExynosAutov9: correct register offsets of few Peric 0/1 clocks.
- Minor code improvements (use of_device_get_match_data() helper, code
style).
- Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he
already maintainers that architecture/platform.
* tag 'samsung-clk-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
clk: samsung: MAINTAINERS: add Krzysztof Kozlowski
clk: samsung: exynos850: Implement CMU_MFCMSCL domain
clk: samsung: exynos850: Implement CMU_IS domain
clk: samsung: exynos850: Implement CMU_AUD domain
clk: samsung: exynos850: Style fixes
clk: samsung: exynosautov9: add fsys1 clock support
clk: samsung: exynosautov9: add fsys0 clock support
clk: samsung: exynosautov9: correct register offsets of peric0/c1
clk: samsung: exynosautov9: add missing gate clks for peric0/c1
dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL
dt-bindings: clock: exynos850: Add Exynos850 CMU_IS
dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD
dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1
dt-bindings: clock: exynosautov9: add fsys1 clock definitions
dt-bindings: clock: exynosautov9: add fys0 clock definitions
clk: samsung: exynos7885: Add TREX clocks
clk: samsung: exynos7885: Implement CMU_FSYS domain
dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1
clk: samsung: exynos-clkout: Use of_device_get_match_data()
Diffstat (limited to 'include/dt-bindings/clock')
-rw-r--r-- | include/dt-bindings/clock/exynos850.h | 136 | ||||
-rw-r--r-- | include/dt-bindings/clock/samsung,exynosautov9.h | 128 |
2 files changed, 233 insertions, 31 deletions
diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h index 0b6a3c6a7c90..88d5289883d3 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -58,7 +58,34 @@ #define CLK_MOUT_CLKCMU_APM_BUS 46 #define CLK_DOUT_CLKCMU_APM_BUS 47 #define CLK_GOUT_CLKCMU_APM_BUS 48 -#define TOP_NR_CLK 49 +#define CLK_MOUT_AUD 49 +#define CLK_GOUT_AUD 50 +#define CLK_DOUT_AUD 51 +#define CLK_MOUT_IS_BUS 52 +#define CLK_MOUT_IS_ITP 53 +#define CLK_MOUT_IS_VRA 54 +#define CLK_MOUT_IS_GDC 55 +#define CLK_GOUT_IS_BUS 56 +#define CLK_GOUT_IS_ITP 57 +#define CLK_GOUT_IS_VRA 58 +#define CLK_GOUT_IS_GDC 59 +#define CLK_DOUT_IS_BUS 60 +#define CLK_DOUT_IS_ITP 61 +#define CLK_DOUT_IS_VRA 62 +#define CLK_DOUT_IS_GDC 63 +#define CLK_MOUT_MFCMSCL_MFC 64 +#define CLK_MOUT_MFCMSCL_M2M 65 +#define CLK_MOUT_MFCMSCL_MCSC 66 +#define CLK_MOUT_MFCMSCL_JPEG 67 +#define CLK_GOUT_MFCMSCL_MFC 68 +#define CLK_GOUT_MFCMSCL_M2M 69 +#define CLK_GOUT_MFCMSCL_MCSC 70 +#define CLK_GOUT_MFCMSCL_JPEG 71 +#define CLK_DOUT_MFCMSCL_MFC 72 +#define CLK_DOUT_MFCMSCL_M2M 73 +#define CLK_DOUT_MFCMSCL_MCSC 74 +#define CLK_DOUT_MFCMSCL_JPEG 75 +#define TOP_NR_CLK 76 /* CMU_APM */ #define CLK_RCO_I3C_PMIC 1 @@ -87,6 +114,69 @@ #define CLK_GOUT_SYSREG_APM_PCLK 24 #define APM_NR_CLK 25 +/* CMU_AUD */ +#define CLK_DOUT_AUD_AUDIF 1 +#define CLK_DOUT_AUD_BUSD 2 +#define CLK_DOUT_AUD_BUSP 3 +#define CLK_DOUT_AUD_CNT 4 +#define CLK_DOUT_AUD_CPU 5 +#define CLK_DOUT_AUD_CPU_ACLK 6 +#define CLK_DOUT_AUD_CPU_PCLKDBG 7 +#define CLK_DOUT_AUD_FM 8 +#define CLK_DOUT_AUD_FM_SPDY 9 +#define CLK_DOUT_AUD_MCLK 10 +#define CLK_DOUT_AUD_UAIF0 11 +#define CLK_DOUT_AUD_UAIF1 12 +#define CLK_DOUT_AUD_UAIF2 13 +#define CLK_DOUT_AUD_UAIF3 14 +#define CLK_DOUT_AUD_UAIF4 15 +#define CLK_DOUT_AUD_UAIF5 16 +#define CLK_DOUT_AUD_UAIF6 17 +#define CLK_FOUT_AUD_PLL 18 +#define CLK_GOUT_AUD_ABOX_ACLK 19 +#define CLK_GOUT_AUD_ASB_CCLK 20 +#define CLK_GOUT_AUD_CA32_CCLK 21 +#define CLK_GOUT_AUD_CNT_BCLK 22 +#define CLK_GOUT_AUD_CODEC_MCLK 23 +#define CLK_GOUT_AUD_DAP_CCLK 24 +#define CLK_GOUT_AUD_GPIO_PCLK 25 +#define CLK_GOUT_AUD_PPMU_ACLK 26 +#define CLK_GOUT_AUD_PPMU_PCLK 27 +#define CLK_GOUT_AUD_SPDY_BCLK 28 +#define CLK_GOUT_AUD_SYSMMU_CLK 29 +#define CLK_GOUT_AUD_SYSREG_PCLK 30 +#define CLK_GOUT_AUD_TZPC_PCLK 31 +#define CLK_GOUT_AUD_UAIF0_BCLK 32 +#define CLK_GOUT_AUD_UAIF1_BCLK 33 +#define CLK_GOUT_AUD_UAIF2_BCLK 34 +#define CLK_GOUT_AUD_UAIF3_BCLK 35 +#define CLK_GOUT_AUD_UAIF4_BCLK 36 +#define CLK_GOUT_AUD_UAIF5_BCLK 37 +#define CLK_GOUT_AUD_UAIF6_BCLK 38 +#define CLK_GOUT_AUD_WDT_PCLK 39 +#define CLK_MOUT_AUD_CPU 40 +#define CLK_MOUT_AUD_CPU_HCH 41 +#define CLK_MOUT_AUD_CPU_USER 42 +#define CLK_MOUT_AUD_FM 43 +#define CLK_MOUT_AUD_PLL 44 +#define CLK_MOUT_AUD_TICK_USB_USER 45 +#define CLK_MOUT_AUD_UAIF0 46 +#define CLK_MOUT_AUD_UAIF1 47 +#define CLK_MOUT_AUD_UAIF2 48 +#define CLK_MOUT_AUD_UAIF3 49 +#define CLK_MOUT_AUD_UAIF4 50 +#define CLK_MOUT_AUD_UAIF5 51 +#define CLK_MOUT_AUD_UAIF6 52 +#define IOCLK_AUDIOCDCLK0 53 +#define IOCLK_AUDIOCDCLK1 54 +#define IOCLK_AUDIOCDCLK2 55 +#define IOCLK_AUDIOCDCLK3 56 +#define IOCLK_AUDIOCDCLK4 57 +#define IOCLK_AUDIOCDCLK5 58 +#define IOCLK_AUDIOCDCLK6 59 +#define TICK_USB 60 +#define AUD_NR_CLK 61 + /* CMU_CMGP */ #define CLK_RCO_CMGP 1 #define CLK_MOUT_CMGP_ADC 2 @@ -121,6 +211,50 @@ #define CLK_GOUT_SYSREG_HSI_PCLK 13 #define HSI_NR_CLK 14 +/* CMU_IS */ +#define CLK_MOUT_IS_BUS_USER 1 +#define CLK_MOUT_IS_ITP_USER 2 +#define CLK_MOUT_IS_VRA_USER 3 +#define CLK_MOUT_IS_GDC_USER 4 +#define CLK_DOUT_IS_BUSP 5 +#define CLK_GOUT_IS_CMU_IS_PCLK 6 +#define CLK_GOUT_IS_CSIS0_ACLK 7 +#define CLK_GOUT_IS_CSIS1_ACLK 8 +#define CLK_GOUT_IS_CSIS2_ACLK 9 +#define CLK_GOUT_IS_TZPC_PCLK 10 +#define CLK_GOUT_IS_CSIS_DMA_CLK 11 +#define CLK_GOUT_IS_GDC_CLK 12 +#define CLK_GOUT_IS_IPP_CLK 13 +#define CLK_GOUT_IS_ITP_CLK 14 +#define CLK_GOUT_IS_MCSC_CLK 15 +#define CLK_GOUT_IS_VRA_CLK 16 +#define CLK_GOUT_IS_PPMU_IS0_ACLK 17 +#define CLK_GOUT_IS_PPMU_IS0_PCLK 18 +#define CLK_GOUT_IS_PPMU_IS1_ACLK 19 +#define CLK_GOUT_IS_PPMU_IS1_PCLK 20 +#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21 +#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22 +#define CLK_GOUT_IS_SYSREG_PCLK 23 +#define IS_NR_CLK 24 + +/* CMU_MFCMSCL */ +#define CLK_MOUT_MFCMSCL_MFC_USER 1 +#define CLK_MOUT_MFCMSCL_M2M_USER 2 +#define CLK_MOUT_MFCMSCL_MCSC_USER 3 +#define CLK_MOUT_MFCMSCL_JPEG_USER 4 +#define CLK_DOUT_MFCMSCL_BUSP 5 +#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK 6 +#define CLK_GOUT_MFCMSCL_TZPC_PCLK 7 +#define CLK_GOUT_MFCMSCL_JPEG_ACLK 8 +#define CLK_GOUT_MFCMSCL_M2M_ACLK 9 +#define CLK_GOUT_MFCMSCL_MCSC_CLK 10 +#define CLK_GOUT_MFCMSCL_MFC_ACLK 11 +#define CLK_GOUT_MFCMSCL_PPMU_ACLK 12 +#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13 +#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14 +#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15 +#define MFCMSCL_NR_CLK 16 + /* CMU_PERI */ #define CLK_MOUT_PERI_BUS_USER 1 #define CLK_MOUT_PERI_UART_USER 2 diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h index ea9f91b4eb1a..42133af6d6b9 100644 --- a/include/dt-bindings/clock/samsung,exynosautov9.h +++ b/include/dt-bindings/clock/samsung,exynosautov9.h @@ -185,6 +185,74 @@ #define CORE_NR_CLK 6 +/* CMU_FSYS0 */ +#define CLK_MOUT_FSYS0_BUS_USER 1 +#define CLK_MOUT_FSYS0_PCIE_USER 2 +#define CLK_GOUT_FSYS0_BUS_PCLK 3 + +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_REFCLK 4 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_REFCLK 5 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_DBI_ACLK 6 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_MSTR_ACLK 7 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X1_SLV_ACLK 8 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_DBI_ACLK 9 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_MSTR_ACLK 10 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_SLV_ACLK 11 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L0_X2_PIPE_CLK 12 +#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L0_CLK 13 +#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L0_CLK 14 + +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_REFCLK 15 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_REFCLK 16 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_DBI_ACLK 17 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_MSTR_ACLK 18 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X1_SLV_ACLK 19 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_DBI_ACLK 20 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_MSTR_ACLK 21 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_SLV_ACLK 22 +#define CLK_GOUT_FSYS0_PCIE_GEN3_2L1_X2_PIPE_CLK 23 +#define CLK_GOUT_FSYS0_PCIE_GEN3A_2L1_CLK 24 +#define CLK_GOUT_FSYS0_PCIE_GEN3B_2L1_CLK 25 + +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_REFCLK 26 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_REFCLK 27 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_DBI_ACLK 28 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_MSTR_ACLK 29 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X2_SLV_ACLK 30 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_DBI_ACLK 31 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_MSTR_ACLK 32 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_SLV_ACLK 33 +#define CLK_GOUT_FSYS0_PCIE_GEN3_4L_X4_PIPE_CLK 34 +#define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK 35 +#define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK 36 + +#define FSYS0_NR_CLK 37 + +/* CMU_FSYS1 */ +#define FOUT_MMC_PLL 1 + +#define CLK_MOUT_FSYS1_BUS_USER 2 +#define CLK_MOUT_FSYS1_MMC_PLL 3 +#define CLK_MOUT_FSYS1_MMC_CARD_USER 4 +#define CLK_MOUT_FSYS1_USBDRD_USER 5 +#define CLK_MOUT_FSYS1_MMC_CARD 6 + +#define CLK_DOUT_FSYS1_MMC_CARD 7 + +#define CLK_GOUT_FSYS1_PCLK 8 +#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN 9 +#define CLK_GOUT_FSYS1_MMC_CARD_ACLK 10 +#define CLK_GOUT_FSYS1_USB20DRD_0_REFCLK 11 +#define CLK_GOUT_FSYS1_USB20DRD_1_REFCLK 12 +#define CLK_GOUT_FSYS1_USB30DRD_0_REFCLK 13 +#define CLK_GOUT_FSYS1_USB30DRD_1_REFCLK 14 +#define CLK_GOUT_FSYS1_USB20_0_ACLK 15 +#define CLK_GOUT_FSYS1_USB20_1_ACLK 16 +#define CLK_GOUT_FSYS1_USB30_0_ACLK 17 +#define CLK_GOUT_FSYS1_USB30_1_ACLK 18 + +#define FSYS1_NR_CLK 19 + /* CMU_FSYS2 */ #define CLK_MOUT_FSYS2_BUS_USER 1 #define CLK_MOUT_FSYS2_UFS_EMBD_USER 2 @@ -226,21 +294,21 @@ #define CLK_GOUT_PERIC0_IPCLK_8 28 #define CLK_GOUT_PERIC0_IPCLK_9 29 #define CLK_GOUT_PERIC0_IPCLK_10 30 -#define CLK_GOUT_PERIC0_IPCLK_11 30 -#define CLK_GOUT_PERIC0_PCLK_0 31 -#define CLK_GOUT_PERIC0_PCLK_1 32 -#define CLK_GOUT_PERIC0_PCLK_2 33 -#define CLK_GOUT_PERIC0_PCLK_3 34 -#define CLK_GOUT_PERIC0_PCLK_4 35 -#define CLK_GOUT_PERIC0_PCLK_5 36 -#define CLK_GOUT_PERIC0_PCLK_6 37 -#define CLK_GOUT_PERIC0_PCLK_7 38 -#define CLK_GOUT_PERIC0_PCLK_8 39 -#define CLK_GOUT_PERIC0_PCLK_9 40 -#define CLK_GOUT_PERIC0_PCLK_10 41 -#define CLK_GOUT_PERIC0_PCLK_11 42 - -#define PERIC0_NR_CLK 43 +#define CLK_GOUT_PERIC0_IPCLK_11 31 +#define CLK_GOUT_PERIC0_PCLK_0 32 +#define CLK_GOUT_PERIC0_PCLK_1 33 +#define CLK_GOUT_PERIC0_PCLK_2 34 +#define CLK_GOUT_PERIC0_PCLK_3 35 +#define CLK_GOUT_PERIC0_PCLK_4 36 +#define CLK_GOUT_PERIC0_PCLK_5 37 +#define CLK_GOUT_PERIC0_PCLK_6 38 +#define CLK_GOUT_PERIC0_PCLK_7 39 +#define CLK_GOUT_PERIC0_PCLK_8 40 +#define CLK_GOUT_PERIC0_PCLK_9 41 +#define CLK_GOUT_PERIC0_PCLK_10 42 +#define CLK_GOUT_PERIC0_PCLK_11 43 + +#define PERIC0_NR_CLK 44 /* CMU_PERIC1 */ #define CLK_MOUT_PERIC1_BUS_USER 1 @@ -272,21 +340,21 @@ #define CLK_GOUT_PERIC1_IPCLK_8 28 #define CLK_GOUT_PERIC1_IPCLK_9 29 #define CLK_GOUT_PERIC1_IPCLK_10 30 -#define CLK_GOUT_PERIC1_IPCLK_11 30 -#define CLK_GOUT_PERIC1_PCLK_0 31 -#define CLK_GOUT_PERIC1_PCLK_1 32 -#define CLK_GOUT_PERIC1_PCLK_2 33 -#define CLK_GOUT_PERIC1_PCLK_3 34 -#define CLK_GOUT_PERIC1_PCLK_4 35 -#define CLK_GOUT_PERIC1_PCLK_5 36 -#define CLK_GOUT_PERIC1_PCLK_6 37 -#define CLK_GOUT_PERIC1_PCLK_7 38 -#define CLK_GOUT_PERIC1_PCLK_8 39 -#define CLK_GOUT_PERIC1_PCLK_9 40 -#define CLK_GOUT_PERIC1_PCLK_10 41 -#define CLK_GOUT_PERIC1_PCLK_11 42 - -#define PERIC1_NR_CLK 43 +#define CLK_GOUT_PERIC1_IPCLK_11 31 +#define CLK_GOUT_PERIC1_PCLK_0 32 +#define CLK_GOUT_PERIC1_PCLK_1 33 +#define CLK_GOUT_PERIC1_PCLK_2 34 +#define CLK_GOUT_PERIC1_PCLK_3 35 +#define CLK_GOUT_PERIC1_PCLK_4 36 +#define CLK_GOUT_PERIC1_PCLK_5 37 +#define CLK_GOUT_PERIC1_PCLK_6 38 +#define CLK_GOUT_PERIC1_PCLK_7 39 +#define CLK_GOUT_PERIC1_PCLK_8 40 +#define CLK_GOUT_PERIC1_PCLK_9 41 +#define CLK_GOUT_PERIC1_PCLK_10 42 +#define CLK_GOUT_PERIC1_PCLK_11 43 + +#define PERIC1_NR_CLK 44 /* CMU_PERIS */ #define CLK_MOUT_PERIS_BUS_USER 1 |