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author | Marek Vasut <marex@denx.de> | 2022-10-31 23:48:38 +0300 |
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committer | Abel Vesa <abel.vesa@linaro.org> | 2022-11-22 01:04:49 +0300 |
commit | 6a11d3a00dc1f152e8cdf97171128c4186695a9d (patch) | |
tree | 19579595d22eb20da49d13246c78e11a11fdda87 /include/dt-bindings/clock | |
parent | f8aa5f6dc1cb71d472d023f87d05f53b1672983f (diff) | |
download | linux-6a11d3a00dc1f152e8cdf97171128c4186695a9d.tar.xz |
clk: imx: pll14xx: Add 320 MHz and 640 MHz entries for PLL146x
The PLL146x is used to implement SYS_PLL3 on i.MX8MP and can be used
to drive UARTn_ROOT clock. By setting the PLL3 to 320 MHz or 640 MHz,
the PLL3 output can be divided down to supply UARTn_ROOT clock with
precise 64 MHz, which divided down further by 16x oversampling factor
used by the i.MX UART core yields 4 Mbdps baud base for the UART IP.
This is useful e.g. for BCM bluetooth chips, which can operate up to
4 Mbdps.
Add 320 MHz and 640 MHz entries so the PLL can be configured accordingly.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20221031204838.195292-1-marex@denx.de
Diffstat (limited to 'include/dt-bindings/clock')
0 files changed, 0 insertions, 0 deletions