diff options
| author | Arindam Nath <arindam.nath@amd.com> | 2011-05-05 10:49:01 +0400 |
|---|---|---|
| committer | Chris Ball <cjb@laptop.org> | 2011-05-25 07:53:45 +0400 |
| commit | 49c468fcf878d2c86e31920cf54aa90c88418a66 (patch) | |
| tree | d8088bf8fb1a011f05ebbdefef49f2a6f4739432 /include/linux/mmc/host.h | |
| parent | 758535c4e3cdd2b5b09565d9651aaa541aac3de8 (diff) | |
| download | linux-49c468fcf878d2c86e31920cf54aa90c88418a66.tar.xz | |
mmc: sd: add support for uhs bus speed mode selection
This patch adds support for setting UHS-I bus speed mode during UHS-I
initialization procedure. Since both the host and card can support
more than one bus speed, we select the highest speed based on both of
their capabilities. First we set the bus speed mode for the card using
CMD6 mode 1, and then we program the host controller to support the
required speed mode. We also set High Speed Enable in case one of the
UHS-I modes is selected. We take care to reset SD clock before setting
UHS mode in the Host Control2 register, and then re-enable it as per
the Host Controller spec v3.00. We then set the clock frequency for
the UHS-I mode selected.
Tested by Zhangfei Gao with a Toshiba uhs card and general hs card,
on mmp2 in SDMA mode.
Signed-off-by: Arindam Nath <arindam.nath@amd.com>
Reviewed-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'include/linux/mmc/host.h')
| -rw-r--r-- | include/linux/mmc/host.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 949e4d525989..62375992bdd6 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -50,6 +50,11 @@ struct mmc_ios { #define MMC_TIMING_LEGACY 0 #define MMC_TIMING_MMC_HS 1 #define MMC_TIMING_SD_HS 2 +#define MMC_TIMING_UHS_SDR12 MMC_TIMING_LEGACY +#define MMC_TIMING_UHS_SDR25 MMC_TIMING_SD_HS +#define MMC_TIMING_UHS_SDR50 3 +#define MMC_TIMING_UHS_SDR104 4 +#define MMC_TIMING_UHS_DDR50 5 unsigned char ddr; /* dual data rate used */ |