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authorKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>2009-11-05 06:05:11 +0300
committerJesse Barnes <jbarnes@virtuousgeek.org>2009-11-07 00:59:02 +0300
commit0efea0006335a2425b1a12a2ad35efad626fe353 (patch)
treed139b06a32665ec1227c06f1c0a14b21e3c0d654 /include/linux/pci.h
parent1e5ad9679016275d422e36b12a98b0927d76f556 (diff)
downloadlinux-0efea0006335a2425b1a12a2ad35efad626fe353.tar.xz
PCI: cache PCIe capability offset
There are a lot of codes that searches PCI express capability offset in the PCI configuration space using pci_find_capability(). Caching it in the struct pci_dev will reduce unncecessary search. This patch adds an additional 'pcie_cap' fields into struct pci_dev, which is initialized at pci device scan time (in set_pcie_port_type()). Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'include/linux/pci.h')
-rw-r--r--include/linux/pci.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 86c31ac454d1..233b3a092035 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -218,6 +218,7 @@ struct pci_dev {
unsigned int class; /* 3 bytes: (base,sub,prog-if) */
u8 revision; /* PCI revision, low byte of class word */
u8 hdr_type; /* PCI header type (`multi' flag masked out) */
+ u8 pcie_cap; /* PCI-E capability offset */
u8 pcie_type; /* PCI-E device/port type */
u8 rom_base_reg; /* which config register controls the ROM */
u8 pin; /* which interrupt pin this device uses */