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authorStephen Warren <swarren@nvidia.com>2011-05-18 02:12:37 +0400
committerGreg Kroah-Hartman <gregkh@suse.de>2011-05-20 03:51:02 +0400
commit5f873bae704cf8b7cbd64b5720912266286c9146 (patch)
tree0e861218bdb25d0ad3f41aa569f89d0f56d59d18 /include/linux/serial_reg.h
parent4539c24fe4f92c09ee668ef959d3e8180df619b9 (diff)
downloadlinux-5f873bae704cf8b7cbd64b5720912266286c9146.tar.xz
tty/serial: Fix break handling for PORT_TEGRA
When a break is received, Tegra's UART apparently fills the FIFO with 0 bytes. These must be drained so that they aren't interpreted as actual data received. This allows e.g. MAGIC_SYSRQ to work on Tegra's UARTs. v2: Added FIXME comment to clear_rx_fifo Originally-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'include/linux/serial_reg.h')
-rw-r--r--include/linux/serial_reg.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h
index 5f66e8499fb9..c75bda37c18e 100644
--- a/include/linux/serial_reg.h
+++ b/include/linux/serial_reg.h
@@ -119,6 +119,7 @@
#define UART_MCR_DTR 0x01 /* DTR complement */
#define UART_LSR 5 /* In: Line Status Register */
+#define UART_LSR_FIFOE 0x80 /* Fifo error */
#define UART_LSR_TEMT 0x40 /* Transmitter empty */
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
#define UART_LSR_BI 0x10 /* Break interrupt indicator */