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authorPaul Mundt <lethal@linux-sh.org>2010-04-15 08:13:52 +0400
committerPaul Mundt <lethal@linux-sh.org>2010-04-15 08:13:52 +0400
commitdc825b17904a06bbd2f79d720b23156e4c01a22f (patch)
tree8f1e13b850a06264530f1f1bb680a541e73cef34 /include/linux/sh_intc.h
parentfecf066c2d2fbc7e6a7e7e3a5af772a165bdd7b0 (diff)
downloadlinux-dc825b17904a06bbd2f79d720b23156e4c01a22f.tar.xz
sh: intc: IRQ auto-distribution support.
This implements support for hardware-managed IRQ balancing as implemented by SH-X3 cores (presently only hooked up for SH7786, but can probably be carried over to other SH-X3 cores, too). CPUs need to specify their distribution register along with the mask definitions, as these follow the same format. Peripheral IRQs that don't opt out of balancing will be automatically distributed at the whim of the hardware block, while each CPU needs to verify whether it is handling the IRQ or not, especially before clearing the mask. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/linux/sh_intc.h')
-rw-r--r--include/linux/sh_intc.h11
1 files changed, 10 insertions, 1 deletions
diff --git a/include/linux/sh_intc.h b/include/linux/sh_intc.h
index f0e8cca199c7..0d6cd38e673d 100644
--- a/include/linux/sh_intc.h
+++ b/include/linux/sh_intc.h
@@ -23,6 +23,9 @@ struct intc_group {
struct intc_mask_reg {
unsigned long set_reg, clr_reg, reg_width;
intc_enum enum_ids[32];
+#ifdef CONFIG_INTC_BALANCING
+ unsigned long dist_reg;
+#endif
#ifdef CONFIG_SMP
unsigned long smp;
#endif
@@ -41,8 +44,14 @@ struct intc_sense_reg {
intc_enum enum_ids[16];
};
+#ifdef CONFIG_INTC_BALANCING
+#define INTC_SMP_BALANCING(reg) .dist_reg = (reg)
+#else
+#define INTC_SMP_BALANCING(reg)
+#endif
+
#ifdef CONFIG_SMP
-#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8)
+#define INTC_SMP(stride, nr) .smp = (stride) | ((nr) << 8)
#else
#define INTC_SMP(stride, nr)
#endif