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authorMichael Buesch <mb@bu3sch.de>2008-02-19 19:46:48 +0300
committerJohn W. Linville <linville@tuxdriver.com>2008-02-21 04:11:49 +0300
commit7cb4461520f307a6e3fb2bb32cb8daee45aa1fae (patch)
tree24d287cb729e511285465456cdd0ec02805e9130 /include/linux/ssb
parent53521d8c90d366191b6c134f88a8ebe83de60614 (diff)
downloadlinux-7cb4461520f307a6e3fb2bb32cb8daee45aa1fae.tar.xz
ssb: Fix pcicore cardbus mode
This fixes the pcicore driver to not die a horrible crash death when inserting a cardbus card. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'include/linux/ssb')
-rw-r--r--include/linux/ssb/ssb.h7
-rw-r--r--include/linux/ssb/ssb_driver_pci.h5
2 files changed, 12 insertions, 0 deletions
diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h
index d14c03685717..20add65215af 100644
--- a/include/linux/ssb/ssb.h
+++ b/include/linux/ssb/ssb.h
@@ -282,6 +282,8 @@ struct ssb_bus {
struct ssb_boardinfo boardinfo;
/* Contents of the SPROM. */
struct ssb_sprom sprom;
+ /* If the board has a cardbus slot, this is set to true. */
+ bool has_cardbus_slot;
#ifdef CONFIG_SSB_EMBEDDED
/* Lock for GPIO register access. */
@@ -299,8 +301,13 @@ struct ssb_bus {
/* The initialization-invariants. */
struct ssb_init_invariants {
+ /* Versioning information about the PCB. */
struct ssb_boardinfo boardinfo;
+ /* The SPROM information. That's either stored in an
+ * EEPROM or NVRAM on the board. */
struct ssb_sprom sprom;
+ /* If the board has a cardbus slot, this is set to true. */
+ bool has_cardbus_slot;
};
/* Type of function to fetch the invariants. */
typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
diff --git a/include/linux/ssb/ssb_driver_pci.h b/include/linux/ssb/ssb_driver_pci.h
index 9cfffb7b1a27..5e25bac4ed31 100644
--- a/include/linux/ssb/ssb_driver_pci.h
+++ b/include/linux/ssb/ssb_driver_pci.h
@@ -51,6 +51,11 @@
#define SSB_PCICORE_SBTOPCI1_MASK 0xFC000000
#define SSB_PCICORE_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
#define SSB_PCICORE_SBTOPCI2_MASK 0xC0000000
+#define SSB_PCICORE_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
+#define SSB_PCICORE_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
+#define SSB_PCICORE_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
+#define SSB_PCICORE_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
+#define SSB_PCICORE_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
/* SBtoPCIx */
#define SSB_PCICORE_SBTOPCI_MEM 0x00000000