summaryrefslogtreecommitdiff
path: root/include/soc/arc
diff options
context:
space:
mode:
authorVineet Gupta <vgupta@synopsys.com>2016-10-31 23:06:19 +0300
committerVineet Gupta <vgupta@synopsys.com>2016-11-30 22:54:25 +0300
commitb26c2e3823bae6ba43a2b263d9bb75a3efd39b6a (patch)
tree9db1449b325dcb708de12e3be54c16890774e9ff /include/soc/arc
parent2d7f5c48c03ee53ad649cbf803dc33730f955234 (diff)
downloadlinux-b26c2e3823bae6ba43a2b263d9bb75a3efd39b6a.tar.xz
ARC: breakout timer include code into separate header ...
... which allows for use in drivers/clocksource later Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'include/soc/arc')
-rw-r--r--include/soc/arc/timers.h38
1 files changed, 38 insertions, 0 deletions
diff --git a/include/soc/arc/timers.h b/include/soc/arc/timers.h
new file mode 100644
index 000000000000..a20ed2fbc432
--- /dev/null
+++ b/include/soc/arc/timers.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SOC_ARC_TIMERS_H
+#define __SOC_ARC_TIMERS_H
+
+#include <soc/arc/aux.h>
+
+/* Timer related Aux registers */
+#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
+#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
+#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
+#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
+#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
+#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
+
+/* CTRL reg bits */
+#define TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
+#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
+
+#define ARC_TIMERN_MAX 0xFFFFFFFF
+
+#define ARC_REG_TIMERS_BCR 0x75
+
+struct bcr_timer {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+ unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
+#else
+ unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
+#endif
+};
+
+#endif