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authorConor Dooley <conor.dooley@microchip.com>2022-09-09 15:31:13 +0300
committerClaudiu Beznea <claudiu.beznea@microchip.com>2022-09-14 10:55:17 +0300
commitb56bae2dd6fda6baf3bb74af3812676eebdd52f2 (patch)
tree5114cb248a7eac901658f79afd185edb7287e696 /include/soc
parent89b16523d949b04c30b91e65bb6f91cac888e062 (diff)
downloadlinux-b56bae2dd6fda6baf3bb74af3812676eebdd52f2.tar.xz
clk: microchip: mpfs: add reset controller
Add a reset controller to PolarFire SoC's clock driver. This reset controller is registered as an aux device and read/write functions exported to the drivers namespace so that the reset controller can access the peripheral device reset register. Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220909123123.2699583-5-conor.dooley@microchip.com
Diffstat (limited to 'include/soc')
-rw-r--r--include/soc/microchip/mpfs.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/include/soc/microchip/mpfs.h b/include/soc/microchip/mpfs.h
index 6466515262bd..f916dcde457f 100644
--- a/include/soc/microchip/mpfs.h
+++ b/include/soc/microchip/mpfs.h
@@ -40,4 +40,12 @@ struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev);
#endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */
+#if IS_ENABLED(CONFIG_MCHP_CLK_MPFS)
+
+u32 mpfs_reset_read(struct device *dev);
+
+void mpfs_reset_write(struct device *dev, u32 val);
+
+#endif /* if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) */
+
#endif /* __SOC_MPFS_H__ */