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authorMatt Roper <matthew.d.roper@intel.com>2023-06-02 00:52:25 +0300
committerRodrigo Vivi <rodrigo.vivi@intel.com>2023-12-20 02:34:14 +0300
commit876611c2b75689c6bea43bdbbbef9b358f71526a (patch)
tree9a5ac2da4dd0a51b434b21713c38796c25631f74 /include/uapi/drm
parentebd288cba7db7097ad50a4736ded94cb0d92fadf (diff)
downloadlinux-876611c2b75689c6bea43bdbbbef9b358f71526a.tar.xz
drm/xe: Memory allocations are tile-based, not GT-based
Since memory and address spaces are a tile concept rather than a GT concept, we need to plumb tile-based handling through lots of memory-related code. Note that one remaining shortcoming here that will need to be addressed before media GT support can be re-enabled is that although the address space is shared between a tile's GTs, each GT caches the PTEs independently in their own TLB and thus TLB invalidation should be handled at the GT level. v2: - Fix kunit test build. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20230601215244.678611-13-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'include/uapi/drm')
-rw-r--r--include/uapi/drm/xe_drm.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 34aff9e15fe6..edd29e7f39eb 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -407,10 +407,10 @@ struct drm_xe_vm_bind_op {
__u64 addr;
/**
- * @gt_mask: Mask for which GTs to create binds for, 0 == All GTs,
+ * @tile_mask: Mask for which tiles to create binds for, 0 == All tiles,
* only applies to creating new VMAs
*/
- __u64 gt_mask;
+ __u64 tile_mask;
/** @op: Operation to perform (lower 16 bits) and flags (upper 16 bits) */
__u32 op;