diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-12-16 03:49:59 +0300 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-12-16 03:49:59 +0300 |
commit | 489e9fea66f31086f85d9a18e61e4791d94a56a4 (patch) | |
tree | 0283bc742248a64ba2df8793572fae526eb23cf4 /include/uapi/linux/pci_regs.h | |
parent | aab7ce2b099bd9df82573cd3170acf6518fdebeb (diff) | |
parent | 255b2d524884e4ec60333131aa0ca0ef19826dc2 (diff) | |
download | linux-489e9fea66f31086f85d9a18e61e4791d94a56a4.tar.xz |
Merge tag 'pci-v5.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas:
"Enumeration:
- Decode PCIe 64 GT/s link speed (Gustavo Pimentel)
- Remove unused HAVE_PCI_SET_MWI (Heiner Kallweit)
- Reduce pci_set_cacheline_size() message to debug level (Heiner
Kallweit)
- Fix pci_slot_release() NULL pointer dereference (Jubin Zhong)
- Unify ECAM constants in native PCI Express drivers (Krzysztof
Wilczyński)
- Return u8 from pci_find_capability() and similar (Puranjay Mohan)
- Return u16 from pci_find_ext_capability() and similar (Bjorn
Helgaas)
- Fix ACPI companion lookup for device 0 on the root bus (Rafael J.
Wysocki)
Resource management:
- Keep both device and resource name for config space remaps
(Alexander Lobakin)
- Bounds-check command-line resource alignment requests (Bjorn
Helgaas)
- Fix overflow in command-line resource alignment requests (Colin Ian
King)
Driver binding:
- Avoid duplicate IDs in driver dynamic IDs list (Zhenzhong Duan)
Power management:
- Save/restore Precision Time Measurement Capability for
suspend/resume (David E. Box)
- Disable PTM during suspend to save power (David E. Box)
- Add sysfs attribute for device power state (Maximilian Luz)
- Rename pci_wakeup_bus() to pci_resume_bus() (Mika Westerberg)
- Do not generate wakeup event when runtime resuming device (Mika
Westerberg)
- Save/restore ASPM L1SS Capability for suspend/resume (Vidya Sagar)
Virtualization:
- Mark AMD Raven iGPU ATS as broken in some platforms (Alex Deucher)
- Add function 1 DMA alias quirk for Marvell 9215 SATA controller
(Bjorn Helgaas)
MSI:
- Disable MSI for Pericom PCIe-USB adapter (Andy Shevchenko)
- Improve warnings for 32-bit-limited MSI support (Vidya Sagar)
Error handling:
- Cache RCEC EA Capability offset in pci_init_capabilities() (Sean V
Kelley)
- Rename reset_link() to reset_subordinates() (Sean V Kelley)
- Write AER Capability only when we control it (Sean V Kelley)
- Clear AER status only when we control AER (Sean V Kelley)
- Bind RCEC devices to the Root Port driver (Qiuxu Zhuo)
- Recover from RCiEP AER errors (Qiuxu Zhuo)
- Recover from RCEC AER errors (Sean V Kelley)
- Add pcie_link_rcec() to associate RCiEPs (Sean V Kelley)
- Add pcie_walk_rcec() to RCEC AER handling (Sean V Kelley)
- Add pcie_walk_rcec() to RCEC PME handling (Sean V Kelley)
- Add RCEC AER error injection support (Qiuxu Zhuo)
Broadcom iProc PCIe controller driver:
- Fix out-of-bound array accesses (Bharat Gooty)
- Invalidate correct PAXB inbound windows (Roman Bacik)
- Enhance PCIe Link information display (Srinath Mannam)
Cadence PCIe controller driver:
- Make "cdns,max-outbound-regions" property optional (Kishon Vijay
Abraham I)
Intel VMD host bridge driver:
- Offset client MSI-X vectors (Jon Derrick)
- Update type of __iomem pointers (Krzysztof Wilczyński)
NVIDIA Tegra PCIe controller driver:
- Move "dbi" accesses to post common DWC initialization (Vidya Sagar)
- Read "dbi" base address to program in application logic (Vidya
Sagar)
- Fix ASPM-L1SS advertisement disable code (Vidya Sagar)
- Set DesignWare IP version (Vidya Sagar)
- Continue unconfig sequence even if parts fail (Vidya Sagar)
- Check return value of tegra_pcie_init_controller() (Vidya Sagar)
- Disable LTSSM during L2 entry (Vidya Sagar)
Qualcomm PCIe controller driver:
- Document PCIe bindings for SM8250 SoC (Manivannan Sadhasivam)
- Add SM8250 SoC support (Manivannan Sadhasivam)
- Add support for configuring BDF to SID mapping for SM8250
(Manivannan Sadhasivam)
Renesas R-Car PCIe controller driver:
- rcar: Drop unused members from struct rcar_pcie_host (Lad
Prabhakar)
- PCI: rcar-pci-host: Document r8a774e1 bindings (Lad Prabhakar)
- PCI: rcar-pci-host: Convert bindings to json-schema (Yoshihiro
Shimoda)
- PCI: rcar-pci-host: Document r8a77965 bindings (Yoshihiro Shimoda)
Samsung Exynos PCIe controller driver:
- Rework driver to support Exynos5433 PCIe PHY (Jaehoon Chung)
- Rework driver to support Exynos5433 variant (Jaehoon Chung)
- Drop samsung,exynos5440-pcie binding (Marek Szyprowski)
- Add the samsung,exynos-pcie binding (Marek Szyprowski)
- Add the samsung,exynos-pcie-phy binding (Marek Szyprowski)
Synopsys DesignWare PCIe controller driver:
- Support multiple ATU memory regions (Rob Herring)
- Move intel-gw ATU offset out of driver match data (Rob Herring)
- Move "dbi", "dbi2", and "addr_space" resource setup into common
code (Rob Herring)
- Remove intel-gw unneeded function wrappers (Rob Herring)
- Ensure all outbound ATU windows are reset (Rob Herring)
- Use the common MSI irq_chip in dra7xx (Rob Herring)
- Drop the .set_num_vectors() host op (Rob Herring)
- Move MSI interrupt setup into DWC common code (Rob Herring)
- Rework MSI initialization (Rob Herring)
- Move link handling into common code (Rob Herring)
- Move dw_pcie_msi_init() into core (Rob Herring)
- Move dw_pcie_setup_rc() to DWC common code (Rob Herring)
- Remove unnecessary wrappers around dw_pcie_host_init() (Rob
Herring)
- Drop keystone duplicated 'num-viewport'" (Rob Herring)
- Move inbound and outbound windows to common struct (Rob Herring)
- Detect number of iATU windows (Rob Herring)
- Warn if non-prefetchable memory aperture size is > 32-bit (Vidya
Sagar)
- Add support to program ATU for >4GB memory (Vidya Sagar)
- Set 32-bit DMA mask for MSI target address allocation (Vidya Sagar)
TI J721E PCIe driver:
- Fix "ti,syscon-pcie-ctrl" to take argument (Kishon Vijay Abraham I)
- Add host mode dt-bindings for TI's J7200 SoC (Kishon Vijay Abraham
I)
- Add EP mode dt-bindings for TI's J7200 SoC (Kishon Vijay Abraham I)
- Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg
(Kishon Vijay Abraham I)
TI Keystone PCIe controller driver:
- Enable compile-testing on !ARM (Alex Dewar)"
* tag 'pci-v5.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (100 commits)
PCI: Add function 1 DMA alias quirk for Marvell 9215 SATA controller
PCI/ACPI: Fix companion lookup for device 0 on the root bus
PCI: Keep both device and resource name for config space remaps
PCI: xgene: Removed unused ".bus_shift" initialisers from pci-xgene.c
PCI: vmd: Update type of the __iomem pointers
PCI: iproc: Convert to use the new ECAM constants
PCI: thunder-pem: Add constant for custom ".bus_shift" initialiser
PCI: Unify ECAM constants in native PCI Express drivers
PCI: Disable PTM during suspend to save power
PCI/PTM: Save/restore Precision Time Measurement Capability for suspend/resume
PCI: Mark AMD Raven iGPU ATS as broken in some platforms
PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg
dt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC
dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC
dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument
PCI: dwc: Set 32-bit DMA mask for MSI target address allocation
PCI: qcom: Add support for configuring BDF to SID mapping for SM8250
PCI: Reduce pci_set_cacheline_size() message to debug level
PCI: Remove unused HAVE_PCI_SET_MWI
PCI: qcom: Add SM8250 SoC support
...
Diffstat (limited to 'include/uapi/linux/pci_regs.h')
-rw-r--r-- | include/uapi/linux/pci_regs.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 8f8bd2318c6c..e709ae8235e7 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -531,6 +531,7 @@ #define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */ +#define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */ #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ #define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */ @@ -562,6 +563,7 @@ #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ #define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */ #define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */ +#define PCI_EXP_LNKSTA_CLS_64_0GB 0x0006 /* Current Link Speed 64.0GT/s */ #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ #define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */ #define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */ @@ -670,6 +672,7 @@ #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */ #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */ +#define PCI_EXP_LNKCAP2_SLS_64_0GB 0x00000040 /* Supported Speed 64GT/s */ #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ #define PCI_EXP_LNKCTL2_TLS 0x000f @@ -678,6 +681,7 @@ #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ +#define PCI_EXP_LNKCTL2_TLS_64_0GT 0x0006 /* Supported Speed 64GT/s */ #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ #define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */ @@ -832,6 +836,13 @@ #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ #define PCI_EXT_CAP_PWR_SIZEOF 16 +/* Root Complex Event Collector Endpoint Association */ +#define PCI_RCEC_RCIEP_BITMAP 4 /* Associated Bitmap for RCiEPs */ +#define PCI_RCEC_BUSN 8 /* RCEC Associated Bus Numbers */ +#define PCI_RCEC_BUSN_REG_VER 0x02 /* Least version with BUSN present */ +#define PCI_RCEC_BUSN_NEXT(x) (((x) >> 8) & 0xff) +#define PCI_RCEC_BUSN_LAST(x) (((x) >> 16) & 0xff) + /* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */ #define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */ #define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) |