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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2017-08-22 16:58:20 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-08-28 21:51:20 +0300
commit63e8d4394a2d226803f47abd7287dbb6d21bf8e4 (patch)
tree205fea237b5faf156fe2ca7a5411fef88c50706e /include/uapi/linux/serial_core.h
parentaef3ad103a686f21b746977d4ed21cc1af36f589 (diff)
downloadlinux-63e8d4394a2d226803f47abd7287dbb6d21bf8e4.tar.xz
serial: pch_uart: Make port type explicit
It used to be a gap in port definitions after PORT_MAX_8250. Since the new drivers are coming the gap become shorter and shorter until the commit a2d6a987bfe4 ("serial: 8250: Add new port type for TI DA8xx/66AK2x") completely removed it. So, while type here is just a formality, make things a little bit more explicit for this driver and move port types to UAPI header. Note, it uses two types for now. Fixes: fddceb8b5399 ("tty: 8250: Add 64byte UART support for FSL platforms") Cc: Priyanka Jain <Priyanka.Jain@freescale.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/uapi/linux/serial_core.h')
-rw-r--r--include/uapi/linux/serial_core.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 38bea3217ead..502aa23c7e15 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -57,7 +57,6 @@
#define PORT_RT2880 29 /* Ralink RT2880 internal UART */
#define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */
#define PORT_DA830 31 /* TI DA8xx/66AK2x */
-#define PORT_MAX_8250 31 /* max port ID */
/*
* ARM specific type numbers. These are not currently guaranteed
@@ -77,6 +76,10 @@
#define PORT_SUNZILOG 38
#define PORT_SUNSAB 39
+/* Intel EG20 */
+#define PORT_PCH_8LINE 44
+#define PORT_PCH_2LINE 45
+
/* DEC */
#define PORT_DZ 46
#define PORT_ZS 47