Merge tag 'edac_updates_for_v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras

Pull EDAC updates from Borislav Petkov:
 "Somewhat busier than usual this cycle:

   - Add support for AST2400 and AST2600 hw to aspeed_edac (Troy Lee)

   - Remove an orphaned mv64x60_edac driver. Good riddance (Michael
     Ellerman)

   - Add a new igen6 driver for Intel client SoCs with an integrated
     memory controller and using in-band ECC (Qiuxu Zhuo and Tony Luck)

   - The usual smattering of fixes and cleanups all over"

* tag 'edac_updates_for_v5.11' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
  EDAC/mv64x60: Remove orphan mv64x60 driver
  EDAC/aspeed: Add support for AST2400 and AST2600
  ARM: dts: aspeed: Add AST2600 EDAC into common devicetree
  dt-bindings: edac: aspeed-sdram-edac: Add ast2400/ast2600 support
  EDAC/amd64: Fix PCI component registration
  EDAC/igen6: ecclog_llist can be static
  EDAC/i10nm: Add Intel Sapphire Rapids server support
  EDAC: Add DDR5 new memory type
  EDAC/i10nm: Use readl() to access MMIO registers
  MAINTAINERS: Add entry for Intel IGEN6 EDAC driver
  EDAC/igen6: Add debugfs interface for Intel client SoC EDAC driver
  EDAC/igen6: Add EDAC driver for Intel client SoCs using IBECC
  EDAC/synopsys: Return the correct value in mc_probe()
  MAINTAINERS: Clean up the F: entries for some EDAC drivers
  EDAC: Add three new memory types
  EDAC: Fix some kernel-doc markups
  EDAC: Do not issue useless debug statements in the polling routine
  EDAC/amd64: Remove unneeded breaks

1 files changed, 14 insertions, 2 deletions

diff --git a/include/linux/edac.h b/include/linux/edac.h
index 15e8f3d8a895..76d3562d3006 100644
--- a/include/linux/edac.h
+++ b/include/linux/edac.h
@@ -175,11 +175,15 @@ static inline char *mc_event_error_type(const unsigned int err_type)
  * @MEM_RDDR3:		Registered DDR3 RAM
  *			This is a variant of the DDR3 memories.
  * @MEM_LRDDR3:		Load-Reduced DDR3 memory.
+ * @MEM_LPDDR3:		Low-Power DDR3 memory.
  * @MEM_DDR4:		Unbuffered DDR4 RAM
  * @MEM_RDDR4:		Registered DDR4 RAM
  *			This is a variant of the DDR4 memories.
  * @MEM_LRDDR4:		Load-Reduced DDR4 memory.
+ * @MEM_LPDDR4:		Low-Power DDR4 memory.
+ * @MEM_DDR5:		Unbuffered DDR5 RAM
  * @MEM_NVDIMM:		Non-volatile RAM
+ * @MEM_WIO2:		Wide I/O 2.
  */
 enum mem_type {
 	MEM_EMPTY = 0,
@@ -200,10 +204,14 @@ enum mem_type {
 	MEM_DDR3,
 	MEM_RDDR3,
 	MEM_LRDDR3,
+	MEM_LPDDR3,
 	MEM_DDR4,
 	MEM_RDDR4,
 	MEM_LRDDR4,
+	MEM_LPDDR4,
+	MEM_DDR5,
 	MEM_NVDIMM,
+	MEM_WIO2,
 };
 
 #define MEM_FLAG_EMPTY		BIT(MEM_EMPTY)
@@ -223,13 +231,17 @@ enum mem_type {
 #define MEM_FLAG_XDR            BIT(MEM_XDR)
 #define MEM_FLAG_DDR3           BIT(MEM_DDR3)
 #define MEM_FLAG_RDDR3          BIT(MEM_RDDR3)
+#define MEM_FLAG_LPDDR3         BIT(MEM_LPDDR3)
 #define MEM_FLAG_DDR4           BIT(MEM_DDR4)
 #define MEM_FLAG_RDDR4          BIT(MEM_RDDR4)
 #define MEM_FLAG_LRDDR4         BIT(MEM_LRDDR4)
+#define MEM_FLAG_LPDDR4         BIT(MEM_LPDDR4)
+#define MEM_FLAG_DDR5           BIT(MEM_DDR5)
 #define MEM_FLAG_NVDIMM         BIT(MEM_NVDIMM)
+#define MEM_FLAG_WIO2		BIT(MEM_WIO2)
 
 /**
- * enum edac-type - Error Detection and Correction capabilities and mode
+ * enum edac_type - Error Detection and Correction capabilities and mode
  * @EDAC_UNKNOWN:	Unknown if ECC is available
  * @EDAC_NONE:		Doesn't support ECC
  * @EDAC_RESERVED:	Reserved ECC type
@@ -309,7 +321,7 @@ enum scrub_type {
 #define OP_OFFLINE		0x300
 
 /**
- * enum edac_mc_layer - memory controller hierarchy layer
+ * enum edac_mc_layer_type - memory controller hierarchy layer
  *
  * @EDAC_MC_LAYER_BRANCH:	memory layer is named "branch"
  * @EDAC_MC_LAYER_CHANNEL:	memory layer is named "channel"