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| author | Ben Zhang <benzh@chromium.org> | 2019-11-06 04:13:30 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-11-11 16:02:02 +0300 |
| commit | eabf424f7b60246c76dcb0ea6f1e83ef9abbeaa6 (patch) | |
| tree | 80a0e927ad50b2b9a1157df134de55703dcb13ba /sound/soc/codecs/rt5677.h | |
| parent | 29073ae40c472f17d42aa38850da861b5e3f912e (diff) | |
| download | linux-eabf424f7b60246c76dcb0ea6f1e83ef9abbeaa6.tar.xz | |
ASoC: rt5677: Mark reg RT5677_PWR_ANLG2 as volatile
The codec dies when RT5677_PWR_ANLG2(MX-64h) is set to 0xACE1
while it's streaming audio over SPI. The DSP firmware turns
on PLL2 (MX-64 bit 8) when SPI streaming starts. However regmap
does not believe that register can change by itself. When
BST1 (bit 15) is turned on with regmap_update_bits(), it doesn't
read the register first before write, so PLL2 power bit is
cleared by accident.
Marking MX-64h as volatile in regmap solved the issue.
Signed-off-by: Ben Zhang <benzh@chromium.org>
Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
Link: https://lore.kernel.org/r/20191106011335.223061-6-cujomalainey@chromium.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/rt5677.h')
0 files changed, 0 insertions, 0 deletions