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| author | Takashi Iwai <tiwai@suse.de> | 2023-06-26 16:38:02 +0300 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2023-06-26 16:38:02 +0300 |
| commit | d6048fdc870240e5020343f8af0c825829c232bd (patch) | |
| tree | d83ca76eaac5f8bf1c4c16f003aad64baa8fae62 /sound/soc/mediatek/mt8188/mt8188-afe-clk.h | |
| parent | a15b51375684c2bfa6017bb185139477e7a3b96c (diff) | |
| parent | 2d0cad0473bd1ffbc5842be0b9f2546265acb011 (diff) | |
| download | linux-d6048fdc870240e5020343f8af0c825829c232bd.tar.xz | |
Merge tag 'asoc-v6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
ASoC: Updates for v6.5
A fairly quiet release from a core and framework point of view, but a
very big one from the point of view of new drivers:
- More refectoring from Morimoto-san, this time mainly around DAI
links and how we control the ordering of trigger() callbacks.
- Convert a lot of drivers to use maple tree based caches.
- Lots of work on the x86 driver stack.
- Compressed audio support for Qualcomm.
- Support for AMD SoundWire, Analog Devices SSM3515, Google Chameleon,
Ingenic X1000, Intel systems with various CODECs, Longsoon platforms,
Maxim MAX98388, Mediatek MT8188, Nuvoton NAU8825C, NXP platforms with
NAU8822, Qualcomm WSA884x, StarFive JH7110, Texas Instruments TAS2781.
Diffstat (limited to 'sound/soc/mediatek/mt8188/mt8188-afe-clk.h')
| -rw-r--r-- | sound/soc/mediatek/mt8188/mt8188-afe-clk.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-clk.h b/sound/soc/mediatek/mt8188/mt8188-afe-clk.h index a4203a87a1e3..ec53c171c170 100644 --- a/sound/soc/mediatek/mt8188/mt8188-afe-clk.h +++ b/sound/soc/mediatek/mt8188/mt8188-afe-clk.h @@ -11,6 +11,10 @@ #ifndef _MT8188_AFE_CLK_H_ #define _MT8188_AFE_CLK_H_ +/* APLL */ +#define APLL1_W_NAME "APLL1" +#define APLL2_W_NAME "APLL2" + enum { /* xtal */ MT8188_CLK_XTAL_26M, @@ -18,13 +22,18 @@ enum { MT8188_CLK_APMIXED_APLL1, MT8188_CLK_APMIXED_APLL2, /* divider */ + MT8188_CLK_TOP_APLL1_D4, + MT8188_CLK_TOP_APLL2_D4, MT8188_CLK_TOP_APLL12_DIV0, MT8188_CLK_TOP_APLL12_DIV1, MT8188_CLK_TOP_APLL12_DIV2, MT8188_CLK_TOP_APLL12_DIV3, + MT8188_CLK_TOP_APLL12_DIV4, MT8188_CLK_TOP_APLL12_DIV9, /* mux */ MT8188_CLK_TOP_A1SYS_HP_SEL, + MT8188_CLK_TOP_A2SYS_SEL, + MT8188_CLK_TOP_AUD_IEC_SEL, MT8188_CLK_TOP_AUD_INTBUS_SEL, MT8188_CLK_TOP_AUDIO_H_SEL, MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL, @@ -99,6 +108,8 @@ struct mtk_base_afe; int mt8188_afe_get_mclk_source_clk_id(int sel); int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll); int mt8188_afe_get_default_mclk_source_by_rate(int rate); +int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate); +int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name); int mt8188_afe_init_clock(struct mtk_base_afe *afe); int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk); void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk); @@ -106,6 +117,10 @@ int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, unsigned int rate); int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, struct clk *parent); +int mt8188_apll1_enable(struct mtk_base_afe *afe); +int mt8188_apll1_disable(struct mtk_base_afe *afe); +int mt8188_apll2_enable(struct mtk_base_afe *afe); +int mt8188_apll2_disable(struct mtk_base_afe *afe); int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe); int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe); int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe); |