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authorAdrian Hunter <adrian.hunter@intel.com>2024-05-02 13:58:46 +0300
committerIngo Molnar <mingo@kernel.org>2024-05-02 14:13:42 +0300
commitb8000264348979b60dbe479255570a40e1b3a097 (patch)
tree3c4f8ce6cb6b7336b0dde61b5d8813701903e7d3 /tools/perf/builtin-version.c
parent59162e0c11d7257cde15f907d19fefe26da66692 (diff)
downloadlinux-b8000264348979b60dbe479255570a40e1b3a097.tar.xz
x86/insn: Add VEX versions of VPDPBUSD, VPDPBUSDS, VPDPWSSD and VPDPWSSDS
The x86 instruction decoder is used not only for decoding kernel instructions. It is also used by perf uprobes (user space probes) and by perf tools Intel Processor Trace decoding. Consequently, it needs to support instructions executed by user space also. Intel Architecture Instruction Set Extensions and Future Features manual number 319433-044 of May 2021, documented VEX versions of instructions VPDPBUSD, VPDPBUSDS, VPDPWSSD and VPDPWSSDS, but the opcode map has them listed as EVEX only. Remove EVEX-only (ev) annotation from instructions VPDPBUSD, VPDPBUSDS, VPDPWSSD and VPDPWSSDS, which allows them to be decoded with either a VEX or EVEX prefix. Fixes: 0153d98f2dd6 ("x86/insn: Add misc instructions to x86 instruction decoder") Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20240502105853.5338-4-adrian.hunter@intel.com
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