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| author | Thomas Renninger <trenn@suse.de> | 2011-07-21 13:54:54 +0400 |
|---|---|---|
| committer | Dominik Brodowski <linux@dominikbrodowski.net> | 2011-07-29 21:37:27 +0400 |
| commit | 029e9f73667f9b4661ac9886f706d75d26850260 (patch) | |
| tree | 4dd812e1de53d07695ce9b889482b032471a6889 /tools/power/cpupower/utils/helpers/cpuid.c | |
| parent | 8fb2e440b223b966f74a04a48f6f71f288fa671b (diff) | |
| download | linux-029e9f73667f9b4661ac9886f706d75d26850260.tar.xz | |
cpupower: Do detect IDA (opportunistic processor performance) via cpuid
IA32-Intel Devel guide Volume 3A - 14.3.2.1
-------------------------------------------
...
Opportunistic processor performance operation can be disabled by setting bit 38 of
IA32_MISC_ENABLES. This mechanism is intended for BIOS only. If
IA32_MISC_ENABLES[38] is set, CPUID.06H:EAX[1] will return 0.
Better detect things via cpuid, this cleans up the code a bit
and the MSR parts were not working correctly anyway.
Signed-off-by: Thomas Renninger <trenn@suse.de>
CC: lenb@kernel.org
CC: linux@dominikbrodowski.net
CC: cpufreq@vger.kernel.org
Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
Diffstat (limited to 'tools/power/cpupower/utils/helpers/cpuid.c')
| -rw-r--r-- | tools/power/cpupower/utils/helpers/cpuid.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/tools/power/cpupower/utils/helpers/cpuid.c b/tools/power/cpupower/utils/helpers/cpuid.c index a97f091fcf2b..906895d21cce 100644 --- a/tools/power/cpupower/utils/helpers/cpuid.c +++ b/tools/power/cpupower/utils/helpers/cpuid.c @@ -131,6 +131,12 @@ out: } if (cpu_info->vendor == X86_VENDOR_INTEL) { + if (cpuid_level >= 6 && + (cpuid_eax(6) & (1 << 1))) + cpu_info->caps |= CPUPOWER_CAP_INTEL_IDA; + } + + if (cpu_info->vendor == X86_VENDOR_INTEL) { /* Intel's perf-bias MSR support */ if (cpuid_level >= 6 && (cpuid_ecx(6) & (1 << 3))) cpu_info->caps |= CPUPOWER_CAP_PERF_BIAS; |