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| author | Dan Williams <dan.j.williams@intel.com> | 2023-06-15 04:30:43 +0300 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-06-26 00:31:33 +0300 |
| commit | 516b300c4ca86aa7953b75ce79b5c5eea5779b22 (patch) | |
| tree | 904fab8243e1b30d6aa89fba09207b67dd271208 /tools/testing/cxl | |
| parent | f3c8a37a432e65dda1384929198dd12c1df3ea38 (diff) | |
| download | linux-516b300c4ca86aa7953b75ce79b5c5eea5779b22.tar.xz | |
cxl/memdev: Formalize endpoint port linkage
Move the endpoint port that the cxl_mem driver establishes from drvdata
to a first class attribute. This is in preparation for device-memory
drivers reusing the CXL core for memory region management. Those drivers
need a type-safe method to retrieve their CXL port linkage. Leave
drvdata for private usage of the cxl_mem driver not external consumers
of a 'struct cxl_memdev' object.
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/168679264292.3436160.3901392135863405807.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/testing/cxl')
0 files changed, 0 insertions, 0 deletions