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| author | Vincent Chen <vincent.chen@sifive.com> | 2022-03-08 11:32:53 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-03-23 00:45:19 +0300 |
| commit | 6d1a6f464efd596779d1b272b3dc8170c5fa189f (patch) | |
| tree | 35f6444e6bae8e031bcefcb457bd0de3ebbfe16a /tools/testing/selftests/rseq/param_test.c | |
| parent | 93917ad50972e6298885d81b37b6a8602eb0b188 (diff) | |
| download | linux-6d1a6f464efd596779d1b272b3dc8170c5fa189f.tar.xz | |
rseq/selftests: Add support for RISC-V
Add support for RISC-V in the rseq selftests, which covers both
64-bit and 32-bit ISA with little endian mode.
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Tested-by: Eric Lin <eric.lin@sifive.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/testing/selftests/rseq/param_test.c')
| -rw-r--r-- | tools/testing/selftests/rseq/param_test.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/tools/testing/selftests/rseq/param_test.c b/tools/testing/selftests/rseq/param_test.c index 699ad5f93c34..0a6b8eafd444 100644 --- a/tools/testing/selftests/rseq/param_test.c +++ b/tools/testing/selftests/rseq/param_test.c @@ -207,6 +207,29 @@ unsigned int yield_mod_cnt, nr_abort; "addiu " INJECT_ASM_REG ", -1\n\t" \ "bnez " INJECT_ASM_REG ", 222b\n\t" \ "333:\n\t" +#elif defined(__riscv) + +#define RSEQ_INJECT_INPUT \ + , [loop_cnt_1]"m"(loop_cnt[1]) \ + , [loop_cnt_2]"m"(loop_cnt[2]) \ + , [loop_cnt_3]"m"(loop_cnt[3]) \ + , [loop_cnt_4]"m"(loop_cnt[4]) \ + , [loop_cnt_5]"m"(loop_cnt[5]) \ + , [loop_cnt_6]"m"(loop_cnt[6]) + +#define INJECT_ASM_REG "t1" + +#define RSEQ_INJECT_CLOBBER \ + , INJECT_ASM_REG + +#define RSEQ_INJECT_ASM(n) \ + "lw " INJECT_ASM_REG ", %[loop_cnt_" #n "]\n\t" \ + "beqz " INJECT_ASM_REG ", 333f\n\t" \ + "222:\n\t" \ + "addi " INJECT_ASM_REG "," INJECT_ASM_REG ", -1\n\t" \ + "bnez " INJECT_ASM_REG ", 222b\n\t" \ + "333:\n\t" + #else #error unsupported target |