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author | Marc Zyngier <maz@kernel.org> | 2023-04-21 11:44:58 +0300 |
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committer | Marc Zyngier <maz@kernel.org> | 2023-04-21 11:44:58 +0300 |
commit | 36fe1b29b3cae48f781011abd5a0b9e938f5b35f (patch) | |
tree | 74ae4b78cee40bdee6fa6653eeb84e6ffec07842 /tools/testing/selftests | |
parent | 6dcf7316e05eccded11fc640813c8a8879f271a6 (diff) | |
parent | bcf3e7da3ad3bfea38ac6ba9f56b99b2877af51f (diff) | |
download | linux-36fe1b29b3cae48f781011abd5a0b9e938f5b35f.tar.xz |
Merge branch kvm-arm64/spec-ptw into kvmarm-master/next
* kvm-arm64/spec-ptw:
: .
: On taking an exception from EL1&0 to EL2(&0), the page table walker is
: allowed to carry on with speculative walks started from EL1&0 while
: running at EL2 (see R_LFHQG). Given that the PTW may be actively using
: the EL1&0 system registers, the only safe way to deal with it is to
: issue a DSB before changing any of it.
:
: We already did the right thing for SPE and TRBE, but ignored the PTW
: for unknown reasons (probably because the architecture wasn't crystal
: clear at the time).
:
: This requires a bit of surgery in the nvhe code, though most of these
: patches are comments so that my future self can understand the purpose
: of these barriers. The VHE code is largely unaffected, thanks to the
: DSB in the context switch.
: .
KVM: arm64: vhe: Drop extra isb() on guest exit
KVM: arm64: vhe: Synchronise with page table walker on MMU update
KVM: arm64: pkvm: Document the side effects of kvm_flush_dcache_to_poc()
KVM: arm64: nvhe: Synchronise with page table walker on TLBI
KVM: arm64: nvhe: Synchronise with page table walker on vcpu run
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'tools/testing/selftests')
0 files changed, 0 insertions, 0 deletions