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| author | Marc Zyngier <maz@kernel.org> | 2023-03-30 20:47:58 +0300 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2023-03-30 21:01:10 +0300 |
| commit | 0630fb8e0a4873e436f0c1c1b27fa60a37eb960c (patch) | |
| tree | 30d3029a0949a68cfcaae7aa63d064b6ddb9431c /tools | |
| parent | 81dc9504a7006b484cfcf074796094ee526b0c45 (diff) | |
| download | linux-0630fb8e0a4873e436f0c1c1b27fa60a37eb960c.tar.xz | |
KVM: arm64: selftests: Add physical timer registers to the sysreg list
Now that KVM exposes CNTPCT_EL0, CNTP_CTL_EL0 and CNT_CVAL_EL0 to
userspace, add them to the get-reg-list selftest.
Reviewed-by: Colton Lewis <coltonlewis@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230330174800.2677007-19-maz@kernel.org
Diffstat (limited to 'tools')
| -rw-r--r-- | tools/testing/selftests/kvm/aarch64/get-reg-list.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c index d287dd2cac0a..1b976b333d2c 100644 --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c @@ -651,7 +651,7 @@ int main(int ac, char **av) * The current blessed list was primed with the output of kernel version * v4.15 with --core-reg-fixup and then later updated with new registers. * - * The blessed list is up to date with kernel version v5.13-rc3 + * The blessed list is up to date with kernel version v6.4 (or so we hope) */ static __u64 base_regs[] = { KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[0]), @@ -858,6 +858,9 @@ static __u64 base_regs[] = { ARM64_SYS_REG(3, 2, 0, 0, 0), /* CSSELR_EL1 */ ARM64_SYS_REG(3, 3, 13, 0, 2), /* TPIDR_EL0 */ ARM64_SYS_REG(3, 3, 13, 0, 3), /* TPIDRRO_EL0 */ + ARM64_SYS_REG(3, 3, 14, 0, 1), /* CNTPCT_EL0 */ + ARM64_SYS_REG(3, 3, 14, 2, 1), /* CNTP_CTL_EL0 */ + ARM64_SYS_REG(3, 3, 14, 2, 2), /* CNTP_CVAL_EL0 */ ARM64_SYS_REG(3, 4, 3, 0, 0), /* DACR32_EL2 */ ARM64_SYS_REG(3, 4, 5, 0, 1), /* IFSR32_EL2 */ ARM64_SYS_REG(3, 4, 5, 3, 0), /* FPEXC32_EL2 */ |