diff options
author | Marc Zyngier <maz@kernel.org> | 2023-04-21 11:31:17 +0300 |
---|---|---|
committer | Marc Zyngier <maz@kernel.org> | 2023-04-21 11:36:40 +0300 |
commit | b22498c4846b52a5df2cc821d97c4049df0cf67a (patch) | |
tree | 5d4bc7d1e9988924b85569255c161556fc270108 /tools | |
parent | ef5f97e9de9fc0d5bb6136de3d01d78c072a452f (diff) | |
parent | a6610435ac17de1ac727c90ad62c723d86c7ea36 (diff) | |
download | linux-b22498c4846b52a5df2cc821d97c4049df0cf67a.tar.xz |
Merge branch kvm-arm64/timer-vm-offsets into kvmarm-master/next
* kvm-arm64/timer-vm-offsets: (21 commits)
: .
: This series aims at satisfying multiple goals:
:
: - allow a VMM to atomically restore a timer offset for a whole VM
: instead of updating the offset each time a vcpu get its counter
: written
:
: - allow a VMM to save/restore the physical timer context, something
: that we cannot do at the moment due to the lack of offsetting
:
: - provide a framework that is suitable for NV support, where we get
: both global and per timer, per vcpu offsetting, and manage
: interrupts in a less braindead way.
:
: Conflict resolution involves using the new per-vcpu config lock instead
: of the home-grown timer lock.
: .
KVM: arm64: Handle 32bit CNTPCTSS traps
KVM: arm64: selftests: Augment existing timer test to handle variable offset
KVM: arm64: selftests: Deal with spurious timer interrupts
KVM: arm64: selftests: Add physical timer registers to the sysreg list
KVM: arm64: nv: timers: Support hyp timer emulation
KVM: arm64: nv: timers: Add a per-timer, per-vcpu offset
KVM: arm64: Document KVM_ARM_SET_CNT_OFFSETS and co
KVM: arm64: timers: Abstract the number of valid timers per vcpu
KVM: arm64: timers: Fast-track CNTPCT_EL0 trap handling
KVM: arm64: Elide kern_hyp_va() in VHE-specific parts of the hypervisor
KVM: arm64: timers: Move the timer IRQs into arch_timer_vm_data
KVM: arm64: timers: Abstract per-timer IRQ access
KVM: arm64: timers: Rationalise per-vcpu timer init
KVM: arm64: timers: Allow save/restoring of the physical timer
KVM: arm64: timers: Allow userspace to set the global counter offset
KVM: arm64: Expose {un,}lock_all_vcpus() to the rest of KVM
KVM: arm64: timers: Allow physical offset without CNTPOFF_EL2
KVM: arm64: timers: Use CNTPOFF_EL2 to offset the physical timer
arm64: Add HAS_ECV_CNTPOFF capability
arm64: Add CNTPOFF_EL2 register definition
...
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'tools')
-rw-r--r-- | tools/testing/selftests/kvm/aarch64/arch_timer.c | 56 | ||||
-rw-r--r-- | tools/testing/selftests/kvm/aarch64/get-reg-list.c | 5 |
2 files changed, 44 insertions, 17 deletions
diff --git a/tools/testing/selftests/kvm/aarch64/arch_timer.c b/tools/testing/selftests/kvm/aarch64/arch_timer.c index 26556a266021..8ef370924a02 100644 --- a/tools/testing/selftests/kvm/aarch64/arch_timer.c +++ b/tools/testing/selftests/kvm/aarch64/arch_timer.c @@ -47,6 +47,7 @@ struct test_args { int nr_iter; int timer_period_ms; int migration_freq_ms; + struct kvm_arm_counter_offset offset; }; static struct test_args test_args = { @@ -54,6 +55,7 @@ static struct test_args test_args = { .nr_iter = NR_TEST_ITERS_DEF, .timer_period_ms = TIMER_TEST_PERIOD_MS_DEF, .migration_freq_ms = TIMER_TEST_MIGRATION_FREQ_MS, + .offset = { .reserved = 1 }, }; #define msecs_to_usecs(msec) ((msec) * 1000LL) @@ -121,25 +123,35 @@ static void guest_validate_irq(unsigned int intid, uint64_t xcnt = 0, xcnt_diff_us, cval = 0; unsigned long xctl = 0; unsigned int timer_irq = 0; + unsigned int accessor; - if (stage == GUEST_STAGE_VTIMER_CVAL || - stage == GUEST_STAGE_VTIMER_TVAL) { - xctl = timer_get_ctl(VIRTUAL); - timer_set_ctl(VIRTUAL, CTL_IMASK); - xcnt = timer_get_cntct(VIRTUAL); - cval = timer_get_cval(VIRTUAL); + if (intid == IAR_SPURIOUS) + return; + + switch (stage) { + case GUEST_STAGE_VTIMER_CVAL: + case GUEST_STAGE_VTIMER_TVAL: + accessor = VIRTUAL; timer_irq = vtimer_irq; - } else if (stage == GUEST_STAGE_PTIMER_CVAL || - stage == GUEST_STAGE_PTIMER_TVAL) { - xctl = timer_get_ctl(PHYSICAL); - timer_set_ctl(PHYSICAL, CTL_IMASK); - xcnt = timer_get_cntct(PHYSICAL); - cval = timer_get_cval(PHYSICAL); + break; + case GUEST_STAGE_PTIMER_CVAL: + case GUEST_STAGE_PTIMER_TVAL: + accessor = PHYSICAL; timer_irq = ptimer_irq; - } else { + break; + default: GUEST_ASSERT(0); + return; } + xctl = timer_get_ctl(accessor); + if ((xctl & CTL_IMASK) || !(xctl & CTL_ENABLE)) + return; + + timer_set_ctl(accessor, CTL_IMASK); + xcnt = timer_get_cntct(accessor); + cval = timer_get_cval(accessor); + xcnt_diff_us = cycles_to_usec(xcnt - shared_data->xcnt); /* Make sure we are dealing with the correct timer IRQ */ @@ -148,6 +160,8 @@ static void guest_validate_irq(unsigned int intid, /* Basic 'timer condition met' check */ GUEST_ASSERT_3(xcnt >= cval, xcnt, cval, xcnt_diff_us); GUEST_ASSERT_1(xctl & CTL_ISTATUS, xctl); + + WRITE_ONCE(shared_data->nr_iter, shared_data->nr_iter + 1); } static void guest_irq_handler(struct ex_regs *regs) @@ -158,8 +172,6 @@ static void guest_irq_handler(struct ex_regs *regs) guest_validate_irq(intid, shared_data); - WRITE_ONCE(shared_data->nr_iter, shared_data->nr_iter + 1); - gic_set_eoi(intid); } @@ -372,6 +384,13 @@ static struct kvm_vm *test_vm_create(void) vm_init_descriptor_tables(vm); vm_install_exception_handler(vm, VECTOR_IRQ_CURRENT, guest_irq_handler); + if (!test_args.offset.reserved) { + if (kvm_has_cap(KVM_CAP_COUNTER_OFFSET)) + vm_ioctl(vm, KVM_ARM_SET_COUNTER_OFFSET, &test_args.offset); + else + TEST_FAIL("no support for global offset\n"); + } + for (i = 0; i < nr_vcpus; i++) vcpu_init_descriptor_tables(vcpus[i]); @@ -403,6 +422,7 @@ static void test_print_help(char *name) TIMER_TEST_PERIOD_MS_DEF); pr_info("\t-m: Frequency (in ms) of vCPUs to migrate to different pCPU. 0 to turn off (default: %u)\n", TIMER_TEST_MIGRATION_FREQ_MS); + pr_info("\t-o: Counter offset (in counter cycles, default: 0)\n"); pr_info("\t-h: print this help screen\n"); } @@ -410,7 +430,7 @@ static bool parse_args(int argc, char *argv[]) { int opt; - while ((opt = getopt(argc, argv, "hn:i:p:m:")) != -1) { + while ((opt = getopt(argc, argv, "hn:i:p:m:o:")) != -1) { switch (opt) { case 'n': test_args.nr_vcpus = atoi_positive("Number of vCPUs", optarg); @@ -429,6 +449,10 @@ static bool parse_args(int argc, char *argv[]) case 'm': test_args.migration_freq_ms = atoi_non_negative("Frequency", optarg); break; + case 'o': + test_args.offset.counter_offset = strtol(optarg, NULL, 0); + test_args.offset.reserved = 0; + break; case 'h': default: goto err; diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c index d287dd2cac0a..1b976b333d2c 100644 --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c @@ -651,7 +651,7 @@ int main(int ac, char **av) * The current blessed list was primed with the output of kernel version * v4.15 with --core-reg-fixup and then later updated with new registers. * - * The blessed list is up to date with kernel version v5.13-rc3 + * The blessed list is up to date with kernel version v6.4 (or so we hope) */ static __u64 base_regs[] = { KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(regs.regs[0]), @@ -858,6 +858,9 @@ static __u64 base_regs[] = { ARM64_SYS_REG(3, 2, 0, 0, 0), /* CSSELR_EL1 */ ARM64_SYS_REG(3, 3, 13, 0, 2), /* TPIDR_EL0 */ ARM64_SYS_REG(3, 3, 13, 0, 3), /* TPIDRRO_EL0 */ + ARM64_SYS_REG(3, 3, 14, 0, 1), /* CNTPCT_EL0 */ + ARM64_SYS_REG(3, 3, 14, 2, 1), /* CNTP_CTL_EL0 */ + ARM64_SYS_REG(3, 3, 14, 2, 2), /* CNTP_CVAL_EL0 */ ARM64_SYS_REG(3, 4, 3, 0, 0), /* DACR32_EL2 */ ARM64_SYS_REG(3, 4, 5, 0, 1), /* IFSR32_EL2 */ ARM64_SYS_REG(3, 4, 5, 3, 0), /* FPEXC32_EL2 */ |