diff options
| -rw-r--r-- | drivers/pci/pci.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 39a8932dc340..952b8a23f5df 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -19,6 +19,22 @@ */ #define PCIE_PME_TO_L2_TIMEOUT_US 10000 +/* + * As described in PCI base specification r6.0, section 6.6.1 <Conventional + * Reset>, there are two different use cases of the value: + * + * - "With a Downstream Port that does not support Link speeds greater + * than 5.0 GT/s, software must wait a minimum of 100 ms following exit + * from a Conventional Reset before sending a Configuration Request to + * the device immediately below that Port." + * + * - "With a Downstream Port that supports Link speeds greater than + * 5.0 GT/s, software must wait a minimum of 100 ms after Link training + * completes before sending a Configuration Request to the device + * immediately below that Port." + */ +#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100 + extern const unsigned char pcie_link_speed[]; extern bool pci_early_dump; |