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-rw-r--r--Documentation/devicetree/bindings/display/msm/dp-controller.yaml1
-rw-r--r--Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml9
-rw-r--r--MAINTAINERS20
-rw-r--r--drivers/gpu/drm/msm/.gitignore1
-rw-r--r--drivers/gpu/drm/msm/Kconfig8
-rw-r--r--drivers/gpu/drm/msm/Makefile106
-rw-r--r--drivers/gpu/drm/msm/adreno/a2xx.xml.h3251
-rw-r--r--drivers/gpu/drm/msm/adreno/a2xx_gpu.c4
-rw-r--r--drivers/gpu/drm/msm/adreno/a2xx_gpu.h4
-rw-r--r--drivers/gpu/drm/msm/adreno/a2xx_gpummu.c (renamed from drivers/gpu/drm/msm/msm_gpummu.c)45
-rw-r--r--drivers/gpu/drm/msm/adreno/a3xx.xml.h3268
-rw-r--r--drivers/gpu/drm/msm/adreno/a4xx.xml.h4379
-rw-r--r--drivers/gpu/drm/msm/adreno/a5xx.xml.h5572
-rw-r--r--drivers/gpu/drm/msm/adreno/a6xx.xml.h11858
-rw-r--r--drivers/gpu/drm/msm/adreno/a6xx_gmu.c2
-rw-r--r--drivers/gpu/drm/msm/adreno/a6xx_gmu.h12
-rw-r--r--drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h422
-rw-r--r--drivers/gpu/drm/msm/adreno/a6xx_gpu.c15
-rw-r--r--drivers/gpu/drm/msm/adreno/a6xx_gpu.h4
-rw-r--r--drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c83
-rw-r--r--drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h14
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_common.xml.h539
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h1446
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h2803
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c12
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c24
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h2
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c3
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c8
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c12
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c660
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h25
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c6
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h4
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c9
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c4
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c30
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h2
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h124
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c40
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h6
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c14
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h4
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c22
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h2
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c13
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h2
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c91
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c56
-rw-r--r--drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h8
-rw-r--r--drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h1181
-rw-r--r--drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c4
-rw-r--r--drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c1
-rw-r--r--drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h4
-rw-r--r--drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c129
-rw-r--r--drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h1979
-rw-r--r--drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h11
-rw-r--r--drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c7
-rw-r--r--drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c1
-rw-r--r--drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h4
-rw-r--r--drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c125
-rw-r--r--drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c4
-rw-r--r--drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h2
-rw-r--r--drivers/gpu/drm/msm/disp/mdp_common.xml.h111
-rw-r--r--drivers/gpu/drm/msm/disp/mdp_format.c630
-rw-r--r--drivers/gpu/drm/msm/disp/mdp_format.h77
-rw-r--r--drivers/gpu/drm/msm/disp/mdp_kms.h18
-rw-r--r--drivers/gpu/drm/msm/dp/dp_audio.c25
-rw-r--r--drivers/gpu/drm/msm/dp/dp_aux.c39
-rw-r--r--drivers/gpu/drm/msm/dp/dp_aux.h1
-rw-r--r--drivers/gpu/drm/msm/dp/dp_catalog.c71
-rw-r--r--drivers/gpu/drm/msm/dp/dp_catalog.h52
-rw-r--r--drivers/gpu/drm/msm/dp/dp_ctrl.c23
-rw-r--r--drivers/gpu/drm/msm/dp/dp_ctrl.h1
-rw-r--r--drivers/gpu/drm/msm/dp/dp_debug.c59
-rw-r--r--drivers/gpu/drm/msm/dp/dp_debug.h38
-rw-r--r--drivers/gpu/drm/msm/dp/dp_display.c101
-rw-r--r--drivers/gpu/drm/msm/dp/dp_display.h3
-rw-r--r--drivers/gpu/drm/msm/dp/dp_drm.c2
-rw-r--r--drivers/gpu/drm/msm/dp/dp_link.c26
-rw-r--r--drivers/gpu/drm/msm/dp/dp_link.h15
-rw-r--r--drivers/gpu/drm/msm/dp/dp_panel.c14
-rw-r--r--drivers/gpu/drm/msm/dp/dp_panel.h3
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi.c26
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi.h7
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi.xml.h790
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi_host.c20
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi_manager.c79
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h227
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h309
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h237
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h384
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h286
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h483
-rw-r--r--drivers/gpu/drm/msm/dsi/mmss_cc.xml.h131
-rw-r--r--drivers/gpu/drm/msm/dsi/phy/dsi_phy.h8
-rw-r--r--drivers/gpu/drm/msm/dsi/sfpb.xml.h70
-rw-r--r--drivers/gpu/drm/msm/hdmi/hdmi.c2
-rw-r--r--drivers/gpu/drm/msm/hdmi/hdmi.h10
-rw-r--r--drivers/gpu/drm/msm/hdmi/hdmi.xml.h1399
-rw-r--r--drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c6
-rw-r--r--drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c4
-rw-r--r--drivers/gpu/drm/msm/hdmi/qfprom.xml.h61
-rw-r--r--drivers/gpu/drm/msm/msm_drv.c3
-rw-r--r--drivers/gpu/drm/msm/msm_drv.h11
-rw-r--r--drivers/gpu/drm/msm/msm_fb.c12
-rw-r--r--drivers/gpu/drm/msm/msm_gpu.c2
-rw-r--r--drivers/gpu/drm/msm/msm_gpu.h12
-rw-r--r--drivers/gpu/drm/msm/msm_kms.h4
-rw-r--r--drivers/gpu/drm/msm/msm_mmu.h5
-rw-r--r--drivers/gpu/drm/msm/registers/.gitignore4
-rw-r--r--drivers/gpu/drm/msm/registers/adreno/a2xx.xml1865
-rw-r--r--drivers/gpu/drm/msm/registers/adreno/a3xx.xml1751
-rw-r--r--drivers/gpu/drm/msm/registers/adreno/a4xx.xml2409
-rw-r--r--drivers/gpu/drm/msm/registers/adreno/a5xx.xml3039
-rw-r--r--drivers/gpu/drm/msm/registers/adreno/a6xx.xml5011
-rw-r--r--drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml228
-rw-r--r--drivers/gpu/drm/msm/registers/adreno/adreno_common.xml400
-rw-r--r--drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml2268
-rw-r--r--drivers/gpu/drm/msm/registers/display/dsi.xml390
-rw-r--r--drivers/gpu/drm/msm/registers/display/dsi_phy_10nm.xml102
-rw-r--r--drivers/gpu/drm/msm/registers/display/dsi_phy_14nm.xml135
-rw-r--r--drivers/gpu/drm/msm/registers/display/dsi_phy_20nm.xml100
-rw-r--r--drivers/gpu/drm/msm/registers/display/dsi_phy_28nm.xml180
-rw-r--r--drivers/gpu/drm/msm/registers/display/dsi_phy_28nm_8960.xml134
-rw-r--r--drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml230
-rw-r--r--drivers/gpu/drm/msm/registers/display/edp.xml239
-rw-r--r--drivers/gpu/drm/msm/registers/display/hdmi.xml1015
-rw-r--r--drivers/gpu/drm/msm/registers/display/mdp4.xml504
-rw-r--r--drivers/gpu/drm/msm/registers/display/mdp5.xml806
-rw-r--r--drivers/gpu/drm/msm/registers/display/mdp_common.xml90
-rw-r--r--drivers/gpu/drm/msm/registers/display/msm.xml32
-rw-r--r--drivers/gpu/drm/msm/registers/display/sfpb.xml17
-rw-r--r--drivers/gpu/drm/msm/registers/freedreno_copyright.xml40
-rw-r--r--drivers/gpu/drm/msm/registers/gen_header.py970
-rw-r--r--drivers/gpu/drm/msm/registers/rules-fd.xsd404
-rw-r--r--drivers/phy/qualcomm/phy-qcom-edp.c76
-rw-r--r--include/linux/phy/phy-dp.h3
138 files changed, 25419 insertions, 41421 deletions
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index ae53cbfb2193..97993feda193 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -29,6 +29,7 @@ properties:
- qcom,sm8650-dp
- items:
- enum:
+ - qcom,sm6350-dp
- qcom,sm8150-dp
- qcom,sm8250-dp
- qcom,sm8450-dp
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
index c9ba1fae8042..bba666bdffe5 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml
@@ -53,6 +53,15 @@ patternProperties:
compatible:
const: qcom,sm6350-dpu
+ "^displayport-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+
+ properties:
+ compatible:
+ contains:
+ const: qcom,sm6350-dp
+
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
diff --git a/MAINTAINERS b/MAINTAINERS
index abd4dbe2c653..d7cfe9895a44 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6816,7 +6816,25 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: Documentation/devicetree/bindings/display/panel/panel-mipi-dbi-spi.yaml
F: drivers/gpu/drm/tiny/panel-mipi-dbi.c
-DRM DRIVER FOR MSM ADRENO GPU
+DRM DRIVER for Qualcomm Adreno GPUs
+M: Rob Clark <robdclark@gmail.com>
+R: Sean Paul <sean@poorly.run>
+R: Konrad Dybcio <konrad.dybcio@linaro.org>
+L: linux-arm-msm@vger.kernel.org
+L: dri-devel@lists.freedesktop.org
+L: freedreno@lists.freedesktop.org
+S: Maintained
+B: https://gitlab.freedesktop.org/drm/msm/-/issues
+T: git https://gitlab.freedesktop.org/drm/msm.git
+F: Documentation/devicetree/bindings/display/msm/gpu.yaml
+F: drivers/gpu/drm/msm/adreno/
+F: drivers/gpu/drm/msm/msm_gpu.*
+F: drivers/gpu/drm/msm/msm_gpu_devfreq.*
+F: drivers/gpu/drm/msm/msm_ringbuffer.*
+F: drivers/gpu/drm/msm/registers/adreno/
+F: include/uapi/drm/msm_drm.h
+
+DRM DRIVER for Qualcomm display hardware
M: Rob Clark <robdclark@gmail.com>
M: Abhinav Kumar <quic_abhinavk@quicinc.com>
M: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
diff --git a/drivers/gpu/drm/msm/.gitignore b/drivers/gpu/drm/msm/.gitignore
new file mode 100644
index 000000000000..9ab870da897d
--- /dev/null
+++ b/drivers/gpu/drm/msm/.gitignore
@@ -0,0 +1 @@
+generated/
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index f7708590583e..cd03e1ad4e3c 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -54,6 +54,14 @@ config DRM_MSM_GPU_SUDO
Only use this if you are a driver developer. This should *not*
be enabled for production kernels. If unsure, say N.
+config DRM_MSM_VALIDATE_XML
+ bool "Validate XML register files against schema"
+ depends on DRM_MSM && EXPERT
+ depends on $(success,$(PYTHON3) -c "import lxml")
+ help
+ Validate XML files with register definitions against rules-fd schema.
+ This option is mostly targeting DRM MSM developers. If unsure, say N.
+
config DRM_MSM_MDSS
bool
depends on DRM_MSM
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index b21ae2880c71..718968717ad5 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -1,13 +1,15 @@
# SPDX-License-Identifier: GPL-2.0
ccflags-y := -I $(srctree)/$(src)
+ccflags-y += -I $(obj)/generated
ccflags-y += -I $(srctree)/$(src)/disp/dpu1
ccflags-$(CONFIG_DRM_MSM_DSI) += -I $(srctree)/$(src)/dsi
ccflags-$(CONFIG_DRM_MSM_DP) += -I $(srctree)/$(src)/dp
-msm-y := \
+adreno-y := \
adreno/adreno_device.o \
adreno/adreno_gpu.o \
adreno/a2xx_gpu.o \
+ adreno/a2xx_gpummu.o \
adreno/a3xx_gpu.o \
adreno/a4xx_gpu.o \
adreno/a5xx_gpu.o \
@@ -17,7 +19,11 @@ msm-y := \
adreno/a6xx_gmu.o \
adreno/a6xx_hfi.o \
-msm-$(CONFIG_DRM_MSM_HDMI) += \
+adreno-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
+
+adreno-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o
+
+msm-display-$(CONFIG_DRM_MSM_HDMI) += \
hdmi/hdmi.o \
hdmi/hdmi_audio.o \
hdmi/hdmi_bridge.o \
@@ -30,7 +36,7 @@ msm-$(CONFIG_DRM_MSM_HDMI) += \
hdmi/hdmi_phy_8x74.o \
hdmi/hdmi_pll_8960.o \
-msm-$(CONFIG_DRM_MSM_MDP4) += \
+msm-display-$(CONFIG_DRM_MSM_MDP4) += \
disp/mdp4/mdp4_crtc.o \
disp/mdp4/mdp4_dsi_encoder.o \
disp/mdp4/mdp4_dtv_encoder.o \
@@ -41,7 +47,7 @@ msm-$(CONFIG_DRM_MSM_MDP4) += \
disp/mdp4/mdp4_kms.o \
disp/mdp4/mdp4_plane.o \
-msm-$(CONFIG_DRM_MSM_MDP5) += \
+msm-display-$(CONFIG_DRM_MSM_MDP5) += \
disp/mdp5/mdp5_cfg.o \
disp/mdp5/mdp5_cmd_encoder.o \
disp/mdp5/mdp5_ctl.o \
@@ -54,7 +60,7 @@ msm-$(CONFIG_DRM_MSM_MDP5) += \
disp/mdp5/mdp5_plane.o \
disp/mdp5/mdp5_smp.o \
-msm-$(CONFIG_DRM_MSM_DPU) += \
+msm-display-$(CONFIG_DRM_MSM_DPU) += \
disp/dpu1/dpu_core_perf.o \
disp/dpu1/dpu_crtc.o \
disp/dpu1/dpu_encoder.o \
@@ -84,14 +90,16 @@ msm-$(CONFIG_DRM_MSM_DPU) += \
disp/dpu1/dpu_vbif.o \
disp/dpu1/dpu_writeback.o
-msm-$(CONFIG_DRM_MSM_MDSS) += \
+msm-display-$(CONFIG_DRM_MSM_MDSS) += \
msm_mdss.o \
-msm-y += \
+msm-display-y += \
disp/mdp_format.o \
disp/mdp_kms.o \
disp/msm_disp_snapshot.o \
disp/msm_disp_snapshot_util.o \
+
+msm-y += \
msm_atomic.o \
msm_atomic_tracepoints.o \
msm_debugfs.o \
@@ -113,14 +121,13 @@ msm-y += \
msm_ringbuffer.o \
msm_submitqueue.o \
msm_gpu_tracepoints.o \
- msm_gpummu.o
-msm-$(CONFIG_DEBUG_FS) += adreno/a5xx_debugfs.o \
- dp/dp_debug.o
+msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
-msm-$(CONFIG_DRM_MSM_GPU_STATE) += adreno/a6xx_gpu_state.o
+msm-display-$(CONFIG_DEBUG_FS) += \
+ dp/dp_debug.o
-msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
+msm-display-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
dp/dp_catalog.o \
dp/dp_ctrl.o \
dp/dp_display.o \
@@ -130,21 +137,76 @@ msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \
dp/dp_audio.o \
dp/dp_utils.o
-msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o
-
-msm-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o
+msm-display-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o
-msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
+msm-display-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
dsi/dsi_cfg.o \
dsi/dsi_host.o \
dsi/dsi_manager.o \
dsi/phy/dsi_phy.o
-msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
-msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
-msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o
-msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o
-msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o
-msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o
+msm-display-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
+msm-display-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
+msm-display-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o
+msm-display-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o
+msm-display-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o
+msm-display-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o
+
+msm-y += $(adreno-y) $(msm-display-y)
obj-$(CONFIG_DRM_MSM) += msm.o
+
+ifeq (y,$(CONFIG_DRM_MSM_VALIDATE_XML))
+ headergen-opts += --validate
+else
+ headergen-opts += --no-validate
+endif
+
+quiet_cmd_headergen = GENHDR $@
+ cmd_headergen = mkdir -p $(obj)/generated && $(PYTHON3) $(srctree)/$(src)/registers/gen_header.py \
+ $(headergen-opts) --rnn $(srctree)/$(src)/registers --xml $< c-defines > $@
+
+$(obj)/generated/%.xml.h: $(src)/registers/adreno/%.xml \
+ $(src)/registers/adreno/adreno_common.xml \
+ $(src)/registers/adreno/adreno_pm4.xml \
+ $(src)/registers/freedreno_copyright.xml \
+ $(src)/registers/gen_header.py \
+ $(src)/registers/rules-fd.xsd \
+ FORCE
+ $(call if_changed,headergen)
+
+$(obj)/generated/%.xml.h: $(src)/registers/display/%.xml \
+ $(src)/registers/freedreno_copyright.xml \
+ $(src)/registers/gen_header.py \
+ $(src)/registers/rules-fd.xsd \
+ FORCE
+ $(call if_changed,headergen)
+
+ADRENO_HEADERS = \
+ generated/a2xx.xml.h \
+ generated/a3xx.xml.h \
+ generated/a4xx.xml.h \
+ generated/a5xx.xml.h \
+ generated/a6xx.xml.h \
+ generated/a6xx_gmu.xml.h \
+ generated/adreno_common.xml.h \
+ generated/adreno_pm4.xml.h \
+
+DISPLAY_HEADERS = \
+ generated/dsi_phy_7nm.xml.h \
+ generated/dsi_phy_10nm.xml.h \
+ generated/dsi_phy_14nm.xml.h \
+ generated/dsi_phy_20nm.xml.h \
+ generated/dsi_phy_28nm_8960.xml.h \
+ generated/dsi_phy_28nm.xml.h \
+ generated/dsi.xml.h \
+ generated/hdmi.xml.h \
+ generated/mdp4.xml.h \
+ generated/mdp5.xml.h \
+ generated/mdp_common.xml.h \
+ generated/sfpb.xml.h
+
+$(addprefix $(obj)/,$(adreno-y)): $(addprefix $(obj)/,$(ADRENO_HEADERS))
+$(addprefix $(obj)/,$(msm-display-y)): $(addprefix $(obj)/,$(DISPLAY_HEADERS))
+
+targets += $(ADRENO_HEADERS) $(DISPLAY_HEADERS)
diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
deleted file mode 100644
index 23141cbcea97..000000000000
--- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h
+++ /dev/null
@@ -1,3251 +0,0 @@
-#ifndef A2XX_XML
-#define A2XX_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
-http://gitlab.freedesktop.org/mesa/mesa/
-git clone https://gitlab.freedesktop.org/mesa/mesa.git
-
-The rules-ng-ng source files this header was generated from are:
-
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from Fri Jun 2 14:59:26 2023)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024)
-
-Copyright (C) 2013-2024 by the following authors:
-- Rob Clark <robdclark@gmail.com> Rob Clark
-- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-*/
-
-#ifdef __KERNEL__
-#include <linux/bug.h>
-#define assert(x) BUG_ON(!(x))
-#else
-#include <assert.h>
-#endif
-
-#ifdef __cplusplus
-#define __struct_cast(X)
-#else
-#define __struct_cast(X) (struct X)
-#endif
-
-enum a2xx_rb_dither_type {
- DITHER_PIXEL = 0,
- DITHER_SUBPIXEL = 1,
-};
-
-enum a2xx_colorformatx {
- COLORX_4_4_4_4 = 0,
- COLORX_1_5_5_5 = 1,
- COLORX_5_6_5 = 2,
- COLORX_8 = 3,
- COLORX_8_8 = 4,
- COLORX_8_8_8_8 = 5,
- COLORX_S8_8_8_8 = 6,
- COLORX_16_FLOAT = 7,
- COLORX_16_16_FLOAT = 8,
- COLORX_16_16_16_16_FLOAT = 9,
- COLORX_32_FLOAT = 10,
- COLORX_32_32_FLOAT = 11,
- COLORX_32_32_32_32_FLOAT = 12,
- COLORX_2_3_3 = 13,
- COLORX_8_8_8 = 14,
-};
-
-enum a2xx_sq_surfaceformat {
- FMT_1_REVERSE = 0,
- FMT_1 = 1,
- FMT_8 = 2,
- FMT_1_5_5_5 = 3,
- FMT_5_6_5 = 4,
- FMT_6_5_5 = 5,
- FMT_8_8_8_8 = 6,
- FMT_2_10_10_10 = 7,
- FMT_8_A = 8,
- FMT_8_B = 9,
- FMT_8_8 = 10,
- FMT_Cr_Y1_Cb_Y0 = 11,
- FMT_Y1_Cr_Y0_Cb = 12,
- FMT_5_5_5_1 = 13,
- FMT_8_8_8_8_A = 14,
- FMT_4_4_4_4 = 15,
- FMT_8_8_8 = 16,
- FMT_DXT1 = 18,
- FMT_DXT2_3 = 19,
- FMT_DXT4_5 = 20,
- FMT_10_10_10_2 = 21,
- FMT_24_8 = 22,
- FMT_16 = 24,
- FMT_16_16 = 25,
- FMT_16_16_16_16 = 26,
- FMT_16_EXPAND = 27,
- FMT_16_16_EXPAND = 28,
- FMT_16_16_16_16_EXPAND = 29,
- FMT_16_FLOAT = 30,
- FMT_16_16_FLOAT = 31,
- FMT_16_16_16_16_FLOAT = 32,
- FMT_32 = 33,
- FMT_32_32 = 34,
- FMT_32_32_32_32 = 35,
- FMT_32_FLOAT = 36,
- FMT_32_32_FLOAT = 37,
- FMT_32_32_32_32_FLOAT = 38,
- FMT_ATI_TC_RGB = 39,
- FMT_ATI_TC_RGBA = 40,
- FMT_ATI_TC_555_565_RGB = 41,
- FMT_ATI_TC_555_565_RGBA = 42,
- FMT_ATI_TC_RGBA_INTERP = 43,
- FMT_ATI_TC_555_565_RGBA_INTERP = 44,
- FMT_ETC1_RGBA_INTERP = 46,
- FMT_ETC1_RGB = 47,
- FMT_ETC1_RGBA = 48,
- FMT_DXN = 49,
- FMT_2_3_3 = 51,
- FMT_2_10_10_10_AS_16_16_16_16 = 54,
- FMT_10_10_10_2_AS_16_16_16_16 = 55,
- FMT_32_32_32_FLOAT = 57,
- FMT_DXT3A = 58,
- FMT_DXT5A = 59,
- FMT_CTX1 = 60,
-};
-
-enum a2xx_sq_ps_vtx_mode {
- POSITION_1_VECTOR = 0,
- POSITION_2_VECTORS_UNUSED = 1,
- POSITION_2_VECTORS_SPRITE = 2,
- POSITION_2_VECTORS_EDGE = 3,
- POSITION_2_VECTORS_KILL = 4,
- POSITION_2_VECTORS_SPRITE_KILL = 5,
- POSITION_2_VECTORS_EDGE_KILL = 6,
- MULTIPASS = 7,
-};
-
-enum a2xx_sq_sample_cntl {
- CENTROIDS_ONLY = 0,
- CENTERS_ONLY = 1,
- CENTROIDS_AND_CENTERS = 2,
-};
-
-enum a2xx_dx_clip_space {
- DXCLIP_OPENGL = 0,
- DXCLIP_DIRECTX = 1,
-};
-
-enum a2xx_pa_su_sc_polymode {
- POLY_DISABLED = 0,
- POLY_DUALMODE = 1,
-};
-
-enum a2xx_rb_edram_mode {
- EDRAM_NOP = 0,
- COLOR_DEPTH = 4,
- DEPTH_ONLY = 5,
- EDRAM_COPY = 6,
-};
-
-enum a2xx_pa_sc_pattern_bit_order {
- LITTLE = 0,
- BIG = 1,
-};
-
-enum a2xx_pa_sc_auto_reset_cntl {
- NEVER = 0,
- EACH_PRIMITIVE = 1,
- EACH_PACKET = 2,
-};
-
-enum a2xx_pa_pixcenter {
- PIXCENTER_D3D = 0,
- PIXCENTER_OGL = 1,
-};
-
-enum a2xx_pa_roundmode {
- TRUNCATE = 0,
- ROUND = 1,
- ROUNDTOEVEN = 2,
- ROUNDTOODD = 3,
-};
-
-enum a2xx_pa_quantmode {
- ONE_SIXTEENTH = 0,
- ONE_EIGTH = 1,
- ONE_QUARTER = 2,
- ONE_HALF = 3,
- ONE = 4,
-};
-
-enum a2xx_rb_copy_sample_select {
- SAMPLE_0 = 0,
- SAMPLE_1 = 1,
- SAMPLE_2 = 2,
- SAMPLE_3 = 3,
- SAMPLE_01 = 4,
- SAMPLE_23 = 5,
- SAMPLE_0123 = 6,
-};
-
-enum a2xx_rb_blend_opcode {
- BLEND2_DST_PLUS_SRC = 0,
- BLEND2_SRC_MINUS_DST = 1,
- BLEND2_MIN_DST_SRC = 2,
- BLEND2_MAX_DST_SRC = 3,
- BLEND2_DST_MINUS_SRC = 4,
- BLEND2_DST_PLUS_SRC_BIAS = 5,
-};
-
-enum a2xx_su_perfcnt_select {
- PERF_PAPC_PASX_REQ = 0,
- PERF_PAPC_PASX_FIRST_VECTOR = 2,
- PERF_PAPC_PASX_SECOND_VECTOR = 3,
- PERF_PAPC_PASX_FIRST_DEAD = 4,
- PERF_PAPC_PASX_SECOND_DEAD = 5,
- PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
- PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
- PERF_PAPC_PA_INPUT_PRIM = 8,
- PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
- PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
- PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
- PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
- PERF_PAPC_CLPR_CULL_PRIM = 13,
- PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
- PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
- PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
- PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
- PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
- PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
- PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
- PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
- PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
- PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
- PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
- PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
- PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
- PERF_PAPC_CLSM_NULL_PRIM = 36,
- PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
- PERF_PAPC_CLSM_CLIP_PRIM = 38,
- PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
- PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
- PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
- PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
- PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
- PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
- PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
- PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
- PERF_PAPC_SU_INPUT_PRIM = 47,
- PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
- PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
- PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
- PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
- PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
- PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
- PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
- PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
- PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
- PERF_PAPC_SU_OUTPUT_PRIM = 57,
- PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
- PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
- PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
- PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
- PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
- PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
- PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
- PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
- PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
- PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
- PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
- PERF_PAPC_PASX_REQ_IDLE = 69,
- PERF_PAPC_PASX_REQ_BUSY = 70,
- PERF_PAPC_PASX_REQ_STALLED = 71,
- PERF_PAPC_PASX_REC_IDLE = 72,
- PERF_PAPC_PASX_REC_BUSY = 73,
- PERF_PAPC_PASX_REC_STARVED_SX = 74,
- PERF_PAPC_PASX_REC_STALLED = 75,
- PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
- PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
- PERF_PAPC_CCGSM_IDLE = 78,
- PERF_PAPC_CCGSM_BUSY = 79,
- PERF_PAPC_CCGSM_STALLED = 80,
- PERF_PAPC_CLPRIM_IDLE = 81,
- PERF_PAPC_CLPRIM_BUSY = 82,
- PERF_PAPC_CLPRIM_STALLED = 83,
- PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
- PERF_PAPC_CLIPSM_IDLE = 85,
- PERF_PAPC_CLIPSM_BUSY = 86,
- PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
- PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
- PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
- PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
- PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
- PERF_PAPC_CLIPGA_IDLE = 92,
- PERF_PAPC_CLIPGA_BUSY = 93,
- PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
- PERF_PAPC_CLIPGA_STALLED = 95,
- PERF_PAPC_CLIP_IDLE = 96,
- PERF_PAPC_CLIP_BUSY = 97,
- PERF_PAPC_SU_IDLE = 98,
- PERF_PAPC_SU_BUSY = 99,
- PERF_PAPC_SU_STARVED_CLIP = 100,
- PERF_PAPC_SU_STALLED_SC = 101,
- PERF_PAPC_SU_FACENESS_CULL = 102,
-};
-
-enum a2xx_sc_perfcnt_select {
- SC_SR_WINDOW_VALID = 0,
- SC_CW_WINDOW_VALID = 1,
- SC_QM_WINDOW_VALID = 2,
- SC_FW_WINDOW_VALID = 3,
- SC_EZ_WINDOW_VALID = 4,
- SC_IT_WINDOW_VALID = 5,
- SC_STARVED_BY_PA = 6,
- SC_STALLED_BY_RB_TILE = 7,
- SC_STALLED_BY_RB_SAMP = 8,
- SC_STARVED_BY_RB_EZ = 9,
- SC_STALLED_BY_SAMPLE_FF = 10,
- SC_STALLED_BY_SQ = 11,
- SC_STALLED_BY_SP = 12,
- SC_TOTAL_NO_PRIMS = 13,
- SC_NON_EMPTY_PRIMS = 14,
- SC_NO_TILES_PASSING_QM = 15,
- SC_NO_PIXELS_PRE_EZ = 16,
- SC_NO_PIXELS_POST_EZ = 17,
-};
-
-enum a2xx_vgt_perfcount_select {
- VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
- VGT_SQ_SEND = 1,
- VGT_SQ_STALLED = 2,
- VGT_SQ_STARVED_BUSY = 3,
- VGT_SQ_STARVED_IDLE = 4,
- VGT_SQ_STATIC = 5,
- VGT_PA_EVENT_WINDOW_ACTIVE = 6,
- VGT_PA_CLIP_V_SEND = 7,
- VGT_PA_CLIP_V_STALLED = 8,
- VGT_PA_CLIP_V_STARVED_BUSY = 9,
- VGT_PA_CLIP_V_STARVED_IDLE = 10,
- VGT_PA_CLIP_V_STATIC = 11,
- VGT_PA_CLIP_P_SEND = 12,
- VGT_PA_CLIP_P_STALLED = 13,
- VGT_PA_CLIP_P_STARVED_BUSY = 14,
- VGT_PA_CLIP_P_STARVED_IDLE = 15,
- VGT_PA_CLIP_P_STATIC = 16,
- VGT_PA_CLIP_S_SEND = 17,
- VGT_PA_CLIP_S_STALLED = 18,
- VGT_PA_CLIP_S_STARVED_BUSY = 19,
- VGT_PA_CLIP_S_STARVED_IDLE = 20,
- VGT_PA_CLIP_S_STATIC = 21,
- RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
- RBIU_IMMED_DATA_FIFO_STARVED = 23,
- RBIU_IMMED_DATA_FIFO_STALLED = 24,
- RBIU_DMA_REQUEST_FIFO_STARVED = 25,
- RBIU_DMA_REQUEST_FIFO_STALLED = 26,
- RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
- RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
- BIN_PRIM_NEAR_CULL = 29,
- BIN_PRIM_ZERO_CULL = 30,
- BIN_PRIM_FAR_CULL = 31,
- BIN_PRIM_BIN_CULL = 32,
- BIN_PRIM_FACE_CULL = 33,
- SPARE34 = 34,
- SPARE35 = 35,
- SPARE36 = 36,
- SPARE37 = 37,
- SPARE38 = 38,
- SPARE39 = 39,
- TE_SU_IN_VALID = 40,
- TE_SU_IN_READ = 41,
- TE_SU_IN_PRIM = 42,
- TE_SU_IN_EOP = 43,
- TE_SU_IN_NULL_PRIM = 44,
- TE_WK_IN_VALID = 45,
- TE_WK_IN_READ = 46,
- TE_OUT_PRIM_VALID = 47,
- TE_OUT_PRIM_READ = 48,
-};
-
-enum a2xx_tcr_perfcount_select {
- DGMMPD_IPMUX0_STALL = 0,
- DGMMPD_IPMUX_ALL_STALL = 4,
- OPMUX0_L2_WRITES = 5,
-};
-
-enum a2xx_tp_perfcount_select {
- POINT_QUADS = 0,
- BILIN_QUADS = 1,
- ANISO_QUADS = 2,
- MIP_QUADS = 3,
- VOL_QUADS = 4,
- MIP_VOL_QUADS = 5,
- MIP_ANISO_QUADS = 6,
- VOL_ANISO_QUADS = 7,
- ANISO_2_1_QUADS = 8,
- ANISO_4_1_QUADS = 9,
- ANISO_6_1_QUADS = 10,
- ANISO_8_1_QUADS = 11,
- ANISO_10_1_QUADS = 12,
- ANISO_12_1_QUADS = 13,
- ANISO_14_1_QUADS = 14,
- ANISO_16_1_QUADS = 15,
- MIP_VOL_ANISO_QUADS = 16,
- ALIGN_2_QUADS = 17,
- ALIGN_4_QUADS = 18,
- PIX_0_QUAD = 19,
- PIX_1_QUAD = 20,
- PIX_2_QUAD = 21,
- PIX_3_QUAD = 22,
- PIX_4_QUAD = 23,
- TP_MIPMAP_LOD0 = 24,
- TP_MIPMAP_LOD1 = 25,
- TP_MIPMAP_LOD2 = 26,
- TP_MIPMAP_LOD3 = 27,
- TP_MIPMAP_LOD4 = 28,
- TP_MIPMAP_LOD5 = 29,
- TP_MIPMAP_LOD6 = 30,
- TP_MIPMAP_LOD7 = 31,
- TP_MIPMAP_LOD8 = 32,
- TP_MIPMAP_LOD9 = 33,
- TP_MIPMAP_LOD10 = 34,
- TP_MIPMAP_LOD11 = 35,
- TP_MIPMAP_LOD12 = 36,
- TP_MIPMAP_LOD13 = 37,
- TP_MIPMAP_LOD14 = 38,
-};
-
-enum a2xx_tcm_perfcount_select {
- QUAD0_RD_LAT_FIFO_EMPTY = 0,
- QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
- QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
- QUAD0_RD_LAT_FIFO_FULL = 5,
- QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
- READ_STARVED_QUAD0 = 28,
- READ_STARVED = 32,
- READ_STALLED_QUAD0 = 33,
- READ_STALLED = 37,
- VALID_READ_QUAD0 = 38,
- TC_TP_STARVED_QUAD0 = 42,
- TC_TP_STARVED = 46,
-};
-
-enum a2xx_tcf_perfcount_select {
- VALID_CYCLES = 0,
- SINGLE_PHASES = 1,
- ANISO_PHASES = 2,
- MIP_PHASES = 3,
- VOL_PHASES = 4,
- MIP_VOL_PHASES = 5,
- MIP_ANISO_PHASES = 6,
- VOL_ANISO_PHASES = 7,
- ANISO_2_1_PHASES = 8,
- ANISO_4_1_PHASES = 9,
- ANISO_6_1_PHASES = 10,
- ANISO_8_1_PHASES = 11,
- ANISO_10_1_PHASES = 12,
- ANISO_12_1_PHASES = 13,
- ANISO_14_1_PHASES = 14,
- ANISO_16_1_PHASES = 15,
- MIP_VOL_ANISO_PHASES = 16,
- ALIGN_2_PHASES = 17,
- ALIGN_4_PHASES = 18,
- TPC_BUSY = 19,
- TPC_STALLED = 20,
- TPC_STARVED = 21,
- TPC_WORKING = 22,
- TPC_WALKER_BUSY = 23,
- TPC_WALKER_STALLED = 24,
- TPC_WALKER_WORKING = 25,
- TPC_ALIGNER_BUSY = 26,
- TPC_ALIGNER_STALLED = 27,
- TPC_ALIGNER_STALLED_BY_BLEND = 28,
- TPC_ALIGNER_STALLED_BY_CACHE = 29,
- TPC_ALIGNER_WORKING = 30,
- TPC_BLEND_BUSY = 31,
- TPC_BLEND_SYNC = 32,
- TPC_BLEND_STARVED = 33,
- TPC_BLEND_WORKING = 34,
- OPCODE_0x00 = 35,
- OPCODE_0x01 = 36,
- OPCODE_0x04 = 37,
- OPCODE_0x10 = 38,
- OPCODE_0x11 = 39,
- OPCODE_0x12 = 40,
- OPCODE_0x13 = 41,
- OPCODE_0x18 = 42,
- OPCODE_0x19 = 43,
- OPCODE_0x1A = 44,
- OPCODE_OTHER = 45,
- IN_FIFO_0_EMPTY = 56,
- IN_FIFO_0_LT_HALF_FULL = 57,
- IN_FIFO_0_HALF_FULL = 58,
- IN_FIFO_0_FULL = 59,
- IN_FIFO_TPC_EMPTY = 72,
- IN_FIFO_TPC_LT_HALF_FULL = 73,
- IN_FIFO_TPC_HALF_FULL = 74,
- IN_FIFO_TPC_FULL = 75,
- TPC_TC_XFC = 76,
- TPC_TC_STATE = 77,
- TC_STALL = 78,
- QUAD0_TAPS = 79,
- QUADS = 83,
- TCA_SYNC_STALL = 84,
- TAG_STALL = 85,
- TCB_SYNC_STALL = 88,
- TCA_VALID = 89,
- PROBES_VALID = 90,
- MISS_STALL = 91,
- FETCH_FIFO_STALL = 92,
- TCO_STALL = 93,
- ANY_STALL = 94,
- TAG_MISSES = 95,
- TAG_HITS = 96,
- SUB_TAG_MISSES = 97,
- SET0_INVALIDATES = 98,
- SET1_INVALIDATES = 99,
- SET2_INVALIDATES = 100,
- SET3_INVALIDATES = 101,
- SET0_TAG_MISSES = 102,
- SET1_TAG_MISSES = 103,
- SET2_TAG_MISSES = 104,
- SET3_TAG_MISSES = 105,
- SET0_TAG_HITS = 106,
- SET1_TAG_HITS = 107,
- SET2_TAG_HITS = 108,
- SET3_TAG_HITS = 109,
- SET0_SUB_TAG_MISSES = 110,
- SET1_SUB_TAG_MISSES = 111,
- SET2_SUB_TAG_MISSES = 112,
- SET3_SUB_TAG_MISSES = 113,
- SET0_EVICT1 = 114,
- SET0_EVICT2 = 115,
- SET0_EVICT3 = 116,
- SET0_EVICT4 = 117,
- SET0_EVICT5 = 118,
- SET0_EVICT6 = 119,
- SET0_EVICT7 = 120,
- SET0_EVICT8 = 121,
- SET1_EVICT1 = 130,
- SET1_EVICT2 = 131,
- SET1_EVICT3 = 132,
- SET1_EVICT4 = 133,
- SET1_EVICT5 = 134,
- SET1_EVICT6 = 135,
- SET1_EVICT7 = 136,
- SET1_EVICT8 = 137,
- SET2_EVICT1 = 146,
- SET2_EVICT2 = 147,
- SET2_EVICT3 = 148,
- SET2_EVICT4 = 149,
- SET2_EVICT5 = 150,
- SET2_EVICT6 = 151,
- SET2_EVICT7 = 152,
- SET2_EVICT8 = 153,
- SET3_EVICT1 = 162,
- SET3_EVICT2 = 163,
- SET3_EVICT3 = 164,
- SET3_EVICT4 = 165,
- SET3_EVICT5 = 166,
- SET3_EVICT6 = 167,
- SET3_EVICT7 = 168,
- SET3_EVICT8 = 169,
- FF_EMPTY = 178,
- FF_LT_HALF_FULL = 179,
- FF_HALF_FULL = 180,
- FF_FULL = 181,
- FF_XFC = 182,
- FF_STALLED = 183,
- FG_MASKS = 184,
- FG_LEFT_MASKS = 185,
- FG_LEFT_MASK_STALLED = 186,
- FG_LEFT_NOT_DONE_STALL = 187,
- FG_LEFT_FG_STALL = 188,
- FG_LEFT_SECTORS = 189,
- FG0_REQUESTS = 195,
- FG0_STALLED = 196,
- MEM_REQ512 = 199,
- MEM_REQ_SENT = 200,
- MEM_LOCAL_READ_REQ = 202,
- TC0_MH_STALLED = 203,
-};
-
-enum a2xx_sq_perfcnt_select {
- SQ_PIXEL_VECTORS_SUB = 0,
- SQ_VERTEX_VECTORS_SUB = 1,
- SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
- SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
- SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
- SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
- SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
- SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
- SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
- SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
- SQ_EXPORT_CYCLES = 10,
- SQ_ALU_CST_WRITTEN = 11,
- SQ_TEX_CST_WRITTEN = 12,
- SQ_ALU_CST_STALL = 13,
- SQ_ALU_TEX_STALL = 14,
- SQ_INST_WRITTEN = 15,
- SQ_BOOLEAN_WRITTEN = 16,
- SQ_LOOPS_WRITTEN = 17,
- SQ_PIXEL_SWAP_IN = 18,
- SQ_PIXEL_SWAP_OUT = 19,
- SQ_VERTEX_SWAP_IN = 20,
- SQ_VERTEX_SWAP_OUT = 21,
- SQ_ALU_VTX_INST_ISSUED = 22,
- SQ_TEX_VTX_INST_ISSUED = 23,
- SQ_VC_VTX_INST_ISSUED = 24,
- SQ_CF_VTX_INST_ISSUED = 25,
- SQ_ALU_PIX_INST_ISSUED = 26,
- SQ_TEX_PIX_INST_ISSUED = 27,
- SQ_VC_PIX_INST_ISSUED = 28,
- SQ_CF_PIX_INST_ISSUED = 29,
- SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
- SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
- SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
- SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
- SQ_ALU_NOPS = 34,
- SQ_PRED_SKIP = 35,
- SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
- SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
- SQ_SYNC_TEX_STALL_VTX = 38,
- SQ_SYNC_VC_STALL_VTX = 39,
- SQ_CONSTANTS_USED_SIMD0 = 40,
- SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
- SQ_GPR_STALL_VTX = 42,
- SQ_GPR_STALL_PIX = 43,
- SQ_VTX_RS_STALL = 44,
- SQ_PIX_RS_STALL = 45,
- SQ_SX_PC_FULL = 46,
- SQ_SX_EXP_BUFF_FULL = 47,
- SQ_SX_POS_BUFF_FULL = 48,
- SQ_INTERP_QUADS = 49,
- SQ_INTERP_ACTIVE = 50,
- SQ_IN_PIXEL_STALL = 51,
- SQ_IN_VTX_STALL = 52,
- SQ_VTX_CNT = 53,
- SQ_VTX_VECTOR2 = 54,
- SQ_VTX_VECTOR3 = 55,
- SQ_VTX_VECTOR4 = 56,
- SQ_PIXEL_VECTOR1 = 57,
- SQ_PIXEL_VECTOR23 = 58,
- SQ_PIXEL_VECTOR4 = 59,
- SQ_CONSTANTS_USED_SIMD1 = 60,
- SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
- SQ_SX_MEM_EXP_FULL = 62,
- SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
- SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
- SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
- SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
- SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
- SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68,
- SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
- SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70,
- SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
- SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
- SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
- SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
- SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
- SQ_PERFCOUNT_VTX_POP_THREAD = 76,
- SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
- SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
- SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
- SQ_PERFCOUNT_PIX_POP_THREAD = 80,
- SQ_SYNC_TEX_STALL_PIX = 81,
- SQ_SYNC_VC_STALL_PIX = 82,
- SQ_CONSTANTS_USED_SIMD2 = 83,
- SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
- SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85,
- SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86,
- SQ_ALU0_FIFO_FULL_SIMD0 = 87,
- SQ_ALU1_FIFO_FULL_SIMD0 = 88,
- SQ_ALU0_FIFO_FULL_SIMD1 = 89,
- SQ_ALU1_FIFO_FULL_SIMD1 = 90,
- SQ_ALU0_FIFO_FULL_SIMD2 = 91,
- SQ_ALU1_FIFO_FULL_SIMD2 = 92,
- SQ_ALU0_FIFO_FULL_SIMD3 = 93,
- SQ_ALU1_FIFO_FULL_SIMD3 = 94,
- VC_PERF_STATIC = 95,
- VC_PERF_STALLED = 96,
- VC_PERF_STARVED = 97,
- VC_PERF_SEND = 98,
- VC_PERF_ACTUAL_STARVED = 99,
- PIXEL_THREAD_0_ACTIVE = 100,
- VERTEX_THREAD_0_ACTIVE = 101,
- PIXEL_THREAD_0_NUMBER = 102,
- VERTEX_THREAD_0_NUMBER = 103,
- VERTEX_EVENT_NUMBER = 104,
- PIXEL_EVENT_NUMBER = 105,
- PTRBUFF_EF_PUSH = 106,
- PTRBUFF_EF_POP_EVENT = 107,
- PTRBUFF_EF_POP_NEW_VTX = 108,
- PTRBUFF_EF_POP_DEALLOC = 109,
- PTRBUFF_EF_POP_PVECTOR = 110,
- PTRBUFF_EF_POP_PVECTOR_X = 111,
- PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
- PTRBUFF_PB_DEALLOC = 113,
- PTRBUFF_PI_STATE_PPB_POP = 114,
- PTRBUFF_PI_RTR = 115,
- PTRBUFF_PI_READ_EN = 116,
- PTRBUFF_PI_BUFF_SWAP = 117,
- PTRBUFF_SQ_FREE_BUFF = 118,
- PTRBUFF_SQ_DEC = 119,
- PTRBUFF_SC_VALID_CNTL_EVENT = 120,
- PTRBUFF_SC_VALID_IJ_XFER = 121,
- PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
- PTRBUFF_QUAL_NEW_VECTOR = 123,
- PTRBUFF_QUAL_EVENT = 124,
- PTRBUFF_END_BUFFER = 125,
- PTRBUFF_FILL_QUAD = 126,
- VERTS_WRITTEN_SPI = 127,
- TP_FETCH_INSTR_EXEC = 128,
- TP_FETCH_INSTR_REQ = 129,
- TP_DATA_RETURN = 130,
- SPI_WRITE_CYCLES_SP = 131,
- SPI_WRITES_SP = 132,
- SP_ALU_INSTR_EXEC = 133,
- SP_CONST_ADDR_TO_SQ = 134,
- SP_PRED_KILLS_TO_SQ = 135,
- SP_EXPORT_CYCLES_TO_SX = 136,
- SP_EXPORTS_TO_SX = 137,
- SQ_CYCLES_ELAPSED = 138,
- SQ_TCFS_OPT_ALLOC_EXEC = 139,
- SQ_TCFS_NO_OPT_ALLOC = 140,
- SQ_ALU0_NO_OPT_ALLOC = 141,
- SQ_ALU1_NO_OPT_ALLOC = 142,
- SQ_TCFS_ARB_XFC_CNT = 143,
- SQ_ALU0_ARB_XFC_CNT = 144,
- SQ_ALU1_ARB_XFC_CNT = 145,
- SQ_TCFS_CFS_UPDATE_CNT = 146,
- SQ_ALU0_CFS_UPDATE_CNT = 147,
- SQ_ALU1_CFS_UPDATE_CNT = 148,
- SQ_VTX_PUSH_THREAD_CNT = 149,
- SQ_VTX_POP_THREAD_CNT = 150,
- SQ_PIX_PUSH_THREAD_CNT = 151,
- SQ_PIX_POP_THREAD_CNT = 152,
- SQ_PIX_TOTAL = 153,
- SQ_PIX_KILLED = 154,
-};
-
-enum a2xx_sx_perfcnt_select {
- SX_EXPORT_VECTORS = 0,
- SX_DUMMY_QUADS = 1,
- SX_ALPHA_FAIL = 2,
- SX_RB_QUAD_BUSY = 3,
- SX_RB_COLOR_BUSY = 4,
- SX_RB_QUAD_STALL = 5,
- SX_RB_COLOR_STALL = 6,
-};
-
-enum a2xx_rbbm_perfcount1_sel {
- RBBM1_COUNT = 0,
- RBBM1_NRT_BUSY = 1,
- RBBM1_RB_BUSY = 2,
- RBBM1_SQ_CNTX0_BUSY = 3,
- RBBM1_SQ_CNTX17_BUSY = 4,
- RBBM1_VGT_BUSY = 5,
- RBBM1_VGT_NODMA_BUSY = 6,
- RBBM1_PA_BUSY = 7,
- RBBM1_SC_CNTX_BUSY = 8,
- RBBM1_TPC_BUSY = 9,
- RBBM1_TC_BUSY = 10,
- RBBM1_SX_BUSY = 11,
- RBBM1_CP_COHER_BUSY = 12,
- RBBM1_CP_NRT_BUSY = 13,
- RBBM1_GFX_IDLE_STALL = 14,
- RBBM1_INTERRUPT = 15,
-};
-
-enum a2xx_cp_perfcount_sel {
- ALWAYS_COUNT = 0,
- TRANS_FIFO_FULL = 1,
- TRANS_FIFO_AF = 2,
- RCIU_PFPTRANS_WAIT = 3,
- RCIU_NRTTRANS_WAIT = 6,
- CSF_NRT_READ_WAIT = 8,
- CSF_I1_FIFO_FULL = 9,
- CSF_I2_FIFO_FULL = 10,
- CSF_ST_FIFO_FULL = 11,
- CSF_RING_ROQ_FULL = 13,
- CSF_I1_ROQ_FULL = 14,
- CSF_I2_ROQ_FULL = 15,
- CSF_ST_ROQ_FULL = 16,
- MIU_TAG_MEM_FULL = 18,
- MIU_WRITECLEAN = 19,
- MIU_NRT_WRITE_STALLED = 22,
- MIU_NRT_READ_STALLED = 23,
- ME_WRITE_CONFIRM_FIFO_FULL = 24,
- ME_VS_DEALLOC_FIFO_FULL = 25,
- ME_PS_DEALLOC_FIFO_FULL = 26,
- ME_REGS_VS_EVENT_FIFO_FULL = 27,
- ME_REGS_PS_EVENT_FIFO_FULL = 28,
- ME_REGS_CF_EVENT_FIFO_FULL = 29,
- ME_MICRO_RB_STARVED = 30,
- ME_MICRO_I1_STARVED = 31,
- ME_MICRO_I2_STARVED = 32,
- ME_MICRO_ST_STARVED = 33,
- RCIU_RBBM_DWORD_SENT = 40,
- ME_BUSY_CLOCKS = 41,
- ME_WAIT_CONTEXT_AVAIL = 42,
- PFP_TYPE0_PACKET = 43,
- PFP_TYPE3_PACKET = 44,
- CSF_RB_WPTR_NEQ_RPTR = 45,
- CSF_I1_SIZE_NEQ_ZERO = 46,
- CSF_I2_SIZE_NEQ_ZERO = 47,
- CSF_RBI1I2_FETCHING = 48,
-};
-
-enum a2xx_rb_perfcnt_select {
- RBPERF_CNTX_BUSY = 0,
- RBPERF_CNTX_BUSY_MAX = 1,
- RBPERF_SX_QUAD_STARVED = 2,
- RBPERF_SX_QUAD_STARVED_MAX = 3,
- RBPERF_GA_GC_CH0_SYS_REQ = 4,
- RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
- RBPERF_GA_GC_CH1_SYS_REQ = 6,
- RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
- RBPERF_MH_STARVED = 8,
- RBPERF_MH_STARVED_MAX = 9,
- RBPERF_AZ_BC_COLOR_BUSY = 10,
- RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
- RBPERF_AZ_BC_Z_BUSY = 12,
- RBPERF_AZ_BC_Z_BUSY_MAX = 13,
- RBPERF_RB_SC_TILE_RTR_N = 14,
- RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
- RBPERF_RB_SC_SAMP_RTR_N = 16,
- RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
- RBPERF_RB_SX_QUAD_RTR_N = 18,
- RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
- RBPERF_RB_SX_COLOR_RTR_N = 20,
- RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
- RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
- RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
- RBPERF_ZXP_STALL = 24,
- RBPERF_ZXP_STALL_MAX = 25,
- RBPERF_EVENT_PENDING = 26,
- RBPERF_EVENT_PENDING_MAX = 27,
- RBPERF_RB_MH_VALID = 28,
- RBPERF_RB_MH_VALID_MAX = 29,
- RBPERF_SX_RB_QUAD_SEND = 30,
- RBPERF_SX_RB_COLOR_SEND = 31,
- RBPERF_SC_RB_TILE_SEND = 32,
- RBPERF_SC_RB_SAMPLE_SEND = 33,
- RBPERF_SX_RB_MEM_EXPORT = 34,
- RBPERF_SX_RB_QUAD_EVENT = 35,
- RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
- RBPERF_SC_RB_TILE_EVENT_ALL = 37,
- RBPERF_RB_SC_EZ_SEND = 38,
- RBPERF_RB_SX_INDEX_SEND = 39,
- RBPERF_GMEM_INTFO_RD = 40,
- RBPERF_GMEM_INTF1_RD = 41,
- RBPERF_GMEM_INTFO_WR = 42,
- RBPERF_GMEM_INTF1_WR = 43,
- RBPERF_RB_CP_CONTEXT_DONE = 44,
- RBPERF_RB_CP_CACHE_FLUSH = 45,
- RBPERF_ZPASS_DONE = 46,
- RBPERF_ZCMD_VALID = 47,
- RBPERF_CCMD_VALID = 48,
- RBPERF_ACCUM_GRANT = 49,
- RBPERF_ACCUM_C0_GRANT = 50,
- RBPERF_ACCUM_C1_GRANT = 51,
- RBPERF_ACCUM_FULL_BE_WR = 52,
- RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
- RBPERF_ACCUM_TIMEOUT_PULSE = 54,
- RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
- RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
-};
-
-enum a2xx_mh_perfcnt_select {
- CP_R0_REQUESTS = 0,
- CP_R1_REQUESTS = 1,
- CP_R2_REQUESTS = 2,
- CP_R3_REQUESTS = 3,
- CP_R4_REQUESTS = 4,
- CP_TOTAL_READ_REQUESTS = 5,
- CP_TOTAL_WRITE_REQUESTS = 6,
- CP_TOTAL_REQUESTS = 7,
- CP_DATA_BYTES_WRITTEN = 8,
- CP_WRITE_CLEAN_RESPONSES = 9,
- CP_R0_READ_BURSTS_RECEIVED = 10,
- CP_R1_READ_BURSTS_RECEIVED = 11,
- CP_R2_READ_BURSTS_RECEIVED = 12,
- CP_R3_READ_BURSTS_RECEIVED = 13,
- CP_R4_READ_BURSTS_RECEIVED = 14,
- CP_TOTAL_READ_BURSTS_RECEIVED = 15,
- CP_R0_DATA_BEATS_READ = 16,
- CP_R1_DATA_BEATS_READ = 17,
- CP_R2_DATA_BEATS_READ = 18,
- CP_R3_DATA_BEATS_READ = 19,
- CP_R4_DATA_BEATS_READ = 20,
- CP_TOTAL_DATA_BEATS_READ = 21,
- VGT_R0_REQUESTS = 22,
- VGT_R1_REQUESTS = 23,
- VGT_TOTAL_REQUESTS = 24,
- VGT_R0_READ_BURSTS_RECEIVED = 25,
- VGT_R1_READ_BURSTS_RECEIVED = 26,
- VGT_TOTAL_READ_BURSTS_RECEIVED = 27,
- VGT_R0_DATA_BEATS_READ = 28,
- VGT_R1_DATA_BEATS_READ = 29,
- VGT_TOTAL_DATA_BEATS_READ = 30,
- TC_TOTAL_REQUESTS = 31,
- TC_ROQ_REQUESTS = 32,
- TC_INFO_SENT = 33,
- TC_READ_BURSTS_RECEIVED = 34,
- TC_DATA_BEATS_READ = 35,
- TCD_BURSTS_READ = 36,
- RB_REQUESTS = 37,
- RB_DATA_BYTES_WRITTEN = 38,
- RB_WRITE_CLEAN_RESPONSES = 39,
- AXI_READ_REQUESTS_ID_0 = 40,
- AXI_READ_REQUESTS_ID_1 = 41,
- AXI_READ_REQUESTS_ID_2 = 42,
- AXI_READ_REQUESTS_ID_3 = 43,
- AXI_READ_REQUESTS_ID_4 = 44,
- AXI_READ_REQUESTS_ID_5 = 45,
- AXI_READ_REQUESTS_ID_6 = 46,
- AXI_READ_REQUESTS_ID_7 = 47,
- AXI_TOTAL_READ_REQUESTS = 48,
- AXI_WRITE_REQUESTS_ID_0 = 49,
- AXI_WRITE_REQUESTS_ID_1 = 50,
- AXI_WRITE_REQUESTS_ID_2 = 51,
- AXI_WRITE_REQUESTS_ID_3 = 52,
- AXI_WRITE_REQUESTS_ID_4 = 53,
- AXI_WRITE_REQUESTS_ID_5 = 54,
- AXI_WRITE_REQUESTS_ID_6 = 55,
- AXI_WRITE_REQUESTS_ID_7 = 56,
- AXI_TOTAL_WRITE_REQUESTS = 57,
- AXI_TOTAL_REQUESTS_ID_0 = 58,
- AXI_TOTAL_REQUESTS_ID_1 = 59,
- AXI_TOTAL_REQUESTS_ID_2 = 60,
- AXI_TOTAL_REQUESTS_ID_3 = 61,
- AXI_TOTAL_REQUESTS_ID_4 = 62,
- AXI_TOTAL_REQUESTS_ID_5 = 63,
- AXI_TOTAL_REQUESTS_ID_6 = 64,
- AXI_TOTAL_REQUESTS_ID_7 = 65,
- AXI_TOTAL_REQUESTS = 66,
- AXI_READ_CHANNEL_BURSTS_ID_0 = 67,
- AXI_READ_CHANNEL_BURSTS_ID_1 = 68,
- AXI_READ_CHANNEL_BURSTS_ID_2 = 69,
- AXI_READ_CHANNEL_BURSTS_ID_3 = 70,
- AXI_READ_CHANNEL_BURSTS_ID_4 = 71,
- AXI_READ_CHANNEL_BURSTS_ID_5 = 72,
- AXI_READ_CHANNEL_BURSTS_ID_6 = 73,
- AXI_READ_CHANNEL_BURSTS_ID_7 = 74,
- AXI_READ_CHANNEL_TOTAL_BURSTS = 75,
- AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76,
- AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77,
- AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78,
- AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79,
- AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80,
- AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81,
- AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82,
- AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83,
- AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84,
- AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85,
- AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86,
- AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87,
- AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88,
- AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89,
- AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90,
- AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91,
- AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92,
- AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93,
- AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94,
- AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95,
- AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96,
- AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97,
- AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98,
- AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99,
- AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100,
- AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101,
- AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102,
- AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103,
- AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104,
- AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105,
- AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106,
- AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107,
- AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108,
- AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109,
- AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110,
- AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111,
- TOTAL_MMU_MISSES = 112,
- MMU_READ_MISSES = 113,
- MMU_WRITE_MISSES = 114,
- TOTAL_MMU_HITS = 115,
- MMU_READ_HITS = 116,
- MMU_WRITE_HITS = 117,
- SPLIT_MODE_TC_HITS = 118,
- SPLIT_MODE_TC_MISSES = 119,
- SPLIT_MODE_NON_TC_HITS = 120,
- SPLIT_MODE_NON_TC_MISSES = 121,
- STALL_AWAITING_TLB_MISS_FETCH = 122,
- MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123,
- MMU_TLB_MISS_DATA_BEATS_READ = 124,
- CP_CYCLES_HELD_OFF = 125,
- VGT_CYCLES_HELD_OFF = 126,
- TC_CYCLES_HELD_OFF = 127,
- TC_ROQ_CYCLES_HELD_OFF = 128,
- TC_CYCLES_HELD_OFF_TCD_FULL = 129,
- RB_CYCLES_HELD_OFF = 130,
- TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131,
- TLB_MISS_CYCLES_HELD_OFF = 132,
- AXI_READ_REQUEST_HELD_OFF = 133,
- AXI_WRITE_REQUEST_HELD_OFF = 134,
- AXI_REQUEST_HELD_OFF = 135,
- AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136,
- AXI_WRITE_DATA_HELD_OFF = 137,
- CP_SAME_PAGE_BANK_REQUESTS = 138,
- VGT_SAME_PAGE_BANK_REQUESTS = 139,
- TC_SAME_PAGE_BANK_REQUESTS = 140,
- TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141,
- RB_SAME_PAGE_BANK_REQUESTS = 142,
- TOTAL_SAME_PAGE_BANK_REQUESTS = 143,
- CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144,
- VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145,
- TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146,
- RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147,
- TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148,
- TOTAL_MH_READ_REQUESTS = 149,
- TOTAL_MH_WRITE_REQUESTS = 150,
- TOTAL_MH_REQUESTS = 151,
- MH_BUSY = 152,
- CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153,
- VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154,
- TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155,
- RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156,
- TC_ROQ_N_VALID_ENTRIES = 157,
- ARQ_N_ENTRIES = 158,
- WDB_N_ENTRIES = 159,
- MH_READ_LATENCY_OUTST_REQ_SUM = 160,
- MC_READ_LATENCY_OUTST_REQ_SUM = 161,
- MC_TOTAL_READ_REQUESTS = 162,
- ELAPSED_CYCLES_MH_GATED_CLK = 163,
- ELAPSED_CLK_CYCLES = 164,
- CP_W_16B_REQUESTS = 165,
- CP_W_32B_REQUESTS = 166,
- TC_16B_REQUESTS = 167,
- TC_32B_REQUESTS = 168,
- PA_REQUESTS = 169,
- PA_DATA_BYTES_WRITTEN = 170,
- PA_WRITE_CLEAN_RESPONSES = 171,
- PA_CYCLES_HELD_OFF = 172,
- AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173,
- AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174,
- AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175,
- AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176,
- AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177,
- AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178,
- AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179,
- AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180,
- AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181,
-};
-
-enum perf_mode_cnt {
- PERF_STATE_RESET = 0,
- PERF_STATE_ENABLE = 1,
- PERF_STATE_FREEZE = 2,
-};
-
-enum adreno_mmu_clnt_beh {
- BEH_NEVR = 0,
- BEH_TRAN_RNG = 1,
- BEH_TRAN_FLT = 2,
-};
-
-enum sq_tex_clamp {
- SQ_TEX_WRAP = 0,
- SQ_TEX_MIRROR = 1,
- SQ_TEX_CLAMP_LAST_TEXEL = 2,
- SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3,
- SQ_TEX_CLAMP_HALF_BORDER = 4,
- SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5,
- SQ_TEX_CLAMP_BORDER = 6,
- SQ_TEX_MIRROR_ONCE_BORDER = 7,
-};
-
-enum sq_tex_swiz {
- SQ_TEX_X = 0,
- SQ_TEX_Y = 1,
- SQ_TEX_Z = 2,
- SQ_TEX_W = 3,
- SQ_TEX_ZERO = 4,
- SQ_TEX_ONE = 5,
-};
-
-enum sq_tex_filter {
- SQ_TEX_FILTER_POINT = 0,
- SQ_TEX_FILTER_BILINEAR = 1,
- SQ_TEX_FILTER_BASEMAP = 2,
- SQ_TEX_FILTER_USE_FETCH_CONST = 3,
-};
-
-enum sq_tex_aniso_filter {
- SQ_TEX_ANISO_FILTER_DISABLED = 0,
- SQ_TEX_ANISO_FILTER_MAX_1_1 = 1,
- SQ_TEX_ANISO_FILTER_MAX_2_1 = 2,
- SQ_TEX_ANISO_FILTER_MAX_4_1 = 3,
- SQ_TEX_ANISO_FILTER_MAX_8_1 = 4,
- SQ_TEX_ANISO_FILTER_MAX_16_1 = 5,
- SQ_TEX_ANISO_FILTER_USE_FETCH_CONST = 7,
-};
-
-enum sq_tex_dimension {
- SQ_TEX_DIMENSION_1D = 0,
- SQ_TEX_DIMENSION_2D = 1,
- SQ_TEX_DIMENSION_3D = 2,
- SQ_TEX_DIMENSION_CUBE = 3,
-};
-
-enum sq_tex_border_color {
- SQ_TEX_BORDER_COLOR_BLACK = 0,
- SQ_TEX_BORDER_COLOR_WHITE = 1,
- SQ_TEX_BORDER_COLOR_ACBYCR_BLACK = 2,
- SQ_TEX_BORDER_COLOR_ACBCRY_BLACK = 3,
-};
-
-enum sq_tex_sign {
- SQ_TEX_SIGN_UNSIGNED = 0,
- SQ_TEX_SIGN_SIGNED = 1,
- SQ_TEX_SIGN_UNSIGNED_BIASED = 2,
- SQ_TEX_SIGN_GAMMA = 3,
-};
-
-enum sq_tex_endian {
- SQ_TEX_ENDIAN_NONE = 0,
- SQ_TEX_ENDIAN_8IN16 = 1,
- SQ_TEX_ENDIAN_8IN32 = 2,
- SQ_TEX_ENDIAN_16IN32 = 3,
-};
-
-enum sq_tex_clamp_policy {
- SQ_TEX_CLAMP_POLICY_D3D = 0,
- SQ_TEX_CLAMP_POLICY_OGL = 1,
-};
-
-enum sq_tex_num_format {
- SQ_TEX_NUM_FORMAT_FRAC = 0,
- SQ_TEX_NUM_FORMAT_INT = 1,
-};
-
-enum sq_tex_type {
- SQ_TEX_TYPE_0 = 0,
- SQ_TEX_TYPE_1 = 1,
- SQ_TEX_TYPE_2 = 2,
- SQ_TEX_TYPE_3 = 3,
-};
-
-#define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001
-
-#define REG_A2XX_RBBM_CNTL 0x0000003b
-
-#define REG_A2XX_RBBM_SOFT_RESET 0x0000003c
-
-#define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0
-
-#define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1
-
-#define REG_A2XX_MH_MMU_CONFIG 0x00000040
-#define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001
-#define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002
-#define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030
-#define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4
-static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
- return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0
-#define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6
-static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
- return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300
-#define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8
-static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
- return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00
-#define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10
-static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
- return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000
-#define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12
-static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
- return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000
-#define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14
-static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
- return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000
-#define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16
-static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
- return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000
-#define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18
-static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
- return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000
-#define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20
-static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
- return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000
-#define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22
-static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
- return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
-}
-#define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000
-#define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24
-static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
-{
- return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
-}
-
-#define REG_A2XX_MH_MMU_VA_RANGE 0x00000041
-#define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK 0x00000fff
-#define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT 0
-static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val)
-{
- return ((val) << A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT) & A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK;
-}
-#define A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK 0xfffff000
-#define A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT 12
-static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val)
-{
- return ((val) << A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT) & A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK;
-}
-
-#define REG_A2XX_MH_MMU_PT_BASE 0x00000042
-
-#define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043
-
-#define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044
-
-#define REG_A2XX_MH_MMU_INVALIDATE 0x00000045
-#define A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00000001
-#define A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC 0x00000002
-
-#define REG_A2XX_MH_MMU_MPU_BASE 0x00000046
-
-#define REG_A2XX_MH_MMU_MPU_END 0x00000047
-
-#define REG_A2XX_NQWAIT_UNTIL 0x00000394
-
-#define REG_A2XX_RBBM_PERFCOUNTER0_SELECT 0x00000395
-
-#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000396
-
-#define REG_A2XX_RBBM_PERFCOUNTER0_LO 0x00000397
-
-#define REG_A2XX_RBBM_PERFCOUNTER0_HI 0x00000398
-
-#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000399
-
-#define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x0000039a
-
-#define REG_A2XX_RBBM_DEBUG 0x0000039b
-
-#define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c
-#define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE 0x00000001
-#define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE 0x00000002
-#define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE 0x00000004
-#define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE 0x00000008
-#define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE 0x00000010
-#define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE 0x00000020
-#define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040
-#define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080
-#define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE 0x00000100
-#define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE 0x00000200
-#define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE 0x00000400
-#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE 0x00000800
-#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE 0x00001000
-#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE 0x00002000
-#define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE 0x00004000
-#define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE 0x00008000
-#define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE 0x00010000
-#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE 0x00020000
-#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE 0x00040000
-#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000
-#define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE 0x00100000
-#define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE 0x00200000
-#define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE 0x00400000
-#define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE 0x00800000
-#define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE 0x01000000
-#define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE 0x02000000
-#define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE 0x04000000
-#define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE 0x08000000
-#define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE 0x10000000
-#define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE 0x20000000
-#define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE 0x40000000
-#define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000
-
-#define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d
-#define A2XX_RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE 0x00000001
-#define A2XX_RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE 0x00000002
-#define A2XX_RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE 0x00000004
-#define A2XX_RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE 0x00000008
-#define A2XX_RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE 0x00000010
-#define A2XX_RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE 0x00000020
-#define A2XX_RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE 0x00000040
-#define A2XX_RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE 0x00000080
-#define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE 0x00000100
-#define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE 0x00000200
-#define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE 0x00000400
-#define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE 0x00000800
-
-#define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0
-
-#define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1
-
-#define REG_A2XX_RBBM_READ_ERROR 0x000003b3
-
-#define REG_A2XX_RBBM_INT_CNTL 0x000003b4
-#define A2XX_RBBM_INT_CNTL_RDERR_INT_MASK 0x00000001
-#define A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK 0x00000002
-#define A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK 0x00080000
-
-#define REG_A2XX_RBBM_INT_STATUS 0x000003b5
-
-#define REG_A2XX_RBBM_INT_ACK 0x000003b6
-
-#define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7
-#define A2XX_MASTER_INT_SIGNAL_MH_INT_STAT 0x00000020
-#define A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT 0x04000000
-#define A2XX_MASTER_INT_SIGNAL_CP_INT_STAT 0x40000000
-#define A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT 0x80000000
-
-#define REG_A2XX_RBBM_PERIPHID1 0x000003f9
-
-#define REG_A2XX_RBBM_PERIPHID2 0x000003fa
-
-#define REG_A2XX_CP_PERFMON_CNTL 0x00000444
-#define A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT__MASK 0x00000007
-#define A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT__SHIFT 0
-static inline uint32_t A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT(enum perf_mode_cnt val)
-{
- return ((val) << A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT__SHIFT) & A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT__MASK;
-}
-
-#define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445
-
-#define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446
-
-#define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447
-
-#define REG_A2XX_RBBM_STATUS 0x000005d0
-#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f
-#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0
-static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val)
-{
- return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK;
-}
-#define A2XX_RBBM_STATUS_TC_BUSY 0x00000020
-#define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100
-#define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200
-#define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400
-#define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800
-#define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000
-#define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000
-#define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000
-#define A2XX_RBBM_STATUS_MH_BUSY 0x00040000
-#define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000
-#define A2XX_RBBM_STATUS_SX_BUSY 0x00200000
-#define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000
-#define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000
-#define A2XX_RBBM_STATUS_PA_BUSY 0x02000000
-#define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000
-#define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000
-#define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000
-#define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000
-#define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000
-
-#define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40
-#define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f
-#define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0
-static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val)
-{
- return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK;
-}
-#define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040
-#define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080
-#define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100
-#define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200
-#define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00
-#define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10
-static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val)
-{
- return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK;
-}
-#define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000
-#define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000
-#define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000
-#define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000
-#define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16
-static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val)
-{
- return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK;
-}
-#define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000
-#define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000
-#define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000
-#define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000
-#define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000
-
-#define REG_A2XX_MH_INTERRUPT_MASK 0x00000a42
-#define A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR 0x00000001
-#define A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR 0x00000002
-#define A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT 0x00000004
-
-#define REG_A2XX_MH_INTERRUPT_STATUS 0x00000a43
-
-#define REG_A2XX_MH_INTERRUPT_CLEAR 0x00000a44
-
-#define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1 0x00000a54
-
-#define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2 0x00000a55
-
-#define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01
-#define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
-#define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0
-static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK;
-}
-#define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
-#define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5
-static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK;
-}
-
-#define REG_A2XX_VSC_PIPE(i0) (0x00000c06 + 0x3*(i0))
-
-static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
-
-static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
-
-static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
-
-#define REG_A2XX_PC_DEBUG_CNTL 0x00000c38
-
-#define REG_A2XX_PC_DEBUG_DATA 0x00000c39
-
-#define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44
-
-#define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80
-
-#define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80
-
-#define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81
-
-#define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81
-
-#define REG_A2XX_PA_SU_FACE_DATA 0x00000c86
-#define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK 0xffffffe0
-#define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT 5
-static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val)
-{
- return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK;
-}
-
-#define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00
-#define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC 0x00000001
-#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK 0x00000ff0
-#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT 4
-static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val)
-{
- return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK;
-}
-#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK 0x000ff000
-#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT 12
-static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val)
-{
- return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK;
-}
-
-#define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01
-
-#define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02
-#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK 0x00000fff
-#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT 0
-static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val)
-{
- return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK;
-}
-#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK 0x0fff0000
-#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT 16
-static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val)
-{
- return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK;
-}
-
-#define REG_A2XX_SQ_DEBUG_MISC 0x00000d05
-
-#define REG_A2XX_SQ_INT_CNTL 0x00000d34
-
-#define REG_A2XX_SQ_INT_STATUS 0x00000d35
-
-#define REG_A2XX_SQ_INT_ACK 0x00000d36
-
-#define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae
-
-#define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf
-
-#define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0
-
-#define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1
-
-#define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2
-
-#define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3
-
-#define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4
-
-#define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5
-
-#define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6
-
-#define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7
-
-#define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8
-
-#define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9
-
-#define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba
-
-#define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb
-
-#define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc
-
-#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd
-
-#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe
-
-#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf
-
-#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0
-
-#define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1
-
-#define REG_A2XX_TC_CNTL_STATUS 0x00000e00
-#define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001
-
-#define REG_A2XX_TP0_CHICKEN 0x00000e1e
-
-#define REG_A2XX_RB_BC_CONTROL 0x00000f01
-#define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001
-#define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006
-#define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1
-static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val)
-{
- return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK;
-}
-#define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008
-#define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010
-#define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020
-#define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040
-#define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080
-#define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00
-#define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8
-static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val)
-{
- return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK;
-}
-#define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000
-#define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000
-#define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000
-#define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000
-#define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000
-#define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18
-static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val)
-{
- return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK;
-}
-#define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000
-#define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000
-#define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23
-static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val)
-{
- return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK;
-}
-#define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000
-#define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27
-static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val)
-{
- return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK;
-}
-#define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000
-#define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000
-#define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000
-
-#define REG_A2XX_RB_EDRAM_INFO 0x00000f02
-
-#define REG_A2XX_RB_DEBUG_CNTL 0x00000f26
-
-#define REG_A2XX_RB_DEBUG_DATA 0x00000f27
-
-#define REG_A2XX_RB_SURFACE_INFO 0x00002000
-#define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK 0x00003fff
-#define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT 0
-static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val)
-{
- return ((val) << A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT) & A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK;
-}
-#define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK 0x0000c000
-#define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT 14
-static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val)
-{
- return ((val) << A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT) & A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK;
-}
-
-#define REG_A2XX_RB_COLOR_INFO 0x00002001
-#define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f
-#define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0
-static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val)
-{
- return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK;
-}
-#define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030
-#define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4
-static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val)
-{
- return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK;
-}
-#define A2XX_RB_COLOR_INFO_LINEAR 0x00000040
-#define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180
-#define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7
-static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val)
-{
- return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK;
-}
-#define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600
-#define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9
-static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val)
-{
- return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK;
-}
-#define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000
-#define A2XX_RB_COLOR_INFO_BASE__SHIFT 12
-static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK;
-}
-
-#define REG_A2XX_RB_DEPTH_INFO 0x00002002
-#define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001
-#define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
-static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
-{
- return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
-}
-#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000
-#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
-static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
-}
-
-#define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005
-
-#define REG_A2XX_COHER_DEST_BASE_0 0x00002006
-
-#define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e
-#define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
-#define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
-#define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
-static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
-{
- return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK;
-}
-#define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
-#define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
-static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
-{
- return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK;
-}
-
-#define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f
-#define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
-#define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
-#define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
-static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
-{
- return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK;
-}
-#define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
-#define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
-static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
-{
- return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK;
-}
-
-#define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080
-#define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff
-#define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0
-static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val)
-{
- return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK;
-}
-#define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000
-#define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16
-static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val)
-{
- return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK;
-}
-#define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000
-
-#define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081
-#define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
-#define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
-#define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
-static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
-{
- return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK;
-}
-#define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
-#define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
-static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
-{
- return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK;
-}
-
-#define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082
-#define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
-#define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
-#define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
-static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
-{
- return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK;
-}
-#define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
-#define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
-static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
-{
- return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK;
-}
-
-#define REG_A2XX_UNKNOWN_2010 0x00002010
-
-#define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100
-
-#define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101
-
-#define REG_A2XX_VGT_INDX_OFFSET 0x00002102
-
-#define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103
-
-#define REG_A2XX_RB_COLOR_MASK 0x00002104
-#define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001
-#define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002
-#define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004
-#define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008
-
-#define REG_A2XX_RB_BLEND_RED 0x00002105
-
-#define REG_A2XX_RB_BLEND_GREEN 0x00002106
-
-#define REG_A2XX_RB_BLEND_BLUE 0x00002107
-
-#define REG_A2XX_RB_BLEND_ALPHA 0x00002108
-
-#define REG_A2XX_RB_FOG_COLOR 0x00002109
-#define A2XX_RB_FOG_COLOR_FOG_RED__MASK 0x000000ff
-#define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT 0
-static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val)
-{
- return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK;
-}
-#define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK 0x0000ff00
-#define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT 8
-static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val)
-{
- return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK;
-}
-#define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK 0x00ff0000
-#define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT 16
-static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val)
-{
- return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK;
-}
-
-#define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c
-#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
-#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
-static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
-{
- return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
-}
-#define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
-#define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
-static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
-{
- return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
-}
-#define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
-#define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
-static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
-{
- return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
-}
-
-#define REG_A2XX_RB_STENCILREFMASK 0x0000210d
-#define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
-#define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
-static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
-{
- return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK;
-}
-#define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
-#define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
-static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
-{
- return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK;
-}
-#define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
-#define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
-static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
-{
- return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
-}
-
-#define REG_A2XX_RB_ALPHA_REF 0x0000210e
-
-#define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f
-#define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff
-#define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0
-static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val)
-{
- return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK;
-}
-
-#define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110
-#define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff
-#define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0
-static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val)
-{
- return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK;
-}
-
-#define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111
-#define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff
-#define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0
-static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val)
-{
- return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK;
-}
-
-#define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112
-#define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff
-#define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0
-static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val)
-{
- return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK;
-}
-
-#define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113
-#define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff
-#define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0
-static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val)
-{
- return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK;
-}
-
-#define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114
-#define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff
-#define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0
-static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val)
-{
- return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK;
-}
-
-#define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180
-#define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff
-#define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0
-static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val)
-{
- return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK;
-}
-#define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00
-#define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8
-static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val)
-{
- return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK;
-}
-#define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000
-#define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000
-#define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000
-#define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000
-#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000
-#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20
-static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val)
-{
- return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK;
-}
-#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000
-#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24
-static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val)
-{
- return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK;
-}
-#define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000
-#define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27
-static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val)
-{
- return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK;
-}
-#define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000
-
-#define REG_A2XX_SQ_CONTEXT_MISC 0x00002181
-#define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001
-#define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002
-#define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c
-#define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2
-static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val)
-{
- return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK;
-}
-#define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00
-#define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8
-static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
-{
- return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK;
-}
-#define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000
-#define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000
-#define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000
-
-#define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182
-#define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK 0x0000ffff
-#define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT 0
-static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val)
-{
- return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK;
-}
-#define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK 0xffff0000
-#define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT 16
-static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val)
-{
- return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK;
-}
-
-#define REG_A2XX_SQ_WRAPPING_0 0x00002183
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK 0x0000000f
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT 0
-static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val)
-{
- return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK;
-}
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK 0x000000f0
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT 4
-static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val)
-{
- return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK;
-}
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK 0x00000f00
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT 8
-static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val)
-{
- return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK;
-}
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK 0x0000f000
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT 12
-static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val)
-{
- return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK;
-}
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK 0x000f0000
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT 16
-static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val)
-{
- return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK;
-}
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK 0x00f00000
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT 20
-static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val)
-{
- return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK;
-}
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK 0x0f000000
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT 24
-static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val)
-{
- return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK;
-}
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK 0xf0000000
-#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT 28
-static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val)
-{
- return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK;
-}
-
-#define REG_A2XX_SQ_WRAPPING_1 0x00002184
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK 0x0000000f
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT 0
-static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val)
-{
- return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK;
-}
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK 0x000000f0
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT 4
-static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val)
-{
- return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK;
-}
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK 0x00000f00
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT 8
-static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val)
-{
- return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK;
-}
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK 0x0000f000
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT 12
-static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val)
-{
- return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK;
-}
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK 0x000f0000
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT 16
-static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val)
-{
- return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK;
-}
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK 0x00f00000
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT 20
-static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val)
-{
- return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK;
-}
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK 0x0f000000
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT 24
-static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val)
-{
- return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK;
-}
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK 0xf0000000
-#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT 28
-static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val)
-{
- return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK;
-}
-
-#define REG_A2XX_SQ_PS_PROGRAM 0x000021f6
-#define A2XX_SQ_PS_PROGRAM_BASE__MASK 0x00000fff
-#define A2XX_SQ_PS_PROGRAM_BASE__SHIFT 0
-static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val)
-{
- return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK;
-}
-#define A2XX_SQ_PS_PROGRAM_SIZE__MASK 0x00fff000
-#define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT 12
-static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val)
-{
- return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK;
-}
-
-#define REG_A2XX_SQ_VS_PROGRAM 0x000021f7
-#define A2XX_SQ_VS_PROGRAM_BASE__MASK 0x00000fff
-#define A2XX_SQ_VS_PROGRAM_BASE__SHIFT 0
-static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val)
-{
- return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK;
-}
-#define A2XX_SQ_VS_PROGRAM_SIZE__MASK 0x00fff000
-#define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT 12
-static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val)
-{
- return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK;
-}
-
-#define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9
-
-#define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc
-#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
-#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
-static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
-{
- return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
-}
-#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
-#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
-static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
-{
- return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
-}
-#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600
-#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9
-static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
-{
- return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
-}
-#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800
-#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11
-static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
-{
- return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
-}
-#define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000
-#define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000
-#define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000
-#define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000
-#define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24
-static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
-{
- return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK;
-}
-
-#define REG_A2XX_VGT_IMMED_DATA 0x000021fd
-
-#define REG_A2XX_RB_DEPTHCONTROL 0x00002200
-#define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001
-#define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002
-#define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004
-#define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008
-#define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070
-#define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4
-static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val)
-{
- return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK;
-}
-#define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080
-#define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700
-#define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8
-static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val)
-{
- return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK;
-}
-#define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800
-#define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11
-static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val)
-{
- return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK;
-}
-#define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000
-#define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14
-static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val)
-{
- return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK;
-}
-#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000
-#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17
-static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val)
-{
- return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK;
-}
-#define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000
-#define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20
-static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val)
-{
- return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK;
-}
-#define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000
-#define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23
-static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val)
-{
- return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK;
-}
-#define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000
-#define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26
-static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val)
-{
- return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK;
-}
-#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000
-#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29
-static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val)
-{
- return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK;
-}
-
-#define REG_A2XX_RB_BLEND_CONTROL 0x00002201
-#define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f
-#define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0
-static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val)
-{
- return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK;
-}
-#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0
-#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5
-static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val)
-{
- return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK;
-}
-#define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00
-#define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8
-static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val)
-{
- return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK;
-}
-#define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000
-#define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16
-static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val)
-{
- return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK;
-}
-#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000
-#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21
-static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val)
-{
- return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK;
-}
-#define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000
-#define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24
-static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val)
-{
- return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK;
-}
-#define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000
-#define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000
-
-#define REG_A2XX_RB_COLORCONTROL 0x00002202
-#define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007
-#define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0
-static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val)
-{
- return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK;
-}
-#define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010
-#define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020
-#define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040
-#define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080
-#define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00
-#define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8
-static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val)
-{
- return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK;
-}
-#define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000
-#define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12
-static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
-{
- return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK;
-}
-#define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000
-#define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14
-static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val)
-{
- return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK;
-}
-#define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24
-static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val)
-{
- return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK;
-}
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26
-static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val)
-{
- return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK;
-}
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28
-static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val)
-{
- return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK;
-}
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000
-#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30
-static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val)
-{
- return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK;
-}
-
-#define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203
-#define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007
-#define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0
-static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val)
-{
- return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK;
-}
-#define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038
-#define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3
-static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val)
-{
- return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK;
-}
-#define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0
-#define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6
-static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val)
-{
- return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK;
-}
-
-#define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204
-#define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000
-#define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000
-#define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000
-#define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19
-static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val)
-{
- return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK;
-}
-#define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000
-#define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000
-#define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000
-#define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000
-#define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000
-
-#define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205
-#define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001
-#define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002
-#define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004
-#define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018
-#define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3
-static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val)
-{
- return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK;
-}
-#define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0
-#define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5
-static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
-{
- return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK;
-}
-#define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700
-#define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8
-static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
-{
- return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK;
-}
-#define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800
-#define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000
-#define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000
-#define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000
-#define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000
-#define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000
-#define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000
-#define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000
-#define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000
-#define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000
-#define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000
-#define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000
-#define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000
-#define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000
-#define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000
-#define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000
-
-#define REG_A2XX_PA_CL_VTE_CNTL 0x00002206
-#define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001
-#define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002
-#define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004
-#define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008
-#define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010
-#define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020
-#define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100
-#define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200
-#define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400
-#define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800
-
-#define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207
-#define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007
-#define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0
-static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val)
-{
- return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK;
-}
-#define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038
-#define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3
-static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val)
-{
- return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK;
-}
-#define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0
-#define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6
-static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val)
-{
- return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK;
-}
-
-#define REG_A2XX_RB_MODECONTROL 0x00002208
-#define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007
-#define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0
-static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val)
-{
- return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK;
-}
-
-#define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209
-
-#define REG_A2XX_RB_SAMPLE_POS 0x0000220a
-
-#define REG_A2XX_CLEAR_COLOR 0x0000220b
-#define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff
-#define A2XX_CLEAR_COLOR_RED__SHIFT 0
-static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val)
-{
- return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK;
-}
-#define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00
-#define A2XX_CLEAR_COLOR_GREEN__SHIFT 8
-static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val)
-{
- return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK;
-}
-#define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000
-#define A2XX_CLEAR_COLOR_BLUE__SHIFT 16
-static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val)
-{
- return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK;
-}
-#define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000
-#define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24
-static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val)
-{
- return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK;
-}
-
-#define REG_A2XX_A220_GRAS_CONTROL 0x00002210
-
-#define REG_A2XX_PA_SU_POINT_SIZE 0x00002280
-#define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff
-#define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0
-static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val)
-{
- return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK;
-}
-#define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000
-#define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16
-static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val)
-{
- return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK;
-}
-
-#define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281
-#define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
-#define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0
-static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val)
-{
- return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK;
-}
-#define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000
-#define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16
-static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val)
-{
- return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK;
-}
-
-#define REG_A2XX_PA_SU_LINE_CNTL 0x00002282
-#define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff
-#define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0
-static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val)
-{
- return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK;
-}
-
-#define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283
-#define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff
-#define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0
-static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val)
-{
- return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK;
-}
-#define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000
-#define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16
-static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val)
-{
- return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK;
-}
-#define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000
-#define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28
-static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val)
-{
- return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK;
-}
-#define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000
-#define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29
-static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val)
-{
- return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK;
-}
-
-#define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293
-#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA 0x00000001
-#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK 0x0000007e
-#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT 1
-static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val)
-{
- return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK;
-}
-#define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z 0x00000100
-
-#define REG_A2XX_VGT_ENHANCE 0x00002294
-
-#define REG_A2XX_PA_SC_LINE_CNTL 0x00002300
-#define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff
-#define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0
-static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val)
-{
- return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK;
-}
-#define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100
-#define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200
-#define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400
-
-#define REG_A2XX_PA_SC_AA_CONFIG 0x00002301
-#define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK 0x00000007
-#define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT 0
-static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val)
-{
- return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK;
-}
-#define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK 0x0001e000
-#define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT 13
-static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val)
-{
- return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK;
-}
-
-#define REG_A2XX_PA_SU_VTX_CNTL 0x00002302
-#define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001
-#define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0
-static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val)
-{
- return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK;
-}
-#define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006
-#define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1
-static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val)
-{
- return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK;
-}
-#define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380
-#define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7
-static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val)
-{
- return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK;
-}
-
-#define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303
-#define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff
-#define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0
-static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val)
-{
- return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK;
-}
-
-#define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304
-#define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff
-#define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0
-static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val)
-{
- return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK;
-}
-
-#define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305
-#define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff
-#define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0
-static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val)
-{
- return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK;
-}
-
-#define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306
-#define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff
-#define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0
-static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val)
-{
- return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK;
-}
-
-#define REG_A2XX_SQ_VS_CONST 0x00002307
-#define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff
-#define A2XX_SQ_VS_CONST_BASE__SHIFT 0
-static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val)
-{
- return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK;
-}
-#define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000
-#define A2XX_SQ_VS_CONST_SIZE__SHIFT 12
-static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val)
-{
- return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK;
-}
-
-#define REG_A2XX_SQ_PS_CONST 0x00002308
-#define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff
-#define A2XX_SQ_PS_CONST_BASE__SHIFT 0
-static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val)
-{
- return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK;
-}
-#define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000
-#define A2XX_SQ_PS_CONST_SIZE__SHIFT 12
-static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val)
-{
- return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK;
-}
-
-#define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309
-
-#define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a
-
-#define REG_A2XX_PA_SC_AA_MASK 0x00002312
-
-#define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316
-#define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK 0x00000007
-#define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT 0
-static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val)
-{
- return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK;
-}
-
-#define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317
-#define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK 0x00000003
-#define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT 0
-static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val)
-{
- return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK;
-}
-
-#define REG_A2XX_RB_COPY_CONTROL 0x00002318
-#define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007
-#define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0
-static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val)
-{
- return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK;
-}
-#define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008
-#define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0
-#define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4
-static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val)
-{
- return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK;
-}
-
-#define REG_A2XX_RB_COPY_DEST_BASE 0x00002319
-
-#define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a
-#define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff
-#define A2XX_RB_COPY_DEST_PITCH__SHIFT 0
-static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK;
-}
-
-#define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b
-#define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007
-#define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0
-static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val)
-{
- return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK;
-}
-#define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008
-#define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0
-#define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4
-static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val)
-{
- return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK;
-}
-#define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
-#define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
-static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val)
-{
- return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK;
-}
-#define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
-#define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
-static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
-{
- return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
-}
-#define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000
-#define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12
-static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val)
-{
- return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK;
-}
-#define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000
-#define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000
-#define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000
-#define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000
-
-#define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c
-#define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff
-#define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0
-static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val)
-{
- return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK;
-}
-#define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000
-#define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13
-static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
-{
- return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK;
-}
-
-#define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d
-
-#define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324
-
-#define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326
-
-#define REG_A2XX_A225_GRAS_UCP0X 0x00002340
-
-#define REG_A2XX_A225_GRAS_UCP5W 0x00002357
-
-#define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360
-
-#define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380
-
-#define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x00002381
-
-#define REG_A2XX_PA_SU_POLY_OFFSET_BACK_SCALE 0x00002382
-
-#define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383
-
-#define REG_A2XX_SQ_CONSTANT_0 0x00004000
-
-#define REG_A2XX_SQ_FETCH_0 0x00004800
-
-#define REG_A2XX_SQ_CF_BOOLEANS 0x00004900
-
-#define REG_A2XX_SQ_CF_LOOP 0x00004908
-
-#define REG_A2XX_COHER_SIZE_PM4 0x00000a29
-
-#define REG_A2XX_COHER_BASE_PM4 0x00000a2a
-
-#define REG_A2XX_COHER_STATUS_PM4 0x00000a2b
-
-#define REG_A2XX_PA_SU_PERFCOUNTER0_SELECT 0x00000c88
-
-#define REG_A2XX_PA_SU_PERFCOUNTER1_SELECT 0x00000c89
-
-#define REG_A2XX_PA_SU_PERFCOUNTER2_SELECT 0x00000c8a
-
-#define REG_A2XX_PA_SU_PERFCOUNTER3_SELECT 0x00000c8b
-
-#define REG_A2XX_PA_SU_PERFCOUNTER0_LOW 0x00000c8c
-
-#define REG_A2XX_PA_SU_PERFCOUNTER0_HI 0x00000c8d
-
-#define REG_A2XX_PA_SU_PERFCOUNTER1_LOW 0x00000c8e
-
-#define REG_A2XX_PA_SU_PERFCOUNTER1_HI 0x00000c8f
-
-#define REG_A2XX_PA_SU_PERFCOUNTER2_LOW 0x00000c90
-
-#define REG_A2XX_PA_SU_PERFCOUNTER2_HI 0x00000c91
-
-#define REG_A2XX_PA_SU_PERFCOUNTER3_LOW 0x00000c92
-
-#define REG_A2XX_PA_SU_PERFCOUNTER3_HI 0x00000c93
-
-#define REG_A2XX_PA_SC_PERFCOUNTER0_SELECT 0x00000c98
-
-#define REG_A2XX_PA_SC_PERFCOUNTER0_LOW 0x00000c99
-
-#define REG_A2XX_PA_SC_PERFCOUNTER0_HI 0x00000c9a
-
-#define REG_A2XX_VGT_PERFCOUNTER0_SELECT 0x00000c48
-
-#define REG_A2XX_VGT_PERFCOUNTER1_SELECT 0x00000c49
-
-#define REG_A2XX_VGT_PERFCOUNTER2_SELECT 0x00000c4a
-
-#define REG_A2XX_VGT_PERFCOUNTER3_SELECT 0x00000c4b
-
-#define REG_A2XX_VGT_PERFCOUNTER0_LOW 0x00000c4c
-
-#define REG_A2XX_VGT_PERFCOUNTER1_LOW 0x00000c4e
-
-#define REG_A2XX_VGT_PERFCOUNTER2_LOW 0x00000c50
-
-#define REG_A2XX_VGT_PERFCOUNTER3_LOW 0x00000c52
-
-#define REG_A2XX_VGT_PERFCOUNTER0_HI 0x00000c4d
-
-#define REG_A2XX_VGT_PERFCOUNTER1_HI 0x00000c4f
-
-#define REG_A2XX_VGT_PERFCOUNTER2_HI 0x00000c51
-
-#define REG_A2XX_VGT_PERFCOUNTER3_HI 0x00000c53
-
-#define REG_A2XX_TCR_PERFCOUNTER0_SELECT 0x00000e05
-
-#define REG_A2XX_TCR_PERFCOUNTER1_SELECT 0x00000e08
-
-#define REG_A2XX_TCR_PERFCOUNTER0_HI 0x00000e06
-
-#define REG_A2XX_TCR_PERFCOUNTER1_HI 0x00000e09
-
-#define REG_A2XX_TCR_PERFCOUNTER0_LOW 0x00000e07
-
-#define REG_A2XX_TCR_PERFCOUNTER1_LOW 0x00000e0a
-
-#define REG_A2XX_TP0_PERFCOUNTER0_SELECT 0x00000e1f
-
-#define REG_A2XX_TP0_PERFCOUNTER0_HI 0x00000e20
-
-#define REG_A2XX_TP0_PERFCOUNTER0_LOW 0x00000e21
-
-#define REG_A2XX_TP0_PERFCOUNTER1_SELECT 0x00000e22
-
-#define REG_A2XX_TP0_PERFCOUNTER1_HI 0x00000e23
-
-#define REG_A2XX_TP0_PERFCOUNTER1_LOW 0x00000e24
-
-#define REG_A2XX_TCM_PERFCOUNTER0_SELECT 0x00000e54
-
-#define REG_A2XX_TCM_PERFCOUNTER1_SELECT 0x00000e57
-
-#define REG_A2XX_TCM_PERFCOUNTER0_HI 0x00000e55
-
-#define REG_A2XX_TCM_PERFCOUNTER1_HI 0x00000e58
-
-#define REG_A2XX_TCM_PERFCOUNTER0_LOW 0x00000e56
-
-#define REG_A2XX_TCM_PERFCOUNTER1_LOW 0x00000e59
-
-#define REG_A2XX_TCF_PERFCOUNTER0_SELECT 0x00000e5a
-
-#define REG_A2XX_TCF_PERFCOUNTER1_SELECT 0x00000e5d
-
-#define REG_A2XX_TCF_PERFCOUNTER2_SELECT 0x00000e60
-
-#define REG_A2XX_TCF_PERFCOUNTER3_SELECT 0x00000e63
-
-#define REG_A2XX_TCF_PERFCOUNTER4_SELECT 0x00000e66
-
-#define REG_A2XX_TCF_PERFCOUNTER5_SELECT 0x00000e69
-
-#define REG_A2XX_TCF_PERFCOUNTER6_SELECT 0x00000e6c
-
-#define REG_A2XX_TCF_PERFCOUNTER7_SELECT 0x00000e6f
-
-#define REG_A2XX_TCF_PERFCOUNTER8_SELECT 0x00000e72
-
-#define REG_A2XX_TCF_PERFCOUNTER9_SELECT 0x00000e75
-
-#define REG_A2XX_TCF_PERFCOUNTER10_SELECT 0x00000e78
-
-#define REG_A2XX_TCF_PERFCOUNTER11_SELECT 0x00000e7b
-
-#define REG_A2XX_TCF_PERFCOUNTER0_HI 0x00000e5b
-
-#define REG_A2XX_TCF_PERFCOUNTER1_HI 0x00000e5e
-
-#define REG_A2XX_TCF_PERFCOUNTER2_HI 0x00000e61
-
-#define REG_A2XX_TCF_PERFCOUNTER3_HI 0x00000e64
-
-#define REG_A2XX_TCF_PERFCOUNTER4_HI 0x00000e67
-
-#define REG_A2XX_TCF_PERFCOUNTER5_HI 0x00000e6a
-
-#define REG_A2XX_TCF_PERFCOUNTER6_HI 0x00000e6d
-
-#define REG_A2XX_TCF_PERFCOUNTER7_HI 0x00000e70
-
-#define REG_A2XX_TCF_PERFCOUNTER8_HI 0x00000e73
-
-#define REG_A2XX_TCF_PERFCOUNTER9_HI 0x00000e76
-
-#define REG_A2XX_TCF_PERFCOUNTER10_HI 0x00000e79
-
-#define REG_A2XX_TCF_PERFCOUNTER11_HI 0x00000e7c
-
-#define REG_A2XX_TCF_PERFCOUNTER0_LOW 0x00000e5c
-
-#define REG_A2XX_TCF_PERFCOUNTER1_LOW 0x00000e5f
-
-#define REG_A2XX_TCF_PERFCOUNTER2_LOW 0x00000e62
-
-#define REG_A2XX_TCF_PERFCOUNTER3_LOW 0x00000e65
-
-#define REG_A2XX_TCF_PERFCOUNTER4_LOW 0x00000e68
-
-#define REG_A2XX_TCF_PERFCOUNTER5_LOW 0x00000e6b
-
-#define REG_A2XX_TCF_PERFCOUNTER6_LOW 0x00000e6e
-
-#define REG_A2XX_TCF_PERFCOUNTER7_LOW 0x00000e71
-
-#define REG_A2XX_TCF_PERFCOUNTER8_LOW 0x00000e74
-
-#define REG_A2XX_TCF_PERFCOUNTER9_LOW 0x00000e77
-
-#define REG_A2XX_TCF_PERFCOUNTER10_LOW 0x00000e7a
-
-#define REG_A2XX_TCF_PERFCOUNTER11_LOW 0x00000e7d
-
-#define REG_A2XX_SQ_PERFCOUNTER0_SELECT 0x00000dc8
-
-#define REG_A2XX_SQ_PERFCOUNTER1_SELECT 0x00000dc9
-
-#define REG_A2XX_SQ_PERFCOUNTER2_SELECT 0x00000dca
-
-#define REG_A2XX_SQ_PERFCOUNTER3_SELECT 0x00000dcb
-
-#define REG_A2XX_SQ_PERFCOUNTER0_LOW 0x00000dcc
-
-#define REG_A2XX_SQ_PERFCOUNTER0_HI 0x00000dcd
-
-#define REG_A2XX_SQ_PERFCOUNTER1_LOW 0x00000dce
-
-#define REG_A2XX_SQ_PERFCOUNTER1_HI 0x00000dcf
-
-#define REG_A2XX_SQ_PERFCOUNTER2_LOW 0x00000dd0
-
-#define REG_A2XX_SQ_PERFCOUNTER2_HI 0x00000dd1
-
-#define REG_A2XX_SQ_PERFCOUNTER3_LOW 0x00000dd2
-
-#define REG_A2XX_SQ_PERFCOUNTER3_HI 0x00000dd3
-
-#define REG_A2XX_SX_PERFCOUNTER0_SELECT 0x00000dd4
-
-#define REG_A2XX_SX_PERFCOUNTER0_LOW 0x00000dd8
-
-#define REG_A2XX_SX_PERFCOUNTER0_HI 0x00000dd9
-
-#define REG_A2XX_MH_PERFCOUNTER0_SELECT 0x00000a46
-
-#define REG_A2XX_MH_PERFCOUNTER1_SELECT 0x00000a4a
-
-#define REG_A2XX_MH_PERFCOUNTER0_CONFIG 0x00000a47
-
-#define REG_A2XX_MH_PERFCOUNTER1_CONFIG 0x00000a4b
-
-#define REG_A2XX_MH_PERFCOUNTER0_LOW 0x00000a48
-
-#define REG_A2XX_MH_PERFCOUNTER1_LOW 0x00000a4c
-
-#define REG_A2XX_MH_PERFCOUNTER0_HI 0x00000a49
-
-#define REG_A2XX_MH_PERFCOUNTER1_HI 0x00000a4d
-
-#define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04
-
-#define REG_A2XX_RB_PERFCOUNTER1_SELECT 0x00000f05
-
-#define REG_A2XX_RB_PERFCOUNTER2_SELECT 0x00000f06
-
-#define REG_A2XX_RB_PERFCOUNTER3_SELECT 0x00000f07
-
-#define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08
-
-#define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09
-
-#define REG_A2XX_RB_PERFCOUNTER1_LOW 0x00000f0a
-
-#define REG_A2XX_RB_PERFCOUNTER1_HI 0x00000f0b
-
-#define REG_A2XX_RB_PERFCOUNTER2_LOW 0x00000f0c
-
-#define REG_A2XX_RB_PERFCOUNTER2_HI 0x00000f0d
-
-#define REG_A2XX_RB_PERFCOUNTER3_LOW 0x00000f0e
-
-#define REG_A2XX_RB_PERFCOUNTER3_HI 0x00000f0f
-
-#define REG_A2XX_SQ_TEX_0 0x00000000
-#define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003
-#define A2XX_SQ_TEX_0_TYPE__SHIFT 0
-static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val)
-{
- return ((val) << A2XX_SQ_TEX_0_TYPE__SHIFT) & A2XX_SQ_TEX_0_TYPE__MASK;
-}
-#define A2XX_SQ_TEX_0_SIGN_X__MASK 0x0000000c
-#define A2XX_SQ_TEX_0_SIGN_X__SHIFT 2
-static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val)
-{
- return ((val) << A2XX_SQ_TEX_0_SIGN_X__SHIFT) & A2XX_SQ_TEX_0_SIGN_X__MASK;
-}
-#define A2XX_SQ_TEX_0_SIGN_Y__MASK 0x00000030
-#define A2XX_SQ_TEX_0_SIGN_Y__SHIFT 4
-static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val)
-{
- return ((val) << A2XX_SQ_TEX_0_SIGN_Y__SHIFT) & A2XX_SQ_TEX_0_SIGN_Y__MASK;
-}
-#define A2XX_SQ_TEX_0_SIGN_Z__MASK 0x000000c0
-#define A2XX_SQ_TEX_0_SIGN_Z__SHIFT 6
-static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val)
-{
- return ((val) << A2XX_SQ_TEX_0_SIGN_Z__SHIFT) & A2XX_SQ_TEX_0_SIGN_Z__MASK;
-}
-#define A2XX_SQ_TEX_0_SIGN_W__MASK 0x00000300
-#define A2XX_SQ_TEX_0_SIGN_W__SHIFT 8
-static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val)
-{
- return ((val) << A2XX_SQ_TEX_0_SIGN_W__SHIFT) & A2XX_SQ_TEX_0_SIGN_W__MASK;
-}
-#define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00
-#define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10
-static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val)
-{
- return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK;
-}
-#define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000
-#define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13
-static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val)
-{
- return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK;
-}
-#define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000
-#define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16
-static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val)
-{
- return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK;
-}
-#define A2XX_SQ_TEX_0_PITCH__MASK 0x7fc00000
-#define A2XX_SQ_TEX_0_PITCH__SHIFT 22
-static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK;
-}
-#define A2XX_SQ_TEX_0_TILED 0x80000000
-
-#define REG_A2XX_SQ_TEX_1 0x00000001
-#define A2XX_SQ_TEX_1_FORMAT__MASK 0x0000003f
-#define A2XX_SQ_TEX_1_FORMAT__SHIFT 0
-static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val)
-{
- return ((val) << A2XX_SQ_TEX_1_FORMAT__SHIFT) & A2XX_SQ_TEX_1_FORMAT__MASK;
-}
-#define A2XX_SQ_TEX_1_ENDIANNESS__MASK 0x000000c0
-#define A2XX_SQ_TEX_1_ENDIANNESS__SHIFT 6
-static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val)
-{
- return ((val) << A2XX_SQ_TEX_1_ENDIANNESS__SHIFT) & A2XX_SQ_TEX_1_ENDIANNESS__MASK;
-}
-#define A2XX_SQ_TEX_1_REQUEST_SIZE__MASK 0x00000300
-#define A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT 8
-static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val)
-{
- return ((val) << A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT) & A2XX_SQ_TEX_1_REQUEST_SIZE__MASK;
-}
-#define A2XX_SQ_TEX_1_STACKED 0x00000400
-#define A2XX_SQ_TEX_1_CLAMP_POLICY__MASK 0x00000800
-#define A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT 11
-static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val)
-{
- return ((val) << A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT) & A2XX_SQ_TEX_1_CLAMP_POLICY__MASK;
-}
-#define A2XX_SQ_TEX_1_BASE_ADDRESS__MASK 0xfffff000
-#define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT 12
-static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK;
-}
-
-#define REG_A2XX_SQ_TEX_2 0x00000002
-#define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff
-#define A2XX_SQ_TEX_2_WIDTH__SHIFT 0
-static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val)
-{
- return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK;
-}
-#define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000
-#define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13
-static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val)
-{
- return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK;
-}
-#define A2XX_SQ_TEX_2_DEPTH__MASK 0xfc000000
-#define A2XX_SQ_TEX_2_DEPTH__SHIFT 26
-static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val)
-{
- return ((val) << A2XX_SQ_TEX_2_DEPTH__SHIFT) & A2XX_SQ_TEX_2_DEPTH__MASK;
-}
-
-#define REG_A2XX_SQ_TEX_3 0x00000003
-#define A2XX_SQ_TEX_3_NUM_FORMAT__MASK 0x00000001
-#define A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT 0
-static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val)
-{
- return ((val) << A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT) & A2XX_SQ_TEX_3_NUM_FORMAT__MASK;
-}
-#define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e
-#define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1
-static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val)
-{
- return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK;
-}
-#define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070
-#define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4
-static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val)
-{
- return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK;
-}
-#define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380
-#define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7
-static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val)
-{
- return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK;
-}
-#define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00
-#define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10
-static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val)
-{
- return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK;
-}
-#define A2XX_SQ_TEX_3_EXP_ADJUST__MASK 0x0007e000
-#define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT 13
-static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(int32_t val)
-{
- return ((val) << A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT) & A2XX_SQ_TEX_3_EXP_ADJUST__MASK;
-}
-#define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000
-#define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19
-static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val)
-{
- return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK;
-}
-#define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000
-#define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21
-static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val)
-{
- return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK;
-}
-#define A2XX_SQ_TEX_3_MIP_FILTER__MASK 0x01800000
-#define A2XX_SQ_TEX_3_MIP_FILTER__SHIFT 23
-static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val)
-{
- return ((val) << A2XX_SQ_TEX_3_MIP_FILTER__SHIFT) & A2XX_SQ_TEX_3_MIP_FILTER__MASK;
-}
-#define A2XX_SQ_TEX_3_ANISO_FILTER__MASK 0x0e000000
-#define A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT 25
-static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val)
-{
- return ((val) << A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT) & A2XX_SQ_TEX_3_ANISO_FILTER__MASK;
-}
-#define A2XX_SQ_TEX_3_BORDER_SIZE__MASK 0x80000000
-#define A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT 31
-static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val)
-{
- return ((val) << A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT) & A2XX_SQ_TEX_3_BORDER_SIZE__MASK;
-}
-
-#define REG_A2XX_SQ_TEX_4 0x00000004
-#define A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK 0x00000001
-#define A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT 0
-static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val)
-{
- return ((val) << A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK;
-}
-#define A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK 0x00000002
-#define A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT 1
-static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val)
-{
- return ((val) << A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK;
-}
-#define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK 0x0000003c
-#define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT 2
-static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val)
-{
- return ((val) << A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK;
-}
-#define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK 0x000003c0
-#define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT 6
-static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val)
-{
- return ((val) << A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK;
-}
-#define A2XX_SQ_TEX_4_MAX_ANISO_WALK 0x00000400
-#define A2XX_SQ_TEX_4_MIN_ANISO_WALK 0x00000800
-#define A2XX_SQ_TEX_4_LOD_BIAS__MASK 0x003ff000
-#define A2XX_SQ_TEX_4_LOD_BIAS__SHIFT 12
-static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val)
-{
- return ((((int32_t)(val * 32.0))) << A2XX_SQ_TEX_4_LOD_BIAS__SHIFT) & A2XX_SQ_TEX_4_LOD_BIAS__MASK;
-}
-#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK 0x07c00000
-#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT 22
-static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val)
-{
- return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK;
-}
-#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK 0xf8000000
-#define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT 27
-static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val)
-{
- return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK;
-}
-
-#define REG_A2XX_SQ_TEX_5 0x00000005
-#define A2XX_SQ_TEX_5_BORDER_COLOR__MASK 0x00000003
-#define A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT 0
-static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val)
-{
- return ((val) << A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT) & A2XX_SQ_TEX_5_BORDER_COLOR__MASK;
-}
-#define A2XX_SQ_TEX_5_FORCE_BCW_MAX 0x00000004
-#define A2XX_SQ_TEX_5_TRI_CLAMP__MASK 0x00000018
-#define A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT 3
-static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val)
-{
- return ((val) << A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT) & A2XX_SQ_TEX_5_TRI_CLAMP__MASK;
-}
-#define A2XX_SQ_TEX_5_ANISO_BIAS__MASK 0x000001e0
-#define A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT 5
-static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val)
-{
- return ((((int32_t)(val * 1.0))) << A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT) & A2XX_SQ_TEX_5_ANISO_BIAS__MASK;
-}
-#define A2XX_SQ_TEX_5_DIMENSION__MASK 0x00000600
-#define A2XX_SQ_TEX_5_DIMENSION__SHIFT 9
-static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val)
-{
- return ((val) << A2XX_SQ_TEX_5_DIMENSION__SHIFT) & A2XX_SQ_TEX_5_DIMENSION__MASK;
-}
-#define A2XX_SQ_TEX_5_PACKED_MIPS 0x00000800
-#define A2XX_SQ_TEX_5_MIP_ADDRESS__MASK 0xfffff000
-#define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT 12
-static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK;
-}
-
-#ifdef __cplusplus
-#endif
-
-#endif /* A2XX_XML */
diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
index 0d8133f3174b..0dc255ddf5ce 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c
@@ -113,7 +113,7 @@ static int a2xx_hw_init(struct msm_gpu *gpu)
uint32_t *ptr, len;
int i, ret;
- msm_gpummu_params(gpu->aspace->mmu, &pt_base, &tran_error);
+ a2xx_gpummu_params(gpu->aspace->mmu, &pt_base, &tran_error);
DBG("%s", gpu->name);
@@ -469,7 +469,7 @@ static struct msm_gpu_state *a2xx_gpu_state_get(struct msm_gpu *gpu)
static struct msm_gem_address_space *
a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
{
- struct msm_mmu *mmu = msm_gpummu_new(&pdev->dev, gpu);
+ struct msm_mmu *mmu = a2xx_gpummu_new(&pdev->dev, gpu);
struct msm_gem_address_space *aspace;
aspace = msm_gem_address_space_create(mmu, "gpu", SZ_16M,
diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.h b/drivers/gpu/drm/msm/adreno/a2xx_gpu.h
index 161a075f94af..53702f19990f 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.h
@@ -19,4 +19,8 @@ struct a2xx_gpu {
};
#define to_a2xx_gpu(x) container_of(x, struct a2xx_gpu, base)
+struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu);
+void a2xx_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base,
+ dma_addr_t *tran_error);
+
#endif /* __A2XX_GPU_H__ */
diff --git a/drivers/gpu/drm/msm/msm_gpummu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpummu.c
index f7d1945e0c9f..39641551eeb6 100644
--- a/drivers/gpu/drm/msm/msm_gpummu.c
+++ b/drivers/gpu/drm/msm/adreno/a2xx_gpummu.c
@@ -5,30 +5,33 @@
#include "msm_drv.h"
#include "msm_mmu.h"
-#include "adreno/adreno_gpu.h"
-#include "adreno/a2xx.xml.h"
-struct msm_gpummu {
+#include "adreno_gpu.h"
+#include "a2xx_gpu.h"
+
+#include "a2xx.xml.h"
+
+struct a2xx_gpummu {
struct msm_mmu base;
struct msm_gpu *gpu;
dma_addr_t pt_base;
uint32_t *table;
};
-#define to_msm_gpummu(x) container_of(x, struct msm_gpummu, base)
+#define to_a2xx_gpummu(x) container_of(x, struct a2xx_gpummu, base)
#define GPUMMU_VA_START SZ_16M
#define GPUMMU_VA_RANGE (0xfff * SZ_64K)
#define GPUMMU_PAGE_SIZE SZ_4K
#define TABLE_SIZE (sizeof(uint32_t) * GPUMMU_VA_RANGE / GPUMMU_PAGE_SIZE)
-static void msm_gpummu_detach(struct msm_mmu *mmu)
+static void a2xx_gpummu_detach(struct msm_mmu *mmu)
{
}
-static int msm_gpummu_map(struct msm_mmu *mmu, uint64_t iova,
+static int a2xx_gpummu_map(struct msm_mmu *mmu, uint64_t iova,
struct sg_table *sgt, size_t len, int prot)
{
- struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
+ struct a2xx_gpummu *gpummu = to_a2xx_gpummu(mmu);
unsigned idx = (iova - GPUMMU_VA_START) / GPUMMU_PAGE_SIZE;
struct sg_dma_page_iter dma_iter;
unsigned prot_bits = 0;
@@ -53,9 +56,9 @@ static int msm_gpummu_map(struct msm_mmu *mmu, uint64_t iova,
return 0;
}
-static int msm_gpummu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len)
+static int a2xx_gpummu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len)
{
- struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
+ struct a2xx_gpummu *gpummu = to_a2xx_gpummu(mmu);
unsigned idx = (iova - GPUMMU_VA_START) / GPUMMU_PAGE_SIZE;
unsigned i;
@@ -68,13 +71,13 @@ static int msm_gpummu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len)
return 0;
}
-static void msm_gpummu_resume_translation(struct msm_mmu *mmu)
+static void a2xx_gpummu_resume_translation(struct msm_mmu *mmu)
{
}
-static void msm_gpummu_destroy(struct msm_mmu *mmu)
+static void a2xx_gpummu_destroy(struct msm_mmu *mmu)
{
- struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
+ struct a2xx_gpummu *gpummu = to_a2xx_gpummu(mmu);
dma_free_attrs(mmu->dev, TABLE_SIZE, gpummu->table, gpummu->pt_base,
DMA_ATTR_FORCE_CONTIGUOUS);
@@ -83,16 +86,16 @@ static void msm_gpummu_destroy(struct msm_mmu *mmu)
}
static const struct msm_mmu_funcs funcs = {
- .detach = msm_gpummu_detach,
- .map = msm_gpummu_map,
- .unmap = msm_gpummu_unmap,
- .destroy = msm_gpummu_destroy,
- .resume_translation = msm_gpummu_resume_translation,
+ .detach = a2xx_gpummu_detach,
+ .map = a2xx_gpummu_map,
+ .unmap = a2xx_gpummu_unmap,
+ .destroy = a2xx_gpummu_destroy,
+ .resume_translation = a2xx_gpummu_resume_translation,
};
-struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu)
+struct msm_mmu *a2xx_gpummu_new(struct device *dev, struct msm_gpu *gpu)
{
- struct msm_gpummu *gpummu;
+ struct a2xx_gpummu *gpummu;
gpummu = kzalloc(sizeof(*gpummu), GFP_KERNEL);
if (!gpummu)
@@ -111,10 +114,10 @@ struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu)
return &gpummu->base;
}
-void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base,
+void a2xx_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base,
dma_addr_t *tran_error)
{
- dma_addr_t base = to_msm_gpummu(mmu)->pt_base;
+ dma_addr_t base = to_a2xx_gpummu(mmu)->pt_base;
*pt_base = base;
*tran_error = base + TABLE_SIZE; /* 32-byte aligned */
diff --git a/drivers/gpu/drm/msm/adreno/a3xx.xml.h b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
deleted file mode 100644
index 5edd740ad3bb..000000000000
--- a/drivers/gpu/drm/msm/adreno/a3xx.xml.h
+++ /dev/null
@@ -1,3268 +0,0 @@
-#ifndef A3XX_XML
-#define A3XX_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
-http://gitlab.freedesktop.org/mesa/mesa/
-git clone https://gitlab.freedesktop.org/mesa/mesa.git
-
-The rules-ng-ng source files this header was generated from are:
-
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84323 bytes, from Wed Aug 23 10:39:39 2023)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024)
-
-Copyright (C) 2013-2024 by the following authors:
-- Rob Clark <robdclark@gmail.com> Rob Clark
-- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-*/
-
-#ifdef __KERNEL__
-#include <linux/bug.h>
-#define assert(x) BUG_ON(!(x))
-#else
-#include <assert.h>
-#endif
-
-#ifdef __cplusplus
-#define __struct_cast(X)
-#else
-#define __struct_cast(X) (struct X)
-#endif
-
-enum a3xx_tile_mode {
- LINEAR = 0,
- TILE_4X4 = 1,
- TILE_32X32 = 2,
- TILE_4X2 = 3,
-};
-
-enum a3xx_state_block_id {
- HLSQ_BLOCK_ID_TP_TEX = 2,
- HLSQ_BLOCK_ID_TP_MIPMAP = 3,
- HLSQ_BLOCK_ID_SP_VS = 4,
- HLSQ_BLOCK_ID_SP_FS = 6,
-};
-
-enum a3xx_cache_opcode {
- INVALIDATE = 1,
-};
-
-enum a3xx_vtx_fmt {
- VFMT_32_FLOAT = 0,
- VFMT_32_32_FLOAT = 1,
- VFMT_32_32_32_FLOAT = 2,
- VFMT_32_32_32_32_FLOAT = 3,
- VFMT_16_FLOAT = 4,
- VFMT_16_16_FLOAT = 5,
- VFMT_16_16_16_FLOAT = 6,
- VFMT_16_16_16_16_FLOAT = 7,
- VFMT_32_FIXED = 8,
- VFMT_32_32_FIXED = 9,
- VFMT_32_32_32_FIXED = 10,
- VFMT_32_32_32_32_FIXED = 11,
- VFMT_16_SINT = 16,
- VFMT_16_16_SINT = 17,
- VFMT_16_16_16_SINT = 18,
- VFMT_16_16_16_16_SINT = 19,
- VFMT_16_UINT = 20,
- VFMT_16_16_UINT = 21,
- VFMT_16_16_16_UINT = 22,
- VFMT_16_16_16_16_UINT = 23,
- VFMT_16_SNORM = 24,
- VFMT_16_16_SNORM = 25,
- VFMT_16_16_16_SNORM = 26,
- VFMT_16_16_16_16_SNORM = 27,
- VFMT_16_UNORM = 28,
- VFMT_16_16_UNORM = 29,
- VFMT_16_16_16_UNORM = 30,
- VFMT_16_16_16_16_UNORM = 31,
- VFMT_32_UINT = 32,
- VFMT_32_32_UINT = 33,
- VFMT_32_32_32_UINT = 34,
- VFMT_32_32_32_32_UINT = 35,
- VFMT_32_SINT = 36,
- VFMT_32_32_SINT = 37,
- VFMT_32_32_32_SINT = 38,
- VFMT_32_32_32_32_SINT = 39,
- VFMT_8_UINT = 40,
- VFMT_8_8_UINT = 41,
- VFMT_8_8_8_UINT = 42,
- VFMT_8_8_8_8_UINT = 43,
- VFMT_8_UNORM = 44,
- VFMT_8_8_UNORM = 45,
- VFMT_8_8_8_UNORM = 46,
- VFMT_8_8_8_8_UNORM = 47,
- VFMT_8_SINT = 48,
- VFMT_8_8_SINT = 49,
- VFMT_8_8_8_SINT = 50,
- VFMT_8_8_8_8_SINT = 51,
- VFMT_8_SNORM = 52,
- VFMT_8_8_SNORM = 53,
- VFMT_8_8_8_SNORM = 54,
- VFMT_8_8_8_8_SNORM = 55,
- VFMT_10_10_10_2_UINT = 56,
- VFMT_10_10_10_2_UNORM = 57,
- VFMT_10_10_10_2_SINT = 58,
- VFMT_10_10_10_2_SNORM = 59,
- VFMT_2_10_10_10_UINT = 60,
- VFMT_2_10_10_10_UNORM = 61,
- VFMT_2_10_10_10_SINT = 62,
- VFMT_2_10_10_10_SNORM = 63,
- VFMT_NONE = 255,
-};
-
-enum a3xx_tex_fmt {
- TFMT_5_6_5_UNORM = 4,
- TFMT_5_5_5_1_UNORM = 5,
- TFMT_4_4_4_4_UNORM = 7,
- TFMT_Z16_UNORM = 9,
- TFMT_X8Z24_UNORM = 10,
- TFMT_Z32_FLOAT = 11,
- TFMT_UV_64X32 = 16,
- TFMT_VU_64X32 = 17,
- TFMT_Y_64X32 = 18,
- TFMT_NV12_64X32 = 19,
- TFMT_UV_LINEAR = 20,
- TFMT_VU_LINEAR = 21,
- TFMT_Y_LINEAR = 22,
- TFMT_NV12_LINEAR = 23,
- TFMT_I420_Y = 24,
- TFMT_I420_U = 26,
- TFMT_I420_V = 27,
- TFMT_ATC_RGB = 32,
- TFMT_ATC_RGBA_EXPLICIT = 33,
- TFMT_ETC1 = 34,
- TFMT_ATC_RGBA_INTERPOLATED = 35,
- TFMT_DXT1 = 36,
- TFMT_DXT3 = 37,
- TFMT_DXT5 = 38,
- TFMT_2_10_10_10_UNORM = 40,
- TFMT_10_10_10_2_UNORM = 41,
- TFMT_9_9_9_E5_FLOAT = 42,
- TFMT_11_11_10_FLOAT = 43,
- TFMT_A8_UNORM = 44,
- TFMT_L8_UNORM = 45,
- TFMT_L8_A8_UNORM = 47,
- TFMT_8_UNORM = 48,
- TFMT_8_8_UNORM = 49,
- TFMT_8_8_8_UNORM = 50,
- TFMT_8_8_8_8_UNORM = 51,
- TFMT_8_SNORM = 52,
- TFMT_8_8_SNORM = 53,
- TFMT_8_8_8_SNORM = 54,
- TFMT_8_8_8_8_SNORM = 55,
- TFMT_8_UINT = 56,
- TFMT_8_8_UINT = 57,
- TFMT_8_8_8_UINT = 58,
- TFMT_8_8_8_8_UINT = 59,
- TFMT_8_SINT = 60,
- TFMT_8_8_SINT = 61,
- TFMT_8_8_8_SINT = 62,
- TFMT_8_8_8_8_SINT = 63,
- TFMT_16_FLOAT = 64,
- TFMT_16_16_FLOAT = 65,
- TFMT_16_16_16_16_FLOAT = 67,
- TFMT_16_UINT = 68,
- TFMT_16_16_UINT = 69,
- TFMT_16_16_16_16_UINT = 71,
- TFMT_16_SINT = 72,
- TFMT_16_16_SINT = 73,
- TFMT_16_16_16_16_SINT = 75,
- TFMT_16_UNORM = 76,
- TFMT_16_16_UNORM = 77,
- TFMT_16_16_16_16_UNORM = 79,
- TFMT_16_SNORM = 80,
- TFMT_16_16_SNORM = 81,
- TFMT_16_16_16_16_SNORM = 83,
- TFMT_32_FLOAT = 84,
- TFMT_32_32_FLOAT = 85,
- TFMT_32_32_32_32_FLOAT = 87,
- TFMT_32_UINT = 88,
- TFMT_32_32_UINT = 89,
- TFMT_32_32_32_32_UINT = 91,
- TFMT_32_SINT = 92,
- TFMT_32_32_SINT = 93,
- TFMT_32_32_32_32_SINT = 95,
- TFMT_2_10_10_10_UINT = 96,
- TFMT_10_10_10_2_UINT = 97,
- TFMT_ETC2_RG11_SNORM = 112,
- TFMT_ETC2_RG11_UNORM = 113,
- TFMT_ETC2_R11_SNORM = 114,
- TFMT_ETC2_R11_UNORM = 115,
- TFMT_ETC2_RGBA8 = 116,
- TFMT_ETC2_RGB8A1 = 117,
- TFMT_ETC2_RGB8 = 118,
- TFMT_NONE = 255,
-};
-
-enum a3xx_color_fmt {
- RB_R5G6B5_UNORM = 0,
- RB_R5G5B5A1_UNORM = 1,
- RB_R4G4B4A4_UNORM = 3,
- RB_R8G8B8_UNORM = 4,
- RB_R8G8B8A8_UNORM = 8,
- RB_R8G8B8A8_SNORM = 9,
- RB_R8G8B8A8_UINT = 10,
- RB_R8G8B8A8_SINT = 11,
- RB_R8G8_UNORM = 12,
- RB_R8G8_SNORM = 13,
- RB_R8G8_UINT = 14,
- RB_R8G8_SINT = 15,
- RB_R10G10B10A2_UNORM = 16,
- RB_A2R10G10B10_UNORM = 17,
- RB_R10G10B10A2_UINT = 18,
- RB_A2R10G10B10_UINT = 19,
- RB_A8_UNORM = 20,
- RB_R8_UNORM = 21,
- RB_R16_FLOAT = 24,
- RB_R16G16_FLOAT = 25,
- RB_R16G16B16A16_FLOAT = 27,
- RB_R11G11B10_FLOAT = 28,
- RB_R16_SNORM = 32,
- RB_R16G16_SNORM = 33,
- RB_R16G16B16A16_SNORM = 35,
- RB_R16_UNORM = 36,
- RB_R16G16_UNORM = 37,
- RB_R16G16B16A16_UNORM = 39,
- RB_R16_SINT = 40,
- RB_R16G16_SINT = 41,
- RB_R16G16B16A16_SINT = 43,
- RB_R16_UINT = 44,
- RB_R16G16_UINT = 45,
- RB_R16G16B16A16_UINT = 47,
- RB_R32_FLOAT = 48,
- RB_R32G32_FLOAT = 49,
- RB_R32G32B32A32_FLOAT = 51,
- RB_R32_SINT = 52,
- RB_R32G32_SINT = 53,
- RB_R32G32B32A32_SINT = 55,
- RB_R32_UINT = 56,
- RB_R32G32_UINT = 57,
- RB_R32G32B32A32_UINT = 59,
- RB_NONE = 255,
-};
-
-enum a3xx_cp_perfcounter_select {
- CP_ALWAYS_COUNT = 0,
- CP_AHB_PFPTRANS_WAIT = 3,
- CP_AHB_NRTTRANS_WAIT = 6,
- CP_CSF_NRT_READ_WAIT = 8,
- CP_CSF_I1_FIFO_FULL = 9,
- CP_CSF_I2_FIFO_FULL = 10,
- CP_CSF_ST_FIFO_FULL = 11,
- CP_RESERVED_12 = 12,
- CP_CSF_RING_ROQ_FULL = 13,
- CP_CSF_I1_ROQ_FULL = 14,
- CP_CSF_I2_ROQ_FULL = 15,
- CP_CSF_ST_ROQ_FULL = 16,
- CP_RESERVED_17 = 17,
- CP_MIU_TAG_MEM_FULL = 18,
- CP_MIU_NRT_WRITE_STALLED = 22,
- CP_MIU_NRT_READ_STALLED = 23,
- CP_ME_REGS_RB_DONE_FIFO_FULL = 26,
- CP_ME_REGS_VS_EVENT_FIFO_FULL = 27,
- CP_ME_REGS_PS_EVENT_FIFO_FULL = 28,
- CP_ME_REGS_CF_EVENT_FIFO_FULL = 29,
- CP_ME_MICRO_RB_STARVED = 30,
- CP_AHB_RBBM_DWORD_SENT = 40,
- CP_ME_BUSY_CLOCKS = 41,
- CP_ME_WAIT_CONTEXT_AVAIL = 42,
- CP_PFP_TYPE0_PACKET = 43,
- CP_PFP_TYPE3_PACKET = 44,
- CP_CSF_RB_WPTR_NEQ_RPTR = 45,
- CP_CSF_I1_SIZE_NEQ_ZERO = 46,
- CP_CSF_I2_SIZE_NEQ_ZERO = 47,
- CP_CSF_RBI1I2_FETCHING = 48,
-};
-
-enum a3xx_gras_tse_perfcounter_select {
- GRAS_TSEPERF_INPUT_PRIM = 0,
- GRAS_TSEPERF_INPUT_NULL_PRIM = 1,
- GRAS_TSEPERF_TRIVAL_REJ_PRIM = 2,
- GRAS_TSEPERF_CLIPPED_PRIM = 3,
- GRAS_TSEPERF_NEW_PRIM = 4,
- GRAS_TSEPERF_ZERO_AREA_PRIM = 5,
- GRAS_TSEPERF_FACENESS_CULLED_PRIM = 6,
- GRAS_TSEPERF_ZERO_PIXEL_PRIM = 7,
- GRAS_TSEPERF_OUTPUT_NULL_PRIM = 8,
- GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM = 9,
- GRAS_TSEPERF_PRE_CLIP_PRIM = 10,
- GRAS_TSEPERF_POST_CLIP_PRIM = 11,
- GRAS_TSEPERF_WORKING_CYCLES = 12,
- GRAS_TSEPERF_PC_STARVE = 13,
- GRAS_TSERASPERF_STALL = 14,
-};
-
-enum a3xx_gras_ras_perfcounter_select {
- GRAS_RASPERF_16X16_TILES = 0,
- GRAS_RASPERF_8X8_TILES = 1,
- GRAS_RASPERF_4X4_TILES = 2,
- GRAS_RASPERF_WORKING_CYCLES = 3,
- GRAS_RASPERF_STALL_CYCLES_BY_RB = 4,
- GRAS_RASPERF_STALL_CYCLES_BY_VSC = 5,
- GRAS_RASPERF_STARVE_CYCLES_BY_TSE = 6,
-};
-
-enum a3xx_hlsq_perfcounter_select {
- HLSQ_PERF_SP_VS_CONSTANT = 0,
- HLSQ_PERF_SP_VS_INSTRUCTIONS = 1,
- HLSQ_PERF_SP_FS_CONSTANT = 2,
- HLSQ_PERF_SP_FS_INSTRUCTIONS = 3,
- HLSQ_PERF_TP_STATE = 4,
- HLSQ_PERF_QUADS = 5,
- HLSQ_PERF_PIXELS = 6,
- HLSQ_PERF_VERTICES = 7,
- HLSQ_PERF_FS8_THREADS = 8,
- HLSQ_PERF_FS16_THREADS = 9,
- HLSQ_PERF_FS32_THREADS = 10,
- HLSQ_PERF_VS8_THREADS = 11,
- HLSQ_PERF_VS16_THREADS = 12,
- HLSQ_PERF_SP_VS_DATA_BYTES = 13,
- HLSQ_PERF_SP_FS_DATA_BYTES = 14,
- HLSQ_PERF_ACTIVE_CYCLES = 15,
- HLSQ_PERF_STALL_CYCLES_SP_STATE = 16,
- HLSQ_PERF_STALL_CYCLES_SP_VS = 17,
- HLSQ_PERF_STALL_CYCLES_SP_FS = 18,
- HLSQ_PERF_STALL_CYCLES_UCHE = 19,
- HLSQ_PERF_RBBM_LOAD_CYCLES = 20,
- HLSQ_PERF_DI_TO_VS_START_SP0 = 21,
- HLSQ_PERF_DI_TO_FS_START_SP0 = 22,
- HLSQ_PERF_VS_START_TO_DONE_SP0 = 23,
- HLSQ_PERF_FS_START_TO_DONE_SP0 = 24,
- HLSQ_PERF_SP_STATE_COPY_CYCLES_VS = 25,
- HLSQ_PERF_SP_STATE_COPY_CYCLES_FS = 26,
- HLSQ_PERF_UCHE_LATENCY_CYCLES = 27,
- HLSQ_PERF_UCHE_LATENCY_COUNT = 28,
-};
-
-enum a3xx_pc_perfcounter_select {
- PC_PCPERF_VISIBILITY_STREAMS = 0,
- PC_PCPERF_TOTAL_INSTANCES = 1,
- PC_PCPERF_PRIMITIVES_PC_VPC = 2,
- PC_PCPERF_PRIMITIVES_KILLED_BY_VS = 3,
- PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS = 4,
- PC_PCPERF_DRAWCALLS_KILLED_BY_VS = 5,
- PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS = 6,
- PC_PCPERF_VERTICES_TO_VFD = 7,
- PC_PCPERF_REUSED_VERTICES = 8,
- PC_PCPERF_CYCLES_STALLED_BY_VFD = 9,
- PC_PCPERF_CYCLES_STALLED_BY_TSE = 10,
- PC_PCPERF_CYCLES_STALLED_BY_VBIF = 11,
- PC_PCPERF_CYCLES_IS_WORKING = 12,
-};
-
-enum a3xx_rb_perfcounter_select {
- RB_RBPERF_ACTIVE_CYCLES_ANY = 0,
- RB_RBPERF_ACTIVE_CYCLES_ALL = 1,
- RB_RBPERF_STARVE_CYCLES_BY_SP = 2,
- RB_RBPERF_STARVE_CYCLES_BY_RAS = 3,
- RB_RBPERF_STARVE_CYCLES_BY_MARB = 4,
- RB_RBPERF_STALL_CYCLES_BY_MARB = 5,
- RB_RBPERF_STALL_CYCLES_BY_HLSQ = 6,
- RB_RBPERF_RB_MARB_DATA = 7,
- RB_RBPERF_SP_RB_QUAD = 8,
- RB_RBPERF_RAS_EARLY_Z_QUADS = 9,
- RB_RBPERF_GMEM_CH0_READ = 10,
- RB_RBPERF_GMEM_CH1_READ = 11,
- RB_RBPERF_GMEM_CH0_WRITE = 12,
- RB_RBPERF_GMEM_CH1_WRITE = 13,
- RB_RBPERF_CP_CONTEXT_DONE = 14,
- RB_RBPERF_CP_CACHE_FLUSH = 15,
- RB_RBPERF_CP_ZPASS_DONE = 16,
-};
-
-enum a3xx_rbbm_perfcounter_select {
- RBBM_ALAWYS_ON = 0,
- RBBM_VBIF_BUSY = 1,
- RBBM_TSE_BUSY = 2,
- RBBM_RAS_BUSY = 3,
- RBBM_PC_DCALL_BUSY = 4,
- RBBM_PC_VSD_BUSY = 5,
- RBBM_VFD_BUSY = 6,
- RBBM_VPC_BUSY = 7,
- RBBM_UCHE_BUSY = 8,
- RBBM_VSC_BUSY = 9,
- RBBM_HLSQ_BUSY = 10,
- RBBM_ANY_RB_BUSY = 11,
- RBBM_ANY_TEX_BUSY = 12,
- RBBM_ANY_USP_BUSY = 13,
- RBBM_ANY_MARB_BUSY = 14,
- RBBM_ANY_ARB_BUSY = 15,
- RBBM_AHB_STATUS_BUSY = 16,
- RBBM_AHB_STATUS_STALLED = 17,
- RBBM_AHB_STATUS_TXFR = 18,
- RBBM_AHB_STATUS_TXFR_SPLIT = 19,
- RBBM_AHB_STATUS_TXFR_ERROR = 20,
- RBBM_AHB_STATUS_LONG_STALL = 21,
- RBBM_RBBM_STATUS_MASKED = 22,
-};
-
-enum a3xx_sp_perfcounter_select {
- SP_LM_LOAD_INSTRUCTIONS = 0,
- SP_LM_STORE_INSTRUCTIONS = 1,
- SP_LM_ATOMICS = 2,
- SP_UCHE_LOAD_INSTRUCTIONS = 3,
- SP_UCHE_STORE_INSTRUCTIONS = 4,
- SP_UCHE_ATOMICS = 5,
- SP_VS_TEX_INSTRUCTIONS = 6,
- SP_VS_CFLOW_INSTRUCTIONS = 7,
- SP_VS_EFU_INSTRUCTIONS = 8,
- SP_VS_FULL_ALU_INSTRUCTIONS = 9,
- SP_VS_HALF_ALU_INSTRUCTIONS = 10,
- SP_FS_TEX_INSTRUCTIONS = 11,
- SP_FS_CFLOW_INSTRUCTIONS = 12,
- SP_FS_EFU_INSTRUCTIONS = 13,
- SP_FS_FULL_ALU_INSTRUCTIONS = 14,
- SP_FS_HALF_ALU_INSTRUCTIONS = 15,
- SP_FS_BARY_INSTRUCTIONS = 16,
- SP_VS_INSTRUCTIONS = 17,
- SP_FS_INSTRUCTIONS = 18,
- SP_ADDR_LOCK_COUNT = 19,
- SP_UCHE_READ_TRANS = 20,
- SP_UCHE_WRITE_TRANS = 21,
- SP_EXPORT_VPC_TRANS = 22,
- SP_EXPORT_RB_TRANS = 23,
- SP_PIXELS_KILLED = 24,
- SP_ICL1_REQUESTS = 25,
- SP_ICL1_MISSES = 26,
- SP_ICL0_REQUESTS = 27,
- SP_ICL0_MISSES = 28,
- SP_ALU_ACTIVE_CYCLES = 29,
- SP_EFU_ACTIVE_CYCLES = 30,
- SP_STALL_CYCLES_BY_VPC = 31,
- SP_STALL_CYCLES_BY_TP = 32,
- SP_STALL_CYCLES_BY_UCHE = 33,
- SP_STALL_CYCLES_BY_RB = 34,
- SP_ACTIVE_CYCLES_ANY = 35,
- SP_ACTIVE_CYCLES_ALL = 36,
-};
-
-enum a3xx_tp_perfcounter_select {
- TPL1_TPPERF_L1_REQUESTS = 0,
- TPL1_TPPERF_TP0_L1_REQUESTS = 1,
- TPL1_TPPERF_TP0_L1_MISSES = 2,
- TPL1_TPPERF_TP1_L1_REQUESTS = 3,
- TPL1_TPPERF_TP1_L1_MISSES = 4,
- TPL1_TPPERF_TP2_L1_REQUESTS = 5,
- TPL1_TPPERF_TP2_L1_MISSES = 6,
- TPL1_TPPERF_TP3_L1_REQUESTS = 7,
- TPL1_TPPERF_TP3_L1_MISSES = 8,
- TPL1_TPPERF_OUTPUT_TEXELS_POINT = 9,
- TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR = 10,
- TPL1_TPPERF_OUTPUT_TEXELS_MIP = 11,
- TPL1_TPPERF_OUTPUT_TEXELS_ANISO = 12,
- TPL1_TPPERF_BILINEAR_OPS = 13,
- TPL1_TPPERF_QUADSQUADS_OFFSET = 14,
- TPL1_TPPERF_QUADQUADS_SHADOW = 15,
- TPL1_TPPERF_QUADS_ARRAY = 16,
- TPL1_TPPERF_QUADS_PROJECTION = 17,
- TPL1_TPPERF_QUADS_GRADIENT = 18,
- TPL1_TPPERF_QUADS_1D2D = 19,
- TPL1_TPPERF_QUADS_3DCUBE = 20,
- TPL1_TPPERF_ZERO_LOD = 21,
- TPL1_TPPERF_OUTPUT_TEXELS = 22,
- TPL1_TPPERF_ACTIVE_CYCLES_ANY = 23,
- TPL1_TPPERF_ACTIVE_CYCLES_ALL = 24,
- TPL1_TPPERF_STALL_CYCLES_BY_ARB = 25,
- TPL1_TPPERF_LATENCY = 26,
- TPL1_TPPERF_LATENCY_TRANS = 27,
-};
-
-enum a3xx_vfd_perfcounter_select {
- VFD_PERF_UCHE_BYTE_FETCHED = 0,
- VFD_PERF_UCHE_TRANS = 1,
- VFD_PERF_VPC_BYPASS_COMPONENTS = 2,
- VFD_PERF_FETCH_INSTRUCTIONS = 3,
- VFD_PERF_DECODE_INSTRUCTIONS = 4,
- VFD_PERF_ACTIVE_CYCLES = 5,
- VFD_PERF_STALL_CYCLES_UCHE = 6,
- VFD_PERF_STALL_CYCLES_HLSQ = 7,
- VFD_PERF_STALL_CYCLES_VPC_BYPASS = 8,
- VFD_PERF_STALL_CYCLES_VPC_ALLOC = 9,
-};
-
-enum a3xx_vpc_perfcounter_select {
- VPC_PERF_SP_LM_PRIMITIVES = 0,
- VPC_PERF_COMPONENTS_FROM_SP = 1,
- VPC_PERF_SP_LM_COMPONENTS = 2,
- VPC_PERF_ACTIVE_CYCLES = 3,
- VPC_PERF_STALL_CYCLES_LM = 4,
- VPC_PERF_STALL_CYCLES_RAS = 5,
-};
-
-enum a3xx_uche_perfcounter_select {
- UCHE_UCHEPERF_VBIF_READ_BEATS_TP = 0,
- UCHE_UCHEPERF_VBIF_READ_BEATS_VFD = 1,
- UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ = 2,
- UCHE_UCHEPERF_VBIF_READ_BEATS_MARB = 3,
- UCHE_UCHEPERF_VBIF_READ_BEATS_SP = 4,
- UCHE_UCHEPERF_READ_REQUESTS_TP = 8,
- UCHE_UCHEPERF_READ_REQUESTS_VFD = 9,
- UCHE_UCHEPERF_READ_REQUESTS_HLSQ = 10,
- UCHE_UCHEPERF_READ_REQUESTS_MARB = 11,
- UCHE_UCHEPERF_READ_REQUESTS_SP = 12,
- UCHE_UCHEPERF_WRITE_REQUESTS_MARB = 13,
- UCHE_UCHEPERF_WRITE_REQUESTS_SP = 14,
- UCHE_UCHEPERF_TAG_CHECK_FAILS = 15,
- UCHE_UCHEPERF_EVICTS = 16,
- UCHE_UCHEPERF_FLUSHES = 17,
- UCHE_UCHEPERF_VBIF_LATENCY_CYCLES = 18,
- UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES = 19,
- UCHE_UCHEPERF_ACTIVE_CYCLES = 20,
-};
-
-enum a3xx_intp_mode {
- SMOOTH = 0,
- FLAT = 1,
- ZERO = 2,
- ONE = 3,
-};
-
-enum a3xx_repl_mode {
- S = 1,
- T = 2,
- ONE_T = 3,
-};
-
-enum a3xx_tex_filter {
- A3XX_TEX_NEAREST = 0,
- A3XX_TEX_LINEAR = 1,
- A3XX_TEX_ANISO = 2,
-};
-
-enum a3xx_tex_clamp {
- A3XX_TEX_REPEAT = 0,
- A3XX_TEX_CLAMP_TO_EDGE = 1,
- A3XX_TEX_MIRROR_REPEAT = 2,
- A3XX_TEX_CLAMP_TO_BORDER = 3,
- A3XX_TEX_MIRROR_CLAMP = 4,
-};
-
-enum a3xx_tex_aniso {
- A3XX_TEX_ANISO_1 = 0,
- A3XX_TEX_ANISO_2 = 1,
- A3XX_TEX_ANISO_4 = 2,
- A3XX_TEX_ANISO_8 = 3,
- A3XX_TEX_ANISO_16 = 4,
-};
-
-enum a3xx_tex_swiz {
- A3XX_TEX_X = 0,
- A3XX_TEX_Y = 1,
- A3XX_TEX_Z = 2,
- A3XX_TEX_W = 3,
- A3XX_TEX_ZERO = 4,
- A3XX_TEX_ONE = 5,
-};
-
-enum a3xx_tex_type {
- A3XX_TEX_1D = 0,
- A3XX_TEX_2D = 1,
- A3XX_TEX_CUBE = 2,
- A3XX_TEX_3D = 3,
-};
-
-enum a3xx_tex_msaa {
- A3XX_TPL1_MSAA1X = 0,
- A3XX_TPL1_MSAA2X = 1,
- A3XX_TPL1_MSAA4X = 2,
- A3XX_TPL1_MSAA8X = 3,
-};
-
-#define A3XX_INT0_RBBM_GPU_IDLE 0x00000001
-#define A3XX_INT0_RBBM_AHB_ERROR 0x00000002
-#define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004
-#define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
-#define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
-#define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
-#define A3XX_INT0_VFD_ERROR 0x00000040
-#define A3XX_INT0_CP_SW_INT 0x00000080
-#define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
-#define A3XX_INT0_CP_OPCODE_ERROR 0x00000200
-#define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
-#define A3XX_INT0_CP_HW_FAULT 0x00000800
-#define A3XX_INT0_CP_DMA 0x00001000
-#define A3XX_INT0_CP_IB2_INT 0x00002000
-#define A3XX_INT0_CP_IB1_INT 0x00004000
-#define A3XX_INT0_CP_RB_INT 0x00008000
-#define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
-#define A3XX_INT0_CP_RB_DONE_TS 0x00020000
-#define A3XX_INT0_CP_VS_DONE_TS 0x00040000
-#define A3XX_INT0_CP_PS_DONE_TS 0x00080000
-#define A3XX_INT0_CACHE_FLUSH_TS 0x00100000
-#define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000
-#define A3XX_INT0_MISC_HANG_DETECT 0x01000000
-#define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000
-
-#define REG_A3XX_RBBM_HW_VERSION 0x00000000
-
-#define REG_A3XX_RBBM_HW_RELEASE 0x00000001
-
-#define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002
-
-#define REG_A3XX_RBBM_CLOCK_CTL 0x00000010
-
-#define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012
-
-#define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018
-
-#define REG_A3XX_RBBM_AHB_CTL0 0x00000020
-
-#define REG_A3XX_RBBM_AHB_CTL1 0x00000021
-
-#define REG_A3XX_RBBM_AHB_CMD 0x00000022
-
-#define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027
-
-#define REG_A3XX_RBBM_GPR0_CTL 0x0000002e
-
-#define REG_A3XX_RBBM_STATUS 0x00000030
-#define A3XX_RBBM_STATUS_HI_BUSY 0x00000001
-#define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
-#define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
-#define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
-#define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000
-#define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000
-#define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000
-#define A3XX_RBBM_STATUS_RB_BUSY 0x00040000
-#define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
-#define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
-#define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000
-#define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000
-#define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000
-#define A3XX_RBBM_STATUS_SP_BUSY 0x01000000
-#define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000
-#define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000
-#define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000
-#define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000
-#define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
-#define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
-#define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000
-
-#define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040
-
-#define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033
-
-#define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050
-
-#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051
-
-#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054
-
-#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057
-
-#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a
-
-#define REG_A3XX_RBBM_INT_SET_CMD 0x00000060
-#define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061
-#define REG_A3XX_RBBM_INT_0_MASK 0x00000063
-#define REG_A3XX_RBBM_INT_0_STATUS 0x00000064
-#define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080
-#define A3XX_RBBM_PERFCTR_CTL_ENABLE 0x00000001
-
-#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081
-
-#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082
-
-#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084
-
-#define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085
-
-#define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086
-
-#define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087
-
-#define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088
-
-#define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090
-
-#define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091
-
-#define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092
-
-#define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093
-
-#define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094
-
-#define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095
-
-#define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096
-
-#define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097
-
-#define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098
-
-#define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099
-
-#define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a
-
-#define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b
-
-#define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c
-
-#define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d
-
-#define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e
-
-#define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f
-
-#define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0
-
-#define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1
-
-#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2
-
-#define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3
-
-#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4
-
-#define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5
-
-#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6
-
-#define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7
-
-#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8
-
-#define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9
-
-#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa
-
-#define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab
-
-#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac
-
-#define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad
-
-#define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae
-
-#define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af
-
-#define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0
-
-#define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1
-
-#define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2
-
-#define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3
-
-#define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4
-
-#define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5
-
-#define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6
-
-#define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7
-
-#define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8
-
-#define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9
-
-#define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba
-
-#define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb
-
-#define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc
-
-#define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd
-
-#define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be
-
-#define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf
-
-#define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0
-
-#define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1
-
-#define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2
-
-#define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3
-
-#define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4
-
-#define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5
-
-#define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6
-
-#define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7
-
-#define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8
-
-#define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9
-
-#define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca
-
-#define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb
-
-#define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc
-
-#define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd
-
-#define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce
-
-#define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf
-
-#define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0
-
-#define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1
-
-#define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2
-
-#define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3
-
-#define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4
-
-#define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5
-
-#define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6
-
-#define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7
-
-#define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8
-
-#define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9
-
-#define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da
-
-#define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db
-
-#define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc
-
-#define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd
-
-#define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de
-
-#define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df
-
-#define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0
-
-#define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1
-
-#define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2
-
-#define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3
-
-#define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4
-
-#define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5
-
-#define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea
-
-#define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb
-
-#define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec
-
-#define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed
-
-#define REG_A3XX_RBBM_RBBM_CTL 0x00000100
-
-#define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111
-
-#define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112
-
-#define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9
-
-#define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca
-
-#define REG_A3XX_CP_ROQ_ADDR 0x000001cc
-
-#define REG_A3XX_CP_ROQ_DATA 0x000001cd
-
-#define REG_A3XX_CP_MERCIU_ADDR 0x000001d1
-
-#define REG_A3XX_CP_MERCIU_DATA 0x000001d2
-
-#define REG_A3XX_CP_MERCIU_DATA2 0x000001d3
-
-#define REG_A3XX_CP_MEQ_ADDR 0x000001da
-
-#define REG_A3XX_CP_MEQ_DATA 0x000001db
-
-#define REG_A3XX_CP_WFI_PEND_CTR 0x000001f5
-
-#define REG_A3XX_RBBM_PM_OVERRIDE2 0x0000039d
-
-#define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445
-
-#define REG_A3XX_CP_HW_FAULT 0x0000045c
-
-#define REG_A3XX_CP_PROTECT_CTRL 0x0000045e
-
-#define REG_A3XX_CP_PROTECT_STATUS 0x0000045f
-
-#define REG_A3XX_CP_PROTECT(i0) (0x00000460 + 0x1*(i0))
-
-static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; }
-
-#define REG_A3XX_CP_AHB_FAULT 0x0000054d
-
-#define REG_A3XX_SQ_GPR_MANAGEMENT 0x00000d00
-
-#define REG_A3XX_SQ_INST_STORE_MANAGMENT 0x00000d02
-
-#define REG_A3XX_TP0_CHICKEN 0x00000e1e
-
-#define REG_A3XX_SP_GLOBAL_MEM_SIZE 0x00000e22
-
-#define REG_A3XX_SP_GLOBAL_MEM_ADDR 0x00000e23
-
-#define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040
-#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000
-#define A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTER 0x00002000
-#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTROID 0x00004000
-#define A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTROID 0x00008000
-#define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000
-#define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000
-#define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000
-#define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000
-#define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000
-#define A3XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
-#define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000
-#define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000
-#define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000
-#define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK 0x1c000000
-#define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT 26
-static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val)
-{
- return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK;
-}
-
-#define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044
-#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
-#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
-static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
-{
- return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
-}
-#define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
-#define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
-static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
-{
- return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
-}
-
-#define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048
-#define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff
-#define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0
-static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val)
-{
- return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK;
-}
-
-#define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049
-#define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff
-#define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0
-static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val)
-{
- return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK;
-}
-
-#define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a
-#define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff
-#define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0
-static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val)
-{
- return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK;
-}
-
-#define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b
-#define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff
-#define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0
-static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val)
-{
- return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK;
-}
-
-#define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c
-#define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff
-#define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0
-static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val)
-{
- return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK;
-}
-
-#define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d
-#define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff
-#define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0
-static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val)
-{
- return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK;
-}
-
-#define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068
-#define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
-#define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
-static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val)
-{
- return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
-}
-#define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
-#define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
-static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val)
-{
- return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
-}
-
-#define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069
-#define A3XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
-#define A3XX_GRAS_SU_POINT_SIZE__SHIFT 0
-static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val)
-{
- return ((((int32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK;
-}
-
-#define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c
-#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff
-#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0
-static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val)
-{
- return ((((int32_t)(val * 1048576.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK;
-}
-
-#define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d
-#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
-#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
-static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
-{
- return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
-}
-
-#define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070
-#define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
-#define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
-#define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
-#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
-#define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
-static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
-{
- return ((((int32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
-}
-#define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
-
-#define REG_A3XX_GRAS_SC_CONTROL 0x00002072
-#define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0
-#define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4
-static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
-{
- return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
-}
-#define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00
-#define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8
-static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
-}
-#define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
-#define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
-static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
-{
- return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
-}
-
-#define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074
-#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
-#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
-#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
-static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
-{
- return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
-}
-#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
-#define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
-static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
-{
- return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
-}
-
-#define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075
-#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
-#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
-#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
-static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
-{
- return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
-}
-#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
-#define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
-static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
-{
- return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
-}
-
-#define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079
-#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
-#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
-#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
-static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
-{
- return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
-}
-#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
-#define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
-static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
-{
- return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
-}
-
-#define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a
-#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
-#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
-#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
-static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
-{
- return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
-}
-#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
-#define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
-static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
-{
- return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
-}
-
-#define REG_A3XX_RB_MODE_CONTROL 0x000020c0
-#define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080
-#define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700
-#define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8
-static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
-{
- return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK;
-}
-#define A3XX_RB_MODE_CONTROL_MRT__MASK 0x00003000
-#define A3XX_RB_MODE_CONTROL_MRT__SHIFT 12
-static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val)
-{
- return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK;
-}
-#define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000
-#define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000
-
-#define REG_A3XX_RB_RENDER_CONTROL 0x000020c1
-#define A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE 0x00000001
-#define A3XX_RB_RENDER_CONTROL_YUV_IN_ENABLE 0x00000002
-#define A3XX_RB_RENDER_CONTROL_COV_VALUE_INPUT_ENABLE 0x00000004
-#define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008
-#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0
-#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4
-static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK;
-}
-#define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000
-#define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000
-#define A3XX_RB_RENDER_CONTROL_COORD_MASK__MASK 0x0003c000
-#define A3XX_RB_RENDER_CONTROL_COORD_MASK__SHIFT 14
-static inline uint32_t A3XX_RB_RENDER_CONTROL_COORD_MASK(uint32_t val)
-{
- return ((val) << A3XX_RB_RENDER_CONTROL_COORD_MASK__SHIFT) & A3XX_RB_RENDER_CONTROL_COORD_MASK__MASK;
-}
-#define A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE 0x00080000
-#define A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE 0x00100000
-#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000
-#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000
-#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24
-static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
-{
- return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK;
-}
-#define A3XX_RB_RENDER_CONTROL_ALPHA_TO_COVERAGE 0x40000000
-#define A3XX_RB_RENDER_CONTROL_ALPHA_TO_ONE 0x80000000
-
-#define REG_A3XX_RB_MSAA_CONTROL 0x000020c2
-#define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400
-#define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000
-#define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12
-static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK;
-}
-#define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000
-#define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16
-static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val)
-{
- return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK;
-}
-
-#define REG_A3XX_RB_ALPHA_REF 0x000020c3
-#define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00
-#define A3XX_RB_ALPHA_REF_UINT__SHIFT 8
-static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val)
-{
- return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK;
-}
-#define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000
-#define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16
-static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val)
-{
- return ((_mesa_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
-}
-
-#define REG_A3XX_RB_MRT(i0) (0x000020c4 + 0x4*(i0))
-
-static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
-#define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
-#define A3XX_RB_MRT_CONTROL_BLEND 0x00000010
-#define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020
-#define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
-#define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
-static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
-{
- return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK;
-}
-#define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000
-#define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12
-static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
-{
- return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK;
-}
-#define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
-#define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
-static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
-{
- return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
-}
-
-static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; }
-#define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
-#define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
-static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val)
-{
- return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
-}
-#define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
-#define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
-static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val)
-{
- return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
-}
-#define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00
-#define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10
-static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
-}
-#define A3XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00004000
-#define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000
-#define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17
-static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
-}
-
-static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; }
-#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0
-#define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4
-static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK;
-}
-
-static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; }
-#define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
-#define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
-static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
-{
- return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
-}
-#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
-#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
-static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
-{
- return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
-}
-#define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
-#define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
-static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
-{
- return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
-}
-#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
-#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
-static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
-{
- return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
-}
-#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
-#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
-static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
-{
- return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
-}
-#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
-#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
-static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
-{
- return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
-}
-#define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000
-
-#define REG_A3XX_RB_BLEND_RED 0x000020e4
-#define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff
-#define A3XX_RB_BLEND_RED_UINT__SHIFT 0
-static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val)
-{
- return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK;
-}
-#define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
-#define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16
-static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)
-{
- return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
-}
-
-#define REG_A3XX_RB_BLEND_GREEN 0x000020e5
-#define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
-#define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0
-static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val)
-{
- return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK;
-}
-#define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
-#define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
-static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)
-{
- return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
-}
-
-#define REG_A3XX_RB_BLEND_BLUE 0x000020e6
-#define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
-#define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0
-static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val)
-{
- return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK;
-}
-#define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
-#define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
-static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)
-{
- return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
-}
-
-#define REG_A3XX_RB_BLEND_ALPHA 0x000020e7
-#define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
-#define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0
-static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val)
-{
- return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK;
-}
-#define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
-#define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
-static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
-{
- return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
-}
-
-#define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8
-
-#define REG_A3XX_RB_CLEAR_COLOR_DW1 0x000020e9
-
-#define REG_A3XX_RB_CLEAR_COLOR_DW2 0x000020ea
-
-#define REG_A3XX_RB_CLEAR_COLOR_DW3 0x000020eb
-
-#define REG_A3XX_RB_COPY_CONTROL 0x000020ec
-#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
-#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
-static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
-{
- return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
-}
-#define A3XX_RB_COPY_CONTROL_DEPTHCLEAR 0x00000008
-#define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
-#define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4
-static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
-{
- return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK;
-}
-#define A3XX_RB_COPY_CONTROL_MSAA_SRGB_DOWNSAMPLE 0x00000080
-#define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
-#define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
-static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
-{
- return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
-}
-#define A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE 0x00001000
-#define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
-#define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
-static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
-{
- assert(!(val & 0x3fff));
- return (((val >> 14)) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
-}
-
-#define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed
-#define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0
-#define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4
-static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK;
-}
-
-#define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee
-#define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
-#define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
-static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK;
-}
-
-#define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef
-#define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003
-#define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0
-static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val)
-{
- return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK;
-}
-#define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
-#define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
-static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val)
-{
- return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK;
-}
-#define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
-#define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
-static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK;
-}
-#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
-#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
-static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
-{
- return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
-}
-#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
-#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
-static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
-{
- return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
-}
-#define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
-#define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
-static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
-{
- return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
-}
-
-#define REG_A3XX_RB_DEPTH_CONTROL 0x00002100
-#define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
-#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x00000002
-#define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
-#define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008
-#define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
-#define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
-static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
-{
- return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
-}
-#define A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080
-#define A3XX_RB_DEPTH_CONTROL_Z_READ_ENABLE 0x80000000
-
-#define REG_A3XX_RB_DEPTH_CLEAR 0x00002101
-
-#define REG_A3XX_RB_DEPTH_INFO 0x00002102
-#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
-#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
-static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
-{
- return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
-}
-#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800
-#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11
-static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
-}
-
-#define REG_A3XX_RB_DEPTH_PITCH 0x00002103
-#define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff
-#define A3XX_RB_DEPTH_PITCH__SHIFT 0
-static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val)
-{
- assert(!(val & 0x7));
- return (((val >> 3)) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK;
-}
-
-#define REG_A3XX_RB_STENCIL_CONTROL 0x00002104
-#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
-#define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
-#define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
-#define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
-#define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
-static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
-{
- return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK;
-}
-#define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
-#define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
-static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
-{
- return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK;
-}
-#define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
-#define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
-static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
-{
- return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK;
-}
-#define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
-#define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
-static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
-{
- return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
-}
-#define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
-#define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
-static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
-{
- return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
-}
-#define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
-#define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
-static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
-{
- return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
-}
-#define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
-#define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
-static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
-{
- return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
-}
-#define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
-#define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
-static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
-{
- return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
-}
-
-#define REG_A3XX_RB_STENCIL_CLEAR 0x00002105
-
-#define REG_A3XX_RB_STENCIL_INFO 0x00002106
-#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff800
-#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 11
-static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
-}
-
-#define REG_A3XX_RB_STENCIL_PITCH 0x00002107
-#define A3XX_RB_STENCIL_PITCH__MASK 0xffffffff
-#define A3XX_RB_STENCIL_PITCH__SHIFT 0
-static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val)
-{
- assert(!(val & 0x7));
- return (((val >> 3)) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK;
-}
-
-#define REG_A3XX_RB_STENCILREFMASK 0x00002108
-#define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
-#define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
-static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
-{
- return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK;
-}
-#define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
-#define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
-static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
-{
- return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK;
-}
-#define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
-#define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
-static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
-{
- return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
-}
-
-#define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109
-#define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
-#define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
-static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
-{
- return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
-}
-#define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
-#define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
-static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
-{
- return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
-}
-#define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
-#define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
-static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
-{
- return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
-}
-
-#define REG_A3XX_RB_LRZ_VSC_CONTROL 0x0000210c
-#define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE 0x00000002
-
-#define REG_A3XX_RB_WINDOW_OFFSET 0x0000210e
-#define A3XX_RB_WINDOW_OFFSET_X__MASK 0x0000ffff
-#define A3XX_RB_WINDOW_OFFSET_X__SHIFT 0
-static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val)
-{
- return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK;
-}
-#define A3XX_RB_WINDOW_OFFSET_Y__MASK 0xffff0000
-#define A3XX_RB_WINDOW_OFFSET_Y__SHIFT 16
-static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val)
-{
- return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK;
-}
-
-#define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110
-#define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET 0x00000001
-#define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
-
-#define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111
-
-#define REG_A3XX_RB_Z_CLAMP_MIN 0x00002114
-
-#define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115
-
-#define REG_A3XX_VGT_BIN_BASE 0x000021e1
-
-#define REG_A3XX_VGT_BIN_SIZE 0x000021e2
-
-#define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4
-#define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000
-#define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16
-static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)
-{
- return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK;
-}
-#define A3XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000
-#define A3XX_PC_VSTREAM_CONTROL_N__SHIFT 22
-static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val)
-{
- return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK;
-}
-
-#define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea
-
-#define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec
-#define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f
-#define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0
-static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val)
-{
- return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK;
-}
-#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0
-#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5
-static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
-{
- return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK;
-}
-#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700
-#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8
-static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
-{
- return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK;
-}
-#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE 0x00001000
-#define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
-#define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
-#define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
-
-#define REG_A3XX_PC_RESTART_INDEX 0x000021ed
-
-#define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200
-#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000030
-#define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
-static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
-}
-#define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
-#define A3XX_HLSQ_CONTROL_0_REG_COMPUTEMODE 0x00000100
-#define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
-#define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
-#define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK 0x00fff000
-#define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT 12
-static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK;
-}
-#define A3XX_HLSQ_CONTROL_0_REG_FSONLYTEX 0x02000000
-#define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
-#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
-#define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
-static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
-}
-#define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
-#define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
-#define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
-#define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
-
-#define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201
-#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x000000c0
-#define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
-static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
-}
-#define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
-#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK 0x00ff0000
-#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT 16
-static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK;
-}
-#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK 0xff000000
-#define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT 24
-static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK;
-}
-
-#define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202
-#define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK 0x000003fc
-#define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT 2
-static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK;
-}
-#define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK 0x03fc0000
-#define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT 18
-static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK;
-}
-#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
-#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
-static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
-}
-
-#define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203
-#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__MASK 0x000000ff
-#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__SHIFT 0
-static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__MASK;
-}
-#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__MASK 0x0000ff00
-#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__SHIFT 8
-static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__MASK;
-}
-#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__MASK 0x00ff0000
-#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__SHIFT 16
-static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__MASK;
-}
-#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__MASK 0xff000000
-#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__SHIFT 24
-static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__MASK;
-}
-
-#define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204
-#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff
-#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
-static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
-}
-#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000
-#define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
-static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
-}
-#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
-#define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
-static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
-}
-
-#define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205
-#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff
-#define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
-static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
-}
-#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000
-#define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
-static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
-}
-#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
-#define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
-static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
-}
-
-#define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206
-#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff
-#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
-static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK;
-}
-#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000
-#define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
-static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK;
-}
-
-#define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207
-#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff
-#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
-static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK;
-}
-#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000
-#define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
-static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK;
-}
-
-#define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a
-#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK 0x00000003
-#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT 0
-static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK;
-}
-#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK 0x00000ffc
-#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT 2
-static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK;
-}
-#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK 0x003ff000
-#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT 12
-static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK;
-}
-#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK 0xffc00000
-#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT 22
-static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val)
-{
- return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK;
-}
-
-#define REG_A3XX_HLSQ_CL_GLOBAL_WORK(i0) (0x0000220b + 0x2*(i0))
-
-static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; }
-
-static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; }
-
-#define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211
-
-#define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212
-
-#define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214
-
-#define REG_A3XX_HLSQ_CL_KERNEL_GROUP(i0) (0x00002215 + 0x1*(i0))
-
-static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; }
-
-#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216
-
-#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217
-
-#define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a
-
-#define REG_A3XX_VFD_CONTROL_0 0x00002240
-#define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff
-#define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
-static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
-{
- return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
-}
-#define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000
-#define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18
-static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val)
-{
- return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK;
-}
-#define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000
-#define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22
-static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
-{
- return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
-}
-#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000
-#define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27
-static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
-{
- return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
-}
-
-#define REG_A3XX_VFD_CONTROL_1 0x00002241
-#define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000000f
-#define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
-static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
-{
- return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
-}
-#define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK 0x000000f0
-#define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT 4
-static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val)
-{
- return ((val) << A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK;
-}
-#define A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK 0x00000f00
-#define A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT 8
-static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val)
-{
- return ((val) << A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK;
-}
-#define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
-#define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
-static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
-{
- return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK;
-}
-#define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
-#define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
-static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
-{
- return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK;
-}
-
-#define REG_A3XX_VFD_INDEX_MIN 0x00002242
-
-#define REG_A3XX_VFD_INDEX_MAX 0x00002243
-
-#define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244
-
-#define REG_A3XX_VFD_INDEX_OFFSET 0x00002245
-
-#define REG_A3XX_VFD_FETCH(i0) (0x00002246 + 0x2*(i0))
-
-static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; }
-#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
-#define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
-static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
-{
- return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
-}
-#define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0000ff80
-#define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
-static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
-{
- return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
-}
-#define A3XX_VFD_FETCH_INSTR_0_INSTANCED 0x00010000
-#define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000
-#define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000
-#define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18
-static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val)
-{
- return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK;
-}
-#define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000
-#define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24
-static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val)
-{
- return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK;
-}
-
-static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; }
-
-#define REG_A3XX_VFD_DECODE(i0) (0x00002266 + 0x1*(i0))
-
-static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; }
-#define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
-#define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
-static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
-{
- return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
-}
-#define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
-#define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
-#define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
-static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val)
-{
- return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK;
-}
-#define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
-#define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12
-static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val)
-{
- return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK;
-}
-#define A3XX_VFD_DECODE_INSTR_INT 0x00100000
-#define A3XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
-#define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
-static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK;
-}
-#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
-#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
-static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
-{
- return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
-}
-#define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
-#define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
-
-#define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e
-#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f
-#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0
-static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val)
-{
- return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK;
-}
-#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00
-#define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8
-static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val)
-{
- return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK;
-}
-
-#define REG_A3XX_VPC_ATTR 0x00002280
-#define A3XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
-#define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0
-static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val)
-{
- return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK;
-}
-#define A3XX_VPC_ATTR_PSIZE 0x00000200
-#define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000
-#define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12
-static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val)
-{
- return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK;
-}
-#define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000
-#define A3XX_VPC_ATTR_LMSIZE__SHIFT 28
-static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val)
-{
- return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK;
-}
-
-#define REG_A3XX_VPC_PACK 0x00002281
-#define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
-#define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
-static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
-{
- return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
-}
-#define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
-#define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
-static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
-{
- return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
-}
-
-#define REG_A3XX_VPC_VARYING_INTERP(i0) (0x00002282 + 0x1*(i0))
-
-static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; }
-#define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK 0x00000003
-#define A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT 0
-static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK;
-}
-#define A3XX_VPC_VARYING_INTERP_MODE_C1__MASK 0x0000000c
-#define A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT 2
-static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK;
-}
-#define A3XX_VPC_VARYING_INTERP_MODE_C2__MASK 0x00000030
-#define A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT 4
-static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK;
-}
-#define A3XX_VPC_VARYING_INTERP_MODE_C3__MASK 0x000000c0
-#define A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT 6
-static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK;
-}
-#define A3XX_VPC_VARYING_INTERP_MODE_C4__MASK 0x00000300
-#define A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT 8
-static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK;
-}
-#define A3XX_VPC_VARYING_INTERP_MODE_C5__MASK 0x00000c00
-#define A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT 10
-static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK;
-}
-#define A3XX_VPC_VARYING_INTERP_MODE_C6__MASK 0x00003000
-#define A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT 12
-static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK;
-}
-#define A3XX_VPC_VARYING_INTERP_MODE_C7__MASK 0x0000c000
-#define A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT 14
-static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK;
-}
-#define A3XX_VPC_VARYING_INTERP_MODE_C8__MASK 0x00030000
-#define A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT 16
-static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK;
-}
-#define A3XX_VPC_VARYING_INTERP_MODE_C9__MASK 0x000c0000
-#define A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT 18
-static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK;
-}
-#define A3XX_VPC_VARYING_INTERP_MODE_CA__MASK 0x00300000
-#define A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT 20
-static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK;
-}
-#define A3XX_VPC_VARYING_INTERP_MODE_CB__MASK 0x00c00000
-#define A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT 22
-static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK;
-}
-#define A3XX_VPC_VARYING_INTERP_MODE_CC__MASK 0x03000000
-#define A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT 24
-static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK;
-}
-#define A3XX_VPC_VARYING_INTERP_MODE_CD__MASK 0x0c000000
-#define A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT 26
-static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK;
-}
-#define A3XX_VPC_VARYING_INTERP_MODE_CE__MASK 0x30000000
-#define A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT 28
-static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK;
-}
-#define A3XX_VPC_VARYING_INTERP_MODE_CF__MASK 0xc0000000
-#define A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT 30
-static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK;
-}
-
-#define REG_A3XX_VPC_VARYING_PS_REPL(i0) (0x00002286 + 0x1*(i0))
-
-static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; }
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK 0x00000003
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT 0
-static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK;
-}
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK 0x0000000c
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT 2
-static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK;
-}
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK 0x00000030
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT 4
-static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK;
-}
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK 0x000000c0
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT 6
-static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK;
-}
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK 0x00000300
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT 8
-static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK;
-}
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK 0x00000c00
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT 10
-static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK;
-}
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK 0x00003000
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT 12
-static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK;
-}
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK 0x0000c000
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT 14
-static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK;
-}
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK 0x00030000
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT 16
-static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK;
-}
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK 0x000c0000
-#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT 18
-static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK;
-}
-#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK 0x00300000
-#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT 20
-static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK;
-}
-#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK 0x00c00000
-#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT 22
-static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK;
-}
-#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK 0x03000000
-#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT 24
-static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK;
-}
-#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK 0x0c000000
-#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT 26
-static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK;
-}
-#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK 0x30000000
-#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT 28
-static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK;
-}
-#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK 0xc0000000
-#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT 30
-static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val)
-{
- return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK;
-}
-
-#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a
-
-#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b
-
-#define REG_A3XX_SP_SP_CTRL_REG 0x000022c0
-#define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000
-#define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x00040000
-#define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18
-static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val)
-{
- return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK;
-}
-#define A3XX_SP_SP_CTRL_REG_BINNING 0x00080000
-#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000
-#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20
-static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val)
-{
- return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK;
-}
-#define A3XX_SP_SP_CTRL_REG_L0MODE__MASK 0x00c00000
-#define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT 22
-static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val)
-{
- return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK;
-}
-
-#define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4
-#define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
-#define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
-static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
-{
- return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
-}
-#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002
-#define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1
-static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
-{
- return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK;
-}
-#define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
-#define A3XX_SP_VS_CTRL_REG0_ALUSCHMODE 0x00000008
-#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
-#define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
-static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
-#define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
-static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
-#define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
-static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
-}
-#define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
-#define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000
-#define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24
-static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK;
-}
-
-#define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5
-#define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff
-#define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
-static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
-}
-#define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00
-#define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10
-static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK;
-}
-#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000
-#define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
-static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
-}
-
-#define REG_A3XX_SP_VS_PARAM_REG 0x000022c6
-#define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
-#define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
-static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK;
-}
-#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
-#define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
-static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
-}
-#define A3XX_SP_VS_PARAM_REG_POS2DMODE 0x00010000
-#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0x01f00000
-#define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
-static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
-}
-
-#define REG_A3XX_SP_VS_OUT(i0) (0x000022c7 + 0x1*(i0))
-
-static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
-#define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
-#define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
-static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK;
-}
-#define A3XX_SP_VS_OUT_REG_A_HALF 0x00000100
-#define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
-#define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
-static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
-}
-#define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
-#define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
-static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK;
-}
-#define A3XX_SP_VS_OUT_REG_B_HALF 0x01000000
-#define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
-#define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
-static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
-}
-
-#define REG_A3XX_SP_VS_VPC_DST(i0) (0x000022d0 + 0x1*(i0))
-
-static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
-#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x0000007f
-#define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
-static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
-}
-#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x00007f00
-#define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
-static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
-}
-#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x007f0000
-#define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
-static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
-}
-#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0x7f000000
-#define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
-static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
-}
-
-#define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4
-#define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff
-#define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0
-static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK;
-}
-#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
-#define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
-static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
-}
-#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
-#define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
-static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5
-
-#define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6
-#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff
-#define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0
-static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
-{
- assert(!(val & 0x7f));
- return (((val >> 7)) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
-}
-#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00
-#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8
-static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK;
-}
-#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000
-#define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24
-static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK;
-}
-
-#define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7
-#define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f
-#define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0
-static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK;
-}
-#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0
-#define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5
-static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
-}
-
-#define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8
-
-#define REG_A3XX_SP_VS_LENGTH_REG 0x000022df
-#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff
-#define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0
-static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val)
-{
- return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK;
-}
-
-#define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0
-#define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
-#define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
-static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
-{
- return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
-}
-#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002
-#define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1
-static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
-{
- return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK;
-}
-#define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
-#define A3XX_SP_FS_CTRL_REG0_ALUSCHMODE 0x00000008
-#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
-#define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
-static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
-#define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
-static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A3XX_SP_FS_CTRL_REG0_FSBYPASSENABLE 0x00020000
-#define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP 0x00040000
-#define A3XX_SP_FS_CTRL_REG0_OUTORDERED 0x00080000
-#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
-#define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
-static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
-}
-#define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
-#define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
-#define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE 0x00800000
-#define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000
-#define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24
-static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK;
-}
-
-#define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1
-#define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff
-#define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
-static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
-}
-#define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00
-#define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10
-static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK;
-}
-#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000
-#define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20
-static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK;
-}
-#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x7f000000
-#define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24
-static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK;
-}
-
-#define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2
-#define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff
-#define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0
-static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK;
-}
-#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
-#define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
-static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
-}
-#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
-#define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
-static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3
-
-#define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4
-#define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff
-#define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0
-static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
-}
-#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00
-#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8
-static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK;
-}
-#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000
-#define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24
-static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK;
-}
-
-#define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5
-#define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f
-#define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0
-static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK;
-}
-#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0
-#define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5
-static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
-}
-
-#define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6
-
-#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8
-
-#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9
-
-#define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec
-#define A3XX_SP_FS_OUTPUT_REG_MRT__MASK 0x00000003
-#define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
-static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK;
-}
-#define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
-#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
-#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
-static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
-}
-
-#define REG_A3XX_SP_FS_MRT(i0) (0x000022f0 + 0x1*(i0))
-
-static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
-#define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
-#define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0
-static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK;
-}
-#define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
-#define A3XX_SP_FS_MRT_REG_SINT 0x00000400
-#define A3XX_SP_FS_MRT_REG_UINT 0x00000800
-
-#define REG_A3XX_SP_FS_IMAGE_OUTPUT(i0) (0x000022f4 + 0x1*(i0))
-
-static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
-#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f
-#define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0
-static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val)
-{
- return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK;
-}
-
-#define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff
-#define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff
-#define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0
-static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val)
-{
- return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK;
-}
-
-#define REG_A3XX_PA_SC_AA_CONFIG 0x00002301
-
-#define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340
-#define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff
-#define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0
-static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val)
-{
- return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK;
-}
-#define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00
-#define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8
-static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val)
-{
- return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK;
-}
-#define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000
-#define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16
-static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
-{
- return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK;
-}
-
-#define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341
-
-#define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342
-#define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff
-#define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0
-static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val)
-{
- return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK;
-}
-#define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00
-#define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8
-static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val)
-{
- return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK;
-}
-#define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000
-#define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16
-static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
-{
- return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK;
-}
-
-#define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343
-
-#define REG_A3XX_VBIF_CLKON 0x00003001
-
-#define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c
-
-#define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d
-
-#define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e
-
-#define REG_A3XX_VBIF_ABIT_SORT 0x0000301c
-
-#define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d
-
-#define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
-
-#define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
-
-#define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
-
-#define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030
-
-#define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031
-
-#define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034
-
-#define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035
-
-#define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036
-
-#define REG_A3XX_VBIF_ARB_CTL 0x0000303c
-
-#define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
-
-#define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058
-
-#define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e
-
-#define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f
-
-#define REG_A3XX_VBIF_PERF_CNT_EN 0x00003070
-#define A3XX_VBIF_PERF_CNT_EN_CNT0 0x00000001
-#define A3XX_VBIF_PERF_CNT_EN_CNT1 0x00000002
-#define A3XX_VBIF_PERF_CNT_EN_PWRCNT0 0x00000004
-#define A3XX_VBIF_PERF_CNT_EN_PWRCNT1 0x00000008
-#define A3XX_VBIF_PERF_CNT_EN_PWRCNT2 0x00000010
-
-#define REG_A3XX_VBIF_PERF_CNT_CLR 0x00003071
-#define A3XX_VBIF_PERF_CNT_CLR_CNT0 0x00000001
-#define A3XX_VBIF_PERF_CNT_CLR_CNT1 0x00000002
-#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0 0x00000004
-#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1 0x00000008
-#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2 0x00000010
-
-#define REG_A3XX_VBIF_PERF_CNT_SEL 0x00003072
-
-#define REG_A3XX_VBIF_PERF_CNT0_LO 0x00003073
-
-#define REG_A3XX_VBIF_PERF_CNT0_HI 0x00003074
-
-#define REG_A3XX_VBIF_PERF_CNT1_LO 0x00003075
-
-#define REG_A3XX_VBIF_PERF_CNT1_HI 0x00003076
-
-#define REG_A3XX_VBIF_PERF_PWR_CNT0_LO 0x00003077
-
-#define REG_A3XX_VBIF_PERF_PWR_CNT0_HI 0x00003078
-
-#define REG_A3XX_VBIF_PERF_PWR_CNT1_LO 0x00003079
-
-#define REG_A3XX_VBIF_PERF_PWR_CNT1_HI 0x0000307a
-
-#define REG_A3XX_VBIF_PERF_PWR_CNT2_LO 0x0000307b
-
-#define REG_A3XX_VBIF_PERF_PWR_CNT2_HI 0x0000307c
-
-#define REG_A3XX_VSC_BIN_SIZE 0x00000c01
-#define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
-#define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
-static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK;
-}
-#define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
-#define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
-static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK;
-}
-
-#define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02
-
-#define REG_A3XX_VSC_PIPE(i0) (0x00000c06 + 0x3*(i0))
-
-static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
-#define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff
-#define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0
-static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val)
-{
- return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK;
-}
-#define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00
-#define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10
-static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val)
-{
- return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK;
-}
-#define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000
-#define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20
-static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val)
-{
- return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK;
-}
-#define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000
-#define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24
-static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val)
-{
- return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK;
-}
-
-static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
-
-static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
-
-#define REG_A3XX_VSC_BIN_CONTROL 0x00000c3c
-#define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE 0x00000001
-
-#define REG_A3XX_UNKNOWN_0C3D 0x00000c3d
-
-#define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48
-
-#define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49
-
-#define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a
-
-#define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b
-
-#define REG_A3XX_GRAS_TSE_DEBUG_ECO 0x00000c81
-
-#define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88
-
-#define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89
-
-#define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a
-
-#define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b
-
-#define REG_A3XX_GRAS_CL_USER_PLANE(i0) (0x00000ca0 + 0x4*(i0))
-
-static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
-
-static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; }
-
-static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; }
-
-static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; }
-
-#define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0
-
-#define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR 0x00000cc1
-
-#define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6
-
-#define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7
-
-#define REG_A3XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
-#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
-#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
-static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
-{
- return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
-}
-#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x0fffc000
-#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 14
-static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
-{
- return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
-}
-
-#define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00
-
-#define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01
-
-#define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02
-
-#define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03
-
-#define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04
-
-#define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05
-
-#define REG_A3XX_UNKNOWN_0E43 0x00000e43
-
-#define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44
-
-#define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45
-
-#define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61
-
-#define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62
-
-#define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64
-
-#define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65
-
-#define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82
-
-#define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84
-
-#define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85
-
-#define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86
-
-#define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87
-
-#define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88
-
-#define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89
-
-#define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0
-#define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff
-#define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0
-static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val)
-{
- return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK;
-}
-
-#define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1
-#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff
-#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0
-static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val)
-{
- return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK;
-}
-#define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000
-#define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28
-static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val)
-{
- return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK;
-}
-#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000
-
-#define REG_A3XX_UNKNOWN_0EA6 0x00000ea6
-
-#define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4
-
-#define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5
-
-#define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6
-
-#define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7
-
-#define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8
-
-#define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9
-
-#define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca
-
-#define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb
-
-#define REG_A3XX_UNKNOWN_0EE0 0x00000ee0
-
-#define REG_A3XX_UNKNOWN_0F03 0x00000f03
-
-#define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04
-
-#define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05
-
-#define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06
-
-#define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07
-
-#define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08
-
-#define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09
-
-#define REG_A3XX_VGT_CL_INITIATOR 0x000021f0
-
-#define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9
-
-#define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc
-#define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
-#define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
-static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
-{
- return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
-}
-#define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
-#define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
-static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
-{
- return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
-}
-#define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600
-#define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9
-static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
-{
- return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
-}
-#define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800
-#define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11
-static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
-{
- return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
-}
-#define A3XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000
-#define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000
-#define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000
-#define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000
-#define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24
-static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
-{
- return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK;
-}
-
-#define REG_A3XX_VGT_IMMED_DATA 0x000021fd
-
-#define REG_A3XX_TEX_SAMP_0 0x00000000
-#define A3XX_TEX_SAMP_0_CLAMPENABLE 0x00000001
-#define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002
-#define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c
-#define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2
-static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val)
-{
- return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK;
-}
-#define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030
-#define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4
-static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val)
-{
- return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK;
-}
-#define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0
-#define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6
-static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val)
-{
- return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK;
-}
-#define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00
-#define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9
-static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val)
-{
- return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK;
-}
-#define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000
-#define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12
-static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val)
-{
- return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK;
-}
-#define A3XX_TEX_SAMP_0_ANISO__MASK 0x00038000
-#define A3XX_TEX_SAMP_0_ANISO__SHIFT 15
-static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val)
-{
- return ((val) << A3XX_TEX_SAMP_0_ANISO__SHIFT) & A3XX_TEX_SAMP_0_ANISO__MASK;
-}
-#define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK 0x00700000
-#define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT 20
-static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val)
-{
- return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK;
-}
-#define A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF 0x01000000
-#define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000
-
-#define REG_A3XX_TEX_SAMP_1 0x00000001
-#define A3XX_TEX_SAMP_1_LOD_BIAS__MASK 0x000007ff
-#define A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT 0
-static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val)
-{
- return ((((int32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK;
-}
-#define A3XX_TEX_SAMP_1_MAX_LOD__MASK 0x003ff000
-#define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT 12
-static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val)
-{
- return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK;
-}
-#define A3XX_TEX_SAMP_1_MIN_LOD__MASK 0xffc00000
-#define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT 22
-static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val)
-{
- return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK;
-}
-
-#define REG_A3XX_TEX_CONST_0 0x00000000
-#define A3XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
-#define A3XX_TEX_CONST_0_TILE_MODE__SHIFT 0
-static inline uint32_t A3XX_TEX_CONST_0_TILE_MODE(enum a3xx_tile_mode val)
-{
- return ((val) << A3XX_TEX_CONST_0_TILE_MODE__SHIFT) & A3XX_TEX_CONST_0_TILE_MODE__MASK;
-}
-#define A3XX_TEX_CONST_0_SRGB 0x00000004
-#define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
-#define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4
-static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val)
-{
- return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK;
-}
-#define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
-#define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
-static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val)
-{
- return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK;
-}
-#define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
-#define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
-static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val)
-{
- return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK;
-}
-#define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
-#define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13
-static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val)
-{
- return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK;
-}
-#define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
-#define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16
-static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val)
-{
- return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK;
-}
-#define A3XX_TEX_CONST_0_MSAATEX__MASK 0x00300000
-#define A3XX_TEX_CONST_0_MSAATEX__SHIFT 20
-static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val)
-{
- return ((val) << A3XX_TEX_CONST_0_MSAATEX__SHIFT) & A3XX_TEX_CONST_0_MSAATEX__MASK;
-}
-#define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000
-#define A3XX_TEX_CONST_0_FMT__SHIFT 22
-static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
-{
- return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK;
-}
-#define A3XX_TEX_CONST_0_NOCONVERT 0x20000000
-#define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000
-#define A3XX_TEX_CONST_0_TYPE__SHIFT 30
-static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val)
-{
- return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK;
-}
-
-#define REG_A3XX_TEX_CONST_1 0x00000001
-#define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff
-#define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0
-static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val)
-{
- return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK;
-}
-#define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000
-#define A3XX_TEX_CONST_1_WIDTH__SHIFT 14
-static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val)
-{
- return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK;
-}
-#define A3XX_TEX_CONST_1_PITCHALIGN__MASK 0xf0000000
-#define A3XX_TEX_CONST_1_PITCHALIGN__SHIFT 28
-static inline uint32_t A3XX_TEX_CONST_1_PITCHALIGN(uint32_t val)
-{
- return ((val) << A3XX_TEX_CONST_1_PITCHALIGN__SHIFT) & A3XX_TEX_CONST_1_PITCHALIGN__MASK;
-}
-
-#define REG_A3XX_TEX_CONST_2 0x00000002
-#define A3XX_TEX_CONST_2_INDX__MASK 0x000001ff
-#define A3XX_TEX_CONST_2_INDX__SHIFT 0
-static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val)
-{
- return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK;
-}
-#define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000
-#define A3XX_TEX_CONST_2_PITCH__SHIFT 12
-static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val)
-{
- return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK;
-}
-#define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000
-#define A3XX_TEX_CONST_2_SWAP__SHIFT 30
-static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK;
-}
-
-#define REG_A3XX_TEX_CONST_3 0x00000003
-#define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x0001ffff
-#define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0
-static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK;
-}
-#define A3XX_TEX_CONST_3_DEPTH__MASK 0x0ffe0000
-#define A3XX_TEX_CONST_3_DEPTH__SHIFT 17
-static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val)
-{
- return ((val) << A3XX_TEX_CONST_3_DEPTH__SHIFT) & A3XX_TEX_CONST_3_DEPTH__MASK;
-}
-#define A3XX_TEX_CONST_3_LAYERSZ2__MASK 0xf0000000
-#define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT 28
-static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK;
-}
-
-#ifdef __cplusplus
-#endif
-
-#endif /* A3XX_XML */
diff --git a/drivers/gpu/drm/msm/adreno/a4xx.xml.h b/drivers/gpu/drm/msm/adreno/a4xx.xml.h
deleted file mode 100644
index 103a416a787f..000000000000
--- a/drivers/gpu/drm/msm/adreno/a4xx.xml.h
+++ /dev/null
@@ -1,4379 +0,0 @@
-#ifndef A4XX_XML
-#define A4XX_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
-http://gitlab.freedesktop.org/mesa/mesa/
-git clone https://gitlab.freedesktop.org/mesa/mesa.git
-
-The rules-ng-ng source files this header was generated from are:
-
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from Fri Jun 2 14:59:26 2023)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024)
-
-Copyright (C) 2013-2024 by the following authors:
-- Rob Clark <robdclark@gmail.com> Rob Clark
-- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-*/
-
-#ifdef __KERNEL__
-#include <linux/bug.h>
-#define assert(x) BUG_ON(!(x))
-#else
-#include <assert.h>
-#endif
-
-#ifdef __cplusplus
-#define __struct_cast(X)
-#else
-#define __struct_cast(X) (struct X)
-#endif
-
-enum a4xx_color_fmt {
- RB4_A8_UNORM = 1,
- RB4_R8_UNORM = 2,
- RB4_R8_SNORM = 3,
- RB4_R8_UINT = 4,
- RB4_R8_SINT = 5,
- RB4_R4G4B4A4_UNORM = 8,
- RB4_R5G5B5A1_UNORM = 10,
- RB4_R5G6B5_UNORM = 14,
- RB4_R8G8_UNORM = 15,
- RB4_R8G8_SNORM = 16,
- RB4_R8G8_UINT = 17,
- RB4_R8G8_SINT = 18,
- RB4_R16_UNORM = 19,
- RB4_R16_SNORM = 20,
- RB4_R16_FLOAT = 21,
- RB4_R16_UINT = 22,
- RB4_R16_SINT = 23,
- RB4_R8G8B8_UNORM = 25,
- RB4_R8G8B8A8_UNORM = 26,
- RB4_R8G8B8A8_SNORM = 28,
- RB4_R8G8B8A8_UINT = 29,
- RB4_R8G8B8A8_SINT = 30,
- RB4_R10G10B10A2_UNORM = 31,
- RB4_R10G10B10A2_UINT = 34,
- RB4_R11G11B10_FLOAT = 39,
- RB4_R16G16_UNORM = 40,
- RB4_R16G16_SNORM = 41,
- RB4_R16G16_FLOAT = 42,
- RB4_R16G16_UINT = 43,
- RB4_R16G16_SINT = 44,
- RB4_R32_FLOAT = 45,
- RB4_R32_UINT = 46,
- RB4_R32_SINT = 47,
- RB4_R16G16B16A16_UNORM = 52,
- RB4_R16G16B16A16_SNORM = 53,
- RB4_R16G16B16A16_FLOAT = 54,
- RB4_R16G16B16A16_UINT = 55,
- RB4_R16G16B16A16_SINT = 56,
- RB4_R32G32_FLOAT = 57,
- RB4_R32G32_UINT = 58,
- RB4_R32G32_SINT = 59,
- RB4_R32G32B32A32_FLOAT = 60,
- RB4_R32G32B32A32_UINT = 61,
- RB4_R32G32B32A32_SINT = 62,
- RB4_NONE = 255,
-};
-
-enum a4xx_tile_mode {
- TILE4_LINEAR = 0,
- TILE4_2 = 2,
- TILE4_3 = 3,
-};
-
-enum a4xx_vtx_fmt {
- VFMT4_32_FLOAT = 1,
- VFMT4_32_32_FLOAT = 2,
- VFMT4_32_32_32_FLOAT = 3,
- VFMT4_32_32_32_32_FLOAT = 4,
- VFMT4_16_FLOAT = 5,
- VFMT4_16_16_FLOAT = 6,
- VFMT4_16_16_16_FLOAT = 7,
- VFMT4_16_16_16_16_FLOAT = 8,
- VFMT4_32_FIXED = 9,
- VFMT4_32_32_FIXED = 10,
- VFMT4_32_32_32_FIXED = 11,
- VFMT4_32_32_32_32_FIXED = 12,
- VFMT4_11_11_10_FLOAT = 13,
- VFMT4_16_SINT = 16,
- VFMT4_16_16_SINT = 17,
- VFMT4_16_16_16_SINT = 18,
- VFMT4_16_16_16_16_SINT = 19,
- VFMT4_16_UINT = 20,
- VFMT4_16_16_UINT = 21,
- VFMT4_16_16_16_UINT = 22,
- VFMT4_16_16_16_16_UINT = 23,
- VFMT4_16_SNORM = 24,
- VFMT4_16_16_SNORM = 25,
- VFMT4_16_16_16_SNORM = 26,
- VFMT4_16_16_16_16_SNORM = 27,
- VFMT4_16_UNORM = 28,
- VFMT4_16_16_UNORM = 29,
- VFMT4_16_16_16_UNORM = 30,
- VFMT4_16_16_16_16_UNORM = 31,
- VFMT4_32_UINT = 32,
- VFMT4_32_32_UINT = 33,
- VFMT4_32_32_32_UINT = 34,
- VFMT4_32_32_32_32_UINT = 35,
- VFMT4_32_SINT = 36,
- VFMT4_32_32_SINT = 37,
- VFMT4_32_32_32_SINT = 38,
- VFMT4_32_32_32_32_SINT = 39,
- VFMT4_8_UINT = 40,
- VFMT4_8_8_UINT = 41,
- VFMT4_8_8_8_UINT = 42,
- VFMT4_8_8_8_8_UINT = 43,
- VFMT4_8_UNORM = 44,
- VFMT4_8_8_UNORM = 45,
- VFMT4_8_8_8_UNORM = 46,
- VFMT4_8_8_8_8_UNORM = 47,
- VFMT4_8_SINT = 48,
- VFMT4_8_8_SINT = 49,
- VFMT4_8_8_8_SINT = 50,
- VFMT4_8_8_8_8_SINT = 51,
- VFMT4_8_SNORM = 52,
- VFMT4_8_8_SNORM = 53,
- VFMT4_8_8_8_SNORM = 54,
- VFMT4_8_8_8_8_SNORM = 55,
- VFMT4_10_10_10_2_UINT = 56,
- VFMT4_10_10_10_2_UNORM = 57,
- VFMT4_10_10_10_2_SINT = 58,
- VFMT4_10_10_10_2_SNORM = 59,
- VFMT4_2_10_10_10_UINT = 60,
- VFMT4_2_10_10_10_UNORM = 61,
- VFMT4_2_10_10_10_SINT = 62,
- VFMT4_2_10_10_10_SNORM = 63,
- VFMT4_NONE = 255,
-};
-
-enum a4xx_tex_fmt {
- TFMT4_A8_UNORM = 3,
- TFMT4_8_UNORM = 4,
- TFMT4_8_SNORM = 5,
- TFMT4_8_UINT = 6,
- TFMT4_8_SINT = 7,
- TFMT4_4_4_4_4_UNORM = 8,
- TFMT4_5_5_5_1_UNORM = 9,
- TFMT4_5_6_5_UNORM = 11,
- TFMT4_L8_A8_UNORM = 13,
- TFMT4_8_8_UNORM = 14,
- TFMT4_8_8_SNORM = 15,
- TFMT4_8_8_UINT = 16,
- TFMT4_8_8_SINT = 17,
- TFMT4_16_UNORM = 18,
- TFMT4_16_SNORM = 19,
- TFMT4_16_FLOAT = 20,
- TFMT4_16_UINT = 21,
- TFMT4_16_SINT = 22,
- TFMT4_8_8_8_8_UNORM = 28,
- TFMT4_8_8_8_8_SNORM = 29,
- TFMT4_8_8_8_8_UINT = 30,
- TFMT4_8_8_8_8_SINT = 31,
- TFMT4_9_9_9_E5_FLOAT = 32,
- TFMT4_10_10_10_2_UNORM = 33,
- TFMT4_10_10_10_2_UINT = 34,
- TFMT4_11_11_10_FLOAT = 37,
- TFMT4_16_16_UNORM = 38,
- TFMT4_16_16_SNORM = 39,
- TFMT4_16_16_FLOAT = 40,
- TFMT4_16_16_UINT = 41,
- TFMT4_16_16_SINT = 42,
- TFMT4_32_FLOAT = 43,
- TFMT4_32_UINT = 44,
- TFMT4_32_SINT = 45,
- TFMT4_16_16_16_16_UNORM = 51,
- TFMT4_16_16_16_16_SNORM = 52,
- TFMT4_16_16_16_16_FLOAT = 53,
- TFMT4_16_16_16_16_UINT = 54,
- TFMT4_16_16_16_16_SINT = 55,
- TFMT4_32_32_FLOAT = 56,
- TFMT4_32_32_UINT = 57,
- TFMT4_32_32_SINT = 58,
- TFMT4_32_32_32_FLOAT = 59,
- TFMT4_32_32_32_UINT = 60,
- TFMT4_32_32_32_SINT = 61,
- TFMT4_32_32_32_32_FLOAT = 63,
- TFMT4_32_32_32_32_UINT = 64,
- TFMT4_32_32_32_32_SINT = 65,
- TFMT4_X8Z24_UNORM = 71,
- TFMT4_DXT1 = 86,
- TFMT4_DXT3 = 87,
- TFMT4_DXT5 = 88,
- TFMT4_RGTC1_UNORM = 90,
- TFMT4_RGTC1_SNORM = 91,
- TFMT4_RGTC2_UNORM = 94,
- TFMT4_RGTC2_SNORM = 95,
- TFMT4_BPTC_UFLOAT = 97,
- TFMT4_BPTC_FLOAT = 98,
- TFMT4_BPTC = 99,
- TFMT4_ATC_RGB = 100,
- TFMT4_ATC_RGBA_EXPLICIT = 101,
- TFMT4_ATC_RGBA_INTERPOLATED = 102,
- TFMT4_ETC2_RG11_UNORM = 103,
- TFMT4_ETC2_RG11_SNORM = 104,
- TFMT4_ETC2_R11_UNORM = 105,
- TFMT4_ETC2_R11_SNORM = 106,
- TFMT4_ETC1 = 107,
- TFMT4_ETC2_RGB8 = 108,
- TFMT4_ETC2_RGBA8 = 109,
- TFMT4_ETC2_RGB8A1 = 110,
- TFMT4_ASTC_4x4 = 111,
- TFMT4_ASTC_5x4 = 112,
- TFMT4_ASTC_5x5 = 113,
- TFMT4_ASTC_6x5 = 114,
- TFMT4_ASTC_6x6 = 115,
- TFMT4_ASTC_8x5 = 116,
- TFMT4_ASTC_8x6 = 117,
- TFMT4_ASTC_8x8 = 118,
- TFMT4_ASTC_10x5 = 119,
- TFMT4_ASTC_10x6 = 120,
- TFMT4_ASTC_10x8 = 121,
- TFMT4_ASTC_10x10 = 122,
- TFMT4_ASTC_12x10 = 123,
- TFMT4_ASTC_12x12 = 124,
- TFMT4_NONE = 255,
-};
-
-enum a4xx_depth_format {
- DEPTH4_NONE = 0,
- DEPTH4_16 = 1,
- DEPTH4_24_8 = 2,
- DEPTH4_32 = 3,
-};
-
-enum a4xx_ccu_perfcounter_select {
- CCU_BUSY_CYCLES = 0,
- CCU_RB_DEPTH_RETURN_STALL = 2,
- CCU_RB_COLOR_RETURN_STALL = 3,
- CCU_DEPTH_BLOCKS = 6,
- CCU_COLOR_BLOCKS = 7,
- CCU_DEPTH_BLOCK_HIT = 8,
- CCU_COLOR_BLOCK_HIT = 9,
- CCU_DEPTH_FLAG1_COUNT = 10,
- CCU_DEPTH_FLAG2_COUNT = 11,
- CCU_DEPTH_FLAG3_COUNT = 12,
- CCU_DEPTH_FLAG4_COUNT = 13,
- CCU_COLOR_FLAG1_COUNT = 14,
- CCU_COLOR_FLAG2_COUNT = 15,
- CCU_COLOR_FLAG3_COUNT = 16,
- CCU_COLOR_FLAG4_COUNT = 17,
- CCU_PARTIAL_BLOCK_READ = 18,
-};
-
-enum a4xx_cp_perfcounter_select {
- CP_ALWAYS_COUNT = 0,
- CP_BUSY = 1,
- CP_PFP_IDLE = 2,
- CP_PFP_BUSY_WORKING = 3,
- CP_PFP_STALL_CYCLES_ANY = 4,
- CP_PFP_STARVE_CYCLES_ANY = 5,
- CP_PFP_STARVED_PER_LOAD_ADDR = 6,
- CP_PFP_STALLED_PER_STORE_ADDR = 7,
- CP_PFP_PC_PROFILE = 8,
- CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
- CP_PFP_COND_INDIRECT_DISCARDED = 10,
- CP_LONG_RESUMPTIONS = 11,
- CP_RESUME_CYCLES = 12,
- CP_RESUME_TO_BOUNDARY_CYCLES = 13,
- CP_LONG_PREEMPTIONS = 14,
- CP_PREEMPT_CYCLES = 15,
- CP_PREEMPT_TO_BOUNDARY_CYCLES = 16,
- CP_ME_FIFO_EMPTY_PFP_IDLE = 17,
- CP_ME_FIFO_EMPTY_PFP_BUSY = 18,
- CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19,
- CP_ME_FIFO_FULL_ME_BUSY = 20,
- CP_ME_FIFO_FULL_ME_NON_WORKING = 21,
- CP_ME_WAITING_FOR_PACKETS = 22,
- CP_ME_BUSY_WORKING = 23,
- CP_ME_STARVE_CYCLES_ANY = 24,
- CP_ME_STARVE_CYCLES_PER_PROFILE = 25,
- CP_ME_STALL_CYCLES_PER_PROFILE = 26,
- CP_ME_PC_PROFILE = 27,
- CP_RCIU_FIFO_EMPTY = 28,
- CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29,
- CP_RCIU_FIFO_FULL = 30,
- CP_RCIU_FIFO_FULL_NO_CONTEXT = 31,
- CP_RCIU_FIFO_FULL_AHB_MASTER = 32,
- CP_RCIU_FIFO_FULL_OTHER = 33,
- CP_AHB_IDLE = 34,
- CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35,
- CP_AHB_STALL_ON_GRANT_SPLIT = 36,
- CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37,
- CP_AHB_BUSY_WORKING = 38,
- CP_AHB_BUSY_STALL_ON_HRDY = 39,
- CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40,
-};
-
-enum a4xx_gras_ras_perfcounter_select {
- RAS_SUPER_TILES = 0,
- RAS_8X8_TILES = 1,
- RAS_4X4_TILES = 2,
- RAS_BUSY_CYCLES = 3,
- RAS_STALL_CYCLES_BY_RB = 4,
- RAS_STALL_CYCLES_BY_VSC = 5,
- RAS_STARVE_CYCLES_BY_TSE = 6,
- RAS_SUPERTILE_CYCLES = 7,
- RAS_TILE_CYCLES = 8,
- RAS_FULLY_COVERED_SUPER_TILES = 9,
- RAS_FULLY_COVERED_8X8_TILES = 10,
- RAS_4X4_PRIM = 11,
- RAS_8X4_4X8_PRIM = 12,
- RAS_8X8_PRIM = 13,
-};
-
-enum a4xx_gras_tse_perfcounter_select {
- TSE_INPUT_PRIM = 0,
- TSE_INPUT_NULL_PRIM = 1,
- TSE_TRIVAL_REJ_PRIM = 2,
- TSE_CLIPPED_PRIM = 3,
- TSE_NEW_PRIM = 4,
- TSE_ZERO_AREA_PRIM = 5,
- TSE_FACENESS_CULLED_PRIM = 6,
- TSE_ZERO_PIXEL_PRIM = 7,
- TSE_OUTPUT_NULL_PRIM = 8,
- TSE_OUTPUT_VISIBLE_PRIM = 9,
- TSE_PRE_CLIP_PRIM = 10,
- TSE_POST_CLIP_PRIM = 11,
- TSE_BUSY_CYCLES = 12,
- TSE_PC_STARVE = 13,
- TSE_RAS_STALL = 14,
- TSE_STALL_BARYPLANE_FIFO_FULL = 15,
- TSE_STALL_ZPLANE_FIFO_FULL = 16,
-};
-
-enum a4xx_hlsq_perfcounter_select {
- HLSQ_SP_VS_STAGE_CONSTANT = 0,
- HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1,
- HLSQ_SP_FS_STAGE_CONSTANT = 2,
- HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3,
- HLSQ_TP_STATE = 4,
- HLSQ_QUADS = 5,
- HLSQ_PIXELS = 6,
- HLSQ_VERTICES = 7,
- HLSQ_SP_VS_STAGE_DATA_BYTES = 13,
- HLSQ_SP_FS_STAGE_DATA_BYTES = 14,
- HLSQ_BUSY_CYCLES = 15,
- HLSQ_STALL_CYCLES_SP_STATE = 16,
- HLSQ_STALL_CYCLES_SP_VS_STAGE = 17,
- HLSQ_STALL_CYCLES_SP_FS_STAGE = 18,
- HLSQ_STALL_CYCLES_UCHE = 19,
- HLSQ_RBBM_LOAD_CYCLES = 20,
- HLSQ_DI_TO_VS_START_SP = 21,
- HLSQ_DI_TO_FS_START_SP = 22,
- HLSQ_VS_STAGE_START_TO_DONE_SP = 23,
- HLSQ_FS_STAGE_START_TO_DONE_SP = 24,
- HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25,
- HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26,
- HLSQ_UCHE_LATENCY_CYCLES = 27,
- HLSQ_UCHE_LATENCY_COUNT = 28,
- HLSQ_STARVE_CYCLES_VFD = 29,
-};
-
-enum a4xx_pc_perfcounter_select {
- PC_VIS_STREAMS_LOADED = 0,
- PC_VPC_PRIMITIVES = 2,
- PC_DEAD_PRIM = 3,
- PC_LIVE_PRIM = 4,
- PC_DEAD_DRAWCALLS = 5,
- PC_LIVE_DRAWCALLS = 6,
- PC_VERTEX_MISSES = 7,
- PC_STALL_CYCLES_VFD = 9,
- PC_STALL_CYCLES_TSE = 10,
- PC_STALL_CYCLES_UCHE = 11,
- PC_WORKING_CYCLES = 12,
- PC_IA_VERTICES = 13,
- PC_GS_PRIMITIVES = 14,
- PC_HS_INVOCATIONS = 15,
- PC_DS_INVOCATIONS = 16,
- PC_DS_PRIMITIVES = 17,
- PC_STARVE_CYCLES_FOR_INDEX = 20,
- PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21,
- PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22,
- PC_STALL_CYCLES_TESS = 23,
- PC_STARVE_CYCLES_FOR_POSITION = 24,
- PC_MODE0_DRAWCALL = 25,
- PC_MODE1_DRAWCALL = 26,
- PC_MODE2_DRAWCALL = 27,
- PC_MODE3_DRAWCALL = 28,
- PC_MODE4_DRAWCALL = 29,
- PC_PREDICATED_DEAD_DRAWCALL = 30,
- PC_STALL_CYCLES_BY_TSE_ONLY = 31,
- PC_STALL_CYCLES_BY_VPC_ONLY = 32,
- PC_VPC_POS_DATA_TRANSACTION = 33,
- PC_BUSY_CYCLES = 34,
- PC_STARVE_CYCLES_DI = 35,
- PC_STALL_CYCLES_VPC = 36,
- TESS_WORKING_CYCLES = 37,
- TESS_NUM_CYCLES_SETUP_WORKING = 38,
- TESS_NUM_CYCLES_PTGEN_WORKING = 39,
- TESS_NUM_CYCLES_CONNGEN_WORKING = 40,
- TESS_BUSY_CYCLES = 41,
- TESS_STARVE_CYCLES_PC = 42,
- TESS_STALL_CYCLES_PC = 43,
-};
-
-enum a4xx_pwr_perfcounter_select {
- PWR_CORE_CLOCK_CYCLES = 0,
- PWR_BUSY_CLOCK_CYCLES = 1,
-};
-
-enum a4xx_rb_perfcounter_select {
- RB_BUSY_CYCLES = 0,
- RB_BUSY_CYCLES_BINNING = 1,
- RB_BUSY_CYCLES_RENDERING = 2,
- RB_BUSY_CYCLES_RESOLVE = 3,
- RB_STARVE_CYCLES_BY_SP = 4,
- RB_STARVE_CYCLES_BY_RAS = 5,
- RB_STARVE_CYCLES_BY_MARB = 6,
- RB_STALL_CYCLES_BY_MARB = 7,
- RB_STALL_CYCLES_BY_HLSQ = 8,
- RB_RB_RB_MARB_DATA = 9,
- RB_SP_RB_QUAD = 10,
- RB_RAS_RB_Z_QUADS = 11,
- RB_GMEM_CH0_READ = 12,
- RB_GMEM_CH1_READ = 13,
- RB_GMEM_CH0_WRITE = 14,
- RB_GMEM_CH1_WRITE = 15,
- RB_CP_CONTEXT_DONE = 16,
- RB_CP_CACHE_FLUSH = 17,
- RB_CP_ZPASS_DONE = 18,
- RB_STALL_FIFO0_FULL = 19,
- RB_STALL_FIFO1_FULL = 20,
- RB_STALL_FIFO2_FULL = 21,
- RB_STALL_FIFO3_FULL = 22,
- RB_RB_HLSQ_TRANSACTIONS = 23,
- RB_Z_READ = 24,
- RB_Z_WRITE = 25,
- RB_C_READ = 26,
- RB_C_WRITE = 27,
- RB_C_READ_LATENCY = 28,
- RB_Z_READ_LATENCY = 29,
- RB_STALL_BY_UCHE = 30,
- RB_MARB_UCHE_TRANSACTIONS = 31,
- RB_CACHE_STALL_MISS = 32,
- RB_CACHE_STALL_FIFO_FULL = 33,
- RB_8BIT_BLENDER_UNITS_ACTIVE = 34,
- RB_16BIT_BLENDER_UNITS_ACTIVE = 35,
- RB_SAMPLER_UNITS_ACTIVE = 36,
- RB_TOTAL_PASS = 38,
- RB_Z_PASS = 39,
- RB_Z_FAIL = 40,
- RB_S_FAIL = 41,
- RB_POWER0 = 42,
- RB_POWER1 = 43,
- RB_POWER2 = 44,
- RB_POWER3 = 45,
- RB_POWER4 = 46,
- RB_POWER5 = 47,
- RB_POWER6 = 48,
- RB_POWER7 = 49,
-};
-
-enum a4xx_rbbm_perfcounter_select {
- RBBM_ALWAYS_ON = 0,
- RBBM_VBIF_BUSY = 1,
- RBBM_TSE_BUSY = 2,
- RBBM_RAS_BUSY = 3,
- RBBM_PC_DCALL_BUSY = 4,
- RBBM_PC_VSD_BUSY = 5,
- RBBM_VFD_BUSY = 6,
- RBBM_VPC_BUSY = 7,
- RBBM_UCHE_BUSY = 8,
- RBBM_VSC_BUSY = 9,
- RBBM_HLSQ_BUSY = 10,
- RBBM_ANY_RB_BUSY = 11,
- RBBM_ANY_TPL1_BUSY = 12,
- RBBM_ANY_SP_BUSY = 13,
- RBBM_ANY_MARB_BUSY = 14,
- RBBM_ANY_ARB_BUSY = 15,
- RBBM_AHB_STATUS_BUSY = 16,
- RBBM_AHB_STATUS_STALLED = 17,
- RBBM_AHB_STATUS_TXFR = 18,
- RBBM_AHB_STATUS_TXFR_SPLIT = 19,
- RBBM_AHB_STATUS_TXFR_ERROR = 20,
- RBBM_AHB_STATUS_LONG_STALL = 21,
- RBBM_STATUS_MASKED = 22,
- RBBM_CP_BUSY_GFX_CORE_IDLE = 23,
- RBBM_TESS_BUSY = 24,
- RBBM_COM_BUSY = 25,
- RBBM_DCOM_BUSY = 32,
- RBBM_ANY_CCU_BUSY = 33,
- RBBM_DPM_BUSY = 34,
-};
-
-enum a4xx_sp_perfcounter_select {
- SP_LM_LOAD_INSTRUCTIONS = 0,
- SP_LM_STORE_INSTRUCTIONS = 1,
- SP_LM_ATOMICS = 2,
- SP_GM_LOAD_INSTRUCTIONS = 3,
- SP_GM_STORE_INSTRUCTIONS = 4,
- SP_GM_ATOMICS = 5,
- SP_VS_STAGE_TEX_INSTRUCTIONS = 6,
- SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7,
- SP_VS_STAGE_EFU_INSTRUCTIONS = 8,
- SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9,
- SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10,
- SP_FS_STAGE_TEX_INSTRUCTIONS = 11,
- SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12,
- SP_FS_STAGE_EFU_INSTRUCTIONS = 13,
- SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14,
- SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15,
- SP_VS_INSTRUCTIONS = 17,
- SP_FS_INSTRUCTIONS = 18,
- SP_ADDR_LOCK_COUNT = 19,
- SP_UCHE_READ_TRANS = 20,
- SP_UCHE_WRITE_TRANS = 21,
- SP_EXPORT_VPC_TRANS = 22,
- SP_EXPORT_RB_TRANS = 23,
- SP_PIXELS_KILLED = 24,
- SP_ICL1_REQUESTS = 25,
- SP_ICL1_MISSES = 26,
- SP_ICL0_REQUESTS = 27,
- SP_ICL0_MISSES = 28,
- SP_ALU_WORKING_CYCLES = 29,
- SP_EFU_WORKING_CYCLES = 30,
- SP_STALL_CYCLES_BY_VPC = 31,
- SP_STALL_CYCLES_BY_TP = 32,
- SP_STALL_CYCLES_BY_UCHE = 33,
- SP_STALL_CYCLES_BY_RB = 34,
- SP_BUSY_CYCLES = 35,
- SP_HS_INSTRUCTIONS = 36,
- SP_DS_INSTRUCTIONS = 37,
- SP_GS_INSTRUCTIONS = 38,
- SP_CS_INSTRUCTIONS = 39,
- SP_SCHEDULER_NON_WORKING = 40,
- SP_WAVE_CONTEXTS = 41,
- SP_WAVE_CONTEXT_CYCLES = 42,
- SP_POWER0 = 43,
- SP_POWER1 = 44,
- SP_POWER2 = 45,
- SP_POWER3 = 46,
- SP_POWER4 = 47,
- SP_POWER5 = 48,
- SP_POWER6 = 49,
- SP_POWER7 = 50,
- SP_POWER8 = 51,
- SP_POWER9 = 52,
- SP_POWER10 = 53,
- SP_POWER11 = 54,
- SP_POWER12 = 55,
- SP_POWER13 = 56,
- SP_POWER14 = 57,
- SP_POWER15 = 58,
-};
-
-enum a4xx_tp_perfcounter_select {
- TP_L1_REQUESTS = 0,
- TP_L1_MISSES = 1,
- TP_QUADS_OFFSET = 8,
- TP_QUAD_SHADOW = 9,
- TP_QUADS_ARRAY = 10,
- TP_QUADS_GRADIENT = 11,
- TP_QUADS_1D2D = 12,
- TP_QUADS_3DCUBE = 13,
- TP_BUSY_CYCLES = 16,
- TP_STALL_CYCLES_BY_ARB = 17,
- TP_STATE_CACHE_REQUESTS = 20,
- TP_STATE_CACHE_MISSES = 21,
- TP_POWER0 = 22,
- TP_POWER1 = 23,
- TP_POWER2 = 24,
- TP_POWER3 = 25,
- TP_POWER4 = 26,
- TP_POWER5 = 27,
- TP_POWER6 = 28,
- TP_POWER7 = 29,
-};
-
-enum a4xx_uche_perfcounter_select {
- UCHE_VBIF_READ_BEATS_TP = 0,
- UCHE_VBIF_READ_BEATS_VFD = 1,
- UCHE_VBIF_READ_BEATS_HLSQ = 2,
- UCHE_VBIF_READ_BEATS_MARB = 3,
- UCHE_VBIF_READ_BEATS_SP = 4,
- UCHE_READ_REQUESTS_TP = 5,
- UCHE_READ_REQUESTS_VFD = 6,
- UCHE_READ_REQUESTS_HLSQ = 7,
- UCHE_READ_REQUESTS_MARB = 8,
- UCHE_READ_REQUESTS_SP = 9,
- UCHE_WRITE_REQUESTS_MARB = 10,
- UCHE_WRITE_REQUESTS_SP = 11,
- UCHE_TAG_CHECK_FAILS = 12,
- UCHE_EVICTS = 13,
- UCHE_FLUSHES = 14,
- UCHE_VBIF_LATENCY_CYCLES = 15,
- UCHE_VBIF_LATENCY_SAMPLES = 16,
- UCHE_BUSY_CYCLES = 17,
- UCHE_VBIF_READ_BEATS_PC = 18,
- UCHE_READ_REQUESTS_PC = 19,
- UCHE_WRITE_REQUESTS_VPC = 20,
- UCHE_STALL_BY_VBIF = 21,
- UCHE_WRITE_REQUESTS_VSC = 22,
- UCHE_POWER0 = 23,
- UCHE_POWER1 = 24,
- UCHE_POWER2 = 25,
- UCHE_POWER3 = 26,
- UCHE_POWER4 = 27,
- UCHE_POWER5 = 28,
- UCHE_POWER6 = 29,
- UCHE_POWER7 = 30,
-};
-
-enum a4xx_vbif_perfcounter_select {
- AXI_READ_REQUESTS_ID_0 = 0,
- AXI_READ_REQUESTS_ID_1 = 1,
- AXI_READ_REQUESTS_ID_2 = 2,
- AXI_READ_REQUESTS_ID_3 = 3,
- AXI_READ_REQUESTS_ID_4 = 4,
- AXI_READ_REQUESTS_ID_5 = 5,
- AXI_READ_REQUESTS_ID_6 = 6,
- AXI_READ_REQUESTS_ID_7 = 7,
- AXI_READ_REQUESTS_ID_8 = 8,
- AXI_READ_REQUESTS_ID_9 = 9,
- AXI_READ_REQUESTS_ID_10 = 10,
- AXI_READ_REQUESTS_ID_11 = 11,
- AXI_READ_REQUESTS_ID_12 = 12,
- AXI_READ_REQUESTS_ID_13 = 13,
- AXI_READ_REQUESTS_ID_14 = 14,
- AXI_READ_REQUESTS_ID_15 = 15,
- AXI0_READ_REQUESTS_TOTAL = 16,
- AXI1_READ_REQUESTS_TOTAL = 17,
- AXI2_READ_REQUESTS_TOTAL = 18,
- AXI3_READ_REQUESTS_TOTAL = 19,
- AXI_READ_REQUESTS_TOTAL = 20,
- AXI_WRITE_REQUESTS_ID_0 = 21,
- AXI_WRITE_REQUESTS_ID_1 = 22,
- AXI_WRITE_REQUESTS_ID_2 = 23,
- AXI_WRITE_REQUESTS_ID_3 = 24,
- AXI_WRITE_REQUESTS_ID_4 = 25,
- AXI_WRITE_REQUESTS_ID_5 = 26,
- AXI_WRITE_REQUESTS_ID_6 = 27,
- AXI_WRITE_REQUESTS_ID_7 = 28,
- AXI_WRITE_REQUESTS_ID_8 = 29,
- AXI_WRITE_REQUESTS_ID_9 = 30,
- AXI_WRITE_REQUESTS_ID_10 = 31,
- AXI_WRITE_REQUESTS_ID_11 = 32,
- AXI_WRITE_REQUESTS_ID_12 = 33,
- AXI_WRITE_REQUESTS_ID_13 = 34,
- AXI_WRITE_REQUESTS_ID_14 = 35,
- AXI_WRITE_REQUESTS_ID_15 = 36,
- AXI0_WRITE_REQUESTS_TOTAL = 37,
- AXI1_WRITE_REQUESTS_TOTAL = 38,
- AXI2_WRITE_REQUESTS_TOTAL = 39,
- AXI3_WRITE_REQUESTS_TOTAL = 40,
- AXI_WRITE_REQUESTS_TOTAL = 41,
- AXI_TOTAL_REQUESTS = 42,
- AXI_READ_DATA_BEATS_ID_0 = 43,
- AXI_READ_DATA_BEATS_ID_1 = 44,
- AXI_READ_DATA_BEATS_ID_2 = 45,
- AXI_READ_DATA_BEATS_ID_3 = 46,
- AXI_READ_DATA_BEATS_ID_4 = 47,
- AXI_READ_DATA_BEATS_ID_5 = 48,
- AXI_READ_DATA_BEATS_ID_6 = 49,
- AXI_READ_DATA_BEATS_ID_7 = 50,
- AXI_READ_DATA_BEATS_ID_8 = 51,
- AXI_READ_DATA_BEATS_ID_9 = 52,
- AXI_READ_DATA_BEATS_ID_10 = 53,
- AXI_READ_DATA_BEATS_ID_11 = 54,
- AXI_READ_DATA_BEATS_ID_12 = 55,
- AXI_READ_DATA_BEATS_ID_13 = 56,
- AXI_READ_DATA_BEATS_ID_14 = 57,
- AXI_READ_DATA_BEATS_ID_15 = 58,
- AXI0_READ_DATA_BEATS_TOTAL = 59,
- AXI1_READ_DATA_BEATS_TOTAL = 60,
- AXI2_READ_DATA_BEATS_TOTAL = 61,
- AXI3_READ_DATA_BEATS_TOTAL = 62,
- AXI_READ_DATA_BEATS_TOTAL = 63,
- AXI_WRITE_DATA_BEATS_ID_0 = 64,
- AXI_WRITE_DATA_BEATS_ID_1 = 65,
- AXI_WRITE_DATA_BEATS_ID_2 = 66,
- AXI_WRITE_DATA_BEATS_ID_3 = 67,
- AXI_WRITE_DATA_BEATS_ID_4 = 68,
- AXI_WRITE_DATA_BEATS_ID_5 = 69,
- AXI_WRITE_DATA_BEATS_ID_6 = 70,
- AXI_WRITE_DATA_BEATS_ID_7 = 71,
- AXI_WRITE_DATA_BEATS_ID_8 = 72,
- AXI_WRITE_DATA_BEATS_ID_9 = 73,
- AXI_WRITE_DATA_BEATS_ID_10 = 74,
- AXI_WRITE_DATA_BEATS_ID_11 = 75,
- AXI_WRITE_DATA_BEATS_ID_12 = 76,
- AXI_WRITE_DATA_BEATS_ID_13 = 77,
- AXI_WRITE_DATA_BEATS_ID_14 = 78,
- AXI_WRITE_DATA_BEATS_ID_15 = 79,
- AXI0_WRITE_DATA_BEATS_TOTAL = 80,
- AXI1_WRITE_DATA_BEATS_TOTAL = 81,
- AXI2_WRITE_DATA_BEATS_TOTAL = 82,
- AXI3_WRITE_DATA_BEATS_TOTAL = 83,
- AXI_WRITE_DATA_BEATS_TOTAL = 84,
- AXI_DATA_BEATS_TOTAL = 85,
- CYCLES_HELD_OFF_ID_0 = 86,
- CYCLES_HELD_OFF_ID_1 = 87,
- CYCLES_HELD_OFF_ID_2 = 88,
- CYCLES_HELD_OFF_ID_3 = 89,
- CYCLES_HELD_OFF_ID_4 = 90,
- CYCLES_HELD_OFF_ID_5 = 91,
- CYCLES_HELD_OFF_ID_6 = 92,
- CYCLES_HELD_OFF_ID_7 = 93,
- CYCLES_HELD_OFF_ID_8 = 94,
- CYCLES_HELD_OFF_ID_9 = 95,
- CYCLES_HELD_OFF_ID_10 = 96,
- CYCLES_HELD_OFF_ID_11 = 97,
- CYCLES_HELD_OFF_ID_12 = 98,
- CYCLES_HELD_OFF_ID_13 = 99,
- CYCLES_HELD_OFF_ID_14 = 100,
- CYCLES_HELD_OFF_ID_15 = 101,
- AXI_READ_REQUEST_HELD_OFF = 102,
- AXI_WRITE_REQUEST_HELD_OFF = 103,
- AXI_REQUEST_HELD_OFF = 104,
- AXI_WRITE_DATA_HELD_OFF = 105,
- OCMEM_AXI_READ_REQUEST_HELD_OFF = 106,
- OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107,
- OCMEM_AXI_REQUEST_HELD_OFF = 108,
- OCMEM_AXI_WRITE_DATA_HELD_OFF = 109,
- ELAPSED_CYCLES_DDR = 110,
- ELAPSED_CYCLES_OCMEM = 111,
-};
-
-enum a4xx_vfd_perfcounter_select {
- VFD_UCHE_BYTE_FETCHED = 0,
- VFD_UCHE_TRANS = 1,
- VFD_FETCH_INSTRUCTIONS = 3,
- VFD_BUSY_CYCLES = 5,
- VFD_STALL_CYCLES_UCHE = 6,
- VFD_STALL_CYCLES_HLSQ = 7,
- VFD_STALL_CYCLES_VPC_BYPASS = 8,
- VFD_STALL_CYCLES_VPC_ALLOC = 9,
- VFD_MODE_0_FIBERS = 13,
- VFD_MODE_1_FIBERS = 14,
- VFD_MODE_2_FIBERS = 15,
- VFD_MODE_3_FIBERS = 16,
- VFD_MODE_4_FIBERS = 17,
- VFD_BFIFO_STALL = 18,
- VFD_NUM_VERTICES_TOTAL = 19,
- VFD_PACKER_FULL = 20,
- VFD_UCHE_REQUEST_FIFO_FULL = 21,
- VFD_STARVE_CYCLES_PC = 22,
- VFD_STARVE_CYCLES_UCHE = 23,
-};
-
-enum a4xx_vpc_perfcounter_select {
- VPC_SP_LM_COMPONENTS = 2,
- VPC_SP0_LM_BYTES = 3,
- VPC_SP1_LM_BYTES = 4,
- VPC_SP2_LM_BYTES = 5,
- VPC_SP3_LM_BYTES = 6,
- VPC_WORKING_CYCLES = 7,
- VPC_STALL_CYCLES_LM = 8,
- VPC_STARVE_CYCLES_RAS = 9,
- VPC_STREAMOUT_CYCLES = 10,
- VPC_UCHE_TRANSACTIONS = 12,
- VPC_STALL_CYCLES_UCHE = 13,
- VPC_BUSY_CYCLES = 14,
- VPC_STARVE_CYCLES_SP = 15,
-};
-
-enum a4xx_vsc_perfcounter_select {
- VSC_BUSY_CYCLES = 0,
- VSC_WORKING_CYCLES = 1,
- VSC_STALL_CYCLES_UCHE = 2,
- VSC_STARVE_CYCLES_RAS = 3,
- VSC_EOT_NUM = 4,
-};
-
-enum a4xx_tex_filter {
- A4XX_TEX_NEAREST = 0,
- A4XX_TEX_LINEAR = 1,
- A4XX_TEX_ANISO = 2,
-};
-
-enum a4xx_tex_clamp {
- A4XX_TEX_REPEAT = 0,
- A4XX_TEX_CLAMP_TO_EDGE = 1,
- A4XX_TEX_MIRROR_REPEAT = 2,
- A4XX_TEX_CLAMP_TO_BORDER = 3,
- A4XX_TEX_MIRROR_CLAMP = 4,
-};
-
-enum a4xx_tex_aniso {
- A4XX_TEX_ANISO_1 = 0,
- A4XX_TEX_ANISO_2 = 1,
- A4XX_TEX_ANISO_4 = 2,
- A4XX_TEX_ANISO_8 = 3,
- A4XX_TEX_ANISO_16 = 4,
-};
-
-enum a4xx_tex_swiz {
- A4XX_TEX_X = 0,
- A4XX_TEX_Y = 1,
- A4XX_TEX_Z = 2,
- A4XX_TEX_W = 3,
- A4XX_TEX_ZERO = 4,
- A4XX_TEX_ONE = 5,
-};
-
-enum a4xx_tex_type {
- A4XX_TEX_1D = 0,
- A4XX_TEX_2D = 1,
- A4XX_TEX_CUBE = 2,
- A4XX_TEX_3D = 3,
- A4XX_TEX_BUFFER = 4,
-};
-
-#define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000
-#define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20
-static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
-{
- return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK;
-}
-
-#define A4XX_INT0_RBBM_GPU_IDLE 0x00000001
-#define A4XX_INT0_RBBM_AHB_ERROR 0x00000002
-#define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004
-#define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
-#define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
-#define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
-#define A4XX_INT0_VFD_ERROR 0x00000040
-#define A4XX_INT0_CP_SW_INT 0x00000080
-#define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
-#define A4XX_INT0_CP_OPCODE_ERROR 0x00000200
-#define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
-#define A4XX_INT0_CP_HW_FAULT 0x00000800
-#define A4XX_INT0_CP_DMA 0x00001000
-#define A4XX_INT0_CP_IB2_INT 0x00002000
-#define A4XX_INT0_CP_IB1_INT 0x00004000
-#define A4XX_INT0_CP_RB_INT 0x00008000
-#define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
-#define A4XX_INT0_CP_RB_DONE_TS 0x00020000
-#define A4XX_INT0_CP_VS_DONE_TS 0x00040000
-#define A4XX_INT0_CP_PS_DONE_TS 0x00080000
-#define A4XX_INT0_CACHE_FLUSH_TS 0x00100000
-#define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000
-#define A4XX_INT0_MISC_HANG_DETECT 0x01000000
-#define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000
-
-#define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0
-
-#define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7
-
-#define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8
-
-#define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9
-
-#define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca
-
-#define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb
-
-#define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc
-
-#define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd
-
-#define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce
-
-#define REG_A4XX_RB_PERFCTR_CCU_SEL_0 0x00000ccf
-
-#define REG_A4XX_RB_PERFCTR_CCU_SEL_1 0x00000cd0
-
-#define REG_A4XX_RB_PERFCTR_CCU_SEL_2 0x00000cd1
-
-#define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2
-
-#define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
-#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
-#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
-static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
-{
- return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
-}
-#define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000
-#define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16
-static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
-{
- return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
-}
-
-#define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc
-
-#define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd
-
-#define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce
-
-#define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf
-
-#define REG_A4XX_RB_MODE_CONTROL 0x000020a0
-#define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f
-#define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0
-static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
-}
-#define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00
-#define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8
-static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
-}
-#define A4XX_RB_MODE_CONTROL_ENABLE_GMEM 0x00010000
-
-#define REG_A4XX_RB_RENDER_CONTROL 0x000020a1
-#define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001
-#define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020
-
-#define REG_A4XX_RB_MSAA_CONTROL 0x000020a2
-#define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000
-#define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000
-#define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13
-static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
-{
- return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
-}
-
-#define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3
-#define A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK 0x0000000f
-#define A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT 0
-static inline uint32_t A4XX_RB_RENDER_CONTROL2_COORD_MASK(uint32_t val)
-{
- return ((val) << A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT) & A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK;
-}
-#define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010
-#define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020
-#define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040
-#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380
-#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7
-static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
-{
- return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
-}
-#define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800
-#define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_PIXEL 0x00001000
-#define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_CENTROID 0x00002000
-#define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_SAMPLE 0x00004000
-#define A4XX_RB_RENDER_CONTROL2_SIZE 0x00008000
-
-#define REG_A4XX_RB_MRT(i0) (0x000020a4 + 0x5*(i0))
-
-static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
-#define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
-#define A4XX_RB_MRT_CONTROL_BLEND 0x00000010
-#define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020
-#define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040
-#define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
-#define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
-static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
-{
- return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK;
-}
-#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
-#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
-static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
-{
- return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
-}
-
-static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }
-#define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
-#define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
-static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)
-{
- return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
-}
-#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
-#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
-static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)
-{
- return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
-}
-#define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600
-#define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9
-static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
-{
- return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
-}
-#define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800
-#define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11
-static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
-}
-#define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000
-#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000
-#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14
-static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
-{
- assert(!(val & 0xf));
- return (((val >> 4)) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
-}
-
-static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
-
-static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
-#define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8
-#define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3
-static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
-{
- return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK;
-}
-
-static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }
-#define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
-#define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
-static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
-{
- return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
-}
-#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
-#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
-static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
-{
- return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
-}
-#define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
-#define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
-static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
-{
- return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
-}
-#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
-#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
-static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
-{
- return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
-}
-#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
-#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
-static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
-{
- return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
-}
-#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
-#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
-static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
-{
- return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
-}
-
-#define REG_A4XX_RB_BLEND_RED 0x000020f0
-#define A4XX_RB_BLEND_RED_UINT__MASK 0x000000ff
-#define A4XX_RB_BLEND_RED_UINT__SHIFT 0
-static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
-{
- return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
-}
-#define A4XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
-#define A4XX_RB_BLEND_RED_SINT__SHIFT 8
-static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val)
-{
- return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK;
-}
-#define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
-#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
-static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
-{
- return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
-}
-
-#define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
-#define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff
-#define A4XX_RB_BLEND_RED_F32__SHIFT 0
-static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
-{
- return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK;
-}
-
-#define REG_A4XX_RB_BLEND_GREEN 0x000020f2
-#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
-#define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
-static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
-{
- return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
-}
-#define A4XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
-#define A4XX_RB_BLEND_GREEN_SINT__SHIFT 8
-static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val)
-{
- return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK;
-}
-#define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
-#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
-static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
-{
- return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
-}
-
-#define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
-#define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
-#define A4XX_RB_BLEND_GREEN_F32__SHIFT 0
-static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
-{
- return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK;
-}
-
-#define REG_A4XX_RB_BLEND_BLUE 0x000020f4
-#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
-#define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
-static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
-{
- return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
-}
-#define A4XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
-#define A4XX_RB_BLEND_BLUE_SINT__SHIFT 8
-static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val)
-{
- return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK;
-}
-#define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
-#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
-static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
-{
- return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
-}
-
-#define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
-#define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
-#define A4XX_RB_BLEND_BLUE_F32__SHIFT 0
-static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
-{
- return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK;
-}
-
-#define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
-#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
-#define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
-static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
-{
- return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
-}
-#define A4XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
-#define A4XX_RB_BLEND_ALPHA_SINT__SHIFT 8
-static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val)
-{
- return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK;
-}
-#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
-#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
-static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
-{
- return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
-}
-
-#define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
-#define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
-#define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0
-static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
-{
- return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK;
-}
-
-#define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8
-#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
-#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
-static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
-{
- return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
-}
-#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
-#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
-#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
-static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
-{
- return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
-}
-
-#define REG_A4XX_RB_FS_OUTPUT 0x000020f9
-#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff
-#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0
-static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
-{
- return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
-}
-#define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100
-#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000
-#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16
-static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
-{
- return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
-}
-
-#define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa
-#define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
-#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc
-#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2
-static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
-}
-
-#define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb
-#define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
-#define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
-static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
-{
- return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
-}
-#define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
-#define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
-static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
-{
- return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
-}
-#define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
-#define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
-static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
-{
- return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
-}
-#define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
-#define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
-static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
-{
- return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
-}
-#define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
-#define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
-static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
-{
- return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
-}
-#define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
-#define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
-static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
-{
- return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
-}
-#define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
-#define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
-static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
-{
- return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
-}
-#define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
-#define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
-static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
-{
- return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
-}
-
-#define REG_A4XX_RB_COPY_CONTROL 0x000020fc
-#define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
-#define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
-static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
-{
- return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
-}
-#define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
-#define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4
-static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
-{
- return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK;
-}
-#define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
-#define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
-static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
-{
- return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
-}
-#define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
-#define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
-static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
-{
- assert(!(val & 0x3fff));
- return (((val >> 14)) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
-}
-
-#define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd
-#define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0
-#define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5
-static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
-}
-
-#define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe
-#define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
-#define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
-static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
-}
-
-#define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff
-#define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
-#define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
-static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)
-{
- return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK;
-}
-#define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
-#define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
-static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK;
-}
-#define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
-#define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
-static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
-{
- return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
-}
-#define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
-#define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
-static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
-{
- return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
-}
-#define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
-#define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
-static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
-{
- return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
-}
-#define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000
-#define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24
-static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
-{
- return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK;
-}
-
-#define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100
-#define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f
-#define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0
-static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
-{
- return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
-}
-#define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020
-
-#define REG_A4XX_RB_DEPTH_CONTROL 0x00002101
-#define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
-#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x00000002
-#define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
-#define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
-#define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
-static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
-{
- return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
-}
-#define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080
-#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
-#define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000
-#define A4XX_RB_DEPTH_CONTROL_Z_READ_ENABLE 0x80000000
-
-#define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
-
-#define REG_A4XX_RB_DEPTH_INFO 0x00002103
-#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
-#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
-static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)
-{
- return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
-}
-#define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000
-#define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
-static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
-}
-
-#define REG_A4XX_RB_DEPTH_PITCH 0x00002104
-#define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff
-#define A4XX_RB_DEPTH_PITCH__SHIFT 0
-static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
-}
-
-#define REG_A4XX_RB_DEPTH_PITCH2 0x00002105
-#define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff
-#define A4XX_RB_DEPTH_PITCH2__SHIFT 0
-static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
-}
-
-#define REG_A4XX_RB_STENCIL_CONTROL 0x00002106
-#define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
-#define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
-#define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
-#define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
-#define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
-static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
-{
- return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK;
-}
-#define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
-#define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
-static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
-{
- return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK;
-}
-#define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
-#define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
-static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
-{
- return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK;
-}
-#define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
-#define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
-static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
-{
- return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
-}
-#define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
-#define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
-static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
-{
- return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
-}
-#define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
-#define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
-static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
-{
- return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
-}
-#define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
-#define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
-static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
-{
- return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
-}
-#define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
-#define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
-static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
-{
- return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
-}
-
-#define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107
-#define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001
-
-#define REG_A4XX_RB_STENCIL_INFO 0x00002108
-#define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
-#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000
-#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12
-static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
-}
-
-#define REG_A4XX_RB_STENCIL_PITCH 0x00002109
-#define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff
-#define A4XX_RB_STENCIL_PITCH__SHIFT 0
-static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
-}
-
-#define REG_A4XX_RB_STENCILREFMASK 0x0000210b
-#define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
-#define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
-static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
-{
- return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK;
-}
-#define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
-#define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
-static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
-{
- return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK;
-}
-#define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
-#define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
-static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
-{
- return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
-}
-
-#define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c
-#define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
-#define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
-static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
-{
- return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
-}
-#define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
-#define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
-static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
-{
- return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
-}
-#define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
-#define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
-static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
-{
- return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
-}
-
-#define REG_A4XX_RB_BIN_OFFSET 0x0000210d
-#define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
-#define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff
-#define A4XX_RB_BIN_OFFSET_X__SHIFT 0
-static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val)
-{
- return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK;
-}
-#define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000
-#define A4XX_RB_BIN_OFFSET_Y__SHIFT 16
-static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
-{
- return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
-}
-
-#define REG_A4XX_RB_VPORT_Z_CLAMP(i0) (0x00002120 + 0x2*(i0))
-
-static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
-
-static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }
-
-#define REG_A4XX_RBBM_HW_VERSION 0x00000000
-
-#define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002
-
-#define REG_A4XX_RBBM_CLOCK_CTL_TP(i0) (0x00000004 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
-
-#define REG_A4XX_RBBM_CLOCK_CTL2_TP(i0) (0x00000008 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
-
-#define REG_A4XX_RBBM_CLOCK_HYST_TP(i0) (0x0000000c + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
-
-#define REG_A4XX_RBBM_CLOCK_DELAY_TP(i0) (0x00000010 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
-
-#define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014
-
-#define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015
-
-#define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016
-
-#define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017
-
-#define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018
-
-#define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019
-
-#define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a
-
-#define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b
-
-#define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c
-
-#define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d
-
-#define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e
-
-#define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f
-
-#define REG_A4XX_RBBM_CLOCK_CTL 0x00000020
-
-#define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021
-
-#define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022
-
-#define REG_A4XX_RBBM_AHB_CTL0 0x00000023
-
-#define REG_A4XX_RBBM_AHB_CTL1 0x00000024
-
-#define REG_A4XX_RBBM_AHB_CMD 0x00000025
-
-#define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026
-
-#define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028
-
-#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b
-
-#define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f
-
-#define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034
-
-#define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036
-
-#define REG_A4XX_RBBM_INT_0_MASK 0x00000037
-
-#define REG_A4XX_RBBM_RBBM_CTL 0x0000003e
-
-#define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f
-
-#define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041
-
-#define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042
-
-#define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
-
-#define REG_A4XX_RBBM_RESET_CYCLES 0x00000047
-
-#define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049
-
-#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a
-
-#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b
-
-#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c
-
-#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d
-
-#define REG_A4XX_RBBM_POWER_CNTL_IP 0x00000098
-#define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE 0x00000001
-#define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON 0x00100000
-
-#define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c
-
-#define REG_A4XX_RBBM_PERFCTR_CP_0_HI 0x0000009d
-
-#define REG_A4XX_RBBM_PERFCTR_CP_1_LO 0x0000009e
-
-#define REG_A4XX_RBBM_PERFCTR_CP_1_HI 0x0000009f
-
-#define REG_A4XX_RBBM_PERFCTR_CP_2_LO 0x000000a0
-
-#define REG_A4XX_RBBM_PERFCTR_CP_2_HI 0x000000a1
-
-#define REG_A4XX_RBBM_PERFCTR_CP_3_LO 0x000000a2
-
-#define REG_A4XX_RBBM_PERFCTR_CP_3_HI 0x000000a3
-
-#define REG_A4XX_RBBM_PERFCTR_CP_4_LO 0x000000a4
-
-#define REG_A4XX_RBBM_PERFCTR_CP_4_HI 0x000000a5
-
-#define REG_A4XX_RBBM_PERFCTR_CP_5_LO 0x000000a6
-
-#define REG_A4XX_RBBM_PERFCTR_CP_5_HI 0x000000a7
-
-#define REG_A4XX_RBBM_PERFCTR_CP_6_LO 0x000000a8
-
-#define REG_A4XX_RBBM_PERFCTR_CP_6_HI 0x000000a9
-
-#define REG_A4XX_RBBM_PERFCTR_CP_7_LO 0x000000aa
-
-#define REG_A4XX_RBBM_PERFCTR_CP_7_HI 0x000000ab
-
-#define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO 0x000000ac
-
-#define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI 0x000000ad
-
-#define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO 0x000000ae
-
-#define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI 0x000000af
-
-#define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO 0x000000b0
-
-#define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI 0x000000b1
-
-#define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO 0x000000b2
-
-#define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI 0x000000b3
-
-#define REG_A4XX_RBBM_PERFCTR_PC_0_LO 0x000000b4
-
-#define REG_A4XX_RBBM_PERFCTR_PC_0_HI 0x000000b5
-
-#define REG_A4XX_RBBM_PERFCTR_PC_1_LO 0x000000b6
-
-#define REG_A4XX_RBBM_PERFCTR_PC_1_HI 0x000000b7
-
-#define REG_A4XX_RBBM_PERFCTR_PC_2_LO 0x000000b8
-
-#define REG_A4XX_RBBM_PERFCTR_PC_2_HI 0x000000b9
-
-#define REG_A4XX_RBBM_PERFCTR_PC_3_LO 0x000000ba
-
-#define REG_A4XX_RBBM_PERFCTR_PC_3_HI 0x000000bb
-
-#define REG_A4XX_RBBM_PERFCTR_PC_4_LO 0x000000bc
-
-#define REG_A4XX_RBBM_PERFCTR_PC_4_HI 0x000000bd
-
-#define REG_A4XX_RBBM_PERFCTR_PC_5_LO 0x000000be
-
-#define REG_A4XX_RBBM_PERFCTR_PC_5_HI 0x000000bf
-
-#define REG_A4XX_RBBM_PERFCTR_PC_6_LO 0x000000c0
-
-#define REG_A4XX_RBBM_PERFCTR_PC_6_HI 0x000000c1
-
-#define REG_A4XX_RBBM_PERFCTR_PC_7_LO 0x000000c2
-
-#define REG_A4XX_RBBM_PERFCTR_PC_7_HI 0x000000c3
-
-#define REG_A4XX_RBBM_PERFCTR_VFD_0_LO 0x000000c4
-
-#define REG_A4XX_RBBM_PERFCTR_VFD_0_HI 0x000000c5
-
-#define REG_A4XX_RBBM_PERFCTR_VFD_1_LO 0x000000c6
-
-#define REG_A4XX_RBBM_PERFCTR_VFD_1_HI 0x000000c7
-
-#define REG_A4XX_RBBM_PERFCTR_VFD_2_LO 0x000000c8
-
-#define REG_A4XX_RBBM_PERFCTR_VFD_2_HI 0x000000c9
-
-#define REG_A4XX_RBBM_PERFCTR_VFD_3_LO 0x000000ca
-
-#define REG_A4XX_RBBM_PERFCTR_VFD_3_HI 0x000000cb
-
-#define REG_A4XX_RBBM_PERFCTR_VFD_4_LO 0x000000cc
-
-#define REG_A4XX_RBBM_PERFCTR_VFD_4_HI 0x000000cd
-
-#define REG_A4XX_RBBM_PERFCTR_VFD_5_LO 0x000000ce
-
-#define REG_A4XX_RBBM_PERFCTR_VFD_5_HI 0x000000cf
-
-#define REG_A4XX_RBBM_PERFCTR_VFD_6_LO 0x000000d0
-
-#define REG_A4XX_RBBM_PERFCTR_VFD_6_HI 0x000000d1
-
-#define REG_A4XX_RBBM_PERFCTR_VFD_7_LO 0x000000d2
-
-#define REG_A4XX_RBBM_PERFCTR_VFD_7_HI 0x000000d3
-
-#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000d4
-
-#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000d5
-
-#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000d6
-
-#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000d7
-
-#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000d8
-
-#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000d9
-
-#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000da
-
-#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000db
-
-#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000dc
-
-#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000dd
-
-#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000de
-
-#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000df
-
-#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO 0x000000e0
-
-#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI 0x000000e1
-
-#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO 0x000000e2
-
-#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI 0x000000e3
-
-#define REG_A4XX_RBBM_PERFCTR_VPC_0_LO 0x000000e4
-
-#define REG_A4XX_RBBM_PERFCTR_VPC_0_HI 0x000000e5
-
-#define REG_A4XX_RBBM_PERFCTR_VPC_1_LO 0x000000e6
-
-#define REG_A4XX_RBBM_PERFCTR_VPC_1_HI 0x000000e7
-
-#define REG_A4XX_RBBM_PERFCTR_VPC_2_LO 0x000000e8
-
-#define REG_A4XX_RBBM_PERFCTR_VPC_2_HI 0x000000e9
-
-#define REG_A4XX_RBBM_PERFCTR_VPC_3_LO 0x000000ea
-
-#define REG_A4XX_RBBM_PERFCTR_VPC_3_HI 0x000000eb
-
-#define REG_A4XX_RBBM_PERFCTR_CCU_0_LO 0x000000ec
-
-#define REG_A4XX_RBBM_PERFCTR_CCU_0_HI 0x000000ed
-
-#define REG_A4XX_RBBM_PERFCTR_CCU_1_LO 0x000000ee
-
-#define REG_A4XX_RBBM_PERFCTR_CCU_1_HI 0x000000ef
-
-#define REG_A4XX_RBBM_PERFCTR_CCU_2_LO 0x000000f0
-
-#define REG_A4XX_RBBM_PERFCTR_CCU_2_HI 0x000000f1
-
-#define REG_A4XX_RBBM_PERFCTR_CCU_3_LO 0x000000f2
-
-#define REG_A4XX_RBBM_PERFCTR_CCU_3_HI 0x000000f3
-
-#define REG_A4XX_RBBM_PERFCTR_TSE_0_LO 0x000000f4
-
-#define REG_A4XX_RBBM_PERFCTR_TSE_0_HI 0x000000f5
-
-#define REG_A4XX_RBBM_PERFCTR_TSE_1_LO 0x000000f6
-
-#define REG_A4XX_RBBM_PERFCTR_TSE_1_HI 0x000000f7
-
-#define REG_A4XX_RBBM_PERFCTR_TSE_2_LO 0x000000f8
-
-#define REG_A4XX_RBBM_PERFCTR_TSE_2_HI 0x000000f9
-
-#define REG_A4XX_RBBM_PERFCTR_TSE_3_LO 0x000000fa
-
-#define REG_A4XX_RBBM_PERFCTR_TSE_3_HI 0x000000fb
-
-#define REG_A4XX_RBBM_PERFCTR_RAS_0_LO 0x000000fc
-
-#define REG_A4XX_RBBM_PERFCTR_RAS_0_HI 0x000000fd
-
-#define REG_A4XX_RBBM_PERFCTR_RAS_1_LO 0x000000fe
-
-#define REG_A4XX_RBBM_PERFCTR_RAS_1_HI 0x000000ff
-
-#define REG_A4XX_RBBM_PERFCTR_RAS_2_LO 0x00000100
-
-#define REG_A4XX_RBBM_PERFCTR_RAS_2_HI 0x00000101
-
-#define REG_A4XX_RBBM_PERFCTR_RAS_3_LO 0x00000102
-
-#define REG_A4XX_RBBM_PERFCTR_RAS_3_HI 0x00000103
-
-#define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO 0x00000104
-
-#define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI 0x00000105
-
-#define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO 0x00000106
-
-#define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI 0x00000107
-
-#define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO 0x00000108
-
-#define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI 0x00000109
-
-#define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO 0x0000010a
-
-#define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI 0x0000010b
-
-#define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO 0x0000010c
-
-#define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI 0x0000010d
-
-#define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO 0x0000010e
-
-#define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI 0x0000010f
-
-#define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO 0x00000110
-
-#define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI 0x00000111
-
-#define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO 0x00000112
-
-#define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI 0x00000113
-
-#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114
-
-#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
-
-#define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116
-
-#define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117
-
-#define REG_A4XX_RBBM_PERFCTR_TP_2_LO 0x00000118
-
-#define REG_A4XX_RBBM_PERFCTR_TP_2_HI 0x00000119
-
-#define REG_A4XX_RBBM_PERFCTR_TP_3_LO 0x0000011a
-
-#define REG_A4XX_RBBM_PERFCTR_TP_3_HI 0x0000011b
-
-#define REG_A4XX_RBBM_PERFCTR_TP_4_LO 0x0000011c
-
-#define REG_A4XX_RBBM_PERFCTR_TP_4_HI 0x0000011d
-
-#define REG_A4XX_RBBM_PERFCTR_TP_5_LO 0x0000011e
-
-#define REG_A4XX_RBBM_PERFCTR_TP_5_HI 0x0000011f
-
-#define REG_A4XX_RBBM_PERFCTR_TP_6_LO 0x00000120
-
-#define REG_A4XX_RBBM_PERFCTR_TP_6_HI 0x00000121
-
-#define REG_A4XX_RBBM_PERFCTR_TP_7_LO 0x00000122
-
-#define REG_A4XX_RBBM_PERFCTR_TP_7_HI 0x00000123
-
-#define REG_A4XX_RBBM_PERFCTR_SP_0_LO 0x00000124
-
-#define REG_A4XX_RBBM_PERFCTR_SP_0_HI 0x00000125
-
-#define REG_A4XX_RBBM_PERFCTR_SP_1_LO 0x00000126
-
-#define REG_A4XX_RBBM_PERFCTR_SP_1_HI 0x00000127
-
-#define REG_A4XX_RBBM_PERFCTR_SP_2_LO 0x00000128
-
-#define REG_A4XX_RBBM_PERFCTR_SP_2_HI 0x00000129
-
-#define REG_A4XX_RBBM_PERFCTR_SP_3_LO 0x0000012a
-
-#define REG_A4XX_RBBM_PERFCTR_SP_3_HI 0x0000012b
-
-#define REG_A4XX_RBBM_PERFCTR_SP_4_LO 0x0000012c
-
-#define REG_A4XX_RBBM_PERFCTR_SP_4_HI 0x0000012d
-
-#define REG_A4XX_RBBM_PERFCTR_SP_5_LO 0x0000012e
-
-#define REG_A4XX_RBBM_PERFCTR_SP_5_HI 0x0000012f
-
-#define REG_A4XX_RBBM_PERFCTR_SP_6_LO 0x00000130
-
-#define REG_A4XX_RBBM_PERFCTR_SP_6_HI 0x00000131
-
-#define REG_A4XX_RBBM_PERFCTR_SP_7_LO 0x00000132
-
-#define REG_A4XX_RBBM_PERFCTR_SP_7_HI 0x00000133
-
-#define REG_A4XX_RBBM_PERFCTR_SP_8_LO 0x00000134
-
-#define REG_A4XX_RBBM_PERFCTR_SP_8_HI 0x00000135
-
-#define REG_A4XX_RBBM_PERFCTR_SP_9_LO 0x00000136
-
-#define REG_A4XX_RBBM_PERFCTR_SP_9_HI 0x00000137
-
-#define REG_A4XX_RBBM_PERFCTR_SP_10_LO 0x00000138
-
-#define REG_A4XX_RBBM_PERFCTR_SP_10_HI 0x00000139
-
-#define REG_A4XX_RBBM_PERFCTR_SP_11_LO 0x0000013a
-
-#define REG_A4XX_RBBM_PERFCTR_SP_11_HI 0x0000013b
-
-#define REG_A4XX_RBBM_PERFCTR_RB_0_LO 0x0000013c
-
-#define REG_A4XX_RBBM_PERFCTR_RB_0_HI 0x0000013d
-
-#define REG_A4XX_RBBM_PERFCTR_RB_1_LO 0x0000013e
-
-#define REG_A4XX_RBBM_PERFCTR_RB_1_HI 0x0000013f
-
-#define REG_A4XX_RBBM_PERFCTR_RB_2_LO 0x00000140
-
-#define REG_A4XX_RBBM_PERFCTR_RB_2_HI 0x00000141
-
-#define REG_A4XX_RBBM_PERFCTR_RB_3_LO 0x00000142
-
-#define REG_A4XX_RBBM_PERFCTR_RB_3_HI 0x00000143
-
-#define REG_A4XX_RBBM_PERFCTR_RB_4_LO 0x00000144
-
-#define REG_A4XX_RBBM_PERFCTR_RB_4_HI 0x00000145
-
-#define REG_A4XX_RBBM_PERFCTR_RB_5_LO 0x00000146
-
-#define REG_A4XX_RBBM_PERFCTR_RB_5_HI 0x00000147
-
-#define REG_A4XX_RBBM_PERFCTR_RB_6_LO 0x00000148
-
-#define REG_A4XX_RBBM_PERFCTR_RB_6_HI 0x00000149
-
-#define REG_A4XX_RBBM_PERFCTR_RB_7_LO 0x0000014a
-
-#define REG_A4XX_RBBM_PERFCTR_RB_7_HI 0x0000014b
-
-#define REG_A4XX_RBBM_PERFCTR_VSC_0_LO 0x0000014c
-
-#define REG_A4XX_RBBM_PERFCTR_VSC_0_HI 0x0000014d
-
-#define REG_A4XX_RBBM_PERFCTR_VSC_1_LO 0x0000014e
-
-#define REG_A4XX_RBBM_PERFCTR_VSC_1_HI 0x0000014f
-
-#define REG_A4XX_RBBM_PERFCTR_PWR_0_LO 0x00000166
-
-#define REG_A4XX_RBBM_PERFCTR_PWR_0_HI 0x00000167
-
-#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
-
-#define REG_A4XX_RBBM_PERFCTR_PWR_1_HI 0x00000169
-
-#define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO 0x0000016e
-
-#define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f
-
-#define REG_A4XX_RBBM_CLOCK_CTL_SP(i0) (0x00000068 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
-
-#define REG_A4XX_RBBM_CLOCK_CTL2_SP(i0) (0x0000006c + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
-
-#define REG_A4XX_RBBM_CLOCK_HYST_SP(i0) (0x00000070 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
-
-#define REG_A4XX_RBBM_CLOCK_DELAY_SP(i0) (0x00000074 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
-
-#define REG_A4XX_RBBM_CLOCK_CTL_RB(i0) (0x00000078 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
-
-#define REG_A4XX_RBBM_CLOCK_CTL2_RB(i0) (0x0000007c + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
-
-#define REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(i0) (0x00000082 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
-
-#define REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(i0) (0x00000086 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
-
-#define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080
-
-#define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081
-
-#define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a
-
-#define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b
-
-#define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c
-
-#define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d
-
-#define REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(i0) (0x0000008e + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
-
-#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x00000099
-
-#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a
-
-#define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
-
-#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
-
-#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172
-
-#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173
-
-#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174
-
-#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175
-
-#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000176
-
-#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000177
-
-#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000178
-
-#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x00000179
-
-#define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a
-
-#define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d
-
-#define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182
-
-#define REG_A4XX_RBBM_AHB_STATUS 0x00000189
-
-#define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c
-
-#define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d
-
-#define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f
-
-#define REG_A4XX_RBBM_STATUS 0x00000191
-#define A4XX_RBBM_STATUS_HI_BUSY 0x00000001
-#define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
-#define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
-#define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
-#define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000
-#define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000
-#define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000
-#define A4XX_RBBM_STATUS_RB_BUSY 0x00040000
-#define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
-#define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
-#define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000
-#define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000
-#define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000
-#define A4XX_RBBM_STATUS_SP_BUSY 0x01000000
-#define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000
-#define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000
-#define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000
-#define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000
-#define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
-#define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
-#define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000
-
-#define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f
-
-#define REG_A4XX_RBBM_POWER_STATUS 0x000001b0
-#define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON 0x00100000
-
-#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x000001b8
-
-#define REG_A4XX_CP_SCRATCH_UMASK 0x00000228
-
-#define REG_A4XX_CP_SCRATCH_ADDR 0x00000229
-
-#define REG_A4XX_CP_RB_BASE 0x00000200
-
-#define REG_A4XX_CP_RB_CNTL 0x00000201
-
-#define REG_A4XX_CP_RB_WPTR 0x00000205
-
-#define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203
-
-#define REG_A4XX_CP_RB_RPTR 0x00000204
-
-#define REG_A4XX_CP_IB1_BASE 0x00000206
-
-#define REG_A4XX_CP_IB1_BUFSZ 0x00000207
-
-#define REG_A4XX_CP_IB2_BASE 0x00000208
-
-#define REG_A4XX_CP_IB2_BUFSZ 0x00000209
-
-#define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c
-
-#define REG_A4XX_CP_ME_NRT_DATA 0x0000020d
-
-#define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217
-
-#define REG_A4XX_CP_QUEUE_THRESH2 0x00000219
-
-#define REG_A4XX_CP_MERCIU_SIZE 0x0000021b
-
-#define REG_A4XX_CP_ROQ_ADDR 0x0000021c
-
-#define REG_A4XX_CP_ROQ_DATA 0x0000021d
-
-#define REG_A4XX_CP_MEQ_ADDR 0x0000021e
-
-#define REG_A4XX_CP_MEQ_DATA 0x0000021f
-
-#define REG_A4XX_CP_MERCIU_ADDR 0x00000220
-
-#define REG_A4XX_CP_MERCIU_DATA 0x00000221
-
-#define REG_A4XX_CP_MERCIU_DATA2 0x00000222
-
-#define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223
-
-#define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224
-
-#define REG_A4XX_CP_ME_RAM_WADDR 0x00000225
-
-#define REG_A4XX_CP_ME_RAM_RADDR 0x00000226
-
-#define REG_A4XX_CP_ME_RAM_DATA 0x00000227
-
-#define REG_A4XX_CP_PREEMPT 0x0000022a
-
-#define REG_A4XX_CP_CNTL 0x0000022c
-
-#define REG_A4XX_CP_ME_CNTL 0x0000022d
-
-#define REG_A4XX_CP_DEBUG 0x0000022e
-
-#define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231
-
-#define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232
-
-#define REG_A4XX_CP_PROTECT(i0) (0x00000240 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
-#define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
-#define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
-static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
-{
- return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK;
-}
-#define A4XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
-#define A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24
-static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
-{
- return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK;
-}
-#define A4XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
-#define A4XX_CP_PROTECT_REG_TRAP_READ 0x40000000
-
-#define REG_A4XX_CP_PROTECT_CTRL 0x00000250
-
-#define REG_A4XX_CP_ST_BASE 0x000004c0
-
-#define REG_A4XX_CP_STQ_AVAIL 0x000004ce
-
-#define REG_A4XX_CP_MERCIU_STAT 0x000004d0
-
-#define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2
-
-#define REG_A4XX_CP_HW_FAULT 0x000004d8
-
-#define REG_A4XX_CP_PROTECT_STATUS 0x000004da
-
-#define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd
-
-#define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500
-
-#define REG_A4XX_CP_PERFCTR_CP_SEL_1 0x00000501
-
-#define REG_A4XX_CP_PERFCTR_CP_SEL_2 0x00000502
-
-#define REG_A4XX_CP_PERFCTR_CP_SEL_3 0x00000503
-
-#define REG_A4XX_CP_PERFCTR_CP_SEL_4 0x00000504
-
-#define REG_A4XX_CP_PERFCTR_CP_SEL_5 0x00000505
-
-#define REG_A4XX_CP_PERFCTR_CP_SEL_6 0x00000506
-
-#define REG_A4XX_CP_PERFCTR_CP_SEL_7 0x00000507
-
-#define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
-
-#define REG_A4XX_CP_SCRATCH(i0) (0x00000578 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
-
-#define REG_A4XX_SP_VS_STATUS 0x00000ec0
-
-#define REG_A4XX_SP_MODE_CONTROL 0x00000ec3
-
-#define REG_A4XX_SP_PERFCTR_SP_SEL_0 0x00000ec4
-
-#define REG_A4XX_SP_PERFCTR_SP_SEL_1 0x00000ec5
-
-#define REG_A4XX_SP_PERFCTR_SP_SEL_2 0x00000ec6
-
-#define REG_A4XX_SP_PERFCTR_SP_SEL_3 0x00000ec7
-
-#define REG_A4XX_SP_PERFCTR_SP_SEL_4 0x00000ec8
-
-#define REG_A4XX_SP_PERFCTR_SP_SEL_5 0x00000ec9
-
-#define REG_A4XX_SP_PERFCTR_SP_SEL_6 0x00000eca
-
-#define REG_A4XX_SP_PERFCTR_SP_SEL_7 0x00000ecb
-
-#define REG_A4XX_SP_PERFCTR_SP_SEL_8 0x00000ecc
-
-#define REG_A4XX_SP_PERFCTR_SP_SEL_9 0x00000ecd
-
-#define REG_A4XX_SP_PERFCTR_SP_SEL_10 0x00000ece
-
-#define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf
-
-#define REG_A4XX_SP_SP_CTRL_REG 0x000022c0
-#define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000
-
-#define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1
-#define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080
-#define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100
-#define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400
-
-#define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4
-#define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
-#define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
-static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
-{
- return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
-}
-#define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002
-#define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
-#define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
-#define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
-static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
-#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
-static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
-#define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
-static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
-}
-#define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
-#define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
-static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
-}
-#define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
-#define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
-
-#define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5
-#define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
-#define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
-static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
-}
-#define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000
-#define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
-static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
-}
-
-#define REG_A4XX_SP_VS_PARAM_REG 0x000022c6
-#define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
-#define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
-static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK;
-}
-#define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
-#define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
-static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
-}
-#define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
-#define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
-static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
-}
-
-#define REG_A4XX_SP_VS_OUT(i0) (0x000022c7 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
-#define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
-#define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
-static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK;
-}
-#define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
-#define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
-static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
-}
-#define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
-#define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
-static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK;
-}
-#define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
-#define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
-static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
-}
-
-#define REG_A4XX_SP_VS_VPC_DST(i0) (0x000022d8 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
-#define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
-#define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
-static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
-}
-#define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
-#define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
-static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
-}
-#define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
-#define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
-static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
-}
-#define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
-#define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
-static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
-}
-
-#define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0
-#define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
-#define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
-static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
-}
-#define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
-#define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
-static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A4XX_SP_VS_OBJ_START 0x000022e1
-
-#define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2
-
-#define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3
-
-#define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5
-
-#define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8
-#define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
-#define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
-static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
-{
- return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
-}
-#define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002
-#define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
-#define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
-#define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
-static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
-#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
-static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
-#define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
-static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
-{
- return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
-}
-#define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
-#define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
-static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
-}
-#define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
-#define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
-
-#define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9
-#define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
-#define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
-static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
-{
- return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
-}
-#define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000
-#define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000
-#define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000
-
-#define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea
-#define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
-#define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
-static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
-}
-#define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
-#define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
-static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A4XX_SP_FS_OBJ_START 0x000022eb
-
-#define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec
-
-#define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed
-
-#define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef
-
-#define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0
-#define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f
-#define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
-static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
-{
- return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
-}
-#define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
-#define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
-#define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
-static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
-{
- return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
-}
-#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000
-#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24
-static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
-{
- return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
-}
-
-#define REG_A4XX_SP_FS_MRT(i0) (0x000022f1 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
-#define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
-#define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0
-static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
-{
- return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
-}
-#define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
-#define A4XX_SP_FS_MRT_REG_COLOR_SINT 0x00000400
-#define A4XX_SP_FS_MRT_REG_COLOR_UINT 0x00000800
-#define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000
-#define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12
-static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
-{
- return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
-}
-#define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000
-
-#define REG_A4XX_SP_CS_CTRL_REG0 0x00002300
-#define A4XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001
-#define A4XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0
-static inline uint32_t A4XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
-{
- return ((val) << A4XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_CS_CTRL_REG0_THREADMODE__MASK;
-}
-#define A4XX_SP_CS_CTRL_REG0_VARYING 0x00000002
-#define A4XX_SP_CS_CTRL_REG0_CACHEINVALID 0x00000004
-#define A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
-#define A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
-static inline uint32_t A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
-#define A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
-static inline uint32_t A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
-#define A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
-static inline uint32_t A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
-{
- return ((val) << A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__MASK;
-}
-#define A4XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
-#define A4XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
-static inline uint32_t A4XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A4XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
-}
-#define A4XX_SP_CS_CTRL_REG0_SUPERTHREADMODE 0x00200000
-#define A4XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00400000
-
-#define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301
-
-#define REG_A4XX_SP_CS_OBJ_START 0x00002302
-
-#define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303
-
-#define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304
-
-#define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305
-
-#define REG_A4XX_SP_CS_LENGTH_REG 0x00002306
-
-#define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d
-#define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
-#define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
-static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
-}
-#define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
-#define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
-static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A4XX_SP_HS_OBJ_START 0x0000230e
-
-#define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f
-
-#define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310
-
-#define REG_A4XX_SP_HS_LENGTH_REG 0x00002312
-
-#define REG_A4XX_SP_DS_PARAM_REG 0x0000231a
-#define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff
-#define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0
-static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)
-{
- return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK;
-}
-#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
-#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
-static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
-{
- return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;
-}
-
-#define REG_A4XX_SP_DS_OUT(i0) (0x0000231b + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
-#define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff
-#define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
-static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
-{
- return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK;
-}
-#define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00
-#define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9
-static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
-{
- return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
-}
-#define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000
-#define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
-static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
-{
- return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK;
-}
-#define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000
-#define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25
-static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
-{
- return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
-}
-
-#define REG_A4XX_SP_DS_VPC_DST(i0) (0x0000232c + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
-#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
-#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
-static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
-{
- return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
-}
-#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
-#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
-static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
-{
- return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
-}
-#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
-#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
-static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
-{
- return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
-}
-#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
-#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
-static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
-{
- return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
-}
-
-#define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334
-#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
-#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
-static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
-}
-#define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
-#define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
-static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A4XX_SP_DS_OBJ_START 0x00002335
-
-#define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336
-
-#define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337
-
-#define REG_A4XX_SP_DS_LENGTH_REG 0x00002339
-
-#define REG_A4XX_SP_GS_PARAM_REG 0x00002341
-#define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff
-#define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0
-static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)
-{
- return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK;
-}
-#define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00
-#define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8
-static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)
-{
- return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK;
-}
-#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
-#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
-static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
-{
- return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;
-}
-
-#define REG_A4XX_SP_GS_OUT(i0) (0x00002342 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
-#define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff
-#define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
-static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
-{
- return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK;
-}
-#define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00
-#define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9
-static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
-{
- return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
-}
-#define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000
-#define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
-static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
-{
- return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK;
-}
-#define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000
-#define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25
-static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
-{
- return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
-}
-
-#define REG_A4XX_SP_GS_VPC_DST(i0) (0x00002353 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
-#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
-#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
-static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
-{
- return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
-}
-#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
-#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
-static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
-{
- return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
-}
-#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
-#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
-static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
-{
- return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
-}
-#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
-#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
-static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
-{
- return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
-}
-
-#define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b
-#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
-#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
-static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
-}
-#define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
-#define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
-static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A4XX_SP_GS_OBJ_START 0x0000235c
-
-#define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d
-
-#define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e
-
-#define REG_A4XX_SP_GS_LENGTH_REG 0x00002360
-
-#define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60
-
-#define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61
-
-#define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64
-
-#define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 0x00000e65
-
-#define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 0x00000e66
-
-#define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 0x00000e67
-
-#define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68
-
-#define REG_A4XX_VPC_ATTR 0x00002140
-#define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
-#define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0
-static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
-{
- return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;
-}
-#define A4XX_VPC_ATTR_PSIZE 0x00000200
-#define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000
-#define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12
-static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)
-{
- return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK;
-}
-#define A4XX_VPC_ATTR_ENABLE 0x02000000
-
-#define REG_A4XX_VPC_PACK 0x00002141
-#define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff
-#define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0
-static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)
-{
- return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK;
-}
-#define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
-#define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
-static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
-{
- return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
-}
-#define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
-#define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
-static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
-{
- return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
-}
-
-#define REG_A4XX_VPC_VARYING_INTERP(i0) (0x00002142 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
-
-#define REG_A4XX_VPC_VARYING_PS_REPL(i0) (0x0000214a + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
-
-#define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e
-
-#define REG_A4XX_VSC_BIN_SIZE 0x00000c00
-#define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
-#define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
-static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
-}
-#define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
-#define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
-static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
-}
-
-#define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01
-
-#define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02
-
-#define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03
-
-#define REG_A4XX_VSC_PIPE_CONFIG(i0) (0x00000c08 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
-#define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
-#define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
-static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
-{
- return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK;
-}
-#define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
-#define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
-static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
-{
- return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK;
-}
-#define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
-#define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
-static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
-{
- return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK;
-}
-#define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
-#define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
-static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
-{
- return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK;
-}
-
-#define REG_A4XX_VSC_PIPE_DATA_ADDRESS(i0) (0x00000c10 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
-
-#define REG_A4XX_VSC_PIPE_DATA_LENGTH(i0) (0x00000c18 + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
-
-#define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41
-
-#define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50
-
-#define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51
-
-#define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40
-
-#define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 0x00000e43
-
-#define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 0x00000e44
-
-#define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 0x00000e45
-
-#define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 0x00000e46
-
-#define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 0x00000e47
-
-#define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 0x00000e48
-
-#define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 0x00000e49
-
-#define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a
-
-#define REG_A4XX_VGT_CL_INITIATOR 0x000021d0
-
-#define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9
-
-#define REG_A4XX_VFD_CONTROL_0 0x00002200
-#define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff
-#define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
-static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
-{
- return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
-}
-#define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00
-#define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9
-static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)
-{
- return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK;
-}
-#define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000
-#define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20
-static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
-{
- return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
-}
-#define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000
-#define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26
-static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
-{
- return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
-}
-
-#define REG_A4XX_VFD_CONTROL_1 0x00002201
-#define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
-#define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
-static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
-{
- return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
-}
-#define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
-#define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
-static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
-{
- return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK;
-}
-#define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
-#define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
-static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
-{
- return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK;
-}
-
-#define REG_A4XX_VFD_CONTROL_2 0x00002202
-
-#define REG_A4XX_VFD_CONTROL_3 0x00002203
-#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00
-#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8
-static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
-{
- return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
-}
-#define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
-#define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
-static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
-{
- return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK;
-}
-#define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
-#define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
-static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
-{
- return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK;
-}
-
-#define REG_A4XX_VFD_CONTROL_4 0x00002204
-
-#define REG_A4XX_VFD_INDEX_OFFSET 0x00002208
-
-#define REG_A4XX_VFD_FETCH(i0) (0x0000220a + 0x4*(i0))
-
-static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
-#define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
-#define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
-static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
-{
- return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
-}
-#define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80
-#define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
-static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
-{
- return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
-}
-#define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000
-#define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000
-
-static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
-
-static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
-#define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xffffffff
-#define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 0
-static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
-{
- return ((val) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
-}
-
-static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
-#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff
-#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0
-static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)
-{
- return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK;
-}
-
-#define REG_A4XX_VFD_DECODE(i0) (0x0000228a + 0x1*(i0))
-
-static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
-#define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
-#define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
-static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
-{
- return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
-}
-#define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
-#define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
-#define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
-static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)
-{
- return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK;
-}
-#define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
-#define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12
-static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
-{
- return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
-}
-#define A4XX_VFD_DECODE_INSTR_INT 0x00100000
-#define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
-#define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
-static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK;
-}
-#define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
-#define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
-static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
-{
- return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
-}
-#define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
-#define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
-
-#define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00
-
-#define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03
-
-#define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 0x00000f04
-
-#define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 0x00000f05
-
-#define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 0x00000f06
-
-#define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 0x00000f07
-
-#define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 0x00000f08
-
-#define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 0x00000f09
-
-#define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 0x00000f0a
-
-#define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b
-
-#define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
-
-#define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381
-#define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff
-#define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0
-static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
-{
- return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK;
-}
-#define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00
-#define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8
-static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
-{
- return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK;
-}
-#define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000
-#define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16
-static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
-{
- return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK;
-}
-#define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000
-#define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24
-static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
-{
- return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK;
-}
-
-#define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384
-
-#define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387
-
-#define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a
-
-#define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d
-
-#define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0
-#define A4XX_TPL1_TP_FS_TEX_COUNT_FS__MASK 0x000000ff
-#define A4XX_TPL1_TP_FS_TEX_COUNT_FS__SHIFT 0
-static inline uint32_t A4XX_TPL1_TP_FS_TEX_COUNT_FS(uint32_t val)
-{
- return ((val) << A4XX_TPL1_TP_FS_TEX_COUNT_FS__SHIFT) & A4XX_TPL1_TP_FS_TEX_COUNT_FS__MASK;
-}
-#define A4XX_TPL1_TP_FS_TEX_COUNT_CS__MASK 0x0000ff00
-#define A4XX_TPL1_TP_FS_TEX_COUNT_CS__SHIFT 8
-static inline uint32_t A4XX_TPL1_TP_FS_TEX_COUNT_CS(uint32_t val)
-{
- return ((val) << A4XX_TPL1_TP_FS_TEX_COUNT_CS__SHIFT) & A4XX_TPL1_TP_FS_TEX_COUNT_CS__MASK;
-}
-
-#define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1
-
-#define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4
-
-#define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5
-
-#define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6
-
-#define REG_A4XX_GRAS_TSE_STATUS 0x00000c80
-
-#define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81
-
-#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88
-
-#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c89
-
-#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c8a
-
-#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b
-
-#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c8c
-
-#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c8d
-
-#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c8e
-
-#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c8f
-
-#define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
-#define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000
-#define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE 0x00010000
-#define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000
-#define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
-
-#define REG_A4XX_GRAS_CNTL 0x00002003
-#define A4XX_GRAS_CNTL_IJ_PERSP 0x00000001
-#define A4XX_GRAS_CNTL_IJ_LINEAR 0x00000002
-
-#define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004
-#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
-#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
-static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
-{
- return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
-}
-#define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
-#define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
-static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
-{
- return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
-}
-
-#define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008
-#define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
-#define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
-static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)
-{
- return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
-}
-
-#define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009
-#define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
-#define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
-static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val)
-{
- return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK;
-}
-
-#define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a
-#define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
-#define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
-static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)
-{
- return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
-}
-
-#define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b
-#define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
-#define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
-static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val)
-{
- return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK;
-}
-
-#define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c
-#define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
-#define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
-static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
-{
- return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
-}
-
-#define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d
-#define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
-#define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
-static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)
-{
- return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
-}
-
-#define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070
-#define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
-#define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
-static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)
-{
- return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
-}
-#define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
-#define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
-static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)
-{
- return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
-}
-
-#define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071
-#define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
-#define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0
-static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
-{
- return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
-}
-
-#define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073
-#define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004
-#define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS 0x00000008
-
-#define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074
-#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
-#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
-static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
-{
- return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
-}
-
-#define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075
-#define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
-#define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
-static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
-{
- return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
-}
-
-#define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076
-#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff
-#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0
-static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
-{
- return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
-}
-
-#define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077
-#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003
-#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0
-static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
-{
- return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
-}
-
-#define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078
-#define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
-#define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
-#define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
-#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
-#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
-static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
-{
- return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
-}
-#define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
-#define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE 0x00002000
-#define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000
-
-#define REG_A4XX_GRAS_SC_CONTROL 0x0000207b
-#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c
-#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2
-static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
-{
- return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
-}
-#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380
-#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7
-static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
-{
- return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
-}
-#define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800
-#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
-#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
-static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
-{
- return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
-}
-
-#define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c
-#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
-#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
-#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
-static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
-{
- return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
-}
-#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
-#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
-static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
-{
- return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
-}
-
-#define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d
-#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
-#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
-#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
-static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
-{
- return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
-}
-#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
-#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
-static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
-{
- return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
-}
-
-#define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c
-#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
-#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
-#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
-static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
-{
- return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
-}
-#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
-#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
-static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
-{
- return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
-}
-
-#define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d
-#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
-#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
-#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
-static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
-{
- return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
-}
-#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
-#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
-static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
-{
- return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
-}
-
-#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e
-#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000
-#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff
-#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0
-static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)
-{
- return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK;
-}
-#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000
-#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16
-static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)
-{
- return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK;
-}
-
-#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f
-#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000
-#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff
-#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0
-static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)
-{
- return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK;
-}
-#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000
-#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16
-static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
-{
- return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK;
-}
-
-#define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80
-
-#define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83
-
-#define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84
-
-#define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88
-
-#define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a
-
-#define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b
-
-#define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c
-
-#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e8e
-
-#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e8f
-
-#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e90
-
-#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e91
-
-#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e92
-
-#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e93
-
-#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e94
-
-#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95
-
-#define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00
-
-#define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04
-
-#define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05
-
-#define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e
-
-#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e06
-
-#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e07
-
-#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e08
-
-#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e09
-
-#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e0a
-
-#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e0b
-
-#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e0c
-
-#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e0d
-
-#define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0
-#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
-#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
-static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
-}
-#define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
-#define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
-#define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
-#define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
-#define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
-#define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
-static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
-}
-#define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
-#define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
-#define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
-#define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
-
-#define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1
-#define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
-#define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
-static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
-}
-#define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
-#define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
-#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000
-#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16
-static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
-}
-#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000
-#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24
-static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK;
-}
-
-#define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2
-#define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
-#define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
-static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
-}
-#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc
-#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2
-static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
-}
-#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00
-#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10
-static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
-}
-#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000
-#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18
-static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
-}
-
-#define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3
-#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
-#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
-static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
-}
-#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
-#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
-static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
-}
-#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
-#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
-static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
-}
-#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
-#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
-static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
-}
-
-#define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4
-#define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
-#define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
-static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
-}
-#define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
-#define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
-static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
-}
-
-#define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5
-#define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
-#define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
-static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
-}
-#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
-#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
-static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
-}
-#define A4XX_HLSQ_VS_CONTROL_REG_SSBO_ENABLE 0x00008000
-#define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000
-#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
-#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
-static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
-}
-#define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
-#define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
-static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
-}
-
-#define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6
-#define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
-#define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
-static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
-}
-#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
-#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
-static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
-}
-#define A4XX_HLSQ_FS_CONTROL_REG_SSBO_ENABLE 0x00008000
-#define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000
-#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
-#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
-static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
-}
-#define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
-#define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
-static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
-}
-
-#define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7
-#define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
-#define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0
-static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
-}
-#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
-#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
-static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
-}
-#define A4XX_HLSQ_HS_CONTROL_REG_SSBO_ENABLE 0x00008000
-#define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000
-#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
-#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
-static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
-}
-#define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
-#define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24
-static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK;
-}
-
-#define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8
-#define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
-#define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0
-static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
-}
-#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
-#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
-static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
-}
-#define A4XX_HLSQ_DS_CONTROL_REG_SSBO_ENABLE 0x00008000
-#define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000
-#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
-#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
-static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
-}
-#define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
-#define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24
-static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK;
-}
-
-#define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9
-#define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
-#define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0
-static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
-}
-#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
-#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
-static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
-}
-#define A4XX_HLSQ_GS_CONTROL_REG_SSBO_ENABLE 0x00008000
-#define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000
-#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
-#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
-static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
-}
-#define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
-#define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24
-static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
-}
-
-#define REG_A4XX_HLSQ_CS_CONTROL_REG 0x000023ca
-#define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
-#define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT 0
-static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK;
-}
-#define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
-#define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
-static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
-}
-#define A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE 0x00008000
-#define A4XX_HLSQ_CS_CONTROL_REG_ENABLED 0x00010000
-#define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
-#define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
-static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK;
-}
-#define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
-#define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT 24
-static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK;
-}
-
-#define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd
-#define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK 0x00000003
-#define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT 0
-static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK;
-}
-#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
-#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT 2
-static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK;
-}
-#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
-#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT 12
-static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK;
-}
-#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
-#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT 22
-static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK;
-}
-
-#define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce
-#define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK 0xffffffff
-#define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT 0
-static inline uint32_t A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT) & A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK;
-}
-
-#define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf
-
-#define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0
-#define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK 0xffffffff
-#define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT 0
-static inline uint32_t A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT) & A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK;
-}
-
-#define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1
-
-#define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2
-#define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK 0xffffffff
-#define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT 0
-static inline uint32_t A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT) & A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK;
-}
-
-#define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3
-
-#define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4
-#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK 0x00000fff
-#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT 0
-static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK;
-}
-#define A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__MASK 0x00fff000
-#define A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__SHIFT 12
-static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__MASK;
-}
-#define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK 0xff000000
-#define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT 24
-static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK;
-}
-
-#define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5
-#define A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__MASK 0x00000fff
-#define A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__SHIFT 0
-static inline uint32_t A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__MASK;
-}
-#define A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__MASK 0x00fff000
-#define A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__SHIFT 12
-static inline uint32_t A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__MASK;
-}
-
-#define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6
-#define A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__MASK 0x00000fff
-#define A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__SHIFT 0
-static inline uint32_t A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__SHIFT) & A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__MASK;
-}
-#define A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__MASK 0x00fff000
-#define A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__SHIFT 12
-static inline uint32_t A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__SHIFT) & A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__MASK;
-}
-
-#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7
-
-#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8
-
-#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9
-
-#define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da
-#define A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__MASK 0x00000fff
-#define A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__SHIFT 0
-static inline uint32_t A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID(uint32_t val)
-{
- return ((val) << A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__SHIFT) & A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__MASK;
-}
-
-#define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db
-
-#define REG_A4XX_PC_BINNING_COMMAND 0x00000d00
-#define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001
-
-#define REG_A4XX_PC_TESSFACTOR_ADDR 0x00000d08
-
-#define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c
-
-#define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
-
-#define REG_A4XX_PC_PERFCTR_PC_SEL_1 0x00000d11
-
-#define REG_A4XX_PC_PERFCTR_PC_SEL_2 0x00000d12
-
-#define REG_A4XX_PC_PERFCTR_PC_SEL_3 0x00000d13
-
-#define REG_A4XX_PC_PERFCTR_PC_SEL_4 0x00000d14
-
-#define REG_A4XX_PC_PERFCTR_PC_SEL_5 0x00000d15
-
-#define REG_A4XX_PC_PERFCTR_PC_SEL_6 0x00000d16
-
-#define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17
-
-#define REG_A4XX_PC_BIN_BASE 0x000021c0
-
-#define REG_A4XX_PC_VSTREAM_CONTROL 0x000021c2
-#define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000
-#define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16
-static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)
-{
- return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK;
-}
-#define A4XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000
-#define A4XX_PC_VSTREAM_CONTROL_N__SHIFT 22
-static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val)
-{
- return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK;
-}
-
-#define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4
-#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f
-#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0
-static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
-{
- return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
-}
-#define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
-#define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
-#define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
-
-#define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5
-#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007
-#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0
-static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
-{
- return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK;
-}
-#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038
-#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT 3
-static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
-{
- return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK;
-}
-#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040
-
-#define REG_A4XX_PC_RESTART_INDEX 0x000021c6
-
-#define REG_A4XX_PC_GS_PARAM 0x000021e5
-#define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
-#define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
-static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
-{
- return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
-}
-#define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
-#define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
-static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
-{
- return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK;
-}
-#define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
-#define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
-static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
-{
- return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
-}
-#define A4XX_PC_GS_PARAM_LAYER 0x80000000
-
-#define REG_A4XX_PC_HS_PARAM 0x000021e7
-#define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
-#define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
-static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
-{
- return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK;
-}
-#define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000
-#define A4XX_PC_HS_PARAM_SPACING__SHIFT 21
-static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
-{
- return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
-}
-#define A4XX_PC_HS_PARAM_CW 0x00800000
-#define A4XX_PC_HS_PARAM_CONNECTED 0x01000000
-
-#define REG_A4XX_VBIF_VERSION 0x00003000
-
-#define REG_A4XX_VBIF_CLKON 0x00003001
-#define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001
-
-#define REG_A4XX_VBIF_ABIT_SORT 0x0000301c
-
-#define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d
-
-#define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
-
-#define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
-
-#define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
-
-#define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030
-
-#define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031
-
-#define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
-
-#define REG_A4XX_VBIF_PERF_CNT_EN0 0x000030c0
-
-#define REG_A4XX_VBIF_PERF_CNT_EN1 0x000030c1
-
-#define REG_A4XX_VBIF_PERF_CNT_EN2 0x000030c2
-
-#define REG_A4XX_VBIF_PERF_CNT_EN3 0x000030c3
-
-#define REG_A4XX_VBIF_PERF_CNT_SEL0 0x000030d0
-
-#define REG_A4XX_VBIF_PERF_CNT_SEL1 0x000030d1
-
-#define REG_A4XX_VBIF_PERF_CNT_SEL2 0x000030d2
-
-#define REG_A4XX_VBIF_PERF_CNT_SEL3 0x000030d3
-
-#define REG_A4XX_VBIF_PERF_CNT_LOW0 0x000030d8
-
-#define REG_A4XX_VBIF_PERF_CNT_LOW1 0x000030d9
-
-#define REG_A4XX_VBIF_PERF_CNT_LOW2 0x000030da
-
-#define REG_A4XX_VBIF_PERF_CNT_LOW3 0x000030db
-
-#define REG_A4XX_VBIF_PERF_CNT_HIGH0 0x000030e0
-
-#define REG_A4XX_VBIF_PERF_CNT_HIGH1 0x000030e1
-
-#define REG_A4XX_VBIF_PERF_CNT_HIGH2 0x000030e2
-
-#define REG_A4XX_VBIF_PERF_CNT_HIGH3 0x000030e3
-
-#define REG_A4XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
-
-#define REG_A4XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
-
-#define REG_A4XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
-
-#define REG_A4XX_UNKNOWN_0CC5 0x00000cc5
-
-#define REG_A4XX_UNKNOWN_0CC6 0x00000cc6
-
-#define REG_A4XX_UNKNOWN_0D01 0x00000d01
-
-#define REG_A4XX_UNKNOWN_0E42 0x00000e42
-
-#define REG_A4XX_UNKNOWN_0EC2 0x00000ec2
-
-#define REG_A4XX_UNKNOWN_2001 0x00002001
-
-#define REG_A4XX_UNKNOWN_209B 0x0000209b
-
-#define REG_A4XX_UNKNOWN_20EF 0x000020ef
-
-#define REG_A4XX_UNKNOWN_2152 0x00002152
-
-#define REG_A4XX_UNKNOWN_2153 0x00002153
-
-#define REG_A4XX_UNKNOWN_2154 0x00002154
-
-#define REG_A4XX_UNKNOWN_2155 0x00002155
-
-#define REG_A4XX_UNKNOWN_2156 0x00002156
-
-#define REG_A4XX_UNKNOWN_2157 0x00002157
-
-#define REG_A4XX_UNKNOWN_21C3 0x000021c3
-
-#define REG_A4XX_UNKNOWN_21E6 0x000021e6
-
-#define REG_A4XX_UNKNOWN_2209 0x00002209
-
-#define REG_A4XX_UNKNOWN_22D7 0x000022d7
-
-#define REG_A4XX_UNKNOWN_2352 0x00002352
-
-#define REG_A4XX_TEX_SAMP_0 0x00000000
-#define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
-#define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
-#define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1
-static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
-{
- return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK;
-}
-#define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
-#define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3
-static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)
-{
- return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK;
-}
-#define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
-#define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5
-static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)
-{
- return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK;
-}
-#define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
-#define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8
-static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)
-{
- return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK;
-}
-#define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
-#define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11
-static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
-{
- return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
-}
-#define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
-#define A4XX_TEX_SAMP_0_ANISO__SHIFT 14
-static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
-{
- return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
-}
-#define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
-#define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
-static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val)
-{
- return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK;
-}
-
-#define REG_A4XX_TEX_SAMP_1 0x00000001
-#define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
-#define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
-static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
-{
- return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
-}
-#define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
-#define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
-#define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
-#define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
-#define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
-static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
-{
- return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
-}
-#define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
-#define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
-static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
-{
- return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
-}
-
-#define REG_A4XX_TEX_CONST_0 0x00000000
-#define A4XX_TEX_CONST_0_TILED 0x00000001
-#define A4XX_TEX_CONST_0_SRGB 0x00000004
-#define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
-#define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4
-static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
-{
- return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK;
-}
-#define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
-#define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
-static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
-{
- return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK;
-}
-#define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
-#define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
-static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
-{
- return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK;
-}
-#define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
-#define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13
-static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
-{
- return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK;
-}
-#define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
-#define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16
-static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)
-{
- return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK;
-}
-#define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000
-#define A4XX_TEX_CONST_0_FMT__SHIFT 22
-static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
-{
- return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
-}
-#define A4XX_TEX_CONST_0_TYPE__MASK 0xe0000000
-#define A4XX_TEX_CONST_0_TYPE__SHIFT 29
-static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
-{
- return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK;
-}
-
-#define REG_A4XX_TEX_CONST_1 0x00000001
-#define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff
-#define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0
-static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
-{
- return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
-}
-#define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000
-#define A4XX_TEX_CONST_1_WIDTH__SHIFT 15
-static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
-{
- return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
-}
-
-#define REG_A4XX_TEX_CONST_2 0x00000002
-#define A4XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
-#define A4XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
-static inline uint32_t A4XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
-{
- return ((val) << A4XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A4XX_TEX_CONST_2_PITCHALIGN__MASK;
-}
-#define A4XX_TEX_CONST_2_BUFFER 0x00000040
-#define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
-#define A4XX_TEX_CONST_2_PITCH__SHIFT 9
-static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
-{
- return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK;
-}
-#define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000
-#define A4XX_TEX_CONST_2_SWAP__SHIFT 30
-static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK;
-}
-
-#define REG_A4XX_TEX_CONST_3 0x00000003
-#define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff
-#define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0
-static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
-}
-#define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000
-#define A4XX_TEX_CONST_3_DEPTH__SHIFT 18
-static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
-{
- return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK;
-}
-
-#define REG_A4XX_TEX_CONST_4 0x00000004
-#define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f
-#define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0
-static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
-}
-#define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0
-#define A4XX_TEX_CONST_4_BASE__SHIFT 5
-static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
-}
-
-#define REG_A4XX_TEX_CONST_5 0x00000005
-
-#define REG_A4XX_TEX_CONST_6 0x00000006
-
-#define REG_A4XX_TEX_CONST_7 0x00000007
-
-#define REG_A4XX_SSBO_0_0 0x00000000
-#define A4XX_SSBO_0_0_BASE__MASK 0xffffffe0
-#define A4XX_SSBO_0_0_BASE__SHIFT 5
-static inline uint32_t A4XX_SSBO_0_0_BASE(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A4XX_SSBO_0_0_BASE__SHIFT) & A4XX_SSBO_0_0_BASE__MASK;
-}
-
-#define REG_A4XX_SSBO_0_1 0x00000001
-#define A4XX_SSBO_0_1_PITCH__MASK 0x003fffff
-#define A4XX_SSBO_0_1_PITCH__SHIFT 0
-static inline uint32_t A4XX_SSBO_0_1_PITCH(uint32_t val)
-{
- return ((val) << A4XX_SSBO_0_1_PITCH__SHIFT) & A4XX_SSBO_0_1_PITCH__MASK;
-}
-
-#define REG_A4XX_SSBO_0_2 0x00000002
-#define A4XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000
-#define A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12
-static inline uint32_t A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A4XX_SSBO_0_2_ARRAY_PITCH__MASK;
-}
-
-#define REG_A4XX_SSBO_0_3 0x00000003
-#define A4XX_SSBO_0_3_CPP__MASK 0x0000003f
-#define A4XX_SSBO_0_3_CPP__SHIFT 0
-static inline uint32_t A4XX_SSBO_0_3_CPP(uint32_t val)
-{
- return ((val) << A4XX_SSBO_0_3_CPP__SHIFT) & A4XX_SSBO_0_3_CPP__MASK;
-}
-
-#define REG_A4XX_SSBO_1_0 0x00000000
-#define A4XX_SSBO_1_0_CPP__MASK 0x0000001f
-#define A4XX_SSBO_1_0_CPP__SHIFT 0
-static inline uint32_t A4XX_SSBO_1_0_CPP(uint32_t val)
-{
- return ((val) << A4XX_SSBO_1_0_CPP__SHIFT) & A4XX_SSBO_1_0_CPP__MASK;
-}
-#define A4XX_SSBO_1_0_FMT__MASK 0x0000ff00
-#define A4XX_SSBO_1_0_FMT__SHIFT 8
-static inline uint32_t A4XX_SSBO_1_0_FMT(enum a4xx_color_fmt val)
-{
- return ((val) << A4XX_SSBO_1_0_FMT__SHIFT) & A4XX_SSBO_1_0_FMT__MASK;
-}
-#define A4XX_SSBO_1_0_WIDTH__MASK 0xffff0000
-#define A4XX_SSBO_1_0_WIDTH__SHIFT 16
-static inline uint32_t A4XX_SSBO_1_0_WIDTH(uint32_t val)
-{
- return ((val) << A4XX_SSBO_1_0_WIDTH__SHIFT) & A4XX_SSBO_1_0_WIDTH__MASK;
-}
-
-#define REG_A4XX_SSBO_1_1 0x00000001
-#define A4XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff
-#define A4XX_SSBO_1_1_HEIGHT__SHIFT 0
-static inline uint32_t A4XX_SSBO_1_1_HEIGHT(uint32_t val)
-{
- return ((val) << A4XX_SSBO_1_1_HEIGHT__SHIFT) & A4XX_SSBO_1_1_HEIGHT__MASK;
-}
-#define A4XX_SSBO_1_1_DEPTH__MASK 0xffff0000
-#define A4XX_SSBO_1_1_DEPTH__SHIFT 16
-static inline uint32_t A4XX_SSBO_1_1_DEPTH(uint32_t val)
-{
- return ((val) << A4XX_SSBO_1_1_DEPTH__SHIFT) & A4XX_SSBO_1_1_DEPTH__MASK;
-}
-
-#ifdef __cplusplus
-#endif
-
-#endif /* A4XX_XML */
diff --git a/drivers/gpu/drm/msm/adreno/a5xx.xml.h b/drivers/gpu/drm/msm/adreno/a5xx.xml.h
deleted file mode 100644
index d66306c14986..000000000000
--- a/drivers/gpu/drm/msm/adreno/a5xx.xml.h
+++ /dev/null
@@ -1,5572 +0,0 @@
-#ifndef A5XX_XML
-#define A5XX_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
-http://gitlab.freedesktop.org/mesa/mesa/
-git clone https://gitlab.freedesktop.org/mesa/mesa.git
-
-The rules-ng-ng source files this header was generated from are:
-
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 151693 bytes, from Wed Aug 23 10:39:39 2023)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024)
-
-Copyright (C) 2013-2024 by the following authors:
-- Rob Clark <robdclark@gmail.com> Rob Clark
-- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-*/
-
-#ifdef __KERNEL__
-#include <linux/bug.h>
-#define assert(x) BUG_ON(!(x))
-#else
-#include <assert.h>
-#endif
-
-#ifdef __cplusplus
-#define __struct_cast(X)
-#else
-#define __struct_cast(X) (struct X)
-#endif
-
-enum a5xx_color_fmt {
- RB5_A8_UNORM = 2,
- RB5_R8_UNORM = 3,
- RB5_R8_SNORM = 4,
- RB5_R8_UINT = 5,
- RB5_R8_SINT = 6,
- RB5_R4G4B4A4_UNORM = 8,
- RB5_R5G5B5A1_UNORM = 10,
- RB5_R5G6B5_UNORM = 14,
- RB5_R8G8_UNORM = 15,
- RB5_R8G8_SNORM = 16,
- RB5_R8G8_UINT = 17,
- RB5_R8G8_SINT = 18,
- RB5_R16_UNORM = 21,
- RB5_R16_SNORM = 22,
- RB5_R16_FLOAT = 23,
- RB5_R16_UINT = 24,
- RB5_R16_SINT = 25,
- RB5_R8G8B8A8_UNORM = 48,
- RB5_R8G8B8_UNORM = 49,
- RB5_R8G8B8A8_SNORM = 50,
- RB5_R8G8B8A8_UINT = 51,
- RB5_R8G8B8A8_SINT = 52,
- RB5_R10G10B10A2_UNORM = 55,
- RB5_R10G10B10A2_UINT = 58,
- RB5_R11G11B10_FLOAT = 66,
- RB5_R16G16_UNORM = 67,
- RB5_R16G16_SNORM = 68,
- RB5_R16G16_FLOAT = 69,
- RB5_R16G16_UINT = 70,
- RB5_R16G16_SINT = 71,
- RB5_R32_FLOAT = 74,
- RB5_R32_UINT = 75,
- RB5_R32_SINT = 76,
- RB5_R16G16B16A16_UNORM = 96,
- RB5_R16G16B16A16_SNORM = 97,
- RB5_R16G16B16A16_FLOAT = 98,
- RB5_R16G16B16A16_UINT = 99,
- RB5_R16G16B16A16_SINT = 100,
- RB5_R32G32_FLOAT = 103,
- RB5_R32G32_UINT = 104,
- RB5_R32G32_SINT = 105,
- RB5_R32G32B32A32_FLOAT = 130,
- RB5_R32G32B32A32_UINT = 131,
- RB5_R32G32B32A32_SINT = 132,
- RB5_NONE = 255,
-};
-
-enum a5xx_tile_mode {
- TILE5_LINEAR = 0,
- TILE5_2 = 2,
- TILE5_3 = 3,
-};
-
-enum a5xx_vtx_fmt {
- VFMT5_8_UNORM = 3,
- VFMT5_8_SNORM = 4,
- VFMT5_8_UINT = 5,
- VFMT5_8_SINT = 6,
- VFMT5_8_8_UNORM = 15,
- VFMT5_8_8_SNORM = 16,
- VFMT5_8_8_UINT = 17,
- VFMT5_8_8_SINT = 18,
- VFMT5_16_UNORM = 21,
- VFMT5_16_SNORM = 22,
- VFMT5_16_FLOAT = 23,
- VFMT5_16_UINT = 24,
- VFMT5_16_SINT = 25,
- VFMT5_8_8_8_UNORM = 33,
- VFMT5_8_8_8_SNORM = 34,
- VFMT5_8_8_8_UINT = 35,
- VFMT5_8_8_8_SINT = 36,
- VFMT5_8_8_8_8_UNORM = 48,
- VFMT5_8_8_8_8_SNORM = 50,
- VFMT5_8_8_8_8_UINT = 51,
- VFMT5_8_8_8_8_SINT = 52,
- VFMT5_10_10_10_2_UNORM = 54,
- VFMT5_10_10_10_2_SNORM = 57,
- VFMT5_10_10_10_2_UINT = 58,
- VFMT5_10_10_10_2_SINT = 59,
- VFMT5_11_11_10_FLOAT = 66,
- VFMT5_16_16_UNORM = 67,
- VFMT5_16_16_SNORM = 68,
- VFMT5_16_16_FLOAT = 69,
- VFMT5_16_16_UINT = 70,
- VFMT5_16_16_SINT = 71,
- VFMT5_32_UNORM = 72,
- VFMT5_32_SNORM = 73,
- VFMT5_32_FLOAT = 74,
- VFMT5_32_UINT = 75,
- VFMT5_32_SINT = 76,
- VFMT5_32_FIXED = 77,
- VFMT5_16_16_16_UNORM = 88,
- VFMT5_16_16_16_SNORM = 89,
- VFMT5_16_16_16_FLOAT = 90,
- VFMT5_16_16_16_UINT = 91,
- VFMT5_16_16_16_SINT = 92,
- VFMT5_16_16_16_16_UNORM = 96,
- VFMT5_16_16_16_16_SNORM = 97,
- VFMT5_16_16_16_16_FLOAT = 98,
- VFMT5_16_16_16_16_UINT = 99,
- VFMT5_16_16_16_16_SINT = 100,
- VFMT5_32_32_UNORM = 101,
- VFMT5_32_32_SNORM = 102,
- VFMT5_32_32_FLOAT = 103,
- VFMT5_32_32_UINT = 104,
- VFMT5_32_32_SINT = 105,
- VFMT5_32_32_FIXED = 106,
- VFMT5_32_32_32_UNORM = 112,
- VFMT5_32_32_32_SNORM = 113,
- VFMT5_32_32_32_UINT = 114,
- VFMT5_32_32_32_SINT = 115,
- VFMT5_32_32_32_FLOAT = 116,
- VFMT5_32_32_32_FIXED = 117,
- VFMT5_32_32_32_32_UNORM = 128,
- VFMT5_32_32_32_32_SNORM = 129,
- VFMT5_32_32_32_32_FLOAT = 130,
- VFMT5_32_32_32_32_UINT = 131,
- VFMT5_32_32_32_32_SINT = 132,
- VFMT5_32_32_32_32_FIXED = 133,
- VFMT5_NONE = 255,
-};
-
-enum a5xx_tex_fmt {
- TFMT5_A8_UNORM = 2,
- TFMT5_8_UNORM = 3,
- TFMT5_8_SNORM = 4,
- TFMT5_8_UINT = 5,
- TFMT5_8_SINT = 6,
- TFMT5_4_4_4_4_UNORM = 8,
- TFMT5_5_5_5_1_UNORM = 10,
- TFMT5_5_6_5_UNORM = 14,
- TFMT5_8_8_UNORM = 15,
- TFMT5_8_8_SNORM = 16,
- TFMT5_8_8_UINT = 17,
- TFMT5_8_8_SINT = 18,
- TFMT5_L8_A8_UNORM = 19,
- TFMT5_16_UNORM = 21,
- TFMT5_16_SNORM = 22,
- TFMT5_16_FLOAT = 23,
- TFMT5_16_UINT = 24,
- TFMT5_16_SINT = 25,
- TFMT5_8_8_8_8_UNORM = 48,
- TFMT5_8_8_8_UNORM = 49,
- TFMT5_8_8_8_8_SNORM = 50,
- TFMT5_8_8_8_8_UINT = 51,
- TFMT5_8_8_8_8_SINT = 52,
- TFMT5_9_9_9_E5_FLOAT = 53,
- TFMT5_10_10_10_2_UNORM = 54,
- TFMT5_10_10_10_2_UINT = 58,
- TFMT5_11_11_10_FLOAT = 66,
- TFMT5_16_16_UNORM = 67,
- TFMT5_16_16_SNORM = 68,
- TFMT5_16_16_FLOAT = 69,
- TFMT5_16_16_UINT = 70,
- TFMT5_16_16_SINT = 71,
- TFMT5_32_FLOAT = 74,
- TFMT5_32_UINT = 75,
- TFMT5_32_SINT = 76,
- TFMT5_16_16_16_16_UNORM = 96,
- TFMT5_16_16_16_16_SNORM = 97,
- TFMT5_16_16_16_16_FLOAT = 98,
- TFMT5_16_16_16_16_UINT = 99,
- TFMT5_16_16_16_16_SINT = 100,
- TFMT5_32_32_FLOAT = 103,
- TFMT5_32_32_UINT = 104,
- TFMT5_32_32_SINT = 105,
- TFMT5_32_32_32_UINT = 114,
- TFMT5_32_32_32_SINT = 115,
- TFMT5_32_32_32_FLOAT = 116,
- TFMT5_32_32_32_32_FLOAT = 130,
- TFMT5_32_32_32_32_UINT = 131,
- TFMT5_32_32_32_32_SINT = 132,
- TFMT5_X8Z24_UNORM = 160,
- TFMT5_ETC2_RG11_UNORM = 171,
- TFMT5_ETC2_RG11_SNORM = 172,
- TFMT5_ETC2_R11_UNORM = 173,
- TFMT5_ETC2_R11_SNORM = 174,
- TFMT5_ETC1 = 175,
- TFMT5_ETC2_RGB8 = 176,
- TFMT5_ETC2_RGBA8 = 177,
- TFMT5_ETC2_RGB8A1 = 178,
- TFMT5_DXT1 = 179,
- TFMT5_DXT3 = 180,
- TFMT5_DXT5 = 181,
- TFMT5_RGTC1_UNORM = 183,
- TFMT5_RGTC1_SNORM = 184,
- TFMT5_RGTC2_UNORM = 187,
- TFMT5_RGTC2_SNORM = 188,
- TFMT5_BPTC_UFLOAT = 190,
- TFMT5_BPTC_FLOAT = 191,
- TFMT5_BPTC = 192,
- TFMT5_ASTC_4x4 = 193,
- TFMT5_ASTC_5x4 = 194,
- TFMT5_ASTC_5x5 = 195,
- TFMT5_ASTC_6x5 = 196,
- TFMT5_ASTC_6x6 = 197,
- TFMT5_ASTC_8x5 = 198,
- TFMT5_ASTC_8x6 = 199,
- TFMT5_ASTC_8x8 = 200,
- TFMT5_ASTC_10x5 = 201,
- TFMT5_ASTC_10x6 = 202,
- TFMT5_ASTC_10x8 = 203,
- TFMT5_ASTC_10x10 = 204,
- TFMT5_ASTC_12x10 = 205,
- TFMT5_ASTC_12x12 = 206,
- TFMT5_NONE = 255,
-};
-
-enum a5xx_depth_format {
- DEPTH5_NONE = 0,
- DEPTH5_16 = 1,
- DEPTH5_24_8 = 2,
- DEPTH5_32 = 4,
-};
-
-enum a5xx_blit_buf {
- BLIT_MRT0 = 0,
- BLIT_MRT1 = 1,
- BLIT_MRT2 = 2,
- BLIT_MRT3 = 3,
- BLIT_MRT4 = 4,
- BLIT_MRT5 = 5,
- BLIT_MRT6 = 6,
- BLIT_MRT7 = 7,
- BLIT_ZS = 8,
- BLIT_S = 9,
-};
-
-enum a5xx_cp_perfcounter_select {
- PERF_CP_ALWAYS_COUNT = 0,
- PERF_CP_BUSY_GFX_CORE_IDLE = 1,
- PERF_CP_BUSY_CYCLES = 2,
- PERF_CP_PFP_IDLE = 3,
- PERF_CP_PFP_BUSY_WORKING = 4,
- PERF_CP_PFP_STALL_CYCLES_ANY = 5,
- PERF_CP_PFP_STARVE_CYCLES_ANY = 6,
- PERF_CP_PFP_ICACHE_MISS = 7,
- PERF_CP_PFP_ICACHE_HIT = 8,
- PERF_CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
- PERF_CP_ME_BUSY_WORKING = 10,
- PERF_CP_ME_IDLE = 11,
- PERF_CP_ME_STARVE_CYCLES_ANY = 12,
- PERF_CP_ME_FIFO_EMPTY_PFP_IDLE = 13,
- PERF_CP_ME_FIFO_EMPTY_PFP_BUSY = 14,
- PERF_CP_ME_FIFO_FULL_ME_BUSY = 15,
- PERF_CP_ME_FIFO_FULL_ME_NON_WORKING = 16,
- PERF_CP_ME_STALL_CYCLES_ANY = 17,
- PERF_CP_ME_ICACHE_MISS = 18,
- PERF_CP_ME_ICACHE_HIT = 19,
- PERF_CP_NUM_PREEMPTIONS = 20,
- PERF_CP_PREEMPTION_REACTION_DELAY = 21,
- PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 22,
- PERF_CP_PREEMPTION_SWITCH_IN_TIME = 23,
- PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 24,
- PERF_CP_PREDICATED_DRAWS_KILLED = 25,
- PERF_CP_MODE_SWITCH = 26,
- PERF_CP_ZPASS_DONE = 27,
- PERF_CP_CONTEXT_DONE = 28,
- PERF_CP_CACHE_FLUSH = 29,
- PERF_CP_LONG_PREEMPTIONS = 30,
-};
-
-enum a5xx_rbbm_perfcounter_select {
- PERF_RBBM_ALWAYS_COUNT = 0,
- PERF_RBBM_ALWAYS_ON = 1,
- PERF_RBBM_TSE_BUSY = 2,
- PERF_RBBM_RAS_BUSY = 3,
- PERF_RBBM_PC_DCALL_BUSY = 4,
- PERF_RBBM_PC_VSD_BUSY = 5,
- PERF_RBBM_STATUS_MASKED = 6,
- PERF_RBBM_COM_BUSY = 7,
- PERF_RBBM_DCOM_BUSY = 8,
- PERF_RBBM_VBIF_BUSY = 9,
- PERF_RBBM_VSC_BUSY = 10,
- PERF_RBBM_TESS_BUSY = 11,
- PERF_RBBM_UCHE_BUSY = 12,
- PERF_RBBM_HLSQ_BUSY = 13,
-};
-
-enum a5xx_pc_perfcounter_select {
- PERF_PC_BUSY_CYCLES = 0,
- PERF_PC_WORKING_CYCLES = 1,
- PERF_PC_STALL_CYCLES_VFD = 2,
- PERF_PC_STALL_CYCLES_TSE = 3,
- PERF_PC_STALL_CYCLES_VPC = 4,
- PERF_PC_STALL_CYCLES_UCHE = 5,
- PERF_PC_STALL_CYCLES_TESS = 6,
- PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
- PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
- PERF_PC_PASS1_TF_STALL_CYCLES = 9,
- PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
- PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
- PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
- PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
- PERF_PC_STARVE_CYCLES_DI = 14,
- PERF_PC_VIS_STREAMS_LOADED = 15,
- PERF_PC_INSTANCES = 16,
- PERF_PC_VPC_PRIMITIVES = 17,
- PERF_PC_DEAD_PRIM = 18,
- PERF_PC_LIVE_PRIM = 19,
- PERF_PC_VERTEX_HITS = 20,
- PERF_PC_IA_VERTICES = 21,
- PERF_PC_IA_PRIMITIVES = 22,
- PERF_PC_GS_PRIMITIVES = 23,
- PERF_PC_HS_INVOCATIONS = 24,
- PERF_PC_DS_INVOCATIONS = 25,
- PERF_PC_VS_INVOCATIONS = 26,
- PERF_PC_GS_INVOCATIONS = 27,
- PERF_PC_DS_PRIMITIVES = 28,
- PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
- PERF_PC_3D_DRAWCALLS = 30,
- PERF_PC_2D_DRAWCALLS = 31,
- PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
- PERF_TESS_BUSY_CYCLES = 33,
- PERF_TESS_WORKING_CYCLES = 34,
- PERF_TESS_STALL_CYCLES_PC = 35,
- PERF_TESS_STARVE_CYCLES_PC = 36,
-};
-
-enum a5xx_vfd_perfcounter_select {
- PERF_VFD_BUSY_CYCLES = 0,
- PERF_VFD_STALL_CYCLES_UCHE = 1,
- PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
- PERF_VFD_STALL_CYCLES_MISS_VB = 3,
- PERF_VFD_STALL_CYCLES_MISS_Q = 4,
- PERF_VFD_STALL_CYCLES_SP_INFO = 5,
- PERF_VFD_STALL_CYCLES_SP_ATTR = 6,
- PERF_VFD_STALL_CYCLES_VFDP_VB = 7,
- PERF_VFD_STALL_CYCLES_VFDP_Q = 8,
- PERF_VFD_DECODER_PACKER_STALL = 9,
- PERF_VFD_STARVE_CYCLES_UCHE = 10,
- PERF_VFD_RBUFFER_FULL = 11,
- PERF_VFD_ATTR_INFO_FIFO_FULL = 12,
- PERF_VFD_DECODED_ATTRIBUTE_BYTES = 13,
- PERF_VFD_NUM_ATTRIBUTES = 14,
- PERF_VFD_INSTRUCTIONS = 15,
- PERF_VFD_UPPER_SHADER_FIBERS = 16,
- PERF_VFD_LOWER_SHADER_FIBERS = 17,
- PERF_VFD_MODE_0_FIBERS = 18,
- PERF_VFD_MODE_1_FIBERS = 19,
- PERF_VFD_MODE_2_FIBERS = 20,
- PERF_VFD_MODE_3_FIBERS = 21,
- PERF_VFD_MODE_4_FIBERS = 22,
- PERF_VFD_TOTAL_VERTICES = 23,
- PERF_VFD_NUM_ATTR_MISS = 24,
- PERF_VFD_1_BURST_REQ = 25,
- PERF_VFDP_STALL_CYCLES_VFD = 26,
- PERF_VFDP_STALL_CYCLES_VFD_INDEX = 27,
- PERF_VFDP_STALL_CYCLES_VFD_PROG = 28,
- PERF_VFDP_STARVE_CYCLES_PC = 29,
- PERF_VFDP_VS_STAGE_32_WAVES = 30,
-};
-
-enum a5xx_hlsq_perfcounter_select {
- PERF_HLSQ_BUSY_CYCLES = 0,
- PERF_HLSQ_STALL_CYCLES_UCHE = 1,
- PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
- PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
- PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
- PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
- PERF_HLSQ_FS_STAGE_32_WAVES = 6,
- PERF_HLSQ_FS_STAGE_64_WAVES = 7,
- PERF_HLSQ_QUADS = 8,
- PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE = 9,
- PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE = 10,
- PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE = 11,
- PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE = 12,
- PERF_HLSQ_CS_INVOCATIONS = 13,
- PERF_HLSQ_COMPUTE_DRAWCALLS = 14,
-};
-
-enum a5xx_vpc_perfcounter_select {
- PERF_VPC_BUSY_CYCLES = 0,
- PERF_VPC_WORKING_CYCLES = 1,
- PERF_VPC_STALL_CYCLES_UCHE = 2,
- PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
- PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
- PERF_VPC_STALL_CYCLES_PC = 5,
- PERF_VPC_STALL_CYCLES_SP_LM = 6,
- PERF_VPC_POS_EXPORT_STALL_CYCLES = 7,
- PERF_VPC_STARVE_CYCLES_SP = 8,
- PERF_VPC_STARVE_CYCLES_LRZ = 9,
- PERF_VPC_PC_PRIMITIVES = 10,
- PERF_VPC_SP_COMPONENTS = 11,
- PERF_VPC_SP_LM_PRIMITIVES = 12,
- PERF_VPC_SP_LM_COMPONENTS = 13,
- PERF_VPC_SP_LM_DWORDS = 14,
- PERF_VPC_STREAMOUT_COMPONENTS = 15,
- PERF_VPC_GRANT_PHASES = 16,
-};
-
-enum a5xx_tse_perfcounter_select {
- PERF_TSE_BUSY_CYCLES = 0,
- PERF_TSE_CLIPPING_CYCLES = 1,
- PERF_TSE_STALL_CYCLES_RAS = 2,
- PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
- PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
- PERF_TSE_STARVE_CYCLES_PC = 5,
- PERF_TSE_INPUT_PRIM = 6,
- PERF_TSE_INPUT_NULL_PRIM = 7,
- PERF_TSE_TRIVAL_REJ_PRIM = 8,
- PERF_TSE_CLIPPED_PRIM = 9,
- PERF_TSE_ZERO_AREA_PRIM = 10,
- PERF_TSE_FACENESS_CULLED_PRIM = 11,
- PERF_TSE_ZERO_PIXEL_PRIM = 12,
- PERF_TSE_OUTPUT_NULL_PRIM = 13,
- PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
- PERF_TSE_CINVOCATION = 15,
- PERF_TSE_CPRIMITIVES = 16,
- PERF_TSE_2D_INPUT_PRIM = 17,
- PERF_TSE_2D_ALIVE_CLCLES = 18,
-};
-
-enum a5xx_ras_perfcounter_select {
- PERF_RAS_BUSY_CYCLES = 0,
- PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
- PERF_RAS_STALL_CYCLES_LRZ = 2,
- PERF_RAS_STARVE_CYCLES_TSE = 3,
- PERF_RAS_SUPER_TILES = 4,
- PERF_RAS_8X4_TILES = 5,
- PERF_RAS_MASKGEN_ACTIVE = 6,
- PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
- PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
- PERF_RAS_PRIM_KILLED_INVISILBE = 9,
-};
-
-enum a5xx_lrz_perfcounter_select {
- PERF_LRZ_BUSY_CYCLES = 0,
- PERF_LRZ_STARVE_CYCLES_RAS = 1,
- PERF_LRZ_STALL_CYCLES_RB = 2,
- PERF_LRZ_STALL_CYCLES_VSC = 3,
- PERF_LRZ_STALL_CYCLES_VPC = 4,
- PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
- PERF_LRZ_STALL_CYCLES_UCHE = 6,
- PERF_LRZ_LRZ_READ = 7,
- PERF_LRZ_LRZ_WRITE = 8,
- PERF_LRZ_READ_LATENCY = 9,
- PERF_LRZ_MERGE_CACHE_UPDATING = 10,
- PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
- PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
- PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
- PERF_LRZ_FULL_8X8_TILES = 14,
- PERF_LRZ_PARTIAL_8X8_TILES = 15,
- PERF_LRZ_TILE_KILLED = 16,
- PERF_LRZ_TOTAL_PIXEL = 17,
- PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
-};
-
-enum a5xx_uche_perfcounter_select {
- PERF_UCHE_BUSY_CYCLES = 0,
- PERF_UCHE_STALL_CYCLES_VBIF = 1,
- PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
- PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
- PERF_UCHE_VBIF_READ_BEATS_TP = 4,
- PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
- PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
- PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
- PERF_UCHE_VBIF_READ_BEATS_SP = 8,
- PERF_UCHE_READ_REQUESTS_TP = 9,
- PERF_UCHE_READ_REQUESTS_VFD = 10,
- PERF_UCHE_READ_REQUESTS_HLSQ = 11,
- PERF_UCHE_READ_REQUESTS_LRZ = 12,
- PERF_UCHE_READ_REQUESTS_SP = 13,
- PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
- PERF_UCHE_WRITE_REQUESTS_SP = 15,
- PERF_UCHE_WRITE_REQUESTS_VPC = 16,
- PERF_UCHE_WRITE_REQUESTS_VSC = 17,
- PERF_UCHE_EVICTS = 18,
- PERF_UCHE_BANK_REQ0 = 19,
- PERF_UCHE_BANK_REQ1 = 20,
- PERF_UCHE_BANK_REQ2 = 21,
- PERF_UCHE_BANK_REQ3 = 22,
- PERF_UCHE_BANK_REQ4 = 23,
- PERF_UCHE_BANK_REQ5 = 24,
- PERF_UCHE_BANK_REQ6 = 25,
- PERF_UCHE_BANK_REQ7 = 26,
- PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
- PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
- PERF_UCHE_GMEM_READ_BEATS = 29,
- PERF_UCHE_FLAG_COUNT = 30,
-};
-
-enum a5xx_tp_perfcounter_select {
- PERF_TP_BUSY_CYCLES = 0,
- PERF_TP_STALL_CYCLES_UCHE = 1,
- PERF_TP_LATENCY_CYCLES = 2,
- PERF_TP_LATENCY_TRANS = 3,
- PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
- PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
- PERF_TP_L1_CACHELINE_REQUESTS = 6,
- PERF_TP_L1_CACHELINE_MISSES = 7,
- PERF_TP_SP_TP_TRANS = 8,
- PERF_TP_TP_SP_TRANS = 9,
- PERF_TP_OUTPUT_PIXELS = 10,
- PERF_TP_FILTER_WORKLOAD_16BIT = 11,
- PERF_TP_FILTER_WORKLOAD_32BIT = 12,
- PERF_TP_QUADS_RECEIVED = 13,
- PERF_TP_QUADS_OFFSET = 14,
- PERF_TP_QUADS_SHADOW = 15,
- PERF_TP_QUADS_ARRAY = 16,
- PERF_TP_QUADS_GRADIENT = 17,
- PERF_TP_QUADS_1D = 18,
- PERF_TP_QUADS_2D = 19,
- PERF_TP_QUADS_BUFFER = 20,
- PERF_TP_QUADS_3D = 21,
- PERF_TP_QUADS_CUBE = 22,
- PERF_TP_STATE_CACHE_REQUESTS = 23,
- PERF_TP_STATE_CACHE_MISSES = 24,
- PERF_TP_DIVERGENT_QUADS_RECEIVED = 25,
- PERF_TP_BINDLESS_STATE_CACHE_REQUESTS = 26,
- PERF_TP_BINDLESS_STATE_CACHE_MISSES = 27,
- PERF_TP_PRT_NON_RESIDENT_EVENTS = 28,
- PERF_TP_OUTPUT_PIXELS_POINT = 29,
- PERF_TP_OUTPUT_PIXELS_BILINEAR = 30,
- PERF_TP_OUTPUT_PIXELS_MIP = 31,
- PERF_TP_OUTPUT_PIXELS_ANISO = 32,
- PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 33,
- PERF_TP_FLAG_CACHE_REQUESTS = 34,
- PERF_TP_FLAG_CACHE_MISSES = 35,
- PERF_TP_L1_5_L2_REQUESTS = 36,
- PERF_TP_2D_OUTPUT_PIXELS = 37,
- PERF_TP_2D_OUTPUT_PIXELS_POINT = 38,
- PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 39,
- PERF_TP_2D_FILTER_WORKLOAD_16BIT = 40,
- PERF_TP_2D_FILTER_WORKLOAD_32BIT = 41,
-};
-
-enum a5xx_sp_perfcounter_select {
- PERF_SP_BUSY_CYCLES = 0,
- PERF_SP_ALU_WORKING_CYCLES = 1,
- PERF_SP_EFU_WORKING_CYCLES = 2,
- PERF_SP_STALL_CYCLES_VPC = 3,
- PERF_SP_STALL_CYCLES_TP = 4,
- PERF_SP_STALL_CYCLES_UCHE = 5,
- PERF_SP_STALL_CYCLES_RB = 6,
- PERF_SP_SCHEDULER_NON_WORKING = 7,
- PERF_SP_WAVE_CONTEXTS = 8,
- PERF_SP_WAVE_CONTEXT_CYCLES = 9,
- PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
- PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
- PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
- PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
- PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
- PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
- PERF_SP_WAVE_CTRL_CYCLES = 16,
- PERF_SP_WAVE_LOAD_CYCLES = 17,
- PERF_SP_WAVE_EMIT_CYCLES = 18,
- PERF_SP_WAVE_NOP_CYCLES = 19,
- PERF_SP_WAVE_WAIT_CYCLES = 20,
- PERF_SP_WAVE_FETCH_CYCLES = 21,
- PERF_SP_WAVE_IDLE_CYCLES = 22,
- PERF_SP_WAVE_END_CYCLES = 23,
- PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
- PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
- PERF_SP_WAVE_JOIN_CYCLES = 26,
- PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
- PERF_SP_LM_STORE_INSTRUCTIONS = 28,
- PERF_SP_LM_ATOMICS = 29,
- PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
- PERF_SP_GM_STORE_INSTRUCTIONS = 31,
- PERF_SP_GM_ATOMICS = 32,
- PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
- PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS = 34,
- PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 35,
- PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 36,
- PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 37,
- PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 38,
- PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 39,
- PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 40,
- PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 41,
- PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 42,
- PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 43,
- PERF_SP_VS_INSTRUCTIONS = 44,
- PERF_SP_FS_INSTRUCTIONS = 45,
- PERF_SP_ADDR_LOCK_COUNT = 46,
- PERF_SP_UCHE_READ_TRANS = 47,
- PERF_SP_UCHE_WRITE_TRANS = 48,
- PERF_SP_EXPORT_VPC_TRANS = 49,
- PERF_SP_EXPORT_RB_TRANS = 50,
- PERF_SP_PIXELS_KILLED = 51,
- PERF_SP_ICL1_REQUESTS = 52,
- PERF_SP_ICL1_MISSES = 53,
- PERF_SP_ICL0_REQUESTS = 54,
- PERF_SP_ICL0_MISSES = 55,
- PERF_SP_HS_INSTRUCTIONS = 56,
- PERF_SP_DS_INSTRUCTIONS = 57,
- PERF_SP_GS_INSTRUCTIONS = 58,
- PERF_SP_CS_INSTRUCTIONS = 59,
- PERF_SP_GPR_READ = 60,
- PERF_SP_GPR_WRITE = 61,
- PERF_SP_LM_CH0_REQUESTS = 62,
- PERF_SP_LM_CH1_REQUESTS = 63,
- PERF_SP_LM_BANK_CONFLICTS = 64,
-};
-
-enum a5xx_rb_perfcounter_select {
- PERF_RB_BUSY_CYCLES = 0,
- PERF_RB_STALL_CYCLES_CCU = 1,
- PERF_RB_STALL_CYCLES_HLSQ = 2,
- PERF_RB_STALL_CYCLES_FIFO0_FULL = 3,
- PERF_RB_STALL_CYCLES_FIFO1_FULL = 4,
- PERF_RB_STALL_CYCLES_FIFO2_FULL = 5,
- PERF_RB_STARVE_CYCLES_SP = 6,
- PERF_RB_STARVE_CYCLES_LRZ_TILE = 7,
- PERF_RB_STARVE_CYCLES_CCU = 8,
- PERF_RB_STARVE_CYCLES_Z_PLANE = 9,
- PERF_RB_STARVE_CYCLES_BARY_PLANE = 10,
- PERF_RB_Z_WORKLOAD = 11,
- PERF_RB_HLSQ_ACTIVE = 12,
- PERF_RB_Z_READ = 13,
- PERF_RB_Z_WRITE = 14,
- PERF_RB_C_READ = 15,
- PERF_RB_C_WRITE = 16,
- PERF_RB_TOTAL_PASS = 17,
- PERF_RB_Z_PASS = 18,
- PERF_RB_Z_FAIL = 19,
- PERF_RB_S_FAIL = 20,
- PERF_RB_BLENDED_FXP_COMPONENTS = 21,
- PERF_RB_BLENDED_FP16_COMPONENTS = 22,
- RB_RESERVED = 23,
- PERF_RB_2D_ALIVE_CYCLES = 24,
- PERF_RB_2D_STALL_CYCLES_A2D = 25,
- PERF_RB_2D_STARVE_CYCLES_SRC = 26,
- PERF_RB_2D_STARVE_CYCLES_SP = 27,
- PERF_RB_2D_STARVE_CYCLES_DST = 28,
- PERF_RB_2D_VALID_PIXELS = 29,
-};
-
-enum a5xx_rb_samples_perfcounter_select {
- TOTAL_SAMPLES = 0,
- ZPASS_SAMPLES = 1,
- ZFAIL_SAMPLES = 2,
- SFAIL_SAMPLES = 3,
-};
-
-enum a5xx_vsc_perfcounter_select {
- PERF_VSC_BUSY_CYCLES = 0,
- PERF_VSC_WORKING_CYCLES = 1,
- PERF_VSC_STALL_CYCLES_UCHE = 2,
- PERF_VSC_EOT_NUM = 3,
-};
-
-enum a5xx_ccu_perfcounter_select {
- PERF_CCU_BUSY_CYCLES = 0,
- PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
- PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
- PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
- PERF_CCU_DEPTH_BLOCKS = 4,
- PERF_CCU_COLOR_BLOCKS = 5,
- PERF_CCU_DEPTH_BLOCK_HIT = 6,
- PERF_CCU_COLOR_BLOCK_HIT = 7,
- PERF_CCU_PARTIAL_BLOCK_READ = 8,
- PERF_CCU_GMEM_READ = 9,
- PERF_CCU_GMEM_WRITE = 10,
- PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
- PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
- PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
- PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
- PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
- PERF_CCU_COLOR_READ_FLAG0_COUNT = 16,
- PERF_CCU_COLOR_READ_FLAG1_COUNT = 17,
- PERF_CCU_COLOR_READ_FLAG2_COUNT = 18,
- PERF_CCU_COLOR_READ_FLAG3_COUNT = 19,
- PERF_CCU_COLOR_READ_FLAG4_COUNT = 20,
- PERF_CCU_2D_BUSY_CYCLES = 21,
- PERF_CCU_2D_RD_REQ = 22,
- PERF_CCU_2D_WR_REQ = 23,
- PERF_CCU_2D_REORDER_STARVE_CYCLES = 24,
- PERF_CCU_2D_PIXELS = 25,
-};
-
-enum a5xx_cmp_perfcounter_select {
- PERF_CMPDECMP_STALL_CYCLES_VBIF = 0,
- PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
- PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
- PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
- PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
- PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
- PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
- PERF_CMPDECMP_VBIF_READ_DATA = 7,
- PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
- PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
- PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
- PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
- PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
- PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
- PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
- PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 15,
- PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 16,
- PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 17,
- PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 18,
- PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 19,
- PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 20,
- PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 21,
- PERF_CMPDECMP_2D_RD_DATA = 22,
- PERF_CMPDECMP_2D_WR_DATA = 23,
-};
-
-enum a5xx_vbif_perfcounter_select {
- AXI_READ_REQUESTS_ID_0 = 0,
- AXI_READ_REQUESTS_ID_1 = 1,
- AXI_READ_REQUESTS_ID_2 = 2,
- AXI_READ_REQUESTS_ID_3 = 3,
- AXI_READ_REQUESTS_ID_4 = 4,
- AXI_READ_REQUESTS_ID_5 = 5,
- AXI_READ_REQUESTS_ID_6 = 6,
- AXI_READ_REQUESTS_ID_7 = 7,
- AXI_READ_REQUESTS_ID_8 = 8,
- AXI_READ_REQUESTS_ID_9 = 9,
- AXI_READ_REQUESTS_ID_10 = 10,
- AXI_READ_REQUESTS_ID_11 = 11,
- AXI_READ_REQUESTS_ID_12 = 12,
- AXI_READ_REQUESTS_ID_13 = 13,
- AXI_READ_REQUESTS_ID_14 = 14,
- AXI_READ_REQUESTS_ID_15 = 15,
- AXI0_READ_REQUESTS_TOTAL = 16,
- AXI1_READ_REQUESTS_TOTAL = 17,
- AXI2_READ_REQUESTS_TOTAL = 18,
- AXI3_READ_REQUESTS_TOTAL = 19,
- AXI_READ_REQUESTS_TOTAL = 20,
- AXI_WRITE_REQUESTS_ID_0 = 21,
- AXI_WRITE_REQUESTS_ID_1 = 22,
- AXI_WRITE_REQUESTS_ID_2 = 23,
- AXI_WRITE_REQUESTS_ID_3 = 24,
- AXI_WRITE_REQUESTS_ID_4 = 25,
- AXI_WRITE_REQUESTS_ID_5 = 26,
- AXI_WRITE_REQUESTS_ID_6 = 27,
- AXI_WRITE_REQUESTS_ID_7 = 28,
- AXI_WRITE_REQUESTS_ID_8 = 29,
- AXI_WRITE_REQUESTS_ID_9 = 30,
- AXI_WRITE_REQUESTS_ID_10 = 31,
- AXI_WRITE_REQUESTS_ID_11 = 32,
- AXI_WRITE_REQUESTS_ID_12 = 33,
- AXI_WRITE_REQUESTS_ID_13 = 34,
- AXI_WRITE_REQUESTS_ID_14 = 35,
- AXI_WRITE_REQUESTS_ID_15 = 36,
- AXI0_WRITE_REQUESTS_TOTAL = 37,
- AXI1_WRITE_REQUESTS_TOTAL = 38,
- AXI2_WRITE_REQUESTS_TOTAL = 39,
- AXI3_WRITE_REQUESTS_TOTAL = 40,
- AXI_WRITE_REQUESTS_TOTAL = 41,
- AXI_TOTAL_REQUESTS = 42,
- AXI_READ_DATA_BEATS_ID_0 = 43,
- AXI_READ_DATA_BEATS_ID_1 = 44,
- AXI_READ_DATA_BEATS_ID_2 = 45,
- AXI_READ_DATA_BEATS_ID_3 = 46,
- AXI_READ_DATA_BEATS_ID_4 = 47,
- AXI_READ_DATA_BEATS_ID_5 = 48,
- AXI_READ_DATA_BEATS_ID_6 = 49,
- AXI_READ_DATA_BEATS_ID_7 = 50,
- AXI_READ_DATA_BEATS_ID_8 = 51,
- AXI_READ_DATA_BEATS_ID_9 = 52,
- AXI_READ_DATA_BEATS_ID_10 = 53,
- AXI_READ_DATA_BEATS_ID_11 = 54,
- AXI_READ_DATA_BEATS_ID_12 = 55,
- AXI_READ_DATA_BEATS_ID_13 = 56,
- AXI_READ_DATA_BEATS_ID_14 = 57,
- AXI_READ_DATA_BEATS_ID_15 = 58,
- AXI0_READ_DATA_BEATS_TOTAL = 59,
- AXI1_READ_DATA_BEATS_TOTAL = 60,
- AXI2_READ_DATA_BEATS_TOTAL = 61,
- AXI3_READ_DATA_BEATS_TOTAL = 62,
- AXI_READ_DATA_BEATS_TOTAL = 63,
- AXI_WRITE_DATA_BEATS_ID_0 = 64,
- AXI_WRITE_DATA_BEATS_ID_1 = 65,
- AXI_WRITE_DATA_BEATS_ID_2 = 66,
- AXI_WRITE_DATA_BEATS_ID_3 = 67,
- AXI_WRITE_DATA_BEATS_ID_4 = 68,
- AXI_WRITE_DATA_BEATS_ID_5 = 69,
- AXI_WRITE_DATA_BEATS_ID_6 = 70,
- AXI_WRITE_DATA_BEATS_ID_7 = 71,
- AXI_WRITE_DATA_BEATS_ID_8 = 72,
- AXI_WRITE_DATA_BEATS_ID_9 = 73,
- AXI_WRITE_DATA_BEATS_ID_10 = 74,
- AXI_WRITE_DATA_BEATS_ID_11 = 75,
- AXI_WRITE_DATA_BEATS_ID_12 = 76,
- AXI_WRITE_DATA_BEATS_ID_13 = 77,
- AXI_WRITE_DATA_BEATS_ID_14 = 78,
- AXI_WRITE_DATA_BEATS_ID_15 = 79,
- AXI0_WRITE_DATA_BEATS_TOTAL = 80,
- AXI1_WRITE_DATA_BEATS_TOTAL = 81,
- AXI2_WRITE_DATA_BEATS_TOTAL = 82,
- AXI3_WRITE_DATA_BEATS_TOTAL = 83,
- AXI_WRITE_DATA_BEATS_TOTAL = 84,
- AXI_DATA_BEATS_TOTAL = 85,
-};
-
-enum a5xx_tex_filter {
- A5XX_TEX_NEAREST = 0,
- A5XX_TEX_LINEAR = 1,
- A5XX_TEX_ANISO = 2,
-};
-
-enum a5xx_tex_clamp {
- A5XX_TEX_REPEAT = 0,
- A5XX_TEX_CLAMP_TO_EDGE = 1,
- A5XX_TEX_MIRROR_REPEAT = 2,
- A5XX_TEX_CLAMP_TO_BORDER = 3,
- A5XX_TEX_MIRROR_CLAMP = 4,
-};
-
-enum a5xx_tex_aniso {
- A5XX_TEX_ANISO_1 = 0,
- A5XX_TEX_ANISO_2 = 1,
- A5XX_TEX_ANISO_4 = 2,
- A5XX_TEX_ANISO_8 = 3,
- A5XX_TEX_ANISO_16 = 4,
-};
-
-enum a5xx_tex_swiz {
- A5XX_TEX_X = 0,
- A5XX_TEX_Y = 1,
- A5XX_TEX_Z = 2,
- A5XX_TEX_W = 3,
- A5XX_TEX_ZERO = 4,
- A5XX_TEX_ONE = 5,
-};
-
-enum a5xx_tex_type {
- A5XX_TEX_1D = 0,
- A5XX_TEX_2D = 1,
- A5XX_TEX_CUBE = 2,
- A5XX_TEX_3D = 3,
- A5XX_TEX_BUFFER = 4,
-};
-
-#define A5XX_INT0_RBBM_GPU_IDLE 0x00000001
-#define A5XX_INT0_RBBM_AHB_ERROR 0x00000002
-#define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004
-#define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
-#define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
-#define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020
-#define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
-#define A5XX_INT0_RBBM_GPC_ERROR 0x00000080
-#define A5XX_INT0_CP_SW 0x00000100
-#define A5XX_INT0_CP_HW_ERROR 0x00000200
-#define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400
-#define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800
-#define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000
-#define A5XX_INT0_CP_IB2 0x00002000
-#define A5XX_INT0_CP_IB1 0x00004000
-#define A5XX_INT0_CP_RB 0x00008000
-#define A5XX_INT0_CP_UNUSED_1 0x00010000
-#define A5XX_INT0_CP_RB_DONE_TS 0x00020000
-#define A5XX_INT0_CP_WT_DONE_TS 0x00040000
-#define A5XX_INT0_UNKNOWN_1 0x00080000
-#define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000
-#define A5XX_INT0_UNUSED_2 0x00200000
-#define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000
-#define A5XX_INT0_MISC_HANG_DETECT 0x00800000
-#define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000
-#define A5XX_INT0_UCHE_TRAP_INTR 0x02000000
-#define A5XX_INT0_DEBBUS_INTR_0 0x04000000
-#define A5XX_INT0_DEBBUS_INTR_1 0x08000000
-#define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000
-#define A5XX_INT0_GPMU_FIRMWARE 0x20000000
-#define A5XX_INT0_ISDB_CPU_IRQ 0x40000000
-#define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000
-
-#define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001
-#define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002
-#define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
-#define A5XX_CP_INT_CP_DMA_ERROR 0x00000008
-#define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
-#define A5XX_CP_INT_CP_AHB_ERROR 0x00000020
-
-#define REG_A5XX_CP_RB_BASE 0x00000800
-
-#define REG_A5XX_CP_RB_BASE_HI 0x00000801
-
-#define REG_A5XX_CP_RB_CNTL 0x00000802
-
-#define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804
-
-#define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805
-
-#define REG_A5XX_CP_RB_RPTR 0x00000806
-
-#define REG_A5XX_CP_RB_WPTR 0x00000807
-
-#define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808
-
-#define REG_A5XX_CP_PFP_STAT_DATA 0x00000809
-
-#define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b
-
-#define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c
-
-#define REG_A5XX_CP_ME_NRT_ADDR_LO 0x0000080d
-
-#define REG_A5XX_CP_ME_NRT_ADDR_HI 0x0000080e
-
-#define REG_A5XX_CP_ME_NRT_DATA 0x00000810
-
-#define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817
-
-#define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818
-
-#define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819
-
-#define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a
-
-#define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f
-
-#define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820
-
-#define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821
-
-#define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822
-
-#define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823
-
-#define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824
-
-#define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825
-
-#define REG_A5XX_CP_MERCIU_SIZE 0x00000826
-
-#define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827
-
-#define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828
-
-#define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829
-
-#define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a
-
-#define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b
-
-#define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f
-
-#define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830
-
-#define REG_A5XX_CP_CNTL 0x00000831
-
-#define REG_A5XX_CP_PFP_ME_CNTL 0x00000832
-
-#define REG_A5XX_CP_CHICKEN_DBG 0x00000833
-
-#define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835
-
-#define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836
-
-#define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838
-
-#define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839
-
-#define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b
-
-#define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c
-
-#define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d
-
-#define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e
-
-#define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f
-
-#define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840
-
-#define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841
-
-#define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860
-
-#define REG_A5XX_CP_ME_STAT_DATA 0x00000b14
-
-#define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15
-
-#define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18
-
-#define REG_A5XX_CP_HW_FAULT 0x00000b1a
-
-#define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c
-
-#define REG_A5XX_CP_IB1_BASE 0x00000b1f
-
-#define REG_A5XX_CP_IB1_BASE_HI 0x00000b20
-
-#define REG_A5XX_CP_IB1_BUFSZ 0x00000b21
-
-#define REG_A5XX_CP_IB2_BASE 0x00000b22
-
-#define REG_A5XX_CP_IB2_BASE_HI 0x00000b23
-
-#define REG_A5XX_CP_IB2_BUFSZ 0x00000b24
-
-#define REG_A5XX_CP_SCRATCH(i0) (0x00000b78 + 0x1*(i0))
-
-static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
-
-#define REG_A5XX_CP_PROTECT(i0) (0x00000880 + 0x1*(i0))
-
-static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; }
-#define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
-#define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
-static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
-{
- return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK;
-}
-#define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
-#define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24
-static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
-{
- return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK;
-}
-#define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
-#define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000
-
-#define REG_A5XX_CP_PROTECT_CNTL 0x000008a0
-
-#define REG_A5XX_CP_AHB_FAULT 0x00000b1b
-
-#define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0
-
-#define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1
-
-#define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2
-
-#define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3
-
-#define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4
-
-#define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5
-
-#define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6
-
-#define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7
-
-#define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1
-
-#define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba
-
-#define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb
-
-#define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc
-
-#define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009
-
-#define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024
-
-#define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f
-
-#define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037
-
-#define REG_A5XX_RBBM_INT_0_MASK 0x00000038
-#define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
-#define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002
-#define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004
-#define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008
-#define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010
-#define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020
-#define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
-#define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
-#define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100
-#define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
-#define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
-#define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
-#define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
-#define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
-#define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
-#define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000
-#define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
-#define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
-#define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
-#define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
-#define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000
-#define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
-#define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
-#define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
-#define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
-#define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000
-#define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000
-#define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
-#define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
-
-#define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f
-
-#define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041
-
-#define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043
-
-#define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
-
-#define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
-
-#define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048
-
-#define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d
-
-#define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e
-
-#define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f
-
-#define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050
-
-#define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051
-
-#define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052
-
-#define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053
-
-#define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054
-
-#define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055
-
-#define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a
-
-#define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b
-
-#define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c
-
-#define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d
-
-#define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f
-
-#define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061
-
-#define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063
-
-#define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066
-
-#define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b
-
-#define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c
-
-#define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d
-
-#define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e
-
-#define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f
-
-#define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070
-
-#define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071
-
-#define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072
-
-#define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b
-
-#define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c
-
-#define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d
-
-#define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e
-
-#define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f
-
-#define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085
-
-#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086
-
-#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087
-
-#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088
-
-#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a
-
-#define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f
-
-#define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090
-
-#define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092
-
-#define REG_A5XX_RBBM_AHB_CNTL0 0x00000093
-
-#define REG_A5XX_RBBM_AHB_CNTL1 0x00000094
-
-#define REG_A5XX_RBBM_AHB_CNTL2 0x00000095
-
-#define REG_A5XX_RBBM_AHB_CMD 0x00000096
-
-#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c
-
-#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d
-
-#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e
-
-#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f
-
-#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0
-
-#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1
-
-#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2
-
-#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7
-
-#define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8
-
-#define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9
-
-#define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa
-
-#define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab
-
-#define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac
-
-#define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad
-
-#define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae
-
-#define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af
-
-#define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0
-
-#define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1
-
-#define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2
-
-#define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3
-
-#define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4
-
-#define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5
-
-#define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6
-
-#define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7
-
-#define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8
-
-#define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9
-
-#define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba
-
-#define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb
-
-#define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8
-
-#define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9
-
-#define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca
-
-#define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0
-
-#define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1
-
-#define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2
-
-#define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3
-
-#define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4
-
-#define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5
-
-#define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6
-
-#define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7
-
-#define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8
-
-#define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9
-
-#define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa
-
-#define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab
-
-#define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac
-
-#define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad
-
-#define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae
-
-#define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af
-
-#define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0
-
-#define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1
-
-#define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2
-
-#define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3
-
-#define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4
-
-#define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5
-
-#define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6
-
-#define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7
-
-#define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8
-
-#define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9
-
-#define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba
-
-#define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb
-
-#define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc
-
-#define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd
-
-#define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be
-
-#define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf
-
-#define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0
-
-#define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1
-
-#define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2
-
-#define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3
-
-#define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4
-
-#define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5
-
-#define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6
-
-#define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7
-
-#define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8
-
-#define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9
-
-#define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca
-
-#define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb
-
-#define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc
-
-#define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd
-
-#define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce
-
-#define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf
-
-#define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0
-
-#define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1
-
-#define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2
-
-#define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3
-
-#define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4
-
-#define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5
-
-#define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6
-
-#define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7
-
-#define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8
-
-#define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9
-
-#define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da
-
-#define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db
-
-#define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc
-
-#define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd
-
-#define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de
-
-#define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df
-
-#define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0
-
-#define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1
-
-#define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2
-
-#define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3
-
-#define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4
-
-#define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5
-
-#define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6
-
-#define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7
-
-#define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8
-
-#define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9
-
-#define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea
-
-#define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb
-
-#define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec
-
-#define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed
-
-#define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee
-
-#define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef
-
-#define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0
-
-#define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1
-
-#define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2
-
-#define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3
-
-#define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4
-
-#define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5
-
-#define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6
-
-#define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7
-
-#define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8
-
-#define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9
-
-#define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa
-
-#define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb
-
-#define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc
-
-#define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd
-
-#define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe
-
-#define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff
-
-#define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400
-
-#define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401
-
-#define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402
-
-#define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403
-
-#define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404
-
-#define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405
-
-#define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406
-
-#define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407
-
-#define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408
-
-#define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409
-
-#define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a
-
-#define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b
-
-#define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c
-
-#define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d
-
-#define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e
-
-#define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f
-
-#define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410
-
-#define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411
-
-#define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412
-
-#define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413
-
-#define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414
-
-#define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415
-
-#define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416
-
-#define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417
-
-#define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418
-
-#define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419
-
-#define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a
-
-#define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b
-
-#define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c
-
-#define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d
-
-#define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e
-
-#define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f
-
-#define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420
-
-#define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421
-
-#define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422
-
-#define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423
-
-#define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424
-
-#define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425
-
-#define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426
-
-#define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427
-
-#define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428
-
-#define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429
-
-#define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a
-
-#define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b
-
-#define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c
-
-#define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d
-
-#define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e
-
-#define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f
-
-#define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430
-
-#define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431
-
-#define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432
-
-#define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433
-
-#define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434
-
-#define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435
-
-#define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436
-
-#define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437
-
-#define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438
-
-#define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439
-
-#define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a
-
-#define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b
-
-#define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c
-
-#define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d
-
-#define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e
-
-#define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f
-
-#define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440
-
-#define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441
-
-#define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442
-
-#define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443
-
-#define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444
-
-#define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445
-
-#define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446
-
-#define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447
-
-#define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448
-
-#define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449
-
-#define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a
-
-#define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b
-
-#define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c
-
-#define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d
-
-#define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e
-
-#define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f
-
-#define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450
-
-#define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451
-
-#define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452
-
-#define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453
-
-#define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454
-
-#define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455
-
-#define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456
-
-#define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457
-
-#define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458
-
-#define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459
-
-#define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a
-
-#define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b
-
-#define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c
-
-#define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d
-
-#define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e
-
-#define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f
-
-#define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460
-
-#define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461
-
-#define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462
-
-#define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463
-
-#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
-
-#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
-
-#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
-
-#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
-
-#define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2
-
-#define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3
-
-#define REG_A5XX_RBBM_STATUS 0x000004f5
-#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000
-#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000
-#define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
-#define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000
-#define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000
-#define A5XX_RBBM_STATUS_SP_BUSY 0x04000000
-#define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000
-#define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000
-#define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000
-#define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000
-#define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000
-#define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
-#define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
-#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000
-#define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000
-#define A5XX_RBBM_STATUS_COM_BUSY 0x00010000
-#define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000
-#define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000
-#define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000
-#define A5XX_RBBM_STATUS_RB_BUSY 0x00001000
-#define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800
-#define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400
-#define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200
-#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100
-#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080
-#define A5XX_RBBM_STATUS_CP_BUSY 0x00000040
-#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020
-#define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010
-#define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008
-#define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
-#define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
-#define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
-
-#define REG_A5XX_RBBM_STATUS3 0x00000530
-#define A5XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
-
-#define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
-
-#define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0
-
-#define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1
-
-#define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3
-
-#define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4
-
-#define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464
-
-#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465
-
-#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466
-
-#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467
-
-#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468
-
-#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469
-
-#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a
-
-#define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f
-
-#define REG_A5XX_RBBM_AHB_ERROR 0x000004ed
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512
-
-#define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513
-
-#define REG_A5XX_RBBM_ISDB_CNT 0x00000533
-
-#define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000
-
-#define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
-
-#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
-
-#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
-
-#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
-
-#define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803
-
-#define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804
-
-#define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805
-
-#define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806
-
-#define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807
-
-#define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
-
-#define REG_A5XX_VSC_BIN_SIZE 0x00000bc2
-#define A5XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
-#define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
-static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK;
-}
-#define A5XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001fe00
-#define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT 9
-static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK;
-}
-
-#define REG_A5XX_VSC_SIZE_ADDRESS_LO 0x00000bc3
-
-#define REG_A5XX_VSC_SIZE_ADDRESS_HI 0x00000bc4
-
-#define REG_A5XX_UNKNOWN_0BC5 0x00000bc5
-
-#define REG_A5XX_UNKNOWN_0BC6 0x00000bc6
-
-#define REG_A5XX_VSC_PIPE_CONFIG(i0) (0x00000bd0 + 0x1*(i0))
-
-static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
-#define A5XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
-#define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
-static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
-{
- return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK;
-}
-#define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
-#define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
-static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
-{
- return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK;
-}
-#define A5XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
-#define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
-static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
-{
- return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK;
-}
-#define A5XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
-#define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
-static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
-{
- return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK;
-}
-
-#define REG_A5XX_VSC_PIPE_DATA_ADDRESS(i0) (0x00000be0 + 0x2*(i0))
-
-static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
-
-static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; }
-
-#define REG_A5XX_VSC_PIPE_DATA_LENGTH(i0) (0x00000c00 + 0x1*(i0))
-
-static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
-
-#define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60
-
-#define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61
-
-#define REG_A5XX_VSC_RESOLVE_CNTL 0x00000cdd
-#define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE 0x80000000
-#define A5XX_VSC_RESOLVE_CNTL_X__MASK 0x00007fff
-#define A5XX_VSC_RESOLVE_CNTL_X__SHIFT 0
-static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val)
-{
- return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK;
-}
-#define A5XX_VSC_RESOLVE_CNTL_Y__MASK 0x7fff0000
-#define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT 16
-static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
-{
- return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK;
-}
-
-#define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81
-
-#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90
-
-#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91
-
-#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92
-
-#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93
-
-#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94
-
-#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95
-
-#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96
-
-#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97
-
-#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98
-
-#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99
-
-#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a
-
-#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b
-
-#define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4
-
-#define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5
-
-#define REG_A5XX_RB_MODE_CNTL 0x00000cc6
-
-#define REG_A5XX_RB_CCU_CNTL 0x00000cc7
-
-#define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0
-
-#define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1
-
-#define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2
-
-#define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3
-
-#define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4
-
-#define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5
-
-#define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6
-
-#define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7
-
-#define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8
-
-#define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9
-
-#define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda
-
-#define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb
-
-#define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0
-
-#define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1
-
-#define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2
-
-#define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3
-
-#define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4
-
-#define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5
-
-#define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec
-
-#define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced
-
-#define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee
-
-#define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef
-
-#define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00
-#define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100
-
-#define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01
-
-#define REG_A5XX_PC_MODE_CNTL 0x00000d02
-
-#define REG_A5XX_PC_INDEX_BUF_LO 0x00000d04
-
-#define REG_A5XX_PC_INDEX_BUF_HI 0x00000d05
-
-#define REG_A5XX_PC_START_INDEX 0x00000d06
-
-#define REG_A5XX_PC_MAX_INDEX 0x00000d07
-
-#define REG_A5XX_PC_TESSFACTOR_ADDR_LO 0x00000d08
-
-#define REG_A5XX_PC_TESSFACTOR_ADDR_HI 0x00000d09
-
-#define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10
-
-#define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11
-
-#define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12
-
-#define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13
-
-#define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14
-
-#define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15
-
-#define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16
-
-#define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17
-
-#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00
-
-#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01
-
-#define REG_A5XX_HLSQ_DBG_ECO_CNTL 0x00000e04
-
-#define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05
-
-#define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06
-
-#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10
-
-#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11
-
-#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12
-
-#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13
-
-#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14
-
-#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15
-
-#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16
-
-#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17
-
-#define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08
-
-#define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00
-
-#define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000
-
-#define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41
-
-#define REG_A5XX_VFD_MODE_CNTL 0x00000e42
-
-#define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50
-
-#define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51
-
-#define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52
-
-#define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53
-
-#define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54
-
-#define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55
-
-#define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56
-
-#define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
-
-#define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
-#define A5XX_VPC_DBG_ECO_CNTL_ALLFLATOPTDIS 0x00000400
-
-#define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
-
-#define REG_A5XX_VPC_MODE_CNTL 0x00000e62
-#define A5XX_VPC_MODE_CNTL_BINNING_PASS 0x00000001
-
-#define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64
-
-#define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65
-
-#define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66
-
-#define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67
-
-#define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80
-
-#define REG_A5XX_UCHE_MODE_CNTL 0x00000e81
-
-#define REG_A5XX_UCHE_SVM_CNTL 0x00000e82
-
-#define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87
-
-#define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88
-
-#define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89
-
-#define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a
-
-#define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b
-
-#define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c
-
-#define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d
-
-#define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e
-
-#define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f
-
-#define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90
-
-#define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91
-
-#define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92
-
-#define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93
-
-#define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94
-
-#define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95
-
-#define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96
-
-#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0
-
-#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1
-
-#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2
-
-#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3
-
-#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4
-
-#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5
-
-#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6
-
-#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7
-
-#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8
-
-#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9
-
-#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa
-
-#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab
-
-#define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1
-
-#define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2
-
-#define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0
-
-#define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1
-
-#define REG_A5XX_SP_MODE_CNTL 0x00000ec2
-
-#define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0
-
-#define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1
-
-#define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2
-
-#define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3
-
-#define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4
-
-#define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5
-
-#define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6
-
-#define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7
-
-#define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8
-
-#define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9
-
-#define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda
-
-#define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb
-
-#define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc
-
-#define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd
-
-#define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede
-
-#define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf
-
-#define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01
-
-#define REG_A5XX_TPL1_MODE_CNTL 0x00000f02
-
-#define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10
-
-#define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11
-
-#define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12
-
-#define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13
-
-#define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14
-
-#define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15
-
-#define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16
-
-#define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17
-
-#define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18
-
-#define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19
-
-#define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a
-
-#define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b
-
-#define REG_A5XX_VBIF_VERSION 0x00003000
-
-#define REG_A5XX_VBIF_CLKON 0x00003001
-
-#define REG_A5XX_VBIF_ABIT_SORT 0x00003028
-
-#define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029
-
-#define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
-
-#define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
-
-#define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
-
-#define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
-
-#define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080
-
-#define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081
-
-#define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
-
-#define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085
-
-#define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086
-
-#define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087
-
-#define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088
-
-#define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c
-
-#define REG_A5XX_VBIF_PERF_CNT_EN0 0x000030c0
-
-#define REG_A5XX_VBIF_PERF_CNT_EN1 0x000030c1
-
-#define REG_A5XX_VBIF_PERF_CNT_EN2 0x000030c2
-
-#define REG_A5XX_VBIF_PERF_CNT_EN3 0x000030c3
-
-#define REG_A5XX_VBIF_PERF_CNT_CLR0 0x000030c8
-
-#define REG_A5XX_VBIF_PERF_CNT_CLR1 0x000030c9
-
-#define REG_A5XX_VBIF_PERF_CNT_CLR2 0x000030ca
-
-#define REG_A5XX_VBIF_PERF_CNT_CLR3 0x000030cb
-
-#define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0
-
-#define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1
-
-#define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2
-
-#define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3
-
-#define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8
-
-#define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9
-
-#define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da
-
-#define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db
-
-#define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0
-
-#define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1
-
-#define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2
-
-#define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3
-
-#define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
-
-#define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
-
-#define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
-
-#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
-
-#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
-
-#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
-
-#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
-
-#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
-
-#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
-
-#define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800
-
-#define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800
-
-#define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840
-
-#define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841
-
-#define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842
-
-#define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843
-
-#define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844
-
-#define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845
-
-#define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846
-
-#define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847
-
-#define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848
-
-#define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849
-
-#define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a
-
-#define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b
-
-#define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c
-
-#define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d
-
-#define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e
-
-#define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f
-
-#define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850
-
-#define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851
-
-#define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852
-
-#define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853
-
-#define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854
-
-#define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855
-
-#define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856
-
-#define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857
-
-#define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858
-
-#define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859
-
-#define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a
-
-#define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b
-
-#define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c
-
-#define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d
-
-#define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e
-
-#define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f
-
-#define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860
-
-#define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861
-
-#define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862
-
-#define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863
-
-#define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864
-
-#define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865
-
-#define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866
-
-#define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867
-
-#define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868
-
-#define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869
-
-#define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a
-
-#define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b
-
-#define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c
-
-#define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d
-
-#define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e
-
-#define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f
-
-#define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870
-
-#define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871
-
-#define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872
-
-#define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873
-
-#define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874
-
-#define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875
-
-#define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876
-
-#define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877
-
-#define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878
-
-#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879
-
-#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a
-
-#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b
-
-#define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c
-
-#define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d
-
-#define REG_A5XX_GPMU_GPMU_SP_CLOCK_CONTROL 0x0000a880
-
-#define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881
-
-#define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886
-
-#define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887
-
-#define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b
-#define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000
-
-#define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d
-#define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000
-
-#define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891
-
-#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892
-
-#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893
-
-#define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894
-
-#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
-
-#define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8
-
-#define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1
-
-#define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6
-
-#define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8
-
-#define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0
-
-#define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1
-
-#define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00
-
-#define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01
-
-#define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02
-
-#define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03
-
-#define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05
-
-#define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06
-
-#define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40
-
-#define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41
-
-#define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42
-
-#define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43
-
-#define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46
-
-#define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60
-
-#define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61
-
-#define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62
-
-#define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80
-
-#define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4
-
-#define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5
-
-#define REG_A5XX_GDPM_CONFIG1 0x0000b80c
-
-#define REG_A5XX_GDPM_CONFIG2 0x0000b80d
-
-#define REG_A5XX_GDPM_INT_EN 0x0000b80f
-
-#define REG_A5XX_GDPM_INT_MASK 0x0000b811
-
-#define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0
-
-#define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a
-
-#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d
-
-#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f
-
-#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421
-
-#define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520
-
-#define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557
-
-#define REG_A5XX_GRAS_CL_CNTL 0x0000e000
-#define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
-
-#define REG_A5XX_GRAS_VS_CL_CNTL 0x0000e001
-#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
-#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0
-static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
-{
- return ((val) << A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
-}
-#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
-#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8
-static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
-{
- return ((val) << A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
-}
-
-#define REG_A5XX_UNKNOWN_E004 0x0000e004
-
-#define REG_A5XX_GRAS_CNTL 0x0000e005
-#define A5XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
-#define A5XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
-#define A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
-#define A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL 0x00000008
-#define A5XX_GRAS_CNTL_IJ_LINEAR_CENTROID 0x00000010
-#define A5XX_GRAS_CNTL_IJ_LINEAR_SAMPLE 0x00000020
-#define A5XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0
-#define A5XX_GRAS_CNTL_COORD_MASK__SHIFT 6
-static inline uint32_t A5XX_GRAS_CNTL_COORD_MASK(uint32_t val)
-{
- return ((val) << A5XX_GRAS_CNTL_COORD_MASK__SHIFT) & A5XX_GRAS_CNTL_COORD_MASK__MASK;
-}
-
-#define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006
-#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
-#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
-static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
-{
- return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
-}
-#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00
-#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
-static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
-{
- return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
-}
-
-#define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010
-#define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
-#define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
-static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val)
-{
- return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
-}
-
-#define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011
-#define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
-#define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
-static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val)
-{
- return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK;
-}
-
-#define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012
-#define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
-#define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
-static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val)
-{
- return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
-}
-
-#define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013
-#define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
-#define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
-static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val)
-{
- return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK;
-}
-
-#define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014
-#define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
-#define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
-static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
-{
- return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
-}
-
-#define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015
-#define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
-#define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
-static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val)
-{
- return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
-}
-
-#define REG_A5XX_GRAS_SU_CNTL 0x0000e090
-#define A5XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
-#define A5XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
-#define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
-#define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
-#define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
-static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
-{
- return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
-}
-#define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
-#define A5XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000
-#define A5XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13
-static inline uint32_t A5XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val)
-{
- return ((val) << A5XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A5XX_GRAS_SU_CNTL_LINE_MODE__MASK;
-}
-
-#define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091
-#define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
-#define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
-static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val)
-{
- return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
-}
-#define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
-#define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
-static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val)
-{
- return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
-}
-
-#define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092
-#define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
-#define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0
-static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val)
-{
- return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK;
-}
-
-#define REG_A5XX_GRAS_SU_LAYERED 0x0000e093
-
-#define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094
-#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
-#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1 0x00000002
-
-#define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095
-#define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
-#define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
-static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
-{
- return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
-}
-
-#define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096
-#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
-#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
-static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
-{
- return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
-}
-
-#define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097
-#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
-#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
-static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
-{
- return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
-}
-
-#define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098
-#define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
-#define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
-static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
-{
- return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
-}
-
-#define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099
-
-#define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0
-#define A5XX_GRAS_SC_CNTL_BINNING_PASS 0x00000001
-#define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000
-
-#define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1
-
-#define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2
-#define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
-#define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
-static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK;
-}
-
-#define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3
-#define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
-#define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
-static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK;
-}
-#define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
-
-#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4
-
-#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa
-#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
-#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff
-#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0
-static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
-{
- return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
-}
-#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000
-#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16
-static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
-{
- return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
-}
-
-#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab
-#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
-#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff
-#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0
-static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
-{
- return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
-}
-#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000
-#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16
-static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
-{
- return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
-}
-
-#define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca
-#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
-#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff
-#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0
-static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
-{
- return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
-}
-#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000
-#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16
-static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
-{
- return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
-}
-
-#define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb
-#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
-#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff
-#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0
-static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
-{
- return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
-}
-#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000
-#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16
-static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
-{
- return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
-}
-
-#define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea
-#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
-#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
-#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
-static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
-{
- return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
-}
-#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
-#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
-static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
-{
- return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
-}
-
-#define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb
-#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
-#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
-#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
-static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
-{
- return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
-}
-#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
-#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
-static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
-{
- return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
-}
-
-#define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100
-#define A5XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
-#define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
-#define A5XX_GRAS_LRZ_CNTL_GREATER 0x00000004
-
-#define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101
-
-#define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102
-
-#define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103
-#define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK 0xffffffff
-#define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT 0
-static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK;
-}
-
-#define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104
-
-#define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105
-
-#define REG_A5XX_RB_CNTL 0x0000e140
-#define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff
-#define A5XX_RB_CNTL_WIDTH__SHIFT 0
-static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK;
-}
-#define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00
-#define A5XX_RB_CNTL_HEIGHT__SHIFT 9
-static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK;
-}
-#define A5XX_RB_CNTL_BYPASS 0x00020000
-
-#define REG_A5XX_RB_RENDER_CNTL 0x0000e141
-#define A5XX_RB_RENDER_CNTL_BINNING_PASS 0x00000001
-#define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040
-#define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE 0x00000080
-#define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
-#define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000
-#define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
-#define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
-static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
-{
- return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
-}
-#define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000
-#define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24
-static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val)
-{
- return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK;
-}
-
-#define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142
-#define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
-#define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
-static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
-}
-
-#define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143
-#define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
-#define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
-static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
-}
-#define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
-
-#define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144
-#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001
-#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002
-#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004
-#define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL 0x00000008
-#define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID 0x00000010
-#define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE 0x00000020
-#define A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0
-#define A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6
-static inline uint32_t A5XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
-{
- return ((val) << A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
-}
-
-#define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145
-#define A5XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
-#define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002
-#define A5XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000004
-
-#define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146
-#define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
-#define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0
-static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val)
-{
- return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK;
-}
-#define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020
-
-#define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147
-#define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
-#define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
-static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
-{
- return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK;
-}
-#define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
-#define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
-static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
-{
- return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK;
-}
-#define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
-#define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
-static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
-{
- return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK;
-}
-#define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
-#define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
-static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
-{
- return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK;
-}
-#define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
-#define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
-static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
-{
- return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK;
-}
-#define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
-#define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
-static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
-{
- return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK;
-}
-#define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
-#define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
-static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
-{
- return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK;
-}
-#define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
-#define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
-static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
-{
- return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK;
-}
-
-#define REG_A5XX_RB_MRT(i0) (0x0000e150 + 0x7*(i0))
-
-static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
-#define A5XX_RB_MRT_CONTROL_BLEND 0x00000001
-#define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002
-#define A5XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004
-#define A5XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078
-#define A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3
-static inline uint32_t A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
-{
- return ((val) << A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A5XX_RB_MRT_CONTROL_ROP_CODE__MASK;
-}
-#define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
-#define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
-static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
-{
- return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
-}
-
-static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; }
-#define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
-#define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
-static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
-{
- return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
-}
-#define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
-#define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
-static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
-{
- return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
-}
-#define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
-#define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
-static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
-{
- return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
-}
-#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
-#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
-static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
-{
- return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
-}
-#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
-#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
-static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
-{
- return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
-}
-#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
-#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
-static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
-{
- return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
-}
-
-static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; }
-#define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
-#define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
-static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
-{
- return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
-}
-#define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
-#define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
-static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val)
-{
- return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
-}
-#define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00001800
-#define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 11
-static inline uint32_t A5XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
-{
- return ((val) << A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
-}
-#define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
-#define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
-static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
-}
-#define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000
-
-static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; }
-#define A5XX_RB_MRT_PITCH__MASK 0xffffffff
-#define A5XX_RB_MRT_PITCH__SHIFT 0
-static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK;
-}
-
-static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; }
-#define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff
-#define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0
-static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK;
-}
-
-static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; }
-
-static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; }
-
-#define REG_A5XX_RB_BLEND_RED 0x0000e1a0
-#define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff
-#define A5XX_RB_BLEND_RED_UINT__SHIFT 0
-static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val)
-{
- return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK;
-}
-#define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
-#define A5XX_RB_BLEND_RED_SINT__SHIFT 8
-static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val)
-{
- return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK;
-}
-#define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
-#define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
-static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
-{
- return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
-}
-
-#define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
-#define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff
-#define A5XX_RB_BLEND_RED_F32__SHIFT 0
-static inline uint32_t A5XX_RB_BLEND_RED_F32(float val)
-{
- return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK;
-}
-
-#define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2
-#define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
-#define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0
-static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val)
-{
- return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK;
-}
-#define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
-#define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8
-static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val)
-{
- return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK;
-}
-#define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
-#define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
-static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
-{
- return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
-}
-
-#define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
-#define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
-#define A5XX_RB_BLEND_GREEN_F32__SHIFT 0
-static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val)
-{
- return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK;
-}
-
-#define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4
-#define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
-#define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0
-static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val)
-{
- return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK;
-}
-#define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
-#define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8
-static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val)
-{
- return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK;
-}
-#define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
-#define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
-static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
-{
- return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
-}
-
-#define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
-#define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
-#define A5XX_RB_BLEND_BLUE_F32__SHIFT 0
-static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val)
-{
- return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK;
-}
-
-#define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6
-#define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
-#define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0
-static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val)
-{
- return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK;
-}
-#define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
-#define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8
-static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)
-{
- return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK;
-}
-#define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
-#define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
-static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
-{
- return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
-}
-
-#define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
-#define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
-#define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0
-static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val)
-{
- return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK;
-}
-
-#define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8
-#define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
-#define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
-static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
-{
- return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
-}
-#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
-#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
-#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
-static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
-{
- return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
-}
-
-#define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9
-#define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
-#define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
-static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
-{
- return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
-}
-#define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
-#define A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
-#define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
-#define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
-static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
-{
- return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
-}
-
-#define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0
-#define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
-#define A5XX_RB_DEPTH_PLANE_CNTL_UNK1 0x00000002
-
-#define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1
-#define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001
-#define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
-#define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
-#define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
-static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
-{
- return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK;
-}
-#define A5XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040
-
-#define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2
-#define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
-#define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
-static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
-{
- return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
-}
-
-#define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3
-
-#define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4
-
-#define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5
-#define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff
-#define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
-static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK;
-}
-
-#define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6
-#define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff
-#define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
-static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
-}
-
-#define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0
-#define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
-#define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
-#define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
-#define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
-#define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
-static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
-{
- return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK;
-}
-#define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
-#define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
-static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
-{
- return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK;
-}
-#define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
-#define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
-static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
-{
- return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK;
-}
-#define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
-#define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
-static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
-{
- return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
-}
-#define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
-#define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
-static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
-{
- return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
-}
-#define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
-#define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
-static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
-{
- return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
-}
-#define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
-#define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
-static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
-{
- return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
-}
-#define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
-#define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
-static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
-{
- return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
-}
-
-#define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1
-#define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
-
-#define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2
-
-#define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3
-
-#define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4
-#define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff
-#define A5XX_RB_STENCIL_PITCH__SHIFT 0
-static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK;
-}
-
-#define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5
-#define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff
-#define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0
-static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK;
-}
-
-#define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6
-#define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
-#define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
-static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
-{
- return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK;
-}
-#define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
-#define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
-static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
-{
- return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK;
-}
-#define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
-#define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
-static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
-{
- return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
-}
-
-#define REG_A5XX_RB_STENCILREFMASK_BF 0x0000e1c7
-#define A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
-#define A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
-static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
-{
- return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
-}
-#define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
-#define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
-static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
-{
- return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
-}
-#define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
-#define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
-static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
-{
- return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
-}
-
-#define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0
-#define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
-#define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff
-#define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0
-static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val)
-{
- return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK;
-}
-#define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000
-#define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16
-static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val)
-{
- return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK;
-}
-
-#define REG_A5XX_RB_SAMPLE_COUNT_CONTROL 0x0000e1d1
-#define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
-
-#define REG_A5XX_RB_BLIT_CNTL 0x0000e210
-#define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000000f
-#define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0
-static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val)
-{
- return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK;
-}
-
-#define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211
-#define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000
-#define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff
-#define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0
-static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val)
-{
- return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK;
-}
-#define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000
-#define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16
-static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val)
-{
- return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK;
-}
-
-#define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212
-#define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000
-#define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff
-#define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0
-static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val)
-{
- return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK;
-}
-#define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000
-#define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16
-static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val)
-{
- return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK;
-}
-
-#define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213
-#define A5XX_RB_RESOLVE_CNTL_3_TILED 0x00000001
-
-#define REG_A5XX_RB_BLIT_DST_LO 0x0000e214
-
-#define REG_A5XX_RB_BLIT_DST_HI 0x0000e215
-
-#define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216
-#define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff
-#define A5XX_RB_BLIT_DST_PITCH__SHIFT 0
-static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK;
-}
-
-#define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217
-#define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff
-#define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
-static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
-}
-
-#define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218
-
-#define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219
-
-#define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a
-
-#define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b
-
-#define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c
-#define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002
-#define A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE 0x00000004
-#define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0
-#define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4
-static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val)
-{
- return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK;
-}
-
-#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240
-
-#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241
-
-#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242
-
-#define REG_A5XX_RB_MRT_FLAG_BUFFER(i0) (0x0000e243 + 0x4*(i0))
-
-static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
-
-static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; }
-
-static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; }
-#define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff
-#define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0
-static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK;
-}
-
-static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; }
-#define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff
-#define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
-static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK;
-}
-
-#define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263
-
-#define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264
-
-#define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265
-#define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff
-#define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0
-static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK;
-}
-
-#define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266
-#define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff
-#define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0
-static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK;
-}
-
-#define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO 0x0000e267
-
-#define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI 0x0000e268
-
-#define REG_A5XX_VPC_CNTL_0 0x0000e280
-#define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f
-#define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0
-static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val)
-{
- return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK;
-}
-#define A5XX_VPC_CNTL_0_VARYING 0x00000800
-
-#define REG_A5XX_VPC_VARYING_INTERP(i0) (0x0000e282 + 0x1*(i0))
-
-static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
-
-#define REG_A5XX_VPC_VARYING_PS_REPL(i0) (0x0000e28a + 0x1*(i0))
-
-static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
-
-#define REG_A5XX_UNKNOWN_E292 0x0000e292
-
-#define REG_A5XX_UNKNOWN_E293 0x0000e293
-
-#define REG_A5XX_VPC_VAR(i0) (0x0000e294 + 0x1*(i0))
-
-static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
-
-#define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
-
-#define REG_A5XX_VPC_CLIP_CNTL 0x0000e29a
-#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
-#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT 0
-static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val)
-{
- return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK;
-}
-#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
-#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
-static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
-{
- return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
-}
-#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
-#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
-static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
-{
- return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
-}
-
-#define REG_A5XX_VPC_PACK 0x0000e29d
-#define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
-#define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0
-static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
-{
- return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK;
-}
-#define A5XX_VPC_PACK_PSIZELOC__MASK 0x0000ff00
-#define A5XX_VPC_PACK_PSIZELOC__SHIFT 8
-static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val)
-{
- return ((val) << A5XX_VPC_PACK_PSIZELOC__SHIFT) & A5XX_VPC_PACK_PSIZELOC__MASK;
-}
-
-#define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0
-
-#define REG_A5XX_VPC_SO_BUF_CNTL 0x0000e2a1
-#define A5XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
-#define A5XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
-#define A5XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
-#define A5XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
-#define A5XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
-
-#define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2
-#define A5XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001
-
-#define REG_A5XX_VPC_SO_CNTL 0x0000e2a3
-#define A5XX_VPC_SO_CNTL_ENABLE 0x00010000
-
-#define REG_A5XX_VPC_SO_PROG 0x0000e2a4
-#define A5XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
-#define A5XX_VPC_SO_PROG_A_BUF__SHIFT 0
-static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val)
-{
- return ((val) << A5XX_VPC_SO_PROG_A_BUF__SHIFT) & A5XX_VPC_SO_PROG_A_BUF__MASK;
-}
-#define A5XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
-#define A5XX_VPC_SO_PROG_A_OFF__SHIFT 2
-static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK;
-}
-#define A5XX_VPC_SO_PROG_A_EN 0x00000800
-#define A5XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
-#define A5XX_VPC_SO_PROG_B_BUF__SHIFT 12
-static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val)
-{
- return ((val) << A5XX_VPC_SO_PROG_B_BUF__SHIFT) & A5XX_VPC_SO_PROG_B_BUF__MASK;
-}
-#define A5XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
-#define A5XX_VPC_SO_PROG_B_OFF__SHIFT 14
-static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK;
-}
-#define A5XX_VPC_SO_PROG_B_EN 0x00800000
-
-#define REG_A5XX_VPC_SO(i0) (0x0000e2a7 + 0x7*(i0))
-
-static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
-
-static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; }
-
-static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; }
-
-static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; }
-
-static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; }
-
-static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; }
-
-static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; }
-
-#define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384
-#define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f
-#define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0
-static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
-{
- return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
-}
-#define A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART 0x00000100
-#define A5XX_PC_PRIMITIVE_CNTL_COUNT_PRIMITIVES 0x00000200
-#define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST 0x00000400
-
-#define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385
-#define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800
-
-#define REG_A5XX_PC_RASTER_CNTL 0x0000e388
-#define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x00000007
-#define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 0
-static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
-{
- return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK;
-}
-#define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000038
-#define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT 3
-static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
-{
- return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK;
-}
-#define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE 0x00000040
-
-#define REG_A5XX_PC_CLIP_CNTL 0x0000e389
-#define A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
-#define A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT 0
-static inline uint32_t A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val)
-{
- return ((val) << A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK;
-}
-
-#define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
-
-#define REG_A5XX_PC_GS_LAYERED 0x0000e38d
-
-#define REG_A5XX_PC_GS_PARAM 0x0000e38e
-#define A5XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
-#define A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
-static inline uint32_t A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
-{
- return ((val) << A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A5XX_PC_GS_PARAM_MAX_VERTICES__MASK;
-}
-#define A5XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
-#define A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
-static inline uint32_t A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
-{
- return ((val) << A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A5XX_PC_GS_PARAM_INVOCATIONS__MASK;
-}
-#define A5XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
-#define A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
-static inline uint32_t A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
-{
- return ((val) << A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A5XX_PC_GS_PARAM_PRIMTYPE__MASK;
-}
-
-#define REG_A5XX_PC_HS_PARAM 0x0000e38f
-#define A5XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
-#define A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
-static inline uint32_t A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
-{
- return ((val) << A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A5XX_PC_HS_PARAM_VERTICES_OUT__MASK;
-}
-#define A5XX_PC_HS_PARAM_SPACING__MASK 0x00600000
-#define A5XX_PC_HS_PARAM_SPACING__SHIFT 21
-static inline uint32_t A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
-{
- return ((val) << A5XX_PC_HS_PARAM_SPACING__SHIFT) & A5XX_PC_HS_PARAM_SPACING__MASK;
-}
-#define A5XX_PC_HS_PARAM_CW 0x00800000
-#define A5XX_PC_HS_PARAM_CONNECTED 0x01000000
-
-#define REG_A5XX_PC_POWER_CNTL 0x0000e3b0
-
-#define REG_A5XX_VFD_CONTROL_0 0x0000e400
-#define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f
-#define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0
-static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
-{
- return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK;
-}
-
-#define REG_A5XX_VFD_CONTROL_1 0x0000e401
-#define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
-#define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
-static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
-{
- return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK;
-}
-#define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
-#define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
-static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
-{
- return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK;
-}
-#define A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000
-#define A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16
-static inline uint32_t A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
-{
- return ((val) << A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
-}
-
-#define REG_A5XX_VFD_CONTROL_2 0x0000e402
-#define A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK 0x000000ff
-#define A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT 0
-static inline uint32_t A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)
-{
- return ((val) << A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK;
-}
-
-#define REG_A5XX_VFD_CONTROL_3 0x0000e403
-#define A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK 0x0000ff00
-#define A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT 8
-static inline uint32_t A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)
-{
- return ((val) << A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK;
-}
-#define A5XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
-#define A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
-static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
-{
- return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSX__MASK;
-}
-#define A5XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
-#define A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
-static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
-{
- return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSY__MASK;
-}
-
-#define REG_A5XX_VFD_CONTROL_4 0x0000e404
-
-#define REG_A5XX_VFD_CONTROL_5 0x0000e405
-
-#define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408
-
-#define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409
-
-#define REG_A5XX_VFD_FETCH(i0) (0x0000e40a + 0x4*(i0))
-
-static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
-
-static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; }
-
-static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; }
-
-static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; }
-
-#define REG_A5XX_VFD_DECODE(i0) (0x0000e48a + 0x2*(i0))
-
-static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
-#define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
-#define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0
-static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val)
-{
- return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK;
-}
-#define A5XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
-#define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000
-#define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
-static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val)
-{
- return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK;
-}
-#define A5XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000
-#define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT 28
-static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK;
-}
-#define A5XX_VFD_DECODE_INSTR_UNK30 0x40000000
-#define A5XX_VFD_DECODE_INSTR_FLOAT 0x80000000
-
-static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; }
-
-#define REG_A5XX_VFD_DEST_CNTL(i0) (0x0000e4ca + 0x1*(i0))
-
-static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
-#define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
-#define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
-static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
-{
- return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
-}
-#define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
-#define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
-static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
-{
- return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
-}
-
-#define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0
-
-#define REG_A5XX_SP_SP_CNTL 0x0000e580
-
-#define REG_A5XX_SP_VS_CONFIG 0x0000e584
-#define A5XX_SP_VS_CONFIG_ENABLED 0x00000001
-#define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
-#define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
-static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
-}
-#define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
-#define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
-static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A5XX_SP_FS_CONFIG 0x0000e585
-#define A5XX_SP_FS_CONFIG_ENABLED 0x00000001
-#define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
-#define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
-static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
-}
-#define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
-#define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
-static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A5XX_SP_HS_CONFIG 0x0000e586
-#define A5XX_SP_HS_CONFIG_ENABLED 0x00000001
-#define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
-#define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
-static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
-}
-#define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
-#define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
-static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A5XX_SP_DS_CONFIG 0x0000e587
-#define A5XX_SP_DS_CONFIG_ENABLED 0x00000001
-#define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
-#define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
-static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
-}
-#define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
-#define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
-static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A5XX_SP_GS_CONFIG 0x0000e588
-#define A5XX_SP_GS_CONFIG_ENABLED 0x00000001
-#define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
-#define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
-static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
-}
-#define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
-#define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
-static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A5XX_SP_CS_CONFIG 0x0000e589
-#define A5XX_SP_CS_CONFIG_ENABLED 0x00000001
-#define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
-#define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
-static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
-}
-#define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
-#define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
-static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a
-
-#define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b
-
-#define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590
-#define A5XX_SP_VS_CTRL_REG0_BUFFER 0x00000004
-#define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00000008
-#define A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 3
-static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
-}
-#define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
-#define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
-static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
-#define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
-static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000
-#define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000
-#define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
-#define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 25
-static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
-{
- return ((val) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
-}
-
-#define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592
-#define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f
-#define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0
-static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
-{
- return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
-}
-
-#define REG_A5XX_SP_VS_OUT(i0) (0x0000e593 + 0x1*(i0))
-
-static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
-#define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
-#define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
-static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
-{
- return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK;
-}
-#define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
-#define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
-static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
-{
- return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
-}
-#define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
-#define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
-static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
-{
- return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK;
-}
-#define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
-#define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
-static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
-{
- return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
-}
-
-#define REG_A5XX_SP_VS_VPC_DST(i0) (0x0000e5a3 + 0x1*(i0))
-
-static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
-#define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
-#define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
-static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
-{
- return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
-}
-#define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
-#define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
-static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
-{
- return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
-}
-#define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
-#define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
-static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
-{
- return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
-}
-#define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
-#define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
-static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
-{
- return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
-}
-
-#define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab
-
-#define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac
-
-#define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad
-
-#define REG_A5XX_SP_VS_PVT_MEM_PARAM 0x0000e5ae
-#define A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
-#define A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
-static inline uint32_t A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
-{
- assert(!(val & 0x1ff));
- return (((val >> 9)) << A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
-}
-#define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
-#define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
-static inline uint32_t A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
-{
- assert(!(val & 0x7ff));
- return (((val >> 11)) << A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
-}
-#define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
-#define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
-static inline uint32_t A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
-{
- return ((val) << A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
-}
-
-#define REG_A5XX_SP_VS_PVT_MEM_ADDR 0x0000e5af
-
-#define REG_A5XX_SP_VS_PVT_MEM_SIZE 0x0000e5b1
-#define A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
-#define A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
-static inline uint32_t A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
-}
-
-#define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0
-#define A5XX_SP_FS_CTRL_REG0_BUFFER 0x00000004
-#define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00000008
-#define A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 3
-static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
-}
-#define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
-#define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
-static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
-#define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
-static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000
-#define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000
-#define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
-#define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 25
-static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
-{
- return ((val) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
-}
-
-#define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2
-
-#define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3
-
-#define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
-
-#define REG_A5XX_SP_FS_PVT_MEM_PARAM 0x0000e5c5
-#define A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
-#define A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
-static inline uint32_t A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
-{
- assert(!(val & 0x1ff));
- return (((val >> 9)) << A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
-}
-#define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
-#define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
-static inline uint32_t A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
-{
- assert(!(val & 0x7ff));
- return (((val >> 11)) << A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
-}
-#define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
-#define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
-static inline uint32_t A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
-{
- return ((val) << A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
-}
-
-#define REG_A5XX_SP_FS_PVT_MEM_ADDR 0x0000e5c6
-
-#define REG_A5XX_SP_FS_PVT_MEM_SIZE 0x0000e5c8
-#define A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
-#define A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
-static inline uint32_t A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
-}
-
-#define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
-#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
-#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
-static inline uint32_t A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
-{
- return ((val) << A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
-}
-#define A5XX_SP_BLEND_CNTL_UNK8 0x00000100
-#define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
-
-#define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca
-#define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
-#define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0
-static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val)
-{
- return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK;
-}
-#define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0
-#define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5
-static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val)
-{
- return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK;
-}
-#define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000
-#define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13
-static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val)
-{
- return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK;
-}
-
-#define REG_A5XX_SP_FS_OUTPUT(i0) (0x0000e5cb + 0x1*(i0))
-
-static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
-#define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
-#define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
-static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
-{
- return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK;
-}
-#define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
-
-#define REG_A5XX_SP_FS_MRT(i0) (0x0000e5d3 + 0x1*(i0))
-
-static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
-#define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
-#define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
-static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)
-{
- return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
-}
-#define A5XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
-#define A5XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
-#define A5XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400
-
-#define REG_A5XX_UNKNOWN_E5DB 0x0000e5db
-
-#define REG_A5XX_SP_CS_CTRL_REG0 0x0000e5f0
-#define A5XX_SP_CS_CTRL_REG0_BUFFER 0x00000004
-#define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00000008
-#define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 3
-static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
-}
-#define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
-#define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
-static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
-#define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
-static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A5XX_SP_CS_CTRL_REG0_VARYING 0x00010000
-#define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00100000
-#define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
-#define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 25
-static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
-{
- return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
-}
-
-#define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2
-
-#define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3
-
-#define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4
-
-#define REG_A5XX_SP_CS_PVT_MEM_PARAM 0x0000e5f5
-#define A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
-#define A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
-static inline uint32_t A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
-{
- assert(!(val & 0x1ff));
- return (((val >> 9)) << A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
-}
-#define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
-#define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
-static inline uint32_t A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
-{
- assert(!(val & 0x7ff));
- return (((val >> 11)) << A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
-}
-#define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
-#define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
-static inline uint32_t A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
-{
- return ((val) << A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
-}
-
-#define REG_A5XX_SP_CS_PVT_MEM_ADDR 0x0000e5f6
-
-#define REG_A5XX_SP_CS_PVT_MEM_SIZE 0x0000e5f8
-#define A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
-#define A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
-static inline uint32_t A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
-}
-
-#define REG_A5XX_SP_HS_CTRL_REG0 0x0000e600
-#define A5XX_SP_HS_CTRL_REG0_BUFFER 0x00000004
-#define A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00000008
-#define A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 3
-static inline uint32_t A5XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
-}
-#define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
-#define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
-static inline uint32_t A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
-#define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
-static inline uint32_t A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A5XX_SP_HS_CTRL_REG0_VARYING 0x00010000
-#define A5XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x00100000
-#define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
-#define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 25
-static inline uint32_t A5XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
-{
- return ((val) << A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
-}
-
-#define REG_A5XX_UNKNOWN_E602 0x0000e602
-
-#define REG_A5XX_SP_HS_OBJ_START_LO 0x0000e603
-
-#define REG_A5XX_SP_HS_OBJ_START_HI 0x0000e604
-
-#define REG_A5XX_SP_HS_PVT_MEM_PARAM 0x0000e605
-#define A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
-#define A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
-static inline uint32_t A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
-{
- assert(!(val & 0x1ff));
- return (((val >> 9)) << A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
-}
-#define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
-#define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
-static inline uint32_t A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
-{
- assert(!(val & 0x7ff));
- return (((val >> 11)) << A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
-}
-#define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
-#define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
-static inline uint32_t A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
-{
- return ((val) << A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
-}
-
-#define REG_A5XX_SP_HS_PVT_MEM_ADDR 0x0000e606
-
-#define REG_A5XX_SP_HS_PVT_MEM_SIZE 0x0000e608
-#define A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
-#define A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
-static inline uint32_t A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
-}
-
-#define REG_A5XX_SP_DS_CTRL_REG0 0x0000e610
-#define A5XX_SP_DS_CTRL_REG0_BUFFER 0x00000004
-#define A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00000008
-#define A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 3
-static inline uint32_t A5XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
-}
-#define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
-#define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
-static inline uint32_t A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
-#define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
-static inline uint32_t A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A5XX_SP_DS_CTRL_REG0_VARYING 0x00010000
-#define A5XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x00100000
-#define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
-#define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 25
-static inline uint32_t A5XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
-{
- return ((val) << A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
-}
-
-#define REG_A5XX_UNKNOWN_E62B 0x0000e62b
-
-#define REG_A5XX_SP_DS_OBJ_START_LO 0x0000e62c
-
-#define REG_A5XX_SP_DS_OBJ_START_HI 0x0000e62d
-
-#define REG_A5XX_SP_DS_PVT_MEM_PARAM 0x0000e62e
-#define A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
-#define A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
-static inline uint32_t A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
-{
- assert(!(val & 0x1ff));
- return (((val >> 9)) << A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
-}
-#define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
-#define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
-static inline uint32_t A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
-{
- assert(!(val & 0x7ff));
- return (((val >> 11)) << A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
-}
-#define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
-#define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
-static inline uint32_t A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
-{
- return ((val) << A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
-}
-
-#define REG_A5XX_SP_DS_PVT_MEM_ADDR 0x0000e62f
-
-#define REG_A5XX_SP_DS_PVT_MEM_SIZE 0x0000e631
-#define A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
-#define A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
-static inline uint32_t A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
-}
-
-#define REG_A5XX_SP_GS_CTRL_REG0 0x0000e640
-#define A5XX_SP_GS_CTRL_REG0_BUFFER 0x00000004
-#define A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00000008
-#define A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 3
-static inline uint32_t A5XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
-}
-#define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
-#define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
-static inline uint32_t A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
-#define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
-static inline uint32_t A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A5XX_SP_GS_CTRL_REG0_VARYING 0x00010000
-#define A5XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x00100000
-#define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
-#define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 25
-static inline uint32_t A5XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
-{
- return ((val) << A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
-}
-
-#define REG_A5XX_UNKNOWN_E65B 0x0000e65b
-
-#define REG_A5XX_SP_GS_OBJ_START_LO 0x0000e65c
-
-#define REG_A5XX_SP_GS_OBJ_START_HI 0x0000e65d
-
-#define REG_A5XX_SP_GS_PVT_MEM_PARAM 0x0000e65e
-#define A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
-#define A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
-static inline uint32_t A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
-{
- assert(!(val & 0x1ff));
- return (((val >> 9)) << A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
-}
-#define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
-#define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
-static inline uint32_t A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
-{
- assert(!(val & 0x7ff));
- return (((val >> 11)) << A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
-}
-#define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
-#define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
-static inline uint32_t A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
-{
- return ((val) << A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
-}
-
-#define REG_A5XX_SP_GS_PVT_MEM_ADDR 0x0000e65f
-
-#define REG_A5XX_SP_GS_PVT_MEM_SIZE 0x0000e661
-#define A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
-#define A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
-static inline uint32_t A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
-}
-
-#define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704
-#define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
-#define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
-static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
-}
-
-#define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705
-#define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
-#define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
-static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
-}
-#define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
-
-#define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000e706
-
-#define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000e707
-
-#define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700
-
-#define REG_A5XX_TPL1_HS_TEX_COUNT 0x0000e701
-
-#define REG_A5XX_TPL1_DS_TEX_COUNT 0x0000e702
-
-#define REG_A5XX_TPL1_GS_TEX_COUNT 0x0000e703
-
-#define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722
-
-#define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723
-
-#define REG_A5XX_TPL1_HS_TEX_SAMP_LO 0x0000e724
-
-#define REG_A5XX_TPL1_HS_TEX_SAMP_HI 0x0000e725
-
-#define REG_A5XX_TPL1_DS_TEX_SAMP_LO 0x0000e726
-
-#define REG_A5XX_TPL1_DS_TEX_SAMP_HI 0x0000e727
-
-#define REG_A5XX_TPL1_GS_TEX_SAMP_LO 0x0000e728
-
-#define REG_A5XX_TPL1_GS_TEX_SAMP_HI 0x0000e729
-
-#define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a
-
-#define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b
-
-#define REG_A5XX_TPL1_HS_TEX_CONST_LO 0x0000e72c
-
-#define REG_A5XX_TPL1_HS_TEX_CONST_HI 0x0000e72d
-
-#define REG_A5XX_TPL1_DS_TEX_CONST_LO 0x0000e72e
-
-#define REG_A5XX_TPL1_DS_TEX_CONST_HI 0x0000e72f
-
-#define REG_A5XX_TPL1_GS_TEX_CONST_LO 0x0000e730
-
-#define REG_A5XX_TPL1_GS_TEX_CONST_HI 0x0000e731
-
-#define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750
-
-#define REG_A5XX_TPL1_CS_TEX_COUNT 0x0000e751
-
-#define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a
-
-#define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b
-
-#define REG_A5XX_TPL1_CS_TEX_SAMP_LO 0x0000e75c
-
-#define REG_A5XX_TPL1_CS_TEX_SAMP_HI 0x0000e75d
-
-#define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e
-
-#define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f
-
-#define REG_A5XX_TPL1_CS_TEX_CONST_LO 0x0000e760
-
-#define REG_A5XX_TPL1_CS_TEX_CONST_HI 0x0000e761
-
-#define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764
-
-#define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784
-#define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000001
-#define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 0
-static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
-}
-#define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK 0x00000004
-#define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT 2
-static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val)
-{
- return ((val) << A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK;
-}
-
-#define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785
-#define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f
-#define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0
-static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK;
-}
-
-#define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786
-#define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
-#define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
-static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
-}
-#define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
-#define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
-static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
-}
-#define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
-#define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
-static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
-}
-#define A5XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000
-#define A5XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24
-static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK;
-}
-
-#define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787
-#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
-#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
-static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
-}
-#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
-#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
-static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
-}
-#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
-#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
-static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
-}
-#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
-#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
-static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
-}
-
-#define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788
-#define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
-#define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
-static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
-}
-#define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
-#define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
-static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
-}
-#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
-#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
-static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
-}
-#define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
-#define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
-static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
-}
-
-#define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a
-
-#define REG_A5XX_HLSQ_VS_CONFIG 0x0000e78b
-#define A5XX_HLSQ_VS_CONFIG_ENABLED 0x00000001
-#define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
-#define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
-static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
-}
-#define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
-#define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
-static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A5XX_HLSQ_FS_CONFIG 0x0000e78c
-#define A5XX_HLSQ_FS_CONFIG_ENABLED 0x00000001
-#define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
-#define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
-static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
-}
-#define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
-#define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
-static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A5XX_HLSQ_HS_CONFIG 0x0000e78d
-#define A5XX_HLSQ_HS_CONFIG_ENABLED 0x00000001
-#define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
-#define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
-static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
-}
-#define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
-#define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
-static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A5XX_HLSQ_DS_CONFIG 0x0000e78e
-#define A5XX_HLSQ_DS_CONFIG_ENABLED 0x00000001
-#define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
-#define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
-static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
-}
-#define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
-#define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
-static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A5XX_HLSQ_GS_CONFIG 0x0000e78f
-#define A5XX_HLSQ_GS_CONFIG_ENABLED 0x00000001
-#define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
-#define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
-static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
-}
-#define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
-#define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
-static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790
-#define A5XX_HLSQ_CS_CONFIG_ENABLED 0x00000001
-#define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
-#define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
-static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
-}
-#define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
-#define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
-static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK;
-}
-
-#define REG_A5XX_HLSQ_VS_CNTL 0x0000e791
-#define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE 0x00000001
-#define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe
-#define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1
-static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK;
-}
-
-#define REG_A5XX_HLSQ_FS_CNTL 0x0000e792
-#define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE 0x00000001
-#define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe
-#define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1
-static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK;
-}
-
-#define REG_A5XX_HLSQ_HS_CNTL 0x0000e793
-#define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE 0x00000001
-#define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe
-#define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1
-static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK;
-}
-
-#define REG_A5XX_HLSQ_DS_CNTL 0x0000e794
-#define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE 0x00000001
-#define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe
-#define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1
-static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK;
-}
-
-#define REG_A5XX_HLSQ_GS_CNTL 0x0000e795
-#define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE 0x00000001
-#define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe
-#define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1
-static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK;
-}
-
-#define REG_A5XX_HLSQ_CS_CNTL 0x0000e796
-#define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE 0x00000001
-#define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe
-#define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1
-static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK;
-}
-
-#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9
-
-#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba
-
-#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb
-
-#define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0
-#define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
-#define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
-static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
-}
-#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
-#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
-static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
-}
-#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
-#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
-static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
-}
-#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
-#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
-static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
-}
-
-#define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1
-#define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff
-#define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0
-static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
-}
-
-#define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2
-#define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff
-#define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0
-static inline uint32_t A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
-}
-
-#define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3
-#define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff
-#define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0
-static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
-}
-
-#define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4
-#define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff
-#define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0
-static inline uint32_t A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
-}
-
-#define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5
-#define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff
-#define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0
-static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
-}
-
-#define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6
-#define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff
-#define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0
-static inline uint32_t A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
-}
-
-#define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7
-#define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
-#define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
-static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
-}
-#define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00
-#define A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8
-static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK0__MASK;
-}
-#define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000
-#define A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16
-static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK1__MASK;
-}
-#define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
-#define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
-static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
-{
- return ((val) << A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
-}
-
-#define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8
-
-#define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0
-
-#define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3
-
-#define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4
-
-#define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5
-
-#define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8
-
-#define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9
-
-#define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca
-
-#define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd
-
-#define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce
-
-#define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf
-
-#define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2
-
-#define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3
-
-#define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4
-
-#define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7
-
-#define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8
-
-#define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9
-
-#define REG_A5XX_HLSQ_CS_CONSTLEN 0x0000e7dc
-
-#define REG_A5XX_HLSQ_CS_INSTRLEN 0x0000e7dd
-
-#define REG_A5XX_RB_2D_BLIT_CNTL 0x00002100
-
-#define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101
-
-#define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102
-
-#define REG_A5XX_RB_2D_SRC_SOLID_DW2 0x00002103
-
-#define REG_A5XX_RB_2D_SRC_SOLID_DW3 0x00002104
-
-#define REG_A5XX_RB_2D_SRC_INFO 0x00002107
-#define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
-#define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
-static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
-{
- return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK;
-}
-#define A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
-#define A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT 8
-static inline uint32_t A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
-{
- return ((val) << A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK;
-}
-#define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
-#define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
-static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK;
-}
-#define A5XX_RB_2D_SRC_INFO_FLAGS 0x00001000
-#define A5XX_RB_2D_SRC_INFO_SRGB 0x00002000
-
-#define REG_A5XX_RB_2D_SRC_LO 0x00002108
-
-#define REG_A5XX_RB_2D_SRC_HI 0x00002109
-
-#define REG_A5XX_RB_2D_SRC_SIZE 0x0000210a
-#define A5XX_RB_2D_SRC_SIZE_PITCH__MASK 0x0000ffff
-#define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0
-static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK;
-}
-#define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000
-#define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16
-static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK;
-}
-
-#define REG_A5XX_RB_2D_DST_INFO 0x00002110
-#define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
-#define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
-static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
-{
- return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
-}
-#define A5XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300
-#define A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8
-static inline uint32_t A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
-{
- return ((val) << A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_DST_INFO_TILE_MODE__MASK;
-}
-#define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
-#define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
-static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
-}
-#define A5XX_RB_2D_DST_INFO_FLAGS 0x00001000
-#define A5XX_RB_2D_DST_INFO_SRGB 0x00002000
-
-#define REG_A5XX_RB_2D_DST_LO 0x00002111
-
-#define REG_A5XX_RB_2D_DST_HI 0x00002112
-
-#define REG_A5XX_RB_2D_DST_SIZE 0x00002113
-#define A5XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff
-#define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0
-static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK;
-}
-#define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000
-#define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16
-static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK;
-}
-
-#define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140
-
-#define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141
-
-#define REG_A5XX_RB_2D_SRC_FLAGS_PITCH 0x00002142
-#define A5XX_RB_2D_SRC_FLAGS_PITCH__MASK 0xffffffff
-#define A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT 0
-static inline uint32_t A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_SRC_FLAGS_PITCH__MASK;
-}
-
-#define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143
-
-#define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
-
-#define REG_A5XX_RB_2D_DST_FLAGS_PITCH 0x00002145
-#define A5XX_RB_2D_DST_FLAGS_PITCH__MASK 0xffffffff
-#define A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0
-static inline uint32_t A5XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_DST_FLAGS_PITCH__MASK;
-}
-
-#define REG_A5XX_GRAS_2D_BLIT_CNTL 0x00002180
-
-#define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181
-#define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
-#define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
-static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
-{
- return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK;
-}
-#define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
-#define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT 8
-static inline uint32_t A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
-{
- return ((val) << A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK;
-}
-#define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
-#define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
-static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK;
-}
-#define A5XX_GRAS_2D_SRC_INFO_FLAGS 0x00001000
-#define A5XX_GRAS_2D_SRC_INFO_SRGB 0x00002000
-
-#define REG_A5XX_GRAS_2D_DST_INFO 0x00002182
-#define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
-#define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
-static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
-{
- return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK;
-}
-#define A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK 0x00000300
-#define A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT 8
-static inline uint32_t A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
-{
- return ((val) << A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK;
-}
-#define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
-#define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10
-static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK;
-}
-#define A5XX_GRAS_2D_DST_INFO_FLAGS 0x00001000
-#define A5XX_GRAS_2D_DST_INFO_SRGB 0x00002000
-
-#define REG_A5XX_UNKNOWN_2184 0x00002184
-
-#define REG_A5XX_TEX_SAMP_0 0x00000000
-#define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
-#define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
-#define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1
-static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val)
-{
- return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK;
-}
-#define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
-#define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3
-static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val)
-{
- return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK;
-}
-#define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
-#define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5
-static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val)
-{
- return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK;
-}
-#define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
-#define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8
-static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val)
-{
- return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK;
-}
-#define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
-#define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11
-static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val)
-{
- return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK;
-}
-#define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
-#define A5XX_TEX_SAMP_0_ANISO__SHIFT 14
-static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val)
-{
- return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK;
-}
-#define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
-#define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
-static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val)
-{
- return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK;
-}
-
-#define REG_A5XX_TEX_SAMP_1 0x00000001
-#define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
-#define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
-static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
-{
- return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
-}
-#define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
-#define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
-#define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
-#define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
-#define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
-static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val)
-{
- return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK;
-}
-#define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
-#define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
-static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
-{
- return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK;
-}
-
-#define REG_A5XX_TEX_SAMP_2 0x00000002
-#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80
-#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7
-static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
-{
- return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
-}
-
-#define REG_A5XX_TEX_SAMP_3 0x00000003
-
-#define REG_A5XX_TEX_CONST_0 0x00000000
-#define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
-#define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0
-static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val)
-{
- return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK;
-}
-#define A5XX_TEX_CONST_0_SRGB 0x00000004
-#define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
-#define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4
-static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val)
-{
- return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK;
-}
-#define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
-#define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
-static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val)
-{
- return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK;
-}
-#define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
-#define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
-static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val)
-{
- return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK;
-}
-#define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
-#define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13
-static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val)
-{
- return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK;
-}
-#define A5XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
-#define A5XX_TEX_CONST_0_MIPLVLS__SHIFT 16
-static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val)
-{
- return ((val) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT) & A5XX_TEX_CONST_0_MIPLVLS__MASK;
-}
-#define A5XX_TEX_CONST_0_SAMPLES__MASK 0x00300000
-#define A5XX_TEX_CONST_0_SAMPLES__SHIFT 20
-static inline uint32_t A5XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A5XX_TEX_CONST_0_SAMPLES__SHIFT) & A5XX_TEX_CONST_0_SAMPLES__MASK;
-}
-#define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000
-#define A5XX_TEX_CONST_0_FMT__SHIFT 22
-static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val)
-{
- return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK;
-}
-#define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000
-#define A5XX_TEX_CONST_0_SWAP__SHIFT 30
-static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK;
-}
-
-#define REG_A5XX_TEX_CONST_1 0x00000001
-#define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
-#define A5XX_TEX_CONST_1_WIDTH__SHIFT 0
-static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val)
-{
- return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK;
-}
-#define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
-#define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15
-static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
-{
- return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK;
-}
-
-#define REG_A5XX_TEX_CONST_2 0x00000002
-#define A5XX_TEX_CONST_2_BUFFER 0x00000010
-#define A5XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
-#define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
-static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
-{
- return ((val) << A5XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A5XX_TEX_CONST_2_PITCHALIGN__MASK;
-}
-#define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
-#define A5XX_TEX_CONST_2_PITCH__SHIFT 7
-static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val)
-{
- return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK;
-}
-#define A5XX_TEX_CONST_2_TYPE__MASK 0xe0000000
-#define A5XX_TEX_CONST_2_TYPE__SHIFT 29
-static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
-{
- return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
-}
-
-#define REG_A5XX_TEX_CONST_3 0x00000003
-#define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
-#define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
-static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
-}
-#define A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000
-#define A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23
-static inline uint32_t A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
-}
-#define A5XX_TEX_CONST_3_TILE_ALL 0x08000000
-#define A5XX_TEX_CONST_3_FLAG 0x10000000
-
-#define REG_A5XX_TEX_CONST_4 0x00000004
-#define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
-#define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5
-static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK;
-}
-
-#define REG_A5XX_TEX_CONST_5 0x00000005
-#define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
-#define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0
-static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val)
-{
- return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK;
-}
-#define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
-#define A5XX_TEX_CONST_5_DEPTH__SHIFT 17
-static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val)
-{
- return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK;
-}
-
-#define REG_A5XX_TEX_CONST_6 0x00000006
-
-#define REG_A5XX_TEX_CONST_7 0x00000007
-
-#define REG_A5XX_TEX_CONST_8 0x00000008
-
-#define REG_A5XX_TEX_CONST_9 0x00000009
-
-#define REG_A5XX_TEX_CONST_10 0x0000000a
-
-#define REG_A5XX_TEX_CONST_11 0x0000000b
-
-#define REG_A5XX_SSBO_0_0 0x00000000
-#define A5XX_SSBO_0_0_BASE_LO__MASK 0xffffffe0
-#define A5XX_SSBO_0_0_BASE_LO__SHIFT 5
-static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A5XX_SSBO_0_0_BASE_LO__SHIFT) & A5XX_SSBO_0_0_BASE_LO__MASK;
-}
-
-#define REG_A5XX_SSBO_0_1 0x00000001
-#define A5XX_SSBO_0_1_PITCH__MASK 0x003fffff
-#define A5XX_SSBO_0_1_PITCH__SHIFT 0
-static inline uint32_t A5XX_SSBO_0_1_PITCH(uint32_t val)
-{
- return ((val) << A5XX_SSBO_0_1_PITCH__SHIFT) & A5XX_SSBO_0_1_PITCH__MASK;
-}
-
-#define REG_A5XX_SSBO_0_2 0x00000002
-#define A5XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000
-#define A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12
-static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A5XX_SSBO_0_2_ARRAY_PITCH__MASK;
-}
-
-#define REG_A5XX_SSBO_0_3 0x00000003
-#define A5XX_SSBO_0_3_CPP__MASK 0x0000003f
-#define A5XX_SSBO_0_3_CPP__SHIFT 0
-static inline uint32_t A5XX_SSBO_0_3_CPP(uint32_t val)
-{
- return ((val) << A5XX_SSBO_0_3_CPP__SHIFT) & A5XX_SSBO_0_3_CPP__MASK;
-}
-
-#define REG_A5XX_SSBO_1_0 0x00000000
-#define A5XX_SSBO_1_0_FMT__MASK 0x0000ff00
-#define A5XX_SSBO_1_0_FMT__SHIFT 8
-static inline uint32_t A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val)
-{
- return ((val) << A5XX_SSBO_1_0_FMT__SHIFT) & A5XX_SSBO_1_0_FMT__MASK;
-}
-#define A5XX_SSBO_1_0_WIDTH__MASK 0xffff0000
-#define A5XX_SSBO_1_0_WIDTH__SHIFT 16
-static inline uint32_t A5XX_SSBO_1_0_WIDTH(uint32_t val)
-{
- return ((val) << A5XX_SSBO_1_0_WIDTH__SHIFT) & A5XX_SSBO_1_0_WIDTH__MASK;
-}
-
-#define REG_A5XX_SSBO_1_1 0x00000001
-#define A5XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff
-#define A5XX_SSBO_1_1_HEIGHT__SHIFT 0
-static inline uint32_t A5XX_SSBO_1_1_HEIGHT(uint32_t val)
-{
- return ((val) << A5XX_SSBO_1_1_HEIGHT__SHIFT) & A5XX_SSBO_1_1_HEIGHT__MASK;
-}
-#define A5XX_SSBO_1_1_DEPTH__MASK 0xffff0000
-#define A5XX_SSBO_1_1_DEPTH__SHIFT 16
-static inline uint32_t A5XX_SSBO_1_1_DEPTH(uint32_t val)
-{
- return ((val) << A5XX_SSBO_1_1_DEPTH__SHIFT) & A5XX_SSBO_1_1_DEPTH__MASK;
-}
-
-#define REG_A5XX_SSBO_2_0 0x00000000
-#define A5XX_SSBO_2_0_BASE_LO__MASK 0xffffffff
-#define A5XX_SSBO_2_0_BASE_LO__SHIFT 0
-static inline uint32_t A5XX_SSBO_2_0_BASE_LO(uint32_t val)
-{
- return ((val) << A5XX_SSBO_2_0_BASE_LO__SHIFT) & A5XX_SSBO_2_0_BASE_LO__MASK;
-}
-
-#define REG_A5XX_SSBO_2_1 0x00000001
-#define A5XX_SSBO_2_1_BASE_HI__MASK 0xffffffff
-#define A5XX_SSBO_2_1_BASE_HI__SHIFT 0
-static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val)
-{
- return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK;
-}
-
-#define REG_A5XX_UBO_0 0x00000000
-#define A5XX_UBO_0_BASE_LO__MASK 0xffffffff
-#define A5XX_UBO_0_BASE_LO__SHIFT 0
-static inline uint32_t A5XX_UBO_0_BASE_LO(uint32_t val)
-{
- return ((val) << A5XX_UBO_0_BASE_LO__SHIFT) & A5XX_UBO_0_BASE_LO__MASK;
-}
-
-#define REG_A5XX_UBO_1 0x00000001
-#define A5XX_UBO_1_BASE_HI__MASK 0x0001ffff
-#define A5XX_UBO_1_BASE_HI__SHIFT 0
-static inline uint32_t A5XX_UBO_1_BASE_HI(uint32_t val)
-{
- return ((val) << A5XX_UBO_1_BASE_HI__SHIFT) & A5XX_UBO_1_BASE_HI__MASK;
-}
-
-#ifdef __cplusplus
-#endif
-
-#endif /* A5XX_XML */
diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
deleted file mode 100644
index 92e23bf2458d..000000000000
--- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
+++ /dev/null
@@ -1,11858 +0,0 @@
-#ifndef A6XX_XML
-#define A6XX_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
-http://gitlab.freedesktop.org/mesa/mesa/
-git clone https://gitlab.freedesktop.org/mesa/mesa.git
-
-The rules-ng-ng source files this header was generated from are:
-
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 243381 bytes, from Sat Feb 24 09:06:40 2024)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85856 bytes, from Fri Feb 23 13:07:00 2024)
-
-Copyright (C) 2013-2024 by the following authors:
-- Rob Clark <robdclark@gmail.com> Rob Clark
-- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-*/
-
-#ifdef __KERNEL__
-#include <linux/bug.h>
-#define assert(x) BUG_ON(!(x))
-#else
-#include <assert.h>
-#endif
-
-#ifdef __cplusplus
-#define __struct_cast(X)
-#else
-#define __struct_cast(X) (struct X)
-#endif
-
-enum a6xx_tile_mode {
- TILE6_LINEAR = 0,
- TILE6_2 = 2,
- TILE6_3 = 3,
-};
-
-enum a6xx_format {
- FMT6_A8_UNORM = 2,
- FMT6_8_UNORM = 3,
- FMT6_8_SNORM = 4,
- FMT6_8_UINT = 5,
- FMT6_8_SINT = 6,
- FMT6_4_4_4_4_UNORM = 8,
- FMT6_5_5_5_1_UNORM = 10,
- FMT6_1_5_5_5_UNORM = 12,
- FMT6_5_6_5_UNORM = 14,
- FMT6_8_8_UNORM = 15,
- FMT6_8_8_SNORM = 16,
- FMT6_8_8_UINT = 17,
- FMT6_8_8_SINT = 18,
- FMT6_L8_A8_UNORM = 19,
- FMT6_16_UNORM = 21,
- FMT6_16_SNORM = 22,
- FMT6_16_FLOAT = 23,
- FMT6_16_UINT = 24,
- FMT6_16_SINT = 25,
- FMT6_8_8_8_UNORM = 33,
- FMT6_8_8_8_SNORM = 34,
- FMT6_8_8_8_UINT = 35,
- FMT6_8_8_8_SINT = 36,
- FMT6_8_8_8_8_UNORM = 48,
- FMT6_8_8_8_X8_UNORM = 49,
- FMT6_8_8_8_8_SNORM = 50,
- FMT6_8_8_8_8_UINT = 51,
- FMT6_8_8_8_8_SINT = 52,
- FMT6_9_9_9_E5_FLOAT = 53,
- FMT6_10_10_10_2_UNORM = 54,
- FMT6_10_10_10_2_UNORM_DEST = 55,
- FMT6_10_10_10_2_SNORM = 57,
- FMT6_10_10_10_2_UINT = 58,
- FMT6_10_10_10_2_SINT = 59,
- FMT6_11_11_10_FLOAT = 66,
- FMT6_16_16_UNORM = 67,
- FMT6_16_16_SNORM = 68,
- FMT6_16_16_FLOAT = 69,
- FMT6_16_16_UINT = 70,
- FMT6_16_16_SINT = 71,
- FMT6_32_UNORM = 72,
- FMT6_32_SNORM = 73,
- FMT6_32_FLOAT = 74,
- FMT6_32_UINT = 75,
- FMT6_32_SINT = 76,
- FMT6_32_FIXED = 77,
- FMT6_16_16_16_UNORM = 88,
- FMT6_16_16_16_SNORM = 89,
- FMT6_16_16_16_FLOAT = 90,
- FMT6_16_16_16_UINT = 91,
- FMT6_16_16_16_SINT = 92,
- FMT6_16_16_16_16_UNORM = 96,
- FMT6_16_16_16_16_SNORM = 97,
- FMT6_16_16_16_16_FLOAT = 98,
- FMT6_16_16_16_16_UINT = 99,
- FMT6_16_16_16_16_SINT = 100,
- FMT6_32_32_UNORM = 101,
- FMT6_32_32_SNORM = 102,
- FMT6_32_32_FLOAT = 103,
- FMT6_32_32_UINT = 104,
- FMT6_32_32_SINT = 105,
- FMT6_32_32_FIXED = 106,
- FMT6_32_32_32_UNORM = 112,
- FMT6_32_32_32_SNORM = 113,
- FMT6_32_32_32_UINT = 114,
- FMT6_32_32_32_SINT = 115,
- FMT6_32_32_32_FLOAT = 116,
- FMT6_32_32_32_FIXED = 117,
- FMT6_32_32_32_32_UNORM = 128,
- FMT6_32_32_32_32_SNORM = 129,
- FMT6_32_32_32_32_FLOAT = 130,
- FMT6_32_32_32_32_UINT = 131,
- FMT6_32_32_32_32_SINT = 132,
- FMT6_32_32_32_32_FIXED = 133,
- FMT6_G8R8B8R8_422_UNORM = 140,
- FMT6_R8G8R8B8_422_UNORM = 141,
- FMT6_R8_G8B8_2PLANE_420_UNORM = 142,
- FMT6_NV21 = 143,
- FMT6_R8_G8_B8_3PLANE_420_UNORM = 144,
- FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145,
- FMT6_NV12_Y = 148,
- FMT6_NV12_UV = 149,
- FMT6_NV12_VU = 150,
- FMT6_NV12_4R = 151,
- FMT6_NV12_4R_Y = 152,
- FMT6_NV12_4R_UV = 153,
- FMT6_P010 = 154,
- FMT6_P010_Y = 155,
- FMT6_P010_UV = 156,
- FMT6_TP10 = 157,
- FMT6_TP10_Y = 158,
- FMT6_TP10_UV = 159,
- FMT6_Z24_UNORM_S8_UINT = 160,
- FMT6_ETC2_RG11_UNORM = 171,
- FMT6_ETC2_RG11_SNORM = 172,
- FMT6_ETC2_R11_UNORM = 173,
- FMT6_ETC2_R11_SNORM = 174,
- FMT6_ETC1 = 175,
- FMT6_ETC2_RGB8 = 176,
- FMT6_ETC2_RGBA8 = 177,
- FMT6_ETC2_RGB8A1 = 178,
- FMT6_DXT1 = 179,
- FMT6_DXT3 = 180,
- FMT6_DXT5 = 181,
- FMT6_RGTC1_UNORM = 183,
- FMT6_RGTC1_SNORM = 184,
- FMT6_RGTC2_UNORM = 187,
- FMT6_RGTC2_SNORM = 188,
- FMT6_BPTC_UFLOAT = 190,
- FMT6_BPTC_FLOAT = 191,
- FMT6_BPTC = 192,
- FMT6_ASTC_4x4 = 193,
- FMT6_ASTC_5x4 = 194,
- FMT6_ASTC_5x5 = 195,
- FMT6_ASTC_6x5 = 196,
- FMT6_ASTC_6x6 = 197,
- FMT6_ASTC_8x5 = 198,
- FMT6_ASTC_8x6 = 199,
- FMT6_ASTC_8x8 = 200,
- FMT6_ASTC_10x5 = 201,
- FMT6_ASTC_10x6 = 202,
- FMT6_ASTC_10x8 = 203,
- FMT6_ASTC_10x10 = 204,
- FMT6_ASTC_12x10 = 205,
- FMT6_ASTC_12x12 = 206,
- FMT6_Z24_UINT_S8_UINT = 234,
- FMT6_NONE = 255,
-};
-
-enum a6xx_polygon_mode {
- POLYMODE6_POINTS = 1,
- POLYMODE6_LINES = 2,
- POLYMODE6_TRIANGLES = 3,
-};
-
-enum a6xx_depth_format {
- DEPTH6_NONE = 0,
- DEPTH6_16 = 1,
- DEPTH6_24_8 = 2,
- DEPTH6_32 = 4,
-};
-
-enum a6xx_shader_id {
- A6XX_TP0_TMO_DATA = 9,
- A6XX_TP0_SMO_DATA = 10,
- A6XX_TP0_MIPMAP_BASE_DATA = 11,
- A6XX_TP1_TMO_DATA = 25,
- A6XX_TP1_SMO_DATA = 26,
- A6XX_TP1_MIPMAP_BASE_DATA = 27,
- A6XX_SP_INST_DATA = 41,
- A6XX_SP_LB_0_DATA = 42,
- A6XX_SP_LB_1_DATA = 43,
- A6XX_SP_LB_2_DATA = 44,
- A6XX_SP_LB_3_DATA = 45,
- A6XX_SP_LB_4_DATA = 46,
- A6XX_SP_LB_5_DATA = 47,
- A6XX_SP_CB_BINDLESS_DATA = 48,
- A6XX_SP_CB_LEGACY_DATA = 49,
- A6XX_SP_UAV_DATA = 50,
- A6XX_SP_INST_TAG = 51,
- A6XX_SP_CB_BINDLESS_TAG = 52,
- A6XX_SP_TMO_UMO_TAG = 53,
- A6XX_SP_SMO_TAG = 54,
- A6XX_SP_STATE_DATA = 55,
- A6XX_HLSQ_CHUNK_CVS_RAM = 73,
- A6XX_HLSQ_CHUNK_CPS_RAM = 74,
- A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75,
- A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76,
- A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77,
- A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78,
- A6XX_HLSQ_CVS_MISC_RAM = 80,
- A6XX_HLSQ_CPS_MISC_RAM = 81,
- A6XX_HLSQ_INST_RAM = 82,
- A6XX_HLSQ_GFX_CVS_CONST_RAM = 83,
- A6XX_HLSQ_GFX_CPS_CONST_RAM = 84,
- A6XX_HLSQ_CVS_MISC_RAM_TAG = 85,
- A6XX_HLSQ_CPS_MISC_RAM_TAG = 86,
- A6XX_HLSQ_INST_RAM_TAG = 87,
- A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88,
- A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89,
- A6XX_HLSQ_PWR_REST_RAM = 90,
- A6XX_HLSQ_PWR_REST_TAG = 91,
- A6XX_HLSQ_DATAPATH_META = 96,
- A6XX_HLSQ_FRONTEND_META = 97,
- A6XX_HLSQ_INDIRECT_META = 98,
- A6XX_HLSQ_BACKEND_META = 99,
- A6XX_SP_LB_6_DATA = 112,
- A6XX_SP_LB_7_DATA = 113,
- A6XX_HLSQ_INST_RAM_1 = 115,
-};
-
-enum a7xx_statetype_id {
- A7XX_TP0_NCTX_REG = 0,
- A7XX_TP0_CTX0_3D_CVS_REG = 1,
- A7XX_TP0_CTX0_3D_CPS_REG = 2,
- A7XX_TP0_CTX1_3D_CVS_REG = 3,
- A7XX_TP0_CTX1_3D_CPS_REG = 4,
- A7XX_TP0_CTX2_3D_CPS_REG = 5,
- A7XX_TP0_CTX3_3D_CPS_REG = 6,
- A7XX_TP0_TMO_DATA = 9,
- A7XX_TP0_SMO_DATA = 10,
- A7XX_TP0_MIPMAP_BASE_DATA = 11,
- A7XX_SP_NCTX_REG = 32,
- A7XX_SP_CTX0_3D_CVS_REG = 33,
- A7XX_SP_CTX0_3D_CPS_REG = 34,
- A7XX_SP_CTX1_3D_CVS_REG = 35,
- A7XX_SP_CTX1_3D_CPS_REG = 36,
- A7XX_SP_CTX2_3D_CPS_REG = 37,
- A7XX_SP_CTX3_3D_CPS_REG = 38,
- A7XX_SP_INST_DATA = 39,
- A7XX_SP_INST_DATA_1 = 40,
- A7XX_SP_LB_0_DATA = 41,
- A7XX_SP_LB_1_DATA = 42,
- A7XX_SP_LB_2_DATA = 43,
- A7XX_SP_LB_3_DATA = 44,
- A7XX_SP_LB_4_DATA = 45,
- A7XX_SP_LB_5_DATA = 46,
- A7XX_SP_LB_6_DATA = 47,
- A7XX_SP_LB_7_DATA = 48,
- A7XX_SP_CB_RAM = 49,
- A7XX_SP_LB_13_DATA = 50,
- A7XX_SP_LB_14_DATA = 51,
- A7XX_SP_INST_TAG = 52,
- A7XX_SP_INST_DATA_2 = 53,
- A7XX_SP_TMO_TAG = 54,
- A7XX_SP_SMO_TAG = 55,
- A7XX_SP_STATE_DATA = 56,
- A7XX_SP_HWAVE_RAM = 57,
- A7XX_SP_L0_INST_BUF = 58,
- A7XX_SP_LB_8_DATA = 59,
- A7XX_SP_LB_9_DATA = 60,
- A7XX_SP_LB_10_DATA = 61,
- A7XX_SP_LB_11_DATA = 62,
- A7XX_SP_LB_12_DATA = 63,
- A7XX_HLSQ_DATAPATH_DSTR_META = 64,
- A7XX_HLSQ_L2STC_TAG_RAM = 67,
- A7XX_HLSQ_L2STC_INFO_CMD = 68,
- A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG = 69,
- A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG = 70,
- A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM = 71,
- A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM = 72,
- A7XX_HLSQ_CHUNK_CVS_RAM = 73,
- A7XX_HLSQ_CHUNK_CPS_RAM = 74,
- A7XX_HLSQ_CHUNK_CVS_RAM_TAG = 75,
- A7XX_HLSQ_CHUNK_CPS_RAM_TAG = 76,
- A7XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77,
- A7XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78,
- A7XX_HLSQ_CVS_MISC_RAM = 79,
- A7XX_HLSQ_CPS_MISC_RAM = 80,
- A7XX_HLSQ_CPS_MISC_RAM_1 = 81,
- A7XX_HLSQ_INST_RAM = 82,
- A7XX_HLSQ_GFX_CVS_CONST_RAM = 83,
- A7XX_HLSQ_GFX_CPS_CONST_RAM = 84,
- A7XX_HLSQ_CVS_MISC_RAM_TAG = 85,
- A7XX_HLSQ_CPS_MISC_RAM_TAG = 86,
- A7XX_HLSQ_INST_RAM_TAG = 87,
- A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88,
- A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89,
- A7XX_HLSQ_GFX_LOCAL_MISC_RAM = 90,
- A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG = 91,
- A7XX_HLSQ_INST_RAM_1 = 92,
- A7XX_HLSQ_STPROC_META = 93,
- A7XX_HLSQ_BV_BE_META = 94,
- A7XX_HLSQ_INST_RAM_2 = 95,
- A7XX_HLSQ_DATAPATH_META = 96,
- A7XX_HLSQ_FRONTEND_META = 97,
- A7XX_HLSQ_INDIRECT_META = 98,
- A7XX_HLSQ_BACKEND_META = 99,
-};
-
-enum a6xx_debugbus_id {
- A6XX_DBGBUS_CP = 1,
- A6XX_DBGBUS_RBBM = 2,
- A6XX_DBGBUS_VBIF = 3,
- A6XX_DBGBUS_HLSQ = 4,
- A6XX_DBGBUS_UCHE = 5,
- A6XX_DBGBUS_DPM = 6,
- A6XX_DBGBUS_TESS = 7,
- A6XX_DBGBUS_PC = 8,
- A6XX_DBGBUS_VFDP = 9,
- A6XX_DBGBUS_VPC = 10,
- A6XX_DBGBUS_TSE = 11,
- A6XX_DBGBUS_RAS = 12,
- A6XX_DBGBUS_VSC = 13,
- A6XX_DBGBUS_COM = 14,
- A6XX_DBGBUS_LRZ = 16,
- A6XX_DBGBUS_A2D = 17,
- A6XX_DBGBUS_CCUFCHE = 18,
- A6XX_DBGBUS_GMU_CX = 19,
- A6XX_DBGBUS_RBP = 20,
- A6XX_DBGBUS_DCS = 21,
- A6XX_DBGBUS_DBGC = 22,
- A6XX_DBGBUS_CX = 23,
- A6XX_DBGBUS_GMU_GX = 24,
- A6XX_DBGBUS_TPFCHE = 25,
- A6XX_DBGBUS_GBIF_GX = 26,
- A6XX_DBGBUS_GPC = 29,
- A6XX_DBGBUS_LARC = 30,
- A6XX_DBGBUS_HLSQ_SPTP = 31,
- A6XX_DBGBUS_RB_0 = 32,
- A6XX_DBGBUS_RB_1 = 33,
- A6XX_DBGBUS_RB_2 = 34,
- A6XX_DBGBUS_UCHE_WRAPPER = 36,
- A6XX_DBGBUS_CCU_0 = 40,
- A6XX_DBGBUS_CCU_1 = 41,
- A6XX_DBGBUS_CCU_2 = 42,
- A6XX_DBGBUS_VFD_0 = 56,
- A6XX_DBGBUS_VFD_1 = 57,
- A6XX_DBGBUS_VFD_2 = 58,
- A6XX_DBGBUS_VFD_3 = 59,
- A6XX_DBGBUS_VFD_4 = 60,
- A6XX_DBGBUS_VFD_5 = 61,
- A6XX_DBGBUS_SP_0 = 64,
- A6XX_DBGBUS_SP_1 = 65,
- A6XX_DBGBUS_SP_2 = 66,
- A6XX_DBGBUS_TPL1_0 = 72,
- A6XX_DBGBUS_TPL1_1 = 73,
- A6XX_DBGBUS_TPL1_2 = 74,
- A6XX_DBGBUS_TPL1_3 = 75,
- A6XX_DBGBUS_TPL1_4 = 76,
- A6XX_DBGBUS_TPL1_5 = 77,
- A6XX_DBGBUS_SPTP_0 = 88,
- A6XX_DBGBUS_SPTP_1 = 89,
- A6XX_DBGBUS_SPTP_2 = 90,
- A6XX_DBGBUS_SPTP_3 = 91,
- A6XX_DBGBUS_SPTP_4 = 92,
- A6XX_DBGBUS_SPTP_5 = 93,
-};
-
-enum a7xx_state_location {
- A7XX_HLSQ_STATE = 0,
- A7XX_HLSQ_DP = 1,
- A7XX_SP_TOP = 2,
- A7XX_USPTP = 3,
-};
-
-enum a7xx_pipe {
- A7XX_PIPE_NONE = 0,
- A7XX_PIPE_BR = 1,
- A7XX_PIPE_BV = 2,
- A7XX_PIPE_LPAC = 3,
-};
-
-enum a7xx_cluster {
- A7XX_CLUSTER_NONE = 0,
- A7XX_CLUSTER_FE = 1,
- A7XX_CLUSTER_SP_VS = 2,
- A7XX_CLUSTER_PC_VS = 3,
- A7XX_CLUSTER_GRAS = 4,
- A7XX_CLUSTER_SP_PS = 5,
- A7XX_CLUSTER_VPC_PS = 6,
- A7XX_CLUSTER_PS = 7,
-};
-
-enum a7xx_debugbus_id {
- A7XX_DBGBUS_CP_0_0 = 1,
- A7XX_DBGBUS_CP_0_1 = 2,
- A7XX_DBGBUS_RBBM = 3,
- A7XX_DBGBUS_GBIF_GX = 5,
- A7XX_DBGBUS_GBIF_CX = 6,
- A7XX_DBGBUS_HLSQ = 7,
- A7XX_DBGBUS_UCHE_0 = 9,
- A7XX_DBGBUS_UCHE_1 = 10,
- A7XX_DBGBUS_TESS_BR = 13,
- A7XX_DBGBUS_TESS_BV = 14,
- A7XX_DBGBUS_PC_BR = 17,
- A7XX_DBGBUS_PC_BV = 18,
- A7XX_DBGBUS_VFDP_BR = 21,
- A7XX_DBGBUS_VFDP_BV = 22,
- A7XX_DBGBUS_VPC_BR = 25,
- A7XX_DBGBUS_VPC_BV = 26,
- A7XX_DBGBUS_TSE_BR = 29,
- A7XX_DBGBUS_TSE_BV = 30,
- A7XX_DBGBUS_RAS_BR = 33,
- A7XX_DBGBUS_RAS_BV = 34,
- A7XX_DBGBUS_VSC = 37,
- A7XX_DBGBUS_COM_0 = 39,
- A7XX_DBGBUS_LRZ_BR = 43,
- A7XX_DBGBUS_LRZ_BV = 44,
- A7XX_DBGBUS_UFC_0 = 47,
- A7XX_DBGBUS_UFC_1 = 48,
- A7XX_DBGBUS_GMU_GX = 55,
- A7XX_DBGBUS_DBGC = 59,
- A7XX_DBGBUS_CX = 60,
- A7XX_DBGBUS_GMU_CX = 61,
- A7XX_DBGBUS_GPC_BR = 62,
- A7XX_DBGBUS_GPC_BV = 63,
- A7XX_DBGBUS_LARC = 66,
- A7XX_DBGBUS_HLSQ_SPTP = 68,
- A7XX_DBGBUS_RB_0 = 70,
- A7XX_DBGBUS_RB_1 = 71,
- A7XX_DBGBUS_RB_2 = 72,
- A7XX_DBGBUS_RB_3 = 73,
- A7XX_DBGBUS_RB_4 = 74,
- A7XX_DBGBUS_RB_5 = 75,
- A7XX_DBGBUS_UCHE_WRAPPER = 102,
- A7XX_DBGBUS_CCU_0 = 106,
- A7XX_DBGBUS_CCU_1 = 107,
- A7XX_DBGBUS_CCU_2 = 108,
- A7XX_DBGBUS_CCU_3 = 109,
- A7XX_DBGBUS_CCU_4 = 110,
- A7XX_DBGBUS_CCU_5 = 111,
- A7XX_DBGBUS_VFD_BR_0 = 138,
- A7XX_DBGBUS_VFD_BR_1 = 139,
- A7XX_DBGBUS_VFD_BR_2 = 140,
- A7XX_DBGBUS_VFD_BR_3 = 141,
- A7XX_DBGBUS_VFD_BR_4 = 142,
- A7XX_DBGBUS_VFD_BR_5 = 143,
- A7XX_DBGBUS_VFD_BR_6 = 144,
- A7XX_DBGBUS_VFD_BR_7 = 145,
- A7XX_DBGBUS_VFD_BV_0 = 202,
- A7XX_DBGBUS_VFD_BV_1 = 203,
- A7XX_DBGBUS_VFD_BV_2 = 204,
- A7XX_DBGBUS_VFD_BV_3 = 205,
- A7XX_DBGBUS_USP_0 = 234,
- A7XX_DBGBUS_USP_1 = 235,
- A7XX_DBGBUS_USP_2 = 236,
- A7XX_DBGBUS_USP_3 = 237,
- A7XX_DBGBUS_USP_4 = 238,
- A7XX_DBGBUS_USP_5 = 239,
- A7XX_DBGBUS_TP_0 = 266,
- A7XX_DBGBUS_TP_1 = 267,
- A7XX_DBGBUS_TP_2 = 268,
- A7XX_DBGBUS_TP_3 = 269,
- A7XX_DBGBUS_TP_4 = 270,
- A7XX_DBGBUS_TP_5 = 271,
- A7XX_DBGBUS_TP_6 = 272,
- A7XX_DBGBUS_TP_7 = 273,
- A7XX_DBGBUS_TP_8 = 274,
- A7XX_DBGBUS_TP_9 = 275,
- A7XX_DBGBUS_TP_10 = 276,
- A7XX_DBGBUS_TP_11 = 277,
- A7XX_DBGBUS_USPTP_0 = 330,
- A7XX_DBGBUS_USPTP_1 = 331,
- A7XX_DBGBUS_USPTP_2 = 332,
- A7XX_DBGBUS_USPTP_3 = 333,
- A7XX_DBGBUS_USPTP_4 = 334,
- A7XX_DBGBUS_USPTP_5 = 335,
- A7XX_DBGBUS_USPTP_6 = 336,
- A7XX_DBGBUS_USPTP_7 = 337,
- A7XX_DBGBUS_USPTP_8 = 338,
- A7XX_DBGBUS_USPTP_9 = 339,
- A7XX_DBGBUS_USPTP_10 = 340,
- A7XX_DBGBUS_USPTP_11 = 341,
- A7XX_DBGBUS_CCHE_0 = 396,
- A7XX_DBGBUS_CCHE_1 = 397,
- A7XX_DBGBUS_CCHE_2 = 398,
- A7XX_DBGBUS_VPC_DSTR_0 = 408,
- A7XX_DBGBUS_VPC_DSTR_1 = 409,
- A7XX_DBGBUS_VPC_DSTR_2 = 410,
- A7XX_DBGBUS_HLSQ_DP_STR_0 = 411,
- A7XX_DBGBUS_HLSQ_DP_STR_1 = 412,
- A7XX_DBGBUS_HLSQ_DP_STR_2 = 413,
- A7XX_DBGBUS_HLSQ_DP_STR_3 = 414,
- A7XX_DBGBUS_HLSQ_DP_STR_4 = 415,
- A7XX_DBGBUS_HLSQ_DP_STR_5 = 416,
- A7XX_DBGBUS_UFC_DSTR_0 = 443,
- A7XX_DBGBUS_UFC_DSTR_1 = 444,
- A7XX_DBGBUS_UFC_DSTR_2 = 445,
- A7XX_DBGBUS_CGC_SUBCORE = 446,
- A7XX_DBGBUS_CGC_CORE = 447,
-};
-
-enum a6xx_cp_perfcounter_select {
- PERF_CP_ALWAYS_COUNT = 0,
- PERF_CP_BUSY_GFX_CORE_IDLE = 1,
- PERF_CP_BUSY_CYCLES = 2,
- PERF_CP_NUM_PREEMPTIONS = 3,
- PERF_CP_PREEMPTION_REACTION_DELAY = 4,
- PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5,
- PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6,
- PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7,
- PERF_CP_PREDICATED_DRAWS_KILLED = 8,
- PERF_CP_MODE_SWITCH = 9,
- PERF_CP_ZPASS_DONE = 10,
- PERF_CP_CONTEXT_DONE = 11,
- PERF_CP_CACHE_FLUSH = 12,
- PERF_CP_LONG_PREEMPTIONS = 13,
- PERF_CP_SQE_I_CACHE_STARVE = 14,
- PERF_CP_SQE_IDLE = 15,
- PERF_CP_SQE_PM4_STARVE_RB_IB = 16,
- PERF_CP_SQE_PM4_STARVE_SDS = 17,
- PERF_CP_SQE_MRB_STARVE = 18,
- PERF_CP_SQE_RRB_STARVE = 19,
- PERF_CP_SQE_VSD_STARVE = 20,
- PERF_CP_VSD_DECODE_STARVE = 21,
- PERF_CP_SQE_PIPE_OUT_STALL = 22,
- PERF_CP_SQE_SYNC_STALL = 23,
- PERF_CP_SQE_PM4_WFI_STALL = 24,
- PERF_CP_SQE_SYS_WFI_STALL = 25,
- PERF_CP_SQE_T4_EXEC = 26,
- PERF_CP_SQE_LOAD_STATE_EXEC = 27,
- PERF_CP_SQE_SAVE_SDS_STATE = 28,
- PERF_CP_SQE_DRAW_EXEC = 29,
- PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30,
- PERF_CP_SQE_EXEC_PROFILED = 31,
- PERF_CP_MEMORY_POOL_EMPTY = 32,
- PERF_CP_MEMORY_POOL_SYNC_STALL = 33,
- PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34,
- PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35,
- PERF_CP_AHB_STALL_SQE_GMU = 36,
- PERF_CP_AHB_STALL_SQE_WR_OTHER = 37,
- PERF_CP_AHB_STALL_SQE_RD_OTHER = 38,
- PERF_CP_CLUSTER0_EMPTY = 39,
- PERF_CP_CLUSTER1_EMPTY = 40,
- PERF_CP_CLUSTER2_EMPTY = 41,
- PERF_CP_CLUSTER3_EMPTY = 42,
- PERF_CP_CLUSTER4_EMPTY = 43,
- PERF_CP_CLUSTER5_EMPTY = 44,
- PERF_CP_PM4_DATA = 45,
- PERF_CP_PM4_HEADERS = 46,
- PERF_CP_VBIF_READ_BEATS = 47,
- PERF_CP_VBIF_WRITE_BEATS = 48,
- PERF_CP_SQE_INSTR_COUNTER = 49,
-};
-
-enum a6xx_rbbm_perfcounter_select {
- PERF_RBBM_ALWAYS_COUNT = 0,
- PERF_RBBM_ALWAYS_ON = 1,
- PERF_RBBM_TSE_BUSY = 2,
- PERF_RBBM_RAS_BUSY = 3,
- PERF_RBBM_PC_DCALL_BUSY = 4,
- PERF_RBBM_PC_VSD_BUSY = 5,
- PERF_RBBM_STATUS_MASKED = 6,
- PERF_RBBM_COM_BUSY = 7,
- PERF_RBBM_DCOM_BUSY = 8,
- PERF_RBBM_VBIF_BUSY = 9,
- PERF_RBBM_VSC_BUSY = 10,
- PERF_RBBM_TESS_BUSY = 11,
- PERF_RBBM_UCHE_BUSY = 12,
- PERF_RBBM_HLSQ_BUSY = 13,
-};
-
-enum a6xx_pc_perfcounter_select {
- PERF_PC_BUSY_CYCLES = 0,
- PERF_PC_WORKING_CYCLES = 1,
- PERF_PC_STALL_CYCLES_VFD = 2,
- PERF_PC_STALL_CYCLES_TSE = 3,
- PERF_PC_STALL_CYCLES_VPC = 4,
- PERF_PC_STALL_CYCLES_UCHE = 5,
- PERF_PC_STALL_CYCLES_TESS = 6,
- PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
- PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
- PERF_PC_PASS1_TF_STALL_CYCLES = 9,
- PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
- PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
- PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
- PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
- PERF_PC_STARVE_CYCLES_DI = 14,
- PERF_PC_VIS_STREAMS_LOADED = 15,
- PERF_PC_INSTANCES = 16,
- PERF_PC_VPC_PRIMITIVES = 17,
- PERF_PC_DEAD_PRIM = 18,
- PERF_PC_LIVE_PRIM = 19,
- PERF_PC_VERTEX_HITS = 20,
- PERF_PC_IA_VERTICES = 21,
- PERF_PC_IA_PRIMITIVES = 22,
- PERF_PC_GS_PRIMITIVES = 23,
- PERF_PC_HS_INVOCATIONS = 24,
- PERF_PC_DS_INVOCATIONS = 25,
- PERF_PC_VS_INVOCATIONS = 26,
- PERF_PC_GS_INVOCATIONS = 27,
- PERF_PC_DS_PRIMITIVES = 28,
- PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
- PERF_PC_3D_DRAWCALLS = 30,
- PERF_PC_2D_DRAWCALLS = 31,
- PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
- PERF_TESS_BUSY_CYCLES = 33,
- PERF_TESS_WORKING_CYCLES = 34,
- PERF_TESS_STALL_CYCLES_PC = 35,
- PERF_TESS_STARVE_CYCLES_PC = 36,
- PERF_PC_TSE_TRANSACTION = 37,
- PERF_PC_TSE_VERTEX = 38,
- PERF_PC_TESS_PC_UV_TRANS = 39,
- PERF_PC_TESS_PC_UV_PATCHES = 40,
- PERF_PC_TESS_FACTOR_TRANS = 41,
-};
-
-enum a6xx_vfd_perfcounter_select {
- PERF_VFD_BUSY_CYCLES = 0,
- PERF_VFD_STALL_CYCLES_UCHE = 1,
- PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
- PERF_VFD_STALL_CYCLES_SP_INFO = 3,
- PERF_VFD_STALL_CYCLES_SP_ATTR = 4,
- PERF_VFD_STARVE_CYCLES_UCHE = 5,
- PERF_VFD_RBUFFER_FULL = 6,
- PERF_VFD_ATTR_INFO_FIFO_FULL = 7,
- PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8,
- PERF_VFD_NUM_ATTRIBUTES = 9,
- PERF_VFD_UPPER_SHADER_FIBERS = 10,
- PERF_VFD_LOWER_SHADER_FIBERS = 11,
- PERF_VFD_MODE_0_FIBERS = 12,
- PERF_VFD_MODE_1_FIBERS = 13,
- PERF_VFD_MODE_2_FIBERS = 14,
- PERF_VFD_MODE_3_FIBERS = 15,
- PERF_VFD_MODE_4_FIBERS = 16,
- PERF_VFD_TOTAL_VERTICES = 17,
- PERF_VFDP_STALL_CYCLES_VFD = 18,
- PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19,
- PERF_VFDP_STALL_CYCLES_VFD_PROG = 20,
- PERF_VFDP_STARVE_CYCLES_PC = 21,
- PERF_VFDP_VS_STAGE_WAVES = 22,
-};
-
-enum a6xx_hlsq_perfcounter_select {
- PERF_HLSQ_BUSY_CYCLES = 0,
- PERF_HLSQ_STALL_CYCLES_UCHE = 1,
- PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
- PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
- PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
- PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
- PERF_HLSQ_FS_STAGE_1X_WAVES = 6,
- PERF_HLSQ_FS_STAGE_2X_WAVES = 7,
- PERF_HLSQ_QUADS = 8,
- PERF_HLSQ_CS_INVOCATIONS = 9,
- PERF_HLSQ_COMPUTE_DRAWCALLS = 10,
- PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11,
- PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12,
- PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13,
- PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14,
- PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15,
- PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16,
- PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17,
- PERF_HLSQ_STALL_CYCLES_VPC = 18,
- PERF_HLSQ_PIXELS = 19,
- PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20,
-};
-
-enum a6xx_vpc_perfcounter_select {
- PERF_VPC_BUSY_CYCLES = 0,
- PERF_VPC_WORKING_CYCLES = 1,
- PERF_VPC_STALL_CYCLES_UCHE = 2,
- PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
- PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
- PERF_VPC_STALL_CYCLES_PC = 5,
- PERF_VPC_STALL_CYCLES_SP_LM = 6,
- PERF_VPC_STARVE_CYCLES_SP = 7,
- PERF_VPC_STARVE_CYCLES_LRZ = 8,
- PERF_VPC_PC_PRIMITIVES = 9,
- PERF_VPC_SP_COMPONENTS = 10,
- PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11,
- PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12,
- PERF_VPC_RB_VISIBLE_PRIMITIVES = 13,
- PERF_VPC_LM_TRANSACTION = 14,
- PERF_VPC_STREAMOUT_TRANSACTION = 15,
- PERF_VPC_VS_BUSY_CYCLES = 16,
- PERF_VPC_PS_BUSY_CYCLES = 17,
- PERF_VPC_VS_WORKING_CYCLES = 18,
- PERF_VPC_PS_WORKING_CYCLES = 19,
- PERF_VPC_STARVE_CYCLES_RB = 20,
- PERF_VPC_NUM_VPCRAM_READ_POS = 21,
- PERF_VPC_WIT_FULL_CYCLES = 22,
- PERF_VPC_VPCRAM_FULL_CYCLES = 23,
- PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24,
- PERF_VPC_NUM_VPCRAM_WRITE = 25,
- PERF_VPC_NUM_VPCRAM_READ_SO = 26,
- PERF_VPC_NUM_ATTR_REQ_LM = 27,
-};
-
-enum a6xx_tse_perfcounter_select {
- PERF_TSE_BUSY_CYCLES = 0,
- PERF_TSE_CLIPPING_CYCLES = 1,
- PERF_TSE_STALL_CYCLES_RAS = 2,
- PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
- PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
- PERF_TSE_STARVE_CYCLES_PC = 5,
- PERF_TSE_INPUT_PRIM = 6,
- PERF_TSE_INPUT_NULL_PRIM = 7,
- PERF_TSE_TRIVAL_REJ_PRIM = 8,
- PERF_TSE_CLIPPED_PRIM = 9,
- PERF_TSE_ZERO_AREA_PRIM = 10,
- PERF_TSE_FACENESS_CULLED_PRIM = 11,
- PERF_TSE_ZERO_PIXEL_PRIM = 12,
- PERF_TSE_OUTPUT_NULL_PRIM = 13,
- PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
- PERF_TSE_CINVOCATION = 15,
- PERF_TSE_CPRIMITIVES = 16,
- PERF_TSE_2D_INPUT_PRIM = 17,
- PERF_TSE_2D_ALIVE_CYCLES = 18,
- PERF_TSE_CLIP_PLANES = 19,
-};
-
-enum a6xx_ras_perfcounter_select {
- PERF_RAS_BUSY_CYCLES = 0,
- PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
- PERF_RAS_STALL_CYCLES_LRZ = 2,
- PERF_RAS_STARVE_CYCLES_TSE = 3,
- PERF_RAS_SUPER_TILES = 4,
- PERF_RAS_8X4_TILES = 5,
- PERF_RAS_MASKGEN_ACTIVE = 6,
- PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
- PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
- PERF_RAS_PRIM_KILLED_INVISILBE = 9,
- PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10,
- PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11,
- PERF_RAS_BLOCKS = 12,
-};
-
-enum a6xx_uche_perfcounter_select {
- PERF_UCHE_BUSY_CYCLES = 0,
- PERF_UCHE_STALL_CYCLES_ARBITER = 1,
- PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
- PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
- PERF_UCHE_VBIF_READ_BEATS_TP = 4,
- PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
- PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
- PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
- PERF_UCHE_VBIF_READ_BEATS_SP = 8,
- PERF_UCHE_READ_REQUESTS_TP = 9,
- PERF_UCHE_READ_REQUESTS_VFD = 10,
- PERF_UCHE_READ_REQUESTS_HLSQ = 11,
- PERF_UCHE_READ_REQUESTS_LRZ = 12,
- PERF_UCHE_READ_REQUESTS_SP = 13,
- PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
- PERF_UCHE_WRITE_REQUESTS_SP = 15,
- PERF_UCHE_WRITE_REQUESTS_VPC = 16,
- PERF_UCHE_WRITE_REQUESTS_VSC = 17,
- PERF_UCHE_EVICTS = 18,
- PERF_UCHE_BANK_REQ0 = 19,
- PERF_UCHE_BANK_REQ1 = 20,
- PERF_UCHE_BANK_REQ2 = 21,
- PERF_UCHE_BANK_REQ3 = 22,
- PERF_UCHE_BANK_REQ4 = 23,
- PERF_UCHE_BANK_REQ5 = 24,
- PERF_UCHE_BANK_REQ6 = 25,
- PERF_UCHE_BANK_REQ7 = 26,
- PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
- PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
- PERF_UCHE_GMEM_READ_BEATS = 29,
- PERF_UCHE_TPH_REF_FULL = 30,
- PERF_UCHE_TPH_VICTIM_FULL = 31,
- PERF_UCHE_TPH_EXT_FULL = 32,
- PERF_UCHE_VBIF_STALL_WRITE_DATA = 33,
- PERF_UCHE_DCMP_LATENCY_SAMPLES = 34,
- PERF_UCHE_DCMP_LATENCY_CYCLES = 35,
- PERF_UCHE_VBIF_READ_BEATS_PC = 36,
- PERF_UCHE_READ_REQUESTS_PC = 37,
- PERF_UCHE_RAM_READ_REQ = 38,
- PERF_UCHE_RAM_WRITE_REQ = 39,
-};
-
-enum a6xx_tp_perfcounter_select {
- PERF_TP_BUSY_CYCLES = 0,
- PERF_TP_STALL_CYCLES_UCHE = 1,
- PERF_TP_LATENCY_CYCLES = 2,
- PERF_TP_LATENCY_TRANS = 3,
- PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
- PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
- PERF_TP_L1_CACHELINE_REQUESTS = 6,
- PERF_TP_L1_CACHELINE_MISSES = 7,
- PERF_TP_SP_TP_TRANS = 8,
- PERF_TP_TP_SP_TRANS = 9,
- PERF_TP_OUTPUT_PIXELS = 10,
- PERF_TP_FILTER_WORKLOAD_16BIT = 11,
- PERF_TP_FILTER_WORKLOAD_32BIT = 12,
- PERF_TP_QUADS_RECEIVED = 13,
- PERF_TP_QUADS_OFFSET = 14,
- PERF_TP_QUADS_SHADOW = 15,
- PERF_TP_QUADS_ARRAY = 16,
- PERF_TP_QUADS_GRADIENT = 17,
- PERF_TP_QUADS_1D = 18,
- PERF_TP_QUADS_2D = 19,
- PERF_TP_QUADS_BUFFER = 20,
- PERF_TP_QUADS_3D = 21,
- PERF_TP_QUADS_CUBE = 22,
- PERF_TP_DIVERGENT_QUADS_RECEIVED = 23,
- PERF_TP_PRT_NON_RESIDENT_EVENTS = 24,
- PERF_TP_OUTPUT_PIXELS_POINT = 25,
- PERF_TP_OUTPUT_PIXELS_BILINEAR = 26,
- PERF_TP_OUTPUT_PIXELS_MIP = 27,
- PERF_TP_OUTPUT_PIXELS_ANISO = 28,
- PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29,
- PERF_TP_FLAG_CACHE_REQUESTS = 30,
- PERF_TP_FLAG_CACHE_MISSES = 31,
- PERF_TP_L1_5_L2_REQUESTS = 32,
- PERF_TP_2D_OUTPUT_PIXELS = 33,
- PERF_TP_2D_OUTPUT_PIXELS_POINT = 34,
- PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35,
- PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36,
- PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37,
- PERF_TP_TPA2TPC_TRANS = 38,
- PERF_TP_L1_MISSES_ASTC_1TILE = 39,
- PERF_TP_L1_MISSES_ASTC_2TILE = 40,
- PERF_TP_L1_MISSES_ASTC_4TILE = 41,
- PERF_TP_L1_5_L2_COMPRESS_REQS = 42,
- PERF_TP_L1_5_L2_COMPRESS_MISS = 43,
- PERF_TP_L1_BANK_CONFLICT = 44,
- PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45,
- PERF_TP_L1_5_MISS_LATENCY_TRANS = 46,
- PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47,
- PERF_TP_FRONTEND_WORKING_CYCLES = 48,
- PERF_TP_L1_TAG_WORKING_CYCLES = 49,
- PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50,
- PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51,
- PERF_TP_BACKEND_WORKING_CYCLES = 52,
- PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53,
- PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54,
- PERF_TP_STARVE_CYCLES_SP = 55,
- PERF_TP_STARVE_CYCLES_UCHE = 56,
-};
-
-enum a6xx_sp_perfcounter_select {
- PERF_SP_BUSY_CYCLES = 0,
- PERF_SP_ALU_WORKING_CYCLES = 1,
- PERF_SP_EFU_WORKING_CYCLES = 2,
- PERF_SP_STALL_CYCLES_VPC = 3,
- PERF_SP_STALL_CYCLES_TP = 4,
- PERF_SP_STALL_CYCLES_UCHE = 5,
- PERF_SP_STALL_CYCLES_RB = 6,
- PERF_SP_NON_EXECUTION_CYCLES = 7,
- PERF_SP_WAVE_CONTEXTS = 8,
- PERF_SP_WAVE_CONTEXT_CYCLES = 9,
- PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
- PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
- PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
- PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
- PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
- PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
- PERF_SP_WAVE_CTRL_CYCLES = 16,
- PERF_SP_WAVE_LOAD_CYCLES = 17,
- PERF_SP_WAVE_EMIT_CYCLES = 18,
- PERF_SP_WAVE_NOP_CYCLES = 19,
- PERF_SP_WAVE_WAIT_CYCLES = 20,
- PERF_SP_WAVE_FETCH_CYCLES = 21,
- PERF_SP_WAVE_IDLE_CYCLES = 22,
- PERF_SP_WAVE_END_CYCLES = 23,
- PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
- PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
- PERF_SP_WAVE_JOIN_CYCLES = 26,
- PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
- PERF_SP_LM_STORE_INSTRUCTIONS = 28,
- PERF_SP_LM_ATOMICS = 29,
- PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
- PERF_SP_GM_STORE_INSTRUCTIONS = 31,
- PERF_SP_GM_ATOMICS = 32,
- PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
- PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34,
- PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35,
- PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36,
- PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37,
- PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38,
- PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39,
- PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40,
- PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41,
- PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42,
- PERF_SP_VS_INSTRUCTIONS = 43,
- PERF_SP_FS_INSTRUCTIONS = 44,
- PERF_SP_ADDR_LOCK_COUNT = 45,
- PERF_SP_UCHE_READ_TRANS = 46,
- PERF_SP_UCHE_WRITE_TRANS = 47,
- PERF_SP_EXPORT_VPC_TRANS = 48,
- PERF_SP_EXPORT_RB_TRANS = 49,
- PERF_SP_PIXELS_KILLED = 50,
- PERF_SP_ICL1_REQUESTS = 51,
- PERF_SP_ICL1_MISSES = 52,
- PERF_SP_HS_INSTRUCTIONS = 53,
- PERF_SP_DS_INSTRUCTIONS = 54,
- PERF_SP_GS_INSTRUCTIONS = 55,
- PERF_SP_CS_INSTRUCTIONS = 56,
- PERF_SP_GPR_READ = 57,
- PERF_SP_GPR_WRITE = 58,
- PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59,
- PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60,
- PERF_SP_LM_BANK_CONFLICTS = 61,
- PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62,
- PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63,
- PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64,
- PERF_SP_LM_WORKING_CYCLES = 65,
- PERF_SP_DISPATCHER_WORKING_CYCLES = 66,
- PERF_SP_SEQUENCER_WORKING_CYCLES = 67,
- PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68,
- PERF_SP_STARVE_CYCLES_HLSQ = 69,
- PERF_SP_NON_EXECUTION_LS_CYCLES = 70,
- PERF_SP_WORKING_EU = 71,
- PERF_SP_ANY_EU_WORKING = 72,
- PERF_SP_WORKING_EU_FS_STAGE = 73,
- PERF_SP_ANY_EU_WORKING_FS_STAGE = 74,
- PERF_SP_WORKING_EU_VS_STAGE = 75,
- PERF_SP_ANY_EU_WORKING_VS_STAGE = 76,
- PERF_SP_WORKING_EU_CS_STAGE = 77,
- PERF_SP_ANY_EU_WORKING_CS_STAGE = 78,
- PERF_SP_GPR_READ_PREFETCH = 79,
- PERF_SP_GPR_READ_CONFLICT = 80,
- PERF_SP_GPR_WRITE_CONFLICT = 81,
- PERF_SP_GM_LOAD_LATENCY_CYCLES = 82,
- PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83,
- PERF_SP_EXECUTABLE_WAVES = 84,
-};
-
-enum a6xx_rb_perfcounter_select {
- PERF_RB_BUSY_CYCLES = 0,
- PERF_RB_STALL_CYCLES_HLSQ = 1,
- PERF_RB_STALL_CYCLES_FIFO0_FULL = 2,
- PERF_RB_STALL_CYCLES_FIFO1_FULL = 3,
- PERF_RB_STALL_CYCLES_FIFO2_FULL = 4,
- PERF_RB_STARVE_CYCLES_SP = 5,
- PERF_RB_STARVE_CYCLES_LRZ_TILE = 6,
- PERF_RB_STARVE_CYCLES_CCU = 7,
- PERF_RB_STARVE_CYCLES_Z_PLANE = 8,
- PERF_RB_STARVE_CYCLES_BARY_PLANE = 9,
- PERF_RB_Z_WORKLOAD = 10,
- PERF_RB_HLSQ_ACTIVE = 11,
- PERF_RB_Z_READ = 12,
- PERF_RB_Z_WRITE = 13,
- PERF_RB_C_READ = 14,
- PERF_RB_C_WRITE = 15,
- PERF_RB_TOTAL_PASS = 16,
- PERF_RB_Z_PASS = 17,
- PERF_RB_Z_FAIL = 18,
- PERF_RB_S_FAIL = 19,
- PERF_RB_BLENDED_FXP_COMPONENTS = 20,
- PERF_RB_BLENDED_FP16_COMPONENTS = 21,
- PERF_RB_PS_INVOCATIONS = 22,
- PERF_RB_2D_ALIVE_CYCLES = 23,
- PERF_RB_2D_STALL_CYCLES_A2D = 24,
- PERF_RB_2D_STARVE_CYCLES_SRC = 25,
- PERF_RB_2D_STARVE_CYCLES_SP = 26,
- PERF_RB_2D_STARVE_CYCLES_DST = 27,
- PERF_RB_2D_VALID_PIXELS = 28,
- PERF_RB_3D_PIXELS = 29,
- PERF_RB_BLENDER_WORKING_CYCLES = 30,
- PERF_RB_ZPROC_WORKING_CYCLES = 31,
- PERF_RB_CPROC_WORKING_CYCLES = 32,
- PERF_RB_SAMPLER_WORKING_CYCLES = 33,
- PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34,
- PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35,
- PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36,
- PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37,
- PERF_RB_STALL_CYCLES_VPC = 38,
- PERF_RB_2D_INPUT_TRANS = 39,
- PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40,
- PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41,
- PERF_RB_BLENDED_FP32_COMPONENTS = 42,
- PERF_RB_COLOR_PIX_TILES = 43,
- PERF_RB_STALL_CYCLES_CCU = 44,
- PERF_RB_EARLY_Z_ARB3_GRANT = 45,
- PERF_RB_LATE_Z_ARB3_GRANT = 46,
- PERF_RB_EARLY_Z_SKIP_GRANT = 47,
-};
-
-enum a6xx_vsc_perfcounter_select {
- PERF_VSC_BUSY_CYCLES = 0,
- PERF_VSC_WORKING_CYCLES = 1,
- PERF_VSC_STALL_CYCLES_UCHE = 2,
- PERF_VSC_EOT_NUM = 3,
- PERF_VSC_INPUT_TILES = 4,
-};
-
-enum a6xx_ccu_perfcounter_select {
- PERF_CCU_BUSY_CYCLES = 0,
- PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
- PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
- PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
- PERF_CCU_DEPTH_BLOCKS = 4,
- PERF_CCU_COLOR_BLOCKS = 5,
- PERF_CCU_DEPTH_BLOCK_HIT = 6,
- PERF_CCU_COLOR_BLOCK_HIT = 7,
- PERF_CCU_PARTIAL_BLOCK_READ = 8,
- PERF_CCU_GMEM_READ = 9,
- PERF_CCU_GMEM_WRITE = 10,
- PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
- PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
- PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
- PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
- PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
- PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16,
- PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17,
- PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18,
- PERF_CCU_COLOR_READ_FLAG0_COUNT = 19,
- PERF_CCU_COLOR_READ_FLAG1_COUNT = 20,
- PERF_CCU_COLOR_READ_FLAG2_COUNT = 21,
- PERF_CCU_COLOR_READ_FLAG3_COUNT = 22,
- PERF_CCU_COLOR_READ_FLAG4_COUNT = 23,
- PERF_CCU_COLOR_READ_FLAG5_COUNT = 24,
- PERF_CCU_COLOR_READ_FLAG6_COUNT = 25,
- PERF_CCU_COLOR_READ_FLAG8_COUNT = 26,
- PERF_CCU_2D_RD_REQ = 27,
- PERF_CCU_2D_WR_REQ = 28,
-};
-
-enum a6xx_lrz_perfcounter_select {
- PERF_LRZ_BUSY_CYCLES = 0,
- PERF_LRZ_STARVE_CYCLES_RAS = 1,
- PERF_LRZ_STALL_CYCLES_RB = 2,
- PERF_LRZ_STALL_CYCLES_VSC = 3,
- PERF_LRZ_STALL_CYCLES_VPC = 4,
- PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
- PERF_LRZ_STALL_CYCLES_UCHE = 6,
- PERF_LRZ_LRZ_READ = 7,
- PERF_LRZ_LRZ_WRITE = 8,
- PERF_LRZ_READ_LATENCY = 9,
- PERF_LRZ_MERGE_CACHE_UPDATING = 10,
- PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
- PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
- PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
- PERF_LRZ_FULL_8X8_TILES = 14,
- PERF_LRZ_PARTIAL_8X8_TILES = 15,
- PERF_LRZ_TILE_KILLED = 16,
- PERF_LRZ_TOTAL_PIXEL = 17,
- PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
- PERF_LRZ_FULLY_COVERED_TILES = 19,
- PERF_LRZ_PARTIAL_COVERED_TILES = 20,
- PERF_LRZ_FEEDBACK_ACCEPT = 21,
- PERF_LRZ_FEEDBACK_DISCARD = 22,
- PERF_LRZ_FEEDBACK_STALL = 23,
- PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24,
- PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25,
- PERF_LRZ_STALL_CYCLES_VC = 26,
- PERF_LRZ_RAS_MASK_TRANS = 27,
-};
-
-enum a6xx_cmp_perfcounter_select {
- PERF_CMPDECMP_STALL_CYCLES_ARB = 0,
- PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
- PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
- PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
- PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
- PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
- PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
- PERF_CMPDECMP_VBIF_READ_DATA = 7,
- PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
- PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
- PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
- PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
- PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
- PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
- PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
- PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15,
- PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16,
- PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17,
- PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18,
- PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19,
- PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20,
- PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21,
- PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22,
- PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23,
- PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24,
- PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25,
- PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26,
- PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27,
- PERF_CMPDECMP_2D_RD_DATA = 28,
- PERF_CMPDECMP_2D_WR_DATA = 29,
- PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30,
- PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31,
- PERF_CMPDECMP_2D_OUTPUT_TRANS = 32,
- PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33,
- PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34,
- PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35,
- PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36,
- PERF_CMPDECMP_2D_BUSY_CYCLES = 37,
- PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38,
- PERF_CMPDECMP_2D_PIXELS = 39,
-};
-
-enum a6xx_2d_ifmt {
- R2D_UNORM8 = 16,
- R2D_INT32 = 7,
- R2D_INT16 = 6,
- R2D_INT8 = 5,
- R2D_FLOAT32 = 4,
- R2D_FLOAT16 = 3,
- R2D_UNORM8_SRGB = 1,
- R2D_RAW = 0,
-};
-
-enum a6xx_ztest_mode {
- A6XX_EARLY_Z = 0,
- A6XX_LATE_Z = 1,
- A6XX_EARLY_LRZ_LATE_Z = 2,
- A6XX_INVALID_ZTEST = 3,
-};
-
-enum a6xx_tess_spacing {
- TESS_EQUAL = 0,
- TESS_FRACTIONAL_ODD = 2,
- TESS_FRACTIONAL_EVEN = 3,
-};
-
-enum a6xx_tess_output {
- TESS_POINTS = 0,
- TESS_LINES = 1,
- TESS_CW_TRIS = 2,
- TESS_CCW_TRIS = 3,
-};
-
-enum a6xx_sequenced_thread_dist {
- DIST_SCREEN_COORD = 0,
- DIST_ALL_TO_RB0 = 1,
-};
-
-enum a6xx_single_prim_mode {
- NO_FLUSH = 0,
- FLUSH_PER_OVERLAP_AND_OVERWRITE = 1,
- FLUSH_PER_OVERLAP = 3,
-};
-
-enum a6xx_raster_mode {
- TYPE_TILED = 0,
- TYPE_WRITER = 1,
-};
-
-enum a6xx_raster_direction {
- LR_TB = 0,
- RL_TB = 1,
- LR_BT = 2,
- RB_BT = 3,
-};
-
-enum a6xx_render_mode {
- RENDERING_PASS = 0,
- BINNING_PASS = 1,
-};
-
-enum a6xx_buffers_location {
- BUFFERS_IN_GMEM = 0,
- BUFFERS_IN_SYSMEM = 3,
-};
-
-enum a6xx_lrz_dir_status {
- LRZ_DIR_LE = 1,
- LRZ_DIR_GE = 2,
- LRZ_DIR_INVALID = 3,
-};
-
-enum a6xx_fragcoord_sample_mode {
- FRAGCOORD_CENTER = 0,
- FRAGCOORD_SAMPLE = 3,
-};
-
-enum a6xx_rotation {
- ROTATE_0 = 0,
- ROTATE_90 = 1,
- ROTATE_180 = 2,
- ROTATE_270 = 3,
- ROTATE_HFLIP = 4,
- ROTATE_VFLIP = 5,
-};
-
-enum a6xx_ccu_cache_size {
- CCU_CACHE_SIZE_FULL = 0,
- CCU_CACHE_SIZE_HALF = 1,
- CCU_CACHE_SIZE_QUARTER = 2,
- CCU_CACHE_SIZE_EIGHTH = 3,
-};
-
-enum a6xx_varying_interp_mode {
- INTERP_SMOOTH = 0,
- INTERP_FLAT = 1,
- INTERP_ZERO = 2,
- INTERP_ONE = 3,
-};
-
-enum a6xx_varying_ps_repl_mode {
- PS_REPL_NONE = 0,
- PS_REPL_S = 1,
- PS_REPL_T = 2,
- PS_REPL_ONE_MINUS_T = 3,
-};
-
-enum a6xx_threadsize {
- THREAD64 = 0,
- THREAD128 = 1,
-};
-
-enum a6xx_bindless_descriptor_size {
- BINDLESS_DESCRIPTOR_16B = 1,
- BINDLESS_DESCRIPTOR_64B = 3,
-};
-
-enum a6xx_isam_mode {
- ISAMMODE_CL = 1,
- ISAMMODE_GL = 2,
-};
-
-enum a7xx_cs_yalign {
- CS_YALIGN_1 = 8,
- CS_YALIGN_2 = 4,
- CS_YALIGN_4 = 2,
- CS_YALIGN_8 = 1,
-};
-
-enum a6xx_tex_filter {
- A6XX_TEX_NEAREST = 0,
- A6XX_TEX_LINEAR = 1,
- A6XX_TEX_ANISO = 2,
- A6XX_TEX_CUBIC = 3,
-};
-
-enum a6xx_tex_clamp {
- A6XX_TEX_REPEAT = 0,
- A6XX_TEX_CLAMP_TO_EDGE = 1,
- A6XX_TEX_MIRROR_REPEAT = 2,
- A6XX_TEX_CLAMP_TO_BORDER = 3,
- A6XX_TEX_MIRROR_CLAMP = 4,
-};
-
-enum a6xx_tex_aniso {
- A6XX_TEX_ANISO_1 = 0,
- A6XX_TEX_ANISO_2 = 1,
- A6XX_TEX_ANISO_4 = 2,
- A6XX_TEX_ANISO_8 = 3,
- A6XX_TEX_ANISO_16 = 4,
-};
-
-enum a6xx_reduction_mode {
- A6XX_REDUCTION_MODE_AVERAGE = 0,
- A6XX_REDUCTION_MODE_MIN = 1,
- A6XX_REDUCTION_MODE_MAX = 2,
-};
-
-enum a6xx_tex_swiz {
- A6XX_TEX_X = 0,
- A6XX_TEX_Y = 1,
- A6XX_TEX_Z = 2,
- A6XX_TEX_W = 3,
- A6XX_TEX_ZERO = 4,
- A6XX_TEX_ONE = 5,
-};
-
-enum a6xx_tex_type {
- A6XX_TEX_1D = 0,
- A6XX_TEX_2D = 1,
- A6XX_TEX_CUBE = 2,
- A6XX_TEX_3D = 3,
- A6XX_TEX_BUFFER = 4,
-};
-
-#define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
-#define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002
-#define A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0 0x00000010
-#define A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1 0x00000020
-#define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040
-#define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
-#define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100
-#define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
-#define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
-#define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
-#define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
-#define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
-#define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
-#define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000
-#define A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT 0x00008000
-#define A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC 0x00010000
-#define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
-#define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
-#define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
-#define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC 0x00200000
-#define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
-#define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000
-#define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
-#define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
-#define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
-#define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
-#define A6XX_RBBM_INT_0_MASK_TSBWRITEERROR 0x10000000
-#define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
-#define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
-
-#define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001
-#define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002
-#define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
-#define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
-#define A6XX_CP_INT_CP_AHB_ERROR 0x00000020
-#define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040
-#define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080
-#define A6XX_CP_INT_CP_OPCODE_ERROR_LPAC 0x00000100
-#define A6XX_CP_INT_CP_UCODE_ERROR_LPAC 0x00000200
-#define A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC 0x00000400
-#define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC 0x00000800
-#define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC 0x00001000
-#define A6XX_CP_INT_CP_OPCODE_ERROR_BV 0x00002000
-#define A6XX_CP_INT_CP_UCODE_ERROR_BV 0x00004000
-#define A6XX_CP_INT_CP_HW_FAULT_ERROR_BV 0x00008000
-#define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV 0x00010000
-#define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV 0x00020000
-
-#define REG_A6XX_CP_RB_BASE 0x00000800
-
-#define REG_A6XX_CP_RB_CNTL 0x00000802
-
-#define REG_A6XX_CP_RB_RPTR_ADDR 0x00000804
-
-#define REG_A6XX_CP_RB_RPTR 0x00000806
-
-#define REG_A6XX_CP_RB_WPTR 0x00000807
-
-#define REG_A6XX_CP_SQE_CNTL 0x00000808
-
-#define REG_A6XX_CP_CP2GMU_STATUS 0x00000812
-#define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001
-
-#define REG_A6XX_CP_HW_FAULT 0x00000821
-
-#define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823
-#define REG_A6XX_CP_PROTECT_STATUS 0x00000824
-
-#define REG_A6XX_CP_STATUS_1 0x00000825
-
-#define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830
-
-#define REG_A6XX_CP_MISC_CNTL 0x00000840
-
-#define REG_A6XX_CP_APRIV_CNTL 0x00000844
-#define A6XX_CP_APRIV_CNTL_CDWRITE 0x00000040
-#define A6XX_CP_APRIV_CNTL_CDREAD 0x00000020
-#define A6XX_CP_APRIV_CNTL_RBRPWB 0x00000008
-#define A6XX_CP_APRIV_CNTL_RBPRIVLEVEL 0x00000004
-#define A6XX_CP_APRIV_CNTL_RBFETCH 0x00000002
-#define A6XX_CP_APRIV_CNTL_ICACHE 0x00000001
-
-#define REG_A6XX_CP_PREEMPT_THRESHOLD 0x000008c0
-
-#define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1
-#define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK 0x000000ff
-#define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT 0
-static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK;
-}
-#define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK 0x0000ff00
-#define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT 8
-static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK;
-}
-#define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000
-#define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16
-static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK;
-}
-#define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000
-#define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24
-static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK;
-}
-
-#define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2
-#define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK 0x000001ff
-#define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0
-static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK;
-}
-#define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000
-#define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16
-static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK;
-}
-
-#define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3
-
-#define REG_A6XX_CP_CHICKEN_DBG 0x00000841
-
-#define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842
-
-#define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843
-
-#define REG_A6XX_CP_PROTECT_CNTL 0x0000084f
-#define A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE 0x00000008
-#define A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN 0x00000002
-#define A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN 0x00000001
-
-#define REG_A6XX_CP_SCRATCH(i0) (0x00000883 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; }
-
-#define REG_A6XX_CP_PROTECT(i0) (0x00000850 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; }
-#define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff
-#define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
-static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
-{
- return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK;
-}
-#define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000
-#define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18
-static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
-{
- return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK;
-}
-#define A6XX_CP_PROTECT_REG_READ 0x80000000
-
-#define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0
-
-#define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO 0x000008a1
-
-#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR 0x000008a3
-
-#define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR 0x000008a5
-
-#define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR 0x000008a7
-
-#define REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS 0x000008ab
-
-#define REG_A6XX_CP_PERFCTR_CP_SEL(i0) (0x000008d0 + 0x1*(i0))
-
-#define REG_A7XX_CP_BV_PERFCTR_CP_SEL(i0) (0x000008e0 + 0x1*(i0))
-
-#define REG_A6XX_CP_CRASH_SCRIPT_BASE 0x00000900
-
-#define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902
-
-#define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903
-
-#define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908
-
-#define REG_A6XX_CP_SQE_STAT_DATA 0x00000909
-
-#define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a
-
-#define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b
-
-#define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c
-
-#define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d
-
-#define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e
-
-#define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f
-
-#define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910
-
-#define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911
-
-#define REG_A6XX_CP_IB1_BASE 0x00000928
-
-#define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a
-
-#define REG_A6XX_CP_IB2_BASE 0x0000092b
-
-#define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d
-
-#define REG_A6XX_CP_SDS_BASE 0x0000092e
-
-#define REG_A6XX_CP_SDS_REM_SIZE 0x00000930
-
-#define REG_A6XX_CP_MRB_BASE 0x00000931
-
-#define REG_A6XX_CP_MRB_REM_SIZE 0x00000933
-
-#define REG_A6XX_CP_VSD_BASE 0x00000934
-
-#define REG_A6XX_CP_ROQ_RB_STAT 0x00000939
-#define A6XX_CP_ROQ_RB_STAT_RPTR__MASK 0x000003ff
-#define A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT 0
-static inline uint32_t A6XX_CP_ROQ_RB_STAT_RPTR(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_RPTR__MASK;
-}
-#define A6XX_CP_ROQ_RB_STAT_WPTR__MASK 0x03ff0000
-#define A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT 16
-static inline uint32_t A6XX_CP_ROQ_RB_STAT_WPTR(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_WPTR__MASK;
-}
-
-#define REG_A6XX_CP_ROQ_IB1_STAT 0x0000093a
-#define A6XX_CP_ROQ_IB1_STAT_RPTR__MASK 0x000003ff
-#define A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT 0
-static inline uint32_t A6XX_CP_ROQ_IB1_STAT_RPTR(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_RPTR__MASK;
-}
-#define A6XX_CP_ROQ_IB1_STAT_WPTR__MASK 0x03ff0000
-#define A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT 16
-static inline uint32_t A6XX_CP_ROQ_IB1_STAT_WPTR(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_WPTR__MASK;
-}
-
-#define REG_A6XX_CP_ROQ_IB2_STAT 0x0000093b
-#define A6XX_CP_ROQ_IB2_STAT_RPTR__MASK 0x000003ff
-#define A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT 0
-static inline uint32_t A6XX_CP_ROQ_IB2_STAT_RPTR(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_RPTR__MASK;
-}
-#define A6XX_CP_ROQ_IB2_STAT_WPTR__MASK 0x03ff0000
-#define A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT 16
-static inline uint32_t A6XX_CP_ROQ_IB2_STAT_WPTR(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_WPTR__MASK;
-}
-
-#define REG_A6XX_CP_ROQ_SDS_STAT 0x0000093c
-#define A6XX_CP_ROQ_SDS_STAT_RPTR__MASK 0x000003ff
-#define A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT 0
-static inline uint32_t A6XX_CP_ROQ_SDS_STAT_RPTR(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_RPTR__MASK;
-}
-#define A6XX_CP_ROQ_SDS_STAT_WPTR__MASK 0x03ff0000
-#define A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT 16
-static inline uint32_t A6XX_CP_ROQ_SDS_STAT_WPTR(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_WPTR__MASK;
-}
-
-#define REG_A6XX_CP_ROQ_MRB_STAT 0x0000093d
-#define A6XX_CP_ROQ_MRB_STAT_RPTR__MASK 0x000003ff
-#define A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT 0
-static inline uint32_t A6XX_CP_ROQ_MRB_STAT_RPTR(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_RPTR__MASK;
-}
-#define A6XX_CP_ROQ_MRB_STAT_WPTR__MASK 0x03ff0000
-#define A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT 16
-static inline uint32_t A6XX_CP_ROQ_MRB_STAT_WPTR(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_WPTR__MASK;
-}
-
-#define REG_A6XX_CP_ROQ_VSD_STAT 0x0000093e
-#define A6XX_CP_ROQ_VSD_STAT_RPTR__MASK 0x000003ff
-#define A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT 0
-static inline uint32_t A6XX_CP_ROQ_VSD_STAT_RPTR(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_RPTR__MASK;
-}
-#define A6XX_CP_ROQ_VSD_STAT_WPTR__MASK 0x03ff0000
-#define A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT 16
-static inline uint32_t A6XX_CP_ROQ_VSD_STAT_WPTR(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_WPTR__MASK;
-}
-
-#define REG_A6XX_CP_IB1_DWORDS 0x00000943
-
-#define REG_A6XX_CP_IB2_DWORDS 0x00000944
-
-#define REG_A6XX_CP_SDS_DWORDS 0x00000945
-
-#define REG_A6XX_CP_MRB_DWORDS 0x00000946
-
-#define REG_A6XX_CP_VSD_DWORDS 0x00000947
-
-#define REG_A6XX_CP_ROQ_AVAIL_RB 0x00000948
-#define A6XX_CP_ROQ_AVAIL_RB_REM__MASK 0xffff0000
-#define A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT 16
-static inline uint32_t A6XX_CP_ROQ_AVAIL_RB_REM(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_RB_REM__MASK;
-}
-
-#define REG_A6XX_CP_ROQ_AVAIL_IB1 0x00000949
-#define A6XX_CP_ROQ_AVAIL_IB1_REM__MASK 0xffff0000
-#define A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT 16
-static inline uint32_t A6XX_CP_ROQ_AVAIL_IB1_REM(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB1_REM__MASK;
-}
-
-#define REG_A6XX_CP_ROQ_AVAIL_IB2 0x0000094a
-#define A6XX_CP_ROQ_AVAIL_IB2_REM__MASK 0xffff0000
-#define A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT 16
-static inline uint32_t A6XX_CP_ROQ_AVAIL_IB2_REM(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB2_REM__MASK;
-}
-
-#define REG_A6XX_CP_ROQ_AVAIL_SDS 0x0000094b
-#define A6XX_CP_ROQ_AVAIL_SDS_REM__MASK 0xffff0000
-#define A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT 16
-static inline uint32_t A6XX_CP_ROQ_AVAIL_SDS_REM(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_SDS_REM__MASK;
-}
-
-#define REG_A6XX_CP_ROQ_AVAIL_MRB 0x0000094c
-#define A6XX_CP_ROQ_AVAIL_MRB_REM__MASK 0xffff0000
-#define A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT 16
-static inline uint32_t A6XX_CP_ROQ_AVAIL_MRB_REM(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_MRB_REM__MASK;
-}
-
-#define REG_A6XX_CP_ROQ_AVAIL_VSD 0x0000094d
-#define A6XX_CP_ROQ_AVAIL_VSD_REM__MASK 0xffff0000
-#define A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT 16
-static inline uint32_t A6XX_CP_ROQ_AVAIL_VSD_REM(uint32_t val)
-{
- return ((val) << A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_VSD_REM__MASK;
-}
-
-#define REG_A6XX_CP_ALWAYS_ON_COUNTER 0x00000980
-
-#define REG_A6XX_CP_AHB_CNTL 0x0000098d
-
-#define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00
-
-#define REG_A7XX_CP_APERTURE_CNTL_HOST 0x00000a00
-#define A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK 0x00003000
-#define A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT 12
-static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_PIPE(enum a7xx_pipe val)
-{
- return ((val) << A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK;
-}
-#define A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK 0x00000700
-#define A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT 8
-static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_CLUSTER(enum a7xx_cluster val)
-{
- return ((val) << A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK;
-}
-#define A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK 0x00000030
-#define A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT 4
-static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_CONTEXT(uint32_t val)
-{
- return ((val) << A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK;
-}
-
-#define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03
-
-#define REG_A7XX_CP_APERTURE_CNTL_CD 0x00000a03
-#define A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK 0x00003000
-#define A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT 12
-static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_PIPE(enum a7xx_pipe val)
-{
- return ((val) << A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK;
-}
-#define A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK 0x00000700
-#define A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT 8
-static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_CLUSTER(enum a7xx_cluster val)
-{
- return ((val) << A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK;
-}
-#define A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK 0x00000030
-#define A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT 4
-static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_CONTEXT(uint32_t val)
-{
- return ((val) << A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK;
-}
-
-#define REG_A7XX_CP_BV_PROTECT_STATUS 0x00000a61
-
-#define REG_A7XX_CP_BV_HW_FAULT 0x00000a64
-
-#define REG_A7XX_CP_BV_DRAW_STATE_ADDR 0x00000a81
-
-#define REG_A7XX_CP_BV_DRAW_STATE_DATA 0x00000a82
-
-#define REG_A7XX_CP_BV_ROQ_DBG_ADDR 0x00000a83
-
-#define REG_A7XX_CP_BV_ROQ_DBG_DATA 0x00000a84
-
-#define REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR 0x00000a85
-
-#define REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA 0x00000a86
-
-#define REG_A7XX_CP_BV_SQE_STAT_ADDR 0x00000a87
-
-#define REG_A7XX_CP_BV_SQE_STAT_DATA 0x00000a88
-
-#define REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR 0x00000a96
-
-#define REG_A7XX_CP_BV_MEM_POOL_DBG_DATA 0x00000a97
-
-#define REG_A7XX_CP_BV_RB_RPTR_ADDR 0x00000a98
-
-#define REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR 0x00000a9a
-
-#define REG_A7XX_CP_RESOURCE_TBL_DBG_DATA 0x00000a9b
-
-#define REG_A7XX_CP_BV_APRIV_CNTL 0x00000ad0
-
-#define REG_A7XX_CP_BV_CHICKEN_DBG 0x00000ada
-
-#define REG_A7XX_CP_LPAC_DRAW_STATE_ADDR 0x00000b0a
-
-#define REG_A7XX_CP_LPAC_DRAW_STATE_DATA 0x00000b0b
-
-#define REG_A7XX_CP_LPAC_ROQ_DBG_ADDR 0x00000b0c
-
-#define REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR 0x00000b27
-
-#define REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA 0x00000b28
-
-#define REG_A7XX_CP_SQE_AC_STAT_ADDR 0x00000b29
-
-#define REG_A7XX_CP_SQE_AC_STAT_DATA 0x00000b2a
-
-#define REG_A7XX_CP_LPAC_APRIV_CNTL 0x00000b31
-
-#define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34
-
-#define REG_A7XX_CP_LPAC_ROQ_DBG_DATA 0x00000b35
-
-#define REG_A7XX_CP_LPAC_FIFO_DBG_DATA 0x00000b36
-
-#define REG_A7XX_CP_LPAC_FIFO_DBG_ADDR 0x00000b40
-
-#define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82
-
-#define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01
-
-#define REG_A6XX_RBBM_GPR0_CNTL 0x00000018
-
-#define REG_A6XX_RBBM_INT_0_STATUS 0x00000201
-#define REG_A6XX_RBBM_STATUS 0x00000210
-#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000
-#define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000
-#define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000
-#define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000
-#define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000
-#define A6XX_RBBM_STATUS_SP_BUSY 0x00040000
-#define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000
-#define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000
-#define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000
-#define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000
-#define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000
-#define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000
-#define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800
-#define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400
-#define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200
-#define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100
-#define A6XX_RBBM_STATUS_RB_BUSY 0x00000080
-#define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040
-#define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020
-#define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010
-#define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008
-#define A6XX_RBBM_STATUS_CP_BUSY 0x00000004
-#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002
-#define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001
-
-#define REG_A6XX_RBBM_STATUS1 0x00000211
-
-#define REG_A6XX_RBBM_STATUS2 0x00000212
-
-#define REG_A6XX_RBBM_STATUS3 0x00000213
-#define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
-
-#define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215
-
-#define REG_A7XX_RBBM_CLOCK_MODE_CP 0x00000260
-
-#define REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ 0x00000284
-
-#define REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS 0x00000285
-
-#define REG_A7XX_RBBM_CLOCK_MODE2_GRAS 0x00000286
-
-#define REG_A7XX_RBBM_CLOCK_MODE_BV_VFD 0x00000287
-
-#define REG_A7XX_RBBM_CLOCK_MODE_BV_GPC 0x00000288
-
-#define REG_A6XX_RBBM_PERFCTR_CP(i0) (0x00000400 + 0x2*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_RBBM(i0) (0x0000041c + 0x2*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_PC(i0) (0x00000424 + 0x2*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_VFD(i0) (0x00000434 + 0x2*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_HLSQ(i0) (0x00000444 + 0x2*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_VPC(i0) (0x00000450 + 0x2*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_CCU(i0) (0x0000045c + 0x2*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_TSE(i0) (0x00000466 + 0x2*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_RAS(i0) (0x0000046e + 0x2*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_UCHE(i0) (0x00000476 + 0x2*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_TP(i0) (0x0000048e + 0x2*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_SP(i0) (0x000004a6 + 0x2*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_RB(i0) (0x000004d6 + 0x2*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_VSC(i0) (0x000004e6 + 0x2*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_LRZ(i0) (0x000004ea + 0x2*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_CMP(i0) (0x000004f2 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_CP(i0) (0x00000300 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_RBBM(i0) (0x0000031c + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_PC(i0) (0x00000324 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_VFD(i0) (0x00000334 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_HLSQ(i0) (0x00000344 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_VPC(i0) (0x00000350 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_CCU(i0) (0x0000035c + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_TSE(i0) (0x00000366 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_RAS(i0) (0x0000036e + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_UCHE(i0) (0x00000376 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_TP(i0) (0x0000038e + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_SP(i0) (0x000003a6 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_RB(i0) (0x000003d6 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_VSC(i0) (0x000003e6 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_LRZ(i0) (0x000003ea + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_CMP(i0) (0x000003f2 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_UFC(i0) (0x000003fa + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR2_HLSQ(i0) (0x00000410 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR2_CP(i0) (0x0000041c + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR2_SP(i0) (0x0000042a + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR2_TP(i0) (0x00000442 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR2_UFC(i0) (0x0000044e + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_BV_PC(i0) (0x00000460 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_BV_VFD(i0) (0x00000470 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_BV_VPC(i0) (0x00000480 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_BV_TSE(i0) (0x0000048c + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_BV_RAS(i0) (0x00000494 + 0x2*(i0))
-
-#define REG_A7XX_RBBM_PERFCTR_BV_LRZ(i0) (0x0000049c + 0x2*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500
-
-#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501
-
-#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502
-
-#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503
-
-#define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504
-
-#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505
-
-#define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506
-
-#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL(i0) (0x00000507 + 0x1*(i0))
-
-#define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b
-
-#define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD 0x0000050e
-
-#define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS 0x0000050f
-
-#define REG_A6XX_RBBM_ISDB_CNT 0x00000533
-
-#define REG_A7XX_RBBM_NC_MODE_CNTL 0x00000534
-
-#define REG_A7XX_RBBM_SNAPSHOT_STATUS 0x00000535
-
-#define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540
-
-#define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541
-
-#define REG_A6XX_RBBM_PRIMCTR_1_LO 0x00000542
-
-#define REG_A6XX_RBBM_PRIMCTR_1_HI 0x00000543
-
-#define REG_A6XX_RBBM_PRIMCTR_2_LO 0x00000544
-
-#define REG_A6XX_RBBM_PRIMCTR_2_HI 0x00000545
-
-#define REG_A6XX_RBBM_PRIMCTR_3_LO 0x00000546
-
-#define REG_A6XX_RBBM_PRIMCTR_3_HI 0x00000547
-
-#define REG_A6XX_RBBM_PRIMCTR_4_LO 0x00000548
-
-#define REG_A6XX_RBBM_PRIMCTR_4_HI 0x00000549
-
-#define REG_A6XX_RBBM_PRIMCTR_5_LO 0x0000054a
-
-#define REG_A6XX_RBBM_PRIMCTR_5_HI 0x0000054b
-
-#define REG_A6XX_RBBM_PRIMCTR_6_LO 0x0000054c
-
-#define REG_A6XX_RBBM_PRIMCTR_6_HI 0x0000054d
-
-#define REG_A6XX_RBBM_PRIMCTR_7_LO 0x0000054e
-
-#define REG_A6XX_RBBM_PRIMCTR_7_HI 0x0000054f
-
-#define REG_A6XX_RBBM_PRIMCTR_8_LO 0x00000550
-
-#define REG_A6XX_RBBM_PRIMCTR_8_HI 0x00000551
-
-#define REG_A6XX_RBBM_PRIMCTR_9_LO 0x00000552
-
-#define REG_A6XX_RBBM_PRIMCTR_9_HI 0x00000553
-
-#define REG_A6XX_RBBM_PRIMCTR_10_LO 0x00000554
-
-#define REG_A6XX_RBBM_PRIMCTR_10_HI 0x00000555
-
-#define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
-
-#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE 0x0000f800
-
-#define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
-
-#define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803
-
-#define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
-
-#define REG_A7XX_RBBM_SECVID_TSB_STATUS 0x0000fc00
-
-#define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010
-
-#define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011
-
-#define REG_A6XX_RBBM_GBIF_HALT 0x00000016
-
-#define REG_A6XX_RBBM_GBIF_HALT_ACK 0x00000017
-
-#define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD 0x0000001c
-#define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x00000001
-
-#define REG_A7XX_RBBM_GBIF_HALT 0x00000016
-
-#define REG_A7XX_RBBM_GBIF_HALT_ACK 0x00000017
-
-#define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f
-
-#define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037
-#define REG_A6XX_RBBM_INT_0_MASK 0x00000038
-#define REG_A7XX_RBBM_INT_2_MASK 0x0000003a
-
-#define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042
-
-#define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043
-
-#define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044
-
-#define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
-
-#define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
-
-#define REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL 0x000000ad
-
-#define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3
-
-#define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4
-
-#define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5
-
-#define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6
-
-#define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb
-
-#define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc
-
-#define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd
-
-#define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be
-
-#define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3
-
-#define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4
-
-#define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5
-
-#define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6
-
-#define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7
-
-#define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8
-
-#define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9
-
-#define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca
-
-#define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb
-
-#define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc
-
-#define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd
-
-#define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce
-
-#define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3
-
-#define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4
-
-#define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5
-
-#define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6
-
-#define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7
-
-#define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8
-
-#define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9
-
-#define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da
-
-#define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db
-
-#define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc
-
-#define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd
-
-#define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de
-
-#define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df
-
-#define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0
-
-#define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1
-
-#define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2
-
-#define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3
-
-#define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4
-
-#define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5
-
-#define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6
-
-#define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7
-
-#define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8
-
-#define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9
-
-#define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea
-
-#define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb
-
-#define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec
-
-#define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed
-
-#define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee
-
-#define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3
-
-#define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4
-
-#define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5
-
-#define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6
-
-#define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb
-
-#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100
-
-#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101
-
-#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102
-
-#define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104
-
-#define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106
-
-#define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109
-
-#define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b
-
-#define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c
-
-#define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d
-
-#define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f
-
-#define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110
-
-#define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112
-
-#define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113
-
-#define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115
-
-#define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119
-
-#define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a
-
-#define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c
-
-#define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d
-
-#define REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD 0x0000011e
-
-#define REG_A7XX_RBBM_CGC_P2S_TRIG_CMD 0x0000011f
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121
-
-#define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122
-
-#define REG_A7XX_RBBM_CGC_P2S_STATUS 0x00000122
-#define A7XX_RBBM_CGC_P2S_STATUS_TXDONE 0x00000001
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_FCHE 0x00000123
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_FCHE 0x00000124
-
-#define REG_A6XX_RBBM_CLOCK_HYST_FCHE 0x00000125
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_MHUB 0x00000126
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_MHUB 0x00000127
-
-#define REG_A6XX_RBBM_CLOCK_HYST_MHUB 0x00000128
-
-#define REG_A6XX_RBBM_CLOCK_DELAY_GLC 0x00000129
-
-#define REG_A6XX_RBBM_CLOCK_HYST_GLC 0x0000012a
-
-#define REG_A6XX_RBBM_CLOCK_CNTL_GLC 0x0000012b
-
-#define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f
-
-#define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603
-#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff
-#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00
-#define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK;
-}
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604
-#define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
-#define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
-#define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
-#define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
-}
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605
-#define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
-#define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
-}
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
-}
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
-}
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
-#define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
-static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
-{
- return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
-}
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f
-
-#define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630
-
-#define REG_A6XX_VSC_PERFCTR_VSC_SEL(i0) (0x00000cd8 + 0x1*(i0))
-
-#define REG_A7XX_VSC_UNKNOWN_0CD8 0x00000cd8
-#define A7XX_VSC_UNKNOWN_0CD8_BINNING 0x00000001
-
-#define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800
-
-#define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000
-
-#define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00
-
-#define REG_A6XX_UCHE_MODE_CNTL 0x00000e01
-
-#define REG_A6XX_UCHE_WRITE_RANGE_MAX 0x00000e05
-
-#define REG_A6XX_UCHE_WRITE_THRU_BASE 0x00000e07
-
-#define REG_A6XX_UCHE_TRAP_BASE 0x00000e09
-
-#define REG_A6XX_UCHE_GMEM_RANGE_MIN 0x00000e0b
-
-#define REG_A6XX_UCHE_GMEM_RANGE_MAX 0x00000e0d
-
-#define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17
-
-#define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18
-
-#define REG_A6XX_UCHE_CLIENT_PF 0x00000e19
-#define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff
-#define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0
-static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val)
-{
- return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK;
-}
-
-#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL(i0) (0x00000e1c + 0x1*(i0))
-
-#define REG_A6XX_UCHE_GBIF_GX_CONFIG 0x00000e3a
-
-#define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c
-
-#define REG_A6XX_VBIF_VERSION 0x00003000
-
-#define REG_A6XX_VBIF_CLKON 0x00003001
-#define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002
-
-#define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
-
-#define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080
-
-#define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081
-
-#define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
-
-#define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085
-
-#define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086
-#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f
-#define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0
-static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val)
-{
- return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK;
-}
-
-#define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087
-
-#define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088
-#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff
-#define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0
-static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
-{
- return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK;
-}
-
-#define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c
-
-#define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0
-
-#define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1
-
-#define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2
-
-#define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3
-
-#define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8
-
-#define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9
-
-#define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da
-
-#define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db
-
-#define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0
-
-#define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1
-
-#define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2
-
-#define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3
-
-#define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
-
-#define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
-
-#define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
-
-#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
-
-#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
-
-#define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
-
-#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
-
-#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
-
-#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
-
-#define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01
-
-#define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02
-
-#define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03
-
-#define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04
-
-#define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05
-
-#define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06
-
-#define REG_A6XX_GBIF_HALT 0x00003c45
-
-#define REG_A6XX_GBIF_HALT_ACK 0x00003c46
-
-#define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0
-
-#define REG_A6XX_GBIF_PERF_PWR_CNT_CLR 0x00003cc1
-
-#define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2
-
-#define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3
-
-#define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4
-
-#define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5
-
-#define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6
-
-#define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7
-
-#define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8
-
-#define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9
-
-#define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca
-
-#define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb
-
-#define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc
-
-#define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd
-
-#define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce
-
-#define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf
-
-#define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0
-
-#define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1
-
-#define REG_A6XX_VSC_DBG_ECO_CNTL 0x00000c00
-
-#define REG_A6XX_VSC_BIN_SIZE 0x00000c02
-#define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
-#define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
-static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK;
-}
-#define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00
-#define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8
-static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
-{
- assert(!(val & 0xf));
- return (((val >> 4)) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK;
-}
-
-#define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03
-
-#define REG_A6XX_VSC_BIN_COUNT 0x00000c06
-#define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe
-#define A6XX_VSC_BIN_COUNT_NX__SHIFT 1
-static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val)
-{
- return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK;
-}
-#define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800
-#define A6XX_VSC_BIN_COUNT_NY__SHIFT 11
-static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val)
-{
- return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK;
-}
-
-#define REG_A6XX_VSC_PIPE_CONFIG(i0) (0x00000c10 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
-#define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
-#define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
-static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
-{
- return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK;
-}
-#define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
-#define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
-static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
-{
- return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK;
-}
-#define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000
-#define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
-static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
-{
- return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK;
-}
-#define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000
-#define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26
-static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
-{
- return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK;
-}
-
-#define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30
-
-#define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32
-
-#define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33
-
-#define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34
-
-#define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36
-
-#define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37
-
-#define REG_A6XX_VSC_STATE(i0) (0x00000c38 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; }
-
-#define REG_A6XX_VSC_PRIM_STRM_SIZE(i0) (0x00000c58 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; }
-
-#define REG_A6XX_VSC_DRAW_STRM_SIZE(i0) (0x00000c78 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; }
-
-#define REG_A7XX_UCHE_UNKNOWN_0E10 0x00000e10
-
-#define REG_A7XX_UCHE_UNKNOWN_0E11 0x00000e11
-
-#define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12
-
-#define REG_A6XX_GRAS_CL_CNTL 0x00008000
-#define A6XX_GRAS_CL_CNTL_CLIP_DISABLE 0x00000001
-#define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE 0x00000002
-#define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE 0x00000004
-#define A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE 0x00000020
-#define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
-#define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE 0x00000080
-#define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE 0x00000100
-#define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE 0x00000200
-
-#define REG_A6XX_GRAS_VS_CL_CNTL 0x00008001
-#define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
-#define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0
-static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
-{
- return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
-}
-#define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
-#define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8
-static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
-{
- return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
-}
-
-#define REG_A6XX_GRAS_DS_CL_CNTL 0x00008002
-#define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
-#define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT 0
-static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val)
-{
- return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK;
-}
-#define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
-#define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT 8
-static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val)
-{
- return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK;
-}
-
-#define REG_A6XX_GRAS_GS_CL_CNTL 0x00008003
-#define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
-#define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT 0
-static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val)
-{
- return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK;
-}
-#define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
-#define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT 8
-static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val)
-{
- return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK;
-}
-
-#define REG_A6XX_GRAS_MAX_LAYER_INDEX 0x00008004
-
-#define REG_A6XX_GRAS_CNTL 0x00008005
-#define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
-#define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
-#define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
-#define A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL 0x00000008
-#define A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID 0x00000010
-#define A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE 0x00000020
-#define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0
-#define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6
-static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val)
-{
- return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK;
-}
-#define A6XX_GRAS_CNTL_UNK10 0x00000400
-#define A6XX_GRAS_CNTL_UNK11 0x00000800
-
-#define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006
-#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff
-#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
-static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
-{
- return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
-}
-#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x0007fc00
-#define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
-static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
-{
- return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
-}
-
-#define REG_A7XX_GRAS_UNKNOWN_8007 0x00008007
-
-#define REG_A7XX_GRAS_UNKNOWN_8008 0x00008008
-
-#define REG_A7XX_GRAS_UNKNOWN_8009 0x00008009
-
-#define REG_A7XX_GRAS_UNKNOWN_800A 0x0000800a
-
-#define REG_A7XX_GRAS_UNKNOWN_800B 0x0000800b
-
-#define REG_A7XX_GRAS_UNKNOWN_800C 0x0000800c
-
-#define REG_A6XX_GRAS_CL_VPORT(i0) (0x00008010 + 0x6*(i0))
-
-static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; }
-#define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff
-#define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0
-static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val)
-{
- return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK;
-}
-
-static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; }
-#define A6XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff
-#define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT 0
-static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val)
-{
- return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK;
-}
-
-static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; }
-#define A6XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff
-#define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0
-static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val)
-{
- return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK;
-}
-
-static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; }
-#define A6XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff
-#define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT 0
-static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val)
-{
- return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK;
-}
-
-static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; }
-#define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff
-#define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0
-static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val)
-{
- return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK;
-}
-
-static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; }
-#define A6XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff
-#define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0
-static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val)
-{
- return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK;
-}
-
-#define REG_A6XX_GRAS_CL_Z_CLAMP(i0) (0x00008070 + 0x2*(i0))
-
-static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; }
-#define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff
-#define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT 0
-static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val)
-{
- return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK;
-}
-
-static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; }
-#define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK 0xffffffff
-#define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT 0
-static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val)
-{
- return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK;
-}
-
-#define REG_A6XX_GRAS_SU_CNTL 0x00008090
-#define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
-#define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
-#define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
-#define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
-#define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
-static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
-{
- return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
-}
-#define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
-#define A6XX_GRAS_SU_CNTL_UNK12 0x00001000
-#define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000
-#define A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13
-static inline uint32_t A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val)
-{
- return ((val) << A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A6XX_GRAS_SU_CNTL_LINE_MODE__MASK;
-}
-#define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000
-#define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15
-static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK;
-}
-#define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00020000
-#define A6XX_GRAS_SU_CNTL_RENDERTARGETINDEXINCR 0x00040000
-#define A6XX_GRAS_SU_CNTL_VIEWPORTINDEXINCR 0x00080000
-#define A6XX_GRAS_SU_CNTL_UNK20__MASK 0x00700000
-#define A6XX_GRAS_SU_CNTL_UNK20__SHIFT 20
-static inline uint32_t A6XX_GRAS_SU_CNTL_UNK20(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SU_CNTL_UNK20__SHIFT) & A6XX_GRAS_SU_CNTL_UNK20__MASK;
-}
-
-#define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091
-#define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
-#define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
-static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val)
-{
- return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
-}
-#define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
-#define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
-static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val)
-{
- return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
-}
-
-#define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092
-#define A6XX_GRAS_SU_POINT_SIZE__MASK 0x0000ffff
-#define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0
-static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK;
-}
-
-#define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094
-#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003
-#define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0
-static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
-{
- return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK;
-}
-
-#define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095
-#define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
-#define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
-static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
-{
- return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
-}
-
-#define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096
-#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
-#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
-static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
-{
- return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
-}
-
-#define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097
-#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
-#define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
-static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
-{
- return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
-}
-
-#define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098
-#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
-#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
-static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
-{
- return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
-}
-#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3 0x00000008
-
-#define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x00008099
-#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001
-#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK 0x00000006
-#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT 1
-static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK;
-}
-#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN 0x00000008
-#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK 0x00000030
-#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT 4
-static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK;
-}
-
-#define REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL 0x0000809a
-#define A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 0x00000001
-#define A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN 0x00000002
-
-#define REG_A6XX_GRAS_VS_LAYER_CNTL 0x0000809b
-#define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER 0x00000001
-#define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW 0x00000002
-
-#define REG_A6XX_GRAS_GS_LAYER_CNTL 0x0000809c
-#define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER 0x00000001
-#define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW 0x00000002
-
-#define REG_A6XX_GRAS_DS_LAYER_CNTL 0x0000809d
-#define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER 0x00000001
-#define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW 0x00000002
-
-#define REG_A6XX_GRAS_SC_CNTL 0x000080a0
-#define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000007
-#define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT 0
-static inline uint32_t A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK;
-}
-#define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK 0x00000018
-#define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT 3
-static inline uint32_t A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val)
-{
- return ((val) << A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK;
-}
-#define A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK 0x00000020
-#define A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT 5
-static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
-{
- return ((val) << A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK;
-}
-#define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK 0x000000c0
-#define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT 6
-static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)
-{
- return ((val) << A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK;
-}
-#define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK 0x00000100
-#define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT 8
-static inline uint32_t A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val)
-{
- return ((val) << A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT) & A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK;
-}
-#define A6XX_GRAS_SC_CNTL_UNK9 0x00000200
-#define A6XX_GRAS_SC_CNTL_ROTATION__MASK 0x00000c00
-#define A6XX_GRAS_SC_CNTL_ROTATION__SHIFT 10
-static inline uint32_t A6XX_GRAS_SC_CNTL_ROTATION(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SC_CNTL_ROTATION__SHIFT) & A6XX_GRAS_SC_CNTL_ROTATION__MASK;
-}
-#define A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN 0x00001000
-
-#define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1
-#define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x0000003f
-#define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0
-static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK;
-}
-#define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00
-#define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8
-static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
-{
- assert(!(val & 0xf));
- return (((val >> 4)) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
-}
-#define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000
-#define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT 18
-static inline uint32_t A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)
-{
- return ((val) << A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK;
-}
-#define A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000
-#define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000
-#define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22
-static inline uint32_t A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val)
-{
- return ((val) << A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK;
-}
-#define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000
-#define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24
-static inline uint32_t A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)
-{
- return ((val) << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK;
-}
-#define A6XX_GRAS_BIN_CONTROL_UNK27 0x08000000
-
-#define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2
-#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
-#define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
-static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK;
-}
-#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2 0x00000004
-#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3 0x00000008
-
-#define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3
-#define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
-#define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
-static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK;
-}
-#define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
-
-#define REG_A6XX_GRAS_SAMPLE_CONFIG 0x000080a4
-#define A6XX_GRAS_SAMPLE_CONFIG_UNK0 0x00000001
-#define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
-
-#define REG_A6XX_GRAS_SAMPLE_LOCATION_0 0x000080a5
-#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
-#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
-static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
-}
-#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
-#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
-static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
-}
-#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
-#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
-static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
-}
-#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
-#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
-static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
-}
-#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
-#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
-static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
-}
-#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
-#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
-static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
-}
-#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
-#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
-static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
-}
-#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
-#define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
-static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
-}
-
-#define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6
-#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
-#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
-static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
-}
-#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
-#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
-static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
-}
-#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
-#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
-static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
-}
-#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
-#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
-static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
-}
-#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
-#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
-static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
-}
-#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
-#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
-static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
-}
-#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
-#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
-static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
-}
-#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
-#define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
-static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
-}
-
-#define REG_A7XX_GRAS_UNKNOWN_80A7 0x000080a7
-
-#define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af
-
-#define REG_A6XX_GRAS_SC_SCREEN_SCISSOR(i0) (0x000080b0 + 0x2*(i0))
-
-static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; }
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
-static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
-}
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0xffff0000
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
-static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
-}
-
-static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; }
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x0000ffff
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
-static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
-}
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0xffff0000
-#define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
-static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
-}
-
-#define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(i0) (0x000080d0 + 0x2*(i0))
-
-static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; }
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT 0
-static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK;
-}
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK 0xffff0000
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT 16
-static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK;
-}
-
-static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; }
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK 0x0000ffff
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT 0
-static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK;
-}
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK 0xffff0000
-#define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT 16
-static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK;
-}
-
-#define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0
-#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00003fff
-#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
-static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
-}
-#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x3fff0000
-#define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
-static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
-}
-
-#define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1
-#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00003fff
-#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
-static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
-}
-#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x3fff0000
-#define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
-static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
-{
- return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
-}
-
-#define REG_A7XX_GRAS_UNKNOWN_80F4 0x000080f4
-
-#define REG_A7XX_GRAS_UNKNOWN_80F5 0x000080f5
-
-#define REG_A7XX_GRAS_UNKNOWN_80F6 0x000080f6
-
-#define REG_A7XX_GRAS_UNKNOWN_80F8 0x000080f8
-
-#define REG_A7XX_GRAS_UNKNOWN_80F9 0x000080f9
-
-#define REG_A7XX_GRAS_UNKNOWN_80FA 0x000080fa
-
-#define REG_A6XX_GRAS_LRZ_CNTL 0x00008100
-#define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
-#define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
-#define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004
-#define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008
-#define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010
-#define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020
-#define A6XX_GRAS_LRZ_CNTL_DIR__MASK 0x000000c0
-#define A6XX_GRAS_LRZ_CNTL_DIR__SHIFT 6
-static inline uint32_t A6XX_GRAS_LRZ_CNTL_DIR(enum a6xx_lrz_dir_status val)
-{
- return ((val) << A6XX_GRAS_LRZ_CNTL_DIR__SHIFT) & A6XX_GRAS_LRZ_CNTL_DIR__MASK;
-}
-#define A6XX_GRAS_LRZ_CNTL_DIR_WRITE 0x00000100
-#define A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR 0x00000200
-#define A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK 0x00003800
-#define A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT 11
-static inline uint32_t A6XX_GRAS_LRZ_CNTL_Z_FUNC(enum adreno_compare_func val)
-{
- return ((val) << A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT) & A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK;
-}
-
-#define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL 0x00008101
-#define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID 0x00000001
-#define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK 0x00000006
-#define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT 1
-static inline uint32_t A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val)
-{
- return ((val) << A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK;
-}
-
-#define REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 0x00008102
-#define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK 0x000000ff
-#define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT 0
-static inline uint32_t A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val)
-{
- return ((val) << A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT) & A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK;
-}
-
-#define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103
-
-#define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105
-#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff
-#define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0
-static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK;
-}
-#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00
-#define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10
-static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0xf));
- return (((val >> 4)) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK;
-}
-
-#define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106
-
-#define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109
-#define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
-
-#define REG_A6XX_GRAS_LRZ_DEPTH_VIEW 0x0000810a
-#define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK 0x000007ff
-#define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT 0
-static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER(uint32_t val)
-{
- return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK;
-}
-#define A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK 0x07ff0000
-#define A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT 16
-static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT(uint32_t val)
-{
- return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK;
-}
-#define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK 0xf0000000
-#define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT 28
-static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(uint32_t val)
-{
- return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK;
-}
-
-#define REG_A7XX_GRAS_UNKNOWN_810B 0x0000810b
-
-#define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110
-
-#define REG_A7XX_GRAS_LRZ_CLEAR_DEPTH_F32 0x00008111
-#define A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK 0xffffffff
-#define A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT 0
-static inline uint32_t A7XX_GRAS_LRZ_CLEAR_DEPTH_F32(float val)
-{
- return ((fui(val)) << A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT) & A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK;
-}
-
-#define REG_A7XX_GRAS_UNKNOWN_8113 0x00008113
-
-#define REG_A7XX_GRAS_UNKNOWN_8120 0x00008120
-
-#define REG_A7XX_GRAS_UNKNOWN_8121 0x00008121
-
-#define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400
-#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007
-#define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0
-static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
-{
- return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK;
-}
-#define A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN 0x00000008
-#define A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK 0x00000070
-#define A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT 4
-static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val)
-{
- return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK;
-}
-#define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080
-#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
-#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
-static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
-{
- return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
-}
-#define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000
-#define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK 0x00060000
-#define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT 17
-static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val)
-{
- return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK;
-}
-#define A6XX_GRAS_2D_BLIT_CNTL_D24S8 0x00080000
-#define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK 0x00f00000
-#define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT 20
-static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val)
-{
- return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK;
-}
-#define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000
-#define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24
-static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
-{
- return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK;
-}
-#define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000
-#define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29
-static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
-{
- return ((val) << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK;
-}
-#define A6XX_GRAS_2D_BLIT_CNTL_UNK30 0x40000000
-
-#define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401
-#define A6XX_GRAS_2D_SRC_TL_X__MASK 0x01ffff00
-#define A6XX_GRAS_2D_SRC_TL_X__SHIFT 8
-static inline uint32_t A6XX_GRAS_2D_SRC_TL_X(int32_t val)
-{
- return ((val) << A6XX_GRAS_2D_SRC_TL_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X__MASK;
-}
-
-#define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402
-#define A6XX_GRAS_2D_SRC_BR_X__MASK 0x01ffff00
-#define A6XX_GRAS_2D_SRC_BR_X__SHIFT 8
-static inline uint32_t A6XX_GRAS_2D_SRC_BR_X(int32_t val)
-{
- return ((val) << A6XX_GRAS_2D_SRC_BR_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X__MASK;
-}
-
-#define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403
-#define A6XX_GRAS_2D_SRC_TL_Y__MASK 0x01ffff00
-#define A6XX_GRAS_2D_SRC_TL_Y__SHIFT 8
-static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y(int32_t val)
-{
- return ((val) << A6XX_GRAS_2D_SRC_TL_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y__MASK;
-}
-
-#define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404
-#define A6XX_GRAS_2D_SRC_BR_Y__MASK 0x01ffff00
-#define A6XX_GRAS_2D_SRC_BR_Y__SHIFT 8
-static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y(int32_t val)
-{
- return ((val) << A6XX_GRAS_2D_SRC_BR_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y__MASK;
-}
-
-#define REG_A6XX_GRAS_2D_DST_TL 0x00008405
-#define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff
-#define A6XX_GRAS_2D_DST_TL_X__SHIFT 0
-static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val)
-{
- return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK;
-}
-#define A6XX_GRAS_2D_DST_TL_Y__MASK 0x3fff0000
-#define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16
-static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val)
-{
- return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK;
-}
-
-#define REG_A6XX_GRAS_2D_DST_BR 0x00008406
-#define A6XX_GRAS_2D_DST_BR_X__MASK 0x00003fff
-#define A6XX_GRAS_2D_DST_BR_X__SHIFT 0
-static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val)
-{
- return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK;
-}
-#define A6XX_GRAS_2D_DST_BR_Y__MASK 0x3fff0000
-#define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16
-static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val)
-{
- return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK;
-}
-
-#define REG_A6XX_GRAS_2D_UNKNOWN_8407 0x00008407
-
-#define REG_A6XX_GRAS_2D_UNKNOWN_8408 0x00008408
-
-#define REG_A6XX_GRAS_2D_UNKNOWN_8409 0x00008409
-
-#define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 0x0000840a
-#define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK 0x00003fff
-#define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT 0
-static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val)
-{
- return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK;
-}
-#define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK 0x3fff0000
-#define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT 16
-static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val)
-{
- return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK;
-}
-
-#define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 0x0000840b
-#define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK 0x00003fff
-#define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT 0
-static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val)
-{
- return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK;
-}
-#define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK 0x3fff0000
-#define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT 16
-static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val)
-{
- return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK;
-}
-
-#define REG_A6XX_GRAS_DBG_ECO_CNTL 0x00008600
-#define A6XX_GRAS_DBG_ECO_CNTL_UNK7 0x00000080
-#define A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS 0x00000800
-
-#define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601
-
-#define REG_A7XX_GRAS_NC_MODE_CNTL 0x00008602
-
-#define REG_A6XX_GRAS_PERFCTR_TSE_SEL(i0) (0x00008610 + 0x1*(i0))
-
-#define REG_A6XX_GRAS_PERFCTR_RAS_SEL(i0) (0x00008614 + 0x1*(i0))
-
-#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL(i0) (0x00008618 + 0x1*(i0))
-
-#define REG_A6XX_RB_BIN_CONTROL 0x00008800
-#define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f
-#define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0
-static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK;
-}
-#define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00
-#define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8
-static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
-{
- assert(!(val & 0xf));
- return (((val >> 4)) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
-}
-#define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000
-#define A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18
-static inline uint32_t A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)
-{
- return ((val) << A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK;
-}
-#define A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000
-#define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000
-#define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22
-static inline uint32_t A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val)
-{
- return ((val) << A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK;
-}
-#define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000
-#define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24
-static inline uint32_t A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)
-{
- return ((val) << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK;
-}
-
-#define REG_A7XX_RB_BIN_CONTROL 0x00008800
-#define A7XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f
-#define A7XX_RB_BIN_CONTROL_BINW__SHIFT 0
-static inline uint32_t A7XX_RB_BIN_CONTROL_BINW(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A7XX_RB_BIN_CONTROL_BINW__SHIFT) & A7XX_RB_BIN_CONTROL_BINW__MASK;
-}
-#define A7XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00
-#define A7XX_RB_BIN_CONTROL_BINH__SHIFT 8
-static inline uint32_t A7XX_RB_BIN_CONTROL_BINH(uint32_t val)
-{
- assert(!(val & 0xf));
- return (((val >> 4)) << A7XX_RB_BIN_CONTROL_BINH__SHIFT) & A7XX_RB_BIN_CONTROL_BINH__MASK;
-}
-#define A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000
-#define A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18
-static inline uint32_t A7XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)
-{
- return ((val) << A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK;
-}
-#define A7XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000
-#define A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000
-#define A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24
-static inline uint32_t A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)
-{
- return ((val) << A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK;
-}
-
-#define REG_A6XX_RB_RENDER_CNTL 0x00008801
-#define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000038
-#define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT 3
-static inline uint32_t A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val)
-{
- return ((val) << A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK;
-}
-#define A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040
-#define A6XX_RB_RENDER_CNTL_BINNING 0x00000080
-#define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00000700
-#define A6XX_RB_RENDER_CNTL_UNK8__SHIFT 8
-static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val)
-{
- return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK;
-}
-#define A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100
-#define A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8
-static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
-{
- return ((val) << A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK;
-}
-#define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600
-#define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9
-static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)
-{
- return ((val) << A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK;
-}
-#define A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800
-#define A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000
-#define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
-#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
-#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
-static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
-{
- return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
-}
-
-#define REG_A7XX_RB_RENDER_CNTL 0x00008801
-#define A7XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040
-#define A7XX_RB_RENDER_CNTL_BINNING 0x00000080
-#define A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100
-#define A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8
-static inline uint32_t A7XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
-{
- return ((val) << A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK;
-}
-#define A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600
-#define A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9
-static inline uint32_t A7XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)
-{
- return ((val) << A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK;
-}
-#define A7XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800
-#define A7XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000
-
-#define REG_A7XX_GRAS_SU_RENDER_CNTL 0x00008116
-#define A7XX_GRAS_SU_RENDER_CNTL_BINNING 0x00000080
-
-#define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802
-#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
-#define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
-static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
-}
-#define A6XX_RB_RAS_MSAA_CNTL_UNK2 0x00000004
-#define A6XX_RB_RAS_MSAA_CNTL_UNK3 0x00000008
-
-#define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803
-#define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
-#define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
-static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
-}
-#define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
-
-#define REG_A6XX_RB_SAMPLE_CONFIG 0x00008804
-#define A6XX_RB_SAMPLE_CONFIG_UNK0 0x00000001
-#define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
-
-#define REG_A6XX_RB_SAMPLE_LOCATION_0 0x00008805
-#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
-#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
-static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
-}
-#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
-#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
-static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
-}
-#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
-#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
-static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
-}
-#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
-#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
-static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
-}
-#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
-#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
-static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
-}
-#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
-#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
-static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
-}
-#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
-#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
-static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
-}
-#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
-#define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
-static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
-}
-
-#define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806
-#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
-#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
-static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
-}
-#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
-#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
-static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
-}
-#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
-#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
-static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
-}
-#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
-#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
-static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
-}
-#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
-#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
-static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
-}
-#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
-#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
-static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
-}
-#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
-#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
-static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
-}
-#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
-#define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
-static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
-}
-
-#define REG_A6XX_RB_RENDER_CONTROL0 0x00008809
-#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001
-#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002
-#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004
-#define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL 0x00000008
-#define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID 0x00000010
-#define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE 0x00000020
-#define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0
-#define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6
-static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
-{
- return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
-}
-#define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400
-
-#define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a
-#define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
-#define A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE 0x00000002
-#define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004
-#define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008
-#define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK 0x00000030
-#define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT 4
-static inline uint32_t A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val)
-{
- return ((val) << A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK;
-}
-#define A6XX_RB_RENDER_CONTROL1_CENTERRHW 0x00000040
-#define A6XX_RB_RENDER_CONTROL1_LINELENGTHEN 0x00000080
-#define A6XX_RB_RENDER_CONTROL1_FOVEATION 0x00000100
-
-#define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b
-#define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001
-#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002
-#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004
-#define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF 0x00000008
-
-#define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c
-#define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
-#define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0
-static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val)
-{
- return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK;
-}
-
-#define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d
-#define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
-#define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
-static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
-{
- return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK;
-}
-#define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
-#define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
-static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
-{
- return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK;
-}
-#define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
-#define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
-static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
-{
- return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK;
-}
-#define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
-#define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
-static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
-{
- return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK;
-}
-#define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
-#define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
-static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
-{
- return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK;
-}
-#define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
-#define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
-static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
-{
- return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK;
-}
-#define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
-#define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
-static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
-{
- return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK;
-}
-#define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
-#define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
-static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
-{
- return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK;
-}
-
-#define REG_A6XX_RB_DITHER_CNTL 0x0000880e
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0
-static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val)
-{
- return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK;
-}
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2
-static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val)
-{
- return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK;
-}
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4
-static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val)
-{
- return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK;
-}
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6
-static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val)
-{
- return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK;
-}
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8
-static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val)
-{
- return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK;
-}
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10
-static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val)
-{
- return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK;
-}
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00003000
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12
-static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val)
-{
- return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK;
-}
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000
-#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14
-static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val)
-{
- return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK;
-}
-
-#define REG_A6XX_RB_SRGB_CNTL 0x0000880f
-#define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001
-#define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002
-#define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004
-#define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008
-#define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010
-#define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020
-#define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040
-#define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080
-
-#define REG_A6XX_RB_SAMPLE_CNTL 0x00008810
-#define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001
-
-#define REG_A6XX_RB_UNKNOWN_8811 0x00008811
-
-#define REG_A7XX_RB_UNKNOWN_8812 0x00008812
-
-#define REG_A6XX_RB_UNKNOWN_8818 0x00008818
-
-#define REG_A6XX_RB_UNKNOWN_8819 0x00008819
-
-#define REG_A6XX_RB_UNKNOWN_881A 0x0000881a
-
-#define REG_A6XX_RB_UNKNOWN_881B 0x0000881b
-
-#define REG_A6XX_RB_UNKNOWN_881C 0x0000881c
-
-#define REG_A6XX_RB_UNKNOWN_881D 0x0000881d
-
-#define REG_A6XX_RB_UNKNOWN_881E 0x0000881e
-
-#define REG_A6XX_RB_MRT(i0) (0x00008820 + 0x8*(i0))
-
-static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; }
-#define A6XX_RB_MRT_CONTROL_BLEND 0x00000001
-#define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002
-#define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004
-#define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078
-#define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3
-static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
-{
- return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK;
-}
-#define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
-#define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
-static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
-{
- return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
-}
-
-static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; }
-#define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
-#define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
-static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
-{
- return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
-}
-#define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
-#define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
-static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
-{
- return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
-}
-#define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
-#define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
-static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
-{
- return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
-}
-#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
-#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
-static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
-{
- return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
-}
-#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
-#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
-static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
-{
- return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
-}
-#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
-#define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
-static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
-{
- return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
-}
-
-static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
-#define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
-#define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
-static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val)
-{
- return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
-}
-#define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
-#define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
-static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)
-{
- return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
-}
-#define A6XX_RB_MRT_BUF_INFO_UNK10 0x00000400
-#define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
-#define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
-static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
-}
-
-static inline uint32_t REG_A7XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; }
-#define A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
-#define A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
-static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val)
-{
- return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
-}
-#define A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
-#define A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
-static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val)
-{
- return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
-}
-#define A7XX_RB_MRT_BUF_INFO_UNK10 0x00000400
-#define A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN 0x00000800
-#define A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
-#define A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
-static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
-}
-
-static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; }
-#define A6XX_RB_MRT_PITCH__MASK 0xffffffff
-#define A6XX_RB_MRT_PITCH__SHIFT 0
-static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK;
-}
-
-static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; }
-#define A6XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff
-#define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0
-static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK;
-}
-
-static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; }
-
-static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; }
-
-#define REG_A6XX_RB_BLEND_RED_F32 0x00008860
-#define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff
-#define A6XX_RB_BLEND_RED_F32__SHIFT 0
-static inline uint32_t A6XX_RB_BLEND_RED_F32(float val)
-{
- return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK;
-}
-
-#define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861
-#define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
-#define A6XX_RB_BLEND_GREEN_F32__SHIFT 0
-static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val)
-{
- return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK;
-}
-
-#define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862
-#define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
-#define A6XX_RB_BLEND_BLUE_F32__SHIFT 0
-static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val)
-{
- return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK;
-}
-
-#define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863
-#define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
-#define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0
-static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val)
-{
- return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK;
-}
-
-#define REG_A6XX_RB_ALPHA_CONTROL 0x00008864
-#define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
-#define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
-static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
-{
- return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
-}
-#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
-#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
-#define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
-static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
-{
- return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
-}
-
-#define REG_A6XX_RB_BLEND_CNTL 0x00008865
-#define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
-#define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
-static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
-{
- return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
-}
-#define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
-#define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
-#define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
-#define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE 0x00000800
-#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
-#define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
-static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
-{
- return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
-}
-
-#define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870
-#define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003
-#define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0
-static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
-{
- return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK;
-}
-
-#define REG_A6XX_RB_DEPTH_CNTL 0x00008871
-#define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001
-#define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
-#define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
-#define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
-static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
-{
- return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
-}
-#define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE 0x00000020
-#define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040
-#define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080
-
-#define REG_A6XX_GRAS_SU_DEPTH_CNTL 0x00008114
-#define A6XX_GRAS_SU_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001
-
-#define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872
-#define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
-#define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
-static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
-{
- return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
-}
-#define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018
-#define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3
-static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
-{
- return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK;
-}
-
-#define REG_A7XX_RB_DEPTH_BUFFER_INFO 0x00008872
-#define A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
-#define A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
-static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val)
-{
- return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
-}
-#define A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018
-#define A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3
-static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
-{
- return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK;
-}
-#define A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK 0x00000060
-#define A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT 5
-static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE(enum a6xx_tile_mode val)
-{
- return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK;
-}
-#define A7XX_RB_DEPTH_BUFFER_INFO_LOSSLESSCOMPEN 0x00000080
-
-#define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873
-#define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff
-#define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
-static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK;
-}
-
-#define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874
-#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0x0fffffff
-#define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
-static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
-}
-
-#define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875
-
-#define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877
-
-#define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878
-#define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff
-#define A6XX_RB_Z_BOUNDS_MIN__SHIFT 0
-static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val)
-{
- return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK;
-}
-
-#define REG_A6XX_RB_Z_BOUNDS_MAX 0x00008879
-#define A6XX_RB_Z_BOUNDS_MAX__MASK 0xffffffff
-#define A6XX_RB_Z_BOUNDS_MAX__SHIFT 0
-static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val)
-{
- return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK;
-}
-
-#define REG_A6XX_RB_STENCIL_CONTROL 0x00008880
-#define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
-#define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
-#define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
-#define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
-#define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
-static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
-{
- return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK;
-}
-#define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
-#define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
-static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
-{
- return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK;
-}
-#define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
-#define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
-static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
-{
- return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK;
-}
-#define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
-#define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
-static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
-{
- return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
-}
-#define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
-#define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
-static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
-{
- return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
-}
-#define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
-#define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
-static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
-{
- return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
-}
-#define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
-#define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
-static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
-{
- return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
-}
-#define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
-#define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
-static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
-{
- return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
-}
-
-#define REG_A6XX_GRAS_SU_STENCIL_CNTL 0x00008115
-#define A6XX_GRAS_SU_STENCIL_CNTL_STENCIL_ENABLE 0x00000001
-
-#define REG_A6XX_RB_STENCIL_INFO 0x00008881
-#define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
-#define A6XX_RB_STENCIL_INFO_UNK1 0x00000002
-
-#define REG_A7XX_RB_STENCIL_INFO 0x00008881
-#define A7XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
-#define A7XX_RB_STENCIL_INFO_UNK1 0x00000002
-#define A7XX_RB_STENCIL_INFO_TILEMODE__MASK 0x0000000c
-#define A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT 2
-static inline uint32_t A7XX_RB_STENCIL_INFO_TILEMODE(enum a6xx_tile_mode val)
-{
- return ((val) << A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT) & A7XX_RB_STENCIL_INFO_TILEMODE__MASK;
-}
-
-#define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882
-#define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff
-#define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0
-static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK;
-}
-
-#define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883
-#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0x00ffffff
-#define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0
-static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK;
-}
-
-#define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884
-
-#define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886
-
-#define REG_A6XX_RB_STENCILREF 0x00008887
-#define A6XX_RB_STENCILREF_REF__MASK 0x000000ff
-#define A6XX_RB_STENCILREF_REF__SHIFT 0
-static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val)
-{
- return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK;
-}
-#define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00
-#define A6XX_RB_STENCILREF_BFREF__SHIFT 8
-static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val)
-{
- return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK;
-}
-
-#define REG_A6XX_RB_STENCILMASK 0x00008888
-#define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff
-#define A6XX_RB_STENCILMASK_MASK__SHIFT 0
-static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val)
-{
- return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK;
-}
-#define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00
-#define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8
-static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val)
-{
- return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK;
-}
-
-#define REG_A6XX_RB_STENCILWRMASK 0x00008889
-#define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff
-#define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0
-static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val)
-{
- return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK;
-}
-#define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00
-#define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8
-static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val)
-{
- return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK;
-}
-
-#define REG_A6XX_RB_WINDOW_OFFSET 0x00008890
-#define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00003fff
-#define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0
-static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val)
-{
- return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK;
-}
-#define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x3fff0000
-#define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16
-static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val)
-{
- return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK;
-}
-
-#define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891
-#define A6XX_RB_SAMPLE_COUNT_CONTROL_DISABLE 0x00000001
-#define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
-
-#define REG_A6XX_RB_LRZ_CNTL 0x00008898
-#define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001
-
-#define REG_A7XX_RB_UNKNOWN_8899 0x00008899
-
-#define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0
-#define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff
-#define A6XX_RB_Z_CLAMP_MIN__SHIFT 0
-static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val)
-{
- return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK;
-}
-
-#define REG_A6XX_RB_Z_CLAMP_MAX 0x000088c1
-#define A6XX_RB_Z_CLAMP_MAX__MASK 0xffffffff
-#define A6XX_RB_Z_CLAMP_MAX__SHIFT 0
-static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val)
-{
- return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK;
-}
-
-#define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0
-#define A6XX_RB_UNKNOWN_88D0_UNK0__MASK 0x00001fff
-#define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT 0
-static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val)
-{
- return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK;
-}
-#define A6XX_RB_UNKNOWN_88D0_UNK16__MASK 0x07ff0000
-#define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT 16
-static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val)
-{
- return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK;
-}
-
-#define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1
-#define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00003fff
-#define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0
-static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val)
-{
- return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK;
-}
-#define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x3fff0000
-#define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16
-static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val)
-{
- return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK;
-}
-
-#define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2
-#define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00003fff
-#define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0
-static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val)
-{
- return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK;
-}
-#define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x3fff0000
-#define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16
-static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val)
-{
- return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK;
-}
-
-#define REG_A6XX_RB_BIN_CONTROL2 0x000088d3
-#define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x0000003f
-#define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0
-static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK;
-}
-#define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00
-#define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8
-static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val)
-{
- assert(!(val & 0xf));
- return (((val >> 4)) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK;
-}
-
-#define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4
-#define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00003fff
-#define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0
-static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val)
-{
- return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK;
-}
-#define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x3fff0000
-#define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16
-static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val)
-{
- return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK;
-}
-
-#define REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL 0x000088d5
-#define A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK 0x00000018
-#define A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT 3
-static inline uint32_t A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK;
-}
-
-#define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6
-
-#define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7
-#define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003
-#define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0
-static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
-{
- return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK;
-}
-#define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004
-#define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018
-#define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3
-static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK;
-}
-#define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060
-#define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5
-static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK;
-}
-#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80
-#define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7
-static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
-{
- return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK;
-}
-#define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000
-
-#define REG_A6XX_RB_BLIT_DST 0x000088d8
-
-#define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da
-#define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff
-#define A6XX_RB_BLIT_DST_PITCH__SHIFT 0
-static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK;
-}
-
-#define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db
-#define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0x1fffffff
-#define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
-static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
-}
-
-#define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc
-
-#define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de
-#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff
-#define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0
-static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK;
-}
-#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800
-#define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11
-static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0x7f));
- return (((val >> 7)) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK;
-}
-
-#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df
-
-#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0
-
-#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1
-
-#define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2
-
-#define REG_A6XX_RB_BLIT_INFO 0x000088e3
-#define A6XX_RB_BLIT_INFO_UNK0 0x00000001
-#define A6XX_RB_BLIT_INFO_GMEM 0x00000002
-#define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004
-#define A6XX_RB_BLIT_INFO_DEPTH 0x00000008
-#define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0
-#define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4
-static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val)
-{
- return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK;
-}
-#define A6XX_RB_BLIT_INFO_LAST__MASK 0x00000300
-#define A6XX_RB_BLIT_INFO_LAST__SHIFT 8
-static inline uint32_t A6XX_RB_BLIT_INFO_LAST(uint32_t val)
-{
- return ((val) << A6XX_RB_BLIT_INFO_LAST__SHIFT) & A6XX_RB_BLIT_INFO_LAST__MASK;
-}
-#define A6XX_RB_BLIT_INFO_BUFFER_ID__MASK 0x0000f000
-#define A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT 12
-static inline uint32_t A6XX_RB_BLIT_INFO_BUFFER_ID(uint32_t val)
-{
- return ((val) << A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT) & A6XX_RB_BLIT_INFO_BUFFER_ID__MASK;
-}
-
-#define REG_A7XX_RB_UNKNOWN_88E4 0x000088e4
-#define A7XX_RB_UNKNOWN_88E4_UNK0 0x00000001
-
-#define REG_A7XX_RB_CCU_CNTL2 0x000088e5
-#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK 0x00000001
-#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT 0
-static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI(uint32_t val)
-{
- return ((val) << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK;
-}
-#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK 0x00000004
-#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT 2
-static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI(uint32_t val)
-{
- return ((val) << A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK;
-}
-#define A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK 0x00000c00
-#define A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT 10
-static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE(enum a6xx_ccu_cache_size val)
-{
- return ((val) << A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK;
-}
-#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK 0x001ff000
-#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT 12
-static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_OFFSET(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK;
-}
-#define A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK 0x00600000
-#define A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT 21
-static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE(enum a6xx_ccu_cache_size val)
-{
- return ((val) << A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK;
-}
-#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK 0xff800000
-#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT 23
-static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_OFFSET(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK;
-}
-
-#define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0
-
-#define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1
-
-#define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3
-#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
-#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
-static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK;
-}
-#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800
-#define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
-static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0x7f));
- return (((val >> 7)) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
-}
-
-#define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4
-
-#define REG_A7XX_RB_UNKNOWN_88F5 0x000088f5
-
-#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900
-
-#define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902
-#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f
-#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
-static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK;
-}
-#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700
-#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8
-static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val)
-{
- return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK;
-}
-#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x0ffff800
-#define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
-static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0x7f));
- return (((val >> 7)) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
-}
-
-#define REG_A6XX_RB_MRT_FLAG_BUFFER(i0) (0x00008903 + 0x3*(i0))
-
-static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; }
-
-static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; }
-#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff
-#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0
-static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK;
-}
-#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800
-#define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11
-static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0x7f));
- return (((val >> 7)) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK;
-}
-
-#define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927
-
-#define REG_A6XX_RB_UNKNOWN_8A00 0x00008a00
-
-#define REG_A6XX_RB_UNKNOWN_8A10 0x00008a10
-
-#define REG_A6XX_RB_UNKNOWN_8A20 0x00008a20
-
-#define REG_A6XX_RB_UNKNOWN_8A30 0x00008a30
-
-#define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00
-#define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000007
-#define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0
-static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
-{
- return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK;
-}
-#define A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN 0x00000008
-#define A6XX_RB_2D_BLIT_CNTL_UNK4__MASK 0x00000070
-#define A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT 4
-static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val)
-{
- return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK4__MASK;
-}
-#define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000080
-#define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
-#define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8
-static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val)
-{
- return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK;
-}
-#define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000
-#define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK 0x00060000
-#define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT 17
-static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val)
-{
- return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK;
-}
-#define A6XX_RB_2D_BLIT_CNTL_D24S8 0x00080000
-#define A6XX_RB_2D_BLIT_CNTL_MASK__MASK 0x00f00000
-#define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT 20
-static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val)
-{
- return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK;
-}
-#define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000
-#define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24
-static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
-{
- return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK;
-}
-#define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000
-#define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29
-static inline uint32_t A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
-{
- return ((val) << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK;
-}
-#define A6XX_RB_2D_BLIT_CNTL_UNK30 0x40000000
-
-#define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01
-
-#define REG_A6XX_RB_2D_DST_INFO 0x00008c17
-#define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
-#define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
-static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val)
-{
- return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
-}
-#define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300
-#define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8
-static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val)
-{
- return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK;
-}
-#define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
-#define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
-static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
-}
-#define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000
-#define A6XX_RB_2D_DST_INFO_SRGB 0x00002000
-#define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000
-#define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14
-static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK;
-}
-#define A6XX_RB_2D_DST_INFO_FILTER 0x00010000
-#define A6XX_RB_2D_DST_INFO_UNK17 0x00020000
-#define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000
-#define A6XX_RB_2D_DST_INFO_UNK19 0x00080000
-#define A6XX_RB_2D_DST_INFO_UNK20 0x00100000
-#define A6XX_RB_2D_DST_INFO_UNK21 0x00200000
-#define A6XX_RB_2D_DST_INFO_UNK22 0x00400000
-#define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000
-#define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23
-static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val)
-{
- return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK;
-}
-#define A6XX_RB_2D_DST_INFO_UNK28 0x10000000
-
-#define REG_A6XX_RB_2D_DST 0x00008c18
-
-#define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a
-#define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff
-#define A6XX_RB_2D_DST_PITCH__SHIFT 0
-static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK;
-}
-
-#define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b
-
-#define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d
-#define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff
-#define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0
-static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK;
-}
-
-#define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e
-
-#define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20
-
-#define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22
-#define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff
-#define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0
-static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK;
-}
-
-#define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23
-
-#define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25
-#define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff
-#define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0
-static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK;
-}
-
-#define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c
-
-#define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d
-
-#define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e
-
-#define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f
-
-#define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01
-
-#define REG_A6XX_RB_DBG_ECO_CNTL 0x00008e04
-
-#define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05
-
-#define REG_A7XX_RB_UNKNOWN_8E06 0x00008e06
-
-#define REG_A6XX_RB_CCU_CNTL 0x00008e07
-#define A6XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE 0x00000001
-#define A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE 0x00000004
-#define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK 0x00000080
-#define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT 7
-static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI(uint32_t val)
-{
- return ((val) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK;
-}
-#define A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK 0x00000200
-#define A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT 9
-static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI(uint32_t val)
-{
- return ((val) << A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK;
-}
-#define A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK 0x00000c00
-#define A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT 10
-static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE(enum a6xx_ccu_cache_size val)
-{
- return ((val) << A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK;
-}
-#define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK 0x001ff000
-#define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT 12
-static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK;
-}
-#define A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK 0x00600000
-#define A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT 21
-static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE(enum a6xx_ccu_cache_size val)
-{
- return ((val) << A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK;
-}
-#define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK 0xff800000
-#define A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT 23
-static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK;
-}
-
-#define REG_A7XX_RB_CCU_CNTL 0x00008e07
-#define A7XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE 0x00000001
-#define A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE 0x00000004
-
-#define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08
-#define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001
-#define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006
-#define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT 1
-static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
-{
- return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK;
-}
-#define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008
-#define A6XX_RB_NC_MODE_CNTL_AMSBC 0x00000010
-#define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000400
-#define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT 10
-static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
-{
- return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK;
-}
-#define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR 0x00000800
-#define A6XX_RB_NC_MODE_CNTL_UNK12__MASK 0x00003000
-#define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT 12
-static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val)
-{
- return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK;
-}
-
-#define REG_A7XX_RB_UNKNOWN_8E09 0x00008e09
-
-#define REG_A6XX_RB_PERFCTR_RB_SEL(i0) (0x00008e10 + 0x1*(i0))
-
-#define REG_A6XX_RB_PERFCTR_CCU_SEL(i0) (0x00008e18 + 0x1*(i0))
-
-#define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28
-
-#define REG_A6XX_RB_PERFCTR_CMP_SEL(i0) (0x00008e2c + 0x1*(i0))
-
-#define REG_A7XX_RB_PERFCTR_UFC_SEL(i0) (0x00008e30 + 0x1*(i0))
-
-#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b
-
-#define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d
-
-#define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50
-
-#define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51
-
-#define REG_A7XX_RB_UNKNOWN_8E79 0x00008e79
-
-#define REG_A6XX_VPC_GS_PARAM 0x00009100
-#define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK 0x000000ff
-#define A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT 0
-static inline uint32_t A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT) & A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK;
-}
-
-#define REG_A6XX_VPC_VS_CLIP_CNTL 0x00009101
-#define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
-#define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT 0
-static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val)
-{
- return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK;
-}
-#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
-#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
-static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
-}
-#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
-#define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
-static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
-}
-
-#define REG_A6XX_VPC_GS_CLIP_CNTL 0x00009102
-#define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
-#define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT 0
-static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK;
-}
-#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
-#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
-static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
-}
-#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
-#define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
-static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
-}
-
-#define REG_A6XX_VPC_DS_CLIP_CNTL 0x00009103
-#define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
-#define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT 0
-static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val)
-{
- return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK;
-}
-#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
-#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
-static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
-}
-#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
-#define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
-static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
-}
-
-#define REG_A6XX_VPC_VS_CLIP_CNTL_V2 0x00009311
-#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff
-#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0
-static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val)
-{
- return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK;
-}
-#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00
-#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8
-static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK;
-}
-#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000
-#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16
-static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK;
-}
-
-#define REG_A6XX_VPC_GS_CLIP_CNTL_V2 0x00009312
-#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff
-#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0
-static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK;
-}
-#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00
-#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8
-static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK;
-}
-#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000
-#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16
-static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK;
-}
-
-#define REG_A6XX_VPC_DS_CLIP_CNTL_V2 0x00009313
-#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff
-#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0
-static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val)
-{
- return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK;
-}
-#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00
-#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8
-static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK;
-}
-#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000
-#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16
-static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK;
-}
-
-#define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104
-#define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
-#define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0
-static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK;
-}
-#define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
-#define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT 8
-static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK;
-}
-#define A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000
-#define A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16
-static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK;
-}
-
-#define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105
-#define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
-#define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT 0
-static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK;
-}
-#define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
-#define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT 8
-static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK;
-}
-#define A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000
-#define A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16
-static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK;
-}
-
-#define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106
-#define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff
-#define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT 0
-static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK;
-}
-#define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00
-#define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT 8
-static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK;
-}
-#define A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000
-#define A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16
-static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK;
-}
-
-#define REG_A6XX_VPC_VS_LAYER_CNTL_V2 0x00009314
-#define A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff
-#define A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0
-static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK;
-}
-#define A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00
-#define A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8
-static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK;
-}
-#define A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000
-#define A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16
-static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK;
-}
-
-#define REG_A6XX_VPC_GS_LAYER_CNTL_V2 0x00009315
-#define A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff
-#define A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0
-static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK;
-}
-#define A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00
-#define A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8
-static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK;
-}
-#define A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000
-#define A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16
-static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK;
-}
-
-#define REG_A6XX_VPC_DS_LAYER_CNTL_V2 0x00009316
-#define A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff
-#define A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0
-static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK;
-}
-#define A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00
-#define A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8
-static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK;
-}
-#define A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000
-#define A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16
-static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK;
-}
-
-#define REG_A6XX_VPC_UNKNOWN_9107 0x00009107
-#define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001
-#define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004
-
-#define REG_A6XX_VPC_POLYGON_MODE 0x00009108
-#define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003
-#define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0
-static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
-{
- return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK;
-}
-
-#define REG_A7XX_VPC_PRIMITIVE_CNTL_0 0x00009109
-#define A7XX_VPC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
-#define A7XX_VPC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002
-#define A7XX_VPC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING 0x00000004
-#define A7XX_VPC_PRIMITIVE_CNTL_0_UNK3 0x00000008
-
-#define REG_A7XX_VPC_PRIMITIVE_CNTL_5 0x0000910a
-#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff
-#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0
-static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val)
-{
- return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK;
-}
-#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00
-#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10
-static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val)
-{
- return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK;
-}
-#define A7XX_VPC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000
-#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000
-#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16
-static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val)
-{
- return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK;
-}
-#define A7XX_VPC_PRIMITIVE_CNTL_5_UNK18 0x00040000
-
-#define REG_A7XX_VPC_MULTIVIEW_MASK 0x0000910b
-
-#define REG_A7XX_VPC_MULTIVIEW_CNTL 0x0000910c
-#define A7XX_VPC_MULTIVIEW_CNTL_ENABLE 0x00000001
-#define A7XX_VPC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
-#define A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
-#define A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT 2
-static inline uint32_t A7XX_VPC_MULTIVIEW_CNTL_VIEWS(uint32_t val)
-{
- return ((val) << A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK;
-}
-
-#define REG_A6XX_VPC_VARYING_INTERP(i0) (0x00009200 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; }
-
-#define REG_A6XX_VPC_VARYING_PS_REPL(i0) (0x00009208 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; }
-
-#define REG_A6XX_VPC_UNKNOWN_9210 0x00009210
-
-#define REG_A6XX_VPC_UNKNOWN_9211 0x00009211
-
-#define REG_A6XX_VPC_VAR(i0) (0x00009212 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; }
-
-#define REG_A6XX_VPC_SO_CNTL 0x00009216
-#define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff
-#define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0
-static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val)
-{
- return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK;
-}
-#define A6XX_VPC_SO_CNTL_RESET 0x00010000
-
-#define REG_A6XX_VPC_SO_PROG 0x00009217
-#define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
-#define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0
-static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val)
-{
- return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK;
-}
-#define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
-#define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2
-static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK;
-}
-#define A6XX_VPC_SO_PROG_A_EN 0x00000800
-#define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
-#define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12
-static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val)
-{
- return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK;
-}
-#define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
-#define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14
-static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK;
-}
-#define A6XX_VPC_SO_PROG_B_EN 0x00800000
-
-#define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218
-
-#define REG_A6XX_VPC_SO(i0) (0x0000921a + 0x7*(i0))
-
-static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; }
-
-static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; }
-
-static inline uint32_t REG_A6XX_VPC_SO_BUFFER_STRIDE(uint32_t i0) { return 0x0000921d + 0x7*i0; }
-
-static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; }
-
-static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; }
-
-#define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236
-#define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001
-
-#define REG_A6XX_VPC_UNKNOWN_9300 0x00009300
-
-#define REG_A6XX_VPC_VS_PACK 0x00009301
-#define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
-#define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT 0
-static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val)
-{
- return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK;
-}
-#define A6XX_VPC_VS_PACK_POSITIONLOC__MASK 0x0000ff00
-#define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT 8
-static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK;
-}
-#define A6XX_VPC_VS_PACK_PSIZELOC__MASK 0x00ff0000
-#define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT 16
-static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK;
-}
-#define A6XX_VPC_VS_PACK_EXTRAPOS__MASK 0x0f000000
-#define A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT 24
-static inline uint32_t A6XX_VPC_VS_PACK_EXTRAPOS(uint32_t val)
-{
- return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK;
-}
-
-#define REG_A6XX_VPC_GS_PACK 0x00009302
-#define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
-#define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT 0
-static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK;
-}
-#define A6XX_VPC_GS_PACK_POSITIONLOC__MASK 0x0000ff00
-#define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT 8
-static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK;
-}
-#define A6XX_VPC_GS_PACK_PSIZELOC__MASK 0x00ff0000
-#define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT 16
-static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK;
-}
-#define A6XX_VPC_GS_PACK_EXTRAPOS__MASK 0x0f000000
-#define A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT 24
-static inline uint32_t A6XX_VPC_GS_PACK_EXTRAPOS(uint32_t val)
-{
- return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK;
-}
-
-#define REG_A6XX_VPC_DS_PACK 0x00009303
-#define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK 0x000000ff
-#define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT 0
-static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val)
-{
- return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK;
-}
-#define A6XX_VPC_DS_PACK_POSITIONLOC__MASK 0x0000ff00
-#define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT 8
-static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK;
-}
-#define A6XX_VPC_DS_PACK_PSIZELOC__MASK 0x00ff0000
-#define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT 16
-static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK;
-}
-#define A6XX_VPC_DS_PACK_EXTRAPOS__MASK 0x0f000000
-#define A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT 24
-static inline uint32_t A6XX_VPC_DS_PACK_EXTRAPOS(uint32_t val)
-{
- return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK;
-}
-
-#define REG_A6XX_VPC_CNTL_0 0x00009304
-#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff
-#define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0
-static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val)
-{
- return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK;
-}
-#define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00
-#define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8
-static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK;
-}
-#define A6XX_VPC_CNTL_0_VARYING 0x00010000
-#define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000
-#define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24
-static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val)
-{
- return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK;
-}
-
-#define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305
-#define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007
-#define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0
-static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val)
-{
- return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK;
-}
-#define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038
-#define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3
-static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val)
-{
- return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK;
-}
-#define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0
-#define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6
-static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val)
-{
- return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK;
-}
-#define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00
-#define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9
-static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val)
-{
- return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK;
-}
-#define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000
-#define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15
-static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val)
-{
- return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK;
-}
-
-#define REG_A6XX_VPC_SO_DISABLE 0x00009306
-#define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001
-
-#define REG_A7XX_VPC_POLYGON_MODE2 0x00009307
-#define A7XX_VPC_POLYGON_MODE2_MODE__MASK 0x00000003
-#define A7XX_VPC_POLYGON_MODE2_MODE__SHIFT 0
-static inline uint32_t A7XX_VPC_POLYGON_MODE2_MODE(enum a6xx_polygon_mode val)
-{
- return ((val) << A7XX_VPC_POLYGON_MODE2_MODE__SHIFT) & A7XX_VPC_POLYGON_MODE2_MODE__MASK;
-}
-
-#define REG_A7XX_VPC_ATTR_BUF_SIZE_GMEM 0x00009308
-#define A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK 0xffffffff
-#define A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT 0
-static inline uint32_t A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(uint32_t val)
-{
- return ((val) << A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK;
-}
-
-#define REG_A7XX_VPC_ATTR_BUF_BASE_GMEM 0x00009309
-#define A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK 0xffffffff
-#define A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT 0
-static inline uint32_t A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM(uint32_t val)
-{
- return ((val) << A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK;
-}
-
-#define REG_A7XX_PC_ATTR_BUF_SIZE_GMEM 0x00009b09
-#define A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK 0xffffffff
-#define A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT 0
-static inline uint32_t A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(uint32_t val)
-{
- return ((val) << A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK;
-}
-
-#define REG_A6XX_VPC_DBG_ECO_CNTL 0x00009600
-
-#define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601
-
-#define REG_A6XX_VPC_UNKNOWN_9602 0x00009602
-
-#define REG_A6XX_VPC_UNKNOWN_9603 0x00009603
-
-#define REG_A6XX_VPC_PERFCTR_VPC_SEL(i0) (0x00009604 + 0x1*(i0))
-
-#define REG_A7XX_VPC_PERFCTR_VPC_SEL(i0) (0x0000960b + 0x1*(i0))
-
-#define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800
-
-#define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801
-#define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff
-#define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0
-static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val)
-{
- return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK;
-}
-#define A6XX_PC_HS_INPUT_SIZE_UNK13 0x00002000
-
-#define REG_A6XX_PC_TESS_CNTL 0x00009802
-#define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003
-#define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0
-static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val)
-{
- return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK;
-}
-#define A6XX_PC_TESS_CNTL_OUTPUT__MASK 0x0000000c
-#define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT 2
-static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val)
-{
- return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK;
-}
-
-#define REG_A6XX_PC_RESTART_INDEX 0x00009803
-
-#define REG_A6XX_PC_MODE_CNTL 0x00009804
-
-#define REG_A6XX_PC_POWER_CNTL 0x00009805
-
-#define REG_A6XX_PC_PS_CNTL 0x00009806
-#define A6XX_PC_PS_CNTL_PRIMITIVEIDEN 0x00000001
-
-#define REG_A6XX_PC_SO_STREAM_CNTL 0x00009808
-#define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000
-#define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15
-static inline uint32_t A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val)
-{
- return ((val) << A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK;
-}
-
-#define REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL 0x0000980a
-#define A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001
-
-#define REG_A6XX_PC_DRAW_CMD 0x00009840
-#define A6XX_PC_DRAW_CMD_STATE_ID__MASK 0x000000ff
-#define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT 0
-static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val)
-{
- return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK;
-}
-
-#define REG_A6XX_PC_DISPATCH_CMD 0x00009841
-#define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK 0x000000ff
-#define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT 0
-static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val)
-{
- return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK;
-}
-
-#define REG_A6XX_PC_EVENT_CMD 0x00009842
-#define A6XX_PC_EVENT_CMD_STATE_ID__MASK 0x00ff0000
-#define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT 16
-static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val)
-{
- return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK;
-}
-#define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f
-#define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0
-static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val)
-{
- return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK;
-}
-
-#define REG_A6XX_PC_MARKER 0x00009880
-
-#define REG_A6XX_PC_POLYGON_MODE 0x00009981
-#define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003
-#define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0
-static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
-{
- return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK;
-}
-
-#define REG_A7XX_PC_POLYGON_MODE 0x00009809
-#define A7XX_PC_POLYGON_MODE_MODE__MASK 0x00000003
-#define A7XX_PC_POLYGON_MODE_MODE__SHIFT 0
-static inline uint32_t A7XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val)
-{
- return ((val) << A7XX_PC_POLYGON_MODE_MODE__SHIFT) & A7XX_PC_POLYGON_MODE_MODE__MASK;
-}
-
-#define REG_A6XX_PC_RASTER_CNTL 0x00009980
-#define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003
-#define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0
-static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val)
-{
- return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK;
-}
-#define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004
-
-#define REG_A7XX_PC_RASTER_CNTL 0x00009107
-#define A7XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003
-#define A7XX_PC_RASTER_CNTL_STREAM__SHIFT 0
-static inline uint32_t A7XX_PC_RASTER_CNTL_STREAM(uint32_t val)
-{
- return ((val) << A7XX_PC_RASTER_CNTL_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_STREAM__MASK;
-}
-#define A7XX_PC_RASTER_CNTL_DISCARD 0x00000004
-
-#define REG_A7XX_PC_RASTER_CNTL_V2 0x00009317
-#define A7XX_PC_RASTER_CNTL_V2_STREAM__MASK 0x00000003
-#define A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT 0
-static inline uint32_t A7XX_PC_RASTER_CNTL_V2_STREAM(uint32_t val)
-{
- return ((val) << A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_V2_STREAM__MASK;
-}
-#define A7XX_PC_RASTER_CNTL_V2_DISCARD 0x00000004
-
-#define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00
-#define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001
-#define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002
-#define A6XX_PC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING 0x00000004
-#define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008
-
-#define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01
-#define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
-#define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
-static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
-{
- return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK;
-}
-#define A6XX_PC_VS_OUT_CNTL_PSIZE 0x00000100
-#define A6XX_PC_VS_OUT_CNTL_LAYER 0x00000200
-#define A6XX_PC_VS_OUT_CNTL_VIEW 0x00000400
-#define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID 0x00000800
-#define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
-#define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT 16
-static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val)
-{
- return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK;
-}
-#define A6XX_PC_VS_OUT_CNTL_SHADINGRATE 0x01000000
-
-#define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02
-#define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
-#define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
-static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
-{
- return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK;
-}
-#define A6XX_PC_GS_OUT_CNTL_PSIZE 0x00000100
-#define A6XX_PC_GS_OUT_CNTL_LAYER 0x00000200
-#define A6XX_PC_GS_OUT_CNTL_VIEW 0x00000400
-#define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID 0x00000800
-#define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
-#define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT 16
-static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val)
-{
- return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK;
-}
-#define A6XX_PC_GS_OUT_CNTL_SHADINGRATE 0x01000000
-
-#define REG_A6XX_PC_HS_OUT_CNTL 0x00009b03
-#define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
-#define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
-static inline uint32_t A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
-{
- return ((val) << A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK;
-}
-#define A6XX_PC_HS_OUT_CNTL_PSIZE 0x00000100
-#define A6XX_PC_HS_OUT_CNTL_LAYER 0x00000200
-#define A6XX_PC_HS_OUT_CNTL_VIEW 0x00000400
-#define A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID 0x00000800
-#define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
-#define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT 16
-static inline uint32_t A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val)
-{
- return ((val) << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK;
-}
-#define A6XX_PC_HS_OUT_CNTL_SHADINGRATE 0x01000000
-
-#define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04
-#define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
-#define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
-static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
-{
- return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK;
-}
-#define A6XX_PC_DS_OUT_CNTL_PSIZE 0x00000100
-#define A6XX_PC_DS_OUT_CNTL_LAYER 0x00000200
-#define A6XX_PC_DS_OUT_CNTL_VIEW 0x00000400
-#define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID 0x00000800
-#define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
-#define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT 16
-static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val)
-{
- return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK;
-}
-#define A6XX_PC_DS_OUT_CNTL_SHADINGRATE 0x01000000
-
-#define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05
-#define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff
-#define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0
-static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val)
-{
- return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK;
-}
-#define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00
-#define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10
-static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val)
-{
- return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK;
-}
-#define A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000
-#define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000
-#define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16
-static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val)
-{
- return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK;
-}
-#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18 0x00040000
-
-#define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06
-#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff
-#define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0
-static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val)
-{
- return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK;
-}
-
-#define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07
-#define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001
-#define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
-#define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
-#define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2
-static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val)
-{
- return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK;
-}
-
-#define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08
-
-#define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00
-#define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f
-#define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0
-static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
-{
- return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK;
-}
-#define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00
-#define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8
-static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val)
-{
- return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK;
-}
-
-#define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00
-
-#define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01
-
-#define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04
-
-#define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06
-
-#define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07
-
-#define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08
-
-#define REG_A7XX_PC_TESSFACTOR_ADDR 0x00009810
-
-#define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b
-#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
-#define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
-static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
-{
- return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK;
-}
-#define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
-#define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
-static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
-{
- return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK;
-}
-#define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300
-#define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8
-static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
-{
- return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK;
-}
-#define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00
-#define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10
-static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val)
-{
- return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK;
-}
-#define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000
-#define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12
-static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val)
-{
- return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK;
-}
-#define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000
-#define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000
-
-#define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c
-
-#define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d
-
-#define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11
-#define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff
-#define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0
-static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val)
-{
- return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK;
-}
-#define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000
-#define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT 16
-static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val)
-{
- return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK;
-}
-#define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK 0x07c00000
-#define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT 22
-static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val)
-{
- return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK;
-}
-
-#define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12
-
-#define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14
-
-#define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c
-#define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001
-
-#define REG_A7XX_PC_UNKNOWN_9E24 0x00009e24
-
-#define REG_A6XX_PC_PERFCTR_PC_SEL(i0) (0x00009e34 + 0x1*(i0))
-
-#define REG_A7XX_PC_PERFCTR_PC_SEL(i0) (0x00009e42 + 0x1*(i0))
-
-#define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72
-
-#define REG_A6XX_VFD_CONTROL_0 0x0000a000
-#define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f
-#define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0
-static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val)
-{
- return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK;
-}
-#define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK 0x00003f00
-#define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT 8
-static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val)
-{
- return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK;
-}
-
-#define REG_A6XX_VFD_CONTROL_1 0x0000a001
-#define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
-#define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
-static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
-{
- return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK;
-}
-#define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
-#define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
-static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
-{
- return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK;
-}
-#define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000
-#define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16
-static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
-{
- return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
-}
-#define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000
-#define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24
-static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val)
-{
- return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK;
-}
-
-#define REG_A6XX_VFD_CONTROL_2 0x0000a002
-#define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK 0x000000ff
-#define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT 0
-static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val)
-{
- return ((val) << A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK;
-}
-#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00
-#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8
-static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)
-{
- return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK;
-}
-
-#define REG_A6XX_VFD_CONTROL_3 0x0000a003
-#define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK 0x000000ff
-#define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT 0
-static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val)
-{
- return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK;
-}
-#define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK 0x0000ff00
-#define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT 8
-static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val)
-{
- return ((val) << A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK;
-}
-#define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
-#define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
-static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
-{
- return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK;
-}
-#define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
-#define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
-static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
-{
- return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK;
-}
-
-#define REG_A6XX_VFD_CONTROL_4 0x0000a004
-#define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff
-#define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0
-static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val)
-{
- return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK;
-}
-
-#define REG_A6XX_VFD_CONTROL_5 0x0000a005
-#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK 0x000000ff
-#define A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT 0
-static inline uint32_t A6XX_VFD_CONTROL_5_REGID_GSHEADER(uint32_t val)
-{
- return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK;
-}
-#define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00
-#define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8
-static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val)
-{
- return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK;
-}
-
-#define REG_A6XX_VFD_CONTROL_6 0x0000a006
-#define A6XX_VFD_CONTROL_6_PRIMID4PSEN 0x00000001
-
-#define REG_A6XX_VFD_MODE_CNTL 0x0000a007
-#define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK 0x00000007
-#define A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT 0
-static inline uint32_t A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val)
-{
- return ((val) << A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT) & A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK;
-}
-
-#define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008
-#define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001
-#define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002
-#define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c
-#define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2
-static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val)
-{
- return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK;
-}
-
-#define REG_A6XX_VFD_ADD_OFFSET 0x0000a009
-#define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001
-#define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002
-
-#define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e
-
-#define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f
-
-#define REG_A6XX_VFD_FETCH(i0) (0x0000a010 + 0x4*(i0))
-
-static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; }
-
-static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; }
-
-static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; }
-
-#define REG_A6XX_VFD_DECODE(i0) (0x0000a090 + 0x2*(i0))
-
-static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; }
-#define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
-#define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0
-static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val)
-{
- return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK;
-}
-#define A6XX_VFD_DECODE_INSTR_OFFSET__MASK 0x0001ffe0
-#define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT 5
-static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val)
-{
- return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK;
-}
-#define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
-#define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000
-#define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
-static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val)
-{
- return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK;
-}
-#define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000
-#define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28
-static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK;
-}
-#define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000
-#define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000
-
-static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; }
-
-#define REG_A6XX_VFD_DEST_CNTL(i0) (0x0000a0d0 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; }
-#define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
-#define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
-static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
-{
- return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
-}
-#define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
-#define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
-static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
-{
- return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
-}
-
-#define REG_A6XX_VFD_POWER_CNTL 0x0000a0f8
-
-#define REG_A7XX_VFD_UNKNOWN_A600 0x0000a600
-
-#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
-
-#define REG_A6XX_VFD_PERFCTR_VFD_SEL(i0) (0x0000a610 + 0x1*(i0))
-
-#define REG_A7XX_VFD_PERFCTR_VFD_SEL(i0) (0x0000a610 + 0x1*(i0))
-
-#define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800
-#define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
-#define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
-static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
-{
- return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
-}
-#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
-#define A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
-static inline uint32_t A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
-#define A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
-static inline uint32_t A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000
-#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
-#define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14
-static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
-}
-#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000
-#define A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE 0x00200000
-
-#define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801
-
-#define REG_A6XX_SP_VS_PRIMITIVE_CNTL 0x0000a802
-#define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
-#define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT 0
-static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK;
-}
-#define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
-#define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
-static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
-}
-
-#define REG_A6XX_SP_VS_OUT(i0) (0x0000a803 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; }
-#define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
-#define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
-static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK;
-}
-#define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
-#define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
-static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
-}
-#define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
-#define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
-static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK;
-}
-#define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
-#define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
-static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
-}
-
-#define REG_A6XX_SP_VS_VPC_DST(i0) (0x0000a813 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; }
-#define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
-#define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
-static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
-}
-#define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
-#define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
-static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
-}
-#define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
-#define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
-static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
-}
-#define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
-#define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
-static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
-}
-
-#define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b
-
-#define REG_A6XX_SP_VS_OBJ_START 0x0000a81c
-
-#define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e
-#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
-#define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
-static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
-{
- assert(!(val & 0x1ff));
- return (((val >> 9)) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
-}
-#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
-#define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
-static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
-}
-
-#define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f
-
-#define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821
-#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
-#define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
-static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
-}
-#define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
-
-#define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822
-
-#define REG_A6XX_SP_VS_CONFIG 0x0000a823
-#define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001
-#define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002
-#define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004
-#define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008
-#define A6XX_SP_VS_CONFIG_ENABLED 0x00000100
-#define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00
-#define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9
-static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK;
-}
-#define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000
-#define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17
-static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK;
-}
-#define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000
-#define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22
-static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
-{
- return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK;
-}
-
-#define REG_A6XX_SP_VS_INSTRLEN 0x0000a824
-
-#define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825
-#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
-#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
-static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
-{
- assert(!(val & 0x7ff));
- return (((val >> 11)) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
-}
-
-#define REG_A7XX_SP_VS_VGPR_CONFIG 0x0000a82d
-
-#define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830
-#define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001
-#define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0
-static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
-{
- return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK;
-}
-#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
-#define A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
-static inline uint32_t A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
-#define A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
-static inline uint32_t A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000
-#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
-#define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14
-static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
-{
- return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
-}
-#define A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE 0x00100000
-
-#define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831
-
-#define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832
-
-#define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833
-
-#define REG_A6XX_SP_HS_OBJ_START 0x0000a834
-
-#define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836
-#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
-#define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
-static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
-{
- assert(!(val & 0x1ff));
- return (((val >> 9)) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
-}
-#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
-#define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
-static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
-{
- return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
-}
-
-#define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837
-
-#define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839
-#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
-#define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
-static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
-}
-#define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
-
-#define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a
-
-#define REG_A6XX_SP_HS_CONFIG 0x0000a83b
-#define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001
-#define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002
-#define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004
-#define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008
-#define A6XX_SP_HS_CONFIG_ENABLED 0x00000100
-#define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00
-#define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9
-static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val)
-{
- return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK;
-}
-#define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000
-#define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17
-static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val)
-{
- return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK;
-}
-#define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000
-#define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22
-static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
-{
- return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK;
-}
-
-#define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c
-
-#define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d
-#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
-#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
-static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
-{
- assert(!(val & 0x7ff));
- return (((val >> 11)) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
-}
-
-#define REG_A7XX_SP_HS_VGPR_CONFIG 0x0000a82f
-
-#define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840
-#define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001
-#define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0
-static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
-{
- return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK;
-}
-#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
-#define A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
-static inline uint32_t A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
-#define A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
-static inline uint32_t A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000
-#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
-#define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14
-static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
-}
-#define A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE 0x00100000
-
-#define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841
-
-#define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842
-#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
-#define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT 0
-static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK;
-}
-#define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
-#define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
-static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
-}
-
-#define REG_A6XX_SP_DS_OUT(i0) (0x0000a843 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; }
-#define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff
-#define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
-static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK;
-}
-#define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00
-#define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8
-static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
-}
-#define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000
-#define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
-static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK;
-}
-#define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000
-#define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24
-static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
-}
-
-#define REG_A6XX_SP_DS_VPC_DST(i0) (0x0000a853 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; }
-#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
-#define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
-static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
-}
-#define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
-#define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
-static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
-}
-#define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
-#define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
-static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
-}
-#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
-#define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
-static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
-}
-
-#define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b
-
-#define REG_A6XX_SP_DS_OBJ_START 0x0000a85c
-
-#define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e
-#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
-#define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
-static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
-{
- assert(!(val & 0x1ff));
- return (((val >> 9)) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
-}
-#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
-#define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
-static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
-}
-
-#define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f
-
-#define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861
-#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
-#define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
-static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
-}
-#define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
-
-#define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862
-
-#define REG_A6XX_SP_DS_CONFIG 0x0000a863
-#define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001
-#define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002
-#define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004
-#define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008
-#define A6XX_SP_DS_CONFIG_ENABLED 0x00000100
-#define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00
-#define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9
-static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK;
-}
-#define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000
-#define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17
-static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK;
-}
-#define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000
-#define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22
-static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
-{
- return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK;
-}
-
-#define REG_A6XX_SP_DS_INSTRLEN 0x0000a864
-
-#define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865
-#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
-#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
-static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
-{
- assert(!(val & 0x7ff));
- return (((val >> 11)) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
-}
-
-#define REG_A7XX_SP_DS_VGPR_CONFIG 0x0000a868
-
-#define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870
-#define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001
-#define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0
-static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
-{
- return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK;
-}
-#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
-#define A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
-static inline uint32_t A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
-#define A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
-static inline uint32_t A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000
-#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
-#define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14
-static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
-}
-#define A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE 0x00100000
-
-#define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871
-
-#define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872
-
-#define REG_A6XX_SP_GS_PRIMITIVE_CNTL 0x0000a873
-#define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f
-#define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT 0
-static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK;
-}
-#define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0
-#define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6
-static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK;
-}
-
-#define REG_A6XX_SP_GS_OUT(i0) (0x0000a874 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; }
-#define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff
-#define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
-static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK;
-}
-#define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00000f00
-#define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 8
-static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
-}
-#define A6XX_SP_GS_OUT_REG_B_REGID__MASK 0x00ff0000
-#define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
-static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK;
-}
-#define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x0f000000
-#define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 24
-static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
-}
-
-#define REG_A6XX_SP_GS_VPC_DST(i0) (0x0000a884 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; }
-#define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
-#define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
-static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
-}
-#define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
-#define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
-static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
-}
-#define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
-#define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
-static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
-}
-#define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
-#define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
-static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
-}
-
-#define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c
-
-#define REG_A6XX_SP_GS_OBJ_START 0x0000a88d
-
-#define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f
-#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
-#define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
-static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
-{
- assert(!(val & 0x1ff));
- return (((val >> 9)) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
-}
-#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
-#define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
-static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
-}
-
-#define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890
-
-#define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892
-#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
-#define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
-static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
-}
-#define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
-
-#define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893
-
-#define REG_A6XX_SP_GS_CONFIG 0x0000a894
-#define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001
-#define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002
-#define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004
-#define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008
-#define A6XX_SP_GS_CONFIG_ENABLED 0x00000100
-#define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00
-#define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9
-static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK;
-}
-#define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000
-#define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17
-static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK;
-}
-#define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000
-#define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22
-static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
-{
- return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK;
-}
-
-#define REG_A6XX_SP_GS_INSTRLEN 0x0000a895
-
-#define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896
-#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
-#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
-static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
-{
- assert(!(val & 0x7ff));
- return (((val >> 11)) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
-}
-
-#define REG_A7XX_SP_GS_VGPR_CONFIG 0x0000a899
-
-#define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0
-
-#define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2
-
-#define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4
-
-#define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6
-
-#define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8
-
-#define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa
-
-#define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac
-
-#define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae
-
-#define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980
-#define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
-#define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
-static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
-{
- return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
-}
-#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
-#define A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
-static inline uint32_t A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
-#define A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
-static inline uint32_t A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000
-#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
-#define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14
-static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
-}
-#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
-#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
-static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
-{
- return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
-}
-#define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000
-#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000
-#define A6XX_SP_FS_CTRL_REG0_LODPIXMASK 0x00800000
-#define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000
-#define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000
-#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000
-#define A6XX_SP_FS_CTRL_REG0_UNK27 0x08000000
-#define A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE 0x10000000
-#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000
-
-#define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981
-
-#define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982
-
-#define REG_A6XX_SP_FS_OBJ_START 0x0000a983
-
-#define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985
-#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
-#define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
-static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
-{
- assert(!(val & 0x1ff));
- return (((val >> 9)) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
-}
-#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
-#define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
-static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
-}
-
-#define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986
-
-#define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988
-#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
-#define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
-static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
-}
-#define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
-
-#define REG_A6XX_SP_BLEND_CNTL 0x0000a989
-#define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
-#define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
-static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
-{
- return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
-}
-#define A6XX_SP_BLEND_CNTL_UNK8 0x00000100
-#define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200
-#define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
-
-#define REG_A6XX_SP_SRGB_CNTL 0x0000a98a
-#define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001
-#define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002
-#define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004
-#define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008
-#define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010
-#define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020
-#define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040
-#define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080
-
-#define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b
-#define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f
-#define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0
-static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK;
-}
-#define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0
-#define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4
-static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK;
-}
-#define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00
-#define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8
-static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK;
-}
-#define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000
-#define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12
-static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK;
-}
-#define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000
-#define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16
-static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK;
-}
-#define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000
-#define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20
-static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK;
-}
-#define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000
-#define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24
-static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK;
-}
-#define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000
-#define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28
-static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK;
-}
-
-#define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c
-#define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001
-#define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00
-#define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8
-static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK;
-}
-#define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000
-#define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16
-static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK;
-}
-#define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK 0xff000000
-#define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT 24
-static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK;
-}
-
-#define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d
-#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f
-#define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0
-static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK;
-}
-
-#define REG_A6XX_SP_FS_OUTPUT(i0) (0x0000a98e + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; }
-#define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
-#define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
-static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK;
-}
-#define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
-
-#define REG_A6XX_SP_FS_MRT(i0) (0x0000a996 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; }
-#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
-#define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
-static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val)
-{
- return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
-}
-#define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
-#define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
-#define A6XX_SP_FS_MRT_REG_UNK10 0x00000400
-
-#define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e
-#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007
-#define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0
-static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK;
-}
-#define A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE 0x00000008
-#define A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD 0x00000010
-#define A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT 0x00000020
-#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK 0x00007fc0
-#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT 6
-static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK;
-}
-#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK 0x01ff0000
-#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT 16
-static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK;
-}
-
-#define REG_A6XX_SP_FS_PREFETCH(i0) (0x0000a99f + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
-#define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f
-#define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0
-static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK;
-}
-#define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000780
-#define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7
-static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK;
-}
-#define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x0000f800
-#define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 11
-static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK;
-}
-#define A6XX_SP_FS_PREFETCH_CMD_DST__MASK 0x003f0000
-#define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT 16
-static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK;
-}
-#define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x03c00000
-#define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 22
-static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK;
-}
-#define A6XX_SP_FS_PREFETCH_CMD_HALF 0x04000000
-#define A6XX_SP_FS_PREFETCH_CMD_UNK27 0x08000000
-#define A6XX_SP_FS_PREFETCH_CMD_BINDLESS 0x10000000
-#define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK 0xe0000000
-#define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 29
-static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val)
-{
- return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK;
-}
-
-#define REG_A7XX_SP_FS_PREFETCH(i0) (0x0000a99f + 0x1*(i0))
-
-static inline uint32_t REG_A7XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; }
-#define A7XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f
-#define A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0
-static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val)
-{
- return ((val) << A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SRC__MASK;
-}
-#define A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000380
-#define A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7
-static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val)
-{
- return ((val) << A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK;
-}
-#define A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x00001c00
-#define A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 10
-static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val)
-{
- return ((val) << A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK;
-}
-#define A7XX_SP_FS_PREFETCH_CMD_DST__MASK 0x0007e000
-#define A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT 13
-static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_DST(uint32_t val)
-{
- return ((val) << A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_DST__MASK;
-}
-#define A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x00780000
-#define A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 19
-static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val)
-{
- return ((val) << A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK;
-}
-#define A7XX_SP_FS_PREFETCH_CMD_HALF 0x00800000
-#define A7XX_SP_FS_PREFETCH_CMD_BINDLESS 0x02000000
-#define A7XX_SP_FS_PREFETCH_CMD_CMD__MASK 0x3c000000
-#define A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 26
-static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val)
-{
- return ((val) << A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_CMD__MASK;
-}
-
-#define REG_A6XX_SP_FS_BINDLESS_PREFETCH(i0) (0x0000a9a3 + 0x1*(i0))
-
-static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; }
-#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff
-#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0
-static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK;
-}
-#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000
-#define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16
-static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK;
-}
-
-#define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7
-
-#define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8
-
-#define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9
-#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
-#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
-static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
-{
- assert(!(val & 0x7ff));
- return (((val >> 11)) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
-}
-
-#define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
-#define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001
-#define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0
-static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
-{
- return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK;
-}
-#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x0000007e
-#define A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 1
-static inline uint32_t A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
-}
-#define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x00001f80
-#define A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 7
-static inline uint32_t A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
-{
- return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
-}
-#define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000
-#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000
-#define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14
-static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
-{
- return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
-}
-#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
-#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
-static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val)
-{
- return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
-}
-#define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000
-#define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000
-#define A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE 0x00800000
-#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000
-
-#define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1
-#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f
-#define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0
-static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val)
-{
- return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK;
-}
-#define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020
-#define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040
-
-#define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2
-
-#define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3
-
-#define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4
-
-#define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6
-#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
-#define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
-static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
-{
- assert(!(val & 0x1ff));
- return (((val >> 9)) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
-}
-#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
-#define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
-static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
-{
- return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
-}
-
-#define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7
-
-#define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9
-#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
-#define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
-static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
-}
-#define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000
-
-#define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba
-
-#define REG_A6XX_SP_CS_CONFIG 0x0000a9bb
-#define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001
-#define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002
-#define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004
-#define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008
-#define A6XX_SP_CS_CONFIG_ENABLED 0x00000100
-#define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00
-#define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9
-static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val)
-{
- return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK;
-}
-#define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000
-#define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17
-static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val)
-{
- return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK;
-}
-#define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000
-#define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22
-static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
-{
- return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK;
-}
-
-#define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc
-
-#define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd
-#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
-#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
-static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
-{
- assert(!(val & 0x7ff));
- return (((val >> 11)) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
-}
-
-#define REG_A7XX_SP_CS_UNKNOWN_A9BE 0x0000a9be
-
-#define REG_A7XX_SP_CS_VGPR_CONFIG 0x0000a9c5
-
-#define REG_A6XX_SP_CS_CNTL_0 0x0000a9c2
-#define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
-#define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT 0
-static inline uint32_t A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val)
-{
- return ((val) << A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK;
-}
-#define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00
-#define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT 8
-static inline uint32_t A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val)
-{
- return ((val) << A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK;
-}
-#define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000
-#define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16
-static inline uint32_t A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)
-{
- return ((val) << A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK;
-}
-#define A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
-#define A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT 24
-static inline uint32_t A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val)
-{
- return ((val) << A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK;
-}
-
-#define REG_A6XX_SP_CS_CNTL_1 0x0000a9c3
-#define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff
-#define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0
-static inline uint32_t A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
-{
- return ((val) << A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
-}
-#define A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE 0x00000100
-#define A6XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000200
-#define A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 9
-static inline uint32_t A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
-{
- return ((val) << A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_SP_CS_CNTL_1_THREADSIZE__MASK;
-}
-#define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400
-
-#define REG_A7XX_SP_CS_CNTL_1 0x0000a9c3
-#define A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff
-#define A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0
-static inline uint32_t A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
-{
- return ((val) << A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
-}
-#define A7XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000100
-#define A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 8
-static inline uint32_t A7XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
-{
- return ((val) << A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_SP_CS_CNTL_1_THREADSIZE__MASK;
-}
-#define A7XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000200
-#define A7XX_SP_CS_CNTL_1_UNK15 0x00008000
-
-#define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0
-
-#define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2
-
-#define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4
-
-#define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6
-
-#define REG_A6XX_SP_CS_BINDLESS_BASE(i0) (0x0000a9e8 + 0x2*(i0))
-
-static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
-#define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003
-#define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0
-static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)
-{
- return ((val) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK;
-}
-#define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc
-#define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2
-static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
-}
-
-#define REG_A7XX_SP_CS_BINDLESS_BASE(i0) (0x0000a9e8 + 0x2*(i0))
-
-static inline uint32_t REG_A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; }
-#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003
-#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0
-static inline uint32_t A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)
-{
- return ((val) << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK;
-}
-#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc
-#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2
-static inline uint32_t A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
-}
-
-#define REG_A6XX_SP_CS_IBO 0x0000a9f2
-
-#define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00
-
-#define REG_A7XX_SP_FS_VGPR_CONFIG 0x0000aa01
-
-#define REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL 0x0000aa02
-#define A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL_ENABLED 0x00000001
-
-#define REG_A7XX_SP_PS_ALIASED_COMPONENTS 0x0000aa03
-#define A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK 0x0000000f
-#define A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT 0
-static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT0(uint32_t val)
-{
- return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK;
-}
-#define A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK 0x000000f0
-#define A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT 4
-static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT1(uint32_t val)
-{
- return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK;
-}
-#define A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK 0x00000f00
-#define A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT 8
-static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT2(uint32_t val)
-{
- return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK;
-}
-#define A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK 0x0000f000
-#define A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT 12
-static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT3(uint32_t val)
-{
- return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK;
-}
-#define A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK 0x000f0000
-#define A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT 16
-static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT4(uint32_t val)
-{
- return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK;
-}
-#define A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK 0x00f00000
-#define A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT 20
-static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT5(uint32_t val)
-{
- return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK;
-}
-#define A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK 0x0f000000
-#define A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT 24
-static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT6(uint32_t val)
-{
- return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK;
-}
-#define A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK 0xf0000000
-#define A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT 28
-static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT7(uint32_t val)
-{
- return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK;
-}
-
-#define REG_A6XX_SP_UNKNOWN_AAF2 0x0000aaf2
-
-#define REG_A6XX_SP_MODE_CONTROL 0x0000ab00
-#define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001
-#define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK 0x00000006
-#define A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT 1
-static inline uint32_t A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val)
-{
- return ((val) << A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT) & A6XX_SP_MODE_CONTROL_ISAMMODE__MASK;
-}
-#define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008
-
-#define REG_A7XX_SP_UNKNOWN_AB01 0x0000ab01
-
-#define REG_A7XX_SP_UNKNOWN_AB02 0x0000ab02
-
-#define REG_A6XX_SP_FS_CONFIG 0x0000ab04
-#define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001
-#define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002
-#define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004
-#define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008
-#define A6XX_SP_FS_CONFIG_ENABLED 0x00000100
-#define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00
-#define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9
-static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK;
-}
-#define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000
-#define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17
-static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK;
-}
-#define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000
-#define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22
-static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val)
-{
- return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK;
-}
-
-#define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05
-
-#define REG_A6XX_SP_BINDLESS_BASE(i0) (0x0000ab10 + 0x2*(i0))
-
-static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; }
-#define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003
-#define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0
-static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)
-{
- return ((val) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK;
-}
-#define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc
-#define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2
-static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
-}
-
-#define REG_A7XX_SP_BINDLESS_BASE(i0) (0x0000ab0a + 0x2*(i0))
-
-static inline uint32_t REG_A7XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000ab0a + 0x2*i0; }
-#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003
-#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0
-static inline uint32_t A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)
-{
- return ((val) << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK;
-}
-#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc
-#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2
-static inline uint32_t A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
-}
-
-#define REG_A6XX_SP_IBO 0x0000ab1a
-
-#define REG_A6XX_SP_IBO_COUNT 0x0000ab20
-
-#define REG_A7XX_SP_UNKNOWN_AB22 0x0000ab22
-
-#define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0
-#define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001
-#define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002
-#define A6XX_SP_2D_DST_FORMAT_UINT 0x00000004
-#define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8
-#define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3
-static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val)
-{
- return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK;
-}
-#define A6XX_SP_2D_DST_FORMAT_SRGB 0x00000800
-#define A6XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000
-#define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT 12
-static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val)
-{
- return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK;
-}
-
-#define REG_A7XX_SP_2D_DST_FORMAT 0x0000a9bf
-#define A7XX_SP_2D_DST_FORMAT_NORM 0x00000001
-#define A7XX_SP_2D_DST_FORMAT_SINT 0x00000002
-#define A7XX_SP_2D_DST_FORMAT_UINT 0x00000004
-#define A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8
-#define A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3
-static inline uint32_t A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val)
-{
- return ((val) << A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK;
-}
-#define A7XX_SP_2D_DST_FORMAT_SRGB 0x00000800
-#define A7XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000
-#define A7XX_SP_2D_DST_FORMAT_MASK__SHIFT 12
-static inline uint32_t A7XX_SP_2D_DST_FORMAT_MASK(uint32_t val)
-{
- return ((val) << A7XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A7XX_SP_2D_DST_FORMAT_MASK__MASK;
-}
-
-#define REG_A6XX_SP_DBG_ECO_CNTL 0x0000ae00
-
-#define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01
-
-#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
-
-#define REG_A6XX_SP_CHICKEN_BITS 0x0000ae03
-
-#define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04
-#define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008
-
-#define REG_A7XX_SP_UNKNOWN_AE06 0x0000ae06
-
-#define REG_A7XX_SP_UNKNOWN_AE08 0x0000ae08
-
-#define REG_A7XX_SP_UNKNOWN_AE09 0x0000ae09
-
-#define REG_A7XX_SP_UNKNOWN_AE0A 0x0000ae0a
-
-#define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f
-#define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001
-#define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002
-#define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004
-#define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008
-#define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010
-#define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020
-
-#define REG_A6XX_SP_PERFCTR_SP_SEL(i0) (0x0000ae10 + 0x1*(i0))
-
-#define REG_A7XX_SP_PERFCTR_HLSQ_SEL(i0) (0x0000ae60 + 0x1*(i0))
-
-#define REG_A7XX_SP_UNKNOWN_AE6A 0x0000ae6a
-
-#define REG_A7XX_SP_UNKNOWN_AE6B 0x0000ae6b
-
-#define REG_A7XX_SP_UNKNOWN_AE6C 0x0000ae6c
-
-#define REG_A7XX_SP_READ_SEL 0x0000ae6d
-#define A7XX_SP_READ_SEL_LOCATION__MASK 0x000c0000
-#define A7XX_SP_READ_SEL_LOCATION__SHIFT 18
-static inline uint32_t A7XX_SP_READ_SEL_LOCATION(enum a7xx_state_location val)
-{
- return ((val) << A7XX_SP_READ_SEL_LOCATION__SHIFT) & A7XX_SP_READ_SEL_LOCATION__MASK;
-}
-#define A7XX_SP_READ_SEL_PIPE__MASK 0x00030000
-#define A7XX_SP_READ_SEL_PIPE__SHIFT 16
-static inline uint32_t A7XX_SP_READ_SEL_PIPE(enum a7xx_pipe val)
-{
- return ((val) << A7XX_SP_READ_SEL_PIPE__SHIFT) & A7XX_SP_READ_SEL_PIPE__MASK;
-}
-#define A7XX_SP_READ_SEL_STATETYPE__MASK 0x0000ff00
-#define A7XX_SP_READ_SEL_STATETYPE__SHIFT 8
-static inline uint32_t A7XX_SP_READ_SEL_STATETYPE(enum a7xx_statetype_id val)
-{
- return ((val) << A7XX_SP_READ_SEL_STATETYPE__SHIFT) & A7XX_SP_READ_SEL_STATETYPE__MASK;
-}
-#define A7XX_SP_READ_SEL_USPTP__MASK 0x000000f0
-#define A7XX_SP_READ_SEL_USPTP__SHIFT 4
-static inline uint32_t A7XX_SP_READ_SEL_USPTP(uint32_t val)
-{
- return ((val) << A7XX_SP_READ_SEL_USPTP__SHIFT) & A7XX_SP_READ_SEL_USPTP__MASK;
-}
-#define A7XX_SP_READ_SEL_SPTP__MASK 0x0000000f
-#define A7XX_SP_READ_SEL_SPTP__SHIFT 0
-static inline uint32_t A7XX_SP_READ_SEL_SPTP(uint32_t val)
-{
- return ((val) << A7XX_SP_READ_SEL_SPTP__SHIFT) & A7XX_SP_READ_SEL_SPTP__MASK;
-}
-
-#define REG_A7XX_SP_DBG_CNTL 0x0000ae71
-
-#define REG_A7XX_SP_UNKNOWN_AE73 0x0000ae73
-
-#define REG_A7XX_SP_PERFCTR_SP_SEL(i0) (0x0000ae80 + 0x1*(i0))
-
-#define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22
-
-#define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180
-
-#define REG_A6XX_SP_UNKNOWN_B182 0x0000b182
-
-#define REG_A6XX_SP_UNKNOWN_B183 0x0000b183
-
-#define REG_A6XX_SP_UNKNOWN_B190 0x0000b190
-
-#define REG_A6XX_SP_UNKNOWN_B191 0x0000b191
-
-#define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300
-#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
-#define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
-static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
-}
-#define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c
-#define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2
-static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val)
-{
- return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK;
-}
-
-#define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301
-#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
-#define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
-static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
-}
-#define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
-
-#define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302
-
-#define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304
-#define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001
-#define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002
-
-#define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305
-#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f
-#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0
-static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK;
-}
-#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0
-#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4
-static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK;
-}
-#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00
-#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8
-static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK;
-}
-#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000
-#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12
-static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK;
-}
-#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000
-#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16
-static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK;
-}
-#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000
-#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20
-static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK;
-}
-#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000
-#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24
-static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK;
-}
-#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000
-#define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28
-static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK;
-}
-
-#define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306
-#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f
-#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0
-static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK;
-}
-#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0
-#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4
-static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK;
-}
-#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00
-#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8
-static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK;
-}
-#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000
-#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12
-static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK;
-}
-#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000
-#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16
-static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK;
-}
-#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000
-#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20
-static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK;
-}
-#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000
-#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24
-static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK;
-}
-#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000
-#define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28
-static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
-{
- return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK;
-}
-
-#define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307
-#define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff
-#define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0
-static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val)
-{
- return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK;
-}
-#define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000
-#define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16
-static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
-{
- return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
-}
-
-#define REG_A6XX_SP_TP_MODE_CNTL 0x0000b309
-#define A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK 0x00000003
-#define A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT 0
-static inline uint32_t A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val)
-{
- return ((val) << A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT) & A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK;
-}
-#define A6XX_SP_TP_MODE_CNTL_UNK3__MASK 0x000000fc
-#define A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT 2
-static inline uint32_t A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val)
-{
- return ((val) << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK;
-}
-
-#define REG_A7XX_SP_UNKNOWN_B310 0x0000b310
-
-#define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
-#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
-#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
-static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)
-{
- return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;
-}
-#define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
-#define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8
-static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)
-{
- return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK;
-}
-#define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
-#define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
-static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
-}
-#define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000
-#define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000
-#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000
-#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14
-static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
-}
-#define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
-#define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000
-#define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000
-#define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000
-#define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000
-#define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000
-#define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000
-#define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000
-#define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23
-static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val)
-{
- return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK;
-}
-#define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000
-
-#define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1
-#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
-#define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0
-static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
-{
- return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK;
-}
-#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000
-#define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15
-static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
-{
- return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
-}
-
-#define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2
-
-#define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4
-#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff
-#define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0
-static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val)
-{
- return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK;
-}
-#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00
-#define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
-static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
-}
-
-#define REG_A7XX_SP_PS_2D_SRC_INFO 0x0000b2c0
-#define A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
-#define A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
-static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val)
-{
- return ((val) << A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK;
-}
-#define A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
-#define A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8
-static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val)
-{
- return ((val) << A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK;
-}
-#define A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
-#define A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
-static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK;
-}
-#define A7XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000
-#define A7XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000
-#define A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000
-#define A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14
-static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK;
-}
-#define A7XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000
-#define A7XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000
-#define A7XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000
-#define A7XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000
-#define A7XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000
-#define A7XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000
-#define A7XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000
-#define A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000
-#define A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23
-static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val)
-{
- return ((val) << A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK;
-}
-#define A7XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000
-
-#define REG_A7XX_SP_PS_2D_SRC_SIZE 0x0000b2c1
-#define A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff
-#define A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0
-static inline uint32_t A7XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val)
-{
- return ((val) << A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK;
-}
-#define A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000
-#define A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15
-static inline uint32_t A7XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val)
-{
- return ((val) << A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK;
-}
-
-#define REG_A7XX_SP_PS_2D_SRC 0x0000b2c2
-
-#define REG_A7XX_SP_PS_2D_SRC_PITCH 0x0000b2c4
-#define A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff
-#define A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0
-static inline uint32_t A7XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val)
-{
- return ((val) << A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK;
-}
-#define A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00
-#define A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9
-static inline uint32_t A7XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK;
-}
-
-#define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5
-
-#define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7
-#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff
-#define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0
-static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK;
-}
-
-#define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8
-
-#define REG_A7XX_SP_PS_2D_SRC_PLANE1 0x0000b2c5
-
-#define REG_A7XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b2c7
-#define A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff
-#define A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0
-static inline uint32_t A7XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK;
-}
-
-#define REG_A7XX_SP_PS_2D_SRC_PLANE2 0x0000b2c8
-
-#define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca
-
-#define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc
-#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff
-#define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0
-static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK;
-}
-
-#define REG_A7XX_SP_PS_2D_SRC_FLAGS 0x0000b2ca
-
-#define REG_A7XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b2cc
-#define A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff
-#define A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0
-static inline uint32_t A7XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK;
-}
-
-#define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd
-
-#define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce
-
-#define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf
-
-#define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0
-
-#define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1
-#define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff
-#define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0
-static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val)
-{
- return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK;
-}
-#define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000
-#define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16
-static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
-{
- return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
-}
-
-#define REG_A7XX_SP_PS_UNKNOWN_B4CD 0x0000b2cd
-
-#define REG_A7XX_SP_PS_UNKNOWN_B4CE 0x0000b2ce
-
-#define REG_A7XX_SP_PS_UNKNOWN_B4CF 0x0000b2cf
-
-#define REG_A7XX_SP_PS_UNKNOWN_B4D0 0x0000b2d0
-
-#define REG_A7XX_SP_PS_2D_WINDOW_OFFSET 0x0000b2d1
-#define A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK 0x00003fff
-#define A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT 0
-static inline uint32_t A7XX_SP_PS_2D_WINDOW_OFFSET_X(uint32_t val)
-{
- return ((val) << A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK;
-}
-#define A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK 0x3fff0000
-#define A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT 16
-static inline uint32_t A7XX_SP_PS_2D_WINDOW_OFFSET_Y(uint32_t val)
-{
- return ((val) << A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK;
-}
-
-#define REG_A7XX_SP_PS_UNKNOWN_B2D2 0x0000b2d2
-
-#define REG_A7XX_SP_WINDOW_OFFSET 0x0000ab21
-#define A7XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff
-#define A7XX_SP_WINDOW_OFFSET_X__SHIFT 0
-static inline uint32_t A7XX_SP_WINDOW_OFFSET_X(uint32_t val)
-{
- return ((val) << A7XX_SP_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_WINDOW_OFFSET_X__MASK;
-}
-#define A7XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000
-#define A7XX_SP_WINDOW_OFFSET_Y__SHIFT 16
-static inline uint32_t A7XX_SP_WINDOW_OFFSET_Y(uint32_t val)
-{
- return ((val) << A7XX_SP_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_WINDOW_OFFSET_Y__MASK;
-}
-
-#define REG_A6XX_TPL1_DBG_ECO_CNTL 0x0000b600
-
-#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
-
-#define REG_A6XX_TPL1_UNKNOWN_B602 0x0000b602
-
-#define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604
-#define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001
-#define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006
-#define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1
-static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val)
-{
- return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK;
-}
-#define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008
-#define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010
-#define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4
-static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val)
-{
- return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK;
-}
-#define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0
-#define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6
-static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val)
-{
- return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK;
-}
-
-#define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605
-
-#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608
-
-#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609
-
-#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a
-
-#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b
-
-#define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c
-
-#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608
-
-#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609
-
-#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a
-
-#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b
-
-#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c
-
-#define REG_A6XX_TPL1_PERFCTR_TP_SEL(i0) (0x0000b610 + 0x1*(i0))
-
-#define REG_A6XX_HLSQ_VS_CNTL 0x0000b800
-#define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff
-#define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0
-static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
-}
-#define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100
-#define A6XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
-
-#define REG_A6XX_HLSQ_HS_CNTL 0x0000b801
-#define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff
-#define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0
-static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
-}
-#define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100
-#define A6XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
-
-#define REG_A6XX_HLSQ_DS_CNTL 0x0000b802
-#define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff
-#define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0
-static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
-}
-#define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100
-#define A6XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
-
-#define REG_A6XX_HLSQ_GS_CNTL 0x0000b803
-#define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff
-#define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0
-static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
-}
-#define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100
-#define A6XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
-
-#define REG_A7XX_HLSQ_VS_CNTL 0x0000a827
-#define A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff
-#define A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0
-static inline uint32_t A7XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK;
-}
-#define A7XX_HLSQ_VS_CNTL_ENABLED 0x00000100
-#define A7XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
-
-#define REG_A7XX_HLSQ_HS_CNTL 0x0000a83f
-#define A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff
-#define A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0
-static inline uint32_t A7XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK;
-}
-#define A7XX_HLSQ_HS_CNTL_ENABLED 0x00000100
-#define A7XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
-
-#define REG_A7XX_HLSQ_DS_CNTL 0x0000a867
-#define A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff
-#define A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0
-static inline uint32_t A7XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK;
-}
-#define A7XX_HLSQ_DS_CNTL_ENABLED 0x00000100
-#define A7XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
-
-#define REG_A7XX_HLSQ_GS_CNTL 0x0000a898
-#define A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff
-#define A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0
-static inline uint32_t A7XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK;
-}
-#define A7XX_HLSQ_GS_CNTL_ENABLED 0x00000100
-#define A7XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
-
-#define REG_A7XX_HLSQ_FS_UNKNOWN_A9AA 0x0000a9aa
-#define A7XX_HLSQ_FS_UNKNOWN_A9AA_CONSTS_LOAD_DISABLE 0x00000001
-
-#define REG_A7XX_HLSQ_UNKNOWN_A9AC 0x0000a9ac
-
-#define REG_A7XX_HLSQ_UNKNOWN_A9AD 0x0000a9ad
-
-#define REG_A7XX_HLSQ_UNKNOWN_A9AE 0x0000a9ae
-#define A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK 0x000000ff
-#define A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT 0
-static inline uint32_t A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT) & A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK;
-}
-#define A7XX_HLSQ_UNKNOWN_A9AE_UNK8 0x00000100
-#define A7XX_HLSQ_UNKNOWN_A9AE_UNK9 0x00000200
-
-#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820
-
-#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821
-
-#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823
-
-#define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980
-#define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001
-#define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0
-static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val)
-{
- return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK;
-}
-#define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002
-#define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc
-#define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2
-static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK;
-}
-
-#define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981
-
-#define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982
-#define A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x00000007
-#define A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK;
-}
-
-#define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983
-#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
-#define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
-}
-#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
-#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
-static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
-}
-#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
-#define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
-static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
-}
-#define A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000
-#define A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24
-static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK;
-}
-
-#define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984
-#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
-#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
-}
-#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
-#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
-static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
-}
-#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
-#define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
-static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
-}
-#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
-#define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
-static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
-}
-
-#define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985
-#define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
-#define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
-}
-#define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
-#define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
-static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
-}
-#define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
-#define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
-static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
-}
-#define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
-#define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
-static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
-}
-
-#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
-#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff
-#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK;
-}
-#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00
-#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8
-static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK;
-}
-
-#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987
-#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff
-#define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
-}
-#define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100
-#define A6XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
-
-#define REG_A7XX_HLSQ_FS_CNTL_0 0x0000a9c6
-#define A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001
-#define A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0
-static inline uint32_t A7XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val)
-{
- return ((val) << A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK;
-}
-#define A7XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002
-#define A7XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc
-#define A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2
-static inline uint32_t A7XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A7XX_HLSQ_FS_CNTL_0_UNK2__MASK;
-}
-
-#define REG_A7XX_HLSQ_CONTROL_1_REG 0x0000a9c7
-#define A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x00000007
-#define A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0
-static inline uint32_t A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK;
-}
-
-#define REG_A7XX_HLSQ_CONTROL_2_REG 0x0000a9c8
-#define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
-#define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
-static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
-}
-#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
-#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
-static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
-}
-#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
-#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
-static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
-}
-#define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000
-#define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24
-static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK;
-}
-
-#define REG_A7XX_HLSQ_CONTROL_3_REG 0x0000a9c9
-#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
-#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
-static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
-}
-#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
-#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
-static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
-}
-#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
-#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
-static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
-}
-#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
-#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
-static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
-}
-
-#define REG_A7XX_HLSQ_CONTROL_4_REG 0x0000a9ca
-#define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
-#define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
-static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
-}
-#define A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
-#define A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
-static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
-}
-#define A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
-#define A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
-static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
-}
-#define A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
-#define A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
-static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
-}
-
-#define REG_A7XX_HLSQ_CONTROL_5_REG 0x0000a9cb
-#define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff
-#define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0
-static inline uint32_t A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK;
-}
-#define A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00
-#define A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8
-static inline uint32_t A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK;
-}
-
-#define REG_A7XX_HLSQ_CS_CNTL 0x0000a9cd
-#define A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff
-#define A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0
-static inline uint32_t A7XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK;
-}
-#define A7XX_HLSQ_CS_CNTL_ENABLED 0x00000100
-#define A7XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
-
-#define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990
-#define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
-#define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
-}
-#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
-#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
-static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
-}
-#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
-#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
-static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
-}
-#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
-#define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
-static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
-}
-
-#define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991
-#define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff
-#define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
-}
-
-#define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992
-#define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff
-#define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
-}
-
-#define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993
-#define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff
-#define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
-}
-
-#define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994
-#define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff
-#define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
-}
-
-#define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995
-#define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff
-#define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
-}
-
-#define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996
-#define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff
-#define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
-}
-
-#define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997
-#define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
-#define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
-}
-#define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00
-#define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8
-static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK;
-}
-#define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000
-#define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16
-static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK;
-}
-#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
-#define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
-static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
-}
-
-#define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998
-#define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff
-#define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
-}
-#define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100
-#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200
-#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9
-static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
-{
- return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK;
-}
-#define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400
-
-#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999
-
-#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a
-
-#define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b
-
-#define REG_A7XX_HLSQ_CS_NDRANGE_0 0x0000a9d4
-#define A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
-#define A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
-static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
-}
-#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
-#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
-static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
-}
-#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
-#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
-static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
-}
-#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
-#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
-static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
-}
-
-#define REG_A7XX_HLSQ_CS_NDRANGE_1 0x0000a9d5
-#define A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff
-#define A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0
-static inline uint32_t A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
-}
-
-#define REG_A7XX_HLSQ_CS_NDRANGE_2 0x0000a9d6
-#define A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff
-#define A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0
-static inline uint32_t A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
-}
-
-#define REG_A7XX_HLSQ_CS_NDRANGE_3 0x0000a9d7
-#define A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff
-#define A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0
-static inline uint32_t A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
-}
-
-#define REG_A7XX_HLSQ_CS_NDRANGE_4 0x0000a9d8
-#define A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff
-#define A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0
-static inline uint32_t A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
-}
-
-#define REG_A7XX_HLSQ_CS_NDRANGE_5 0x0000a9d9
-#define A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff
-#define A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0
-static inline uint32_t A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
-}
-
-#define REG_A7XX_HLSQ_CS_NDRANGE_6 0x0000a9da
-#define A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff
-#define A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0
-static inline uint32_t A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
-}
-
-#define REG_A7XX_HLSQ_CS_KERNEL_GROUP_X 0x0000a9dc
-
-#define REG_A7XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000a9dd
-
-#define REG_A7XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000a9de
-
-#define REG_A7XX_HLSQ_CS_CNTL_1 0x0000a9db
-#define A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff
-#define A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0
-static inline uint32_t A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
-}
-#define A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200
-#define A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9
-static inline uint32_t A7XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
-{
- return ((val) << A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK;
-}
-#define A7XX_HLSQ_CS_CNTL_1_UNK11 0x00000800
-#define A7XX_HLSQ_CS_CNTL_1_UNK22 0x00400000
-#define A7XX_HLSQ_CS_CNTL_1_UNK26 0x04000000
-#define A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK 0x78000000
-#define A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT 27
-static inline uint32_t A7XX_HLSQ_CS_CNTL_1_YALIGN(enum a7xx_cs_yalign val)
-{
- return ((val) << A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT) & A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK;
-}
-
-#define REG_A7XX_HLSQ_CS_LOCAL_SIZE 0x0000a9df
-#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK 0x00000ffc
-#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT 2
-static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK;
-}
-#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK 0x003ff000
-#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT 12
-static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK;
-}
-#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK 0xffc00000
-#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT 22
-static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK;
-}
-
-#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0
-
-#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1
-
-#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3
-
-#define REG_A6XX_HLSQ_CS_BINDLESS_BASE(i0) (0x0000b9c0 + 0x2*(i0))
-
-static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
-#define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003
-#define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)
-{
- return ((val) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK;
-}
-#define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc
-#define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2
-static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
-}
-
-#define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 0x0000b9d0
-#define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK 0x0000001f
-#define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT) & A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK;
-}
-#define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 0x00000020
-#define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 0x00000040
-
-#define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00
-#define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff
-#define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0
-static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK;
-}
-
-#define REG_A6XX_HLSQ_DISPATCH_CMD 0x0000bb01
-#define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK 0x000000ff
-#define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT 0
-static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK;
-}
-
-#define REG_A6XX_HLSQ_EVENT_CMD 0x0000bb02
-#define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK 0x00ff0000
-#define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT 16
-static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK;
-}
-#define A6XX_HLSQ_EVENT_CMD_EVENT__MASK 0x0000007f
-#define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT 0
-static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val)
-{
- return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK;
-}
-
-#define REG_A6XX_HLSQ_INVALIDATE_CMD 0x0000bb08
-#define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001
-#define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002
-#define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004
-#define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008
-#define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010
-#define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020
-#define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040
-#define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080
-#define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST 0x00080000
-#define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST 0x00000100
-#define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x00003e00
-#define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9
-static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK;
-}
-#define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x0007c000
-#define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 14
-static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK;
-}
-
-#define REG_A7XX_HLSQ_INVALIDATE_CMD 0x0000ab1f
-#define A7XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001
-#define A7XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002
-#define A7XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004
-#define A7XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008
-#define A7XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010
-#define A7XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020
-#define A7XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040
-#define A7XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080
-#define A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x0001fe00
-#define A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9
-static inline uint32_t A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK;
-}
-#define A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x01fe0000
-#define A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 17
-static inline uint32_t A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val)
-{
- return ((val) << A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK;
-}
-
-#define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10
-#define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff
-#define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0
-static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
-}
-#define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100
-#define A6XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
-
-#define REG_A7XX_HLSQ_FS_CNTL 0x0000ab03
-#define A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff
-#define A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0
-static inline uint32_t A7XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK;
-}
-#define A7XX_HLSQ_FS_CNTL_ENABLED 0x00000100
-#define A7XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200
-
-#define REG_A7XX_HLSQ_SHARED_CONSTS_IMM(i0) (0x0000ab40 + 0x1*(i0))
-
-#define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11
-#define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001
-
-#define REG_A6XX_HLSQ_BINDLESS_BASE(i0) (0x0000bb20 + 0x2*(i0))
-
-static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; }
-#define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003
-#define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0
-static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val)
-{
- return ((val) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK;
-}
-#define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc
-#define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2
-static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK;
-}
-
-#define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80
-#define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00
-#define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT 8
-static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val)
-{
- return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK;
-}
-#define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK 0x0000007f
-#define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT 0
-static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
-{
- return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK;
-}
-
-#define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00
-
-#define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01
-
-#define REG_A6XX_HLSQ_DBG_ECO_CNTL 0x0000be04
-
-#define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05
-
-#define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08
-
-#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(i0) (0x0000be10 + 0x1*(i0))
-
-#define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22
-
-#define REG_A7XX_SP_AHB_READ_APERTURE 0x0000c000
-
-#define REG_A7XX_SP_UNKNOWN_0CE2 0x00000ce2
-
-#define REG_A7XX_SP_UNKNOWN_0CE4 0x00000ce4
-
-#define REG_A7XX_SP_UNKNOWN_0CE6 0x00000ce6
-
-#define REG_A6XX_CP_EVENT_START 0x0000d600
-#define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff
-#define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0
-static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val)
-{
- return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK;
-}
-
-#define REG_A6XX_CP_EVENT_END 0x0000d601
-#define A6XX_CP_EVENT_END_STATE_ID__MASK 0x000000ff
-#define A6XX_CP_EVENT_END_STATE_ID__SHIFT 0
-static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val)
-{
- return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK;
-}
-
-#define REG_A6XX_CP_2D_EVENT_START 0x0000d700
-#define A6XX_CP_2D_EVENT_START_STATE_ID__MASK 0x000000ff
-#define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT 0
-static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val)
-{
- return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK;
-}
-
-#define REG_A6XX_CP_2D_EVENT_END 0x0000d701
-#define A6XX_CP_2D_EVENT_END_STATE_ID__MASK 0x000000ff
-#define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT 0
-static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val)
-{
- return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK;
-}
-
-#define REG_A6XX_TEX_SAMP_0 0x00000000
-#define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
-#define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
-#define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1
-static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val)
-{
- return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK;
-}
-#define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
-#define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3
-static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val)
-{
- return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK;
-}
-#define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
-#define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5
-static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val)
-{
- return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK;
-}
-#define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
-#define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8
-static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val)
-{
- return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK;
-}
-#define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
-#define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11
-static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val)
-{
- return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK;
-}
-#define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
-#define A6XX_TEX_SAMP_0_ANISO__SHIFT 14
-static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val)
-{
- return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK;
-}
-#define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
-#define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
-static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val)
-{
- return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK;
-}
-
-#define REG_A6XX_TEX_SAMP_1 0x00000001
-#define A6XX_TEX_SAMP_1_CLAMPENABLE 0x00000001
-#define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
-#define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
-static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
-{
- return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
-}
-#define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
-#define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
-#define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
-#define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
-#define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
-static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val)
-{
- return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK;
-}
-#define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
-#define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
-static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val)
-{
- return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK;
-}
-
-#define REG_A6XX_TEX_SAMP_2 0x00000002
-#define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003
-#define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0
-static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val)
-{
- return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK;
-}
-#define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020
-#define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80
-#define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7
-static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val)
-{
- return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK;
-}
-
-#define REG_A6XX_TEX_SAMP_3 0x00000003
-
-#define REG_A6XX_TEX_CONST_0 0x00000000
-#define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
-#define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0
-static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val)
-{
- return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK;
-}
-#define A6XX_TEX_CONST_0_SRGB 0x00000004
-#define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
-#define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4
-static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val)
-{
- return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK;
-}
-#define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
-#define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
-static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val)
-{
- return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK;
-}
-#define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
-#define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
-static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val)
-{
- return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK;
-}
-#define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
-#define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13
-static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val)
-{
- return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK;
-}
-#define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
-#define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16
-static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val)
-{
- return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK;
-}
-#define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X 0x00010000
-#define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y 0x00040000
-#define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000
-#define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20
-static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
-{
- return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK;
-}
-#define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000
-#define A6XX_TEX_CONST_0_FMT__SHIFT 22
-static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val)
-{
- return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK;
-}
-#define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000
-#define A6XX_TEX_CONST_0_SWAP__SHIFT 30
-static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
-{
- return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK;
-}
-
-#define REG_A6XX_TEX_CONST_1 0x00000001
-#define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
-#define A6XX_TEX_CONST_1_WIDTH__SHIFT 0
-static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val)
-{
- return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK;
-}
-#define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
-#define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15
-static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val)
-{
- return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK;
-}
-
-#define REG_A6XX_TEX_CONST_2 0x00000002
-#define A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK 0x0000fff0
-#define A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT 4
-static inline uint32_t A6XX_TEX_CONST_2_STRUCTSIZETEXELS(uint32_t val)
-{
- return ((val) << A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT) & A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK;
-}
-#define A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK 0x003f0000
-#define A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT 16
-static inline uint32_t A6XX_TEX_CONST_2_STARTOFFSETTEXELS(uint32_t val)
-{
- return ((val) << A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT) & A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK;
-}
-#define A6XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
-#define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
-static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
-{
- return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK;
-}
-#define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
-#define A6XX_TEX_CONST_2_PITCH__SHIFT 7
-static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val)
-{
- return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK;
-}
-#define A6XX_TEX_CONST_2_TYPE__MASK 0xe0000000
-#define A6XX_TEX_CONST_2_TYPE__SHIFT 29
-static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)
-{
- return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK;
-}
-
-#define REG_A6XX_TEX_CONST_3 0x00000003
-#define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x007fffff
-#define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
-static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK;
-}
-#define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000
-#define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23
-static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
-{
- assert(!(val & 0xfff));
- return (((val >> 12)) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
-}
-#define A6XX_TEX_CONST_3_TILE_ALL 0x08000000
-#define A6XX_TEX_CONST_3_FLAG 0x10000000
-
-#define REG_A6XX_TEX_CONST_4 0x00000004
-#define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
-#define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5
-static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK;
-}
-
-#define REG_A6XX_TEX_CONST_5 0x00000005
-#define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
-#define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0
-static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val)
-{
- return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK;
-}
-#define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
-#define A6XX_TEX_CONST_5_DEPTH__SHIFT 17
-static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val)
-{
- return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK;
-}
-
-#define REG_A6XX_TEX_CONST_6 0x00000006
-#define A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK 0x00000fff
-#define A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT 0
-static inline uint32_t A6XX_TEX_CONST_6_MIN_LOD_CLAMP(float val)
-{
- return ((((uint32_t)(val * 256.0))) << A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT) & A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK;
-}
-#define A6XX_TEX_CONST_6_PLANE_PITCH__MASK 0xffffff00
-#define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT 8
-static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val)
-{
- return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK;
-}
-
-#define REG_A6XX_TEX_CONST_7 0x00000007
-#define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0
-#define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5
-static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val)
-{
- assert(!(val & 0x1f));
- return (((val >> 5)) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK;
-}
-
-#define REG_A6XX_TEX_CONST_8 0x00000008
-#define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff
-#define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0
-static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val)
-{
- return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK;
-}
-
-#define REG_A6XX_TEX_CONST_9 0x00000009
-#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff
-#define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
-static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
-{
- assert(!(val & 0xf));
- return (((val >> 4)) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
-}
-
-#define REG_A6XX_TEX_CONST_10 0x0000000a
-#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f
-#define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0
-static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val)
-{
- assert(!(val & 0x3f));
- return (((val >> 6)) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK;
-}
-#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00
-#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8
-static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val)
-{
- return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK;
-}
-#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK 0x0000f000
-#define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT 12
-static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val)
-{
- return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK;
-}
-
-#define REG_A6XX_TEX_CONST_11 0x0000000b
-
-#define REG_A6XX_TEX_CONST_12 0x0000000c
-
-#define REG_A6XX_TEX_CONST_13 0x0000000d
-
-#define REG_A6XX_TEX_CONST_14 0x0000000e
-
-#define REG_A6XX_TEX_CONST_15 0x0000000f
-
-#define REG_A6XX_UBO_0 0x00000000
-#define A6XX_UBO_0_BASE_LO__MASK 0xffffffff
-#define A6XX_UBO_0_BASE_LO__SHIFT 0
-static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val)
-{
- return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK;
-}
-
-#define REG_A6XX_UBO_1 0x00000001
-#define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff
-#define A6XX_UBO_1_BASE_HI__SHIFT 0
-static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val)
-{
- return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK;
-}
-#define A6XX_UBO_1_SIZE__MASK 0xfffe0000
-#define A6XX_UBO_1_SIZE__SHIFT 17
-static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val)
-{
- return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK;
-}
-
-#define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140
-
-#define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148
-
-#define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540
-
-#define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541
-
-#define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542
-
-#define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543
-
-#define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544
-
-#define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545
-
-#define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572
-
-#define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573
-
-#define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574
-
-#define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575
-
-#define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576
-
-#define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577
-
-#define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4
-
-#define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5
-
-#define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6
-
-#define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7
-
-#define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8
-
-#define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9
-
-#define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6
-
-#define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7
-
-#define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8
-
-#define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9
-
-#define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da
-
-#define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db
-
-#define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000
-#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff
-#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00
-#define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK;
-}
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004
-#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f
-#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000
-#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000
-#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK;
-}
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005
-#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000
-#define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK;
-}
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK;
-}
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK;
-}
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000
-#define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28
-static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
-{
- return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK;
-}
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f
-
-#define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030
-
-#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001
-
-#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002
-
-#define REG_A7XX_CX_MISC_TCM_RET_CNTL 0x00000039
-
-#ifdef __cplusplus
-template<chip CHIP> constexpr inline uint16_t CMD_REGS[] = {};
-template<chip CHIP> constexpr inline uint16_t RP_BLIT_REGS[] = {};
-template<> constexpr inline uint16_t CMD_REGS<A6XX>[] = {
- 0xc03,
- 0xc04,
- 0xc30,
- 0xc31,
- 0xc32,
- 0xc33,
- 0xc34,
- 0xc35,
- 0xc36,
- 0xc37,
- 0xe12,
- 0xe17,
- 0xe19,
- 0x8099,
- 0x80af,
- 0x810a,
- 0x8110,
- 0x8600,
- 0x880e,
- 0x8811,
- 0x8818,
- 0x8819,
- 0x881a,
- 0x881b,
- 0x881c,
- 0x881d,
- 0x881e,
- 0x8864,
- 0x8891,
- 0x88f0,
- 0x8927,
- 0x8928,
- 0x8e01,
- 0x8e04,
- 0x8e07,
- 0x9210,
- 0x9211,
- 0x9218,
- 0x9219,
- 0x921a,
- 0x921b,
- 0x921c,
- 0x921d,
- 0x921e,
- 0x921f,
- 0x9220,
- 0x9221,
- 0x9222,
- 0x9223,
- 0x9224,
- 0x9225,
- 0x9226,
- 0x9227,
- 0x9228,
- 0x9229,
- 0x922a,
- 0x922b,
- 0x922c,
- 0x922d,
- 0x922e,
- 0x922f,
- 0x9230,
- 0x9231,
- 0x9232,
- 0x9233,
- 0x9234,
- 0x9235,
- 0x9236,
- 0x9300,
- 0x9600,
- 0x9601,
- 0x9602,
- 0x9e08,
- 0x9e09,
- 0x9e72,
- 0xa007,
- 0xa009,
- 0xa8a0,
- 0xa8a1,
- 0xa8a2,
- 0xa8a3,
- 0xa8a4,
- 0xa8a5,
- 0xa8a6,
- 0xa8a7,
- 0xa8a8,
- 0xa8a9,
- 0xa8aa,
- 0xa8ab,
- 0xa8ac,
- 0xa8ad,
- 0xa8ae,
- 0xa8af,
- 0xa9a8,
- 0xa9b0,
- 0xa9b1,
- 0xa9b2,
- 0xa9b3,
- 0xa9b4,
- 0xa9b5,
- 0xa9b6,
- 0xa9b7,
- 0xa9b8,
- 0xa9b9,
- 0xa9ba,
- 0xa9bb,
- 0xa9bc,
- 0xa9bd,
- 0xa9c2,
- 0xa9c3,
- 0xa9e2,
- 0xa9e3,
- 0xa9e6,
- 0xa9e7,
- 0xa9e8,
- 0xa9e9,
- 0xa9ea,
- 0xa9eb,
- 0xa9ec,
- 0xa9ed,
- 0xa9ee,
- 0xa9ef,
- 0xa9f0,
- 0xa9f1,
- 0xaaf2,
- 0xab1a,
- 0xab1b,
- 0xab20,
- 0xae00,
- 0xae03,
- 0xae04,
- 0xae0f,
- 0xb180,
- 0xb181,
- 0xb182,
- 0xb183,
- 0xb302,
- 0xb303,
- 0xb309,
- 0xb600,
- 0xb602,
- 0xb605,
- 0xb987,
- 0xb9d0,
- 0xbb08,
- 0xbb11,
- 0xbb20,
- 0xbb21,
- 0xbb22,
- 0xbb23,
- 0xbb24,
- 0xbb25,
- 0xbb26,
- 0xbb27,
- 0xbb28,
- 0xbb29,
- 0xbe00,
- 0xbe01,
- 0xbe04,
-};
-template<> constexpr inline uint16_t CMD_REGS<A7XX>[] = {
- 0xc03,
- 0xc04,
- 0xc30,
- 0xc31,
- 0xc32,
- 0xc33,
- 0xc34,
- 0xc35,
- 0xc36,
- 0xc37,
- 0xce2,
- 0xce3,
- 0xce4,
- 0xce5,
- 0xce6,
- 0xce7,
- 0xe10,
- 0xe11,
- 0xe12,
- 0xe17,
- 0xe19,
- 0x8008,
- 0x8009,
- 0x800a,
- 0x800b,
- 0x800c,
- 0x8099,
- 0x80a7,
- 0x80af,
- 0x80f4,
- 0x80f5,
- 0x80f5,
- 0x80f6,
- 0x80f6,
- 0x80f7,
- 0x80f8,
- 0x80f9,
- 0x80f9,
- 0x80fa,
- 0x80fa,
- 0x80fb,
- 0x810a,
- 0x810b,
- 0x8110,
- 0x8120,
- 0x8121,
- 0x8600,
- 0x880e,
- 0x8811,
- 0x8818,
- 0x8819,
- 0x881a,
- 0x881b,
- 0x881c,
- 0x881d,
- 0x881e,
- 0x8864,
- 0x8891,
- 0x8899,
- 0x88e5,
- 0x88f0,
- 0x8927,
- 0x8928,
- 0x8e01,
- 0x8e04,
- 0x8e06,
- 0x8e07,
- 0x8e09,
- 0x8e79,
- 0x9218,
- 0x9219,
- 0x921a,
- 0x921b,
- 0x921c,
- 0x921d,
- 0x921e,
- 0x921f,
- 0x9220,
- 0x9221,
- 0x9222,
- 0x9223,
- 0x9224,
- 0x9225,
- 0x9226,
- 0x9227,
- 0x9228,
- 0x9229,
- 0x922a,
- 0x922b,
- 0x922c,
- 0x922d,
- 0x922e,
- 0x922f,
- 0x9230,
- 0x9231,
- 0x9232,
- 0x9233,
- 0x9234,
- 0x9235,
- 0x9236,
- 0x9300,
- 0x9600,
- 0x9601,
- 0x9602,
- 0x9810,
- 0x9811,
- 0x9e24,
- 0x9e72,
- 0xa007,
- 0xa009,
- 0xa600,
- 0xa82d,
- 0xa82f,
- 0xa868,
- 0xa899,
- 0xa8a0,
- 0xa8a1,
- 0xa8a2,
- 0xa8a3,
- 0xa8a4,
- 0xa8a5,
- 0xa8a6,
- 0xa8a7,
- 0xa8a8,
- 0xa8a9,
- 0xa8aa,
- 0xa8ab,
- 0xa8ac,
- 0xa8ad,
- 0xa8ae,
- 0xa8af,
- 0xa9a8,
- 0xa9ac,
- 0xa9ad,
- 0xa9b0,
- 0xa9b1,
- 0xa9b2,
- 0xa9b3,
- 0xa9b4,
- 0xa9b5,
- 0xa9b6,
- 0xa9b7,
- 0xa9b8,
- 0xa9b9,
- 0xa9ba,
- 0xa9bb,
- 0xa9bc,
- 0xa9bd,
- 0xa9be,
- 0xa9c2,
- 0xa9c3,
- 0xa9c5,
- 0xa9cd,
- 0xa9df,
- 0xa9e2,
- 0xa9e3,
- 0xa9e6,
- 0xa9e7,
- 0xa9e8,
- 0xa9e9,
- 0xa9ea,
- 0xa9eb,
- 0xa9ec,
- 0xa9ed,
- 0xa9ee,
- 0xa9ef,
- 0xa9f0,
- 0xa9f1,
- 0xa9f2,
- 0xa9f3,
- 0xa9f4,
- 0xa9f5,
- 0xa9f6,
- 0xa9f7,
- 0xaa01,
- 0xaa02,
- 0xaa03,
- 0xaaf2,
- 0xab01,
- 0xab02,
- 0xab1a,
- 0xab1b,
- 0xab1f,
- 0xab20,
- 0xab22,
- 0xae00,
- 0xae03,
- 0xae04,
- 0xae06,
- 0xae08,
- 0xae09,
- 0xae0a,
- 0xae0f,
- 0xae6a,
- 0xae6b,
- 0xae6c,
- 0xae73,
- 0xb180,
- 0xb181,
- 0xb182,
- 0xb183,
- 0xb302,
- 0xb303,
- 0xb309,
- 0xb310,
- 0xb600,
- 0xb602,
- 0xb608,
- 0xb609,
- 0xb60a,
- 0xb60b,
- 0xb60c,
-};
-template<> constexpr inline uint16_t RP_BLIT_REGS<A6XX>[] = {
- 0xc02,
- 0xc06,
- 0xc10,
- 0xc11,
- 0xc12,
- 0xc13,
- 0xc14,
- 0xc15,
- 0xc16,
- 0xc17,
- 0xc18,
- 0xc19,
- 0xc1a,
- 0xc1b,
- 0xc1c,
- 0xc1d,
- 0xc1e,
- 0xc1f,
- 0xc20,
- 0xc21,
- 0xc22,
- 0xc23,
- 0xc24,
- 0xc25,
- 0xc26,
- 0xc27,
- 0xc28,
- 0xc29,
- 0xc2a,
- 0xc2b,
- 0xc2c,
- 0xc2d,
- 0xc2e,
- 0xc2f,
- 0xc38,
- 0xc39,
- 0xc3a,
- 0xc3b,
- 0xc3c,
- 0xc3d,
- 0xc3e,
- 0xc3f,
- 0xc40,
- 0xc41,
- 0xc42,
- 0xc43,
- 0xc44,
- 0xc45,
- 0xc46,
- 0xc47,
- 0xc48,
- 0xc49,
- 0xc4a,
- 0xc4b,
- 0xc4c,
- 0xc4d,
- 0xc4e,
- 0xc4f,
- 0xc50,
- 0xc51,
- 0xc52,
- 0xc53,
- 0xc54,
- 0xc55,
- 0xc56,
- 0xc57,
- 0xc58,
- 0xc59,
- 0xc5a,
- 0xc5b,
- 0xc5c,
- 0xc5d,
- 0xc5e,
- 0xc5f,
- 0xc60,
- 0xc61,
- 0xc62,
- 0xc63,
- 0xc64,
- 0xc65,
- 0xc66,
- 0xc67,
- 0xc68,
- 0xc69,
- 0xc6a,
- 0xc6b,
- 0xc6c,
- 0xc6d,
- 0xc6e,
- 0xc6f,
- 0xc70,
- 0xc71,
- 0xc72,
- 0xc73,
- 0xc74,
- 0xc75,
- 0xc76,
- 0xc77,
- 0xc78,
- 0xc79,
- 0xc7a,
- 0xc7b,
- 0xc7c,
- 0xc7d,
- 0xc7e,
- 0xc7f,
- 0xc80,
- 0xc81,
- 0xc82,
- 0xc83,
- 0xc84,
- 0xc85,
- 0xc86,
- 0xc87,
- 0xc88,
- 0xc89,
- 0xc8a,
- 0xc8b,
- 0xc8c,
- 0xc8d,
- 0xc8e,
- 0xc8f,
- 0xc90,
- 0xc91,
- 0xc92,
- 0xc93,
- 0xc94,
- 0xc95,
- 0xc96,
- 0xc97,
- 0x8000,
- 0x8001,
- 0x8002,
- 0x8003,
- 0x8004,
- 0x8005,
- 0x8006,
- 0x8010,
- 0x8011,
- 0x8012,
- 0x8013,
- 0x8014,
- 0x8015,
- 0x8016,
- 0x8017,
- 0x8018,
- 0x8019,
- 0x801a,
- 0x801b,
- 0x801c,
- 0x801d,
- 0x801e,
- 0x801f,
- 0x8020,
- 0x8021,
- 0x8022,
- 0x8023,
- 0x8024,
- 0x8025,
- 0x8026,
- 0x8027,
- 0x8028,
- 0x8029,
- 0x802a,
- 0x802b,
- 0x802c,
- 0x802d,
- 0x802e,
- 0x802f,
- 0x8030,
- 0x8031,
- 0x8032,
- 0x8033,
- 0x8034,
- 0x8035,
- 0x8036,
- 0x8037,
- 0x8038,
- 0x8039,
- 0x803a,
- 0x803b,
- 0x803c,
- 0x803d,
- 0x803e,
- 0x803f,
- 0x8040,
- 0x8041,
- 0x8042,
- 0x8043,
- 0x8044,
- 0x8045,
- 0x8046,
- 0x8047,
- 0x8048,
- 0x8049,
- 0x804a,
- 0x804b,
- 0x804c,
- 0x804d,
- 0x804e,
- 0x804f,
- 0x8050,
- 0x8051,
- 0x8052,
- 0x8053,
- 0x8054,
- 0x8055,
- 0x8056,
- 0x8057,
- 0x8058,
- 0x8059,
- 0x805a,
- 0x805b,
- 0x805c,
- 0x805d,
- 0x805e,
- 0x805f,
- 0x8060,
- 0x8061,
- 0x8062,
- 0x8063,
- 0x8064,
- 0x8065,
- 0x8066,
- 0x8067,
- 0x8068,
- 0x8069,
- 0x806a,
- 0x806b,
- 0x806c,
- 0x806d,
- 0x806e,
- 0x806f,
- 0x8070,
- 0x8071,
- 0x8072,
- 0x8073,
- 0x8074,
- 0x8075,
- 0x8076,
- 0x8077,
- 0x8078,
- 0x8079,
- 0x807a,
- 0x807b,
- 0x807c,
- 0x807d,
- 0x807e,
- 0x807f,
- 0x8080,
- 0x8081,
- 0x8082,
- 0x8083,
- 0x8084,
- 0x8085,
- 0x8086,
- 0x8087,
- 0x8088,
- 0x8089,
- 0x808a,
- 0x808b,
- 0x808c,
- 0x808d,
- 0x808e,
- 0x808f,
- 0x8090,
- 0x8091,
- 0x8092,
- 0x8094,
- 0x8095,
- 0x8096,
- 0x8097,
- 0x8098,
- 0x809b,
- 0x809c,
- 0x809d,
- 0x80a0,
- 0x80a1,
- 0x80a2,
- 0x80a3,
- 0x80a4,
- 0x80a5,
- 0x80a6,
- 0x80b0,
- 0x80b1,
- 0x80b2,
- 0x80b3,
- 0x80b4,
- 0x80b5,
- 0x80b6,
- 0x80b7,
- 0x80b8,
- 0x80b9,
- 0x80ba,
- 0x80bb,
- 0x80bc,
- 0x80bd,
- 0x80be,
- 0x80bf,
- 0x80c0,
- 0x80c1,
- 0x80c2,
- 0x80c3,
- 0x80c4,
- 0x80c5,
- 0x80c6,
- 0x80c7,
- 0x80c8,
- 0x80c9,
- 0x80ca,
- 0x80cb,
- 0x80cc,
- 0x80cd,
- 0x80ce,
- 0x80cf,
- 0x80d0,
- 0x80d1,
- 0x80d2,
- 0x80d3,
- 0x80d4,
- 0x80d5,
- 0x80d6,
- 0x80d7,
- 0x80d8,
- 0x80d9,
- 0x80da,
- 0x80db,
- 0x80dc,
- 0x80dd,
- 0x80de,
- 0x80df,
- 0x80e0,
- 0x80e1,
- 0x80e2,
- 0x80e3,
- 0x80e4,
- 0x80e5,
- 0x80e6,
- 0x80e7,
- 0x80e8,
- 0x80e9,
- 0x80ea,
- 0x80eb,
- 0x80ec,
- 0x80ed,
- 0x80ee,
- 0x80ef,
- 0x80f0,
- 0x80f1,
- 0x8100,
- 0x8101,
- 0x8102,
- 0x8103,
- 0x8104,
- 0x8105,
- 0x8106,
- 0x8107,
- 0x8109,
- 0x8114,
- 0x8115,
- 0x8400,
- 0x8401,
- 0x8402,
- 0x8403,
- 0x8404,
- 0x8405,
- 0x8406,
- 0x840a,
- 0x840b,
- 0x8800,
- 0x8801,
- 0x8802,
- 0x8803,
- 0x8804,
- 0x8805,
- 0x8806,
- 0x8809,
- 0x880a,
- 0x880b,
- 0x880c,
- 0x880d,
- 0x880f,
- 0x8810,
- 0x8820,
- 0x8821,
- 0x8822,
- 0x8823,
- 0x8824,
- 0x8825,
- 0x8826,
- 0x8827,
- 0x8828,
- 0x8829,
- 0x882a,
- 0x882b,
- 0x882c,
- 0x882d,
- 0x882e,
- 0x882f,
- 0x8830,
- 0x8831,
- 0x8832,
- 0x8833,
- 0x8834,
- 0x8835,
- 0x8836,
- 0x8837,
- 0x8838,
- 0x8839,
- 0x883a,
- 0x883b,
- 0x883c,
- 0x883d,
- 0x883e,
- 0x883f,
- 0x8840,
- 0x8841,
- 0x8842,
- 0x8843,
- 0x8844,
- 0x8845,
- 0x8846,
- 0x8847,
- 0x8848,
- 0x8849,
- 0x884a,
- 0x884b,
- 0x884c,
- 0x884d,
- 0x884e,
- 0x884f,
- 0x8850,
- 0x8851,
- 0x8852,
- 0x8853,
- 0x8854,
- 0x8855,
- 0x8856,
- 0x8857,
- 0x8858,
- 0x8859,
- 0x885a,
- 0x885b,
- 0x885c,
- 0x885d,
- 0x885e,
- 0x885f,
- 0x8860,
- 0x8861,
- 0x8862,
- 0x8863,
- 0x8865,
- 0x8870,
- 0x8871,
- 0x8872,
- 0x8873,
- 0x8874,
- 0x8875,
- 0x8876,
- 0x8877,
- 0x8878,
- 0x8879,
- 0x8880,
- 0x8881,
- 0x8882,
- 0x8883,
- 0x8884,
- 0x8885,
- 0x8886,
- 0x8887,
- 0x8888,
- 0x8889,
- 0x8890,
- 0x8898,
- 0x88c0,
- 0x88c1,
- 0x88d0,
- 0x88d1,
- 0x88d2,
- 0x88d3,
- 0x88d4,
- 0x88d5,
- 0x88d6,
- 0x88d7,
- 0x88d8,
- 0x88d9,
- 0x88da,
- 0x88db,
- 0x88dc,
- 0x88dd,
- 0x88de,
- 0x88df,
- 0x88e0,
- 0x88e1,
- 0x88e2,
- 0x88e3,
- 0x8900,
- 0x8901,
- 0x8902,
- 0x8903,
- 0x8904,
- 0x8905,
- 0x8906,
- 0x8907,
- 0x8908,
- 0x8909,
- 0x890a,
- 0x890b,
- 0x890c,
- 0x890d,
- 0x890e,
- 0x890f,
- 0x8910,
- 0x8911,
- 0x8912,
- 0x8913,
- 0x8914,
- 0x8915,
- 0x8916,
- 0x8917,
- 0x8918,
- 0x8919,
- 0x891a,
- 0x8a00,
- 0x8a10,
- 0x8a20,
- 0x8a30,
- 0x8c00,
- 0x8c01,
- 0x8c17,
- 0x8c18,
- 0x8c19,
- 0x8c1a,
- 0x8c1b,
- 0x8c1c,
- 0x8c1d,
- 0x8c1e,
- 0x8c1f,
- 0x8c20,
- 0x8c21,
- 0x8c22,
- 0x8c23,
- 0x8c24,
- 0x8c25,
- 0x8c2c,
- 0x8c2d,
- 0x8c2e,
- 0x8c2f,
- 0x9100,
- 0x9101,
- 0x9102,
- 0x9103,
- 0x9104,
- 0x9105,
- 0x9106,
- 0x9107,
- 0x9108,
- 0x9200,
- 0x9201,
- 0x9202,
- 0x9203,
- 0x9204,
- 0x9205,
- 0x9206,
- 0x9207,
- 0x9208,
- 0x9209,
- 0x920a,
- 0x920b,
- 0x920c,
- 0x920d,
- 0x920e,
- 0x920f,
- 0x9212,
- 0x9213,
- 0x9214,
- 0x9215,
- 0x9216,
- 0x9217,
- 0x9301,
- 0x9302,
- 0x9303,
- 0x9304,
- 0x9305,
- 0x9306,
- 0x9311,
- 0x9312,
- 0x9313,
- 0x9314,
- 0x9315,
- 0x9316,
- 0x9800,
- 0x9801,
- 0x9802,
- 0x9803,
- 0x9804,
- 0x9805,
- 0x9806,
- 0x9808,
- 0x9980,
- 0x9981,
- 0x9b00,
- 0x9b01,
- 0x9b02,
- 0x9b03,
- 0x9b04,
- 0x9b05,
- 0x9b06,
- 0x9b07,
- 0x9b08,
- 0xa000,
- 0xa001,
- 0xa002,
- 0xa003,
- 0xa004,
- 0xa005,
- 0xa006,
- 0xa008,
- 0xa00e,
- 0xa00f,
- 0xa010,
- 0xa011,
- 0xa012,
- 0xa013,
- 0xa014,
- 0xa015,
- 0xa016,
- 0xa017,
- 0xa018,
- 0xa019,
- 0xa01a,
- 0xa01b,
- 0xa01c,
- 0xa01d,
- 0xa01e,
- 0xa01f,
- 0xa020,
- 0xa021,
- 0xa022,
- 0xa023,
- 0xa024,
- 0xa025,
- 0xa026,
- 0xa027,
- 0xa028,
- 0xa029,
- 0xa02a,
- 0xa02b,
- 0xa02c,
- 0xa02d,
- 0xa02e,
- 0xa02f,
- 0xa030,
- 0xa031,
- 0xa032,
- 0xa033,
- 0xa034,
- 0xa035,
- 0xa036,
- 0xa037,
- 0xa038,
- 0xa039,
- 0xa03a,
- 0xa03b,
- 0xa03c,
- 0xa03d,
- 0xa03e,
- 0xa03f,
- 0xa040,
- 0xa041,
- 0xa042,
- 0xa043,
- 0xa044,
- 0xa045,
- 0xa046,
- 0xa047,
- 0xa048,
- 0xa049,
- 0xa04a,
- 0xa04b,
- 0xa04c,
- 0xa04d,
- 0xa04e,
- 0xa04f,
- 0xa050,
- 0xa051,
- 0xa052,
- 0xa053,
- 0xa054,
- 0xa055,
- 0xa056,
- 0xa057,
- 0xa058,
- 0xa059,
- 0xa05a,
- 0xa05b,
- 0xa05c,
- 0xa05d,
- 0xa05e,
- 0xa05f,
- 0xa060,
- 0xa061,
- 0xa062,
- 0xa063,
- 0xa064,
- 0xa065,
- 0xa066,
- 0xa067,
- 0xa068,
- 0xa069,
- 0xa06a,
- 0xa06b,
- 0xa06c,
- 0xa06d,
- 0xa06e,
- 0xa06f,
- 0xa070,
- 0xa071,
- 0xa072,
- 0xa073,
- 0xa074,
- 0xa075,
- 0xa076,
- 0xa077,
- 0xa078,
- 0xa079,
- 0xa07a,
- 0xa07b,
- 0xa07c,
- 0xa07d,
- 0xa07e,
- 0xa07f,
- 0xa080,
- 0xa081,
- 0xa082,
- 0xa083,
- 0xa084,
- 0xa085,
- 0xa086,
- 0xa087,
- 0xa088,
- 0xa089,
- 0xa08a,
- 0xa08b,
- 0xa08c,
- 0xa08d,
- 0xa08e,
- 0xa08f,
- 0xa090,
- 0xa091,
- 0xa092,
- 0xa093,
- 0xa094,
- 0xa095,
- 0xa096,
- 0xa097,
- 0xa098,
- 0xa099,
- 0xa09a,
- 0xa09b,
- 0xa09c,
- 0xa09d,
- 0xa09e,
- 0xa09f,
- 0xa0a0,
- 0xa0a1,
- 0xa0a2,
- 0xa0a3,
- 0xa0a4,
- 0xa0a5,
- 0xa0a6,
- 0xa0a7,
- 0xa0a8,
- 0xa0a9,
- 0xa0aa,
- 0xa0ab,
- 0xa0ac,
- 0xa0ad,
- 0xa0ae,
- 0xa0af,
- 0xa0b0,
- 0xa0b1,
- 0xa0b2,
- 0xa0b3,
- 0xa0b4,
- 0xa0b5,
- 0xa0b6,
- 0xa0b7,
- 0xa0b8,
- 0xa0b9,
- 0xa0ba,
- 0xa0bb,
- 0xa0bc,
- 0xa0bd,
- 0xa0be,
- 0xa0bf,
- 0xa0c0,
- 0xa0c1,
- 0xa0c2,
- 0xa0c3,
- 0xa0c4,
- 0xa0c5,
- 0xa0c6,
- 0xa0c7,
- 0xa0c8,
- 0xa0c9,
- 0xa0ca,
- 0xa0cb,
- 0xa0cc,
- 0xa0cd,
- 0xa0ce,
- 0xa0cf,
- 0xa0d0,
- 0xa0d1,
- 0xa0d2,
- 0xa0d3,
- 0xa0d4,
- 0xa0d5,
- 0xa0d6,
- 0xa0d7,
- 0xa0d8,
- 0xa0d9,
- 0xa0da,
- 0xa0db,
- 0xa0dc,
- 0xa0dd,
- 0xa0de,
- 0xa0df,
- 0xa0e0,
- 0xa0e1,
- 0xa0e2,
- 0xa0e3,
- 0xa0e4,
- 0xa0e5,
- 0xa0e6,
- 0xa0e7,
- 0xa0e8,
- 0xa0e9,
- 0xa0ea,
- 0xa0eb,
- 0xa0ec,
- 0xa0ed,
- 0xa0ee,
- 0xa0ef,
- 0xa0f8,
- 0xa800,
- 0xa802,
- 0xa803,
- 0xa804,
- 0xa805,
- 0xa806,
- 0xa807,
- 0xa808,
- 0xa809,
- 0xa80a,
- 0xa80b,
- 0xa80c,
- 0xa80d,
- 0xa80e,
- 0xa80f,
- 0xa810,
- 0xa811,
- 0xa812,
- 0xa813,
- 0xa814,
- 0xa815,
- 0xa816,
- 0xa817,
- 0xa818,
- 0xa819,
- 0xa81a,
- 0xa81b,
- 0xa81c,
- 0xa81d,
- 0xa81e,
- 0xa81f,
- 0xa820,
- 0xa821,
- 0xa822,
- 0xa823,
- 0xa824,
- 0xa825,
- 0xa830,
- 0xa831,
- 0xa832,
- 0xa833,
- 0xa834,
- 0xa835,
- 0xa836,
- 0xa837,
- 0xa838,
- 0xa839,
- 0xa83a,
- 0xa83b,
- 0xa83c,
- 0xa83d,
- 0xa840,
- 0xa842,
- 0xa843,
- 0xa844,
- 0xa845,
- 0xa846,
- 0xa847,
- 0xa848,
- 0xa849,
- 0xa84a,
- 0xa84b,
- 0xa84c,
- 0xa84d,
- 0xa84e,
- 0xa84f,
- 0xa850,
- 0xa851,
- 0xa852,
- 0xa853,
- 0xa854,
- 0xa855,
- 0xa856,
- 0xa857,
- 0xa858,
- 0xa859,
- 0xa85a,
- 0xa85b,
- 0xa85c,
- 0xa85d,
- 0xa85e,
- 0xa85f,
- 0xa860,
- 0xa861,
- 0xa862,
- 0xa863,
- 0xa864,
- 0xa865,
- 0xa870,
- 0xa871,
- 0xa872,
- 0xa873,
- 0xa874,
- 0xa875,
- 0xa876,
- 0xa877,
- 0xa878,
- 0xa879,
- 0xa87a,
- 0xa87b,
- 0xa87c,
- 0xa87d,
- 0xa87e,
- 0xa87f,
- 0xa880,
- 0xa881,
- 0xa882,
- 0xa883,
- 0xa884,
- 0xa885,
- 0xa886,
- 0xa887,
- 0xa888,
- 0xa889,
- 0xa88a,
- 0xa88b,
- 0xa88c,
- 0xa88d,
- 0xa88e,
- 0xa88f,
- 0xa890,
- 0xa891,
- 0xa892,
- 0xa893,
- 0xa894,
- 0xa895,
- 0xa896,
- 0xa980,
- 0xa982,
- 0xa983,
- 0xa984,
- 0xa985,
- 0xa986,
- 0xa987,
- 0xa988,
- 0xa989,
- 0xa98a,
- 0xa98b,
- 0xa98c,
- 0xa98d,
- 0xa98e,
- 0xa98f,
- 0xa990,
- 0xa991,
- 0xa992,
- 0xa993,
- 0xa994,
- 0xa995,
- 0xa996,
- 0xa997,
- 0xa998,
- 0xa999,
- 0xa99a,
- 0xa99b,
- 0xa99c,
- 0xa99d,
- 0xa99e,
- 0xa99f,
- 0xa9a0,
- 0xa9a1,
- 0xa9a2,
- 0xa9a3,
- 0xa9a4,
- 0xa9a5,
- 0xa9a6,
- 0xa9a7,
- 0xa9a9,
- 0xa9e0,
- 0xa9e1,
- 0xa9e4,
- 0xa9e5,
- 0xab00,
- 0xab04,
- 0xab05,
- 0xab10,
- 0xab11,
- 0xab12,
- 0xab13,
- 0xab14,
- 0xab15,
- 0xab16,
- 0xab17,
- 0xab18,
- 0xab19,
- 0xacc0,
- 0xb300,
- 0xb301,
- 0xb304,
- 0xb305,
- 0xb306,
- 0xb307,
- 0xb4c0,
- 0xb4c1,
- 0xb4c2,
- 0xb4c3,
- 0xb4c4,
- 0xb4ca,
- 0xb4cb,
- 0xb4cc,
- 0xb4d1,
- 0xb800,
- 0xb801,
- 0xb802,
- 0xb803,
- 0xb980,
- 0xb982,
- 0xb983,
- 0xb984,
- 0xb985,
- 0xb986,
- 0xb990,
- 0xb991,
- 0xb992,
- 0xb993,
- 0xb994,
- 0xb995,
- 0xb996,
- 0xb997,
- 0xb998,
- 0xb999,
- 0xb99a,
- 0xb99b,
- 0xb9c0,
- 0xb9c1,
- 0xb9c2,
- 0xb9c3,
- 0xb9c4,
- 0xb9c5,
- 0xb9c6,
- 0xb9c7,
- 0xb9c8,
- 0xb9c9,
- 0xbb10,
-};
-template<> constexpr inline uint16_t RP_BLIT_REGS<A7XX>[] = {
- 0xc02,
- 0xc06,
- 0xc10,
- 0xc11,
- 0xc12,
- 0xc13,
- 0xc14,
- 0xc15,
- 0xc16,
- 0xc17,
- 0xc18,
- 0xc19,
- 0xc1a,
- 0xc1b,
- 0xc1c,
- 0xc1d,
- 0xc1e,
- 0xc1f,
- 0xc20,
- 0xc21,
- 0xc22,
- 0xc23,
- 0xc24,
- 0xc25,
- 0xc26,
- 0xc27,
- 0xc28,
- 0xc29,
- 0xc2a,
- 0xc2b,
- 0xc2c,
- 0xc2d,
- 0xc2e,
- 0xc2f,
- 0xc38,
- 0xc39,
- 0xc3a,
- 0xc3b,
- 0xc3c,
- 0xc3d,
- 0xc3e,
- 0xc3f,
- 0xc40,
- 0xc41,
- 0xc42,
- 0xc43,
- 0xc44,
- 0xc45,
- 0xc46,
- 0xc47,
- 0xc48,
- 0xc49,
- 0xc4a,
- 0xc4b,
- 0xc4c,
- 0xc4d,
- 0xc4e,
- 0xc4f,
- 0xc50,
- 0xc51,
- 0xc52,
- 0xc53,
- 0xc54,
- 0xc55,
- 0xc56,
- 0xc57,
- 0x8000,
- 0x8001,
- 0x8002,
- 0x8003,
- 0x8004,
- 0x8005,
- 0x8006,
- 0x8007,
- 0x8010,
- 0x8011,
- 0x8012,
- 0x8013,
- 0x8014,
- 0x8015,
- 0x8016,
- 0x8017,
- 0x8018,
- 0x8019,
- 0x801a,
- 0x801b,
- 0x801c,
- 0x801d,
- 0x801e,
- 0x801f,
- 0x8020,
- 0x8021,
- 0x8022,
- 0x8023,
- 0x8024,
- 0x8025,
- 0x8026,
- 0x8027,
- 0x8028,
- 0x8029,
- 0x802a,
- 0x802b,
- 0x802c,
- 0x802d,
- 0x802e,
- 0x802f,
- 0x8030,
- 0x8031,
- 0x8032,
- 0x8033,
- 0x8034,
- 0x8035,
- 0x8036,
- 0x8037,
- 0x8038,
- 0x8039,
- 0x803a,
- 0x803b,
- 0x803c,
- 0x803d,
- 0x803e,
- 0x803f,
- 0x8040,
- 0x8041,
- 0x8042,
- 0x8043,
- 0x8044,
- 0x8045,
- 0x8046,
- 0x8047,
- 0x8048,
- 0x8049,
- 0x804a,
- 0x804b,
- 0x804c,
- 0x804d,
- 0x804e,
- 0x804f,
- 0x8050,
- 0x8051,
- 0x8052,
- 0x8053,
- 0x8054,
- 0x8055,
- 0x8056,
- 0x8057,
- 0x8058,
- 0x8059,
- 0x805a,
- 0x805b,
- 0x805c,
- 0x805d,
- 0x805e,
- 0x805f,
- 0x8060,
- 0x8061,
- 0x8062,
- 0x8063,
- 0x8064,
- 0x8065,
- 0x8066,
- 0x8067,
- 0x8068,
- 0x8069,
- 0x806a,
- 0x806b,
- 0x806c,
- 0x806d,
- 0x806e,
- 0x806f,
- 0x8070,
- 0x8071,
- 0x8072,
- 0x8073,
- 0x8074,
- 0x8075,
- 0x8076,
- 0x8077,
- 0x8078,
- 0x8079,
- 0x807a,
- 0x807b,
- 0x807c,
- 0x807d,
- 0x807e,
- 0x807f,
- 0x8080,
- 0x8081,
- 0x8082,
- 0x8083,
- 0x8084,
- 0x8085,
- 0x8086,
- 0x8087,
- 0x8088,
- 0x8089,
- 0x808a,
- 0x808b,
- 0x808c,
- 0x808d,
- 0x808e,
- 0x808f,
- 0x8090,
- 0x8091,
- 0x8092,
- 0x8094,
- 0x8095,
- 0x8096,
- 0x8097,
- 0x8098,
- 0x809b,
- 0x809c,
- 0x809d,
- 0x80a0,
- 0x80a1,
- 0x80a2,
- 0x80a3,
- 0x80a4,
- 0x80a5,
- 0x80a6,
- 0x80b0,
- 0x80b1,
- 0x80b2,
- 0x80b3,
- 0x80b4,
- 0x80b5,
- 0x80b6,
- 0x80b7,
- 0x80b8,
- 0x80b9,
- 0x80ba,
- 0x80bb,
- 0x80bc,
- 0x80bd,
- 0x80be,
- 0x80bf,
- 0x80c0,
- 0x80c1,
- 0x80c2,
- 0x80c3,
- 0x80c4,
- 0x80c5,
- 0x80c6,
- 0x80c7,
- 0x80c8,
- 0x80c9,
- 0x80ca,
- 0x80cb,
- 0x80cc,
- 0x80cd,
- 0x80ce,
- 0x80cf,
- 0x80d0,
- 0x80d1,
- 0x80d2,
- 0x80d3,
- 0x80d4,
- 0x80d5,
- 0x80d6,
- 0x80d7,
- 0x80d8,
- 0x80d9,
- 0x80da,
- 0x80db,
- 0x80dc,
- 0x80dd,
- 0x80de,
- 0x80df,
- 0x80e0,
- 0x80e1,
- 0x80e2,
- 0x80e3,
- 0x80e4,
- 0x80e5,
- 0x80e6,
- 0x80e7,
- 0x80e8,
- 0x80e9,
- 0x80ea,
- 0x80eb,
- 0x80ec,
- 0x80ed,
- 0x80ee,
- 0x80ef,
- 0x80f0,
- 0x80f1,
- 0x8100,
- 0x8101,
- 0x8102,
- 0x8103,
- 0x8104,
- 0x8105,
- 0x8106,
- 0x8107,
- 0x8109,
- 0x8113,
- 0x8114,
- 0x8115,
- 0x8116,
- 0x8400,
- 0x8401,
- 0x8402,
- 0x8403,
- 0x8404,
- 0x8405,
- 0x8406,
- 0x840a,
- 0x840b,
- 0x8800,
- 0x8801,
- 0x8802,
- 0x8803,
- 0x8804,
- 0x8805,
- 0x8806,
- 0x8809,
- 0x880a,
- 0x880b,
- 0x880c,
- 0x880d,
- 0x880f,
- 0x8810,
- 0x8812,
- 0x8820,
- 0x8821,
- 0x8822,
- 0x8823,
- 0x8824,
- 0x8825,
- 0x8826,
- 0x8827,
- 0x8828,
- 0x8829,
- 0x882a,
- 0x882b,
- 0x882c,
- 0x882d,
- 0x882e,
- 0x882f,
- 0x8830,
- 0x8831,
- 0x8832,
- 0x8833,
- 0x8834,
- 0x8835,
- 0x8836,
- 0x8837,
- 0x8838,
- 0x8839,
- 0x883a,
- 0x883b,
- 0x883c,
- 0x883d,
- 0x883e,
- 0x883f,
- 0x8840,
- 0x8841,
- 0x8842,
- 0x8843,
- 0x8844,
- 0x8845,
- 0x8846,
- 0x8847,
- 0x8848,
- 0x8849,
- 0x884a,
- 0x884b,
- 0x884c,
- 0x884d,
- 0x884e,
- 0x884f,
- 0x8850,
- 0x8851,
- 0x8852,
- 0x8853,
- 0x8854,
- 0x8855,
- 0x8856,
- 0x8857,
- 0x8858,
- 0x8859,
- 0x885a,
- 0x885b,
- 0x885c,
- 0x885d,
- 0x885e,
- 0x885f,
- 0x8860,
- 0x8861,
- 0x8862,
- 0x8863,
- 0x8865,
- 0x8870,
- 0x8871,
- 0x8872,
- 0x8873,
- 0x8874,
- 0x8875,
- 0x8876,
- 0x8877,
- 0x8878,
- 0x8879,
- 0x8880,
- 0x8881,
- 0x8882,
- 0x8883,
- 0x8884,
- 0x8885,
- 0x8886,
- 0x8887,
- 0x8888,
- 0x8889,
- 0x8890,
- 0x8898,
- 0x88c0,
- 0x88c1,
- 0x88d0,
- 0x88d1,
- 0x88d2,
- 0x88d3,
- 0x88d4,
- 0x88d5,
- 0x88d6,
- 0x88d7,
- 0x88d8,
- 0x88d9,
- 0x88da,
- 0x88db,
- 0x88dc,
- 0x88dd,
- 0x88de,
- 0x88df,
- 0x88e0,
- 0x88e1,
- 0x88e2,
- 0x88e3,
- 0x8900,
- 0x8901,
- 0x8902,
- 0x8903,
- 0x8904,
- 0x8905,
- 0x8906,
- 0x8907,
- 0x8908,
- 0x8909,
- 0x890a,
- 0x890b,
- 0x890c,
- 0x890d,
- 0x890e,
- 0x890f,
- 0x8910,
- 0x8911,
- 0x8912,
- 0x8913,
- 0x8914,
- 0x8915,
- 0x8916,
- 0x8917,
- 0x8918,
- 0x8919,
- 0x891a,
- 0x8c00,
- 0x8c01,
- 0x8c17,
- 0x8c18,
- 0x8c19,
- 0x8c1a,
- 0x8c1b,
- 0x8c1c,
- 0x8c1d,
- 0x8c1e,
- 0x8c1f,
- 0x8c20,
- 0x8c21,
- 0x8c22,
- 0x8c23,
- 0x8c24,
- 0x8c25,
- 0x8c2c,
- 0x8c2d,
- 0x8c2e,
- 0x8c2f,
- 0x9101,
- 0x9102,
- 0x9103,
- 0x9104,
- 0x9105,
- 0x9106,
- 0x9107,
- 0x9108,
- 0x9109,
- 0x910a,
- 0x910b,
- 0x910c,
- 0x9200,
- 0x9201,
- 0x9202,
- 0x9203,
- 0x9204,
- 0x9205,
- 0x9206,
- 0x9207,
- 0x9208,
- 0x9209,
- 0x920a,
- 0x920b,
- 0x920c,
- 0x920d,
- 0x920e,
- 0x920f,
- 0x9212,
- 0x9213,
- 0x9214,
- 0x9215,
- 0x9216,
- 0x9217,
- 0x9301,
- 0x9302,
- 0x9303,
- 0x9304,
- 0x9305,
- 0x9306,
- 0x9307,
- 0x9308,
- 0x9309,
- 0x9311,
- 0x9312,
- 0x9313,
- 0x9314,
- 0x9315,
- 0x9316,
- 0x9317,
- 0x9800,
- 0x9801,
- 0x9802,
- 0x9803,
- 0x9804,
- 0x9805,
- 0x9806,
- 0x9808,
- 0x9809,
- 0x9b00,
- 0x9b01,
- 0x9b02,
- 0x9b03,
- 0x9b04,
- 0x9b05,
- 0x9b07,
- 0x9b08,
- 0x9b09,
- 0xa000,
- 0xa001,
- 0xa002,
- 0xa003,
- 0xa004,
- 0xa005,
- 0xa006,
- 0xa008,
- 0xa00e,
- 0xa00f,
- 0xa010,
- 0xa011,
- 0xa012,
- 0xa013,
- 0xa014,
- 0xa015,
- 0xa016,
- 0xa017,
- 0xa018,
- 0xa019,
- 0xa01a,
- 0xa01b,
- 0xa01c,
- 0xa01d,
- 0xa01e,
- 0xa01f,
- 0xa020,
- 0xa021,
- 0xa022,
- 0xa023,
- 0xa024,
- 0xa025,
- 0xa026,
- 0xa027,
- 0xa028,
- 0xa029,
- 0xa02a,
- 0xa02b,
- 0xa02c,
- 0xa02d,
- 0xa02e,
- 0xa02f,
- 0xa030,
- 0xa031,
- 0xa032,
- 0xa033,
- 0xa034,
- 0xa035,
- 0xa036,
- 0xa037,
- 0xa038,
- 0xa039,
- 0xa03a,
- 0xa03b,
- 0xa03c,
- 0xa03d,
- 0xa03e,
- 0xa03f,
- 0xa040,
- 0xa041,
- 0xa042,
- 0xa043,
- 0xa044,
- 0xa045,
- 0xa046,
- 0xa047,
- 0xa048,
- 0xa049,
- 0xa04a,
- 0xa04b,
- 0xa04c,
- 0xa04d,
- 0xa04e,
- 0xa04f,
- 0xa050,
- 0xa051,
- 0xa052,
- 0xa053,
- 0xa054,
- 0xa055,
- 0xa056,
- 0xa057,
- 0xa058,
- 0xa059,
- 0xa05a,
- 0xa05b,
- 0xa05c,
- 0xa05d,
- 0xa05e,
- 0xa05f,
- 0xa060,
- 0xa061,
- 0xa062,
- 0xa063,
- 0xa064,
- 0xa065,
- 0xa066,
- 0xa067,
- 0xa068,
- 0xa069,
- 0xa06a,
- 0xa06b,
- 0xa06c,
- 0xa06d,
- 0xa06e,
- 0xa06f,
- 0xa070,
- 0xa071,
- 0xa072,
- 0xa073,
- 0xa074,
- 0xa075,
- 0xa076,
- 0xa077,
- 0xa078,
- 0xa079,
- 0xa07a,
- 0xa07b,
- 0xa07c,
- 0xa07d,
- 0xa07e,
- 0xa07f,
- 0xa080,
- 0xa081,
- 0xa082,
- 0xa083,
- 0xa084,
- 0xa085,
- 0xa086,
- 0xa087,
- 0xa088,
- 0xa089,
- 0xa08a,
- 0xa08b,
- 0xa08c,
- 0xa08d,
- 0xa08e,
- 0xa08f,
- 0xa090,
- 0xa091,
- 0xa092,
- 0xa093,
- 0xa094,
- 0xa095,
- 0xa096,
- 0xa097,
- 0xa098,
- 0xa099,
- 0xa09a,
- 0xa09b,
- 0xa09c,
- 0xa09d,
- 0xa09e,
- 0xa09f,
- 0xa0a0,
- 0xa0a1,
- 0xa0a2,
- 0xa0a3,
- 0xa0a4,
- 0xa0a5,
- 0xa0a6,
- 0xa0a7,
- 0xa0a8,
- 0xa0a9,
- 0xa0aa,
- 0xa0ab,
- 0xa0ac,
- 0xa0ad,
- 0xa0ae,
- 0xa0af,
- 0xa0b0,
- 0xa0b1,
- 0xa0b2,
- 0xa0b3,
- 0xa0b4,
- 0xa0b5,
- 0xa0b6,
- 0xa0b7,
- 0xa0b8,
- 0xa0b9,
- 0xa0ba,
- 0xa0bb,
- 0xa0bc,
- 0xa0bd,
- 0xa0be,
- 0xa0bf,
- 0xa0c0,
- 0xa0c1,
- 0xa0c2,
- 0xa0c3,
- 0xa0c4,
- 0xa0c5,
- 0xa0c6,
- 0xa0c7,
- 0xa0c8,
- 0xa0c9,
- 0xa0ca,
- 0xa0cb,
- 0xa0cc,
- 0xa0cd,
- 0xa0ce,
- 0xa0cf,
- 0xa0d0,
- 0xa0d1,
- 0xa0d2,
- 0xa0d3,
- 0xa0d4,
- 0xa0d5,
- 0xa0d6,
- 0xa0d7,
- 0xa0d8,
- 0xa0d9,
- 0xa0da,
- 0xa0db,
- 0xa0dc,
- 0xa0dd,
- 0xa0de,
- 0xa0df,
- 0xa0e0,
- 0xa0e1,
- 0xa0e2,
- 0xa0e3,
- 0xa0e4,
- 0xa0e5,
- 0xa0e6,
- 0xa0e7,
- 0xa0e8,
- 0xa0e9,
- 0xa0ea,
- 0xa0eb,
- 0xa0ec,
- 0xa0ed,
- 0xa0ee,
- 0xa0ef,
- 0xa0f8,
- 0xa800,
- 0xa802,
- 0xa803,
- 0xa804,
- 0xa805,
- 0xa806,
- 0xa807,
- 0xa808,
- 0xa809,
- 0xa80a,
- 0xa80b,
- 0xa80c,
- 0xa80d,
- 0xa80e,
- 0xa80f,
- 0xa810,
- 0xa811,
- 0xa812,
- 0xa813,
- 0xa814,
- 0xa815,
- 0xa816,
- 0xa817,
- 0xa818,
- 0xa819,
- 0xa81a,
- 0xa81b,
- 0xa81c,
- 0xa81d,
- 0xa81e,
- 0xa81f,
- 0xa820,
- 0xa821,
- 0xa822,
- 0xa823,
- 0xa824,
- 0xa825,
- 0xa827,
- 0xa830,
- 0xa831,
- 0xa832,
- 0xa833,
- 0xa834,
- 0xa835,
- 0xa836,
- 0xa837,
- 0xa838,
- 0xa839,
- 0xa83a,
- 0xa83b,
- 0xa83c,
- 0xa83d,
- 0xa83f,
- 0xa840,
- 0xa842,
- 0xa843,
- 0xa844,
- 0xa845,
- 0xa846,
- 0xa847,
- 0xa848,
- 0xa849,
- 0xa84a,
- 0xa84b,
- 0xa84c,
- 0xa84d,
- 0xa84e,
- 0xa84f,
- 0xa850,
- 0xa851,
- 0xa852,
- 0xa853,
- 0xa854,
- 0xa855,
- 0xa856,
- 0xa857,
- 0xa858,
- 0xa859,
- 0xa85a,
- 0xa85b,
- 0xa85c,
- 0xa85d,
- 0xa85e,
- 0xa85f,
- 0xa860,
- 0xa861,
- 0xa862,
- 0xa863,
- 0xa864,
- 0xa865,
- 0xa867,
- 0xa870,
- 0xa871,
- 0xa872,
- 0xa873,
- 0xa874,
- 0xa875,
- 0xa876,
- 0xa877,
- 0xa878,
- 0xa879,
- 0xa87a,
- 0xa87b,
- 0xa87c,
- 0xa87d,
- 0xa87e,
- 0xa87f,
- 0xa880,
- 0xa881,
- 0xa882,
- 0xa883,
- 0xa884,
- 0xa885,
- 0xa886,
- 0xa887,
- 0xa888,
- 0xa889,
- 0xa88a,
- 0xa88b,
- 0xa88c,
- 0xa88d,
- 0xa88e,
- 0xa88f,
- 0xa890,
- 0xa891,
- 0xa892,
- 0xa893,
- 0xa894,
- 0xa895,
- 0xa896,
- 0xa898,
- 0xa980,
- 0xa982,
- 0xa983,
- 0xa984,
- 0xa985,
- 0xa986,
- 0xa987,
- 0xa988,
- 0xa989,
- 0xa98a,
- 0xa98b,
- 0xa98c,
- 0xa98d,
- 0xa98e,
- 0xa98f,
- 0xa990,
- 0xa991,
- 0xa992,
- 0xa993,
- 0xa994,
- 0xa995,
- 0xa996,
- 0xa997,
- 0xa998,
- 0xa999,
- 0xa99a,
- 0xa99b,
- 0xa99c,
- 0xa99d,
- 0xa99e,
- 0xa99f,
- 0xa9a0,
- 0xa9a1,
- 0xa9a2,
- 0xa9a3,
- 0xa9a4,
- 0xa9a5,
- 0xa9a6,
- 0xa9a7,
- 0xa9a9,
- 0xa9aa,
- 0xa9ae,
- 0xa9bf,
- 0xa9c6,
- 0xa9c7,
- 0xa9c8,
- 0xa9c9,
- 0xa9ca,
- 0xa9cb,
- 0xa9d4,
- 0xa9d5,
- 0xa9d6,
- 0xa9d7,
- 0xa9d8,
- 0xa9d9,
- 0xa9da,
- 0xa9db,
- 0xa9dc,
- 0xa9dd,
- 0xa9de,
- 0xa9e0,
- 0xa9e1,
- 0xa9e4,
- 0xa9e5,
- 0xab00,
- 0xab03,
- 0xab04,
- 0xab05,
- 0xab0a,
- 0xab0b,
- 0xab0c,
- 0xab0d,
- 0xab0e,
- 0xab0f,
- 0xab10,
- 0xab11,
- 0xab12,
- 0xab13,
- 0xab14,
- 0xab15,
- 0xab16,
- 0xab17,
- 0xab18,
- 0xab19,
- 0xab21,
- 0xb2c0,
- 0xb2c2,
- 0xb2c3,
- 0xb2ca,
- 0xb2cb,
- 0xb2cc,
- 0xb2d2,
- 0xb300,
- 0xb301,
- 0xb304,
- 0xb305,
- 0xb306,
- 0xb307,
-};
-#endif
-
-#endif /* A6XX_XML */
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 8bea8ef26f77..0e3dfd4c2bc8 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -507,7 +507,7 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
{
- msm_writel(value, ptr + (offset << 2));
+ writel(value, ptr + (offset << 2));
}
static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
index 592b296aab22..94b6c5cab6f4 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
@@ -103,12 +103,12 @@ struct a6xx_gmu {
static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
{
- return msm_readl(gmu->mmio + (offset << 2));
+ return readl(gmu->mmio + (offset << 2));
}
static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
{
- msm_writel(value, gmu->mmio + (offset << 2));
+ writel(value, gmu->mmio + (offset << 2));
}
static inline void
@@ -131,8 +131,8 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
{
u64 val;
- val = (u64) msm_readl(gmu->mmio + (lo << 2));
- val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
+ val = (u64) readl(gmu->mmio + (lo << 2));
+ val |= ((u64) readl(gmu->mmio + (hi << 2)) << 32);
return val;
}
@@ -143,12 +143,12 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)
{
- return msm_readl(gmu->rscc + (offset << 2));
+ return readl(gmu->rscc + (offset << 2));
}
static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
{
- msm_writel(value, gmu->rscc + (offset << 2));
+ writel(value, gmu->rscc + (offset << 2));
}
#define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
deleted file mode 100644
index 9d7f93929367..000000000000
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
+++ /dev/null
@@ -1,422 +0,0 @@
-#ifndef A6XX_GMU_XML
-#define A6XX_GMU_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
-http://gitlab.freedesktop.org/mesa/mesa/
-git clone https://gitlab.freedesktop.org/mesa/mesa.git
-
-The rules-ng-ng source files this header was generated from are:
-
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11820 bytes, from Fri Jun 2 14:59:26 2023)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
-
-Copyright (C) 2013-2024 by the following authors:
-- Rob Clark <robdclark@gmail.com> Rob Clark
-- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-*/
-
-#ifdef __KERNEL__
-#include <linux/bug.h>
-#define assert(x) BUG_ON(!(x))
-#else
-#include <assert.h>
-#endif
-
-#ifdef __cplusplus
-#define __struct_cast(X)
-#else
-#define __struct_cast(X) (struct X)
-#endif
-
-#define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB 0x00800000
-#define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB 0x40000000
-
-#define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK 0x00400000
-#define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK 0x40000000
-#define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK 0x40000000
-#define A6XX_GMU_OOB_DCVS_SET_MASK 0x00800000
-#define A6XX_GMU_OOB_DCVS_CHECK_MASK 0x80000000
-#define A6XX_GMU_OOB_DCVS_CLEAR_MASK 0x80000000
-#define A6XX_GMU_OOB_GPU_SET_MASK 0x00040000
-#define A6XX_GMU_OOB_GPU_CHECK_MASK 0x04000000
-#define A6XX_GMU_OOB_GPU_CLEAR_MASK 0x04000000
-#define A6XX_GMU_OOB_PERFCNTR_SET_MASK 0x00020000
-#define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK 0x02000000
-#define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK 0x02000000
-
-#define A6XX_HFI_IRQ_MSGQ_MASK 0x00000001
-#define A6XX_HFI_IRQ_DSGQ_MASK 0x00000002
-#define A6XX_HFI_IRQ_BLOCKED_MSG_MASK 0x00000004
-#define A6XX_HFI_IRQ_CM3_FAULT_MASK 0x00800000
-#define A6XX_HFI_IRQ_GMU_ERR_MASK__MASK 0x007f0000
-#define A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT 16
-static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val)
-{
- return ((val) << A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT) & A6XX_HFI_IRQ_GMU_ERR_MASK__MASK;
-}
-#define A6XX_HFI_IRQ_OOB_MASK__MASK 0xff000000
-#define A6XX_HFI_IRQ_OOB_MASK__SHIFT 24
-static inline uint32_t A6XX_HFI_IRQ_OOB_MASK(uint32_t val)
-{
- return ((val) << A6XX_HFI_IRQ_OOB_MASK__SHIFT) & A6XX_HFI_IRQ_OOB_MASK__MASK;
-}
-
-#define A6XX_HFI_H2F_IRQ_MASK_BIT 0x00000001
-
-#define REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL 0x00000080
-
-#define REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL 0x00000081
-
-#define REG_A6XX_GMU_CM3_ITCM_START 0x00000c00
-
-#define REG_A6XX_GMU_CM3_DTCM_START 0x00001c00
-
-#define REG_A6XX_GMU_NMI_CONTROL_STATUS 0x000023f0
-
-#define REG_A6XX_GMU_BOOT_SLUMBER_OPTION 0x000023f8
-
-#define REG_A6XX_GMU_GX_VOTE_IDX 0x000023f9
-
-#define REG_A6XX_GMU_MX_VOTE_IDX 0x000023fa
-
-#define REG_A6XX_GMU_DCVS_ACK_OPTION 0x000023fc
-
-#define REG_A6XX_GMU_DCVS_PERF_SETTING 0x000023fd
-
-#define REG_A6XX_GMU_DCVS_BW_SETTING 0x000023fe
-
-#define REG_A6XX_GMU_DCVS_RETURN 0x000023ff
-
-#define REG_A6XX_GMU_ICACHE_CONFIG 0x00004c00
-
-#define REG_A6XX_GMU_DCACHE_CONFIG 0x00004c01
-
-#define REG_A6XX_GMU_SYS_BUS_CONFIG 0x00004c0f
-
-#define REG_A6XX_GMU_CM3_SYSRESET 0x00005000
-
-#define REG_A6XX_GMU_CM3_BOOT_CONFIG 0x00005001
-
-#define REG_A6XX_GMU_CM3_FW_BUSY 0x0000501a
-
-#define REG_A6XX_GMU_CM3_FW_INIT_RESULT 0x0000501c
-
-#define REG_A6XX_GMU_CM3_CFG 0x0000502d
-
-#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE 0x00005040
-
-#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0 0x00005041
-
-#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1 0x00005042
-
-#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L 0x00005044
-
-#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H 0x00005045
-
-#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L 0x00005046
-
-#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H 0x00005047
-
-#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L 0x00005048
-
-#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H 0x00005049
-
-#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L 0x0000504a
-
-#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H 0x0000504b
-
-#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L 0x0000504c
-
-#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H 0x0000504d
-
-#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L 0x0000504e
-
-#define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H 0x0000504f
-
-#define REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL 0x000050c0
-#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE 0x00000001
-#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE 0x00000002
-#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE 0x00000004
-#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK 0x00003c00
-#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT 10
-static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS(uint32_t val)
-{
- return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK;
-}
-#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK 0xffffc000
-#define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT 14
-static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_t val)
-{
- return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK;
-}
-
-#define REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST 0x000050c1
-
-#define REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST 0x000050c2
-
-#define REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS 0x000050d0
-#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF 0x00000001
-#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON 0x00000002
-#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF 0x00000004
-#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON 0x00000008
-#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF 0x00000010
-#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE 0x00000020
-#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF 0x00000040
-#define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF 0x00000080
-
-#define REG_A6XX_GMU_GPU_NAP_CTRL 0x000050e4
-#define A6XX_GMU_GPU_NAP_CTRL_HW_NAP_ENABLE 0x00000001
-#define A6XX_GMU_GPU_NAP_CTRL_SID__MASK 0x000001f0
-#define A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT 4
-static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
-{
- return ((val) << A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT) & A6XX_GMU_GPU_NAP_CTRL_SID__MASK;
-}
-
-#define REG_A6XX_GMU_RPMH_CTRL 0x000050e8
-#define A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE 0x00000001
-#define A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE 0x00000010
-#define A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE 0x00000100
-#define A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE 0x00000200
-#define A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE 0x00000400
-#define A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE 0x00000800
-#define A6XX_GMU_RPMH_CTRL_DDR_MIN_VOTE_ENABLE 0x00001000
-#define A6XX_GMU_RPMH_CTRL_MX_MIN_VOTE_ENABLE 0x00002000
-#define A6XX_GMU_RPMH_CTRL_CX_MIN_VOTE_ENABLE 0x00004000
-#define A6XX_GMU_RPMH_CTRL_GFX_MIN_VOTE_ENABLE 0x00008000
-
-#define REG_A6XX_GMU_RPMH_HYST_CTRL 0x000050e9
-
-#define REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE 0x000050ec
-
-#define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x000050f0
-
-#define REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF 0x000050f1
-
-#define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG 0x00005100
-
-#define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP 0x00005101
-
-#define REG_A6XX_GMU_BOOT_KMD_LM_HANDSHAKE 0x000051f0
-
-#define REG_A6XX_GMU_LLM_GLM_SLEEP_CTRL 0x00005157
-
-#define REG_A6XX_GMU_LLM_GLM_SLEEP_STATUS 0x00005158
-
-#define REG_A6XX_GMU_ALWAYS_ON_COUNTER_L 0x00005088
-
-#define REG_A6XX_GMU_ALWAYS_ON_COUNTER_H 0x00005089
-
-#define REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE 0x000050c3
-
-#define REG_A6XX_GMU_HFI_CTRL_STATUS 0x00005180
-
-#define REG_A6XX_GMU_HFI_VERSION_INFO 0x00005181
-
-#define REG_A6XX_GMU_HFI_SFR_ADDR 0x00005182
-
-#define REG_A6XX_GMU_HFI_MMAP_ADDR 0x00005183
-
-#define REG_A6XX_GMU_HFI_QTBL_INFO 0x00005184
-
-#define REG_A6XX_GMU_HFI_QTBL_ADDR 0x00005185
-
-#define REG_A6XX_GMU_HFI_CTRL_INIT 0x00005186
-
-#define REG_A6XX_GMU_GMU2HOST_INTR_SET 0x00005190
-
-#define REG_A6XX_GMU_GMU2HOST_INTR_CLR 0x00005191
-
-#define REG_A6XX_GMU_GMU2HOST_INTR_INFO 0x00005192
-#define A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ 0x00000001
-#define A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT 0x00800000
-
-#define REG_A6XX_GMU_GMU2HOST_INTR_MASK 0x00005193
-
-#define REG_A6XX_GMU_HOST2GMU_INTR_SET 0x00005194
-
-#define REG_A6XX_GMU_HOST2GMU_INTR_CLR 0x00005195
-
-#define REG_A6XX_GMU_HOST2GMU_INTR_RAW_INFO 0x00005196
-
-#define REG_A6XX_GMU_HOST2GMU_INTR_EN_0 0x00005197
-
-#define REG_A6XX_GMU_HOST2GMU_INTR_EN_1 0x00005198
-
-#define REG_A6XX_GMU_HOST2GMU_INTR_EN_2 0x00005199
-
-#define REG_A6XX_GMU_HOST2GMU_INTR_EN_3 0x0000519a
-
-#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_0 0x0000519b
-
-#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_1 0x0000519c
-
-#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_2 0x0000519d
-
-#define REG_A6XX_GMU_HOST2GMU_INTR_INFO_3 0x0000519e
-
-#define REG_A6XX_GMU_GENERAL_0 0x000051c5
-
-#define REG_A6XX_GMU_GENERAL_1 0x000051c6
-
-#define REG_A6XX_GMU_GENERAL_6 0x000051cb
-
-#define REG_A6XX_GMU_GENERAL_7 0x000051cc
-
-#define REG_A7XX_GMU_GENERAL_8 0x000051cd
-
-#define REG_A7XX_GMU_GENERAL_9 0x000051ce
-
-#define REG_A7XX_GMU_GENERAL_10 0x000051cf
-
-#define REG_A6XX_GMU_ISENSE_CTRL 0x0000515d
-
-#define REG_A6XX_GPU_CS_ENABLE_REG 0x00008920
-
-#define REG_A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL 0x0000515d
-
-#define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL3 0x00008578
-
-#define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL2 0x00008558
-
-#define REG_A6XX_GPU_CS_A_SENSOR_CTRL_0 0x00008580
-
-#define REG_A6XX_GPU_CS_A_SENSOR_CTRL_2 0x00027ada
-
-#define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a
-
-#define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x00008957
-
-#define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a
-
-#define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000881d
-
-#define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000881f
-
-#define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x00008821
-
-#define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965
-
-#define REG_A6XX_GPU_CS_AMP_PERIOD_CTRL 0x0000896d
-
-#define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965
-
-#define REG_A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD 0x0000514d
-
-#define REG_A6XX_GMU_AO_INTERRUPT_EN 0x00009303
-
-#define REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR 0x00009304
-
-#define REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS 0x00009305
-#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE 0x00000001
-#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_RSCC_COMP 0x00000002
-#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_VDROOP 0x00000004
-#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR 0x00000008
-#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_DBD_WAKEUP 0x00000010
-#define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR 0x00000020
-
-#define REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK 0x00009306
-
-#define REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL 0x00009309
-
-#define REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL 0x0000930a
-
-#define REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL 0x0000930b
-
-#define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS 0x0000930c
-#define A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB 0x00800000
-
-#define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2 0x0000930d
-
-#define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK 0x0000930e
-
-#define REG_A6XX_GMU_AO_AHB_FENCE_CTRL 0x00009310
-
-#define REG_A6XX_GMU_AHB_FENCE_STATUS 0x00009313
-
-#define REG_A6XX_GMU_AHB_FENCE_STATUS_CLR 0x00009314
-
-#define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x00009315
-
-#define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316
-
-#define REG_A6XX_GMU_RSCC_CONTROL_REQ 0x00009307
-
-#define REG_A6XX_GMU_RSCC_CONTROL_ACK 0x00009308
-
-#define REG_A6XX_GMU_AHB_FENCE_RANGE_0 0x00009311
-
-#define REG_A6XX_GMU_AHB_FENCE_RANGE_1 0x00009312
-
-#define REG_A6XX_GPU_CC_GX_GDSCR 0x00009c03
-
-#define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42
-
-#define REG_A6XX_GPU_CPR_FSM_CTL 0x0000c001
-
-#define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00000004
-
-#define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00000008
-
-#define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO 0x00000009
-
-#define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI 0x0000000a
-
-#define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0 0x0000000b
-
-#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR 0x0000000d
-
-#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA 0x0000000e
-
-#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0 0x00000082
-
-#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0 0x00000083
-
-#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0 0x00000089
-
-#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0 0x0000008c
-
-#define REG_A6XX_RSCC_OVERRIDE_START_ADDR 0x00000100
-
-#define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00000101
-
-#define REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740 0x00000154
-
-#define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00000180
-
-#define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00000346
-
-#define REG_A6XX_RSCC_TCS1_DRV0_STATUS 0x000003ee
-
-#define REG_A6XX_RSCC_TCS2_DRV0_STATUS 0x00000496
-
-#define REG_A6XX_RSCC_TCS3_DRV0_STATUS 0x0000053e
-
-#ifdef __cplusplus
-#endif
-
-#endif /* A6XX_GMU_XML */
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index cf0b1de1c071..973872ad0474 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -284,7 +284,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
- get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
+ get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0),
rbmemptr_stats(ring, index, cpcycles_start));
get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
rbmemptr_stats(ring, index, alwayson_start));
@@ -330,7 +330,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
OUT_PKT7(ring, CP_SET_MARKER, 1);
OUT_RING(ring, 0x00e); /* IB1LIST end */
- get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
+ get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0),
rbmemptr_stats(ring, index, cpcycles_end));
get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
rbmemptr_stats(ring, index, alwayson_end));
@@ -1255,8 +1255,9 @@ static const u32 a730_protect[] = {
A6XX_PROTECT_NORDWR(0x00699, 0x01e9),
A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
- /* 0x008d0-0x008dd are unprotected on purpose for tools like perfetto */
- A6XX_PROTECT_RDONLY(0x008de, 0x0154),
+ /* 0x008d0-0x008dd and 0x008e0-0x008e6 are unprotected on purpose for tools like perfetto */
+ A6XX_PROTECT_NORDWR(0x008de, 0x0001),
+ A6XX_PROTECT_RDONLY(0x008e7, 0x014b),
A6XX_PROTECT_NORDWR(0x00900, 0x004d),
A6XX_PROTECT_NORDWR(0x0098d, 0x00b2),
A6XX_PROTECT_NORDWR(0x00a41, 0x01be),
@@ -1291,8 +1292,7 @@ static const u32 a730_protect[] = {
A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
A6XX_PROTECT_NORDWR(0x1f878, 0x002a),
- /* CP_PROTECT_REG[44, 46] are left untouched! */
- 0,
+ /* CP_PROTECT_REG[45, 46] are left untouched! */
0,
0,
A6XX_PROTECT_NORDWR(0x1f8c0, 0x00000),
@@ -3062,7 +3062,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
ret = a6xx_set_supported_hw(&pdev->dev, config->info);
if (ret) {
- a6xx_destroy(&(a6xx_gpu->base.base));
+ a6xx_llc_slices_destroy(a6xx_gpu);
+ kfree(a6xx_gpu);
return ERR_PTR(ret);
}
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index 34822b080759..8917032b7515 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -69,12 +69,12 @@ static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u3
static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)
{
- return msm_readl(a6xx_gpu->llc_mmio + (reg << 2));
+ return readl(a6xx_gpu->llc_mmio + (reg << 2));
}
static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
{
- msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
+ writel(value, a6xx_gpu->llc_mmio + (reg << 2));
}
#define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
index a847a0f7a73c..0a7717a4fc2f 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
@@ -13,15 +13,18 @@
*/
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wunused-variable"
+#pragma GCC diagnostic ignored "-Wunused-const-variable"
#include "adreno_gen7_0_0_snapshot.h"
#include "adreno_gen7_2_0_snapshot.h"
+#include "adreno_gen7_9_0_snapshot.h"
#pragma GCC diagnostic pop
struct a6xx_gpu_state_obj {
const void *handle;
u32 *data;
+ u32 count; /* optional, used when count potentially read from hw */
};
struct a6xx_gpu_state {
@@ -192,10 +195,10 @@ static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset,
}
#define cxdbg_write(ptr, offset, val) \
- msm_writel((val), (ptr) + ((offset) << 2))
+ writel((val), (ptr) + ((offset) << 2))
#define cxdbg_read(ptr, offset) \
- msm_readl((ptr) + ((offset) << 2))
+ readl((ptr) + ((offset) << 2))
/* read a value from the CX debug bus */
static int cx_debugbus_read(void __iomem *cxdbg, u32 block, u32 offset,
@@ -384,21 +387,29 @@ static void a7xx_get_debugbus_blocks(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
- int debugbus_blocks_count, total_debugbus_blocks;
- const u32 *debugbus_blocks;
+ int debugbus_blocks_count, gbif_debugbus_blocks_count, total_debugbus_blocks;
+ const u32 *debugbus_blocks, *gbif_debugbus_blocks;
int i;
if (adreno_is_a730(adreno_gpu)) {
debugbus_blocks = gen7_0_0_debugbus_blocks;
debugbus_blocks_count = ARRAY_SIZE(gen7_0_0_debugbus_blocks);
- } else {
- BUG_ON(!adreno_is_a740_family(adreno_gpu));
+ gbif_debugbus_blocks = a7xx_gbif_debugbus_blocks;
+ gbif_debugbus_blocks_count = ARRAY_SIZE(a7xx_gbif_debugbus_blocks);
+ } else if (adreno_is_a740_family(adreno_gpu)) {
debugbus_blocks = gen7_2_0_debugbus_blocks;
debugbus_blocks_count = ARRAY_SIZE(gen7_2_0_debugbus_blocks);
+ gbif_debugbus_blocks = a7xx_gbif_debugbus_blocks;
+ gbif_debugbus_blocks_count = ARRAY_SIZE(a7xx_gbif_debugbus_blocks);
+ } else {
+ BUG_ON(!adreno_is_a750(adreno_gpu));
+ debugbus_blocks = gen7_9_0_debugbus_blocks;
+ debugbus_blocks_count = ARRAY_SIZE(gen7_9_0_debugbus_blocks);
+ gbif_debugbus_blocks = gen7_9_0_gbif_debugbus_blocks;
+ gbif_debugbus_blocks_count = ARRAY_SIZE(gen7_9_0_gbif_debugbus_blocks);
}
- total_debugbus_blocks = debugbus_blocks_count +
- ARRAY_SIZE(a7xx_gbif_debugbus_blocks);
+ total_debugbus_blocks = debugbus_blocks_count + gbif_debugbus_blocks_count;
a6xx_state->debugbus = state_kcalloc(a6xx_state, total_debugbus_blocks,
sizeof(*a6xx_state->debugbus));
@@ -410,9 +421,9 @@ static void a7xx_get_debugbus_blocks(struct msm_gpu *gpu,
&a6xx_state->debugbus[i]);
}
- for (i = 0; i < ARRAY_SIZE(a7xx_gbif_debugbus_blocks); i++) {
+ for (i = 0; i < gbif_debugbus_blocks_count; i++) {
a6xx_get_debugbus_block(gpu,
- a6xx_state, &a7xx_gbif_debugbus_blocks[i],
+ a6xx_state, &a7xx_debugbus_blocks[gbif_debugbus_blocks[i]],
&a6xx_state->debugbus[i + debugbus_blocks_count]);
}
}
@@ -813,10 +824,13 @@ static void a7xx_get_clusters(struct msm_gpu *gpu,
if (adreno_is_a730(adreno_gpu)) {
clusters = gen7_0_0_clusters;
clusters_size = ARRAY_SIZE(gen7_0_0_clusters);
- } else {
- BUG_ON(!adreno_is_a740_family(adreno_gpu));
+ } else if (adreno_is_a740_family(adreno_gpu)) {
clusters = gen7_2_0_clusters;
clusters_size = ARRAY_SIZE(gen7_2_0_clusters);
+ } else {
+ BUG_ON(!adreno_is_a750(adreno_gpu));
+ clusters = gen7_9_0_clusters;
+ clusters_size = ARRAY_SIZE(gen7_9_0_clusters);
}
a6xx_state->clusters = state_kcalloc(a6xx_state,
@@ -948,10 +962,13 @@ static void a7xx_get_shaders(struct msm_gpu *gpu,
if (adreno_is_a730(adreno_gpu)) {
shader_blocks = gen7_0_0_shader_blocks;
num_shader_blocks = ARRAY_SIZE(gen7_0_0_shader_blocks);
- } else {
- BUG_ON(!adreno_is_a740_family(adreno_gpu));
+ } else if (adreno_is_a740_family(adreno_gpu)) {
shader_blocks = gen7_2_0_shader_blocks;
num_shader_blocks = ARRAY_SIZE(gen7_2_0_shader_blocks);
+ } else {
+ BUG_ON(!adreno_is_a750(adreno_gpu));
+ shader_blocks = gen7_9_0_shader_blocks;
+ num_shader_blocks = ARRAY_SIZE(gen7_9_0_shader_blocks);
}
a6xx_state->shaders = state_kcalloc(a6xx_state,
@@ -1337,10 +1354,13 @@ static void a7xx_get_registers(struct msm_gpu *gpu,
if (adreno_is_a730(adreno_gpu)) {
reglist = gen7_0_0_reg_list;
pre_crashdumper_regs = gen7_0_0_pre_crashdumper_gpu_registers;
- } else {
- BUG_ON(!adreno_is_a740_family(adreno_gpu));
+ } else if (adreno_is_a740_family(adreno_gpu)) {
reglist = gen7_2_0_reg_list;
pre_crashdumper_regs = gen7_0_0_pre_crashdumper_gpu_registers;
+ } else {
+ BUG_ON(!adreno_is_a750(adreno_gpu));
+ reglist = gen7_9_0_reg_list;
+ pre_crashdumper_regs = gen7_9_0_pre_crashdumper_gpu_registers;
}
count = A7XX_PRE_CRASHDUMPER_SIZE + A7XX_POST_CRASHDUMPER_SIZE;
@@ -1388,7 +1408,8 @@ static void a7xx_get_post_crashdumper_registers(struct msm_gpu *gpu,
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
const u32 *regs;
- BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu)));
+ BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu) ||
+ adreno_is_a750(adreno_gpu)));
regs = gen7_0_0_post_crashdumper_registers;
a7xx_get_ahb_gpu_registers(gpu,
@@ -1417,16 +1438,18 @@ static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu)
/* Read a block of data from an indexed register pair */
static void a6xx_get_indexed_regs(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
- struct a6xx_indexed_registers *indexed,
+ const struct a6xx_indexed_registers *indexed,
struct a6xx_gpu_state_obj *obj)
{
+ u32 count = indexed->count;
int i;
obj->handle = (const void *) indexed;
if (indexed->count_fn)
- indexed->count = indexed->count_fn(gpu);
+ count = indexed->count_fn(gpu);
- obj->data = state_kcalloc(a6xx_state, indexed->count, sizeof(u32));
+ obj->data = state_kcalloc(a6xx_state, count, sizeof(u32));
+ obj->count = count;
if (!obj->data)
return;
@@ -1434,7 +1457,7 @@ static void a6xx_get_indexed_regs(struct msm_gpu *gpu,
gpu_write(gpu, indexed->addr, 0);
/* Read the data - each read increments the internal address by 1 */
- for (i = 0; i < indexed->count; i++)
+ for (i = 0; i < count; i++)
obj->data[i] = gpu_read(gpu, indexed->data);
}
@@ -1491,10 +1514,18 @@ static void a7xx_get_indexed_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ const struct a6xx_indexed_registers *indexed_regs;
int i, indexed_count, mempool_count;
- BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu)));
- indexed_count = ARRAY_SIZE(a7xx_indexed_reglist);
+ if (adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu)) {
+ indexed_regs = a7xx_indexed_reglist;
+ indexed_count = ARRAY_SIZE(a7xx_indexed_reglist);
+ } else {
+ BUG_ON(!adreno_is_a750(adreno_gpu));
+ indexed_regs = gen7_9_0_cp_indexed_reg_list;
+ indexed_count = ARRAY_SIZE(gen7_9_0_cp_indexed_reg_list);
+ }
+
mempool_count = ARRAY_SIZE(a7xx_cp_bv_mempool_indexed);
a6xx_state->indexed_regs = state_kcalloc(a6xx_state,
@@ -1507,7 +1538,7 @@ static void a7xx_get_indexed_registers(struct msm_gpu *gpu,
/* First read the common regs */
for (i = 0; i < indexed_count; i++)
- a6xx_get_indexed_regs(gpu, a6xx_state, &a7xx_indexed_reglist[i],
+ a6xx_get_indexed_regs(gpu, a6xx_state, &indexed_regs[i],
&a6xx_state->indexed_regs[i]);
gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, 0, BIT(2));
@@ -1862,9 +1893,9 @@ static void a6xx_show_indexed_regs(struct a6xx_gpu_state_obj *obj,
return;
print_name(p, " - regs-name: ", indexed->name);
- drm_printf(p, " dwords: %d\n", indexed->count);
+ drm_printf(p, " dwords: %d\n", obj->count);
- print_ascii85(p, indexed->count << 2, obj->data);
+ print_ascii85(p, obj->count << 2, obj->data);
}
static void a6xx_show_debugbus_block(const struct a6xx_debugbus_block *block,
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
index 5ddd32063bcc..dd4c28a8d923 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
@@ -397,7 +397,7 @@ struct a6xx_indexed_registers {
u32 (*count_fn)(struct msm_gpu *gpu);
};
-static struct a6xx_indexed_registers a6xx_indexed_reglist[] = {
+static const struct a6xx_indexed_registers a6xx_indexed_reglist[] = {
{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
@@ -408,7 +408,7 @@ static struct a6xx_indexed_registers a6xx_indexed_reglist[] = {
REG_A6XX_CP_ROQ_DBG_DATA, 0, a6xx_get_cp_roq_size},
};
-static struct a6xx_indexed_registers a7xx_indexed_reglist[] = {
+static const struct a6xx_indexed_registers a7xx_indexed_reglist[] = {
{ "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
REG_A6XX_CP_SQE_STAT_DATA, 0x33, NULL },
{ "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
@@ -433,12 +433,12 @@ static struct a6xx_indexed_registers a7xx_indexed_reglist[] = {
REG_A6XX_CP_ROQ_DBG_DATA, 0, a7xx_get_cp_roq_size },
};
-static struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
+static const struct a6xx_indexed_registers a6xx_cp_mempool_indexed = {
"CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2060, NULL,
};
-static struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = {
+static const struct a6xx_indexed_registers a7xx_cp_bv_mempool_indexed[] = {
{ "CP_MEMPOOL", REG_A6XX_CP_MEM_POOL_DBG_ADDR,
REG_A6XX_CP_MEM_POOL_DBG_DATA, 0x2100, NULL },
{ "CP_BV_MEMPOOL", REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR,
@@ -517,9 +517,9 @@ static const struct a6xx_debugbus_block a650_debugbus_blocks[] = {
DEBUGBUS(A6XX_DBGBUS_SPTP_5, 0x100),
};
-static const struct a6xx_debugbus_block a7xx_gbif_debugbus_blocks[] = {
- DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100),
- DEBUGBUS(A7XX_DBGBUS_GBIF_GX, 0x100),
+static const u32 a7xx_gbif_debugbus_blocks[] = {
+ A7XX_DBGBUS_GBIF_CX,
+ A7XX_DBGBUS_GBIF_GX,
};
static const struct a6xx_debugbus_block a7xx_cx_debugbus_blocks[] = {
diff --git a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
deleted file mode 100644
index fbc27930e550..000000000000
--- a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
+++ /dev/null
@@ -1,539 +0,0 @@
-#ifndef ADRENO_COMMON_XML
-#define ADRENO_COMMON_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
-http://gitlab.freedesktop.org/mesa/mesa/
-git clone https://gitlab.freedesktop.org/mesa/mesa.git
-
-The rules-ng-ng source files this header was generated from are:
-
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
-*/
-
-#ifdef __KERNEL__
-#include <linux/bug.h>
-#define assert(x) BUG_ON(!(x))
-#else
-#include <assert.h>
-#endif
-
-#ifdef __cplusplus
-#define __struct_cast(X)
-#else
-#define __struct_cast(X) (struct X)
-#endif
-
-enum chip {
- A2XX = 2,
- A3XX = 3,
- A4XX = 4,
- A5XX = 5,
- A6XX = 6,
- A7XX = 7,
-};
-
-enum adreno_pa_su_sc_draw {
- PC_DRAW_POINTS = 0,
- PC_DRAW_LINES = 1,
- PC_DRAW_TRIANGLES = 2,
-};
-
-enum adreno_compare_func {
- FUNC_NEVER = 0,
- FUNC_LESS = 1,
- FUNC_EQUAL = 2,
- FUNC_LEQUAL = 3,
- FUNC_GREATER = 4,
- FUNC_NOTEQUAL = 5,
- FUNC_GEQUAL = 6,
- FUNC_ALWAYS = 7,
-};
-
-enum adreno_stencil_op {
- STENCIL_KEEP = 0,
- STENCIL_ZERO = 1,
- STENCIL_REPLACE = 2,
- STENCIL_INCR_CLAMP = 3,
- STENCIL_DECR_CLAMP = 4,
- STENCIL_INVERT = 5,
- STENCIL_INCR_WRAP = 6,
- STENCIL_DECR_WRAP = 7,
-};
-
-enum adreno_rb_blend_factor {
- FACTOR_ZERO = 0,
- FACTOR_ONE = 1,
- FACTOR_SRC_COLOR = 4,
- FACTOR_ONE_MINUS_SRC_COLOR = 5,
- FACTOR_SRC_ALPHA = 6,
- FACTOR_ONE_MINUS_SRC_ALPHA = 7,
- FACTOR_DST_COLOR = 8,
- FACTOR_ONE_MINUS_DST_COLOR = 9,
- FACTOR_DST_ALPHA = 10,
- FACTOR_ONE_MINUS_DST_ALPHA = 11,
- FACTOR_CONSTANT_COLOR = 12,
- FACTOR_ONE_MINUS_CONSTANT_COLOR = 13,
- FACTOR_CONSTANT_ALPHA = 14,
- FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15,
- FACTOR_SRC_ALPHA_SATURATE = 16,
- FACTOR_SRC1_COLOR = 20,
- FACTOR_ONE_MINUS_SRC1_COLOR = 21,
- FACTOR_SRC1_ALPHA = 22,
- FACTOR_ONE_MINUS_SRC1_ALPHA = 23,
-};
-
-enum adreno_rb_surface_endian {
- ENDIAN_NONE = 0,
- ENDIAN_8IN16 = 1,
- ENDIAN_8IN32 = 2,
- ENDIAN_16IN32 = 3,
- ENDIAN_8IN64 = 4,
- ENDIAN_8IN128 = 5,
-};
-
-enum adreno_rb_dither_mode {
- DITHER_DISABLE = 0,
- DITHER_ALWAYS = 1,
- DITHER_IF_ALPHA_OFF = 2,
-};
-
-enum adreno_rb_depth_format {
- DEPTHX_16 = 0,
- DEPTHX_24_8 = 1,
- DEPTHX_32 = 2,
-};
-
-enum adreno_rb_copy_control_mode {
- RB_COPY_RESOLVE = 1,
- RB_COPY_CLEAR = 2,
- RB_COPY_DEPTH_STENCIL = 5,
-};
-
-enum a3xx_rop_code {
- ROP_CLEAR = 0,
- ROP_NOR = 1,
- ROP_AND_INVERTED = 2,
- ROP_COPY_INVERTED = 3,
- ROP_AND_REVERSE = 4,
- ROP_INVERT = 5,
- ROP_XOR = 6,
- ROP_NAND = 7,
- ROP_AND = 8,
- ROP_EQUIV = 9,
- ROP_NOOP = 10,
- ROP_OR_INVERTED = 11,
- ROP_COPY = 12,
- ROP_OR_REVERSE = 13,
- ROP_OR = 14,
- ROP_SET = 15,
-};
-
-enum a3xx_render_mode {
- RB_RENDERING_PASS = 0,
- RB_TILING_PASS = 1,
- RB_RESOLVE_PASS = 2,
- RB_COMPUTE_PASS = 3,
-};
-
-enum a3xx_msaa_samples {
- MSAA_ONE = 0,
- MSAA_TWO = 1,
- MSAA_FOUR = 2,
- MSAA_EIGHT = 3,
-};
-
-enum a3xx_threadmode {
- MULTI = 0,
- SINGLE = 1,
-};
-
-enum a3xx_instrbuffermode {
- CACHE = 0,
- BUFFER = 1,
-};
-
-enum a3xx_threadsize {
- TWO_QUADS = 0,
- FOUR_QUADS = 1,
-};
-
-enum a3xx_color_swap {
- WZYX = 0,
- WXYZ = 1,
- ZYXW = 2,
- XYZW = 3,
-};
-
-enum a3xx_rb_blend_opcode {
- BLEND_DST_PLUS_SRC = 0,
- BLEND_SRC_MINUS_DST = 1,
- BLEND_DST_MINUS_SRC = 2,
- BLEND_MIN_DST_SRC = 3,
- BLEND_MAX_DST_SRC = 4,
-};
-
-enum a4xx_tess_spacing {
- EQUAL_SPACING = 0,
- ODD_SPACING = 2,
- EVEN_SPACING = 3,
-};
-
-enum a5xx_address_mode {
- ADDR_32B = 0,
- ADDR_64B = 1,
-};
-
-enum a5xx_line_mode {
- BRESENHAM = 0,
- RECTANGULAR = 1,
-};
-
-enum a6xx_tex_prefetch_cmd {
- TEX_PREFETCH_UNK0 = 0,
- TEX_PREFETCH_SAM = 1,
- TEX_PREFETCH_GATHER4R = 2,
- TEX_PREFETCH_GATHER4G = 3,
- TEX_PREFETCH_GATHER4B = 4,
- TEX_PREFETCH_GATHER4A = 5,
- TEX_PREFETCH_UNK6 = 6,
- TEX_PREFETCH_UNK7 = 7,
-};
-
-#define REG_AXXX_CP_RB_BASE 0x000001c0
-
-#define REG_AXXX_CP_RB_CNTL 0x000001c1
-#define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f
-#define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0
-static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val)
-{
- return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK;
-}
-#define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00
-#define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8
-static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val)
-{
- return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK;
-}
-#define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000
-#define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16
-static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val)
-{
- return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK;
-}
-#define AXXX_CP_RB_CNTL_POLL_EN 0x00100000
-#define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000
-#define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000
-
-#define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3
-#define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003
-#define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0
-static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val)
-{
- return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK;
-}
-#define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc
-#define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2
-static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK;
-}
-
-#define REG_AXXX_CP_RB_RPTR 0x000001c4
-
-#define REG_AXXX_CP_RB_WPTR 0x000001c5
-
-#define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6
-
-#define REG_AXXX_CP_RB_RPTR_WR 0x000001c7
-
-#define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8
-
-#define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5
-#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f
-#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0
-static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val)
-{
- return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK;
-}
-#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00
-#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8
-static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val)
-{
- return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK;
-}
-#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000
-#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16
-static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
-{
- return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK;
-}
-
-#define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6
-#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000
-#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16
-static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val)
-{
- return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK;
-}
-#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000
-#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24
-static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val)
-{
- return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK;
-}
-
-#define REG_AXXX_CP_CSQ_AVAIL 0x000001d7
-#define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f
-#define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0
-static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val)
-{
- return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK;
-}
-#define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00
-#define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8
-static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val)
-{
- return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK;
-}
-#define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000
-#define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16
-static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val)
-{
- return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK;
-}
-
-#define REG_AXXX_CP_STQ_AVAIL 0x000001d8
-#define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f
-#define AXXX_CP_STQ_AVAIL_ST__SHIFT 0
-static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val)
-{
- return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK;
-}
-
-#define REG_AXXX_CP_MEQ_AVAIL 0x000001d9
-#define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f
-#define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0
-static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val)
-{
- return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK;
-}
-
-#define REG_AXXX_SCRATCH_UMSK 0x000001dc
-#define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff
-#define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0
-static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val)
-{
- return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK;
-}
-#define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000
-#define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16
-static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
-{
- return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK;
-}
-
-#define REG_AXXX_SCRATCH_ADDR 0x000001dd
-
-#define REG_AXXX_CP_ME_RDADDR 0x000001ea
-
-#define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec
-
-#define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed
-
-#define REG_AXXX_CP_INT_CNTL 0x000001f2
-#define AXXX_CP_INT_CNTL_SW_INT_MASK 0x00080000
-#define AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK 0x00800000
-#define AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK 0x01000000
-#define AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK 0x02000000
-#define AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK 0x04000000
-#define AXXX_CP_INT_CNTL_IB_ERROR_MASK 0x08000000
-#define AXXX_CP_INT_CNTL_IB2_INT_MASK 0x20000000
-#define AXXX_CP_INT_CNTL_IB1_INT_MASK 0x40000000
-#define AXXX_CP_INT_CNTL_RB_INT_MASK 0x80000000
-
-#define REG_AXXX_CP_INT_STATUS 0x000001f3
-
-#define REG_AXXX_CP_INT_ACK 0x000001f4
-
-#define REG_AXXX_CP_ME_CNTL 0x000001f6
-#define AXXX_CP_ME_CNTL_BUSY 0x20000000
-#define AXXX_CP_ME_CNTL_HALT 0x10000000
-
-#define REG_AXXX_CP_ME_STATUS 0x000001f7
-
-#define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8
-
-#define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9
-
-#define REG_AXXX_CP_ME_RAM_DATA 0x000001fa
-
-#define REG_AXXX_CP_DEBUG 0x000001fc
-#define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000
-#define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000
-#define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000
-#define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000
-#define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000
-#define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000
-#define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000
-#define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000
-
-#define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd
-#define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f
-#define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0
-static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val)
-{
- return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK;
-}
-#define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000
-#define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16
-static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val)
-{
- return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK;
-}
-
-#define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe
-#define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f
-#define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0
-static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val)
-{
- return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK;
-}
-#define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000
-#define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16
-static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val)
-{
- return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK;
-}
-
-#define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff
-#define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f
-#define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0
-static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val)
-{
- return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK;
-}
-#define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000
-#define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16
-static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
-{
- return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;
-}
-
-#define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440
-
-#define REG_AXXX_CP_STQ_ST_STAT 0x00000443
-
-#define REG_AXXX_CP_ST_BASE 0x0000044d
-
-#define REG_AXXX_CP_ST_BUFSZ 0x0000044e
-
-#define REG_AXXX_CP_MEQ_STAT 0x0000044f
-
-#define REG_AXXX_CP_MIU_TAG_STAT 0x00000452
-
-#define REG_AXXX_CP_BIN_MASK_LO 0x00000454
-
-#define REG_AXXX_CP_BIN_MASK_HI 0x00000455
-
-#define REG_AXXX_CP_BIN_SELECT_LO 0x00000456
-
-#define REG_AXXX_CP_BIN_SELECT_HI 0x00000457
-
-#define REG_AXXX_CP_IB1_BASE 0x00000458
-
-#define REG_AXXX_CP_IB1_BUFSZ 0x00000459
-
-#define REG_AXXX_CP_IB2_BASE 0x0000045a
-
-#define REG_AXXX_CP_IB2_BUFSZ 0x0000045b
-
-#define REG_AXXX_CP_STAT 0x0000047f
-#define AXXX_CP_STAT_CP_BUSY 0x80000000
-#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000
-#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000
-#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000
-#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000
-#define AXXX_CP_STAT_ME_BUSY 0x04000000
-#define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000
-#define AXXX_CP_STAT_CP_3D_BUSY 0x00800000
-#define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000
-#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000
-#define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000
-#define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000
-#define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000
-#define AXXX_CP_STAT_PFP_BUSY 0x00020000
-#define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000
-#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000
-#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000
-#define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800
-#define AXXX_CP_STAT_CSF_BUSY 0x00000400
-#define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200
-#define AXXX_CP_STAT_EVENT_BUSY 0x00000100
-#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080
-#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040
-#define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020
-#define AXXX_CP_STAT_RCIU_BUSY 0x00000010
-#define AXXX_CP_STAT_RBIU_BUSY 0x00000008
-#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004
-#define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002
-#define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001
-
-#define REG_AXXX_CP_SCRATCH_REG0 0x00000578
-
-#define REG_AXXX_CP_SCRATCH_REG1 0x00000579
-
-#define REG_AXXX_CP_SCRATCH_REG2 0x0000057a
-
-#define REG_AXXX_CP_SCRATCH_REG3 0x0000057b
-
-#define REG_AXXX_CP_SCRATCH_REG4 0x0000057c
-
-#define REG_AXXX_CP_SCRATCH_REG5 0x0000057d
-
-#define REG_AXXX_CP_SCRATCH_REG6 0x0000057e
-
-#define REG_AXXX_CP_SCRATCH_REG7 0x0000057f
-
-#define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600
-
-#define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601
-
-#define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602
-
-#define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603
-
-#define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604
-
-#define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605
-
-#define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606
-
-#define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607
-
-#define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608
-
-#define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609
-
-#define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a
-
-#define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b
-
-#define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c
-
-#define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d
-
-#define REG_AXXX_CP_ME_NRT_DATA 0x0000060e
-
-#define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612
-
-#define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613
-
-#define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614
-
-#ifdef __cplusplus
-#endif
-
-#endif /* ADRENO_COMMON_XML */
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h b/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h
new file mode 100644
index 000000000000..260d66eccfec
--- /dev/null
+++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h
@@ -0,0 +1,1446 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+#ifndef __ADRENO_GEN7_9_0_SNAPSHOT_H
+#define __ADRENO_GEN7_9_0_SNAPSHOT_H
+
+#include "a6xx_gpu_state.h"
+
+static const u32 gen7_9_0_debugbus_blocks[] = {
+ A7XX_DBGBUS_CP_0_0,
+ A7XX_DBGBUS_CP_0_1,
+ A7XX_DBGBUS_RBBM,
+ A7XX_DBGBUS_HLSQ,
+ A7XX_DBGBUS_UCHE_0,
+ A7XX_DBGBUS_UCHE_1,
+ A7XX_DBGBUS_TESS_BR,
+ A7XX_DBGBUS_TESS_BV,
+ A7XX_DBGBUS_PC_BR,
+ A7XX_DBGBUS_PC_BV,
+ A7XX_DBGBUS_VFDP_BR,
+ A7XX_DBGBUS_VFDP_BV,
+ A7XX_DBGBUS_VPC_BR,
+ A7XX_DBGBUS_VPC_BV,
+ A7XX_DBGBUS_TSE_BR,
+ A7XX_DBGBUS_TSE_BV,
+ A7XX_DBGBUS_RAS_BR,
+ A7XX_DBGBUS_RAS_BV,
+ A7XX_DBGBUS_VSC,
+ A7XX_DBGBUS_COM_0,
+ A7XX_DBGBUS_LRZ_BR,
+ A7XX_DBGBUS_LRZ_BV,
+ A7XX_DBGBUS_UFC_0,
+ A7XX_DBGBUS_UFC_1,
+ A7XX_DBGBUS_GMU_GX,
+ A7XX_DBGBUS_DBGC,
+ A7XX_DBGBUS_GPC_BR,
+ A7XX_DBGBUS_GPC_BV,
+ A7XX_DBGBUS_LARC,
+ A7XX_DBGBUS_HLSQ_SPTP,
+ A7XX_DBGBUS_RB_0,
+ A7XX_DBGBUS_RB_1,
+ A7XX_DBGBUS_RB_2,
+ A7XX_DBGBUS_RB_3,
+ A7XX_DBGBUS_RB_4,
+ A7XX_DBGBUS_RB_5,
+ A7XX_DBGBUS_UCHE_WRAPPER,
+ A7XX_DBGBUS_CCU_0,
+ A7XX_DBGBUS_CCU_1,
+ A7XX_DBGBUS_CCU_2,
+ A7XX_DBGBUS_CCU_3,
+ A7XX_DBGBUS_CCU_4,
+ A7XX_DBGBUS_CCU_5,
+ A7XX_DBGBUS_VFD_BR_0,
+ A7XX_DBGBUS_VFD_BR_1,
+ A7XX_DBGBUS_VFD_BR_2,
+ A7XX_DBGBUS_VFD_BV_0,
+ A7XX_DBGBUS_VFD_BV_1,
+ A7XX_DBGBUS_VFD_BV_2,
+ A7XX_DBGBUS_USP_0,
+ A7XX_DBGBUS_USP_1,
+ A7XX_DBGBUS_USP_2,
+ A7XX_DBGBUS_USP_3,
+ A7XX_DBGBUS_USP_4,
+ A7XX_DBGBUS_USP_5,
+ A7XX_DBGBUS_TP_0,
+ A7XX_DBGBUS_TP_1,
+ A7XX_DBGBUS_TP_2,
+ A7XX_DBGBUS_TP_3,
+ A7XX_DBGBUS_TP_4,
+ A7XX_DBGBUS_TP_5,
+ A7XX_DBGBUS_TP_6,
+ A7XX_DBGBUS_TP_7,
+ A7XX_DBGBUS_TP_8,
+ A7XX_DBGBUS_TP_9,
+ A7XX_DBGBUS_TP_10,
+ A7XX_DBGBUS_TP_11,
+ A7XX_DBGBUS_USPTP_0,
+ A7XX_DBGBUS_USPTP_1,
+ A7XX_DBGBUS_USPTP_2,
+ A7XX_DBGBUS_USPTP_3,
+ A7XX_DBGBUS_USPTP_4,
+ A7XX_DBGBUS_USPTP_5,
+ A7XX_DBGBUS_USPTP_6,
+ A7XX_DBGBUS_USPTP_7,
+ A7XX_DBGBUS_USPTP_8,
+ A7XX_DBGBUS_USPTP_9,
+ A7XX_DBGBUS_USPTP_10,
+ A7XX_DBGBUS_USPTP_11,
+ A7XX_DBGBUS_CCHE_0,
+ A7XX_DBGBUS_CCHE_1,
+ A7XX_DBGBUS_CCHE_2,
+ A7XX_DBGBUS_VPC_DSTR_0,
+ A7XX_DBGBUS_VPC_DSTR_1,
+ A7XX_DBGBUS_VPC_DSTR_2,
+ A7XX_DBGBUS_HLSQ_DP_STR_0,
+ A7XX_DBGBUS_HLSQ_DP_STR_1,
+ A7XX_DBGBUS_HLSQ_DP_STR_2,
+ A7XX_DBGBUS_HLSQ_DP_STR_3,
+ A7XX_DBGBUS_HLSQ_DP_STR_4,
+ A7XX_DBGBUS_HLSQ_DP_STR_5,
+ A7XX_DBGBUS_UFC_DSTR_0,
+ A7XX_DBGBUS_UFC_DSTR_1,
+ A7XX_DBGBUS_UFC_DSTR_2,
+ A7XX_DBGBUS_CGC_SUBCORE,
+ A7XX_DBGBUS_CGC_CORE,
+};
+
+static const u32 gen7_9_0_gbif_debugbus_blocks[] = {
+ A7XX_DBGBUS_GBIF_GX,
+};
+
+static const u32 gen7_9_0_cx_debugbus_blocks[] = {
+ A7XX_DBGBUS_CX,
+ A7XX_DBGBUS_GMU_CX,
+ A7XX_DBGBUS_GBIF_CX,
+};
+
+static struct gen7_shader_block gen7_9_0_shader_blocks[] = {
+ { A7XX_TP0_TMO_DATA, 0x0200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_TP0_SMO_DATA, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_TP0_MIPMAP_BASE_DATA, 0x03C0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_INST_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_INST_DATA_1, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_LB_0_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_LB_1_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_LB_2_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_LB_3_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_LB_4_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_LB_5_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_LB_6_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_LB_7_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_CB_RAM, 0x0390, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_LB_13_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_LB_14_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_INST_TAG, 0x00C0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_INST_DATA_2, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_TMO_TAG, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_SMO_TAG, 0x0080, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_STATE_DATA, 0x0040, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_HWAVE_RAM, 0x0100, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_L0_INST_BUF, 0x0050, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_LB_8_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_LB_9_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_LB_10_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_LB_11_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_SP_LB_12_DATA, 0x0800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP },
+ { A7XX_HLSQ_DATAPATH_DSTR_META, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_DATAPATH_DSTR_META, 0x0010, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_L2STC_TAG_RAM, 0x0200, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_L2STC_INFO_CMD, 0x0474, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x0080, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x0400, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CHUNK_CVS_RAM, 0x01C0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CHUNK_CVS_RAM, 0x01C0, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CHUNK_CPS_RAM, 0x0300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CHUNK_CPS_RAM, 0x0180, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x0010, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x0010, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CVS_MISC_RAM, 0x0540, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CVS_MISC_RAM, 0x0540, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CPS_MISC_RAM, 0x0640, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CPS_MISC_RAM, 0x00B0, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CPS_MISC_RAM_1, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_INST_RAM, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_INST_RAM, 0x0800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_INST_RAM, 0x0200, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x0800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x0800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x0050, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x0050, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x0050, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x0008, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_INST_RAM_TAG, 0x0014, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_INST_RAM_TAG, 0x0010, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_INST_RAM_TAG, 0x0004, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x0020, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x03C0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x0280, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_GFX_LOCAL_MISC_RAM, 0x0050, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG, 0x0008, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_INST_RAM_1, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_STPROC_META, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_BV_BE_META, 0x0018, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_BV_BE_META, 0x0018, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_INST_RAM_2, 0x0800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_DATAPATH_META, 0x0020, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_FRONTEND_META, 0x0080, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_INDIRECT_META, 0x0010, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE },
+ { A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE },
+};
+
+/*
+ * Block : ['PRE_CRASHDUMPER', 'GBIF']
+ * pairs : 2 (Regs:5), 5 (Regs:38)
+ */
+static const u32 gen7_9_0_pre_crashdumper_gpu_registers[] = {
+ 0x00210, 0x00213, 0x00536, 0x00536, 0x03c00, 0x03c0b, 0x03c40, 0x03c42,
+ 0x03c45, 0x03c47, 0x03c49, 0x03c4a, 0x03cc0, 0x03cd1,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_pre_crashdumper_gpu_registers), 8));
+
+/*
+ * Block : ['BROADCAST', 'CP', 'GRAS', 'GXCLKCTL']
+ * Block : ['PC', 'RBBM', 'RDVM', 'UCHE']
+ * Block : ['VFD', 'VPC', 'VSC']
+ * Pipeline: A7XX_PIPE_NONE
+ * pairs : 196 (Regs:1778)
+ */
+static const u32 gen7_9_0_gpu_registers[] = {
+ 0x00000, 0x00000, 0x00002, 0x00002, 0x00011, 0x00012, 0x00016, 0x0001b,
+ 0x0001f, 0x00032, 0x00038, 0x0003c, 0x00044, 0x00044, 0x00047, 0x00047,
+ 0x00049, 0x0004a, 0x0004c, 0x0004c, 0x00056, 0x00056, 0x00073, 0x0007d,
+ 0x00090, 0x000a8, 0x000ad, 0x000ad, 0x00117, 0x00117, 0x00120, 0x00122,
+ 0x00130, 0x0013f, 0x00142, 0x0015f, 0x00162, 0x00164, 0x00166, 0x00171,
+ 0x00173, 0x00174, 0x00176, 0x0017b, 0x0017e, 0x00180, 0x00183, 0x00192,
+ 0x00195, 0x00196, 0x00199, 0x0019a, 0x0019d, 0x001a2, 0x001aa, 0x001ae,
+ 0x001b9, 0x001b9, 0x001bb, 0x001bb, 0x001be, 0x001be, 0x001c1, 0x001c2,
+ 0x001c5, 0x001c5, 0x001c7, 0x001c7, 0x001c9, 0x001c9, 0x001cb, 0x001ce,
+ 0x001d1, 0x001df, 0x001e1, 0x001e3, 0x001e5, 0x001e5, 0x001e7, 0x001e9,
+ 0x00200, 0x0020d, 0x00215, 0x00253, 0x00260, 0x00260, 0x00264, 0x00270,
+ 0x00272, 0x00274, 0x00281, 0x00281, 0x00283, 0x00283, 0x00289, 0x0028d,
+ 0x00290, 0x002a2, 0x002c0, 0x002c1, 0x00300, 0x00401, 0x00410, 0x00451,
+ 0x00460, 0x004a3, 0x004c0, 0x004d1, 0x00500, 0x00500, 0x00507, 0x0050b,
+ 0x0050f, 0x0050f, 0x00511, 0x00511, 0x00533, 0x00535, 0x00540, 0x0055b,
+ 0x00564, 0x00567, 0x00574, 0x00577, 0x00584, 0x0059b, 0x005fb, 0x005ff,
+ 0x00800, 0x00808, 0x00810, 0x00813, 0x00820, 0x00821, 0x00823, 0x00827,
+ 0x00830, 0x00834, 0x0083f, 0x00841, 0x00843, 0x00847, 0x0084f, 0x00886,
+ 0x008a0, 0x008ab, 0x008c0, 0x008c0, 0x008c4, 0x008c4, 0x008c6, 0x008c6,
+ 0x008d0, 0x008dd, 0x008e0, 0x008e6, 0x008f0, 0x008f3, 0x00900, 0x00903,
+ 0x00908, 0x00911, 0x00928, 0x0093e, 0x00942, 0x0094d, 0x00980, 0x00984,
+ 0x0098d, 0x0098f, 0x009b0, 0x009b4, 0x009c2, 0x009c9, 0x009ce, 0x009d7,
+ 0x009e0, 0x009e7, 0x00a00, 0x00a00, 0x00a02, 0x00a03, 0x00a10, 0x00a4f,
+ 0x00a61, 0x00a9f, 0x00ad0, 0x00adb, 0x00b00, 0x00b31, 0x00b35, 0x00b3c,
+ 0x00b40, 0x00b40, 0x00b70, 0x00b73, 0x00b78, 0x00b79, 0x00b7c, 0x00b7d,
+ 0x00b80, 0x00b81, 0x00b84, 0x00b85, 0x00b88, 0x00b89, 0x00b8c, 0x00b8d,
+ 0x00b90, 0x00b93, 0x00b98, 0x00b99, 0x00b9c, 0x00b9d, 0x00ba0, 0x00ba1,
+ 0x00ba4, 0x00ba5, 0x00ba8, 0x00ba9, 0x00bac, 0x00bad, 0x00bb0, 0x00bb1,
+ 0x00bb4, 0x00bb5, 0x00bb8, 0x00bb9, 0x00bbc, 0x00bbd, 0x00bc0, 0x00bc1,
+ 0x00c00, 0x00c00, 0x00c02, 0x00c04, 0x00c06, 0x00c06, 0x00c10, 0x00cd9,
+ 0x00ce0, 0x00d0c, 0x00df0, 0x00df4, 0x00e01, 0x00e02, 0x00e07, 0x00e0e,
+ 0x00e10, 0x00e13, 0x00e17, 0x00e19, 0x00e1c, 0x00e2b, 0x00e30, 0x00e32,
+ 0x00e3a, 0x00e3d, 0x00e50, 0x00e5b, 0x02840, 0x0287f, 0x0ec00, 0x0ec01,
+ 0x0ec05, 0x0ec05, 0x0ec07, 0x0ec07, 0x0ec0a, 0x0ec0a, 0x0ec12, 0x0ec12,
+ 0x0ec26, 0x0ec28, 0x0ec2b, 0x0ec2d, 0x0ec2f, 0x0ec2f, 0x0ec40, 0x0ec41,
+ 0x0ec45, 0x0ec45, 0x0ec47, 0x0ec47, 0x0ec4a, 0x0ec4a, 0x0ec52, 0x0ec52,
+ 0x0ec66, 0x0ec68, 0x0ec6b, 0x0ec6d, 0x0ec6f, 0x0ec6f, 0x0ec80, 0x0ec81,
+ 0x0ec85, 0x0ec85, 0x0ec87, 0x0ec87, 0x0ec8a, 0x0ec8a, 0x0ec92, 0x0ec92,
+ 0x0eca6, 0x0eca8, 0x0ecab, 0x0ecad, 0x0ecaf, 0x0ecaf, 0x0ecc0, 0x0ecc1,
+ 0x0ecc5, 0x0ecc5, 0x0ecc7, 0x0ecc7, 0x0ecca, 0x0ecca, 0x0ecd2, 0x0ecd2,
+ 0x0ece6, 0x0ece8, 0x0eceb, 0x0eced, 0x0ecef, 0x0ecef, 0x0ed00, 0x0ed01,
+ 0x0ed05, 0x0ed05, 0x0ed07, 0x0ed07, 0x0ed0a, 0x0ed0a, 0x0ed12, 0x0ed12,
+ 0x0ed26, 0x0ed28, 0x0ed2b, 0x0ed2d, 0x0ed2f, 0x0ed2f, 0x0ed40, 0x0ed41,
+ 0x0ed45, 0x0ed45, 0x0ed47, 0x0ed47, 0x0ed4a, 0x0ed4a, 0x0ed52, 0x0ed52,
+ 0x0ed66, 0x0ed68, 0x0ed6b, 0x0ed6d, 0x0ed6f, 0x0ed6f, 0x0ed80, 0x0ed81,
+ 0x0ed85, 0x0ed85, 0x0ed87, 0x0ed87, 0x0ed8a, 0x0ed8a, 0x0ed92, 0x0ed92,
+ 0x0eda6, 0x0eda8, 0x0edab, 0x0edad, 0x0edaf, 0x0edaf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_gpu_registers), 8));
+
+static const u32 gen7_9_0_gxclkctl_registers[] = {
+ 0x18800, 0x18800, 0x18808, 0x1880b, 0x18820, 0x18822, 0x18830, 0x18830,
+ 0x18834, 0x1883b,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_gxclkctl_registers), 8));
+
+/*
+ * Block : ['GMUAO', 'GMUCX', 'GMUCX_RAM']
+ * Pipeline: A7XX_PIPE_NONE
+ * pairs : 134 (Regs:429)
+ */
+static const u32 gen7_9_0_gmu_registers[] = {
+ 0x10001, 0x10001, 0x10003, 0x10003, 0x10401, 0x10401, 0x10403, 0x10403,
+ 0x10801, 0x10801, 0x10803, 0x10803, 0x10c01, 0x10c01, 0x10c03, 0x10c03,
+ 0x11001, 0x11001, 0x11003, 0x11003, 0x11401, 0x11401, 0x11403, 0x11403,
+ 0x11801, 0x11801, 0x11803, 0x11803, 0x11c01, 0x11c01, 0x11c03, 0x11c03,
+ 0x1f400, 0x1f40b, 0x1f40f, 0x1f411, 0x1f500, 0x1f500, 0x1f507, 0x1f507,
+ 0x1f509, 0x1f50b, 0x1f700, 0x1f701, 0x1f704, 0x1f706, 0x1f708, 0x1f709,
+ 0x1f70c, 0x1f70d, 0x1f710, 0x1f711, 0x1f713, 0x1f716, 0x1f718, 0x1f71d,
+ 0x1f720, 0x1f724, 0x1f729, 0x1f729, 0x1f730, 0x1f747, 0x1f750, 0x1f756,
+ 0x1f758, 0x1f759, 0x1f75c, 0x1f75c, 0x1f760, 0x1f761, 0x1f764, 0x1f76b,
+ 0x1f770, 0x1f775, 0x1f780, 0x1f785, 0x1f790, 0x1f798, 0x1f7a0, 0x1f7a8,
+ 0x1f7b0, 0x1f7b3, 0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c,
+ 0x1f80f, 0x1f80f, 0x1f811, 0x1f811, 0x1f813, 0x1f817, 0x1f819, 0x1f81c,
+ 0x1f824, 0x1f82a, 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f860, 0x1f860,
+ 0x1f862, 0x1f866, 0x1f868, 0x1f869, 0x1f870, 0x1f879, 0x1f87f, 0x1f881,
+ 0x1f890, 0x1f896, 0x1f8a0, 0x1f8a2, 0x1f8a4, 0x1f8af, 0x1f8b8, 0x1f8b9,
+ 0x1f8c0, 0x1f8c1, 0x1f8c3, 0x1f8c4, 0x1f8d0, 0x1f8d0, 0x1f8ec, 0x1f8ec,
+ 0x1f8f0, 0x1f8f1, 0x1f910, 0x1f917, 0x1f920, 0x1f921, 0x1f924, 0x1f925,
+ 0x1f928, 0x1f929, 0x1f92c, 0x1f92d, 0x1f942, 0x1f944, 0x1f948, 0x1f94a,
+ 0x1f94f, 0x1f951, 0x1f954, 0x1f955, 0x1f95d, 0x1f95d, 0x1f962, 0x1f96b,
+ 0x1f970, 0x1f971, 0x1f973, 0x1f977, 0x1f97c, 0x1f97c, 0x1f980, 0x1f981,
+ 0x1f984, 0x1f986, 0x1f992, 0x1f993, 0x1f996, 0x1f99e, 0x1f9c5, 0x1f9d4,
+ 0x1f9f0, 0x1f9f1, 0x1f9f8, 0x1f9fa, 0x1f9fc, 0x1f9fc, 0x1fa00, 0x1fa03,
+ 0x20000, 0x20013, 0x20018, 0x2001a, 0x20020, 0x20021, 0x20024, 0x20025,
+ 0x2002a, 0x2002c, 0x20030, 0x20031, 0x20034, 0x20036, 0x23801, 0x23801,
+ 0x23803, 0x23803, 0x23805, 0x23805, 0x23807, 0x23807, 0x23809, 0x23809,
+ 0x2380b, 0x2380b, 0x2380d, 0x2380d, 0x2380f, 0x2380f, 0x23811, 0x23811,
+ 0x23813, 0x23813, 0x23815, 0x23815, 0x23817, 0x23817, 0x23819, 0x23819,
+ 0x2381b, 0x2381b, 0x2381d, 0x2381d, 0x2381f, 0x23820, 0x23822, 0x23822,
+ 0x23824, 0x23824, 0x23826, 0x23826, 0x23828, 0x23828, 0x2382a, 0x2382a,
+ 0x2382c, 0x2382c, 0x2382e, 0x2382e, 0x23830, 0x23830, 0x23832, 0x23832,
+ 0x23834, 0x23834, 0x23836, 0x23836, 0x23838, 0x23838, 0x2383a, 0x2383a,
+ 0x2383c, 0x2383c, 0x2383e, 0x2383e, 0x23840, 0x23847, 0x23b00, 0x23b01,
+ 0x23b03, 0x23b03, 0x23b05, 0x23b0e, 0x23b10, 0x23b13, 0x23b15, 0x23b16,
+ 0x23b28, 0x23b28, 0x23b30, 0x23b30,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_gmu_registers), 8));
+
+/*
+ * Block : ['GMUGX']
+ * Pipeline: A7XX_PIPE_NONE
+ * pairs : 44 (Regs:454)
+ */
+static const u32 gen7_9_0_gmugx_registers[] = {
+ 0x1a400, 0x1a41f, 0x1a440, 0x1a45f, 0x1a480, 0x1a49f, 0x1a4c0, 0x1a4df,
+ 0x1a500, 0x1a51f, 0x1a540, 0x1a55f, 0x1a580, 0x1a59f, 0x1a600, 0x1a61f,
+ 0x1a640, 0x1a65f, 0x1a780, 0x1a781, 0x1a783, 0x1a785, 0x1a787, 0x1a789,
+ 0x1a78b, 0x1a78d, 0x1a78f, 0x1a791, 0x1a793, 0x1a795, 0x1a797, 0x1a799,
+ 0x1a79b, 0x1a79d, 0x1a79f, 0x1a7a1, 0x1a7a3, 0x1a7a3, 0x1a7a8, 0x1a7b9,
+ 0x1a7c0, 0x1a7c1, 0x1a7c4, 0x1a7c5, 0x1a7c8, 0x1a7c9, 0x1a7cc, 0x1a7cd,
+ 0x1a7d0, 0x1a7d1, 0x1a7d4, 0x1a7d5, 0x1a7d8, 0x1a7d9, 0x1a7dc, 0x1a7dd,
+ 0x1a7e0, 0x1a7e1, 0x1a7fc, 0x1a7fd, 0x1a800, 0x1a808, 0x1a816, 0x1a816,
+ 0x1a81e, 0x1a81e, 0x1a826, 0x1a826, 0x1a82e, 0x1a82e, 0x1a836, 0x1a836,
+ 0x1a83e, 0x1a83e, 0x1a846, 0x1a846, 0x1a84e, 0x1a84e, 0x1a856, 0x1a856,
+ 0x1a883, 0x1a884, 0x1a890, 0x1a8b3, 0x1a900, 0x1a92b, 0x1a940, 0x1a940,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_gmugx_registers), 8));
+
+/*
+ * Block : ['CX_MISC']
+ * Pipeline: A7XX_PIPE_NONE
+ * pairs : 7 (Regs:56)
+ */
+static const u32 gen7_9_0_cx_misc_registers[] = {
+ 0x27800, 0x27800, 0x27810, 0x27814, 0x27820, 0x27824, 0x27828, 0x2782a,
+ 0x27832, 0x27857, 0x27880, 0x27881, 0x27c00, 0x27c01,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_cx_misc_registers), 8));
+
+/*
+ * Block : ['DBGC']
+ * Pipeline: A7XX_PIPE_NONE
+ * pairs : 19 (Regs:155)
+ */
+static const u32 gen7_9_0_dbgc_registers[] = {
+ 0x00600, 0x0061c, 0x0061e, 0x00634, 0x00640, 0x00643, 0x0064e, 0x00652,
+ 0x00654, 0x0065e, 0x00699, 0x00699, 0x0069b, 0x0069e, 0x006c2, 0x006e4,
+ 0x006e6, 0x006e6, 0x006e9, 0x006e9, 0x006eb, 0x006eb, 0x006f1, 0x006f4,
+ 0x00700, 0x00707, 0x00718, 0x00718, 0x00720, 0x00729, 0x00740, 0x0074a,
+ 0x00758, 0x00758, 0x00760, 0x00762,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_dbgc_registers), 8));
+
+/*
+ * Block : ['CX_DBGC']
+ * Pipeline: A7XX_PIPE_NONE
+ * pairs : 7 (Regs:75)
+ */
+static const u32 gen7_9_0_cx_dbgc_registers[] = {
+ 0x18400, 0x1841c, 0x1841e, 0x18434, 0x18440, 0x18443, 0x1844e, 0x18452,
+ 0x18454, 0x1845e, 0x18520, 0x18520, 0x18580, 0x18581,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_cx_dbgc_registers), 8));
+
+/*
+ * Block : ['BROADCAST', 'CP', 'CX_DBGC', 'CX_MISC', 'DBGC', 'GBIF']
+ * Block : ['GMUAO', 'GMUCX', 'GMUGX', 'GRAS', 'GXCLKCTL', 'PC']
+ * Block : ['RBBM', 'RDVM', 'UCHE', 'VFD', 'VPC', 'VSC']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_NONE
+ * pairs : 29 (Regs:573)
+ */
+static const u32 gen7_9_0_non_context_pipe_br_registers[] = {
+ 0x00887, 0x0088c, 0x08600, 0x08602, 0x08610, 0x0861b, 0x08620, 0x08620,
+ 0x08630, 0x08630, 0x08637, 0x08639, 0x08640, 0x08640, 0x09600, 0x09603,
+ 0x0960a, 0x09616, 0x09624, 0x0963a, 0x09640, 0x09640, 0x09e00, 0x09e00,
+ 0x09e02, 0x09e07, 0x09e0a, 0x09e16, 0x09e18, 0x09e1a, 0x09e1c, 0x09e1c,
+ 0x09e20, 0x09e25, 0x09e30, 0x09e31, 0x09e40, 0x09e51, 0x09e64, 0x09e6c,
+ 0x09e70, 0x09e72, 0x09e78, 0x09e79, 0x09e80, 0x09fff, 0x0a600, 0x0a600,
+ 0x0a603, 0x0a603, 0x0a610, 0x0a61f, 0x0a630, 0x0a631, 0x0a638, 0x0a63c,
+ 0x0a640, 0x0a65f,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_pipe_br_registers), 8));
+
+/*
+ * Block : ['BROADCAST', 'CP', 'CX_DBGC', 'CX_MISC', 'DBGC', 'GBIF']
+ * Block : ['GMUAO', 'GMUCX', 'GMUGX', 'GRAS', 'GXCLKCTL', 'PC']
+ * Block : ['RBBM', 'RDVM', 'UCHE', 'VFD', 'VPC', 'VSC']
+ * Pipeline: A7XX_PIPE_BV
+ * Cluster : A7XX_CLUSTER_NONE
+ * pairs : 29 (Regs:573)
+ */
+static const u32 gen7_9_0_non_context_pipe_bv_registers[] = {
+ 0x00887, 0x0088c, 0x08600, 0x08602, 0x08610, 0x0861b, 0x08620, 0x08620,
+ 0x08630, 0x08630, 0x08637, 0x08639, 0x08640, 0x08640, 0x09600, 0x09603,
+ 0x0960a, 0x09616, 0x09624, 0x0963a, 0x09640, 0x09640, 0x09e00, 0x09e00,
+ 0x09e02, 0x09e07, 0x09e0a, 0x09e16, 0x09e18, 0x09e1a, 0x09e1c, 0x09e1c,
+ 0x09e20, 0x09e25, 0x09e30, 0x09e31, 0x09e40, 0x09e51, 0x09e64, 0x09e6c,
+ 0x09e70, 0x09e72, 0x09e78, 0x09e79, 0x09e80, 0x09fff, 0x0a600, 0x0a600,
+ 0x0a603, 0x0a603, 0x0a610, 0x0a61f, 0x0a630, 0x0a631, 0x0a638, 0x0a63c,
+ 0x0a640, 0x0a65f,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_pipe_bv_registers), 8));
+
+/*
+ * Block : ['BROADCAST', 'CP', 'CX_DBGC', 'CX_MISC', 'DBGC', 'GBIF']
+ * Block : ['GMUAO', 'GMUCX', 'GMUGX', 'GRAS', 'GXCLKCTL', 'PC']
+ * Block : ['RBBM', 'RDVM', 'UCHE', 'VFD', 'VPC', 'VSC']
+ * Pipeline: A7XX_PIPE_LPAC
+ * Cluster : A7XX_CLUSTER_NONE
+ * pairs : 2 (Regs:7)
+ */
+static const u32 gen7_9_0_non_context_pipe_lpac_registers[] = {
+ 0x00887, 0x0088c, 0x00f80, 0x00f80,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_pipe_lpac_registers), 8));
+
+/*
+ * Block : ['RB']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_NONE
+ * pairs : 5 (Regs:37)
+ */
+static const u32 gen7_9_0_non_context_rb_pipe_br_rac_registers[] = {
+ 0x08e10, 0x08e1c, 0x08e20, 0x08e25, 0x08e51, 0x08e5a, 0x08e6a, 0x08e6d,
+ 0x08ea0, 0x08ea3,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_rb_pipe_br_rac_registers), 8));
+
+/*
+ * Block : ['RB']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_NONE
+ * pairs : 15 (Regs:66)
+ */
+static const u32 gen7_9_0_non_context_rb_pipe_br_rbp_registers[] = {
+ 0x08e01, 0x08e01, 0x08e04, 0x08e04, 0x08e06, 0x08e09, 0x08e0c, 0x08e0c,
+ 0x08e28, 0x08e28, 0x08e2c, 0x08e35, 0x08e3b, 0x08e40, 0x08e50, 0x08e50,
+ 0x08e5b, 0x08e5d, 0x08e5f, 0x08e5f, 0x08e61, 0x08e61, 0x08e63, 0x08e66,
+ 0x08e68, 0x08e69, 0x08e70, 0x08e7d, 0x08e80, 0x08e8f,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_rb_pipe_br_rbp_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_NONE
+ * Location: A7XX_HLSQ_STATE
+ * pairs : 4 (Regs:28)
+ */
+static const u32 gen7_9_0_non_context_sp_pipe_br_hlsq_state_registers[] = {
+ 0x0ae52, 0x0ae52, 0x0ae60, 0x0ae67, 0x0ae69, 0x0ae75, 0x0aec0, 0x0aec5,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp_pipe_br_hlsq_state_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_NONE
+ * Location: A7XX_SP_TOP
+ * pairs : 10 (Regs:61)
+ */
+static const u32 gen7_9_0_non_context_sp_pipe_br_sp_top_registers[] = {
+ 0x0ae00, 0x0ae00, 0x0ae02, 0x0ae04, 0x0ae06, 0x0ae0a, 0x0ae0c, 0x0ae0c,
+ 0x0ae0f, 0x0ae0f, 0x0ae28, 0x0ae2b, 0x0ae35, 0x0ae35, 0x0ae3a, 0x0ae3f,
+ 0x0ae50, 0x0ae52, 0x0ae80, 0x0aea3,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp_pipe_br_sp_top_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_NONE
+ * Location: A7XX_USPTP
+ * pairs : 12 (Regs:62)
+ */
+static const u32 gen7_9_0_non_context_sp_pipe_br_usptp_registers[] = {
+ 0x0ae00, 0x0ae00, 0x0ae02, 0x0ae04, 0x0ae06, 0x0ae0a, 0x0ae0c, 0x0ae0c,
+ 0x0ae0f, 0x0ae0f, 0x0ae28, 0x0ae2b, 0x0ae30, 0x0ae32, 0x0ae35, 0x0ae35,
+ 0x0ae3a, 0x0ae3b, 0x0ae3e, 0x0ae3f, 0x0ae50, 0x0ae52, 0x0ae80, 0x0aea3,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp_pipe_br_usptp_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_NONE
+ * Location: A7XX_HLSQ_DP_STR
+ * pairs : 2 (Regs:5)
+ */
+static const u32 gen7_9_0_non_context_sp_pipe_br_hlsq_dp_str_registers[] = {
+ 0x0ae6b, 0x0ae6c, 0x0ae73, 0x0ae75,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp_pipe_br_hlsq_dp_str_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_LPAC
+ * Cluster : A7XX_CLUSTER_NONE
+ * Location: A7XX_HLSQ_STATE
+ * pairs : 1 (Regs:5)
+ */
+static const u32 gen7_9_0_non_context_sp_pipe_lpac_hlsq_state_registers[] = {
+ 0x0af88, 0x0af8c,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp_pipe_lpac_hlsq_state_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_LPAC
+ * Cluster : A7XX_CLUSTER_NONE
+ * Location: A7XX_SP_TOP
+ * pairs : 1 (Regs:6)
+ */
+static const u32 gen7_9_0_non_context_sp_pipe_lpac_sp_top_registers[] = {
+ 0x0af80, 0x0af85,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp_pipe_lpac_sp_top_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_LPAC
+ * Cluster : A7XX_CLUSTER_NONE
+ * Location: A7XX_USPTP
+ * pairs : 2 (Regs:9)
+ */
+static const u32 gen7_9_0_non_context_sp_pipe_lpac_usptp_registers[] = {
+ 0x0af80, 0x0af85, 0x0af90, 0x0af92,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_sp_pipe_lpac_usptp_registers), 8));
+
+/*
+ * Block : ['TPL1']
+ * Pipeline: A7XX_PIPE_NONE
+ * Cluster : A7XX_CLUSTER_NONE
+ * Location: A7XX_USPTP
+ * pairs : 5 (Regs:29)
+ */
+static const u32 gen7_9_0_non_context_tpl1_pipe_none_usptp_registers[] = {
+ 0x0b602, 0x0b602, 0x0b604, 0x0b604, 0x0b608, 0x0b60c, 0x0b610, 0x0b621,
+ 0x0b630, 0x0b633,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_tpl1_pipe_none_usptp_registers), 8));
+
+/*
+ * Block : ['TPL1']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_NONE
+ * Location: A7XX_USPTP
+ * pairs : 1 (Regs:1)
+ */
+static const u32 gen7_9_0_non_context_tpl1_pipe_br_usptp_registers[] = {
+ 0x0b600, 0x0b600,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_tpl1_pipe_br_usptp_registers), 8));
+
+/*
+ * Block : ['TPL1']
+ * Pipeline: A7XX_PIPE_LPAC
+ * Cluster : A7XX_CLUSTER_NONE
+ * Location: A7XX_USPTP
+ * pairs : 1 (Regs:1)
+ */
+static const u32 gen7_9_0_non_context_tpl1_pipe_lpac_usptp_registers[] = {
+ 0x0b780, 0x0b780,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_non_context_tpl1_pipe_lpac_usptp_registers), 8));
+
+/*
+ * Block : ['GRAS']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_GRAS
+ * pairs : 14 (Regs:293)
+ */
+static const u32 gen7_9_0_gras_pipe_br_cluster_gras_registers[] = {
+ 0x08000, 0x0800c, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d,
+ 0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa,
+ 0x08100, 0x08107, 0x08109, 0x0810b, 0x08110, 0x08116, 0x08120, 0x0813f,
+ 0x08400, 0x08406, 0x0840a, 0x0840b,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_gras_pipe_br_cluster_gras_registers), 8));
+
+/*
+ * Block : ['GRAS']
+ * Pipeline: A7XX_PIPE_BV
+ * Cluster : A7XX_CLUSTER_GRAS
+ * pairs : 14 (Regs:293)
+ */
+static const u32 gen7_9_0_gras_pipe_bv_cluster_gras_registers[] = {
+ 0x08000, 0x0800c, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d,
+ 0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa,
+ 0x08100, 0x08107, 0x08109, 0x0810b, 0x08110, 0x08116, 0x08120, 0x0813f,
+ 0x08400, 0x08406, 0x0840a, 0x0840b,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_gras_pipe_bv_cluster_gras_registers), 8));
+
+/*
+ * Block : ['PC']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_FE
+ * pairs : 6 (Regs:31)
+ */
+static const u32 gen7_9_0_pc_pipe_br_cluster_fe_registers[] = {
+ 0x09800, 0x09804, 0x09806, 0x0980a, 0x09810, 0x09811, 0x09884, 0x09886,
+ 0x09970, 0x09972, 0x09b00, 0x09b0c,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_pc_pipe_br_cluster_fe_registers), 8));
+
+/*
+ * Block : ['PC']
+ * Pipeline: A7XX_PIPE_BV
+ * Cluster : A7XX_CLUSTER_FE
+ * pairs : 6 (Regs:31)
+ */
+static const u32 gen7_9_0_pc_pipe_bv_cluster_fe_registers[] = {
+ 0x09800, 0x09804, 0x09806, 0x0980a, 0x09810, 0x09811, 0x09884, 0x09886,
+ 0x09970, 0x09972, 0x09b00, 0x09b0c,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_pc_pipe_bv_cluster_fe_registers), 8));
+
+/*
+ * Block : ['VFD']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_FE
+ * pairs : 2 (Regs:236)
+ */
+static const u32 gen7_9_0_vfd_pipe_br_cluster_fe_registers[] = {
+ 0x0a000, 0x0a009, 0x0a00e, 0x0a0ef,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_vfd_pipe_br_cluster_fe_registers), 8));
+
+/*
+ * Block : ['VFD']
+ * Pipeline: A7XX_PIPE_BV
+ * Cluster : A7XX_CLUSTER_FE
+ * pairs : 2 (Regs:236)
+ */
+static const u32 gen7_9_0_vfd_pipe_bv_cluster_fe_registers[] = {
+ 0x0a000, 0x0a009, 0x0a00e, 0x0a0ef,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_vfd_pipe_bv_cluster_fe_registers), 8));
+
+/*
+ * Block : ['VPC']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_FE
+ * pairs : 2 (Regs:18)
+ */
+static const u32 gen7_9_0_vpc_pipe_br_cluster_fe_registers[] = {
+ 0x09300, 0x0930a, 0x09311, 0x09317,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_br_cluster_fe_registers), 8));
+
+/*
+ * Block : ['VPC']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_PC_VS
+ * pairs : 3 (Regs:30)
+ */
+static const u32 gen7_9_0_vpc_pipe_br_cluster_pc_vs_registers[] = {
+ 0x09101, 0x0910c, 0x09300, 0x0930a, 0x09311, 0x09317,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_br_cluster_pc_vs_registers), 8));
+
+/*
+ * Block : ['VPC']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_VPC_PS
+ * pairs : 5 (Regs:76)
+ */
+static const u32 gen7_9_0_vpc_pipe_br_cluster_vpc_ps_registers[] = {
+ 0x09200, 0x0920f, 0x09212, 0x09216, 0x09218, 0x0923c, 0x09300, 0x0930a,
+ 0x09311, 0x09317,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_br_cluster_vpc_ps_registers), 8));
+
+/*
+ * Block : ['VPC']
+ * Pipeline: A7XX_PIPE_BV
+ * Cluster : A7XX_CLUSTER_FE
+ * pairs : 2 (Regs:18)
+ */
+static const u32 gen7_9_0_vpc_pipe_bv_cluster_fe_registers[] = {
+ 0x09300, 0x0930a, 0x09311, 0x09317,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_bv_cluster_fe_registers), 8));
+
+/*
+ * Block : ['VPC']
+ * Pipeline: A7XX_PIPE_BV
+ * Cluster : A7XX_CLUSTER_PC_VS
+ * pairs : 3 (Regs:30)
+ */
+static const u32 gen7_9_0_vpc_pipe_bv_cluster_pc_vs_registers[] = {
+ 0x09101, 0x0910c, 0x09300, 0x0930a, 0x09311, 0x09317,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_bv_cluster_pc_vs_registers), 8));
+
+/*
+ * Block : ['VPC']
+ * Pipeline: A7XX_PIPE_BV
+ * Cluster : A7XX_CLUSTER_VPC_PS
+ * pairs : 5 (Regs:76)
+ */
+static const u32 gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers[] = {
+ 0x09200, 0x0920f, 0x09212, 0x09216, 0x09218, 0x0923c, 0x09300, 0x0930a,
+ 0x09311, 0x09317,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers), 8));
+
+/*
+ * Block : ['RB']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_PS
+ * pairs : 39 (Regs:133)
+ */
+static const u32 gen7_9_0_rb_pipe_br_cluster_ps_rac_registers[] = {
+ 0x08802, 0x08802, 0x08804, 0x08806, 0x08809, 0x0880a, 0x0880e, 0x08811,
+ 0x08818, 0x0881e, 0x08821, 0x08821, 0x08823, 0x08826, 0x08829, 0x08829,
+ 0x0882b, 0x0882e, 0x08831, 0x08831, 0x08833, 0x08836, 0x08839, 0x08839,
+ 0x0883b, 0x0883e, 0x08841, 0x08841, 0x08843, 0x08846, 0x08849, 0x08849,
+ 0x0884b, 0x0884e, 0x08851, 0x08851, 0x08853, 0x08856, 0x08859, 0x08859,
+ 0x0885b, 0x0885e, 0x08860, 0x08864, 0x08870, 0x08870, 0x08873, 0x08876,
+ 0x08878, 0x08879, 0x08882, 0x08885, 0x08887, 0x08889, 0x08891, 0x08891,
+ 0x08898, 0x08899, 0x088c0, 0x088c1, 0x088e5, 0x088e5, 0x088f4, 0x088f5,
+ 0x08a00, 0x08a05, 0x08a10, 0x08a15, 0x08a20, 0x08a25, 0x08a30, 0x08a35,
+ 0x08c00, 0x08c01, 0x08c18, 0x08c1f, 0x08c26, 0x08c34,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_rb_pipe_br_cluster_ps_rac_registers), 8));
+
+/*
+ * Block : ['RB']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_PS
+ * pairs : 34 (Regs:100)
+ */
+static const u32 gen7_9_0_rb_pipe_br_cluster_ps_rbp_registers[] = {
+ 0x08800, 0x08801, 0x08803, 0x08803, 0x0880b, 0x0880d, 0x08812, 0x08812,
+ 0x08820, 0x08820, 0x08822, 0x08822, 0x08827, 0x08828, 0x0882a, 0x0882a,
+ 0x0882f, 0x08830, 0x08832, 0x08832, 0x08837, 0x08838, 0x0883a, 0x0883a,
+ 0x0883f, 0x08840, 0x08842, 0x08842, 0x08847, 0x08848, 0x0884a, 0x0884a,
+ 0x0884f, 0x08850, 0x08852, 0x08852, 0x08857, 0x08858, 0x0885a, 0x0885a,
+ 0x0885f, 0x0885f, 0x08865, 0x08865, 0x08871, 0x08872, 0x08877, 0x08877,
+ 0x08880, 0x08881, 0x08886, 0x08886, 0x08890, 0x08890, 0x088d0, 0x088e4,
+ 0x088e8, 0x088ea, 0x088f0, 0x088f0, 0x08900, 0x0891a, 0x08927, 0x08928,
+ 0x08c17, 0x08c17, 0x08c20, 0x08c25,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_rb_pipe_br_cluster_ps_rbp_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_SP_VS
+ * Location: A7XX_HLSQ_STATE
+ * pairs : 29 (Regs:215)
+ */
+static const u32 gen7_9_0_sp_pipe_br_cluster_sp_vs_hlsq_state_registers[] = {
+ 0x0a800, 0x0a801, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824,
+ 0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a832, 0x0a835, 0x0a83a, 0x0a83a,
+ 0x0a83c, 0x0a83c, 0x0a83f, 0x0a841, 0x0a85b, 0x0a85d, 0x0a862, 0x0a862,
+ 0x0a864, 0x0a864, 0x0a867, 0x0a867, 0x0a870, 0x0a870, 0x0a872, 0x0a872,
+ 0x0a88c, 0x0a88e, 0x0a893, 0x0a893, 0x0a895, 0x0a895, 0x0a898, 0x0a898,
+ 0x0a89a, 0x0a89d, 0x0a8a0, 0x0a8af, 0x0a8c0, 0x0a8c3, 0x0a974, 0x0a977,
+ 0x0ab00, 0x0ab03, 0x0ab05, 0x0ab05, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20,
+ 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_cluster_sp_vs_hlsq_state_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_SP_VS
+ * Location: A7XX_SP_TOP
+ * pairs : 22 (Regs:73)
+ */
+static const u32 gen7_9_0_sp_pipe_br_cluster_sp_vs_sp_top_registers[] = {
+ 0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a82d, 0x0a82d,
+ 0x0a82f, 0x0a831, 0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840,
+ 0x0a85c, 0x0a85d, 0x0a862, 0x0a864, 0x0a868, 0x0a868, 0x0a870, 0x0a871,
+ 0x0a88d, 0x0a88e, 0x0a893, 0x0a895, 0x0a899, 0x0a899, 0x0a8a0, 0x0a8af,
+ 0x0a974, 0x0a977, 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab04, 0x0ab05,
+ 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_cluster_sp_vs_sp_top_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_SP_VS
+ * Location: A7XX_USPTP
+ * pairs : 16 (Regs:269)
+ */
+static const u32 gen7_9_0_sp_pipe_br_cluster_sp_vs_usptp_registers[] = {
+ 0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a82d, 0x0a82d,
+ 0x0a82f, 0x0a833, 0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861,
+ 0x0a863, 0x0a868, 0x0a870, 0x0a88c, 0x0a88f, 0x0a892, 0x0a894, 0x0a899,
+ 0x0a8c0, 0x0a8c3, 0x0ab00, 0x0ab05, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_cluster_sp_vs_usptp_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_SP_PS
+ * Location: A7XX_HLSQ_STATE
+ * pairs : 21 (Regs:334)
+ */
+static const u32 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_state_registers[] = {
+ 0x0a980, 0x0a984, 0x0a99e, 0x0a99e, 0x0a9a7, 0x0a9a7, 0x0a9aa, 0x0a9aa,
+ 0x0a9ae, 0x0a9b0, 0x0a9b2, 0x0a9b5, 0x0a9ba, 0x0a9ba, 0x0a9bc, 0x0a9bc,
+ 0x0a9c4, 0x0a9c4, 0x0a9c6, 0x0a9c6, 0x0a9cd, 0x0a9cd, 0x0a9e0, 0x0a9fc,
+ 0x0aa00, 0x0aa00, 0x0aa30, 0x0aa31, 0x0aa40, 0x0aabf, 0x0aaf2, 0x0aaf3,
+ 0x0ab00, 0x0ab03, 0x0ab05, 0x0ab05, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20,
+ 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_state_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_SP_PS
+ * Location: A7XX_HLSQ_DP
+ * pairs : 3 (Regs:19)
+ */
+static const u32 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers[] = {
+ 0x0a9b1, 0x0a9b1, 0x0a9c6, 0x0a9cb, 0x0a9d4, 0x0a9df,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_SP_PS
+ * Location: A7XX_SP_TOP
+ * pairs : 18 (Regs:77)
+ */
+static const u32 gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers[] = {
+ 0x0a980, 0x0a980, 0x0a982, 0x0a984, 0x0a99e, 0x0a9a2, 0x0a9a7, 0x0a9a8,
+ 0x0a9aa, 0x0a9aa, 0x0a9ae, 0x0a9ae, 0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5,
+ 0x0a9ba, 0x0a9bc, 0x0a9c5, 0x0a9c5, 0x0a9e0, 0x0a9f9, 0x0aa00, 0x0aa03,
+ 0x0aaf2, 0x0aaf3, 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab04, 0x0ab05,
+ 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_SP_PS
+ * Location: A7XX_USPTP
+ * pairs : 17 (Regs:333)
+ */
+static const u32 gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers[] = {
+ 0x0a980, 0x0a982, 0x0a985, 0x0a9a6, 0x0a9a8, 0x0a9a9, 0x0a9ab, 0x0a9ae,
+ 0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9bf, 0x0a9c2, 0x0a9c3,
+ 0x0a9c5, 0x0a9c5, 0x0a9cd, 0x0a9cd, 0x0a9d0, 0x0a9d3, 0x0aa01, 0x0aa03,
+ 0x0aa30, 0x0aa31, 0x0aa40, 0x0aabf, 0x0ab00, 0x0ab05, 0x0ab21, 0x0ab22,
+ 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_SP_PS
+ * Location: A7XX_HLSQ_DP_STR
+ * pairs : 1 (Regs:6)
+ */
+static const u32 gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers[] = {
+ 0x0a9c6, 0x0a9cb,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_BV
+ * Cluster : A7XX_CLUSTER_SP_VS
+ * Location: A7XX_HLSQ_STATE
+ * pairs : 28 (Regs:213)
+ */
+static const u32 gen7_9_0_sp_pipe_bv_cluster_sp_vs_hlsq_state_registers[] = {
+ 0x0a800, 0x0a801, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824,
+ 0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a832, 0x0a835, 0x0a83a, 0x0a83a,
+ 0x0a83c, 0x0a83c, 0x0a83f, 0x0a841, 0x0a85b, 0x0a85d, 0x0a862, 0x0a862,
+ 0x0a864, 0x0a864, 0x0a867, 0x0a867, 0x0a870, 0x0a870, 0x0a872, 0x0a872,
+ 0x0a88c, 0x0a88e, 0x0a893, 0x0a893, 0x0a895, 0x0a895, 0x0a898, 0x0a898,
+ 0x0a89a, 0x0a89d, 0x0a8a0, 0x0a8af, 0x0a8c0, 0x0a8c3, 0x0a974, 0x0a977,
+ 0x0ab00, 0x0ab02, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_bv_cluster_sp_vs_hlsq_state_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_BV
+ * Cluster : A7XX_CLUSTER_SP_VS
+ * Location: A7XX_SP_TOP
+ * pairs : 21 (Regs:71)
+ */
+static const u32 gen7_9_0_sp_pipe_bv_cluster_sp_vs_sp_top_registers[] = {
+ 0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a82d, 0x0a82d,
+ 0x0a82f, 0x0a831, 0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840,
+ 0x0a85c, 0x0a85d, 0x0a862, 0x0a864, 0x0a868, 0x0a868, 0x0a870, 0x0a871,
+ 0x0a88d, 0x0a88e, 0x0a893, 0x0a895, 0x0a899, 0x0a899, 0x0a8a0, 0x0a8af,
+ 0x0a974, 0x0a977, 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab0a, 0x0ab1b,
+ 0x0ab20, 0x0ab20,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_bv_cluster_sp_vs_sp_top_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_BV
+ * Cluster : A7XX_CLUSTER_SP_VS
+ * Location: A7XX_USPTP
+ * pairs : 16 (Regs:266)
+ */
+static const u32 gen7_9_0_sp_pipe_bv_cluster_sp_vs_usptp_registers[] = {
+ 0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a82d, 0x0a82d,
+ 0x0a82f, 0x0a833, 0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861,
+ 0x0a863, 0x0a868, 0x0a870, 0x0a88c, 0x0a88f, 0x0a892, 0x0a894, 0x0a899,
+ 0x0a8c0, 0x0a8c3, 0x0ab00, 0x0ab02, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_bv_cluster_sp_vs_usptp_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_LPAC
+ * Cluster : A7XX_CLUSTER_SP_PS
+ * Location: A7XX_HLSQ_STATE
+ * pairs : 14 (Regs:299)
+ */
+static const u32 gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_state_registers[] = {
+ 0x0a9b0, 0x0a9b0, 0x0a9b2, 0x0a9b5, 0x0a9ba, 0x0a9ba, 0x0a9bc, 0x0a9bc,
+ 0x0a9c4, 0x0a9c4, 0x0a9cd, 0x0a9cd, 0x0a9e2, 0x0a9e3, 0x0a9e6, 0x0a9fc,
+ 0x0aa00, 0x0aa00, 0x0aa31, 0x0aa35, 0x0aa40, 0x0aabf, 0x0aaf3, 0x0aaf3,
+ 0x0ab00, 0x0ab01, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_state_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_LPAC
+ * Cluster : A7XX_CLUSTER_SP_PS
+ * Location: A7XX_HLSQ_DP
+ * pairs : 2 (Regs:13)
+ */
+static const u32 gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_dp_registers[] = {
+ 0x0a9b1, 0x0a9b1, 0x0a9d4, 0x0a9df,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_dp_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_LPAC
+ * Cluster : A7XX_CLUSTER_SP_PS
+ * Location: A7XX_SP_TOP
+ * pairs : 9 (Regs:34)
+ */
+static const u32 gen7_9_0_sp_pipe_lpac_cluster_sp_ps_sp_top_registers[] = {
+ 0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9bc, 0x0a9c5, 0x0a9c5,
+ 0x0a9e2, 0x0a9e3, 0x0a9e6, 0x0a9f9, 0x0aa00, 0x0aa00, 0x0aaf3, 0x0aaf3,
+ 0x0ab00, 0x0ab00,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_lpac_cluster_sp_ps_sp_top_registers), 8));
+
+/*
+ * Block : ['SP']
+ * Pipeline: A7XX_PIPE_LPAC
+ * Cluster : A7XX_CLUSTER_SP_PS
+ * Location: A7XX_USPTP
+ * pairs : 11 (Regs:279)
+ */
+static const u32 gen7_9_0_sp_pipe_lpac_cluster_sp_ps_usptp_registers[] = {
+ 0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9be, 0x0a9c2, 0x0a9c3,
+ 0x0a9c5, 0x0a9c5, 0x0a9cd, 0x0a9cd, 0x0a9d0, 0x0a9d3, 0x0aa31, 0x0aa31,
+ 0x0aa40, 0x0aabf, 0x0ab00, 0x0ab01, 0x0ab40, 0x0abbf,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_sp_pipe_lpac_cluster_sp_ps_usptp_registers), 8));
+
+/*
+ * Block : ['TPL1']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_SP_VS
+ * Location: A7XX_USPTP
+ * pairs : 3 (Regs:10)
+ */
+static const u32 gen7_9_0_tpl1_pipe_br_cluster_sp_vs_usptp_registers[] = {
+ 0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_br_cluster_sp_vs_usptp_registers), 8));
+
+/*
+ * Block : ['TPL1']
+ * Pipeline: A7XX_PIPE_BR
+ * Cluster : A7XX_CLUSTER_SP_PS
+ * Location: A7XX_USPTP
+ * pairs : 6 (Regs:42)
+ */
+static const u32 gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers[] = {
+ 0x0b180, 0x0b183, 0x0b190, 0x0b195, 0x0b2c0, 0x0b2d5, 0x0b300, 0x0b307,
+ 0x0b309, 0x0b309, 0x0b310, 0x0b310,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers), 8));
+
+/*
+ * Block : ['TPL1']
+ * Pipeline: A7XX_PIPE_BV
+ * Cluster : A7XX_CLUSTER_SP_VS
+ * Location: A7XX_USPTP
+ * pairs : 3 (Regs:10)
+ */
+static const u32 gen7_9_0_tpl1_pipe_bv_cluster_sp_vs_usptp_registers[] = {
+ 0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_bv_cluster_sp_vs_usptp_registers), 8));
+
+/*
+ * Block : ['TPL1']
+ * Pipeline: A7XX_PIPE_LPAC
+ * Cluster : A7XX_CLUSTER_SP_PS
+ * Location: A7XX_USPTP
+ * pairs : 5 (Regs:7)
+ */
+static const u32 gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers[] = {
+ 0x0b180, 0x0b181, 0x0b300, 0x0b301, 0x0b307, 0x0b307, 0x0b309, 0x0b309,
+ 0x0b310, 0x0b310,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers), 8));
+
+static const struct gen7_sel_reg gen7_9_0_rb_rac_sel = {
+ .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
+ .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
+ .val = 0,
+};
+
+static const struct gen7_sel_reg gen7_9_0_rb_rbp_sel = {
+ .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
+ .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
+ .val = 0x9,
+};
+
+static struct gen7_cluster_registers gen7_9_0_clusters[] = {
+ { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
+ gen7_9_0_non_context_pipe_br_registers, },
+ { A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT,
+ gen7_9_0_non_context_pipe_bv_registers, },
+ { A7XX_CLUSTER_NONE, A7XX_PIPE_LPAC, STATE_NON_CONTEXT,
+ gen7_9_0_non_context_pipe_lpac_registers, },
+ { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
+ gen7_9_0_non_context_rb_pipe_br_rac_registers, &gen7_9_0_rb_rac_sel, },
+ { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
+ gen7_9_0_non_context_rb_pipe_br_rbp_registers, &gen7_9_0_rb_rbp_sel, },
+ { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_9_0_rb_pipe_br_cluster_ps_rac_registers, &gen7_9_0_rb_rac_sel, },
+ { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_9_0_rb_pipe_br_cluster_ps_rac_registers, &gen7_9_0_rb_rac_sel, },
+ { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_9_0_rb_pipe_br_cluster_ps_rbp_registers, &gen7_9_0_rb_rbp_sel, },
+ { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_9_0_rb_pipe_br_cluster_ps_rbp_registers, &gen7_9_0_rb_rbp_sel, },
+ { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_9_0_gras_pipe_br_cluster_gras_registers, },
+ { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_9_0_gras_pipe_br_cluster_gras_registers, },
+ { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_9_0_gras_pipe_bv_cluster_gras_registers, },
+ { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_9_0_gras_pipe_bv_cluster_gras_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_9_0_pc_pipe_br_cluster_fe_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_9_0_pc_pipe_br_cluster_fe_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_9_0_pc_pipe_bv_cluster_fe_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_9_0_pc_pipe_bv_cluster_fe_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_9_0_vfd_pipe_br_cluster_fe_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_9_0_vfd_pipe_br_cluster_fe_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_9_0_vfd_pipe_bv_cluster_fe_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_9_0_vfd_pipe_bv_cluster_fe_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_9_0_vpc_pipe_br_cluster_fe_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_9_0_vpc_pipe_br_cluster_fe_registers, },
+ { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_9_0_vpc_pipe_br_cluster_pc_vs_registers, },
+ { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_9_0_vpc_pipe_br_cluster_pc_vs_registers, },
+ { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
+ gen7_9_0_vpc_pipe_br_cluster_vpc_ps_registers, },
+ { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
+ gen7_9_0_vpc_pipe_br_cluster_vpc_ps_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_9_0_vpc_pipe_bv_cluster_fe_registers, },
+ { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_9_0_vpc_pipe_bv_cluster_fe_registers, },
+ { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_9_0_vpc_pipe_bv_cluster_pc_vs_registers, },
+ { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_9_0_vpc_pipe_bv_cluster_pc_vs_registers, },
+ { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
+ gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers, },
+ { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
+ gen7_9_0_vpc_pipe_bv_cluster_vpc_ps_registers, },
+};
+
+static struct gen7_sptp_cluster_registers gen7_9_0_sptp_clusters[] = {
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
+ gen7_9_0_non_context_sp_pipe_br_hlsq_state_registers, 0xae00},
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
+ gen7_9_0_non_context_sp_pipe_br_sp_top_registers, 0xae00},
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_9_0_non_context_sp_pipe_br_usptp_registers, 0xae00},
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP_STR,
+ gen7_9_0_non_context_sp_pipe_br_hlsq_dp_str_registers, 0xae00},
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE,
+ gen7_9_0_non_context_sp_pipe_lpac_hlsq_state_registers, 0xaf80},
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP,
+ gen7_9_0_non_context_sp_pipe_lpac_sp_top_registers, 0xaf80},
+ { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
+ gen7_9_0_non_context_sp_pipe_lpac_usptp_registers, 0xaf80},
+ { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_NONE, 0, A7XX_USPTP,
+ gen7_9_0_non_context_tpl1_pipe_none_usptp_registers, 0xb600},
+ { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_9_0_non_context_tpl1_pipe_br_usptp_registers, 0xb600},
+ { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
+ gen7_9_0_non_context_tpl1_pipe_lpac_usptp_registers, 0xb780},
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
+ gen7_9_0_sp_pipe_br_cluster_sp_vs_hlsq_state_registers, 0xa800},
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
+ gen7_9_0_sp_pipe_br_cluster_sp_vs_sp_top_registers, 0xa800},
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_9_0_sp_pipe_br_cluster_sp_vs_usptp_registers, 0xa800},
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_HLSQ_STATE,
+ gen7_9_0_sp_pipe_bv_cluster_sp_vs_hlsq_state_registers, 0xa800},
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_SP_TOP,
+ gen7_9_0_sp_pipe_bv_cluster_sp_vs_sp_top_registers, 0xa800},
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP,
+ gen7_9_0_sp_pipe_bv_cluster_sp_vs_usptp_registers, 0xa800},
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE,
+ gen7_9_0_sp_pipe_br_cluster_sp_vs_hlsq_state_registers, 0xa800},
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP,
+ gen7_9_0_sp_pipe_br_cluster_sp_vs_sp_top_registers, 0xa800},
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
+ gen7_9_0_sp_pipe_br_cluster_sp_vs_usptp_registers, 0xa800},
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_HLSQ_STATE,
+ gen7_9_0_sp_pipe_bv_cluster_sp_vs_hlsq_state_registers, 0xa800},
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_SP_TOP,
+ gen7_9_0_sp_pipe_bv_cluster_sp_vs_sp_top_registers, 0xa800},
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP,
+ gen7_9_0_sp_pipe_bv_cluster_sp_vs_usptp_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_state_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP_STR,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE,
+ gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_state_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_DP,
+ gen7_9_0_sp_pipe_lpac_cluster_sp_ps_hlsq_dp_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP,
+ gen7_9_0_sp_pipe_lpac_cluster_sp_ps_sp_top_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
+ gen7_9_0_sp_pipe_lpac_cluster_sp_ps_usptp_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_state_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_DP,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_DP_STR,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_DP,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_SP_TOP,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_DP_STR,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_DP,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_SP_TOP,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_sp_top_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_usptp_registers, 0xa800},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_DP_STR,
+ gen7_9_0_sp_pipe_br_cluster_sp_ps_hlsq_dp_str_registers, 0xa800},
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_9_0_tpl1_pipe_br_cluster_sp_vs_usptp_registers, 0xb000},
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP,
+ gen7_9_0_tpl1_pipe_bv_cluster_sp_vs_usptp_registers, 0xb000},
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
+ gen7_9_0_tpl1_pipe_br_cluster_sp_vs_usptp_registers, 0xb000},
+ { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP,
+ gen7_9_0_tpl1_pipe_bv_cluster_sp_vs_usptp_registers, 0xb000},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
+ gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
+ gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers, 0xb000},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
+ gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP,
+ gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000},
+ { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP,
+ gen7_9_0_tpl1_pipe_br_cluster_sp_ps_usptp_registers, 0xb000},
+};
+
+static struct a6xx_indexed_registers gen7_9_0_cp_indexed_reg_list[] = {
+ { "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR,
+ REG_A6XX_CP_SQE_STAT_DATA, 0x00040},
+ { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR,
+ REG_A6XX_CP_DRAW_STATE_DATA, 0x00200},
+ { "CP_ROQ", REG_A6XX_CP_ROQ_DBG_ADDR,
+ REG_A6XX_CP_ROQ_DBG_DATA, 0x00800},
+ { "CP_UCODE_DBG_DATA", REG_A6XX_CP_SQE_UCODE_DBG_ADDR,
+ REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x08000},
+ { "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_DRAW_STATE_ADDR,
+ REG_A7XX_CP_BV_DRAW_STATE_DATA, 0x00200},
+ { "CP_BV_ROQ_DBG_ADDR", REG_A7XX_CP_BV_ROQ_DBG_ADDR,
+ REG_A7XX_CP_BV_ROQ_DBG_DATA, 0x00800},
+ { "CP_BV_SQE_UCODE_DBG_ADDR", REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR,
+ REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA, 0x08000},
+ { "CP_BV_SQE_STAT_ADDR", REG_A7XX_CP_BV_SQE_STAT_ADDR,
+ REG_A7XX_CP_BV_SQE_STAT_DATA, 0x00040},
+ { "CP_RESOURCE_TBL", REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR,
+ REG_A7XX_CP_RESOURCE_TBL_DBG_DATA, 0x04100},
+ { "CP_LPAC_DRAW_STATE_ADDR", REG_A7XX_CP_LPAC_DRAW_STATE_ADDR,
+ REG_A7XX_CP_LPAC_DRAW_STATE_DATA, 0x00200},
+ { "CP_LPAC_ROQ", REG_A7XX_CP_LPAC_ROQ_DBG_ADDR,
+ REG_A7XX_CP_LPAC_ROQ_DBG_DATA, 0x00200},
+ { "CP_SQE_AC_UCODE_DBG_ADDR", REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR,
+ REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA, 0x08000},
+ { "CP_SQE_AC_STAT_ADDR", REG_A7XX_CP_SQE_AC_STAT_ADDR,
+ REG_A7XX_CP_SQE_AC_STAT_DATA, 0x00040},
+ { "CP_LPAC_FIFO_DBG_ADDR", REG_A7XX_CP_LPAC_FIFO_DBG_ADDR,
+ REG_A7XX_CP_LPAC_FIFO_DBG_DATA, 0x00040},
+ { "CP_AQE_ROQ_0", REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0,
+ REG_A7XX_CP_AQE_ROQ_DBG_DATA_0, 0x00100},
+ { "CP_AQE_ROQ_1", REG_A7XX_CP_AQE_ROQ_DBG_ADDR_1,
+ REG_A7XX_CP_AQE_ROQ_DBG_DATA_1, 0x00100},
+ { "CP_AQE_UCODE_DBG_0", REG_A7XX_CP_AQE_UCODE_DBG_ADDR_0,
+ REG_A7XX_CP_AQE_UCODE_DBG_DATA_0, 0x08000},
+ { "CP_AQE_UCODE_DBG_1", REG_A7XX_CP_AQE_UCODE_DBG_ADDR_1,
+ REG_A7XX_CP_AQE_UCODE_DBG_DATA_1, 0x08000},
+ { "CP_AQE_STAT_0", REG_A7XX_CP_AQE_STAT_ADDR_0,
+ REG_A7XX_CP_AQE_STAT_DATA_0, 0x00040},
+ { "CP_AQE_STAT_1", REG_A7XX_CP_AQE_STAT_ADDR_1,
+ REG_A7XX_CP_AQE_STAT_DATA_1, 0x00040},
+};
+
+static struct gen7_reg_list gen7_9_0_reg_list[] = {
+ { gen7_9_0_gpu_registers, NULL},
+ { gen7_9_0_cx_misc_registers, NULL},
+ { gen7_9_0_cx_dbgc_registers, NULL},
+ { gen7_9_0_dbgc_registers, NULL},
+ { NULL, NULL},
+};
+
+static const u32 gen7_9_0_cpr_registers[] = {
+ 0x26800, 0x26805, 0x26808, 0x2680d, 0x26814, 0x26815, 0x2681c, 0x2681c,
+ 0x26820, 0x26839, 0x26840, 0x26841, 0x26848, 0x26849, 0x26850, 0x26851,
+ 0x26880, 0x268a1, 0x26980, 0x269b0, 0x269c0, 0x269c8, 0x269e0, 0x269ee,
+ 0x269fb, 0x269ff, 0x26a02, 0x26a07, 0x26a09, 0x26a0b, 0x26a10, 0x26b0f,
+ 0x27440, 0x27441, 0x27444, 0x27444, 0x27480, 0x274a2, 0x274ac, 0x274c4,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_cpr_registers), 8));
+
+static const u32 gen7_9_0_dpm_registers[] = {
+ 0x1aa00, 0x1aa06, 0x1aa09, 0x1aa0a, 0x1aa0c, 0x1aa0d, 0x1aa0f, 0x1aa12,
+ 0x1aa14, 0x1aa47, 0x1aa50, 0x1aa51,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_dpm_registers), 8));
+
+static const u32 gen7_9_0_dpm_leakage_registers[] = {
+ 0x21c00, 0x21c00, 0x21c08, 0x21c09, 0x21c0e, 0x21c0f, 0x21c4f, 0x21c50,
+ 0x21c52, 0x21c52, 0x21c54, 0x21c56, 0x21c58, 0x21c5a, 0x21c5c, 0x21c60,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_dpm_leakage_registers), 8));
+
+static const u32 gen7_9_0_gfx_gpu_acd_registers[] = {
+ 0x18c00, 0x18c16, 0x18c20, 0x18c2d, 0x18c30, 0x18c31, 0x18c35, 0x18c35,
+ 0x18c37, 0x18c37, 0x18c3a, 0x18c3a, 0x18c42, 0x18c42, 0x18c56, 0x18c58,
+ 0x18c5b, 0x18c5d, 0x18c5f, 0x18c62,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_gfx_gpu_acd_registers), 8));
+
+static const u32 gen7_9_0_gpucc_registers[] = {
+ 0x24000, 0x2400f, 0x24400, 0x2440f, 0x24800, 0x24805, 0x24c00, 0x24cff,
+ 0x25400, 0x25404, 0x25800, 0x25804, 0x25c00, 0x25c04, 0x26000, 0x26004,
+ 0x26400, 0x26405, 0x26414, 0x2641d, 0x2642a, 0x26430, 0x26432, 0x26434,
+ 0x26441, 0x2644b, 0x2644d, 0x26463, 0x26466, 0x26468, 0x26478, 0x2647a,
+ 0x26489, 0x2648a, 0x2649c, 0x2649e, 0x264a0, 0x264a6, 0x264c5, 0x264c7,
+ 0x264d6, 0x264d8, 0x264e8, 0x264e9, 0x264f9, 0x264fc, 0x2650b, 0x2650b,
+ 0x2651c, 0x2651e, 0x26540, 0x2654e, 0x26554, 0x26573, 0x26576, 0x2657a,
+ UINT_MAX, UINT_MAX,
+
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_gpucc_registers), 8));
+
+static const u32 gen7_9_0_isense_registers[] = {
+ 0x22c3a, 0x22c3c, 0x22c41, 0x22c41, 0x22c46, 0x22c47, 0x22c4c, 0x22c4c,
+ 0x22c51, 0x22c51, 0x22c56, 0x22c56, 0x22c5b, 0x22c5b, 0x22c60, 0x22c60,
+ 0x22c65, 0x22c65, 0x22c6a, 0x22c70, 0x22c75, 0x22c75, 0x22c7a, 0x22c7a,
+ 0x22c7f, 0x22c7f, 0x22c84, 0x22c85, 0x22c8a, 0x22c8a, 0x22c8f, 0x22c8f,
+ 0x23000, 0x23009, 0x2300e, 0x2300e, 0x23013, 0x23013, 0x23018, 0x23018,
+ 0x2301d, 0x2301d, 0x23022, 0x23022, 0x23027, 0x23032, 0x23037, 0x23037,
+ 0x2303c, 0x2303c, 0x23041, 0x23041, 0x23046, 0x23046, 0x2304b, 0x2304b,
+ 0x23050, 0x23050, 0x23055, 0x23055, 0x2305a, 0x2305a, 0x2305f, 0x2305f,
+ 0x23064, 0x23064, 0x23069, 0x2306a, 0x2306f, 0x2306f, 0x23074, 0x23075,
+ 0x2307a, 0x2307e, 0x23083, 0x23083, 0x23088, 0x23088, 0x2308d, 0x2308d,
+ 0x23092, 0x23092, 0x230e2, 0x230e2,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_isense_registers), 8));
+
+static const u32 gen7_9_0_rscc_registers[] = {
+ 0x14000, 0x14036, 0x14040, 0x14047, 0x14080, 0x14084, 0x14089, 0x1408c,
+ 0x14091, 0x14094, 0x14099, 0x1409c, 0x140a1, 0x140a4, 0x140a9, 0x140ac,
+ 0x14100, 0x14104, 0x14114, 0x14119, 0x14124, 0x14132, 0x14154, 0x1416b,
+ 0x14340, 0x14342, 0x14344, 0x1437c, 0x143f0, 0x143f8, 0x143fa, 0x143fe,
+ 0x14400, 0x14404, 0x14406, 0x1440a, 0x1440c, 0x14410, 0x14412, 0x14416,
+ 0x14418, 0x1441c, 0x1441e, 0x14422, 0x14424, 0x14424, 0x14498, 0x144a0,
+ 0x144a2, 0x144a6, 0x144a8, 0x144ac, 0x144ae, 0x144b2, 0x144b4, 0x144b8,
+ 0x144ba, 0x144be, 0x144c0, 0x144c4, 0x144c6, 0x144ca, 0x144cc, 0x144cc,
+ 0x14540, 0x14548, 0x1454a, 0x1454e, 0x14550, 0x14554, 0x14556, 0x1455a,
+ 0x1455c, 0x14560, 0x14562, 0x14566, 0x14568, 0x1456c, 0x1456e, 0x14572,
+ 0x14574, 0x14574, 0x145e8, 0x145f0, 0x145f2, 0x145f6, 0x145f8, 0x145fc,
+ 0x145fe, 0x14602, 0x14604, 0x14608, 0x1460a, 0x1460e, 0x14610, 0x14614,
+ 0x14616, 0x1461a, 0x1461c, 0x1461c, 0x14690, 0x14698, 0x1469a, 0x1469e,
+ 0x146a0, 0x146a4, 0x146a6, 0x146aa, 0x146ac, 0x146b0, 0x146b2, 0x146b6,
+ 0x146b8, 0x146bc, 0x146be, 0x146c2, 0x146c4, 0x146c4, 0x14738, 0x14740,
+ 0x14742, 0x14746, 0x14748, 0x1474c, 0x1474e, 0x14752, 0x14754, 0x14758,
+ 0x1475a, 0x1475e, 0x14760, 0x14764, 0x14766, 0x1476a, 0x1476c, 0x1476c,
+ 0x147e0, 0x147e8, 0x147ea, 0x147ee, 0x147f0, 0x147f4, 0x147f6, 0x147fa,
+ 0x147fc, 0x14800, 0x14802, 0x14806, 0x14808, 0x1480c, 0x1480e, 0x14812,
+ 0x14814, 0x14814, 0x14888, 0x14890, 0x14892, 0x14896, 0x14898, 0x1489c,
+ 0x1489e, 0x148a2, 0x148a4, 0x148a8, 0x148aa, 0x148ae, 0x148b0, 0x148b4,
+ 0x148b6, 0x148ba, 0x148bc, 0x148bc, 0x14930, 0x14938, 0x1493a, 0x1493e,
+ 0x14940, 0x14944, 0x14946, 0x1494a, 0x1494c, 0x14950, 0x14952, 0x14956,
+ 0x14958, 0x1495c, 0x1495e, 0x14962, 0x14964, 0x14964,
+ UINT_MAX, UINT_MAX,
+};
+static_assert(IS_ALIGNED(sizeof(gen7_9_0_rscc_registers), 8));
+
+static const u32 *gen7_9_0_external_core_regs[] = {
+ gen7_9_0_gpucc_registers,
+ gen7_9_0_gxclkctl_registers,
+ gen7_9_0_cpr_registers,
+ gen7_9_0_dpm_registers,
+ gen7_9_0_dpm_leakage_registers,
+ gen7_9_0_gfx_gpu_acd_registers,
+};
+#endif /*_ADRENO_GEN7_9_0_SNAPSHOT_H */
diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
deleted file mode 100644
index 7067376e25e1..000000000000
--- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
+++ /dev/null
@@ -1,2803 +0,0 @@
-#ifndef ADRENO_PM4_XML
-#define ADRENO_PM4_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
-http://gitlab.freedesktop.org/mesa/mesa/
-git clone https://gitlab.freedesktop.org/mesa/mesa.git
-
-The rules-ng-ng source files this header was generated from are:
-
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85856 bytes, from Fri Feb 23 13:07:00 2024)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
-*/
-
-#ifdef __KERNEL__
-#include <linux/bug.h>
-#define assert(x) BUG_ON(!(x))
-#else
-#include <assert.h>
-#endif
-
-#ifdef __cplusplus
-#define __struct_cast(X)
-#else
-#define __struct_cast(X) (struct X)
-#endif
-
-enum vgt_event_type {
- VS_DEALLOC = 0,
- PS_DEALLOC = 1,
- VS_DONE_TS = 2,
- PS_DONE_TS = 3,
- CACHE_FLUSH_TS = 4,
- CONTEXT_DONE = 5,
- CACHE_FLUSH = 6,
- VIZQUERY_START = 7,
- HLSQ_FLUSH = 7,
- VIZQUERY_END = 8,
- SC_WAIT_WC = 9,
- WRITE_PRIMITIVE_COUNTS = 9,
- START_PRIMITIVE_CTRS = 11,
- STOP_PRIMITIVE_CTRS = 12,
- RST_PIX_CNT = 13,
- RST_VTX_CNT = 14,
- TILE_FLUSH = 15,
- STAT_EVENT = 16,
- CACHE_FLUSH_AND_INV_TS_EVENT = 20,
- ZPASS_DONE = 21,
- CACHE_FLUSH_AND_INV_EVENT = 22,
- RB_DONE_TS = 22,
- PERFCOUNTER_START = 23,
- PERFCOUNTER_STOP = 24,
- VS_FETCH_DONE = 27,
- FACENESS_FLUSH = 28,
- WT_DONE_TS = 8,
- START_FRAGMENT_CTRS = 13,
- STOP_FRAGMENT_CTRS = 14,
- START_COMPUTE_CTRS = 15,
- STOP_COMPUTE_CTRS = 16,
- FLUSH_SO_0 = 17,
- FLUSH_SO_1 = 18,
- FLUSH_SO_2 = 19,
- FLUSH_SO_3 = 20,
- PC_CCU_INVALIDATE_DEPTH = 24,
- PC_CCU_INVALIDATE_COLOR = 25,
- PC_CCU_RESOLVE_TS = 26,
- PC_CCU_FLUSH_DEPTH_TS = 28,
- PC_CCU_FLUSH_COLOR_TS = 29,
- BLIT = 30,
- LRZ_CLEAR = 37,
- LRZ_FLUSH = 38,
- BLIT_OP_FILL_2D = 39,
- BLIT_OP_COPY_2D = 40,
- UNK_40 = 40,
- BLIT_OP_SCALE_2D = 42,
- CONTEXT_DONE_2D = 43,
- UNK_2C = 44,
- UNK_2D = 45,
- CACHE_INVALIDATE = 49,
- LABEL = 63,
- DUMMY_EVENT = 1,
- CCU_INVALIDATE_DEPTH = 24,
- CCU_INVALIDATE_COLOR = 25,
- CCU_RESOLVE_CLEAN = 26,
- CCU_FLUSH_DEPTH = 28,
- CCU_FLUSH_COLOR = 29,
- CCU_RESOLVE = 30,
- CCU_END_RESOLVE_GROUP = 31,
- CCU_CLEAN_DEPTH = 32,
- CCU_CLEAN_COLOR = 33,
- CACHE_RESET = 48,
- CACHE_CLEAN = 49,
- CACHE_FLUSH7 = 50,
- CACHE_INVALIDATE7 = 51,
-};
-
-enum pc_di_primtype {
- DI_PT_NONE = 0,
- DI_PT_POINTLIST_PSIZE = 1,
- DI_PT_LINELIST = 2,
- DI_PT_LINESTRIP = 3,
- DI_PT_TRILIST = 4,
- DI_PT_TRIFAN = 5,
- DI_PT_TRISTRIP = 6,
- DI_PT_LINELOOP = 7,
- DI_PT_RECTLIST = 8,
- DI_PT_POINTLIST = 9,
- DI_PT_LINE_ADJ = 10,
- DI_PT_LINESTRIP_ADJ = 11,
- DI_PT_TRI_ADJ = 12,
- DI_PT_TRISTRIP_ADJ = 13,
- DI_PT_PATCHES0 = 31,
- DI_PT_PATCHES1 = 32,
- DI_PT_PATCHES2 = 33,
- DI_PT_PATCHES3 = 34,
- DI_PT_PATCHES4 = 35,
- DI_PT_PATCHES5 = 36,
- DI_PT_PATCHES6 = 37,
- DI_PT_PATCHES7 = 38,
- DI_PT_PATCHES8 = 39,
- DI_PT_PATCHES9 = 40,
- DI_PT_PATCHES10 = 41,
- DI_PT_PATCHES11 = 42,
- DI_PT_PATCHES12 = 43,
- DI_PT_PATCHES13 = 44,
- DI_PT_PATCHES14 = 45,
- DI_PT_PATCHES15 = 46,
- DI_PT_PATCHES16 = 47,
- DI_PT_PATCHES17 = 48,
- DI_PT_PATCHES18 = 49,
- DI_PT_PATCHES19 = 50,
- DI_PT_PATCHES20 = 51,
- DI_PT_PATCHES21 = 52,
- DI_PT_PATCHES22 = 53,
- DI_PT_PATCHES23 = 54,
- DI_PT_PATCHES24 = 55,
- DI_PT_PATCHES25 = 56,
- DI_PT_PATCHES26 = 57,
- DI_PT_PATCHES27 = 58,
- DI_PT_PATCHES28 = 59,
- DI_PT_PATCHES29 = 60,
- DI_PT_PATCHES30 = 61,
- DI_PT_PATCHES31 = 62,
-};
-
-enum pc_di_src_sel {
- DI_SRC_SEL_DMA = 0,
- DI_SRC_SEL_IMMEDIATE = 1,
- DI_SRC_SEL_AUTO_INDEX = 2,
- DI_SRC_SEL_AUTO_XFB = 3,
-};
-
-enum pc_di_face_cull_sel {
- DI_FACE_CULL_NONE = 0,
- DI_FACE_CULL_FETCH = 1,
- DI_FACE_BACKFACE_CULL = 2,
- DI_FACE_FRONTFACE_CULL = 3,
-};
-
-enum pc_di_index_size {
- INDEX_SIZE_IGN = 0,
- INDEX_SIZE_16_BIT = 0,
- INDEX_SIZE_32_BIT = 1,
- INDEX_SIZE_8_BIT = 2,
- INDEX_SIZE_INVALID = 0,
-};
-
-enum pc_di_vis_cull_mode {
- IGNORE_VISIBILITY = 0,
- USE_VISIBILITY = 1,
-};
-
-enum adreno_pm4_packet_type {
- CP_TYPE0_PKT = 0x00000000,
- CP_TYPE1_PKT = 0x40000000,
- CP_TYPE2_PKT = 0x80000000,
- CP_TYPE3_PKT = 0xc0000000,
- CP_TYPE4_PKT = 0x40000000,
- CP_TYPE7_PKT = 0x70000000,
-};
-
-enum adreno_pm4_type3_packets {
- CP_ME_INIT = 72,
- CP_NOP = 16,
- CP_PREEMPT_ENABLE = 28,
- CP_PREEMPT_TOKEN = 30,
- CP_INDIRECT_BUFFER = 63,
- CP_INDIRECT_BUFFER_CHAIN = 87,
- CP_INDIRECT_BUFFER_PFD = 55,
- CP_WAIT_FOR_IDLE = 38,
- CP_WAIT_REG_MEM = 60,
- CP_WAIT_REG_EQ = 82,
- CP_WAIT_REG_GTE = 83,
- CP_WAIT_UNTIL_READ = 92,
- CP_WAIT_IB_PFD_COMPLETE = 93,
- CP_REG_RMW = 33,
- CP_SET_BIN_DATA = 47,
- CP_SET_BIN_DATA5 = 47,
- CP_REG_TO_MEM = 62,
- CP_MEM_WRITE = 61,
- CP_MEM_WRITE_CNTR = 79,
- CP_COND_EXEC = 68,
- CP_COND_WRITE = 69,
- CP_COND_WRITE5 = 69,
- CP_EVENT_WRITE = 70,
- CP_EVENT_WRITE7 = 70,
- CP_EVENT_WRITE_SHD = 88,
- CP_EVENT_WRITE_CFL = 89,
- CP_EVENT_WRITE_ZPD = 91,
- CP_RUN_OPENCL = 49,
- CP_DRAW_INDX = 34,
- CP_DRAW_INDX_2 = 54,
- CP_DRAW_INDX_BIN = 52,
- CP_DRAW_INDX_2_BIN = 53,
- CP_VIZ_QUERY = 35,
- CP_SET_STATE = 37,
- CP_SET_CONSTANT = 45,
- CP_IM_LOAD = 39,
- CP_IM_LOAD_IMMEDIATE = 43,
- CP_LOAD_CONSTANT_CONTEXT = 46,
- CP_INVALIDATE_STATE = 59,
- CP_SET_SHADER_BASES = 74,
- CP_SET_BIN_MASK = 80,
- CP_SET_BIN_SELECT = 81,
- CP_CONTEXT_UPDATE = 94,
- CP_INTERRUPT = 64,
- CP_IM_STORE = 44,
- CP_SET_DRAW_INIT_FLAGS = 75,
- CP_SET_PROTECTED_MODE = 95,
- CP_BOOTSTRAP_UCODE = 111,
- CP_LOAD_STATE = 48,
- CP_LOAD_STATE4 = 48,
- CP_COND_INDIRECT_BUFFER_PFE = 58,
- CP_COND_INDIRECT_BUFFER_PFD = 50,
- CP_INDIRECT_BUFFER_PFE = 63,
- CP_SET_BIN = 76,
- CP_TEST_TWO_MEMS = 113,
- CP_REG_WR_NO_CTXT = 120,
- CP_RECORD_PFP_TIMESTAMP = 17,
- CP_SET_SECURE_MODE = 102,
- CP_WAIT_FOR_ME = 19,
- CP_SET_DRAW_STATE = 67,
- CP_DRAW_INDX_OFFSET = 56,
- CP_DRAW_INDIRECT = 40,
- CP_DRAW_INDX_INDIRECT = 41,
- CP_DRAW_INDIRECT_MULTI = 42,
- CP_DRAW_AUTO = 36,
- CP_DRAW_PRED_ENABLE_GLOBAL = 25,
- CP_DRAW_PRED_ENABLE_LOCAL = 26,
- CP_DRAW_PRED_SET = 78,
- CP_WIDE_REG_WRITE = 116,
- CP_SCRATCH_TO_REG = 77,
- CP_REG_TO_SCRATCH = 74,
- CP_WAIT_MEM_WRITES = 18,
- CP_COND_REG_EXEC = 71,
- CP_MEM_TO_REG = 66,
- CP_EXEC_CS_INDIRECT = 65,
- CP_EXEC_CS = 51,
- CP_PERFCOUNTER_ACTION = 80,
- CP_SMMU_TABLE_UPDATE = 83,
- CP_SET_MARKER = 101,
- CP_SET_PSEUDO_REG = 86,
- CP_CONTEXT_REG_BUNCH = 92,
- CP_YIELD_ENABLE = 28,
- CP_SKIP_IB2_ENABLE_GLOBAL = 29,
- CP_SKIP_IB2_ENABLE_LOCAL = 35,
- CP_SET_SUBDRAW_SIZE = 53,
- CP_WHERE_AM_I = 98,
- CP_SET_VISIBILITY_OVERRIDE = 100,
- CP_PREEMPT_ENABLE_GLOBAL = 105,
- CP_PREEMPT_ENABLE_LOCAL = 106,
- CP_CONTEXT_SWITCH_YIELD = 107,
- CP_SET_RENDER_MODE = 108,
- CP_COMPUTE_CHECKPOINT = 110,
- CP_MEM_TO_MEM = 115,
- CP_BLIT = 44,
- CP_REG_TEST = 57,
- CP_SET_MODE = 99,
- CP_LOAD_STATE6_GEOM = 50,
- CP_LOAD_STATE6_FRAG = 52,
- CP_LOAD_STATE6 = 54,
- IN_IB_PREFETCH_END = 23,
- IN_SUBBLK_PREFETCH = 31,
- IN_INSTR_PREFETCH = 32,
- IN_INSTR_MATCH = 71,
- IN_CONST_PREFETCH = 73,
- IN_INCR_UPDT_STATE = 85,
- IN_INCR_UPDT_CONST = 86,
- IN_INCR_UPDT_INSTR = 87,
- PKT4 = 4,
- IN_IB_END = 10,
- IN_GMU_INTERRUPT = 11,
- IN_PREEMPT = 15,
- CP_SCRATCH_WRITE = 76,
- CP_REG_TO_MEM_OFFSET_MEM = 116,
- CP_REG_TO_MEM_OFFSET_REG = 114,
- CP_WAIT_MEM_GTE = 20,
- CP_WAIT_TWO_REGS = 112,
- CP_MEMCPY = 117,
- CP_SET_BIN_DATA5_OFFSET = 46,
- CP_SET_UNK_BIN_DATA = 45,
- CP_CONTEXT_SWITCH = 84,
- CP_SET_CTXSWITCH_IB = 85,
- CP_REG_WRITE = 109,
- CP_START_BIN = 80,
- CP_END_BIN = 81,
- CP_PREEMPT_DISABLE = 108,
- CP_WAIT_TIMESTAMP = 20,
- CP_GLOBAL_TIMESTAMP = 21,
- CP_LOCAL_TIMESTAMP = 22,
- CP_THREAD_CONTROL = 23,
- CP_RESOURCE_LIST = 24,
- CP_BV_BR_COUNT_OPS = 27,
- CP_MODIFY_TIMESTAMP = 28,
- CP_CONTEXT_REG_BUNCH2 = 93,
- CP_MEM_TO_SCRATCH_MEM = 73,
- CP_FIXED_STRIDE_DRAW_TABLE = 127,
- CP_RESET_CONTEXT_STATE = 31,
-};
-
-enum adreno_state_block {
- SB_VERT_TEX = 0,
- SB_VERT_MIPADDR = 1,
- SB_FRAG_TEX = 2,
- SB_FRAG_MIPADDR = 3,
- SB_VERT_SHADER = 4,
- SB_GEOM_SHADER = 5,
- SB_FRAG_SHADER = 6,
- SB_COMPUTE_SHADER = 7,
-};
-
-enum adreno_state_type {
- ST_SHADER = 0,
- ST_CONSTANTS = 1,
-};
-
-enum adreno_state_src {
- SS_DIRECT = 0,
- SS_INVALID_ALL_IC = 2,
- SS_INVALID_PART_IC = 3,
- SS_INDIRECT = 4,
- SS_INDIRECT_TCM = 5,
- SS_INDIRECT_STM = 6,
-};
-
-enum a4xx_state_block {
- SB4_VS_TEX = 0,
- SB4_HS_TEX = 1,
- SB4_DS_TEX = 2,
- SB4_GS_TEX = 3,
- SB4_FS_TEX = 4,
- SB4_CS_TEX = 5,
- SB4_VS_SHADER = 8,
- SB4_HS_SHADER = 9,
- SB4_DS_SHADER = 10,
- SB4_GS_SHADER = 11,
- SB4_FS_SHADER = 12,
- SB4_CS_SHADER = 13,
- SB4_SSBO = 14,
- SB4_CS_SSBO = 15,
-};
-
-enum a4xx_state_type {
- ST4_SHADER = 0,
- ST4_CONSTANTS = 1,
- ST4_UBO = 2,
-};
-
-enum a4xx_state_src {
- SS4_DIRECT = 0,
- SS4_INDIRECT = 2,
-};
-
-enum a6xx_state_block {
- SB6_VS_TEX = 0,
- SB6_HS_TEX = 1,
- SB6_DS_TEX = 2,
- SB6_GS_TEX = 3,
- SB6_FS_TEX = 4,
- SB6_CS_TEX = 5,
- SB6_VS_SHADER = 8,
- SB6_HS_SHADER = 9,
- SB6_DS_SHADER = 10,
- SB6_GS_SHADER = 11,
- SB6_FS_SHADER = 12,
- SB6_CS_SHADER = 13,
- SB6_IBO = 14,
- SB6_CS_IBO = 15,
-};
-
-enum a6xx_state_type {
- ST6_SHADER = 0,
- ST6_CONSTANTS = 1,
- ST6_UBO = 2,
- ST6_IBO = 3,
-};
-
-enum a6xx_state_src {
- SS6_DIRECT = 0,
- SS6_BINDLESS = 1,
- SS6_INDIRECT = 2,
- SS6_UBO = 3,
-};
-
-enum a4xx_index_size {
- INDEX4_SIZE_8_BIT = 0,
- INDEX4_SIZE_16_BIT = 1,
- INDEX4_SIZE_32_BIT = 2,
-};
-
-enum a6xx_patch_type {
- TESS_QUADS = 0,
- TESS_TRIANGLES = 1,
- TESS_ISOLINES = 2,
-};
-
-enum a6xx_draw_indirect_opcode {
- INDIRECT_OP_NORMAL = 2,
- INDIRECT_OP_INDEXED = 4,
- INDIRECT_OP_INDIRECT_COUNT = 6,
- INDIRECT_OP_INDIRECT_COUNT_INDEXED = 7,
-};
-
-enum cp_draw_pred_src {
- PRED_SRC_MEM = 5,
-};
-
-enum cp_draw_pred_test {
- NE_0_PASS = 0,
- EQ_0_PASS = 1,
-};
-
-enum cp_cond_function {
- WRITE_ALWAYS = 0,
- WRITE_LT = 1,
- WRITE_LE = 2,
- WRITE_EQ = 3,
- WRITE_NE = 4,
- WRITE_GE = 5,
- WRITE_GT = 6,
-};
-
-enum poll_memory_type {
- POLL_REGISTER = 0,
- POLL_MEMORY = 1,
- POLL_SCRATCH = 2,
- POLL_ON_CHIP = 3,
-};
-
-enum render_mode_cmd {
- BYPASS = 1,
- BINNING = 2,
- GMEM = 3,
- BLIT2D = 5,
- BLIT2DSCALE = 7,
- END2D = 8,
-};
-
-enum event_write_src {
- EV_WRITE_USER_32B = 0,
- EV_WRITE_USER_64B = 1,
- EV_WRITE_TIMESTAMP_SUM = 2,
- EV_WRITE_ALWAYSON = 3,
- EV_WRITE_REGS_CONTENT = 4,
-};
-
-enum event_write_dst {
- EV_DST_RAM = 0,
- EV_DST_ONCHIP = 1,
-};
-
-enum cp_blit_cmd {
- BLIT_OP_FILL = 0,
- BLIT_OP_COPY = 1,
- BLIT_OP_SCALE = 3,
-};
-
-enum a6xx_marker {
- RM6_BYPASS = 1,
- RM6_BINNING = 2,
- RM6_GMEM = 4,
- RM6_ENDVIS = 5,
- RM6_RESOLVE = 6,
- RM6_YIELD = 7,
- RM6_COMPUTE = 8,
- RM6_BLIT2DSCALE = 12,
- RM6_IB1LIST_START = 13,
- RM6_IB1LIST_END = 14,
- RM6_IFPC_ENABLE = 256,
- RM6_IFPC_DISABLE = 257,
-};
-
-enum pseudo_reg {
- SMMU_INFO = 0,
- NON_SECURE_SAVE_ADDR = 1,
- SECURE_SAVE_ADDR = 2,
- NON_PRIV_SAVE_ADDR = 3,
- COUNTER = 4,
- DRAW_STRM_ADDRESS = 8,
- DRAW_STRM_SIZE_ADDRESS = 9,
- PRIM_STRM_ADDRESS = 10,
- UNK_STRM_ADDRESS = 11,
- UNK_STRM_SIZE_ADDRESS = 12,
- BINDLESS_BASE_0_ADDR = 16,
- BINDLESS_BASE_1_ADDR = 17,
- BINDLESS_BASE_2_ADDR = 18,
- BINDLESS_BASE_3_ADDR = 19,
- BINDLESS_BASE_4_ADDR = 20,
- BINDLESS_BASE_5_ADDR = 21,
- BINDLESS_BASE_6_ADDR = 22,
-};
-
-enum source_type {
- SOURCE_REG = 0,
- SOURCE_SCRATCH_MEM = 1,
-};
-
-enum compare_mode {
- PRED_TEST = 1,
- REG_COMPARE = 2,
- RENDER_MODE = 3,
- REG_COMPARE_IMM = 4,
- THREAD_MODE = 5,
-};
-
-enum ctxswitch_ib {
- RESTORE_IB = 0,
- YIELD_RESTORE_IB = 1,
- SAVE_IB = 2,
- RB_SAVE_IB = 3,
-};
-
-enum reg_tracker {
- TRACK_CNTL_REG = 1,
- TRACK_RENDER_CNTL = 2,
- UNK_EVENT_WRITE = 4,
- TRACK_LRZ = 8,
-};
-
-enum ts_wait_value_src {
- TS_WAIT_GE_32B = 0,
- TS_WAIT_GE_64B = 1,
- TS_WAIT_GE_TIMESTAMP_SUM = 2,
-};
-
-enum ts_wait_type {
- TS_WAIT_RAM = 0,
- TS_WAIT_ONCHIP = 1,
-};
-
-enum pipe_count_op {
- PIPE_CLEAR_BV_BR = 1,
- PIPE_SET_BR_OFFSET = 2,
- PIPE_BR_WAIT_FOR_BV = 3,
- PIPE_BV_WAIT_FOR_BR = 4,
-};
-
-enum timestamp_op {
- MODIFY_TIMESTAMP_CLEAR = 0,
- MODIFY_TIMESTAMP_ADD_GLOBAL = 1,
- MODIFY_TIMESTAMP_ADD_LOCAL = 2,
-};
-
-enum cp_thread {
- CP_SET_THREAD_BR = 1,
- CP_SET_THREAD_BV = 2,
- CP_SET_THREAD_BOTH = 3,
-};
-
-#define REG_CP_LOAD_STATE_0 0x00000000
-#define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
-#define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
-static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
-{
- return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
-}
-#define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
-#define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
-static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
-{
- return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
-}
-#define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
-#define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
-static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
-{
- return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
-}
-#define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
-#define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
-static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
-{
- return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
-}
-
-#define REG_CP_LOAD_STATE_1 0x00000001
-#define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
-#define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
-static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
-{
- return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
-}
-#define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
-#define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
-static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
-}
-
-#define REG_CP_LOAD_STATE4_0 0x00000000
-#define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff
-#define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0
-static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
-{
- return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
-}
-#define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000
-#define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16
-static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
-{
- return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
-}
-#define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000
-#define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18
-static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
-{
- return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
-}
-#define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000
-#define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22
-static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
-{
- return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
-}
-
-#define REG_CP_LOAD_STATE4_1 0x00000001
-#define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003
-#define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0
-static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
-{
- return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
-}
-#define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc
-#define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2
-static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
-}
-
-#define REG_CP_LOAD_STATE4_2 0x00000002
-#define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
-#define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0
-static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
-{
- return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
-}
-
-#define REG_CP_LOAD_STATE6_0 0x00000000
-#define CP_LOAD_STATE6_0_DST_OFF__MASK 0x00003fff
-#define CP_LOAD_STATE6_0_DST_OFF__SHIFT 0
-static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)
-{
- return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;
-}
-#define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x0000c000
-#define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT 14
-static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)
-{
- return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK;
-}
-#define CP_LOAD_STATE6_0_STATE_SRC__MASK 0x00030000
-#define CP_LOAD_STATE6_0_STATE_SRC__SHIFT 16
-static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)
-{
- return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK;
-}
-#define CP_LOAD_STATE6_0_STATE_BLOCK__MASK 0x003c0000
-#define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT 18
-static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)
-{
- return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK;
-}
-#define CP_LOAD_STATE6_0_NUM_UNIT__MASK 0xffc00000
-#define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT 22
-static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)
-{
- return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK;
-}
-
-#define REG_CP_LOAD_STATE6_1 0x00000001
-#define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK 0xfffffffc
-#define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2
-static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)
-{
- assert(!(val & 0x3));
- return (((val >> 2)) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;
-}
-
-#define REG_CP_LOAD_STATE6_2 0x00000002
-#define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
-#define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT 0
-static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)
-{
- return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;
-}
-
-#define REG_CP_LOAD_STATE6_EXT_SRC_ADDR 0x00000001
-
-#define REG_CP_DRAW_INDX_0 0x00000000
-#define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
-#define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
-{
- return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
-}
-
-#define REG_CP_DRAW_INDX_1 0x00000001
-#define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
-#define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
-{
- return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
-}
-#define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
-#define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
-static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
-{
- return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
-}
-#define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
-#define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
-static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
-{
- return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
-}
-#define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
-#define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
-static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
-{
- return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
-}
-#define CP_DRAW_INDX_1_NOT_EOP 0x00001000
-#define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
-#define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
-#define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000
-#define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24
-static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
-{
- return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
-}
-
-#define REG_CP_DRAW_INDX_2 0x00000002
-#define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
-#define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
-{
- return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
-}
-
-#define REG_CP_DRAW_INDX_3 0x00000003
-#define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff
-#define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
-{
- return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
-}
-
-#define REG_CP_DRAW_INDX_4 0x00000004
-#define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff
-#define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
-{
- return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
-}
-
-#define REG_CP_DRAW_INDX_2_0 0x00000000
-#define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
-#define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
-{
- return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
-}
-
-#define REG_CP_DRAW_INDX_2_1 0x00000001
-#define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
-#define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
-{
- return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
-}
-#define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
-#define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
-static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
-{
- return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
-}
-#define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
-#define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
-static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
-{
- return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
-}
-#define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
-#define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
-static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
-{
- return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
-}
-#define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
-#define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
-#define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
-#define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000
-#define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24
-static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
-{
- return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
-}
-
-#define REG_CP_DRAW_INDX_2_2 0x00000002
-#define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
-#define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
-{
- return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
-}
-
-#define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
-#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
-#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
-{
- return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
-}
-#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
-#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
-static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
-{
- return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
-}
-#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300
-#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
-static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
-{
- return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
-}
-#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
-#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
-static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
-{
- return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
-}
-#define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK 0x00003000
-#define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT 12
-static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val)
-{
- return ((val) << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK;
-}
-#define CP_DRAW_INDX_OFFSET_0_GS_ENABLE 0x00010000
-#define CP_DRAW_INDX_OFFSET_0_TESS_ENABLE 0x00020000
-
-#define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
-#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
-#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
-{
- return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
-}
-
-#define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
-#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
-#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
-{
- return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
-}
-
-#define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
-#define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK 0xffffffff
-#define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val)
-{
- return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK;
-}
-
-#define REG_A5XX_CP_DRAW_INDX_OFFSET_4 0x00000004
-#define A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK 0xffffffff
-#define A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT 0
-static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val)
-{
- return ((val) << A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK;
-}
-
-#define REG_A5XX_CP_DRAW_INDX_OFFSET_5 0x00000005
-#define A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK 0xffffffff
-#define A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT 0
-static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val)
-{
- return ((val) << A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK;
-}
-
-#define REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE 0x00000004
-
-#define REG_A5XX_CP_DRAW_INDX_OFFSET_6 0x00000006
-#define A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK 0xffffffff
-#define A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT 0
-static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val)
-{
- return ((val) << A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK;
-}
-
-#define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
-#define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
-#define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint64_t val)
-{
- return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
-}
-
-#define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
-#define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff
-#define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0
-static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
-{
- return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
-}
-
-#define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000
-#define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
-#define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0
-static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
-{
- return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK;
-}
-#define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
-#define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6
-static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
-{
- return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK;
-}
-#define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300
-#define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8
-static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
-{
- return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;
-}
-#define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
-#define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10
-static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
-{
- return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
-}
-#define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK 0x00003000
-#define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT 12
-static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
-{
- return ((val) << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK;
-}
-#define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE 0x00010000
-#define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE 0x00020000
-
-#define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001
-#define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff
-#define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0
-static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)
-{
- return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;
-}
-
-#define REG_A5XX_CP_DRAW_INDIRECT_1 0x00000001
-#define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK 0xffffffff
-#define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT 0
-static inline uint32_t A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val)
-{
- return ((val) << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK;
-}
-
-#define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002
-#define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff
-#define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0
-static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
-{
- return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
-}
-
-#define REG_A5XX_CP_DRAW_INDIRECT_INDIRECT 0x00000001
-
-#define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000
-#define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
-#define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0
-static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
-{
- return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK;
-}
-#define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
-#define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6
-static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
-{
- return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK;
-}
-#define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300
-#define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8
-static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
-{
- return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK;
-}
-#define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
-#define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10
-static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
-{
- return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
-}
-#define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK 0x00003000
-#define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT 12
-static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val)
-{
- return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK;
-}
-#define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE 0x00010000
-#define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE 0x00020000
-
-#define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
-#define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff
-#define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0
-static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)
-{
- return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK;
-}
-
-#define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
-#define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff
-#define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0
-static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)
-{
- return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK;
-}
-
-#define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
-#define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff
-#define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0
-static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)
-{
- return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK;
-}
-
-#define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
-#define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff
-#define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0
-static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)
-{
- return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK;
-}
-
-#define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
-#define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff
-#define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0
-static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
-{
- return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
-}
-
-#define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE 0x00000001
-
-#define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
-#define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff
-#define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0
-static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)
-{
- return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK;
-}
-
-#define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004
-#define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff
-#define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0
-static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)
-{
- return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK;
-}
-
-#define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005
-#define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff
-#define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0
-static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
-{
- return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
-}
-
-#define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT 0x00000004
-
-#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 0x00000000
-#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK 0x0000003f
-#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT 0
-static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val)
-{
- return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK;
-}
-#define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK 0x000000c0
-#define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT 6
-static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val)
-{
- return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK;
-}
-#define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK 0x00000300
-#define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT 8
-static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val)
-{
- return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK;
-}
-#define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK 0x00000c00
-#define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT 10
-static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val)
-{
- return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK;
-}
-#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK 0x00003000
-#define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT 12
-static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val)
-{
- return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK;
-}
-#define A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE 0x00010000
-#define A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE 0x00020000
-
-#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 0x00000001
-#define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK 0x0000000f
-#define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT 0
-static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val)
-{
- return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK;
-}
-#define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK 0x003fff00
-#define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT 8
-static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val)
-{
- return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK;
-}
-
-#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT 0x00000002
-
-#define REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003
-
-#define REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005
-
-#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX 0x00000003
-
-#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES 0x00000005
-
-#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006
-
-#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000008
-
-#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003
-
-#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT 0x00000005
-
-#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000007
-
-#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX 0x00000003
-
-#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES 0x00000005
-
-#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006
-
-#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT 0x00000008
-
-#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE 0x0000000a
-
-#define REG_CP_DRAW_AUTO_0 0x00000000
-#define CP_DRAW_AUTO_0_PRIM_TYPE__MASK 0x0000003f
-#define CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT 0
-static inline uint32_t CP_DRAW_AUTO_0_PRIM_TYPE(enum pc_di_primtype val)
-{
- return ((val) << CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT) & CP_DRAW_AUTO_0_PRIM_TYPE__MASK;
-}
-#define CP_DRAW_AUTO_0_SOURCE_SELECT__MASK 0x000000c0
-#define CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT 6
-static inline uint32_t CP_DRAW_AUTO_0_SOURCE_SELECT(enum pc_di_src_sel val)
-{
- return ((val) << CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT) & CP_DRAW_AUTO_0_SOURCE_SELECT__MASK;
-}
-#define CP_DRAW_AUTO_0_VIS_CULL__MASK 0x00000300
-#define CP_DRAW_AUTO_0_VIS_CULL__SHIFT 8
-static inline uint32_t CP_DRAW_AUTO_0_VIS_CULL(enum pc_di_vis_cull_mode val)
-{
- return ((val) << CP_DRAW_AUTO_0_VIS_CULL__SHIFT) & CP_DRAW_AUTO_0_VIS_CULL__MASK;
-}
-#define CP_DRAW_AUTO_0_INDEX_SIZE__MASK 0x00000c00
-#define CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT 10
-static inline uint32_t CP_DRAW_AUTO_0_INDEX_SIZE(enum a4xx_index_size val)
-{
- return ((val) << CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT) & CP_DRAW_AUTO_0_INDEX_SIZE__MASK;
-}
-#define CP_DRAW_AUTO_0_PATCH_TYPE__MASK 0x00003000
-#define CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT 12
-static inline uint32_t CP_DRAW_AUTO_0_PATCH_TYPE(enum a6xx_patch_type val)
-{
- return ((val) << CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT) & CP_DRAW_AUTO_0_PATCH_TYPE__MASK;
-}
-#define CP_DRAW_AUTO_0_GS_ENABLE 0x00010000
-#define CP_DRAW_AUTO_0_TESS_ENABLE 0x00020000
-
-#define REG_CP_DRAW_AUTO_1 0x00000001
-#define CP_DRAW_AUTO_1_NUM_INSTANCES__MASK 0xffffffff
-#define CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT 0
-static inline uint32_t CP_DRAW_AUTO_1_NUM_INSTANCES(uint32_t val)
-{
- return ((val) << CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT) & CP_DRAW_AUTO_1_NUM_INSTANCES__MASK;
-}
-
-#define REG_CP_DRAW_AUTO_NUM_VERTICES_BASE 0x00000002
-
-#define REG_CP_DRAW_AUTO_4 0x00000004
-#define CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK 0xffffffff
-#define CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT 0
-static inline uint32_t CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET(uint32_t val)
-{
- return ((val) << CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT) & CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK;
-}
-
-#define REG_CP_DRAW_AUTO_5 0x00000005
-#define CP_DRAW_AUTO_5_STRIDE__MASK 0xffffffff
-#define CP_DRAW_AUTO_5_STRIDE__SHIFT 0
-static inline uint32_t CP_DRAW_AUTO_5_STRIDE(uint32_t val)
-{
- return ((val) << CP_DRAW_AUTO_5_STRIDE__SHIFT) & CP_DRAW_AUTO_5_STRIDE__MASK;
-}
-
-#define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 0x00000000
-#define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE 0x00000001
-
-#define REG_CP_DRAW_PRED_ENABLE_LOCAL_0 0x00000000
-#define CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE 0x00000001
-
-#define REG_CP_DRAW_PRED_SET_0 0x00000000
-#define CP_DRAW_PRED_SET_0_SRC__MASK 0x000000f0
-#define CP_DRAW_PRED_SET_0_SRC__SHIFT 4
-static inline uint32_t CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val)
-{
- return ((val) << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK;
-}
-#define CP_DRAW_PRED_SET_0_TEST__MASK 0x00000100
-#define CP_DRAW_PRED_SET_0_TEST__SHIFT 8
-static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val)
-{
- return ((val) << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK;
-}
-
-#define REG_CP_DRAW_PRED_SET_MEM_ADDR 0x00000001
-
-#define REG_CP_SET_DRAW_STATE_(i0) (0x00000000 + 0x3*(i0))
-
-static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
-#define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
-#define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0
-static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
-{
- return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
-}
-#define CP_SET_DRAW_STATE__0_DIRTY 0x00010000
-#define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
-#define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
-#define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
-#define CP_SET_DRAW_STATE__0_BINNING 0x00100000
-#define CP_SET_DRAW_STATE__0_GMEM 0x00200000
-#define CP_SET_DRAW_STATE__0_SYSMEM 0x00400000
-#define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
-#define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24
-static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
-{
- return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
-}
-
-static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
-#define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff
-#define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0
-static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
-{
- return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
-}
-
-static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
-#define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff
-#define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0
-static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
-{
- return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
-}
-
-#define REG_CP_SET_BIN_0 0x00000000
-
-#define REG_CP_SET_BIN_1 0x00000001
-#define CP_SET_BIN_1_X1__MASK 0x0000ffff
-#define CP_SET_BIN_1_X1__SHIFT 0
-static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
-{
- return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
-}
-#define CP_SET_BIN_1_Y1__MASK 0xffff0000
-#define CP_SET_BIN_1_Y1__SHIFT 16
-static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
-{
- return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
-}
-
-#define REG_CP_SET_BIN_2 0x00000002
-#define CP_SET_BIN_2_X2__MASK 0x0000ffff
-#define CP_SET_BIN_2_X2__SHIFT 0
-static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
-{
- return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
-}
-#define CP_SET_BIN_2_Y2__MASK 0xffff0000
-#define CP_SET_BIN_2_Y2__SHIFT 16
-static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
-{
- return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
-}
-
-#define REG_CP_SET_BIN_DATA_0 0x00000000
-#define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
-#define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
-static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
-{
- return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
-}
-
-#define REG_CP_SET_BIN_DATA_1 0x00000001
-#define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
-#define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
-static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
-{
- return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
-}
-
-#define REG_CP_SET_BIN_DATA5_0 0x00000000
-#define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000
-#define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16
-static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
-{
- return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
-}
-#define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000
-#define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22
-static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
-{
- return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
-}
-
-#define REG_CP_SET_BIN_DATA5_1 0x00000001
-#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff
-#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0
-static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
-{
- return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
-}
-
-#define REG_CP_SET_BIN_DATA5_2 0x00000002
-#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff
-#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0
-static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
-{
- return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
-}
-
-#define REG_CP_SET_BIN_DATA5_3 0x00000003
-#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff
-#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0
-static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
-{
- return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
-}
-
-#define REG_CP_SET_BIN_DATA5_4 0x00000004
-#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff
-#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0
-static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
-{
- return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
-}
-
-#define REG_CP_SET_BIN_DATA5_5 0x00000005
-#define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK 0xffffffff
-#define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT 0
-static inline uint32_t CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val)
-{
- return ((val) << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK;
-}
-
-#define REG_CP_SET_BIN_DATA5_6 0x00000006
-#define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK 0xffffffff
-#define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT 0
-static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val)
-{
- return ((val) << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK;
-}
-
-#define REG_CP_SET_BIN_DATA5_7 0x00000007
-
-#define REG_CP_SET_BIN_DATA5_9 0x00000009
-
-#define REG_CP_SET_BIN_DATA5_OFFSET_0 0x00000000
-#define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK 0x003f0000
-#define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT 16
-static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val)
-{
- return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK;
-}
-#define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK 0x07c00000
-#define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT 22
-static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val)
-{
- return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK;
-}
-
-#define REG_CP_SET_BIN_DATA5_OFFSET_1 0x00000001
-#define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK 0xffffffff
-#define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT 0
-static inline uint32_t CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val)
-{
- return ((val) << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK;
-}
-
-#define REG_CP_SET_BIN_DATA5_OFFSET_2 0x00000002
-#define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK 0xffffffff
-#define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT 0
-static inline uint32_t CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val)
-{
- return ((val) << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK;
-}
-
-#define REG_CP_SET_BIN_DATA5_OFFSET_3 0x00000003
-#define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK 0xffffffff
-#define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT 0
-static inline uint32_t CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val)
-{
- return ((val) << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK;
-}
-
-#define REG_CP_REG_RMW_0 0x00000000
-#define CP_REG_RMW_0_DST_REG__MASK 0x0003ffff
-#define CP_REG_RMW_0_DST_REG__SHIFT 0
-static inline uint32_t CP_REG_RMW_0_DST_REG(uint32_t val)
-{
- return ((val) << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK;
-}
-#define CP_REG_RMW_0_ROTATE__MASK 0x1f000000
-#define CP_REG_RMW_0_ROTATE__SHIFT 24
-static inline uint32_t CP_REG_RMW_0_ROTATE(uint32_t val)
-{
- return ((val) << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK;
-}
-#define CP_REG_RMW_0_SRC1_ADD 0x20000000
-#define CP_REG_RMW_0_SRC1_IS_REG 0x40000000
-#define CP_REG_RMW_0_SRC0_IS_REG 0x80000000
-
-#define REG_CP_REG_RMW_1 0x00000001
-#define CP_REG_RMW_1_SRC0__MASK 0xffffffff
-#define CP_REG_RMW_1_SRC0__SHIFT 0
-static inline uint32_t CP_REG_RMW_1_SRC0(uint32_t val)
-{
- return ((val) << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK;
-}
-
-#define REG_CP_REG_RMW_2 0x00000002
-#define CP_REG_RMW_2_SRC1__MASK 0xffffffff
-#define CP_REG_RMW_2_SRC1__SHIFT 0
-static inline uint32_t CP_REG_RMW_2_SRC1(uint32_t val)
-{
- return ((val) << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK;
-}
-
-#define REG_CP_REG_TO_MEM_0 0x00000000
-#define CP_REG_TO_MEM_0_REG__MASK 0x0003ffff
-#define CP_REG_TO_MEM_0_REG__SHIFT 0
-static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
-{
- return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
-}
-#define CP_REG_TO_MEM_0_CNT__MASK 0x3ffc0000
-#define CP_REG_TO_MEM_0_CNT__SHIFT 18
-static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
-{
- return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
-}
-#define CP_REG_TO_MEM_0_64B 0x40000000
-#define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
-
-#define REG_CP_REG_TO_MEM_1 0x00000001
-#define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
-#define CP_REG_TO_MEM_1_DEST__SHIFT 0
-static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
-{
- return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
-}
-
-#define REG_CP_REG_TO_MEM_2 0x00000002
-#define CP_REG_TO_MEM_2_DEST_HI__MASK 0xffffffff
-#define CP_REG_TO_MEM_2_DEST_HI__SHIFT 0
-static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)
-{
- return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;
-}
-
-#define REG_CP_REG_TO_MEM_OFFSET_REG_0 0x00000000
-#define CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK 0x0003ffff
-#define CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT 0
-static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val)
-{
- return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK;
-}
-#define CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK 0x3ffc0000
-#define CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT 18
-static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val)
-{
- return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK;
-}
-#define CP_REG_TO_MEM_OFFSET_REG_0_64B 0x40000000
-#define CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE 0x80000000
-
-#define REG_CP_REG_TO_MEM_OFFSET_REG_1 0x00000001
-#define CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK 0xffffffff
-#define CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT 0
-static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val)
-{
- return ((val) << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK;
-}
-
-#define REG_CP_REG_TO_MEM_OFFSET_REG_2 0x00000002
-#define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK 0xffffffff
-#define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT 0
-static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val)
-{
- return ((val) << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK;
-}
-
-#define REG_CP_REG_TO_MEM_OFFSET_REG_3 0x00000003
-#define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK 0x0003ffff
-#define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT 0
-static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val)
-{
- return ((val) << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK;
-}
-#define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH 0x00080000
-
-#define REG_CP_REG_TO_MEM_OFFSET_MEM_0 0x00000000
-#define CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK 0x0003ffff
-#define CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT 0
-static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val)
-{
- return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK;
-}
-#define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK 0x3ffc0000
-#define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT 18
-static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val)
-{
- return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK;
-}
-#define CP_REG_TO_MEM_OFFSET_MEM_0_64B 0x40000000
-#define CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE 0x80000000
-
-#define REG_CP_REG_TO_MEM_OFFSET_MEM_1 0x00000001
-#define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK 0xffffffff
-#define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT 0
-static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val)
-{
- return ((val) << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK;
-}
-
-#define REG_CP_REG_TO_MEM_OFFSET_MEM_2 0x00000002
-#define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK 0xffffffff
-#define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT 0
-static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val)
-{
- return ((val) << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK;
-}
-
-#define REG_CP_REG_TO_MEM_OFFSET_MEM_3 0x00000003
-#define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK 0xffffffff
-#define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT 0
-static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val)
-{
- return ((val) << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK;
-}
-
-#define REG_CP_REG_TO_MEM_OFFSET_MEM_4 0x00000004
-#define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK 0xffffffff
-#define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT 0
-static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val)
-{
- return ((val) << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK;
-}
-
-#define REG_CP_MEM_TO_REG_0 0x00000000
-#define CP_MEM_TO_REG_0_REG__MASK 0x0003ffff
-#define CP_MEM_TO_REG_0_REG__SHIFT 0
-static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)
-{
- return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK;
-}
-#define CP_MEM_TO_REG_0_CNT__MASK 0x3ff80000
-#define CP_MEM_TO_REG_0_CNT__SHIFT 19
-static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)
-{
- return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;
-}
-#define CP_MEM_TO_REG_0_SHIFT_BY_2 0x40000000
-#define CP_MEM_TO_REG_0_UNK31 0x80000000
-
-#define REG_CP_MEM_TO_REG_1 0x00000001
-#define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff
-#define CP_MEM_TO_REG_1_SRC__SHIFT 0
-static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val)
-{
- return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK;
-}
-
-#define REG_CP_MEM_TO_REG_2 0x00000002
-#define CP_MEM_TO_REG_2_SRC_HI__MASK 0xffffffff
-#define CP_MEM_TO_REG_2_SRC_HI__SHIFT 0
-static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)
-{
- return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK;
-}
-
-#define REG_CP_MEM_TO_MEM_0 0x00000000
-#define CP_MEM_TO_MEM_0_NEG_A 0x00000001
-#define CP_MEM_TO_MEM_0_NEG_B 0x00000002
-#define CP_MEM_TO_MEM_0_NEG_C 0x00000004
-#define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
-#define CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES 0x40000000
-#define CP_MEM_TO_MEM_0_UNK31 0x80000000
-
-#define REG_CP_MEMCPY_0 0x00000000
-#define CP_MEMCPY_0_DWORDS__MASK 0xffffffff
-#define CP_MEMCPY_0_DWORDS__SHIFT 0
-static inline uint32_t CP_MEMCPY_0_DWORDS(uint32_t val)
-{
- return ((val) << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK;
-}
-
-#define REG_CP_MEMCPY_1 0x00000001
-#define CP_MEMCPY_1_SRC_LO__MASK 0xffffffff
-#define CP_MEMCPY_1_SRC_LO__SHIFT 0
-static inline uint32_t CP_MEMCPY_1_SRC_LO(uint32_t val)
-{
- return ((val) << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK;
-}
-
-#define REG_CP_MEMCPY_2 0x00000002
-#define CP_MEMCPY_2_SRC_HI__MASK 0xffffffff
-#define CP_MEMCPY_2_SRC_HI__SHIFT 0
-static inline uint32_t CP_MEMCPY_2_SRC_HI(uint32_t val)
-{
- return ((val) << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK;
-}
-
-#define REG_CP_MEMCPY_3 0x00000003
-#define CP_MEMCPY_3_DST_LO__MASK 0xffffffff
-#define CP_MEMCPY_3_DST_LO__SHIFT 0
-static inline uint32_t CP_MEMCPY_3_DST_LO(uint32_t val)
-{
- return ((val) << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK;
-}
-
-#define REG_CP_MEMCPY_4 0x00000004
-#define CP_MEMCPY_4_DST_HI__MASK 0xffffffff
-#define CP_MEMCPY_4_DST_HI__SHIFT 0
-static inline uint32_t CP_MEMCPY_4_DST_HI(uint32_t val)
-{
- return ((val) << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK;
-}
-
-#define REG_CP_REG_TO_SCRATCH_0 0x00000000
-#define CP_REG_TO_SCRATCH_0_REG__MASK 0x0003ffff
-#define CP_REG_TO_SCRATCH_0_REG__SHIFT 0
-static inline uint32_t CP_REG_TO_SCRATCH_0_REG(uint32_t val)
-{
- return ((val) << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK;
-}
-#define CP_REG_TO_SCRATCH_0_SCRATCH__MASK 0x00700000
-#define CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT 20
-static inline uint32_t CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val)
-{
- return ((val) << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK;
-}
-#define CP_REG_TO_SCRATCH_0_CNT__MASK 0x07000000
-#define CP_REG_TO_SCRATCH_0_CNT__SHIFT 24
-static inline uint32_t CP_REG_TO_SCRATCH_0_CNT(uint32_t val)
-{
- return ((val) << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK;
-}
-
-#define REG_CP_SCRATCH_TO_REG_0 0x00000000
-#define CP_SCRATCH_TO_REG_0_REG__MASK 0x0003ffff
-#define CP_SCRATCH_TO_REG_0_REG__SHIFT 0
-static inline uint32_t CP_SCRATCH_TO_REG_0_REG(uint32_t val)
-{
- return ((val) << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK;
-}
-#define CP_SCRATCH_TO_REG_0_UNK18 0x00040000
-#define CP_SCRATCH_TO_REG_0_SCRATCH__MASK 0x00700000
-#define CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT 20
-static inline uint32_t CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val)
-{
- return ((val) << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK;
-}
-#define CP_SCRATCH_TO_REG_0_CNT__MASK 0x07000000
-#define CP_SCRATCH_TO_REG_0_CNT__SHIFT 24
-static inline uint32_t CP_SCRATCH_TO_REG_0_CNT(uint32_t val)
-{
- return ((val) << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK;
-}
-
-#define REG_CP_SCRATCH_WRITE_0 0x00000000
-#define CP_SCRATCH_WRITE_0_SCRATCH__MASK 0x00700000
-#define CP_SCRATCH_WRITE_0_SCRATCH__SHIFT 20
-static inline uint32_t CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val)
-{
- return ((val) << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK;
-}
-
-#define REG_CP_MEM_WRITE_0 0x00000000
-#define CP_MEM_WRITE_0_ADDR_LO__MASK 0xffffffff
-#define CP_MEM_WRITE_0_ADDR_LO__SHIFT 0
-static inline uint32_t CP_MEM_WRITE_0_ADDR_LO(uint32_t val)
-{
- return ((val) << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK;
-}
-
-#define REG_CP_MEM_WRITE_1 0x00000001
-#define CP_MEM_WRITE_1_ADDR_HI__MASK 0xffffffff
-#define CP_MEM_WRITE_1_ADDR_HI__SHIFT 0
-static inline uint32_t CP_MEM_WRITE_1_ADDR_HI(uint32_t val)
-{
- return ((val) << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK;
-}
-
-#define REG_CP_COND_WRITE_0 0x00000000
-#define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
-#define CP_COND_WRITE_0_FUNCTION__SHIFT 0
-static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
-{
- return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
-}
-#define CP_COND_WRITE_0_POLL_MEMORY 0x00000010
-#define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100
-
-#define REG_CP_COND_WRITE_1 0x00000001
-#define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff
-#define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0
-static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
-{
- return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
-}
-
-#define REG_CP_COND_WRITE_2 0x00000002
-#define CP_COND_WRITE_2_REF__MASK 0xffffffff
-#define CP_COND_WRITE_2_REF__SHIFT 0
-static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
-{
- return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
-}
-
-#define REG_CP_COND_WRITE_3 0x00000003
-#define CP_COND_WRITE_3_MASK__MASK 0xffffffff
-#define CP_COND_WRITE_3_MASK__SHIFT 0
-static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
-{
- return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
-}
-
-#define REG_CP_COND_WRITE_4 0x00000004
-#define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff
-#define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0
-static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
-{
- return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
-}
-
-#define REG_CP_COND_WRITE_5 0x00000005
-#define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff
-#define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0
-static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
-{
- return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
-}
-
-#define REG_CP_COND_WRITE5_0 0x00000000
-#define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007
-#define CP_COND_WRITE5_0_FUNCTION__SHIFT 0
-static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
-{
- return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
-}
-#define CP_COND_WRITE5_0_SIGNED_COMPARE 0x00000008
-#define CP_COND_WRITE5_0_POLL__MASK 0x00000030
-#define CP_COND_WRITE5_0_POLL__SHIFT 4
-static inline uint32_t CP_COND_WRITE5_0_POLL(enum poll_memory_type val)
-{
- return ((val) << CP_COND_WRITE5_0_POLL__SHIFT) & CP_COND_WRITE5_0_POLL__MASK;
-}
-#define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
-
-#define REG_CP_COND_WRITE5_1 0x00000001
-#define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff
-#define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0
-static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
-{
- return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
-}
-
-#define REG_CP_COND_WRITE5_2 0x00000002
-#define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff
-#define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0
-static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
-{
- return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
-}
-
-#define REG_CP_COND_WRITE5_3 0x00000003
-#define CP_COND_WRITE5_3_REF__MASK 0xffffffff
-#define CP_COND_WRITE5_3_REF__SHIFT 0
-static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
-{
- return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
-}
-
-#define REG_CP_COND_WRITE5_4 0x00000004
-#define CP_COND_WRITE5_4_MASK__MASK 0xffffffff
-#define CP_COND_WRITE5_4_MASK__SHIFT 0
-static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
-{
- return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
-}
-
-#define REG_CP_COND_WRITE5_5 0x00000005
-#define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff
-#define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0
-static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
-{
- return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
-}
-
-#define REG_CP_COND_WRITE5_6 0x00000006
-#define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff
-#define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0
-static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
-{
- return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
-}
-
-#define REG_CP_COND_WRITE5_7 0x00000007
-#define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff
-#define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0
-static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
-{
- return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
-}
-
-#define REG_CP_WAIT_MEM_GTE_0 0x00000000
-#define CP_WAIT_MEM_GTE_0_RESERVED__MASK 0xffffffff
-#define CP_WAIT_MEM_GTE_0_RESERVED__SHIFT 0
-static inline uint32_t CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val)
-{
- return ((val) << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK;
-}
-
-#define REG_CP_WAIT_MEM_GTE_1 0x00000001
-#define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK 0xffffffff
-#define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT 0
-static inline uint32_t CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val)
-{
- return ((val) << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK;
-}
-
-#define REG_CP_WAIT_MEM_GTE_2 0x00000002
-#define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK 0xffffffff
-#define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT 0
-static inline uint32_t CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val)
-{
- return ((val) << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK;
-}
-
-#define REG_CP_WAIT_MEM_GTE_3 0x00000003
-#define CP_WAIT_MEM_GTE_3_REF__MASK 0xffffffff
-#define CP_WAIT_MEM_GTE_3_REF__SHIFT 0
-static inline uint32_t CP_WAIT_MEM_GTE_3_REF(uint32_t val)
-{
- return ((val) << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK;
-}
-
-#define REG_CP_WAIT_REG_MEM_0 0x00000000
-#define CP_WAIT_REG_MEM_0_FUNCTION__MASK 0x00000007
-#define CP_WAIT_REG_MEM_0_FUNCTION__SHIFT 0
-static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val)
-{
- return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK;
-}
-#define CP_WAIT_REG_MEM_0_SIGNED_COMPARE 0x00000008
-#define CP_WAIT_REG_MEM_0_POLL__MASK 0x00000030
-#define CP_WAIT_REG_MEM_0_POLL__SHIFT 4
-static inline uint32_t CP_WAIT_REG_MEM_0_POLL(enum poll_memory_type val)
-{
- return ((val) << CP_WAIT_REG_MEM_0_POLL__SHIFT) & CP_WAIT_REG_MEM_0_POLL__MASK;
-}
-#define CP_WAIT_REG_MEM_0_WRITE_MEMORY 0x00000100
-
-#define REG_CP_WAIT_REG_MEM_1 0x00000001
-#define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK 0xffffffff
-#define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT 0
-static inline uint32_t CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val)
-{
- return ((val) << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK;
-}
-
-#define REG_CP_WAIT_REG_MEM_2 0x00000002
-#define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK 0xffffffff
-#define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT 0
-static inline uint32_t CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val)
-{
- return ((val) << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK;
-}
-
-#define REG_CP_WAIT_REG_MEM_3 0x00000003
-#define CP_WAIT_REG_MEM_3_REF__MASK 0xffffffff
-#define CP_WAIT_REG_MEM_3_REF__SHIFT 0
-static inline uint32_t CP_WAIT_REG_MEM_3_REF(uint32_t val)
-{
- return ((val) << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK;
-}
-
-#define REG_CP_WAIT_REG_MEM_4 0x00000004
-#define CP_WAIT_REG_MEM_4_MASK__MASK 0xffffffff
-#define CP_WAIT_REG_MEM_4_MASK__SHIFT 0
-static inline uint32_t CP_WAIT_REG_MEM_4_MASK(uint32_t val)
-{
- return ((val) << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK;
-}
-
-#define REG_CP_WAIT_REG_MEM_5 0x00000005
-#define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK 0xffffffff
-#define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT 0
-static inline uint32_t CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val)
-{
- return ((val) << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK;
-}
-
-#define REG_CP_WAIT_TWO_REGS_0 0x00000000
-#define CP_WAIT_TWO_REGS_0_REG0__MASK 0x0003ffff
-#define CP_WAIT_TWO_REGS_0_REG0__SHIFT 0
-static inline uint32_t CP_WAIT_TWO_REGS_0_REG0(uint32_t val)
-{
- return ((val) << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK;
-}
-
-#define REG_CP_WAIT_TWO_REGS_1 0x00000001
-#define CP_WAIT_TWO_REGS_1_REG1__MASK 0x0003ffff
-#define CP_WAIT_TWO_REGS_1_REG1__SHIFT 0
-static inline uint32_t CP_WAIT_TWO_REGS_1_REG1(uint32_t val)
-{
- return ((val) << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK;
-}
-
-#define REG_CP_WAIT_TWO_REGS_2 0x00000002
-#define CP_WAIT_TWO_REGS_2_REF__MASK 0xffffffff
-#define CP_WAIT_TWO_REGS_2_REF__SHIFT 0
-static inline uint32_t CP_WAIT_TWO_REGS_2_REF(uint32_t val)
-{
- return ((val) << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK;
-}
-
-#define REG_CP_DISPATCH_COMPUTE_0 0x00000000
-
-#define REG_CP_DISPATCH_COMPUTE_1 0x00000001
-#define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff
-#define CP_DISPATCH_COMPUTE_1_X__SHIFT 0
-static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
-{
- return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
-}
-
-#define REG_CP_DISPATCH_COMPUTE_2 0x00000002
-#define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff
-#define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0
-static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
-{
- return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
-}
-
-#define REG_CP_DISPATCH_COMPUTE_3 0x00000003
-#define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff
-#define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0
-static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
-{
- return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
-}
-
-#define REG_CP_SET_RENDER_MODE_0 0x00000000
-#define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff
-#define CP_SET_RENDER_MODE_0_MODE__SHIFT 0
-static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
-{
- return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
-}
-
-#define REG_CP_SET_RENDER_MODE_1 0x00000001
-#define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff
-#define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0
-static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
-{
- return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
-}
-
-#define REG_CP_SET_RENDER_MODE_2 0x00000002
-#define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff
-#define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0
-static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
-{
- return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
-}
-
-#define REG_CP_SET_RENDER_MODE_3 0x00000003
-#define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008
-#define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
-
-#define REG_CP_SET_RENDER_MODE_4 0x00000004
-
-#define REG_CP_SET_RENDER_MODE_5 0x00000005
-#define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff
-#define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0
-static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
-{
- return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
-}
-
-#define REG_CP_SET_RENDER_MODE_6 0x00000006
-#define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff
-#define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0
-static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
-{
- return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
-}
-
-#define REG_CP_SET_RENDER_MODE_7 0x00000007
-#define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff
-#define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0
-static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
-{
- return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
-}
-
-#define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000
-#define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff
-#define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0
-static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
-{
- return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
-}
-
-#define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001
-#define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff
-#define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0
-static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
-{
- return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
-}
-
-#define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
-
-#define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
-
-#define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
-#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK 0xffffffff
-#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT 0
-static inline uint32_t CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(uint32_t val)
-{
- return ((val) << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK;
-}
-
-#define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
-#define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
-#define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0
-static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
-{
- return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
-}
-
-#define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006
-#define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff
-#define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0
-static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
-{
- return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
-}
-
-#define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007
-
-#define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
-
-#define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
-#define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff
-#define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0
-static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
-{
- return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
-}
-
-#define REG_CP_PERFCOUNTER_ACTION_2 0x00000002
-#define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff
-#define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0
-static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
-{
- return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
-}
-
-#define REG_CP_EVENT_WRITE_0 0x00000000
-#define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff
-#define CP_EVENT_WRITE_0_EVENT__SHIFT 0
-static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
-{
- return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
-}
-#define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000
-#define CP_EVENT_WRITE_0_IRQ 0x80000000
-
-#define REG_CP_EVENT_WRITE_1 0x00000001
-#define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
-#define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0
-static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
-{
- return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
-}
-
-#define REG_CP_EVENT_WRITE_2 0x00000002
-#define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff
-#define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0
-static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
-{
- return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
-}
-
-#define REG_CP_EVENT_WRITE_3 0x00000003
-
-#define REG_CP_EVENT_WRITE7_0 0x00000000
-#define CP_EVENT_WRITE7_0_EVENT__MASK 0x000000ff
-#define CP_EVENT_WRITE7_0_EVENT__SHIFT 0
-static inline uint32_t CP_EVENT_WRITE7_0_EVENT(enum vgt_event_type val)
-{
- return ((val) << CP_EVENT_WRITE7_0_EVENT__SHIFT) & CP_EVENT_WRITE7_0_EVENT__MASK;
-}
-#define CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT 0x00001000
-#define CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET 0x00002000
-#define CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT_DIFF 0x00004000
-#define CP_EVENT_WRITE7_0_INC_BV_COUNT 0x00010000
-#define CP_EVENT_WRITE7_0_INC_BR_COUNT 0x00020000
-#define CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE 0x00040000
-#define CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE 0x00080000
-#define CP_EVENT_WRITE7_0_WRITE_SRC__MASK 0x00700000
-#define CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT 20
-static inline uint32_t CP_EVENT_WRITE7_0_WRITE_SRC(enum event_write_src val)
-{
- return ((val) << CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT) & CP_EVENT_WRITE7_0_WRITE_SRC__MASK;
-}
-#define CP_EVENT_WRITE7_0_WRITE_DST__MASK 0x01000000
-#define CP_EVENT_WRITE7_0_WRITE_DST__SHIFT 24
-static inline uint32_t CP_EVENT_WRITE7_0_WRITE_DST(enum event_write_dst val)
-{
- return ((val) << CP_EVENT_WRITE7_0_WRITE_DST__SHIFT) & CP_EVENT_WRITE7_0_WRITE_DST__MASK;
-}
-#define CP_EVENT_WRITE7_0_WRITE_ENABLED 0x08000000
-
-#define REG_EV_DST_RAM_CP_EVENT_WRITE7_1 0x00000001
-#define EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK 0xffffffff
-#define EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT 0
-static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO(uint32_t val)
-{
- return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK;
-}
-
-#define REG_EV_DST_RAM_CP_EVENT_WRITE7_2 0x00000002
-#define EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK 0xffffffff
-#define EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT 0
-static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI(uint32_t val)
-{
- return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK;
-}
-
-#define REG_EV_DST_RAM_CP_EVENT_WRITE7_3 0x00000003
-#define EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK 0xffffffff
-#define EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT 0
-static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0(uint32_t val)
-{
- return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK;
-}
-
-#define REG_EV_DST_RAM_CP_EVENT_WRITE7_4 0x00000004
-#define EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK 0xffffffff
-#define EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT 0
-static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1(uint32_t val)
-{
- return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK;
-}
-
-#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1 0x00000001
-#define EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK 0xffffffff
-#define EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT 0
-static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0(uint32_t val)
-{
- return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK;
-}
-
-#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3 0x00000003
-#define EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK 0xffffffff
-#define EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT 0
-static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0(uint32_t val)
-{
- return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK;
-}
-
-#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4 0x00000004
-#define EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK 0xffffffff
-#define EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT 0
-static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1(uint32_t val)
-{
- return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK;
-}
-
-#define REG_CP_BLIT_0 0x00000000
-#define CP_BLIT_0_OP__MASK 0x0000000f
-#define CP_BLIT_0_OP__SHIFT 0
-static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
-{
- return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
-}
-
-#define REG_CP_BLIT_1 0x00000001
-#define CP_BLIT_1_SRC_X1__MASK 0x00003fff
-#define CP_BLIT_1_SRC_X1__SHIFT 0
-static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
-{
- return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
-}
-#define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000
-#define CP_BLIT_1_SRC_Y1__SHIFT 16
-static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
-{
- return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
-}
-
-#define REG_CP_BLIT_2 0x00000002
-#define CP_BLIT_2_SRC_X2__MASK 0x00003fff
-#define CP_BLIT_2_SRC_X2__SHIFT 0
-static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
-{
- return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
-}
-#define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000
-#define CP_BLIT_2_SRC_Y2__SHIFT 16
-static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
-{
- return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
-}
-
-#define REG_CP_BLIT_3 0x00000003
-#define CP_BLIT_3_DST_X1__MASK 0x00003fff
-#define CP_BLIT_3_DST_X1__SHIFT 0
-static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
-{
- return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
-}
-#define CP_BLIT_3_DST_Y1__MASK 0x3fff0000
-#define CP_BLIT_3_DST_Y1__SHIFT 16
-static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
-{
- return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
-}
-
-#define REG_CP_BLIT_4 0x00000004
-#define CP_BLIT_4_DST_X2__MASK 0x00003fff
-#define CP_BLIT_4_DST_X2__SHIFT 0
-static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
-{
- return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
-}
-#define CP_BLIT_4_DST_Y2__MASK 0x3fff0000
-#define CP_BLIT_4_DST_Y2__SHIFT 16
-static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
-{
- return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
-}
-
-#define REG_CP_EXEC_CS_0 0x00000000
-
-#define REG_CP_EXEC_CS_1 0x00000001
-#define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff
-#define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0
-static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
-{
- return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
-}
-
-#define REG_CP_EXEC_CS_2 0x00000002
-#define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff
-#define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0
-static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
-{
- return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
-}
-
-#define REG_CP_EXEC_CS_3 0x00000003
-#define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff
-#define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0
-static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
-{
- return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
-}
-
-#define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000
-
-#define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001
-#define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff
-#define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0
-static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)
-{
- return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;
-}
-
-#define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002
-#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc
-#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2
-static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)
-{
- return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK;
-}
-#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000
-#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12
-static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)
-{
- return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK;
-}
-#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000
-#define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22
-static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)
-{
- return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK;
-}
-
-#define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001
-#define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff
-#define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0
-static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
-{
- return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK;
-}
-
-#define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002
-#define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff
-#define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0
-static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
-{
- return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK;
-}
-
-#define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003
-#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc
-#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2
-static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
-{
- return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK;
-}
-#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000
-#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12
-static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
-{
- return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK;
-}
-#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000
-#define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22
-static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
-{
- return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
-}
-
-#define REG_A6XX_CP_SET_MARKER_0 0x00000000
-#define A6XX_CP_SET_MARKER_0_MODE__MASK 0x000001ff
-#define A6XX_CP_SET_MARKER_0_MODE__SHIFT 0
-static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_marker val)
-{
- return ((val) << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK;
-}
-#define A6XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f
-#define A6XX_CP_SET_MARKER_0_MARKER__SHIFT 0
-static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_marker val)
-{
- return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK;
-}
-
-#define REG_A6XX_CP_SET_PSEUDO_REG_(i0) (0x00000000 + 0x3*(i0))
-
-static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
-#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x000007ff
-#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0
-static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
-{
- return ((val) << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK;
-}
-
-static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
-#define A6XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff
-#define A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0
-static inline uint32_t A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)
-{
- return ((val) << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK;
-}
-
-static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
-#define A6XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff
-#define A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0
-static inline uint32_t A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)
-{
- return ((val) << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK;
-}
-
-#define REG_A6XX_CP_REG_TEST_0 0x00000000
-#define A6XX_CP_REG_TEST_0_REG__MASK 0x0003ffff
-#define A6XX_CP_REG_TEST_0_REG__SHIFT 0
-static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val)
-{
- return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK;
-}
-#define A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK 0x0003ffff
-#define A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT 0
-static inline uint32_t A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET(uint32_t val)
-{
- return ((val) << A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT) & A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK;
-}
-#define A6XX_CP_REG_TEST_0_SOURCE__MASK 0x00040000
-#define A6XX_CP_REG_TEST_0_SOURCE__SHIFT 18
-static inline uint32_t A6XX_CP_REG_TEST_0_SOURCE(enum source_type val)
-{
- return ((val) << A6XX_CP_REG_TEST_0_SOURCE__SHIFT) & A6XX_CP_REG_TEST_0_SOURCE__MASK;
-}
-#define A6XX_CP_REG_TEST_0_BIT__MASK 0x01f00000
-#define A6XX_CP_REG_TEST_0_BIT__SHIFT 20
-static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val)
-{
- return ((val) << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK;
-}
-#define A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME 0x02000000
-#define A6XX_CP_REG_TEST_0_PRED_BIT__MASK 0x7c000000
-#define A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT 26
-static inline uint32_t A6XX_CP_REG_TEST_0_PRED_BIT(uint32_t val)
-{
- return ((val) << A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT) & A6XX_CP_REG_TEST_0_PRED_BIT__MASK;
-}
-#define A6XX_CP_REG_TEST_0_PRED_UPDATE 0x80000000
-
-#define REG_A6XX_CP_REG_TEST_PRED_MASK 0x00000001
-
-#define REG_A6XX_CP_REG_TEST_PRED_VAL 0x00000002
-
-#define REG_CP_COND_REG_EXEC_0 0x00000000
-#define CP_COND_REG_EXEC_0_REG0__MASK 0x0003ffff
-#define CP_COND_REG_EXEC_0_REG0__SHIFT 0
-static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val)
-{
- return ((val) << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK;
-}
-#define CP_COND_REG_EXEC_0_PRED_BIT__MASK 0x007c0000
-#define CP_COND_REG_EXEC_0_PRED_BIT__SHIFT 18
-static inline uint32_t CP_COND_REG_EXEC_0_PRED_BIT(uint32_t val)
-{
- return ((val) << CP_COND_REG_EXEC_0_PRED_BIT__SHIFT) & CP_COND_REG_EXEC_0_PRED_BIT__MASK;
-}
-#define CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME 0x00800000
-#define CP_COND_REG_EXEC_0_ONCHIP_MEM 0x01000000
-#define CP_COND_REG_EXEC_0_BINNING 0x02000000
-#define CP_COND_REG_EXEC_0_GMEM 0x04000000
-#define CP_COND_REG_EXEC_0_SYSMEM 0x08000000
-#define CP_COND_REG_EXEC_0_BV 0x02000000
-#define CP_COND_REG_EXEC_0_BR 0x04000000
-#define CP_COND_REG_EXEC_0_LPAC 0x08000000
-#define CP_COND_REG_EXEC_0_MODE__MASK 0xf0000000
-#define CP_COND_REG_EXEC_0_MODE__SHIFT 28
-static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val)
-{
- return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK;
-}
-
-#define REG_PRED_TEST_CP_COND_REG_EXEC_1 0x00000001
-#define PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff
-#define PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0
-static inline uint32_t PRED_TEST_CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
-{
- return ((val) << PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK;
-}
-
-#define REG_REG_COMPARE_CP_COND_REG_EXEC_1 0x00000001
-#define REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK 0x0003ffff
-#define REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT 0
-static inline uint32_t REG_COMPARE_CP_COND_REG_EXEC_1_REG1(uint32_t val)
-{
- return ((val) << REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT) & REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK;
-}
-#define REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM 0x01000000
-
-#define REG_RENDER_MODE_CP_COND_REG_EXEC_1 0x00000001
-#define RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff
-#define RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0
-static inline uint32_t RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
-{
- return ((val) << RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK;
-}
-
-#define REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1 0x00000001
-#define REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK 0xffffffff
-#define REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT 0
-static inline uint32_t REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM(uint32_t val)
-{
- return ((val) << REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT) & REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK;
-}
-
-#define REG_THREAD_MODE_CP_COND_REG_EXEC_1 0x00000001
-#define THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff
-#define THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0
-static inline uint32_t THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS(uint32_t val)
-{
- return ((val) << THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK;
-}
-
-#define REG_CP_COND_REG_EXEC_2 0x00000002
-#define CP_COND_REG_EXEC_2_DWORDS__MASK 0x00ffffff
-#define CP_COND_REG_EXEC_2_DWORDS__SHIFT 0
-static inline uint32_t CP_COND_REG_EXEC_2_DWORDS(uint32_t val)
-{
- return ((val) << CP_COND_REG_EXEC_2_DWORDS__SHIFT) & CP_COND_REG_EXEC_2_DWORDS__MASK;
-}
-
-#define REG_CP_COND_EXEC_0 0x00000000
-#define CP_COND_EXEC_0_ADDR0_LO__MASK 0xffffffff
-#define CP_COND_EXEC_0_ADDR0_LO__SHIFT 0
-static inline uint32_t CP_COND_EXEC_0_ADDR0_LO(uint32_t val)
-{
- return ((val) << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK;
-}
-
-#define REG_CP_COND_EXEC_1 0x00000001
-#define CP_COND_EXEC_1_ADDR0_HI__MASK 0xffffffff
-#define CP_COND_EXEC_1_ADDR0_HI__SHIFT 0
-static inline uint32_t CP_COND_EXEC_1_ADDR0_HI(uint32_t val)
-{
- return ((val) << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK;
-}
-
-#define REG_CP_COND_EXEC_2 0x00000002
-#define CP_COND_EXEC_2_ADDR1_LO__MASK 0xffffffff
-#define CP_COND_EXEC_2_ADDR1_LO__SHIFT 0
-static inline uint32_t CP_COND_EXEC_2_ADDR1_LO(uint32_t val)
-{
- return ((val) << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK;
-}
-
-#define REG_CP_COND_EXEC_3 0x00000003
-#define CP_COND_EXEC_3_ADDR1_HI__MASK 0xffffffff
-#define CP_COND_EXEC_3_ADDR1_HI__SHIFT 0
-static inline uint32_t CP_COND_EXEC_3_ADDR1_HI(uint32_t val)
-{
- return ((val) << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK;
-}
-
-#define REG_CP_COND_EXEC_4 0x00000004
-#define CP_COND_EXEC_4_REF__MASK 0xffffffff
-#define CP_COND_EXEC_4_REF__SHIFT 0
-static inline uint32_t CP_COND_EXEC_4_REF(uint32_t val)
-{
- return ((val) << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK;
-}
-
-#define REG_CP_COND_EXEC_5 0x00000005
-#define CP_COND_EXEC_5_DWORDS__MASK 0xffffffff
-#define CP_COND_EXEC_5_DWORDS__SHIFT 0
-static inline uint32_t CP_COND_EXEC_5_DWORDS(uint32_t val)
-{
- return ((val) << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK;
-}
-
-#define REG_CP_SET_CTXSWITCH_IB_0 0x00000000
-#define CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK 0xffffffff
-#define CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT 0
-static inline uint32_t CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val)
-{
- return ((val) << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK;
-}
-
-#define REG_CP_SET_CTXSWITCH_IB_1 0x00000001
-#define CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK 0xffffffff
-#define CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT 0
-static inline uint32_t CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val)
-{
- return ((val) << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK;
-}
-
-#define REG_CP_SET_CTXSWITCH_IB_2 0x00000002
-#define CP_SET_CTXSWITCH_IB_2_DWORDS__MASK 0x000fffff
-#define CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT 0
-static inline uint32_t CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val)
-{
- return ((val) << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK;
-}
-#define CP_SET_CTXSWITCH_IB_2_TYPE__MASK 0x00300000
-#define CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT 20
-static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val)
-{
- return ((val) << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK;
-}
-
-#define REG_CP_REG_WRITE_0 0x00000000
-#define CP_REG_WRITE_0_TRACKER__MASK 0x0000000f
-#define CP_REG_WRITE_0_TRACKER__SHIFT 0
-static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val)
-{
- return ((val) << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK;
-}
-
-#define REG_CP_REG_WRITE_1 0x00000001
-
-#define REG_CP_REG_WRITE_2 0x00000002
-
-#define REG_CP_SMMU_TABLE_UPDATE_0 0x00000000
-#define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK 0xffffffff
-#define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT 0
-static inline uint32_t CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val)
-{
- return ((val) << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK;
-}
-
-#define REG_CP_SMMU_TABLE_UPDATE_1 0x00000001
-#define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK 0x0000ffff
-#define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT 0
-static inline uint32_t CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val)
-{
- return ((val) << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK;
-}
-#define CP_SMMU_TABLE_UPDATE_1_ASID__MASK 0xffff0000
-#define CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT 16
-static inline uint32_t CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val)
-{
- return ((val) << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK;
-}
-
-#define REG_CP_SMMU_TABLE_UPDATE_2 0x00000002
-#define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK 0xffffffff
-#define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT 0
-static inline uint32_t CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val)
-{
- return ((val) << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK;
-}
-
-#define REG_CP_SMMU_TABLE_UPDATE_3 0x00000003
-#define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK 0xffffffff
-#define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT 0
-static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val)
-{
- return ((val) << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK;
-}
-
-#define REG_CP_START_BIN_BIN_COUNT 0x00000000
-
-#define REG_CP_START_BIN_PREFIX_ADDR 0x00000001
-
-#define REG_CP_START_BIN_PREFIX_DWORDS 0x00000003
-
-#define REG_CP_START_BIN_BODY_DWORDS 0x00000004
-
-#define REG_CP_WAIT_TIMESTAMP_0 0x00000000
-#define CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK 0x00000003
-#define CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT 0
-static inline uint32_t CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC(enum ts_wait_value_src val)
-{
- return ((val) << CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK;
-}
-#define CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK 0x00000010
-#define CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT 4
-static inline uint32_t CP_WAIT_TIMESTAMP_0_WAIT_DST(enum ts_wait_type val)
-{
- return ((val) << CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK;
-}
-
-#define REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR 0x00000001
-
-#define REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0 0x00000001
-
-#define REG_CP_WAIT_TIMESTAMP_SRC_0 0x00000003
-
-#define REG_CP_WAIT_TIMESTAMP_SRC_1 0x00000004
-
-#define REG_CP_BV_BR_COUNT_OPS_0 0x00000000
-#define CP_BV_BR_COUNT_OPS_0_OP__MASK 0x0000000f
-#define CP_BV_BR_COUNT_OPS_0_OP__SHIFT 0
-static inline uint32_t CP_BV_BR_COUNT_OPS_0_OP(enum pipe_count_op val)
-{
- return ((val) << CP_BV_BR_COUNT_OPS_0_OP__SHIFT) & CP_BV_BR_COUNT_OPS_0_OP__MASK;
-}
-
-#define REG_CP_BV_BR_COUNT_OPS_1 0x00000001
-#define CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK 0x0000ffff
-#define CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT 0
-static inline uint32_t CP_BV_BR_COUNT_OPS_1_BR_OFFSET(uint32_t val)
-{
- return ((val) << CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT) & CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK;
-}
-
-#define REG_CP_MODIFY_TIMESTAMP_0 0x00000000
-#define CP_MODIFY_TIMESTAMP_0_ADD__MASK 0x000000ff
-#define CP_MODIFY_TIMESTAMP_0_ADD__SHIFT 0
-static inline uint32_t CP_MODIFY_TIMESTAMP_0_ADD(uint32_t val)
-{
- return ((val) << CP_MODIFY_TIMESTAMP_0_ADD__SHIFT) & CP_MODIFY_TIMESTAMP_0_ADD__MASK;
-}
-#define CP_MODIFY_TIMESTAMP_0_OP__MASK 0xf0000000
-#define CP_MODIFY_TIMESTAMP_0_OP__SHIFT 28
-static inline uint32_t CP_MODIFY_TIMESTAMP_0_OP(enum timestamp_op val)
-{
- return ((val) << CP_MODIFY_TIMESTAMP_0_OP__SHIFT) & CP_MODIFY_TIMESTAMP_0_OP__MASK;
-}
-
-#define REG_CP_MEM_TO_SCRATCH_MEM_0 0x00000000
-#define CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK 0x0000003f
-#define CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT 0
-static inline uint32_t CP_MEM_TO_SCRATCH_MEM_0_CNT(uint32_t val)
-{
- return ((val) << CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT) & CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK;
-}
-
-#define REG_CP_MEM_TO_SCRATCH_MEM_1 0x00000001
-#define CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK 0x0000003f
-#define CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT 0
-static inline uint32_t CP_MEM_TO_SCRATCH_MEM_1_OFFSET(uint32_t val)
-{
- return ((val) << CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT) & CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK;
-}
-
-#define REG_CP_MEM_TO_SCRATCH_MEM_2 0x00000002
-#define CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK 0xffffffff
-#define CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT 0
-static inline uint32_t CP_MEM_TO_SCRATCH_MEM_2_SRC(uint32_t val)
-{
- return ((val) << CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT) & CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK;
-}
-
-#define REG_CP_MEM_TO_SCRATCH_MEM_3 0x00000003
-#define CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK 0xffffffff
-#define CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT 0
-static inline uint32_t CP_MEM_TO_SCRATCH_MEM_3_SRC_HI(uint32_t val)
-{
- return ((val) << CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT) & CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK;
-}
-
-#define REG_CP_THREAD_CONTROL_0 0x00000000
-#define CP_THREAD_CONTROL_0_THREAD__MASK 0x00000003
-#define CP_THREAD_CONTROL_0_THREAD__SHIFT 0
-static inline uint32_t CP_THREAD_CONTROL_0_THREAD(enum cp_thread val)
-{
- return ((val) << CP_THREAD_CONTROL_0_THREAD__SHIFT) & CP_THREAD_CONTROL_0_THREAD__MASK;
-}
-#define CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE 0x08000000
-#define CP_THREAD_CONTROL_0_SYNC_THREADS 0x80000000
-
-#define REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE 0x00000000
-
-#define REG_CP_FIXED_STRIDE_DRAW_TABLE_2 0x00000002
-#define CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK 0x00000fff
-#define CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT 0
-static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE(uint32_t val)
-{
- return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK;
-}
-#define CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK 0xfff00000
-#define CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT 20
-static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE(uint32_t val)
-{
- return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK;
-}
-
-#define REG_CP_FIXED_STRIDE_DRAW_TABLE_3 0x00000003
-#define CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK 0xffffffff
-#define CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT 0
-static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT(uint32_t val)
-{
- return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK;
-}
-
-#define REG_CP_RESET_CONTEXT_STATE_0 0x00000000
-#define CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS 0x00000001
-#define CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE 0x00000002
-#define CP_RESET_CONTEXT_STATE_0_CLEAR_GLOBAL_LOCAL_TS 0x00000004
-
-#ifdef __cplusplus
-#endif
-
-#endif /* ADRENO_PM4_XML */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 88c2e51ab166..9f2164782844 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -320,7 +320,7 @@ static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
}
static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
- struct dpu_plane_state *pstate, struct dpu_format *format)
+ struct dpu_plane_state *pstate, const struct msm_format *format)
{
struct dpu_hw_mixer *lm = mixer->hw_lm;
uint32_t blend_op;
@@ -363,7 +363,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
fg_alpha, bg_alpha, blend_op);
DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
- &format->base.pixel_format, format->alpha_enable, blend_op);
+ &format->pixel_format, format->alpha_enable, blend_op);
}
static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
@@ -395,7 +395,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
struct dpu_crtc_mixer *mixer,
u32 num_mixers,
enum dpu_stage stage,
- struct dpu_format *format,
+ const struct msm_format *format,
uint64_t modifier,
struct dpu_sw_pipe *pipe,
unsigned int stage_idx,
@@ -412,7 +412,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
state, to_dpu_plane_state(state), stage_idx,
- format->base.pixel_format,
+ format->pixel_format,
modifier);
DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n",
@@ -440,7 +440,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
struct drm_plane_state *state;
struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
struct dpu_plane_state *pstate = NULL;
- struct dpu_format *format;
+ const struct msm_format *format;
struct dpu_hw_ctl *ctl = mixer->lm_ctl;
uint32_t lm_idx;
@@ -459,7 +459,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
pstate = to_dpu_plane_state(state);
fb = state->fb;
- format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
+ format = msm_framebuffer_format(pstate->base.fb);
if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
bg_alpha_enable = true;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 9a14d2232e4a..119f3ea50a7c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -675,7 +675,7 @@ static int dpu_encoder_virt_atomic_check(
if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) {
fb = conn_state->writeback_job->fb;
- if (fb && DPU_FORMAT_IS_YUV(to_dpu_format(msm_framebuffer_format(fb))))
+ if (fb && MSM_FORMAT_IS_YUV(msm_framebuffer_format(fb)))
topology.needs_cdm = true;
} else if (disp_info->intf_type == INTF_DP) {
if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], adj_mode))
@@ -2184,7 +2184,7 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
}
void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
- const struct dpu_format *dpu_fmt,
+ const struct msm_format *dpu_fmt,
u32 output_type)
{
struct dpu_hw_cdm *hw_cdm;
@@ -2202,9 +2202,9 @@ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
if (!hw_cdm)
return;
- if (!DPU_FORMAT_IS_YUV(dpu_fmt)) {
- DPU_DEBUG("[enc:%d] cdm_disable fmt:%x\n", DRMID(phys_enc->parent),
- dpu_fmt->base.pixel_format);
+ if (!MSM_FORMAT_IS_YUV(dpu_fmt)) {
+ DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent),
+ &dpu_fmt->pixel_format);
if (hw_cdm->ops.bind_pingpong_blk)
hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE);
@@ -2217,25 +2217,25 @@ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
cdm_cfg->output_height = phys_enc->cached_mode.vdisplay;
cdm_cfg->output_fmt = dpu_fmt;
cdm_cfg->output_type = output_type;
- cdm_cfg->output_bit_depth = DPU_FORMAT_IS_DX(dpu_fmt) ?
+ cdm_cfg->output_bit_depth = MSM_FORMAT_IS_DX(dpu_fmt) ?
CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l;
/* enable 10 bit logic */
switch (cdm_cfg->output_fmt->chroma_sample) {
- case DPU_CHROMA_RGB:
+ case CHROMA_FULL:
cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
break;
- case DPU_CHROMA_H2V1:
+ case CHROMA_H2V1:
cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
break;
- case DPU_CHROMA_420:
+ case CHROMA_420:
cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
break;
- case DPU_CHROMA_H1V2:
+ case CHROMA_H1V2:
default:
DPU_ERROR("[enc:%d] unsupported chroma sampling type\n",
DRMID(phys_enc->parent));
@@ -2244,9 +2244,9 @@ void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
break;
}
- DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n",
+ DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%p4cc,%d,%d,%d,%d]\n",
DRMID(phys_enc->parent), cdm_cfg->output_width,
- cdm_cfg->output_height, cdm_cfg->output_fmt->base.pixel_format,
+ cdm_cfg->output_height, &cdm_cfg->output_fmt->pixel_format,
cdm_cfg->output_type, cdm_cfg->output_bit_depth,
cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 98d1b64a43e8..002e89cc1705 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -393,7 +393,7 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc);
* @output_type: HDMI/WB
*/
void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc,
- const struct dpu_format *dpu_fmt,
+ const struct msm_format *dpu_fmt,
u32 output_type);
/**
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index fc1d5736d7fc..489be1c0c704 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -448,9 +448,6 @@ static void dpu_encoder_phys_cmd_enable_helper(
_dpu_encoder_phys_cmd_pingpong_config(phys_enc);
- if (!dpu_encoder_phys_cmd_is_master(phys_enc))
- return;
-
ctl = phys_enc->hw_ctl;
ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index d9e7dbf0499c..ef69c2f408c3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -235,7 +235,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
{
struct drm_display_mode mode;
struct dpu_hw_intf_timing_params timing_params = { 0 };
- const struct dpu_format *fmt = NULL;
+ const struct msm_format *fmt = NULL;
u32 fmt_fourcc;
unsigned long lock_flags;
struct dpu_hw_intf_cfg intf_cfg = { 0 };
@@ -274,7 +274,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params);
- fmt = dpu_get_dpu_format(fmt_fourcc);
+ fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
if (phys_enc->hw_cdm)
@@ -409,12 +409,12 @@ end:
static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc)
{
struct dpu_hw_ctl *ctl;
- const struct dpu_format *fmt;
+ const struct msm_format *fmt;
u32 fmt_fourcc;
ctl = phys_enc->hw_ctl;
fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc);
- fmt = dpu_get_dpu_format(fmt_fourcc);
+ fmt = mdp_get_format(&phys_enc->dpu_kms->base, fmt_fourcc, 0);
DPU_DEBUG_VIDENC(phys_enc, "\n");
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 1924a2b28e53..d3ea91c1d7d2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -322,11 +322,11 @@ static void dpu_encoder_phys_wb_setup(
struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
struct drm_writeback_job *wb_job;
const struct msm_format *format;
- const struct dpu_format *dpu_fmt;
+ const struct msm_format *dpu_fmt;
wb_job = wb_enc->wb_job;
format = msm_framebuffer_format(wb_enc->wb_job->fb);
- dpu_fmt = dpu_get_dpu_format_ext(format->pixel_format, wb_job->fb->modifier);
+ dpu_fmt = mdp_get_format(&phys_enc->dpu_kms->base, format->pixel_format, wb_job->fb->modifier);
DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n",
hw_wb->idx - WB_0, mode.name,
@@ -576,11 +576,11 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc
format = msm_framebuffer_format(job->fb);
- wb_cfg->dest.format = dpu_get_dpu_format_ext(
- format->pixel_format, job->fb->modifier);
+ wb_cfg->dest.format = mdp_get_format(&phys_enc->dpu_kms->base,
+ format->pixel_format, job->fb->modifier);
if (!wb_cfg->dest.format) {
/* this error should be detected during atomic_check */
- DPU_ERROR("failed to get format %x\n", format->pixel_format);
+ DPU_ERROR("failed to get format %p4cc\n", &format->pixel_format);
return;
}
@@ -594,7 +594,7 @@ static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc
wb_cfg->dest.height = job->fb->height;
wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
- if ((wb_cfg->dest.format->fetch_planes == DPU_PLANE_PLANAR) &&
+ if ((wb_cfg->dest.format->fetch_type == MDP_PLANE_PLANAR) &&
(wb_cfg->dest.format->element[0] == C1_B_Cb))
swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
index e366ab134249..6b1e9a617da3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
@@ -11,179 +11,12 @@
#include "dpu_kms.h"
#include "dpu_formats.h"
-#define DPU_UBWC_META_MACRO_W_H 16
-#define DPU_UBWC_META_BLOCK_SIZE 256
#define DPU_UBWC_PLANE_SIZE_ALIGNMENT 4096
-#define DPU_TILE_HEIGHT_DEFAULT 1
-#define DPU_TILE_HEIGHT_TILED 4
-#define DPU_TILE_HEIGHT_UBWC 4
-#define DPU_TILE_HEIGHT_NV12 8
-
#define DPU_MAX_IMG_WIDTH 0x3FFF
#define DPU_MAX_IMG_HEIGHT 0x3FFF
/*
- * DPU supported format packing, bpp, and other format
- * information.
- * DPU currently only supports interleaved RGB formats
- * UBWC support for a pixel format is indicated by the flag,
- * there is additional meta data plane for such formats
- */
-
-#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha, \
-bp, flg, fm, np) \
-{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_INTERLEAVED, \
- .alpha_enable = alpha, \
- .element = { (e0), (e1), (e2), (e3) }, \
- .bits = { g, b, r, a }, \
- .chroma_sample = DPU_CHROMA_RGB, \
- .unpack_align_msb = 0, \
- .unpack_tight = 1, \
- .unpack_count = uc, \
- .bpp = bp, \
- .fetch_mode = fm, \
- .flag = {(flg)}, \
- .num_planes = np, \
- .tile_height = DPU_TILE_HEIGHT_DEFAULT \
-}
-
-#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \
-alpha, bp, flg, fm, np, th) \
-{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_INTERLEAVED, \
- .alpha_enable = alpha, \
- .element = { (e0), (e1), (e2), (e3) }, \
- .bits = { g, b, r, a }, \
- .chroma_sample = DPU_CHROMA_RGB, \
- .unpack_align_msb = 0, \
- .unpack_tight = 1, \
- .unpack_count = uc, \
- .bpp = bp, \
- .fetch_mode = fm, \
- .flag = {(flg)}, \
- .num_planes = np, \
- .tile_height = th \
-}
-
-
-#define INTERLEAVED_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, e3, \
-alpha, chroma, count, bp, flg, fm, np) \
-{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_INTERLEAVED, \
- .alpha_enable = alpha, \
- .element = { (e0), (e1), (e2), (e3)}, \
- .bits = { g, b, r, a }, \
- .chroma_sample = chroma, \
- .unpack_align_msb = 0, \
- .unpack_tight = 1, \
- .unpack_count = count, \
- .bpp = bp, \
- .fetch_mode = fm, \
- .flag = {(flg)}, \
- .num_planes = np, \
- .tile_height = DPU_TILE_HEIGHT_DEFAULT \
-}
-
-#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
-{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = false, \
- .element = { (e0), (e1), 0, 0 }, \
- .bits = { g, b, r, a }, \
- .chroma_sample = chroma, \
- .unpack_align_msb = 0, \
- .unpack_tight = 1, \
- .unpack_count = 2, \
- .bpp = 2, \
- .fetch_mode = fm, \
- .flag = {(flg)}, \
- .num_planes = np, \
- .tile_height = DPU_TILE_HEIGHT_DEFAULT \
-}
-
-#define PSEUDO_YUV_FMT_TILED(fmt, a, r, g, b, e0, e1, chroma, \
-flg, fm, np, th) \
-{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = false, \
- .element = { (e0), (e1), 0, 0 }, \
- .bits = { g, b, r, a }, \
- .chroma_sample = chroma, \
- .unpack_align_msb = 0, \
- .unpack_tight = 1, \
- .unpack_count = 2, \
- .bpp = 2, \
- .fetch_mode = fm, \
- .flag = {(flg)}, \
- .num_planes = np, \
- .tile_height = th \
-}
-
-#define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\
-{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = false, \
- .element = { (e0), (e1), 0, 0 }, \
- .bits = { g, b, r, a }, \
- .chroma_sample = chroma, \
- .unpack_align_msb = 1, \
- .unpack_tight = 0, \
- .unpack_count = 2, \
- .bpp = 2, \
- .fetch_mode = fm, \
- .flag = {(flg)}, \
- .num_planes = np, \
- .tile_height = DPU_TILE_HEIGHT_DEFAULT \
-}
-
-#define PSEUDO_YUV_FMT_LOOSE_TILED(fmt, a, r, g, b, e0, e1, chroma, \
-flg, fm, np, th) \
-{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_PSEUDO_PLANAR, \
- .alpha_enable = false, \
- .element = { (e0), (e1), 0, 0 }, \
- .bits = { g, b, r, a }, \
- .chroma_sample = chroma, \
- .unpack_align_msb = 1, \
- .unpack_tight = 0, \
- .unpack_count = 2, \
- .bpp = 2, \
- .fetch_mode = fm, \
- .flag = {(flg)}, \
- .num_planes = np, \
- .tile_height = th \
-}
-
-
-#define PLANAR_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, alpha, chroma, bp, \
-flg, fm, np) \
-{ \
- .base.pixel_format = DRM_FORMAT_ ## fmt, \
- .fetch_planes = DPU_PLANE_PLANAR, \
- .alpha_enable = alpha, \
- .element = { (e0), (e1), (e2), 0 }, \
- .bits = { g, b, r, a }, \
- .chroma_sample = chroma, \
- .unpack_align_msb = 0, \
- .unpack_tight = 1, \
- .unpack_count = 1, \
- .bpp = bp, \
- .fetch_mode = fm, \
- .flag = {(flg)}, \
- .num_planes = np, \
- .tile_height = DPU_TILE_HEIGHT_DEFAULT \
-}
-
-/*
* struct dpu_media_color_map - maps drm format to media format
* @format: DRM base pixel format
* @color: Media API color related to DRM format
@@ -193,380 +26,11 @@ struct dpu_media_color_map {
uint32_t color;
};
-static const struct dpu_format dpu_format_map[] = {
- INTERLEAVED_RGB_FMT(ARGB8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- true, 4, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ABGR8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XBGR8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBA8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- true, 4, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRA8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- true, 4, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRX8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- false, 4, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XRGB8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- false, 4, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBX8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- false, 4, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGB888,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
- false, 3, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGR888,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
- false, 3, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGB565,
- 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
- C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
- false, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGR565,
- 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
- false, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ARGB1555,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- true, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ABGR1555,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBA5551,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- true, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRA5551,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- true, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XRGB1555,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- false, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XBGR1555,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBX5551,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- false, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRX5551,
- COLOR_ALPHA_1BIT, COLOR_5BIT, COLOR_5BIT, COLOR_5BIT,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- false, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ARGB4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- true, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ABGR4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBA4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- true, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRA4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- true, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XRGB4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- false, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XBGR4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBX4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- false, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRX4444,
- COLOR_ALPHA_4BIT, COLOR_4BIT, COLOR_4BIT, COLOR_4BIT,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- false, 2, 0,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRA1010102,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- true, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBA1010102,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- true, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ABGR2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(ARGB2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XRGB2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
- false, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(BGRX1010102,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
- false, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(XBGR2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
-
- INTERLEAVED_RGB_FMT(RGBX1010102,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
- false, 4, DPU_FORMAT_FLAG_DX,
- DPU_FETCH_LINEAR, 1),
-
- PSEUDO_YUV_FMT(NV12,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C1_B_Cb, C2_R_Cr,
- DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
-
- PSEUDO_YUV_FMT(NV21,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C1_B_Cb,
- DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
-
- PSEUDO_YUV_FMT(NV16,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C1_B_Cb, C2_R_Cr,
- DPU_CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
-
- PSEUDO_YUV_FMT(NV61,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C1_B_Cb,
- DPU_CHROMA_H2V1, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
-
- PSEUDO_YUV_FMT_LOOSE(P010,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C1_B_Cb, C2_R_Cr,
- DPU_CHROMA_420, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
-
- INTERLEAVED_YUV_FMT(VYUY,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
- false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
-
- INTERLEAVED_YUV_FMT(UYVY,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
- false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
-
- INTERLEAVED_YUV_FMT(YUYV,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
- false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
-
- INTERLEAVED_YUV_FMT(YVYU,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
- false, DPU_CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 2),
-
- PLANAR_YUV_FMT(YUV420,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C1_B_Cb, C0_G_Y,
- false, DPU_CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 3),
-
- PLANAR_YUV_FMT(YVU420,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C1_B_Cb, C2_R_Cr, C0_G_Y,
- false, DPU_CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
- DPU_FETCH_LINEAR, 3),
-};
-
-/*
- * UBWC formats table:
- * This table holds the UBWC formats supported.
- * If a compression ratio needs to be used for this or any other format,
- * the data will be passed by user-space.
- */
-static const struct dpu_format dpu_format_map_ubwc[] = {
- INTERLEAVED_RGB_FMT_TILED(BGR565,
- 0, COLOR_5BIT, COLOR_6BIT, COLOR_5BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
- false, 2, DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(ABGR8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- /* ARGB8888 and ABGR8888 purposely have the same color
- * ordering. The hardware only supports ABGR8888 UBWC
- * natively.
- */
- INTERLEAVED_RGB_FMT_TILED(ARGB8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(XBGR8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(XRGB8888,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- /* XRGB2101010 and ARGB2101010 purposely have the same color
- * ordering. The hardware only supports ARGB2101010 UBWC
- * natively.
- */
- INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
- COLOR_8BIT, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC),
-
- PSEUDO_YUV_FMT_TILED(NV12,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C1_B_Cb, C2_R_Cr,
- DPU_CHROMA_420, DPU_FORMAT_FLAG_YUV |
- DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12),
-
- PSEUDO_YUV_FMT_TILED(P010,
- 0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
- C1_B_Cb, C2_R_Cr,
- DPU_CHROMA_420, DPU_FORMAT_FLAG_DX |
- DPU_FORMAT_FLAG_YUV |
- DPU_FORMAT_FLAG_COMPRESSED,
- DPU_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC),
-};
-
/* _dpu_get_v_h_subsample_rate - Get subsample rates for all formats we support
* Note: Not using the drm_format_*_subsampling since we have formats
*/
static void _dpu_get_v_h_subsample_rate(
- enum dpu_chroma_samp_type chroma_sample,
+ enum mdp_chroma_samp_type chroma_sample,
uint32_t *v_sample,
uint32_t *h_sample)
{
@@ -574,15 +38,15 @@ static void _dpu_get_v_h_subsample_rate(
return;
switch (chroma_sample) {
- case DPU_CHROMA_H2V1:
+ case CHROMA_H2V1:
*v_sample = 1;
*h_sample = 2;
break;
- case DPU_CHROMA_H1V2:
+ case CHROMA_H1V2:
*v_sample = 2;
*h_sample = 1;
break;
- case DPU_CHROMA_420:
+ case CHROMA_420:
*v_sample = 2;
*h_sample = 2;
break;
@@ -593,7 +57,7 @@ static void _dpu_get_v_h_subsample_rate(
}
}
-static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
+static int _dpu_format_get_media_color_ubwc(const struct msm_format *fmt)
{
static const struct dpu_media_color_map dpu_media_ubwc_map[] = {
{DRM_FORMAT_ABGR8888, COLOR_FMT_RGBA8888_UBWC},
@@ -609,10 +73,10 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
int color_fmt = -1;
int i;
- if (fmt->base.pixel_format == DRM_FORMAT_NV12 ||
- fmt->base.pixel_format == DRM_FORMAT_P010) {
- if (DPU_FORMAT_IS_DX(fmt)) {
- if (fmt->unpack_tight)
+ if (fmt->pixel_format == DRM_FORMAT_NV12 ||
+ fmt->pixel_format == DRM_FORMAT_P010) {
+ if (MSM_FORMAT_IS_DX(fmt)) {
+ if (fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT)
color_fmt = COLOR_FMT_NV12_BPP10_UBWC;
else
color_fmt = COLOR_FMT_P010_UBWC;
@@ -622,7 +86,7 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
}
for (i = 0; i < ARRAY_SIZE(dpu_media_ubwc_map); ++i)
- if (fmt->base.pixel_format == dpu_media_ubwc_map[i].format) {
+ if (fmt->pixel_format == dpu_media_ubwc_map[i].format) {
color_fmt = dpu_media_ubwc_map[i].color;
break;
}
@@ -630,14 +94,14 @@ static int _dpu_format_get_media_color_ubwc(const struct dpu_format *fmt)
}
static int _dpu_format_get_plane_sizes_ubwc(
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
const uint32_t width,
const uint32_t height,
struct dpu_hw_fmt_layout *layout)
{
int i;
int color;
- bool meta = DPU_FORMAT_IS_UBWC(fmt);
+ bool meta = MSM_FORMAT_IS_UBWC(fmt);
memset(layout, 0, sizeof(struct dpu_hw_fmt_layout));
layout->format = fmt;
@@ -647,12 +111,12 @@ static int _dpu_format_get_plane_sizes_ubwc(
color = _dpu_format_get_media_color_ubwc(fmt);
if (color < 0) {
- DRM_ERROR("UBWC format not supported for fmt: %4.4s\n",
- (char *)&fmt->base.pixel_format);
+ DRM_ERROR("UBWC format not supported for fmt: %p4cc\n",
+ &fmt->pixel_format);
return -EINVAL;
}
- if (DPU_FORMAT_IS_YUV(layout->format)) {
+ if (MSM_FORMAT_IS_YUV(layout->format)) {
uint32_t y_sclines, uv_sclines;
uint32_t y_meta_scanlines = 0;
uint32_t uv_meta_scanlines = 0;
@@ -709,7 +173,7 @@ done:
}
static int _dpu_format_get_plane_sizes_linear(
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
const uint32_t width,
const uint32_t height,
struct dpu_hw_fmt_layout *layout,
@@ -724,7 +188,7 @@ static int _dpu_format_get_plane_sizes_linear(
layout->num_planes = fmt->num_planes;
/* Due to memset above, only need to set planes of interest */
- if (fmt->fetch_planes == DPU_PLANE_INTERLEAVED) {
+ if (fmt->fetch_type == MDP_PLANE_INTERLEAVED) {
layout->num_planes = 1;
layout->plane_size[0] = width * height * layout->format->bpp;
layout->plane_pitch[0] = width * layout->format->bpp;
@@ -742,8 +206,8 @@ static int _dpu_format_get_plane_sizes_linear(
return -EINVAL;
}
- if ((fmt->base.pixel_format == DRM_FORMAT_NV12) &&
- (DPU_FORMAT_IS_DX(fmt)))
+ if ((fmt->pixel_format == DRM_FORMAT_NV12) &&
+ (MSM_FORMAT_IS_DX(fmt)))
bpp = 2;
layout->plane_pitch[0] = width * bpp;
layout->plane_pitch[1] = layout->plane_pitch[0] / h_subsample;
@@ -751,7 +215,7 @@ static int _dpu_format_get_plane_sizes_linear(
layout->plane_size[1] = layout->plane_pitch[1] *
(height / v_subsample);
- if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
+ if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) {
layout->num_planes = 2;
layout->plane_size[1] *= 2;
layout->plane_pitch[1] *= 2;
@@ -781,7 +245,7 @@ static int _dpu_format_get_plane_sizes_linear(
}
static int dpu_format_get_plane_sizes(
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
const uint32_t w,
const uint32_t h,
struct dpu_hw_fmt_layout *layout,
@@ -797,7 +261,7 @@ static int dpu_format_get_plane_sizes(
return -ERANGE;
}
- if (DPU_FORMAT_IS_UBWC(fmt) || DPU_FORMAT_IS_TILE(fmt))
+ if (MSM_FORMAT_IS_UBWC(fmt) || MSM_FORMAT_IS_TILE(fmt))
return _dpu_format_get_plane_sizes_ubwc(fmt, w, h, layout);
return _dpu_format_get_plane_sizes_linear(fmt, w, h, layout, pitches);
@@ -823,10 +287,10 @@ static int _dpu_format_populate_addrs_ubwc(
return -EFAULT;
}
- meta = DPU_FORMAT_IS_UBWC(layout->format);
+ meta = MSM_FORMAT_IS_UBWC(layout->format);
/* Per-format logic for verifying active planes */
- if (DPU_FORMAT_IS_YUV(layout->format)) {
+ if (MSM_FORMAT_IS_YUV(layout->format)) {
/************************************************/
/* UBWC ** */
/* buffer ** DPU PLANE */
@@ -942,7 +406,7 @@ int dpu_format_populate_layout(
return -ERANGE;
}
- layout->format = to_dpu_format(msm_framebuffer_format(fb));
+ layout->format = msm_framebuffer_format(fb);
/* Populate the plane sizes etc via get_format */
ret = dpu_format_get_plane_sizes(layout->format, fb->width, fb->height,
@@ -951,8 +415,8 @@ int dpu_format_populate_layout(
return ret;
/* Populate the addresses given the fb */
- if (DPU_FORMAT_IS_UBWC(layout->format) ||
- DPU_FORMAT_IS_TILE(layout->format))
+ if (MSM_FORMAT_IS_UBWC(layout->format) ||
+ MSM_FORMAT_IS_TILE(layout->format))
ret = _dpu_format_populate_addrs_ubwc(aspace, fb, layout);
else
ret = _dpu_format_populate_addrs_linear(aspace, fb, layout);
@@ -962,23 +426,21 @@ int dpu_format_populate_layout(
int dpu_format_check_modified_format(
const struct msm_kms *kms,
- const struct msm_format *msm_fmt,
+ const struct msm_format *fmt,
const struct drm_mode_fb_cmd2 *cmd,
struct drm_gem_object **bos)
{
const struct drm_format_info *info;
- const struct dpu_format *fmt;
struct dpu_hw_fmt_layout layout;
uint32_t bos_total_size = 0;
int ret, i;
- if (!msm_fmt || !cmd || !bos) {
+ if (!fmt || !cmd || !bos) {
DRM_ERROR("invalid arguments\n");
return -EINVAL;
}
- fmt = to_dpu_format(msm_fmt);
- info = drm_format_info(fmt->base.pixel_format);
+ info = drm_format_info(fmt->pixel_format);
if (!info)
return -EINVAL;
@@ -1004,65 +466,3 @@ int dpu_format_check_modified_format(
return 0;
}
-
-const struct dpu_format *dpu_get_dpu_format_ext(
- const uint32_t format,
- const uint64_t modifier)
-{
- uint32_t i = 0;
- const struct dpu_format *fmt = NULL;
- const struct dpu_format *map = NULL;
- ssize_t map_size = 0;
-
- /*
- * Currently only support exactly zero or one modifier.
- * All planes use the same modifier.
- */
- DRM_DEBUG_ATOMIC("plane format modifier 0x%llX\n", modifier);
-
- switch (modifier) {
- case 0:
- map = dpu_format_map;
- map_size = ARRAY_SIZE(dpu_format_map);
- break;
- case DRM_FORMAT_MOD_QCOM_COMPRESSED:
- map = dpu_format_map_ubwc;
- map_size = ARRAY_SIZE(dpu_format_map_ubwc);
- DRM_DEBUG_ATOMIC("found fmt: %4.4s DRM_FORMAT_MOD_QCOM_COMPRESSED\n",
- (char *)&format);
- break;
- default:
- DPU_ERROR("unsupported format modifier %llX\n", modifier);
- return NULL;
- }
-
- for (i = 0; i < map_size; i++) {
- if (format == map[i].base.pixel_format) {
- fmt = &map[i];
- break;
- }
- }
-
- if (fmt == NULL)
- DPU_ERROR("unsupported fmt: %4.4s modifier 0x%llX\n",
- (char *)&format, modifier);
- else
- DRM_DEBUG_ATOMIC("fmt %4.4s mod 0x%llX ubwc %d yuv %d\n",
- (char *)&format, modifier,
- DPU_FORMAT_IS_UBWC(fmt),
- DPU_FORMAT_IS_YUV(fmt));
-
- return fmt;
-}
-
-const struct msm_format *dpu_get_msm_format(
- struct msm_kms *kms,
- const uint32_t format,
- const uint64_t modifiers)
-{
- const struct dpu_format *fmt = dpu_get_dpu_format_ext(format,
- modifiers);
- if (fmt)
- return &fmt->base;
- return NULL;
-}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
index 84b8b3289f18..210d0ed5f0af 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
@@ -10,17 +10,6 @@
#include "dpu_hw_mdss.h"
/**
- * dpu_get_dpu_format_ext() - Returns dpu format structure pointer.
- * @format: DRM FourCC Code
- * @modifiers: format modifier array from client, one per plane
- */
-const struct dpu_format *dpu_get_dpu_format_ext(
- const uint32_t format,
- const uint64_t modifier);
-
-#define dpu_get_dpu_format(f) dpu_get_dpu_format_ext(f, 0)
-
-/**
* dpu_find_format - validate if the pixel format is supported
* @format: dpu format
* @supported_formats: supported formats by dpu HW
@@ -43,22 +32,10 @@ static inline bool dpu_find_format(u32 format, const u32 *supported_formats,
}
/**
- * dpu_get_msm_format - get an dpu_format by its msm_format base
- * callback function registers with the msm_kms layer
- * @kms: kms driver
- * @format: DRM FourCC Code
- * @modifiers: data layout modifier
- */
-const struct msm_format *dpu_get_msm_format(
- struct msm_kms *kms,
- const uint32_t format,
- const uint64_t modifiers);
-
-/**
* dpu_format_check_modified_format - validate format and buffers for
* dpu non-standard, i.e. modified format
* @kms: kms driver
- * @msm_fmt: pointer to the msm_fmt base pointer of an dpu_format
+ * @msm_fmt: pointer to the msm_fmt base pointer of an msm_format
* @cmd: fb_cmd2 structure user request
* @bos: gem buffer object list
*
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
index 9016b3ade6bc..55d2768a6d4d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
@@ -170,7 +170,7 @@ static int dpu_hw_cdm_setup_cdwn(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *
static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cdm)
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
- const struct dpu_format *fmt;
+ const struct msm_format *fmt;
u32 opmode = 0;
u32 csc = 0;
@@ -179,14 +179,14 @@ static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cdm)
fmt = cdm->output_fmt;
- if (!DPU_FORMAT_IS_YUV(fmt))
+ if (!MSM_FORMAT_IS_YUV(fmt))
return -EINVAL;
dpu_hw_csc_setup(&ctx->hw, CDM_CSC_10_MATRIX_COEFF_0, cdm->csc_cfg, true);
dpu_hw_cdm_setup_cdwn(ctx, cdm);
if (cdm->output_type == CDM_CDWN_OUTPUT_HDMI) {
- if (fmt->chroma_sample == DPU_CHROMA_H1V2)
+ if (fmt->chroma_sample == CHROMA_H1V2)
return -EINVAL; /*unsupported format */
opmode = CDM_HDMI_PACK_OP_MODE_EN;
opmode |= (fmt->chroma_sample << 1);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
index 348424df87c6..ec71c9886d75 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
@@ -19,7 +19,7 @@ struct dpu_hw_cdm;
* @output_bit_depth: output bit-depth of CDM block
* @h_cdwn_type: downsample type used for horizontal pixels
* @v_cdwn_type: downsample type used for vertical pixels
- * @output_fmt: handle to dpu_format of CDM block
+ * @output_fmt: handle to msm_format of CDM block
* @csc_cfg: handle to CSC matrix programmed for CDM block
* @output_type: interface to which CDM is paired (HDMI/WB)
* @pp_id: ping-pong block to which CDM is bound to
@@ -30,7 +30,7 @@ struct dpu_hw_cdm_cfg {
u32 output_bit_depth;
u32 h_cdwn_type;
u32 v_cdwn_type;
- const struct dpu_format *output_fmt;
+ const struct msm_format *output_fmt;
const struct dpu_csc_cfg *csc_cfg;
u32 output_type;
int pp_id;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index a06f69d0b257..2e50049f2f85 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -545,6 +545,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
u32 intf_active = 0;
+ u32 dsc_active = 0;
u32 wb_active = 0;
u32 mode_sel = 0;
@@ -560,6 +561,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE);
wb_active = DPU_REG_READ(c, CTL_WB_ACTIVE);
+ dsc_active = DPU_REG_READ(c, CTL_DSC_ACTIVE);
if (cfg->intf)
intf_active |= BIT(cfg->intf - INTF_0);
@@ -567,17 +569,18 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
if (cfg->wb)
wb_active |= BIT(cfg->wb - WB_0);
+ if (cfg->dsc)
+ dsc_active |= cfg->dsc;
+
DPU_REG_WRITE(c, CTL_TOP, mode_sel);
DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
+ DPU_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);
if (cfg->merge_3d)
DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
BIT(cfg->merge_3d - MERGE_3D_0));
- if (cfg->dsc)
- DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
-
if (cfg->cdm)
DPU_REG_WRITE(c, CTL_CDM_ACTIVE, cfg->cdm);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 6a0a74832fb6..b85881aab047 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -223,9 +223,11 @@ static void dpu_core_irq_callback_handler(struct dpu_kms *dpu_kms, unsigned int
VERB("IRQ=[%d, %d]\n", DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx));
- if (!irq_entry->cb)
+ if (!irq_entry->cb) {
DRM_ERROR("no registered cb, IRQ=[%d, %d]\n",
DPU_IRQ_REG(irq_idx), DPU_IRQ_BIT(irq_idx));
+ return;
+ }
atomic_inc(&irq_entry->count);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 965692ef7892..225c1c7768ff 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -96,11 +96,11 @@
#define INTF_CFG2_DCE_DATA_COMPRESS BIT(12)
-static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
+static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,
const struct dpu_hw_intf_timing_params *p,
- const struct dpu_format *fmt)
+ const struct msm_format *fmt)
{
- struct dpu_hw_blk_reg_map *c = &ctx->hw;
+ struct dpu_hw_blk_reg_map *c = &intf->hw;
u32 hsync_period, vsync_period;
u32 display_v_start, display_v_end;
u32 hsync_start_x, hsync_end_x;
@@ -118,7 +118,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
/* read interface_cfg */
intf_cfg = DPU_REG_READ(c, INTF_CONFIG);
- if (ctx->cap->type == INTF_DP)
+ if (intf->cap->type == INTF_DP)
dp_intf = true;
hsync_period = p->hsync_pulse_width + p->h_back_porch + p->width +
@@ -194,16 +194,16 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
(p->vsync_polarity << 1) | /* VSYNC Polarity */
(p->hsync_polarity << 0); /* HSYNC Polarity */
- if (!DPU_FORMAT_IS_YUV(fmt))
- panel_format = (fmt->bits[C0_G_Y] |
- (fmt->bits[C1_B_Cb] << 2) |
- (fmt->bits[C2_R_Cr] << 4) |
+ if (!MSM_FORMAT_IS_YUV(fmt))
+ panel_format = (fmt->bpc_g_y |
+ (fmt->bpc_b_cb << 2) |
+ (fmt->bpc_r_cr << 4) |
(0x21 << 8));
else
/* Interface treats all the pixel data in RGB888 format */
- panel_format = (COLOR_8BIT |
- (COLOR_8BIT << 2) |
- (COLOR_8BIT << 4) |
+ panel_format = (BPC8 |
+ (BPC8 << 2) |
+ (BPC8 << 4) |
(0x21 << 8));
DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);
@@ -223,7 +223,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3);
DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg);
DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
- if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) {
+ if (intf->cap->features & BIT(DPU_DATA_HCTL_EN)) {
/*
* DATA_HCTL_EN controls data timing which can be different from
* video timing. It is recommended to enable it for all cases, except
@@ -518,10 +518,10 @@ static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf,
}
-static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx,
+static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *intf,
struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg)
{
- u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2);
+ u32 intf_cfg2 = DPU_REG_READ(&intf->hw, INTF_CONFIG2);
if (cmd_mode_cfg->data_compress)
intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
@@ -529,7 +529,7 @@ static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx,
if (cmd_mode_cfg->wide_bus_en)
intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN;
- DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2);
+ DPU_REG_WRITE(&intf->hw, INTF_CONFIG2, intf_cfg2);
}
struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 6f4c87244f94..f9015c67a574 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -81,7 +81,7 @@ struct dpu_hw_intf_cmd_mode_cfg {
struct dpu_hw_intf_ops {
void (*setup_timing_gen)(struct dpu_hw_intf *intf,
const struct dpu_hw_intf_timing_params *p,
- const struct dpu_format *fmt);
+ const struct msm_format *fmt);
void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
const struct dpu_hw_intf_prog_fetch *fetch);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index 5df545904057..66759623fc42 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -10,6 +10,8 @@
#include "msm_drv.h"
+#include "disp/mdp_format.h"
+
#define DPU_DBG_NAME "dpu"
#define DPU_NONE 0
@@ -35,28 +37,6 @@
#define DPU_MAX_DE_CURVES 3
#endif
-enum dpu_format_flags {
- DPU_FORMAT_FLAG_YUV_BIT,
- DPU_FORMAT_FLAG_DX_BIT,
- DPU_FORMAT_FLAG_COMPRESSED_BIT,
- DPU_FORMAT_FLAG_BIT_MAX,
-};
-
-#define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT)
-#define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT)
-#define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT)
-#define DPU_FORMAT_IS_YUV(X) \
- (test_bit(DPU_FORMAT_FLAG_YUV_BIT, (X)->flag))
-#define DPU_FORMAT_IS_DX(X) \
- (test_bit(DPU_FORMAT_FLAG_DX_BIT, (X)->flag))
-#define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == DPU_FETCH_LINEAR)
-#define DPU_FORMAT_IS_TILE(X) \
- (((X)->fetch_mode == DPU_FETCH_UBWC) && \
- !test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
-#define DPU_FORMAT_IS_UBWC(X) \
- (((X)->fetch_mode == DPU_FETCH_UBWC) && \
- test_bit(DPU_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
-
#define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0)
#define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0)
#define DPU_BLEND_FG_ALPHA_FG_PIXEL (2 << 0)
@@ -291,67 +271,6 @@ enum dpu_vbif {
};
/**
- * DPU HW,Component order color map
- */
-enum {
- C0_G_Y = 0,
- C1_B_Cb = 1,
- C2_R_Cr = 2,
- C3_ALPHA = 3
-};
-
-/**
- * enum dpu_plane_type - defines how the color component pixel packing
- * @DPU_PLANE_INTERLEAVED : Color components in single plane
- * @DPU_PLANE_PLANAR : Color component in separate planes
- * @DPU_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane
- */
-enum dpu_plane_type {
- DPU_PLANE_INTERLEAVED,
- DPU_PLANE_PLANAR,
- DPU_PLANE_PSEUDO_PLANAR,
-};
-
-/**
- * enum dpu_chroma_samp_type - chroma sub-samplng type
- * @DPU_CHROMA_RGB : No chroma subsampling
- * @DPU_CHROMA_H2V1 : Chroma pixels are horizontally subsampled
- * @DPU_CHROMA_H1V2 : Chroma pixels are vertically subsampled
- * @DPU_CHROMA_420 : 420 subsampling
- */
-enum dpu_chroma_samp_type {
- DPU_CHROMA_RGB,
- DPU_CHROMA_H2V1,
- DPU_CHROMA_H1V2,
- DPU_CHROMA_420
-};
-
-/**
- * dpu_fetch_type - Defines How DPU HW fetches data
- * @DPU_FETCH_LINEAR : fetch is line by line
- * @DPU_FETCH_TILE : fetches data in Z order from a tile
- * @DPU_FETCH_UBWC : fetch and decompress data
- */
-enum dpu_fetch_type {
- DPU_FETCH_LINEAR,
- DPU_FETCH_TILE,
- DPU_FETCH_UBWC
-};
-
-/**
- * Value of enum chosen to fit the number of bits
- * expected by the HW programming.
- */
-enum {
- COLOR_ALPHA_1BIT = 0,
- COLOR_ALPHA_4BIT = 1,
- COLOR_4BIT = 0,
- COLOR_5BIT = 1, /* No 5-bit Alpha */
- COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */
- COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */
-};
-
-/**
* enum dpu_3d_blend_mode
* Desribes how the 3d data is blended
* @BLEND_3D_NONE : 3d blending not enabled
@@ -370,43 +289,6 @@ enum dpu_3d_blend_mode {
BLEND_3D_MAX
};
-/** struct dpu_format - defines the format configuration which
- * allows DPU HW to correctly fetch and decode the format
- * @base: base msm_format structure containing fourcc code
- * @fetch_planes: how the color components are packed in pixel format
- * @element: element color ordering
- * @bits: element bit widths
- * @chroma_sample: chroma sub-samplng type
- * @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB
- * @unpack_tight: 0 for loose, 1 for tight
- * @unpack_count: 0 = 1 component, 1 = 2 component
- * @bpp: bytes per pixel
- * @alpha_enable: whether the format has an alpha channel
- * @num_planes: number of planes (including meta data planes)
- * @fetch_mode: linear, tiled, or ubwc hw fetch behavior
- * @flag: usage bit flags
- * @tile_width: format tile width
- * @tile_height: format tile height
- */
-struct dpu_format {
- struct msm_format base;
- enum dpu_plane_type fetch_planes;
- u8 element[DPU_MAX_PLANES];
- u8 bits[DPU_MAX_PLANES];
- enum dpu_chroma_samp_type chroma_sample;
- u8 unpack_align_msb;
- u8 unpack_tight;
- u8 unpack_count;
- u8 bpp;
- u8 alpha_enable;
- u8 num_planes;
- enum dpu_fetch_type fetch_mode;
- DECLARE_BITMAP(flag, DPU_FORMAT_FLAG_BIT_MAX);
- u16 tile_width;
- u16 tile_height;
-};
-#define to_dpu_format(x) container_of(x, struct dpu_format, base)
-
/**
* struct dpu_hw_fmt_layout - format information of the source pixel data
* @format: pixel format parameters
@@ -419,7 +301,7 @@ struct dpu_format {
* @plane_pitch: pitch of each plane
*/
struct dpu_hw_fmt_layout {
- const struct dpu_format *format;
+ const struct msm_format *format;
uint32_t num_planes;
uint32_t width;
uint32_t height;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
index 8586f2761782..2c720f1fc1b2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
@@ -208,7 +208,7 @@ static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx,
* Setup source pixel format, flip,
*/
static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt, u32 flags)
+ const struct msm_format *fmt, u32 flags)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
struct dpu_hw_blk_reg_map *c;
@@ -243,20 +243,20 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
chroma_samp = fmt->chroma_sample;
if (flags & DPU_SSPP_SOURCE_ROTATED_90) {
- if (chroma_samp == DPU_CHROMA_H2V1)
- chroma_samp = DPU_CHROMA_H1V2;
- else if (chroma_samp == DPU_CHROMA_H1V2)
- chroma_samp = DPU_CHROMA_H2V1;
+ if (chroma_samp == CHROMA_H2V1)
+ chroma_samp = CHROMA_H1V2;
+ else if (chroma_samp == CHROMA_H1V2)
+ chroma_samp = CHROMA_H2V1;
}
- src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) |
- (fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) |
- (fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0);
+ src_format = (chroma_samp << 23) | (fmt->fetch_type << 19) |
+ (fmt->bpc_a << 6) | (fmt->bpc_r_cr << 4) |
+ (fmt->bpc_b_cb << 2) | (fmt->bpc_g_y << 0);
if (flags & DPU_SSPP_ROT_90)
src_format |= BIT(11); /* ROT90 */
- if (fmt->alpha_enable && fmt->fetch_planes == DPU_PLANE_INTERLEAVED)
+ if (fmt->alpha_enable && fmt->fetch_type == MDP_PLANE_INTERLEAVED)
src_format |= BIT(8); /* SRCC3_EN */
if (flags & DPU_SSPP_SOLID_FILL)
@@ -265,12 +265,12 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) |
(fmt->element[1] << 8) | (fmt->element[0] << 0);
src_format |= ((fmt->unpack_count - 1) << 12) |
- (fmt->unpack_tight << 17) |
- (fmt->unpack_align_msb << 18) |
+ ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) |
+ ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB ? 1 : 0) << 18) |
((fmt->bpp - 1) << 9);
- if (fmt->fetch_mode != DPU_FETCH_LINEAR) {
- if (DPU_FORMAT_IS_UBWC(fmt))
+ if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
+ if (MSM_FORMAT_IS_UBWC(fmt))
opmode |= MDSS_MDP_OP_BWC_EN;
src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */
DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
@@ -297,7 +297,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
break;
case UBWC_4_0:
DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
- DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
+ MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
break;
}
}
@@ -305,20 +305,20 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe,
opmode |= MDSS_MDP_OP_PE_OVERRIDE;
/* if this is YUV pixel format, enable CSC */
- if (DPU_FORMAT_IS_YUV(fmt))
+ if (MSM_FORMAT_IS_YUV(fmt))
src_format |= BIT(15);
- if (DPU_FORMAT_IS_DX(fmt))
+ if (MSM_FORMAT_IS_DX(fmt))
src_format |= BIT(14);
/* update scaler opmode, if appropriate */
if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
- DPU_FORMAT_IS_YUV(fmt));
+ MSM_FORMAT_IS_YUV(fmt));
else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
_sspp_setup_csc10_opmode(ctx,
VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
- DPU_FORMAT_IS_YUV(fmt));
+ MSM_FORMAT_IS_YUV(fmt));
DPU_REG_WRITE(c, format_off, src_format);
DPU_REG_WRITE(c, unpack_pat_off, unpack);
@@ -387,7 +387,7 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx,
static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
- const struct dpu_format *format)
+ const struct msm_format *format)
{
if (!ctx || !scaler3_cfg)
return;
@@ -558,7 +558,7 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx,
}
static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
bool enable)
{
struct dpu_hw_sspp *ctx = pipe->sspp;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
index b7dc52312c39..4a910b808687 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
@@ -183,7 +183,7 @@ struct dpu_hw_sspp_ops {
* @flags: Extra flags for format config
*/
void (*setup_format)(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt, u32 flags);
+ const struct msm_format *fmt, u32 flags);
/**
* setup_rects - setup pipe ROI rectangles
@@ -279,7 +279,7 @@ struct dpu_hw_sspp_ops {
*/
void (*setup_scaler)(struct dpu_hw_sspp *ctx,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
- const struct dpu_format *format);
+ const struct msm_format *format);
/**
* setup_cdp - setup client driven prefetch
@@ -288,7 +288,7 @@ struct dpu_hw_sspp_ops {
* @enable: whether the CDP should be enabled for this pipe
*/
void (*setup_cdp)(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
bool enable);
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
index dd475827314e..486be346d40d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
@@ -282,7 +282,7 @@ static void _dpu_hw_setup_scaler3_de(struct dpu_hw_blk_reg_map *c,
void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
u32 scaler_offset, u32 scaler_version,
- const struct dpu_format *format)
+ const struct msm_format *format)
{
u32 op_mode = 0;
u32 phase_init, preload, src_y_rgb, src_uv, dst;
@@ -293,7 +293,7 @@ void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
op_mode |= BIT(0);
op_mode |= (scaler3_cfg->y_rgb_filter_cfg & 0x3) << 16;
- if (format && DPU_FORMAT_IS_YUV(format)) {
+ if (format && MSM_FORMAT_IS_YUV(format)) {
op_mode |= BIT(12);
op_mode |= (scaler3_cfg->uv_filter_cfg & 0x3) << 24;
}
@@ -367,7 +367,7 @@ void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
DPU_REG_WRITE(c, QSEED3_DST_SIZE + scaler_offset, dst);
end:
- if (format && !DPU_FORMAT_IS_DX(format))
+ if (format && !MSM_FORMAT_IS_DX(format))
op_mode |= BIT(14);
if (format && format->alpha_enable) {
@@ -522,16 +522,16 @@ int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
#define CDP_PRELOAD_AHEAD_64 BIT(3)
void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset,
- const struct dpu_format *fmt, bool enable)
+ const struct msm_format *fmt, bool enable)
{
u32 cdp_cntl = CDP_PRELOAD_AHEAD_64;
if (enable)
cdp_cntl |= CDP_ENABLE;
- if (DPU_FORMAT_IS_UBWC(fmt))
+ if (MSM_FORMAT_IS_UBWC(fmt))
cdp_cntl |= CDP_UBWC_META_ENABLE;
- if (DPU_FORMAT_IS_UBWC(fmt) ||
- DPU_FORMAT_IS_TILE(fmt))
+ if (MSM_FORMAT_IS_UBWC(fmt) ||
+ MSM_FORMAT_IS_TILE(fmt))
cdp_cntl |= CDP_TILE_AMORTIZE_ENABLE;
DPU_REG_WRITE(c, offset, cdp_cntl);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
index 64ded69fa903..67b08e99335d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
@@ -344,14 +344,14 @@ void *dpu_hw_util_get_dir(void);
void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
struct dpu_hw_scaler3_cfg *scaler3_cfg,
u32 scaler_offset, u32 scaler_version,
- const struct dpu_format *format);
+ const struct msm_format *format);
void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
u32 csc_reg_off,
const struct dpu_csc_cfg *data, bool csc10);
void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset,
- const struct dpu_format *fmt, bool enable);
+ const struct msm_format *fmt, bool enable);
u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl,
u32 total_fl);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index e75995f7fcea..93ff01c889b5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -67,7 +67,7 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
struct dpu_hw_wb_cfg *data)
{
struct dpu_hw_blk_reg_map *c = &ctx->hw;
- const struct dpu_format *fmt = data->dest.format;
+ const struct msm_format *fmt = data->dest.format;
u32 dst_format, pattern, ystride0, ystride1, outsize, chroma_samp;
u32 write_config = 0;
u32 opmode = 0;
@@ -76,20 +76,20 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
chroma_samp = fmt->chroma_sample;
dst_format = (chroma_samp << 23) |
- (fmt->fetch_planes << 19) |
- (fmt->bits[C3_ALPHA] << 6) |
- (fmt->bits[C2_R_Cr] << 4) |
- (fmt->bits[C1_B_Cb] << 2) |
- (fmt->bits[C0_G_Y] << 0);
+ (fmt->fetch_type << 19) |
+ (fmt->bpc_a << 6) |
+ (fmt->bpc_r_cr << 4) |
+ (fmt->bpc_b_cb << 2) |
+ (fmt->bpc_g_y << 0);
- if (fmt->bits[C3_ALPHA] || fmt->alpha_enable) {
+ if (fmt->bpc_a || fmt->alpha_enable) {
dst_format |= BIT(8); /* DSTC3_EN */
if (!fmt->alpha_enable ||
!(ctx->caps->features & BIT(DPU_WB_PIPE_ALPHA)))
dst_format |= BIT(14); /* DST_ALPHA_X */
}
- if (DPU_FORMAT_IS_YUV(fmt))
+ if (MSM_FORMAT_IS_YUV(fmt))
dst_format |= BIT(15);
pattern = (fmt->element[3] << 24) |
@@ -97,8 +97,8 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
(fmt->element[1] << 8) |
(fmt->element[0] << 0);
- dst_format |= (fmt->unpack_align_msb << 18) |
- (fmt->unpack_tight << 17) |
+ dst_format |= ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB ? 1 : 0) << 18) |
+ ((fmt->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT ? 1 : 0) << 17) |
((fmt->unpack_count - 1) << 12) |
((fmt->bpp - 1) << 9);
@@ -149,7 +149,7 @@ static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx,
}
static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
bool enable)
{
if (!ctx)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
index e671796ea379..37497473e16c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h
@@ -46,7 +46,7 @@ struct dpu_hw_wb_ops {
struct dpu_hw_qos_cfg *cfg);
void (*setup_cdp)(struct dpu_hw_wb *ctx,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
bool enable);
bool (*setup_clk_force_ctrl)(struct dpu_hw_wb *ctx,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index a1f5d7c4ab91..1955848b1b78 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -348,9 +348,18 @@ static void dpu_kms_global_destroy_state(struct drm_private_obj *obj,
kfree(dpu_state);
}
+static void dpu_kms_global_print_state(struct drm_printer *p,
+ const struct drm_private_state *state)
+{
+ const struct dpu_global_state *global_state = to_dpu_global_state(state);
+
+ dpu_rm_print_state(p, global_state);
+}
+
static const struct drm_private_state_funcs dpu_kms_global_state_funcs = {
.atomic_duplicate_state = dpu_kms_global_duplicate_state,
.atomic_destroy_state = dpu_kms_global_destroy_state,
+ .atomic_print_state = dpu_kms_global_print_state,
};
static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)
@@ -364,6 +373,9 @@ static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)
drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state,
&state->base,
&dpu_kms_global_state_funcs);
+
+ state->rm = &dpu_kms->rm;
+
return 0;
}
@@ -970,7 +982,6 @@ static const struct msm_kms_funcs kms_funcs = {
.enable_vblank = dpu_kms_enable_vblank,
.disable_vblank = dpu_kms_disable_vblank,
.check_modified_format = dpu_format_check_modified_format,
- .get_format = dpu_get_msm_format,
.destroy = dpu_kms_destroy,
.snapshot = dpu_kms_mdp_snapshot,
#ifdef CONFIG_DEBUG_FS
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index b5db3fc76ca6..e2adc937ea63 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -130,6 +130,8 @@ struct vsync_info {
struct dpu_global_state {
struct drm_private_state base;
+ struct dpu_rm *rm;
+
uint32_t pingpong_to_enc_id[PINGPONG_MAX - PINGPONG_0];
uint32_t mixer_to_enc_id[LM_MAX - LM_0];
uint32_t ctl_to_enc_id[CTL_MAX - CTL_0];
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index ff975ad51145..1c3a2657450c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -113,7 +113,7 @@ static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
* Prefill BW Equation: line src bytes * line_time
*/
static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
const struct drm_display_mode *mode,
struct dpu_sw_pipe_cfg *pipe_cfg)
{
@@ -195,7 +195,7 @@ static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode,
static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
struct dpu_sw_pipe *pipe,
enum dpu_qos_lut_usage lut_usage,
- const struct dpu_format *fmt, u32 src_width)
+ const struct msm_format *fmt, u32 src_width)
{
struct dpu_plane *pdpu;
u32 fixed_buff_size;
@@ -214,8 +214,8 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
/* FIXME: in multirect case account for the src_width of all the planes */
- if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) {
- if (fmt->chroma_sample == DPU_CHROMA_420) {
+ if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) {
+ if (fmt->chroma_sample == CHROMA_420) {
/* NV12 */
total_fl = (fixed_buff_size / 2) /
((src_width + 32) * fmt->bpp);
@@ -234,9 +234,9 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
}
}
- DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s w:%u fl:%u\n",
+ DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc w:%u fl:%u\n",
pipe->sspp->idx - SSPP_VIG0,
- (char *)&fmt->base.pixel_format,
+ &fmt->pixel_format,
src_width, total_fl);
return total_fl;
@@ -251,7 +251,7 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
*/
static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg)
+ const struct msm_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg)
{
struct dpu_plane *pdpu = to_dpu_plane(plane);
struct dpu_hw_qos_cfg cfg;
@@ -260,7 +260,7 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
if (!pdpu->is_rt_pipe) {
lut_usage = DPU_QOS_LUT_USAGE_NRT;
} else {
- if (fmt && DPU_FORMAT_IS_LINEAR(fmt))
+ if (fmt && MSM_FORMAT_IS_LINEAR(fmt))
lut_usage = DPU_QOS_LUT_USAGE_LINEAR;
else
lut_usage = DPU_QOS_LUT_USAGE_MACROTILE;
@@ -284,26 +284,26 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
pdpu->is_rt_pipe);
trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0,
- (fmt) ? fmt->base.pixel_format : 0,
+ (fmt) ? fmt->pixel_format : 0,
pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage);
- DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n",
+ DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc rt:%d fl:%u lut:0x%llx\n",
pdpu->pipe - SSPP_VIG0,
- fmt ? (char *)&fmt->base.pixel_format : NULL,
+ fmt ? &fmt->pixel_format : NULL,
pdpu->is_rt_pipe, total_fl, cfg.creq_lut);
trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
- (fmt) ? fmt->base.pixel_format : 0,
+ (fmt) ? fmt->pixel_format : 0,
(fmt) ? fmt->fetch_mode : 0,
cfg.danger_lut,
cfg.safe_lut);
- DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n",
- pdpu->pipe - SSPP_VIG0,
- fmt ? (char *)&fmt->base.pixel_format : NULL,
- fmt ? fmt->fetch_mode : -1,
- cfg.danger_lut,
- cfg.safe_lut);
+ DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc mode:%d luts[0x%x, 0x%x]\n",
+ pdpu->pipe - SSPP_VIG0,
+ fmt ? &fmt->pixel_format : NULL,
+ fmt ? fmt->fetch_mode : -1,
+ cfg.danger_lut,
+ cfg.safe_lut);
pipe->sspp->ops.setup_qos_lut(pipe->sspp, &cfg);
}
@@ -425,7 +425,7 @@ static void _dpu_plane_set_qos_remap(struct drm_plane *plane,
static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
struct dpu_hw_scaler3_cfg *scale_cfg,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v,
unsigned int rotation)
{
@@ -477,7 +477,7 @@ static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
}
}
- if (!(DPU_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
+ if (!(MSM_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
&& (src_w == dst_w))
return;
@@ -510,11 +510,11 @@ static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg,
}
static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt)
+ const struct msm_format *fmt)
{
const struct dpu_csc_cfg *csc_ptr;
- if (!DPU_FORMAT_IS_YUV(fmt))
+ if (!MSM_FORMAT_IS_YUV(fmt))
return NULL;
if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features)
@@ -526,12 +526,12 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe,
}
static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe,
- const struct dpu_format *fmt, bool color_fill,
+ const struct msm_format *fmt, bool color_fill,
struct dpu_sw_pipe_cfg *pipe_cfg,
unsigned int rotation)
{
struct dpu_hw_sspp *pipe_hw = pipe->sspp;
- const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format);
+ const struct drm_format_info *info = drm_format_info(fmt->pixel_format);
struct dpu_hw_scaler3_cfg scaler3_cfg;
struct dpu_hw_pixel_ext pixel_ext;
u32 src_width = drm_rect_width(&pipe_cfg->src_rect);
@@ -577,7 +577,7 @@ static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate,
struct dpu_sw_pipe *pipe,
struct drm_rect *dst_rect,
u32 fill_color,
- const struct dpu_format *fmt)
+ const struct msm_format *fmt)
{
struct dpu_sw_pipe_cfg pipe_cfg;
@@ -615,8 +615,9 @@ static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate,
static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
uint32_t color, uint32_t alpha)
{
- const struct dpu_format *fmt;
+ const struct msm_format *fmt;
const struct drm_plane *plane = &pdpu->base;
+ struct msm_drm_private *priv = plane->dev->dev_private;
struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24);
@@ -626,7 +627,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
* select fill format to match user property expectation,
* h/w only supports RGB variants
*/
- fmt = dpu_get_dpu_format(DRM_FORMAT_ABGR8888);
+ fmt = mdp_get_format(priv->kms, DRM_FORMAT_ABGR8888, 0);
/* should not happen ever */
if (!fmt)
return;
@@ -704,7 +705,7 @@ static void dpu_plane_cleanup_fb(struct drm_plane *plane,
static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
const struct dpu_sspp_sub_blks *sblk,
- struct drm_rect src, const struct dpu_format *fmt)
+ struct drm_rect src, const struct msm_format *fmt)
{
size_t num_formats;
const u32 *supported_formats;
@@ -723,8 +724,8 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
supported_formats = sblk->rotation_cfg->rot_format_list;
num_formats = sblk->rotation_cfg->rot_num_formats;
- if (!DPU_FORMAT_IS_UBWC(fmt) ||
- !dpu_find_format(fmt->base.pixel_format, supported_formats, num_formats))
+ if (!MSM_FORMAT_IS_UBWC(fmt) ||
+ !dpu_find_format(fmt->pixel_format, supported_formats, num_formats))
return -EINVAL;
return 0;
@@ -733,15 +734,15 @@ static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
struct dpu_sw_pipe *pipe,
struct dpu_sw_pipe_cfg *pipe_cfg,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
const struct drm_display_mode *mode)
{
uint32_t min_src_size;
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
- min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1;
+ min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1;
- if (DPU_FORMAT_IS_YUV(fmt) &&
+ if (MSM_FORMAT_IS_YUV(fmt) &&
(!pipe->sspp->cap->sblk->scaler_blk.len ||
!pipe->sspp->cap->sblk->csc_blk.len)) {
DPU_DEBUG_PLANE(pdpu,
@@ -758,7 +759,7 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
}
/* valid yuv image */
- if (DPU_FORMAT_IS_YUV(fmt) &&
+ if (MSM_FORMAT_IS_YUV(fmt) &&
(pipe_cfg->src_rect.x1 & 0x1 ||
pipe_cfg->src_rect.y1 & 0x1 ||
drm_rect_width(&pipe_cfg->src_rect) & 0x1 ||
@@ -798,7 +799,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
struct dpu_sw_pipe *pipe = &pstate->pipe;
struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
const struct drm_crtc_state *crtc_state = NULL;
- const struct dpu_format *fmt;
+ const struct msm_format *fmt;
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
struct drm_rect fb_rect = { 0 };
@@ -858,7 +859,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
return -E2BIG;
}
- fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb));
+ fmt = msm_framebuffer_format(new_plane_state->fb);
max_linewidth = pdpu->catalog->caps->max_linewidth;
@@ -870,7 +871,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
* full width is more than max_linewidth, thus each rect is
* wider than allowed.
*/
- if (DPU_FORMAT_IS_UBWC(fmt) &&
+ if (MSM_FORMAT_IS_UBWC(fmt) &&
drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) {
DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n",
DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
@@ -887,7 +888,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) ||
(!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) &&
!test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) ||
- DPU_FORMAT_IS_YUV(fmt)) {
+ MSM_FORMAT_IS_YUV(fmt)) {
DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n",
DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
return -E2BIG;
@@ -945,8 +946,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe)
{
- const struct dpu_format *format =
- to_dpu_format(msm_framebuffer_format(pdpu->base.state->fb));
+ const struct msm_format *format =
+ msm_framebuffer_format(pdpu->base.state->fb);
const struct dpu_csc_cfg *csc_ptr;
if (!pipe->sspp || !pipe->sspp->ops.setup_csc)
@@ -1017,7 +1018,7 @@ void dpu_plane_set_error(struct drm_plane *plane, bool error)
static void dpu_plane_sspp_update_pipe(struct drm_plane *plane,
struct dpu_sw_pipe *pipe,
struct dpu_sw_pipe_cfg *pipe_cfg,
- const struct dpu_format *fmt,
+ const struct msm_format *fmt,
int frame_rate,
struct dpu_hw_fmt_layout *layout)
{
@@ -1095,8 +1096,8 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
struct drm_crtc *crtc = state->crtc;
struct drm_framebuffer *fb = state->fb;
bool is_rt_pipe;
- const struct dpu_format *fmt =
- to_dpu_format(msm_framebuffer_format(fb));
+ const struct msm_format *fmt =
+ msm_framebuffer_format(fb);
struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
@@ -1118,9 +1119,9 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
pdpu->is_rt_pipe = is_rt_pipe;
DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
- ", %4.4s ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
+ ", %p4cc ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
crtc->base.id, DRM_RECT_ARG(&state->dst),
- (char *)&fmt->base.pixel_format, DPU_FORMAT_IS_UBWC(fmt));
+ &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt));
dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt,
drm_mode_vrefresh(&crtc->mode),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index cb5ce3c62a22..44938ba7a2b7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -758,3 +758,59 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
return num_blks;
}
+
+static void dpu_rm_print_state_helper(struct drm_printer *p,
+ struct dpu_hw_blk *blk,
+ uint32_t mapping)
+{
+ if (!blk)
+ drm_puts(p, "- ");
+ else if (!mapping)
+ drm_puts(p, "# ");
+ else
+ drm_printf(p, "%d ", mapping);
+}
+
+
+void dpu_rm_print_state(struct drm_printer *p,
+ const struct dpu_global_state *global_state)
+{
+ const struct dpu_rm *rm = global_state->rm;
+ int i;
+
+ drm_puts(p, "resource mapping:\n");
+ drm_puts(p, "\tpingpong=");
+ for (i = 0; i < ARRAY_SIZE(global_state->pingpong_to_enc_id); i++)
+ dpu_rm_print_state_helper(p, rm->pingpong_blks[i],
+ global_state->pingpong_to_enc_id[i]);
+ drm_puts(p, "\n");
+
+ drm_puts(p, "\tmixer=");
+ for (i = 0; i < ARRAY_SIZE(global_state->mixer_to_enc_id); i++)
+ dpu_rm_print_state_helper(p, rm->mixer_blks[i],
+ global_state->mixer_to_enc_id[i]);
+ drm_puts(p, "\n");
+
+ drm_puts(p, "\tctl=");
+ for (i = 0; i < ARRAY_SIZE(global_state->ctl_to_enc_id); i++)
+ dpu_rm_print_state_helper(p, rm->ctl_blks[i],
+ global_state->ctl_to_enc_id[i]);
+ drm_puts(p, "\n");
+
+ drm_puts(p, "\tdspp=");
+ for (i = 0; i < ARRAY_SIZE(global_state->dspp_to_enc_id); i++)
+ dpu_rm_print_state_helper(p, rm->dspp_blks[i],
+ global_state->dspp_to_enc_id[i]);
+ drm_puts(p, "\n");
+
+ drm_puts(p, "\tdsc=");
+ for (i = 0; i < ARRAY_SIZE(global_state->dsc_to_enc_id); i++)
+ dpu_rm_print_state_helper(p, rm->dsc_blks[i],
+ global_state->dsc_to_enc_id[i]);
+ drm_puts(p, "\n");
+
+ drm_puts(p, "\tcdm=");
+ dpu_rm_print_state_helper(p, rm->cdm_blk,
+ global_state->cdm_to_enc_id);
+ drm_puts(p, "\n");
+}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index e3f83ebc656b..e63db8ace6b9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -90,6 +90,14 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size);
/**
+ * dpu_rm_print_state - output the RM private state
+ * @p: DRM printer
+ * @global_state: global state
+ */
+void dpu_rm_print_state(struct drm_printer *p,
+ const struct dpu_global_state *global_state);
+
+/**
* dpu_rm_get_intf - Return a struct dpu_hw_intf instance given it's index.
* @rm: DPU Resource Manager handle
* @intf_idx: INTF's index
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h b/drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h
deleted file mode 100644
index cc8fde450884..000000000000
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h
+++ /dev/null
@@ -1,1181 +0,0 @@
-#ifndef MDP4_XML
-#define MDP4_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
-
-Copyright (C) 2013-2022 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-enum mdp4_pipe {
- VG1 = 0,
- VG2 = 1,
- RGB1 = 2,
- RGB2 = 3,
- RGB3 = 4,
- VG3 = 5,
- VG4 = 6,
-};
-
-enum mdp4_mixer {
- MIXER0 = 0,
- MIXER1 = 1,
- MIXER2 = 2,
-};
-
-enum mdp4_intf {
- INTF_LCDC_DTV = 0,
- INTF_DSI_VIDEO = 1,
- INTF_DSI_CMD = 2,
- INTF_EBI2_TV = 3,
-};
-
-enum mdp4_cursor_format {
- CURSOR_ARGB = 1,
- CURSOR_XRGB = 2,
-};
-
-enum mdp4_frame_format {
- FRAME_LINEAR = 0,
- FRAME_TILE_ARGB_4X4 = 1,
- FRAME_TILE_YCBCR_420 = 2,
-};
-
-enum mdp4_scale_unit {
- SCALE_FIR = 0,
- SCALE_MN_PHASE = 1,
- SCALE_PIXEL_RPT = 2,
-};
-
-enum mdp4_dma {
- DMA_P = 0,
- DMA_S = 1,
- DMA_E = 2,
-};
-
-#define MDP4_IRQ_OVERLAY0_DONE 0x00000001
-#define MDP4_IRQ_OVERLAY1_DONE 0x00000002
-#define MDP4_IRQ_DMA_S_DONE 0x00000004
-#define MDP4_IRQ_DMA_E_DONE 0x00000008
-#define MDP4_IRQ_DMA_P_DONE 0x00000010
-#define MDP4_IRQ_VG1_HISTOGRAM 0x00000020
-#define MDP4_IRQ_VG2_HISTOGRAM 0x00000040
-#define MDP4_IRQ_PRIMARY_VSYNC 0x00000080
-#define MDP4_IRQ_PRIMARY_INTF_UDERRUN 0x00000100
-#define MDP4_IRQ_EXTERNAL_VSYNC 0x00000200
-#define MDP4_IRQ_EXTERNAL_INTF_UDERRUN 0x00000400
-#define MDP4_IRQ_PRIMARY_RDPTR 0x00000800
-#define MDP4_IRQ_DMA_P_HISTOGRAM 0x00020000
-#define MDP4_IRQ_DMA_S_HISTOGRAM 0x04000000
-#define MDP4_IRQ_OVERLAY2_DONE 0x40000000
-#define REG_MDP4_VERSION 0x00000000
-#define MDP4_VERSION_MINOR__MASK 0x00ff0000
-#define MDP4_VERSION_MINOR__SHIFT 16
-static inline uint32_t MDP4_VERSION_MINOR(uint32_t val)
-{
- return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK;
-}
-#define MDP4_VERSION_MAJOR__MASK 0xff000000
-#define MDP4_VERSION_MAJOR__SHIFT 24
-static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val)
-{
- return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK;
-}
-
-#define REG_MDP4_OVLP0_KICK 0x00000004
-
-#define REG_MDP4_OVLP1_KICK 0x00000008
-
-#define REG_MDP4_OVLP2_KICK 0x000000d0
-
-#define REG_MDP4_DMA_P_KICK 0x0000000c
-
-#define REG_MDP4_DMA_S_KICK 0x00000010
-
-#define REG_MDP4_DMA_E_KICK 0x00000014
-
-#define REG_MDP4_DISP_STATUS 0x00000018
-
-#define REG_MDP4_DISP_INTF_SEL 0x00000038
-#define MDP4_DISP_INTF_SEL_PRIM__MASK 0x00000003
-#define MDP4_DISP_INTF_SEL_PRIM__SHIFT 0
-static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)
-{
- return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK;
-}
-#define MDP4_DISP_INTF_SEL_SEC__MASK 0x0000000c
-#define MDP4_DISP_INTF_SEL_SEC__SHIFT 2
-static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)
-{
- return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK;
-}
-#define MDP4_DISP_INTF_SEL_EXT__MASK 0x00000030
-#define MDP4_DISP_INTF_SEL_EXT__SHIFT 4
-static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)
-{
- return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK;
-}
-#define MDP4_DISP_INTF_SEL_DSI_VIDEO 0x00000040
-#define MDP4_DISP_INTF_SEL_DSI_CMD 0x00000080
-
-#define REG_MDP4_RESET_STATUS 0x0000003c
-
-#define REG_MDP4_READ_CNFG 0x0000004c
-
-#define REG_MDP4_INTR_ENABLE 0x00000050
-
-#define REG_MDP4_INTR_STATUS 0x00000054
-
-#define REG_MDP4_INTR_CLEAR 0x00000058
-
-#define REG_MDP4_EBI2_LCD0 0x00000060
-
-#define REG_MDP4_EBI2_LCD1 0x00000064
-
-#define REG_MDP4_PORTMAP_MODE 0x00000070
-
-#define REG_MDP4_CS_CONTROLLER0 0x000000c0
-
-#define REG_MDP4_CS_CONTROLLER1 0x000000c4
-
-#define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0
-static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;
-}
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4
-static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;
-}
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8
-static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;
-}
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12
-static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;
-}
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16
-static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;
-}
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20
-static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;
-}
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24
-static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;
-}
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28
-static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;
-}
-#define MDP4_LAYERMIXER2_IN_CFG_PIPE7_MIXER1 0x80000000
-
-#define REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD 0x000100fc
-
-#define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100
-#define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007
-#define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0
-static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;
-}
-#define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008
-#define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070
-#define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4
-static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;
-}
-#define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080
-#define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700
-#define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8
-static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;
-}
-#define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800
-#define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000
-#define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12
-static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;
-}
-#define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000
-#define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000
-#define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16
-static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;
-}
-#define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000
-#define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000
-#define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20
-static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;
-}
-#define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000
-#define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000
-#define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24
-static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;
-}
-#define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000
-#define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000
-#define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28
-static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;
-}
-#define MDP4_LAYERMIXER_IN_CFG_PIPE7_MIXER1 0x80000000
-
-#define REG_MDP4_VG2_SRC_FORMAT 0x00030050
-
-#define REG_MDP4_VG2_CONST_COLOR 0x00031008
-
-#define REG_MDP4_OVERLAY_FLUSH 0x00018000
-#define MDP4_OVERLAY_FLUSH_OVLP0 0x00000001
-#define MDP4_OVERLAY_FLUSH_OVLP1 0x00000002
-#define MDP4_OVERLAY_FLUSH_VG1 0x00000004
-#define MDP4_OVERLAY_FLUSH_VG2 0x00000008
-#define MDP4_OVERLAY_FLUSH_RGB1 0x00000010
-#define MDP4_OVERLAY_FLUSH_RGB2 0x00000020
-
-static inline uint32_t __offset_OVLP(uint32_t idx)
-{
- switch (idx) {
- case 0: return 0x00010000;
- case 1: return 0x00018000;
- case 2: return 0x00088000;
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); }
-
-static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); }
-
-static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); }
-#define MDP4_OVLP_SIZE_HEIGHT__MASK 0xffff0000
-#define MDP4_OVLP_SIZE_HEIGHT__SHIFT 16
-static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val)
-{
- return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK;
-}
-#define MDP4_OVLP_SIZE_WIDTH__MASK 0x0000ffff
-#define MDP4_OVLP_SIZE_WIDTH__SHIFT 0
-static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val)
-{
- return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK;
-}
-
-static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); }
-
-static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); }
-
-static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); }
-
-static inline uint32_t __offset_STAGE(uint32_t idx)
-{
- switch (idx) {
- case 0: return 0x00000104;
- case 1: return 0x00000124;
- case 2: return 0x00000144;
- case 3: return 0x00000160;
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
-
-static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
-#define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003
-#define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0
-static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)
-{
- return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;
-}
-#define MDP4_OVLP_STAGE_OP_FG_INV_ALPHA 0x00000004
-#define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008
-#define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030
-#define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4
-static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)
-{
- return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;
-}
-#define MDP4_OVLP_STAGE_OP_BG_INV_ALPHA 0x00000040
-#define MDP4_OVLP_STAGE_OP_BG_MOD_ALPHA 0x00000080
-#define MDP4_OVLP_STAGE_OP_FG_TRANSP 0x00000100
-#define MDP4_OVLP_STAGE_OP_BG_TRANSP 0x00000200
-
-static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); }
-
-static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); }
-
-static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); }
-
-static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); }
-
-static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); }
-
-static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); }
-
-static inline uint32_t __offset_STAGE_CO3(uint32_t idx)
-{
- switch (idx) {
- case 0: return 0x00001004;
- case 1: return 0x00001404;
- case 2: return 0x00001804;
- case 3: return 0x00001b84;
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
-
-static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); }
-#define MDP4_OVLP_STAGE_CO3_SEL_FG_ALPHA 0x00000001
-
-static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); }
-
-static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); }
-
-static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); }
-
-static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); }
-
-static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); }
-
-static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); }
-
-
-static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; }
-
-#define REG_MDP4_DMA_P_OP_MODE 0x00090070
-
-static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; }
-
-static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; }
-
-#define REG_MDP4_DMA_S_OP_MODE 0x000a0028
-
-static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; }
-
-static inline uint32_t __offset_DMA(enum mdp4_dma idx)
-{
- switch (idx) {
- case DMA_P: return 0x00090000;
- case DMA_S: return 0x000a0000;
- case DMA_E: return 0x000b0000;
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
-
-static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
-#define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003
-#define MDP4_DMA_CONFIG_G_BPC__SHIFT 0
-static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)
-{
- return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;
-}
-#define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c
-#define MDP4_DMA_CONFIG_B_BPC__SHIFT 2
-static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)
-{
- return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;
-}
-#define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030
-#define MDP4_DMA_CONFIG_R_BPC__SHIFT 4
-static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)
-{
- return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;
-}
-#define MDP4_DMA_CONFIG_PACK_ALIGN_MSB 0x00000080
-#define MDP4_DMA_CONFIG_PACK__MASK 0x0000ff00
-#define MDP4_DMA_CONFIG_PACK__SHIFT 8
-static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val)
-{
- return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK;
-}
-#define MDP4_DMA_CONFIG_DEFLKR_EN 0x01000000
-#define MDP4_DMA_CONFIG_DITHER_EN 0x01000000
-
-static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); }
-#define MDP4_DMA_SRC_SIZE_HEIGHT__MASK 0xffff0000
-#define MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT 16
-static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val)
-{
- return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK;
-}
-#define MDP4_DMA_SRC_SIZE_WIDTH__MASK 0x0000ffff
-#define MDP4_DMA_SRC_SIZE_WIDTH__SHIFT 0
-static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val)
-{
- return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK;
-}
-
-static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); }
-
-static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); }
-
-static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); }
-#define MDP4_DMA_DST_SIZE_HEIGHT__MASK 0xffff0000
-#define MDP4_DMA_DST_SIZE_HEIGHT__SHIFT 16
-static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val)
-{
- return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK;
-}
-#define MDP4_DMA_DST_SIZE_WIDTH__MASK 0x0000ffff
-#define MDP4_DMA_DST_SIZE_WIDTH__SHIFT 0
-static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val)
-{
- return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK;
-}
-
-static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); }
-#define MDP4_DMA_CURSOR_SIZE_WIDTH__MASK 0x0000007f
-#define MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT 0
-static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val)
-{
- return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK;
-}
-#define MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK 0x007f0000
-#define MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT 16
-static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val)
-{
- return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK;
-}
-
-static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); }
-
-static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); }
-#define MDP4_DMA_CURSOR_POS_X__MASK 0x0000ffff
-#define MDP4_DMA_CURSOR_POS_X__SHIFT 0
-static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val)
-{
- return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK;
-}
-#define MDP4_DMA_CURSOR_POS_Y__MASK 0xffff0000
-#define MDP4_DMA_CURSOR_POS_Y__SHIFT 16
-static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val)
-{
- return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK;
-}
-
-static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); }
-#define MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN 0x00000001
-#define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK 0x00000006
-#define MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT 1
-static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)
-{
- return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__MASK;
-}
-#define MDP4_DMA_CURSOR_BLEND_CONFIG_TRANSP_EN 0x00000008
-
-static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); }
-
-static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); }
-
-static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); }
-
-static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); }
-
-static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); }
-
-
-static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
-
-static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }
-#define MDP4_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
-#define MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
-static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK;
-}
-#define MDP4_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
-#define MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT 0
-static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK;
-}
-
-static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; }
-#define MDP4_PIPE_SRC_XY_Y__MASK 0xffff0000
-#define MDP4_PIPE_SRC_XY_Y__SHIFT 16
-static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK;
-}
-#define MDP4_PIPE_SRC_XY_X__MASK 0x0000ffff
-#define MDP4_PIPE_SRC_XY_X__SHIFT 0
-static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK;
-}
-
-static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; }
-#define MDP4_PIPE_DST_SIZE_HEIGHT__MASK 0xffff0000
-#define MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT 16
-static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)
-{
- return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK;
-}
-#define MDP4_PIPE_DST_SIZE_WIDTH__MASK 0x0000ffff
-#define MDP4_PIPE_DST_SIZE_WIDTH__SHIFT 0
-static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)
-{
- return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK;
-}
-
-static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; }
-#define MDP4_PIPE_DST_XY_Y__MASK 0xffff0000
-#define MDP4_PIPE_DST_XY_Y__SHIFT 16
-static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val)
-{
- return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK;
-}
-#define MDP4_PIPE_DST_XY_X__MASK 0x0000ffff
-#define MDP4_PIPE_DST_XY_X__SHIFT 0
-static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val)
-{
- return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK;
-}
-
-static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; }
-
-static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; }
-
-static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; }
-
-static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0; }
-
-static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; }
-#define MDP4_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
-#define MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT 0
-static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK;
-}
-#define MDP4_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
-#define MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT 16
-static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK;
-}
-
-static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; }
-#define MDP4_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
-#define MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT 0
-static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK;
-}
-#define MDP4_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
-#define MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT 16
-static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK;
-}
-
-static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; }
-#define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK 0xffff0000
-#define MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT 16
-static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__MASK;
-}
-#define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK 0x0000ffff
-#define MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT 0
-static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MASK;
-}
-
-static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; }
-#define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
-#define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
-static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
-{
- return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;
-}
-#define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
-#define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
-static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
-{
- return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;
-}
-#define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
-#define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
-static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
-{
- return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;
-}
-#define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
-#define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
-static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
-{
- return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;
-}
-#define MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
-#define MDP4_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
-#define MDP4_PIPE_SRC_FORMAT_CPP__SHIFT 9
-static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK;
-}
-#define MDP4_PIPE_SRC_FORMAT_ROTATED_90 0x00001000
-#define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00006000
-#define MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 13
-static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
-}
-#define MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
-#define MDP4_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
-#define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK 0x00180000
-#define MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT 19
-static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MASK;
-}
-#define MDP4_PIPE_SRC_FORMAT_SOLID_FILL 0x00400000
-#define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x0c000000
-#define MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 26
-static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
-{
- return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
-}
-#define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK 0x60000000
-#define MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT 29
-static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val)
-{
- return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MASK;
-}
-
-static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; }
-#define MDP4_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
-#define MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
-static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK;
-}
-#define MDP4_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
-#define MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
-static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK;
-}
-#define MDP4_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
-#define MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
-static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK;
-}
-#define MDP4_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
-#define MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
-static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
-{
- return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK;
-}
-
-static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; }
-#define MDP4_PIPE_OP_MODE_SCALEX_EN 0x00000001
-#define MDP4_PIPE_OP_MODE_SCALEY_EN 0x00000002
-#define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK 0x0000000c
-#define MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT 2
-static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val)
-{
- return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MASK;
-}
-#define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK 0x00000030
-#define MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT 4
-static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val)
-{
- return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MASK;
-}
-#define MDP4_PIPE_OP_MODE_SRC_YCBCR 0x00000200
-#define MDP4_PIPE_OP_MODE_DST_YCBCR 0x00000400
-#define MDP4_PIPE_OP_MODE_CSC_EN 0x00000800
-#define MDP4_PIPE_OP_MODE_FLIP_LR 0x00002000
-#define MDP4_PIPE_OP_MODE_FLIP_UD 0x00004000
-#define MDP4_PIPE_OP_MODE_DITHER_EN 0x00008000
-#define MDP4_PIPE_OP_MODE_IGC_LUT_EN 0x00010000
-#define MDP4_PIPE_OP_MODE_DEINT_EN 0x00040000
-#define MDP4_PIPE_OP_MODE_DEINT_ODD_REF 0x00080000
-
-static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; }
-
-static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; }
-
-static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; }
-
-static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; }
-
-static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; }
-
-
-static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
-
-static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; }
-
-#define REG_MDP4_LCDC 0x000c0000
-
-#define REG_MDP4_LCDC_ENABLE 0x000c0000
-
-#define REG_MDP4_LCDC_HSYNC_CTRL 0x000c0004
-#define MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
-#define MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT 0
-static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val)
-{
- return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK;
-}
-#define MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK 0xffff0000
-#define MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT 16
-static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val)
-{
- return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK;
-}
-
-#define REG_MDP4_LCDC_VSYNC_PERIOD 0x000c0008
-
-#define REG_MDP4_LCDC_VSYNC_LEN 0x000c000c
-
-#define REG_MDP4_LCDC_DISPLAY_HCTRL 0x000c0010
-#define MDP4_LCDC_DISPLAY_HCTRL_START__MASK 0x0000ffff
-#define MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT 0
-static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val)
-{
- return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK;
-}
-#define MDP4_LCDC_DISPLAY_HCTRL_END__MASK 0xffff0000
-#define MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT 16
-static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val)
-{
- return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK;
-}
-
-#define REG_MDP4_LCDC_DISPLAY_VSTART 0x000c0014
-
-#define REG_MDP4_LCDC_DISPLAY_VEND 0x000c0018
-
-#define REG_MDP4_LCDC_ACTIVE_HCTL 0x000c001c
-#define MDP4_LCDC_ACTIVE_HCTL_START__MASK 0x00007fff
-#define MDP4_LCDC_ACTIVE_HCTL_START__SHIFT 0
-static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val)
-{
- return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK;
-}
-#define MDP4_LCDC_ACTIVE_HCTL_END__MASK 0x7fff0000
-#define MDP4_LCDC_ACTIVE_HCTL_END__SHIFT 16
-static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val)
-{
- return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK;
-}
-#define MDP4_LCDC_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
-
-#define REG_MDP4_LCDC_ACTIVE_VSTART 0x000c0020
-
-#define REG_MDP4_LCDC_ACTIVE_VEND 0x000c0024
-
-#define REG_MDP4_LCDC_BORDER_CLR 0x000c0028
-
-#define REG_MDP4_LCDC_UNDERFLOW_CLR 0x000c002c
-#define MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
-#define MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT 0
-static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val)
-{
- return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK;
-}
-#define MDP4_LCDC_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
-
-#define REG_MDP4_LCDC_HSYNC_SKEW 0x000c0030
-
-#define REG_MDP4_LCDC_TEST_CNTL 0x000c0034
-
-#define REG_MDP4_LCDC_CTRL_POLARITY 0x000c0038
-#define MDP4_LCDC_CTRL_POLARITY_HSYNC_LOW 0x00000001
-#define MDP4_LCDC_CTRL_POLARITY_VSYNC_LOW 0x00000002
-#define MDP4_LCDC_CTRL_POLARITY_DATA_EN_LOW 0x00000004
-
-#define REG_MDP4_LCDC_LVDS_INTF_CTL 0x000c2000
-#define MDP4_LCDC_LVDS_INTF_CTL_MODE_SEL 0x00000004
-#define MDP4_LCDC_LVDS_INTF_CTL_RGB_OUT 0x00000008
-#define MDP4_LCDC_LVDS_INTF_CTL_CH_SWAP 0x00000010
-#define MDP4_LCDC_LVDS_INTF_CTL_CH1_RES_BIT 0x00000020
-#define MDP4_LCDC_LVDS_INTF_CTL_CH2_RES_BIT 0x00000040
-#define MDP4_LCDC_LVDS_INTF_CTL_ENABLE 0x00000080
-#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE0_EN 0x00000100
-#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE1_EN 0x00000200
-#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE2_EN 0x00000400
-#define MDP4_LCDC_LVDS_INTF_CTL_CH1_DATA_LANE3_EN 0x00000800
-#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE0_EN 0x00001000
-#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE1_EN 0x00002000
-#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE2_EN 0x00004000
-#define MDP4_LCDC_LVDS_INTF_CTL_CH2_DATA_LANE3_EN 0x00008000
-#define MDP4_LCDC_LVDS_INTF_CTL_CH1_CLK_LANE_EN 0x00010000
-#define MDP4_LCDC_LVDS_INTF_CTL_CH2_CLK_LANE_EN 0x00020000
-
-static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; }
-
-static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0; }
-#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK 0x000000ff
-#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT 0
-static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val)
-{
- return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__MASK;
-}
-#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK 0x0000ff00
-#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT 8
-static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val)
-{
- return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__MASK;
-}
-#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK 0x00ff0000
-#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT 16
-static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val)
-{
- return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__MASK;
-}
-#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK 0xff000000
-#define MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT 24
-static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val)
-{
- return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__MASK;
-}
-
-static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0; }
-#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK 0x000000ff
-#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT 0
-static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val)
-{
- return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__MASK;
-}
-#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK 0x0000ff00
-#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT 8
-static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val)
-{
- return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__MASK;
-}
-#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK 0x00ff0000
-#define MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT 16
-static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val)
-{
- return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__MASK;
-}
-
-#define REG_MDP4_LCDC_LVDS_PHY_RESET 0x000c2034
-
-#define REG_MDP4_LVDS_PHY_PLL_CTRL_0 0x000c3000
-
-#define REG_MDP4_LVDS_PHY_PLL_CTRL_1 0x000c3004
-
-#define REG_MDP4_LVDS_PHY_PLL_CTRL_2 0x000c3008
-
-#define REG_MDP4_LVDS_PHY_PLL_CTRL_3 0x000c300c
-
-#define REG_MDP4_LVDS_PHY_PLL_CTRL_5 0x000c3014
-
-#define REG_MDP4_LVDS_PHY_PLL_CTRL_6 0x000c3018
-
-#define REG_MDP4_LVDS_PHY_PLL_CTRL_7 0x000c301c
-
-#define REG_MDP4_LVDS_PHY_PLL_CTRL_8 0x000c3020
-
-#define REG_MDP4_LVDS_PHY_PLL_CTRL_9 0x000c3024
-
-#define REG_MDP4_LVDS_PHY_PLL_LOCKED 0x000c3080
-
-#define REG_MDP4_LVDS_PHY_CFG2 0x000c3108
-
-#define REG_MDP4_LVDS_PHY_CFG0 0x000c3100
-#define MDP4_LVDS_PHY_CFG0_SERIALIZATION_ENBLE 0x00000010
-#define MDP4_LVDS_PHY_CFG0_CHANNEL0 0x00000040
-#define MDP4_LVDS_PHY_CFG0_CHANNEL1 0x00000080
-
-#define REG_MDP4_DTV 0x000d0000
-
-#define REG_MDP4_DTV_ENABLE 0x000d0000
-
-#define REG_MDP4_DTV_HSYNC_CTRL 0x000d0004
-#define MDP4_DTV_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
-#define MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT 0
-static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val)
-{
- return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK;
-}
-#define MDP4_DTV_HSYNC_CTRL_PERIOD__MASK 0xffff0000
-#define MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT 16
-static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val)
-{
- return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK;
-}
-
-#define REG_MDP4_DTV_VSYNC_PERIOD 0x000d0008
-
-#define REG_MDP4_DTV_VSYNC_LEN 0x000d000c
-
-#define REG_MDP4_DTV_DISPLAY_HCTRL 0x000d0018
-#define MDP4_DTV_DISPLAY_HCTRL_START__MASK 0x0000ffff
-#define MDP4_DTV_DISPLAY_HCTRL_START__SHIFT 0
-static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val)
-{
- return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK;
-}
-#define MDP4_DTV_DISPLAY_HCTRL_END__MASK 0xffff0000
-#define MDP4_DTV_DISPLAY_HCTRL_END__SHIFT 16
-static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val)
-{
- return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK;
-}
-
-#define REG_MDP4_DTV_DISPLAY_VSTART 0x000d001c
-
-#define REG_MDP4_DTV_DISPLAY_VEND 0x000d0020
-
-#define REG_MDP4_DTV_ACTIVE_HCTL 0x000d002c
-#define MDP4_DTV_ACTIVE_HCTL_START__MASK 0x00007fff
-#define MDP4_DTV_ACTIVE_HCTL_START__SHIFT 0
-static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val)
-{
- return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK;
-}
-#define MDP4_DTV_ACTIVE_HCTL_END__MASK 0x7fff0000
-#define MDP4_DTV_ACTIVE_HCTL_END__SHIFT 16
-static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val)
-{
- return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK;
-}
-#define MDP4_DTV_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
-
-#define REG_MDP4_DTV_ACTIVE_VSTART 0x000d0030
-
-#define REG_MDP4_DTV_ACTIVE_VEND 0x000d0038
-
-#define REG_MDP4_DTV_BORDER_CLR 0x000d0040
-
-#define REG_MDP4_DTV_UNDERFLOW_CLR 0x000d0044
-#define MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
-#define MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT 0
-static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val)
-{
- return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK;
-}
-#define MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
-
-#define REG_MDP4_DTV_HSYNC_SKEW 0x000d0048
-
-#define REG_MDP4_DTV_TEST_CNTL 0x000d004c
-
-#define REG_MDP4_DTV_CTRL_POLARITY 0x000d0050
-#define MDP4_DTV_CTRL_POLARITY_HSYNC_LOW 0x00000001
-#define MDP4_DTV_CTRL_POLARITY_VSYNC_LOW 0x00000002
-#define MDP4_DTV_CTRL_POLARITY_DATA_EN_LOW 0x00000004
-
-#define REG_MDP4_DSI 0x000e0000
-
-#define REG_MDP4_DSI_ENABLE 0x000e0000
-
-#define REG_MDP4_DSI_HSYNC_CTRL 0x000e0004
-#define MDP4_DSI_HSYNC_CTRL_PULSEW__MASK 0x0000ffff
-#define MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT 0
-static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val)
-{
- return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK;
-}
-#define MDP4_DSI_HSYNC_CTRL_PERIOD__MASK 0xffff0000
-#define MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT 16
-static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val)
-{
- return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK;
-}
-
-#define REG_MDP4_DSI_VSYNC_PERIOD 0x000e0008
-
-#define REG_MDP4_DSI_VSYNC_LEN 0x000e000c
-
-#define REG_MDP4_DSI_DISPLAY_HCTRL 0x000e0010
-#define MDP4_DSI_DISPLAY_HCTRL_START__MASK 0x0000ffff
-#define MDP4_DSI_DISPLAY_HCTRL_START__SHIFT 0
-static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val)
-{
- return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK;
-}
-#define MDP4_DSI_DISPLAY_HCTRL_END__MASK 0xffff0000
-#define MDP4_DSI_DISPLAY_HCTRL_END__SHIFT 16
-static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val)
-{
- return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK;
-}
-
-#define REG_MDP4_DSI_DISPLAY_VSTART 0x000e0014
-
-#define REG_MDP4_DSI_DISPLAY_VEND 0x000e0018
-
-#define REG_MDP4_DSI_ACTIVE_HCTL 0x000e001c
-#define MDP4_DSI_ACTIVE_HCTL_START__MASK 0x00007fff
-#define MDP4_DSI_ACTIVE_HCTL_START__SHIFT 0
-static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val)
-{
- return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK;
-}
-#define MDP4_DSI_ACTIVE_HCTL_END__MASK 0x7fff0000
-#define MDP4_DSI_ACTIVE_HCTL_END__SHIFT 16
-static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val)
-{
- return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK;
-}
-#define MDP4_DSI_ACTIVE_HCTL_ACTIVE_START_X 0x80000000
-
-#define REG_MDP4_DSI_ACTIVE_VSTART 0x000e0020
-
-#define REG_MDP4_DSI_ACTIVE_VEND 0x000e0024
-
-#define REG_MDP4_DSI_BORDER_CLR 0x000e0028
-
-#define REG_MDP4_DSI_UNDERFLOW_CLR 0x000e002c
-#define MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK 0x00ffffff
-#define MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT 0
-static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val)
-{
- return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK;
-}
-#define MDP4_DSI_UNDERFLOW_CLR_ENABLE_RECOVERY 0x80000000
-
-#define REG_MDP4_DSI_HSYNC_SKEW 0x000e0030
-
-#define REG_MDP4_DSI_TEST_CNTL 0x000e0034
-
-#define REG_MDP4_DSI_CTRL_POLARITY 0x000e0038
-#define MDP4_DSI_CTRL_POLARITY_HSYNC_LOW 0x00000001
-#define MDP4_DSI_CTRL_POLARITY_VSYNC_LOW 0x00000002
-#define MDP4_DSI_CTRL_POLARITY_DATA_EN_LOW 0x00000004
-
-
-#endif /* MDP4_XML */
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
index 75f93e346282..b8610aa806ea 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c
@@ -182,8 +182,8 @@ static void blend_setup(struct drm_crtc *crtc)
enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
int idx = idxs[pipe_id];
if (idx > 0) {
- const struct mdp_format *format =
- to_mdp_format(msm_framebuffer_format(plane->state->fb));
+ const struct msm_format *format =
+ msm_framebuffer_format(plane->state->fb);
alpha[idx-1] = format->alpha_enable;
}
}
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
index 4ba1cb74ad76..6e4e74f9d63d 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c
@@ -151,7 +151,6 @@ static const struct mdp_kms_funcs kms_funcs = {
.flush_commit = mdp4_flush_commit,
.wait_flush = mdp4_wait_flush,
.complete_commit = mdp4_complete_commit,
- .get_format = mdp_get_format,
.round_pixclk = mdp4_round_pixclk,
.destroy = mdp4_destroy,
},
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
index 01179e764a29..94b1ba92785f 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
@@ -44,12 +44,12 @@ struct mdp4_kms {
static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
{
- msm_writel(data, mdp4_kms->mmio + reg);
+ writel(data, mdp4_kms->mmio + reg);
}
static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
{
- return msm_readl(mdp4_kms->mmio + reg);
+ return readl(mdp4_kms->mmio + reg);
}
static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
index b689b618da78..3fefb2088008 100644
--- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_plane.c
@@ -20,12 +20,6 @@ struct mdp4_plane {
const char *name;
enum mdp4_pipe pipe;
-
- uint32_t caps;
- uint32_t nformats;
- uint32_t formats[32];
-
- bool enabled;
};
#define to_mdp4_plane(x) container_of(x, struct mdp4_plane, base)
@@ -59,15 +53,6 @@ static struct mdp4_kms *get_kms(struct drm_plane *plane)
return to_mdp4_kms(to_mdp_kms(priv->kms));
}
-static void mdp4_plane_destroy(struct drm_plane *plane)
-{
- struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
-
- drm_plane_cleanup(plane);
-
- kfree(mdp4_plane);
-}
-
/* helper to install properties which are common to planes and crtcs */
static void mdp4_plane_install_properties(struct drm_plane *plane,
struct drm_mode_object *obj)
@@ -85,7 +70,6 @@ static int mdp4_plane_set_property(struct drm_plane *plane,
static const struct drm_plane_funcs mdp4_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
- .destroy = mdp4_plane_destroy,
.set_property = mdp4_plane_set_property,
.reset = drm_atomic_helper_plane_reset,
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
@@ -218,7 +202,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
struct mdp4_kms *mdp4_kms = get_kms(plane);
enum mdp4_pipe pipe = mdp4_plane->pipe;
- const struct mdp_format *format;
+ const struct msm_format *format;
uint32_t op_mode = 0;
uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT;
@@ -241,7 +225,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
fb->base.id, src_x, src_y, src_w, src_h,
crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
- format = to_mdp_format(msm_framebuffer_format(fb));
+ format = msm_framebuffer_format(fb);
if (src_w > (crtc_w * DOWN_SCALE_MAX)) {
DRM_DEV_ERROR(dev->dev, "Width down scaling exceeds limits!\n");
@@ -267,7 +251,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
uint32_t sel_unit = SCALE_FIR;
op_mode |= MDP4_PIPE_OP_MODE_SCALEX_EN;
- if (MDP_FORMAT_IS_YUV(format)) {
+ if (MSM_FORMAT_IS_YUV(format)) {
if (crtc_w > src_w)
sel_unit = SCALE_PIXEL_RPT;
else if (crtc_w <= (src_w / 4))
@@ -283,7 +267,7 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
uint32_t sel_unit = SCALE_FIR;
op_mode |= MDP4_PIPE_OP_MODE_SCALEY_EN;
- if (MDP_FORMAT_IS_YUV(format)) {
+ if (MSM_FORMAT_IS_YUV(format)) {
if (crtc_h > src_h)
sel_unit = SCALE_PIXEL_RPT;
@@ -316,24 +300,25 @@ static int mdp4_plane_mode_set(struct drm_plane *plane,
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_FORMAT(pipe),
MDP4_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
- MDP4_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
- MDP4_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
- MDP4_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
+ MDP4_PIPE_SRC_FORMAT_R_BPC(format->bpc_r_cr) |
+ MDP4_PIPE_SRC_FORMAT_G_BPC(format->bpc_g_y) |
+ MDP4_PIPE_SRC_FORMAT_B_BPC(format->bpc_b_cb) |
COND(format->alpha_enable, MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
- MDP4_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
+ MDP4_PIPE_SRC_FORMAT_CPP(format->bpp - 1) |
MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) |
MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample) |
MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(frame_type) |
- COND(format->unpack_tight, MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));
+ COND(format->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT,
+ MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe),
- MDP4_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
- MDP4_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
- MDP4_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
- MDP4_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
+ MDP4_PIPE_SRC_UNPACK_ELEM0(format->element[0]) |
+ MDP4_PIPE_SRC_UNPACK_ELEM1(format->element[1]) |
+ MDP4_PIPE_SRC_UNPACK_ELEM2(format->element[2]) |
+ MDP4_PIPE_SRC_UNPACK_ELEM3(format->element[3]));
- if (MDP_FORMAT_IS_YUV(format)) {
+ if (MSM_FORMAT_IS_YUV(format)) {
struct csc_cfg *csc = mdp_get_default_csc_cfg(CSC_YUV2RGB);
op_mode |= MDP4_PIPE_OP_MODE_SRC_YCBCR;
@@ -371,37 +356,81 @@ static const uint64_t supported_format_modifiers[] = {
DRM_FORMAT_MOD_INVALID
};
+static const uint32_t mdp4_rgb_formats[] = {
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_RGBA8888,
+ DRM_FORMAT_BGRA8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_RGBX8888,
+ DRM_FORMAT_BGRX8888,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+};
+
+static const uint32_t mdp4_rgb_yuv_formats[] = {
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_RGBA8888,
+ DRM_FORMAT_BGRA8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_RGBX8888,
+ DRM_FORMAT_BGRX8888,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_NV21,
+ DRM_FORMAT_NV16,
+ DRM_FORMAT_NV61,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_YUV420,
+ DRM_FORMAT_YVU420,
+};
+
/* initialize plane */
struct drm_plane *mdp4_plane_init(struct drm_device *dev,
enum mdp4_pipe pipe_id, bool private_plane)
{
struct drm_plane *plane = NULL;
struct mdp4_plane *mdp4_plane;
- int ret;
enum drm_plane_type type;
+ uint32_t pipe_caps;
+ const uint32_t *formats;
+ size_t nformats;
- mdp4_plane = kzalloc(sizeof(*mdp4_plane), GFP_KERNEL);
- if (!mdp4_plane) {
- ret = -ENOMEM;
- goto fail;
+ type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
+
+ pipe_caps = mdp4_pipe_caps(pipe_id);
+ if (pipe_supports_yuv(pipe_caps)) {
+ formats = mdp4_rgb_yuv_formats;
+ nformats = ARRAY_SIZE(mdp4_rgb_yuv_formats);
+ } else {
+ formats = mdp4_rgb_formats;
+ nformats = ARRAY_SIZE(mdp4_rgb_formats);
}
+ mdp4_plane = drmm_universal_plane_alloc(dev, struct mdp4_plane, base,
+ 0xff, &mdp4_plane_funcs,
+ formats, nformats,
+ supported_format_modifiers,
+ type, NULL);
+ if (IS_ERR(mdp4_plane))
+ return ERR_CAST(mdp4_plane);
+
plane = &mdp4_plane->base;
mdp4_plane->pipe = pipe_id;
mdp4_plane->name = pipe_names[pipe_id];
- mdp4_plane->caps = mdp4_pipe_caps(pipe_id);
-
- mdp4_plane->nformats = mdp_get_formats(mdp4_plane->formats,
- ARRAY_SIZE(mdp4_plane->formats),
- !pipe_supports_yuv(mdp4_plane->caps));
-
- type = private_plane ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
- ret = drm_universal_plane_init(dev, plane, 0xff, &mdp4_plane_funcs,
- mdp4_plane->formats, mdp4_plane->nformats,
- supported_format_modifiers, type, NULL);
- if (ret)
- goto fail;
drm_plane_helper_add(plane, &mdp4_plane_helper_funcs);
@@ -410,10 +439,4 @@ struct drm_plane *mdp4_plane_init(struct drm_device *dev,
drm_plane_enable_fb_damage_clips(plane);
return plane;
-
-fail:
- if (plane)
- mdp4_plane_destroy(plane);
-
- return ERR_PTR(ret);
}
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h
deleted file mode 100644
index 270e11c904bd..000000000000
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h
+++ /dev/null
@@ -1,1979 +0,0 @@
-#ifndef MDP5_XML
-#define MDP5_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
-
-Copyright (C) 2013-2022 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-enum mdp5_intf_type {
- INTF_DISABLED = 0,
- INTF_DSI = 1,
- INTF_HDMI = 3,
- INTF_LCDC = 5,
- INTF_eDP = 9,
- INTF_VIRTUAL = 100,
- INTF_WB = 101,
-};
-
-enum mdp5_intfnum {
- NO_INTF = 0,
- INTF0 = 1,
- INTF1 = 2,
- INTF2 = 3,
- INTF3 = 4,
-};
-
-enum mdp5_pipe {
- SSPP_NONE = 0,
- SSPP_VIG0 = 1,
- SSPP_VIG1 = 2,
- SSPP_VIG2 = 3,
- SSPP_RGB0 = 4,
- SSPP_RGB1 = 5,
- SSPP_RGB2 = 6,
- SSPP_DMA0 = 7,
- SSPP_DMA1 = 8,
- SSPP_VIG3 = 9,
- SSPP_RGB3 = 10,
- SSPP_CURSOR0 = 11,
- SSPP_CURSOR1 = 12,
-};
-
-enum mdp5_format {
- DUMMY = 0,
-};
-
-enum mdp5_ctl_mode {
- MODE_NONE = 0,
- MODE_WB_0_BLOCK = 1,
- MODE_WB_1_BLOCK = 2,
- MODE_WB_0_LINE = 3,
- MODE_WB_1_LINE = 4,
- MODE_WB_2_LINE = 5,
-};
-
-enum mdp5_pack_3d {
- PACK_3D_FRAME_INT = 0,
- PACK_3D_H_ROW_INT = 1,
- PACK_3D_V_ROW_INT = 2,
- PACK_3D_COL_INT = 3,
-};
-
-enum mdp5_scale_filter {
- SCALE_FILTER_NEAREST = 0,
- SCALE_FILTER_BIL = 1,
- SCALE_FILTER_PCMN = 2,
- SCALE_FILTER_CA = 3,
-};
-
-enum mdp5_pipe_bwc {
- BWC_LOSSLESS = 0,
- BWC_Q_HIGH = 1,
- BWC_Q_MED = 2,
-};
-
-enum mdp5_cursor_format {
- CURSOR_FMT_ARGB8888 = 0,
- CURSOR_FMT_ARGB1555 = 2,
- CURSOR_FMT_ARGB4444 = 4,
-};
-
-enum mdp5_cursor_alpha {
- CURSOR_ALPHA_CONST = 0,
- CURSOR_ALPHA_PER_PIXEL = 2,
-};
-
-enum mdp5_igc_type {
- IGC_VIG = 0,
- IGC_RGB = 1,
- IGC_DMA = 2,
- IGC_DSPP = 3,
-};
-
-enum mdp5_data_format {
- DATA_FORMAT_RGB = 0,
- DATA_FORMAT_YUV = 1,
-};
-
-enum mdp5_block_size {
- BLOCK_SIZE_64 = 0,
- BLOCK_SIZE_128 = 1,
-};
-
-enum mdp5_rotate_mode {
- ROTATE_0 = 0,
- ROTATE_90 = 1,
-};
-
-enum mdp5_chroma_downsample_method {
- DS_MTHD_NO_PIXEL_DROP = 0,
- DS_MTHD_PIXEL_DROP = 1,
-};
-
-#define MDP5_IRQ_WB_0_DONE 0x00000001
-#define MDP5_IRQ_WB_1_DONE 0x00000002
-#define MDP5_IRQ_WB_2_DONE 0x00000010
-#define MDP5_IRQ_PING_PONG_0_DONE 0x00000100
-#define MDP5_IRQ_PING_PONG_1_DONE 0x00000200
-#define MDP5_IRQ_PING_PONG_2_DONE 0x00000400
-#define MDP5_IRQ_PING_PONG_3_DONE 0x00000800
-#define MDP5_IRQ_PING_PONG_0_RD_PTR 0x00001000
-#define MDP5_IRQ_PING_PONG_1_RD_PTR 0x00002000
-#define MDP5_IRQ_PING_PONG_2_RD_PTR 0x00004000
-#define MDP5_IRQ_PING_PONG_3_RD_PTR 0x00008000
-#define MDP5_IRQ_PING_PONG_0_WR_PTR 0x00010000
-#define MDP5_IRQ_PING_PONG_1_WR_PTR 0x00020000
-#define MDP5_IRQ_PING_PONG_2_WR_PTR 0x00040000
-#define MDP5_IRQ_PING_PONG_3_WR_PTR 0x00080000
-#define MDP5_IRQ_PING_PONG_0_AUTO_REF 0x00100000
-#define MDP5_IRQ_PING_PONG_1_AUTO_REF 0x00200000
-#define MDP5_IRQ_PING_PONG_2_AUTO_REF 0x00400000
-#define MDP5_IRQ_PING_PONG_3_AUTO_REF 0x00800000
-#define MDP5_IRQ_INTF0_UNDER_RUN 0x01000000
-#define MDP5_IRQ_INTF0_VSYNC 0x02000000
-#define MDP5_IRQ_INTF1_UNDER_RUN 0x04000000
-#define MDP5_IRQ_INTF1_VSYNC 0x08000000
-#define MDP5_IRQ_INTF2_UNDER_RUN 0x10000000
-#define MDP5_IRQ_INTF2_VSYNC 0x20000000
-#define MDP5_IRQ_INTF3_UNDER_RUN 0x40000000
-#define MDP5_IRQ_INTF3_VSYNC 0x80000000
-#define REG_MDSS_HW_VERSION 0x00000000
-#define MDSS_HW_VERSION_STEP__MASK 0x0000ffff
-#define MDSS_HW_VERSION_STEP__SHIFT 0
-static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val)
-{
- return ((val) << MDSS_HW_VERSION_STEP__SHIFT) & MDSS_HW_VERSION_STEP__MASK;
-}
-#define MDSS_HW_VERSION_MINOR__MASK 0x0fff0000
-#define MDSS_HW_VERSION_MINOR__SHIFT 16
-static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val)
-{
- return ((val) << MDSS_HW_VERSION_MINOR__SHIFT) & MDSS_HW_VERSION_MINOR__MASK;
-}
-#define MDSS_HW_VERSION_MAJOR__MASK 0xf0000000
-#define MDSS_HW_VERSION_MAJOR__SHIFT 28
-static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)
-{
- return ((val) << MDSS_HW_VERSION_MAJOR__SHIFT) & MDSS_HW_VERSION_MAJOR__MASK;
-}
-
-#define REG_MDSS_HW_INTR_STATUS 0x00000010
-#define MDSS_HW_INTR_STATUS_INTR_MDP 0x00000001
-#define MDSS_HW_INTR_STATUS_INTR_DSI0 0x00000010
-#define MDSS_HW_INTR_STATUS_INTR_DSI1 0x00000020
-#define MDSS_HW_INTR_STATUS_INTR_HDMI 0x00000100
-#define MDSS_HW_INTR_STATUS_INTR_EDP 0x00001000
-
-#define REG_MDP5_HW_VERSION 0x00000000
-#define MDP5_HW_VERSION_STEP__MASK 0x0000ffff
-#define MDP5_HW_VERSION_STEP__SHIFT 0
-static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val)
-{
- return ((val) << MDP5_HW_VERSION_STEP__SHIFT) & MDP5_HW_VERSION_STEP__MASK;
-}
-#define MDP5_HW_VERSION_MINOR__MASK 0x0fff0000
-#define MDP5_HW_VERSION_MINOR__SHIFT 16
-static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val)
-{
- return ((val) << MDP5_HW_VERSION_MINOR__SHIFT) & MDP5_HW_VERSION_MINOR__MASK;
-}
-#define MDP5_HW_VERSION_MAJOR__MASK 0xf0000000
-#define MDP5_HW_VERSION_MAJOR__SHIFT 28
-static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val)
-{
- return ((val) << MDP5_HW_VERSION_MAJOR__SHIFT) & MDP5_HW_VERSION_MAJOR__MASK;
-}
-
-#define REG_MDP5_DISP_INTF_SEL 0x00000004
-#define MDP5_DISP_INTF_SEL_INTF0__MASK 0x000000ff
-#define MDP5_DISP_INTF_SEL_INTF0__SHIFT 0
-static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)
-{
- return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK;
-}
-#define MDP5_DISP_INTF_SEL_INTF1__MASK 0x0000ff00
-#define MDP5_DISP_INTF_SEL_INTF1__SHIFT 8
-static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)
-{
- return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK;
-}
-#define MDP5_DISP_INTF_SEL_INTF2__MASK 0x00ff0000
-#define MDP5_DISP_INTF_SEL_INTF2__SHIFT 16
-static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)
-{
- return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK;
-}
-#define MDP5_DISP_INTF_SEL_INTF3__MASK 0xff000000
-#define MDP5_DISP_INTF_SEL_INTF3__SHIFT 24
-static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)
-{
- return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK;
-}
-
-#define REG_MDP5_INTR_EN 0x00000010
-
-#define REG_MDP5_INTR_STATUS 0x00000014
-
-#define REG_MDP5_INTR_CLEAR 0x00000018
-
-#define REG_MDP5_HIST_INTR_EN 0x0000001c
-
-#define REG_MDP5_HIST_INTR_STATUS 0x00000020
-
-#define REG_MDP5_HIST_INTR_CLEAR 0x00000024
-
-#define REG_MDP5_SPARE_0 0x00000028
-#define MDP5_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN 0x00000001
-
-static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; }
-
-static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; }
-#define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff
-#define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0
-static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)
-{
- return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK;
-}
-#define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00
-#define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8
-static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)
-{
- return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK;
-}
-#define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000
-#define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16
-static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)
-{
- return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK;
-}
-
-static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; }
-
-static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; }
-#define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff
-#define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0
-static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)
-{
- return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK;
-}
-#define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00
-#define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8
-static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)
-{
- return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK;
-}
-#define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000
-#define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16
-static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)
-{
- return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK;
-}
-
-static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
-{
- switch (idx) {
- case IGC_VIG: return 0x00000200;
- case IGC_RGB: return 0x00000210;
- case IGC_DMA: return 0x00000220;
- case IGC_DSPP: return 0x00000300;
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }
-
-static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
-#define MDP5_IGC_LUT_REG_VAL__MASK 0x00000fff
-#define MDP5_IGC_LUT_REG_VAL__SHIFT 0
-static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)
-{
- return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK;
-}
-#define MDP5_IGC_LUT_REG_INDEX_UPDATE 0x02000000
-#define MDP5_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000
-#define MDP5_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000
-#define MDP5_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000
-
-#define REG_MDP5_SPLIT_DPL_EN 0x000002f4
-
-#define REG_MDP5_SPLIT_DPL_UPPER 0x000002f8
-#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL 0x00000002
-#define MDP5_SPLIT_DPL_UPPER_SMART_PANEL_FREE_RUN 0x00000004
-#define MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX 0x00000010
-#define MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX 0x00000100
-
-#define REG_MDP5_SPLIT_DPL_LOWER 0x000003f0
-#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL 0x00000002
-#define MDP5_SPLIT_DPL_LOWER_SMART_PANEL_FREE_RUN 0x00000004
-#define MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC 0x00000010
-#define MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC 0x00000100
-
-static inline uint32_t __offset_CTL(uint32_t idx)
-{
- switch (idx) {
- case 0: return (mdp5_cfg->ctl.base[0]);
- case 1: return (mdp5_cfg->ctl.base[1]);
- case 2: return (mdp5_cfg->ctl.base[2]);
- case 3: return (mdp5_cfg->ctl.base[3]);
- case 4: return (mdp5_cfg->ctl.base[4]);
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }
-
-static inline uint32_t __offset_LAYER(uint32_t idx)
-{
- switch (idx) {
- case 0: return 0x00000000;
- case 1: return 0x00000004;
- case 2: return 0x00000008;
- case 3: return 0x0000000c;
- case 4: return 0x00000010;
- case 5: return 0x00000024;
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
-
-static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); }
-#define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007
-#define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0
-static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(uint32_t val)
-{
- return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK;
-}
-#define MDP5_CTL_LAYER_REG_VIG1__MASK 0x00000038
-#define MDP5_CTL_LAYER_REG_VIG1__SHIFT 3
-static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(uint32_t val)
-{
- return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK;
-}
-#define MDP5_CTL_LAYER_REG_VIG2__MASK 0x000001c0
-#define MDP5_CTL_LAYER_REG_VIG2__SHIFT 6
-static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(uint32_t val)
-{
- return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK;
-}
-#define MDP5_CTL_LAYER_REG_RGB0__MASK 0x00000e00
-#define MDP5_CTL_LAYER_REG_RGB0__SHIFT 9
-static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(uint32_t val)
-{
- return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK;
-}
-#define MDP5_CTL_LAYER_REG_RGB1__MASK 0x00007000
-#define MDP5_CTL_LAYER_REG_RGB1__SHIFT 12
-static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(uint32_t val)
-{
- return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK;
-}
-#define MDP5_CTL_LAYER_REG_RGB2__MASK 0x00038000
-#define MDP5_CTL_LAYER_REG_RGB2__SHIFT 15
-static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(uint32_t val)
-{
- return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK;
-}
-#define MDP5_CTL_LAYER_REG_DMA0__MASK 0x001c0000
-#define MDP5_CTL_LAYER_REG_DMA0__SHIFT 18
-static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(uint32_t val)
-{
- return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK;
-}
-#define MDP5_CTL_LAYER_REG_DMA1__MASK 0x00e00000
-#define MDP5_CTL_LAYER_REG_DMA1__SHIFT 21
-static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(uint32_t val)
-{
- return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK;
-}
-#define MDP5_CTL_LAYER_REG_BORDER_COLOR 0x01000000
-#define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000
-#define MDP5_CTL_LAYER_REG_VIG3__MASK 0x1c000000
-#define MDP5_CTL_LAYER_REG_VIG3__SHIFT 26
-static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(uint32_t val)
-{
- return ((val) << MDP5_CTL_LAYER_REG_VIG3__SHIFT) & MDP5_CTL_LAYER_REG_VIG3__MASK;
-}
-#define MDP5_CTL_LAYER_REG_RGB3__MASK 0xe0000000
-#define MDP5_CTL_LAYER_REG_RGB3__SHIFT 29
-static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(uint32_t val)
-{
- return ((val) << MDP5_CTL_LAYER_REG_RGB3__SHIFT) & MDP5_CTL_LAYER_REG_RGB3__MASK;
-}
-
-static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }
-#define MDP5_CTL_OP_MODE__MASK 0x0000000f
-#define MDP5_CTL_OP_MODE__SHIFT 0
-static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
-{
- return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK;
-}
-#define MDP5_CTL_OP_INTF_NUM__MASK 0x00000070
-#define MDP5_CTL_OP_INTF_NUM__SHIFT 4
-static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)
-{
- return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK;
-}
-#define MDP5_CTL_OP_CMD_MODE 0x00020000
-#define MDP5_CTL_OP_PACK_3D_ENABLE 0x00080000
-#define MDP5_CTL_OP_PACK_3D__MASK 0x00300000
-#define MDP5_CTL_OP_PACK_3D__SHIFT 20
-static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
-{
- return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK;
-}
-
-static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }
-#define MDP5_CTL_FLUSH_VIG0 0x00000001
-#define MDP5_CTL_FLUSH_VIG1 0x00000002
-#define MDP5_CTL_FLUSH_VIG2 0x00000004
-#define MDP5_CTL_FLUSH_RGB0 0x00000008
-#define MDP5_CTL_FLUSH_RGB1 0x00000010
-#define MDP5_CTL_FLUSH_RGB2 0x00000020
-#define MDP5_CTL_FLUSH_LM0 0x00000040
-#define MDP5_CTL_FLUSH_LM1 0x00000080
-#define MDP5_CTL_FLUSH_LM2 0x00000100
-#define MDP5_CTL_FLUSH_LM3 0x00000200
-#define MDP5_CTL_FLUSH_LM4 0x00000400
-#define MDP5_CTL_FLUSH_DMA0 0x00000800
-#define MDP5_CTL_FLUSH_DMA1 0x00001000
-#define MDP5_CTL_FLUSH_DSPP0 0x00002000
-#define MDP5_CTL_FLUSH_DSPP1 0x00004000
-#define MDP5_CTL_FLUSH_DSPP2 0x00008000
-#define MDP5_CTL_FLUSH_WB 0x00010000
-#define MDP5_CTL_FLUSH_CTL 0x00020000
-#define MDP5_CTL_FLUSH_VIG3 0x00040000
-#define MDP5_CTL_FLUSH_RGB3 0x00080000
-#define MDP5_CTL_FLUSH_LM5 0x00100000
-#define MDP5_CTL_FLUSH_DSPP3 0x00200000
-#define MDP5_CTL_FLUSH_CURSOR_0 0x00400000
-#define MDP5_CTL_FLUSH_CURSOR_1 0x00800000
-#define MDP5_CTL_FLUSH_CHROMADOWN_0 0x04000000
-#define MDP5_CTL_FLUSH_TIMING_3 0x10000000
-#define MDP5_CTL_FLUSH_TIMING_2 0x20000000
-#define MDP5_CTL_FLUSH_TIMING_1 0x40000000
-#define MDP5_CTL_FLUSH_TIMING_0 0x80000000
-
-static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }
-
-static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }
-
-static inline uint32_t __offset_LAYER_EXT(uint32_t idx)
-{
- switch (idx) {
- case 0: return 0x00000040;
- case 1: return 0x00000044;
- case 2: return 0x00000048;
- case 3: return 0x0000004c;
- case 4: return 0x00000050;
- case 5: return 0x00000054;
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
-
-static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); }
-#define MDP5_CTL_LAYER_EXT_REG_VIG0_BIT3 0x00000001
-#define MDP5_CTL_LAYER_EXT_REG_VIG1_BIT3 0x00000004
-#define MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3 0x00000010
-#define MDP5_CTL_LAYER_EXT_REG_VIG3_BIT3 0x00000040
-#define MDP5_CTL_LAYER_EXT_REG_RGB0_BIT3 0x00000100
-#define MDP5_CTL_LAYER_EXT_REG_RGB1_BIT3 0x00000400
-#define MDP5_CTL_LAYER_EXT_REG_RGB2_BIT3 0x00001000
-#define MDP5_CTL_LAYER_EXT_REG_RGB3_BIT3 0x00004000
-#define MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3 0x00010000
-#define MDP5_CTL_LAYER_EXT_REG_DMA1_BIT3 0x00040000
-#define MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK 0x00f00000
-#define MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT 20
-static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR0(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR0__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR0__MASK;
-}
-#define MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK 0x3c000000
-#define MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT 26
-static inline uint32_t MDP5_CTL_LAYER_EXT_REG_CURSOR1(enum mdp_mixer_stage_id val)
-{
- return ((val) << MDP5_CTL_LAYER_EXT_REG_CURSOR1__SHIFT) & MDP5_CTL_LAYER_EXT_REG_CURSOR1__MASK;
-}
-
-static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)
-{
- switch (idx) {
- case SSPP_NONE: return (INVALID_IDX(idx));
- case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);
- case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]);
- case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]);
- case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]);
- case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]);
- case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]);
- case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]);
- case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]);
- case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]);
- case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]);
- case SSPP_CURSOR0: return (mdp5_cfg->pipe_cursor.base[0]);
- case SSPP_CURSOR1: return (mdp5_cfg->pipe_cursor.base[1]);
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); }
-#define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00080000
-#define MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 19
-static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)
-{
- return ((val) << MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
-}
-#define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00040000
-#define MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 18
-static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)
-{
- return ((val) << MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
-}
-#define MDP5_PIPE_OP_MODE_CSC_1_EN 0x00020000
-
-static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); }
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT 0
-static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)
-{
- return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11__MASK;
-}
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT 16
-static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)
-{
- return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); }
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT 0
-static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)
-{
- return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13__MASK;
-}
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT 16
-static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)
-{
- return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); }
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT 0
-static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)
-{
- return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22__MASK;
-}
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT 16
-static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)
-{
- return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); }
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT 0
-static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)
-{
- return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31__MASK;
-}
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT 16
-static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)
-{
- return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); }
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
-#define MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT 0
-static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)
-{
- return ((val) << MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; }
-#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK 0x000000ff
-#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT 0
-static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)
-{
- return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH__MASK;
-}
-#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK 0x0000ff00
-#define MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT 8
-static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)
-{
- return ((val) << MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; }
-#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK 0x000000ff
-#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT 0
-static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)
-{
- return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH__MASK;
-}
-#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK 0x0000ff00
-#define MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT 8
-static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)
-{
- return ((val) << MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__SHIFT) & MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; }
-#define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK 0x000001ff
-#define MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT 0
-static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)
-{
- return ((val) << MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; }
-#define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK 0x000001ff
-#define MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT 0
-static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)
-{
- return ((val) << MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__SHIFT) & MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }
-#define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
-#define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
-static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK;
-}
-#define MDP5_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
-#define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT 0
-static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); }
-#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK 0xffff0000
-#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT 16
-static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK;
-}
-#define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK 0x0000ffff
-#define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT 0
-static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); }
-#define MDP5_PIPE_SRC_XY_Y__MASK 0xffff0000
-#define MDP5_PIPE_SRC_XY_Y__SHIFT 16
-static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK;
-}
-#define MDP5_PIPE_SRC_XY_X__MASK 0x0000ffff
-#define MDP5_PIPE_SRC_XY_X__SHIFT 0
-static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); }
-#define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK 0xffff0000
-#define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT 16
-static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
-{
- return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK;
-}
-#define MDP5_PIPE_OUT_SIZE_WIDTH__MASK 0x0000ffff
-#define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT 0
-static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
-{
- return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); }
-#define MDP5_PIPE_OUT_XY_Y__MASK 0xffff0000
-#define MDP5_PIPE_OUT_XY_Y__SHIFT 16
-static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
-{
- return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK;
-}
-#define MDP5_PIPE_OUT_XY_X__MASK 0x0000ffff
-#define MDP5_PIPE_OUT_XY_X__SHIFT 0
-static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
-{
- return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); }
-#define MDP5_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
-#define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT 0
-static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK;
-}
-#define MDP5_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
-#define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT 16
-static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); }
-#define MDP5_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
-#define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT 0
-static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK;
-}
-#define MDP5_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
-#define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT 16
-static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); }
-#define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
-#define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
-static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
-{
- return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK;
-}
-#define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
-#define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
-static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
-{
- return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK;
-}
-#define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
-#define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
-static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
-{
- return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK;
-}
-#define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
-#define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
-static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
-{
- return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK;
-}
-#define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
-#define MDP5_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
-#define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT 9
-static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK;
-}
-#define MDP5_PIPE_SRC_FORMAT_ROT90 0x00000800
-#define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00003000
-#define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 12
-static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
-}
-#define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
-#define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
-#define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK 0x00180000
-#define MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT 19
-static inline uint32_t MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(enum mdp_fetch_type val)
-{
- return ((val) << MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__SHIFT) & MDP5_PIPE_SRC_FORMAT_FETCH_TYPE__MASK;
-}
-#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x01800000
-#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 23
-static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)
-{
- return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); }
-#define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
-#define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
-static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK;
-}
-#define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
-#define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
-static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK;
-}
-#define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
-#define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
-static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK;
-}
-#define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
-#define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
-static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); }
-#define MDP5_PIPE_SRC_OP_MODE_BWC_EN 0x00000001
-#define MDP5_PIPE_SRC_OP_MODE_BWC__MASK 0x00000006
-#define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT 1
-static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
-{
- return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK;
-}
-#define MDP5_PIPE_SRC_OP_MODE_FLIP_LR 0x00002000
-#define MDP5_PIPE_SRC_OP_MODE_FLIP_UD 0x00004000
-#define MDP5_PIPE_SRC_OP_MODE_IGC_EN 0x00010000
-#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0 0x00020000
-#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000
-#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000
-#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000
-#define MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE 0x80000000
-
-static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); }
-#define MDP5_PIPE_DECIMATION_VERT__MASK 0x000000ff
-#define MDP5_PIPE_DECIMATION_VERT__SHIFT 0
-static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
-{
- return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK;
-}
-#define MDP5_PIPE_DECIMATION_HORZ__MASK 0x0000ff00
-#define MDP5_PIPE_DECIMATION_HORZ__SHIFT 8
-static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
-{
- return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
-}
-
-static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx)
-{
- switch (idx) {
- case COMP_0: return 0x00000100;
- case COMP_1_2: return 0x00000110;
- case COMP_3: return 0x00000120;
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
-
-static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
-#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK 0x000000ff
-#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT 0
-static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK;
-}
-#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK 0x0000ff00
-#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT 8
-static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val)
-{
- return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK;
-}
-#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK 0x00ff0000
-#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT 16
-static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK;
-}
-#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK 0xff000000
-#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT 24
-static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val)
-{
- return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
-#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK 0x000000ff
-#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT 0
-static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK;
-}
-#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK 0x0000ff00
-#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT 8
-static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val)
-{
- return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK;
-}
-#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK 0x00ff0000
-#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT 16
-static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK;
-}
-#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK 0xff000000
-#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT 24
-static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val)
-{
- return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); }
-#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK 0x0000ffff
-#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT 0
-static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK;
-}
-#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK 0xffff0000
-#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT 16
-static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val)
-{
- return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); }
-#define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001
-#define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002
-#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK 0x00000300
-#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT 8
-static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(enum mdp5_scale_filter val)
-{
- return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0__MASK;
-}
-#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK 0x00000c00
-#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT 10
-static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(enum mdp5_scale_filter val)
-{
- return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0__MASK;
-}
-#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK 0x00003000
-#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT 12
-static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(enum mdp5_scale_filter val)
-{
- return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2__MASK;
-}
-#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK 0x0000c000
-#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT 14
-static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(enum mdp5_scale_filter val)
-{
- return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2__MASK;
-}
-#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK 0x00030000
-#define MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT 16
-static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(enum mdp5_scale_filter val)
-{
- return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3__MASK;
-}
-#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK 0x000c0000
-#define MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT 18
-static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(enum mdp5_scale_filter val)
-{
- return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3__MASK;
-}
-
-static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); }
-
-static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); }
-
-static inline uint32_t __offset_LM(uint32_t idx)
-{
- switch (idx) {
- case 0: return (mdp5_cfg->lm.base[0]);
- case 1: return (mdp5_cfg->lm.base[1]);
- case 2: return (mdp5_cfg->lm.base[2]);
- case 3: return (mdp5_cfg->lm.base[3]);
- case 4: return (mdp5_cfg->lm.base[4]);
- case 5: return (mdp5_cfg->lm.base[5]);
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
-
-static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }
-#define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA 0x00000002
-#define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA 0x00000004
-#define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA 0x00000008
-#define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA 0x00000010
-#define MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA 0x00000020
-#define MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA 0x00000040
-#define MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA 0x00000080
-#define MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT 0x80000000
-
-static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }
-#define MDP5_LM_OUT_SIZE_HEIGHT__MASK 0xffff0000
-#define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT 16
-static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
-{
- return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK;
-}
-#define MDP5_LM_OUT_SIZE_WIDTH__MASK 0x0000ffff
-#define MDP5_LM_OUT_SIZE_WIDTH__SHIFT 0
-static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
-{
- return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK;
-}
-
-static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); }
-
-static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); }
-
-static inline uint32_t __offset_BLEND(uint32_t idx)
-{
- switch (idx) {
- case 0: return 0x00000020;
- case 1: return 0x00000050;
- case 2: return 0x00000080;
- case 3: return 0x000000b0;
- case 4: return 0x00000230;
- case 5: return 0x00000260;
- case 6: return 0x00000290;
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
-
-static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); }
-#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003
-#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0
-static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
-{
- return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK;
-}
-#define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA 0x00000004
-#define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA 0x00000008
-#define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA 0x00000010
-#define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN 0x00000020
-#define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK 0x00000300
-#define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT 8
-static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
-{
- return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK;
-}
-#define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA 0x00000400
-#define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA 0x00000800
-#define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000
-#define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000
-
-static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); }
-
-static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); }
-
-static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); }
-
-static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); }
-
-static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); }
-
-static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); }
-
-static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); }
-
-static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); }
-
-static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); }
-
-static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); }
-
-static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); }
-#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK 0x0000ffff
-#define MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT 0
-static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)
-{
- return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_W__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_W__MASK;
-}
-#define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK 0xffff0000
-#define MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT 16
-static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)
-{
- return ((val) << MDP5_LM_CURSOR_IMG_SIZE_SRC_H__SHIFT) & MDP5_LM_CURSOR_IMG_SIZE_SRC_H__MASK;
-}
-
-static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }
-#define MDP5_LM_CURSOR_SIZE_ROI_W__MASK 0x0000ffff
-#define MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT 0
-static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)
-{
- return ((val) << MDP5_LM_CURSOR_SIZE_ROI_W__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_W__MASK;
-}
-#define MDP5_LM_CURSOR_SIZE_ROI_H__MASK 0xffff0000
-#define MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT 16
-static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)
-{
- return ((val) << MDP5_LM_CURSOR_SIZE_ROI_H__SHIFT) & MDP5_LM_CURSOR_SIZE_ROI_H__MASK;
-}
-
-static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }
-#define MDP5_LM_CURSOR_XY_SRC_X__MASK 0x0000ffff
-#define MDP5_LM_CURSOR_XY_SRC_X__SHIFT 0
-static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)
-{
- return ((val) << MDP5_LM_CURSOR_XY_SRC_X__SHIFT) & MDP5_LM_CURSOR_XY_SRC_X__MASK;
-}
-#define MDP5_LM_CURSOR_XY_SRC_Y__MASK 0xffff0000
-#define MDP5_LM_CURSOR_XY_SRC_Y__SHIFT 16
-static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)
-{
- return ((val) << MDP5_LM_CURSOR_XY_SRC_Y__SHIFT) & MDP5_LM_CURSOR_XY_SRC_Y__MASK;
-}
-
-static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); }
-#define MDP5_LM_CURSOR_STRIDE_STRIDE__MASK 0x0000ffff
-#define MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT 0
-static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)
-{
- return ((val) << MDP5_LM_CURSOR_STRIDE_STRIDE__SHIFT) & MDP5_LM_CURSOR_STRIDE_STRIDE__MASK;
-}
-
-static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); }
-#define MDP5_LM_CURSOR_FORMAT_FORMAT__MASK 0x00000007
-#define MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT 0
-static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)
-{
- return ((val) << MDP5_LM_CURSOR_FORMAT_FORMAT__SHIFT) & MDP5_LM_CURSOR_FORMAT_FORMAT__MASK;
-}
-
-static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); }
-
-static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); }
-#define MDP5_LM_CURSOR_START_XY_X_START__MASK 0x0000ffff
-#define MDP5_LM_CURSOR_START_XY_X_START__SHIFT 0
-static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)
-{
- return ((val) << MDP5_LM_CURSOR_START_XY_X_START__SHIFT) & MDP5_LM_CURSOR_START_XY_X_START__MASK;
-}
-#define MDP5_LM_CURSOR_START_XY_Y_START__MASK 0xffff0000
-#define MDP5_LM_CURSOR_START_XY_Y_START__SHIFT 16
-static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)
-{
- return ((val) << MDP5_LM_CURSOR_START_XY_Y_START__SHIFT) & MDP5_LM_CURSOR_START_XY_Y_START__MASK;
-}
-
-static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); }
-#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN 0x00000001
-#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK 0x00000006
-#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT 1
-static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)
-{
- return ((val) << MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__SHIFT) & MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL__MASK;
-}
-#define MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_TRANSP_EN 0x00000008
-
-static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); }
-
-static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); }
-
-static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); }
-
-static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); }
-
-static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); }
-
-static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }
-
-static inline uint32_t __offset_DSPP(uint32_t idx)
-{
- switch (idx) {
- case 0: return (mdp5_cfg->dspp.base[0]);
- case 1: return (mdp5_cfg->dspp.base[1]);
- case 2: return (mdp5_cfg->dspp.base[2]);
- case 3: return (mdp5_cfg->dspp.base[3]);
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
-
-static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }
-#define MDP5_DSPP_OP_MODE_IGC_LUT_EN 0x00000001
-#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK 0x0000000e
-#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT 1
-static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
-{
- return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK;
-}
-#define MDP5_DSPP_OP_MODE_PCC_EN 0x00000010
-#define MDP5_DSPP_OP_MODE_DITHER_EN 0x00000100
-#define MDP5_DSPP_OP_MODE_HIST_EN 0x00010000
-#define MDP5_DSPP_OP_MODE_AUTO_CLEAR 0x00020000
-#define MDP5_DSPP_OP_MODE_HIST_LUT_EN 0x00080000
-#define MDP5_DSPP_OP_MODE_PA_EN 0x00100000
-#define MDP5_DSPP_OP_MODE_GAMUT_EN 0x00800000
-#define MDP5_DSPP_OP_MODE_GAMUT_ORDER 0x01000000
-
-static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); }
-
-static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); }
-
-static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); }
-
-static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); }
-
-static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); }
-
-static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }
-
-static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); }
-
-static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }
-
-static inline uint32_t __offset_PP(uint32_t idx)
-{
- switch (idx) {
- case 0: return (mdp5_cfg->pp.base[0]);
- case 1: return (mdp5_cfg->pp.base[1]);
- case 2: return (mdp5_cfg->pp.base[2]);
- case 3: return (mdp5_cfg->pp.base[3]);
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
-
-static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }
-
-static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0); }
-#define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK 0x0007ffff
-#define MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT 0
-static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val)
-{
- return ((val) << MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__SHIFT) & MDP5_PP_SYNC_CONFIG_VSYNC_COUNT__MASK;
-}
-#define MDP5_PP_SYNC_CONFIG_VSYNC_COUNTER_EN 0x00080000
-#define MDP5_PP_SYNC_CONFIG_VSYNC_IN_EN 0x00100000
-
-static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0); }
-
-static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0); }
-#define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK 0x0000ffff
-#define MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT 0
-static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val)
-{
- return ((val) << MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_LINE_COUNT__MASK;
-}
-#define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK 0xffff0000
-#define MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT 16
-static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val)
-{
- return ((val) << MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__SHIFT) & MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT__MASK;
-}
-
-static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0); }
-
-static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0); }
-#define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK 0x0000ffff
-#define MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT 0
-static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val)
-{
- return ((val) << MDP5_PP_INT_COUNT_VAL_LINE_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_LINE_COUNT__MASK;
-}
-#define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK 0xffff0000
-#define MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT 16
-static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val)
-{
- return ((val) << MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__SHIFT) & MDP5_PP_INT_COUNT_VAL_FRAME_COUNT__MASK;
-}
-
-static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); }
-#define MDP5_PP_SYNC_THRESH_START__MASK 0x0000ffff
-#define MDP5_PP_SYNC_THRESH_START__SHIFT 0
-static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val)
-{
- return ((val) << MDP5_PP_SYNC_THRESH_START__SHIFT) & MDP5_PP_SYNC_THRESH_START__MASK;
-}
-#define MDP5_PP_SYNC_THRESH_CONTINUE__MASK 0xffff0000
-#define MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT 16
-static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val)
-{
- return ((val) << MDP5_PP_SYNC_THRESH_CONTINUE__SHIFT) & MDP5_PP_SYNC_THRESH_CONTINUE__MASK;
-}
-
-static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); }
-
-static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); }
-
-static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); }
-
-static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0); }
-
-static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0); }
-
-static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0); }
-
-static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); }
-
-static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0); }
-
-static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); }
-
-static inline uint32_t __offset_WB(uint32_t idx)
-{
- switch (idx) {
-#if 0 /* TEMPORARY until patch that adds wb.base[] is merged */
- case 0: return (mdp5_cfg->wb.base[0]);
- case 1: return (mdp5_cfg->wb.base[1]);
- case 2: return (mdp5_cfg->wb.base[2]);
- case 3: return (mdp5_cfg->wb.base[3]);
- case 4: return (mdp5_cfg->wb.base[4]);
-#endif
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); }
-#define MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK 0x00000003
-#define MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT 0
-static inline uint32_t MDP5_WB_DST_FORMAT_DSTC0_OUT(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_FORMAT_DSTC0_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC0_OUT__MASK;
-}
-#define MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK 0x0000000c
-#define MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT 2
-static inline uint32_t MDP5_WB_DST_FORMAT_DSTC1_OUT(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_FORMAT_DSTC1_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC1_OUT__MASK;
-}
-#define MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK 0x00000030
-#define MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT 4
-static inline uint32_t MDP5_WB_DST_FORMAT_DSTC2_OUT(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_FORMAT_DSTC2_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC2_OUT__MASK;
-}
-#define MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK 0x000000c0
-#define MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT 6
-static inline uint32_t MDP5_WB_DST_FORMAT_DSTC3_OUT(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_FORMAT_DSTC3_OUT__SHIFT) & MDP5_WB_DST_FORMAT_DSTC3_OUT__MASK;
-}
-#define MDP5_WB_DST_FORMAT_DSTC3_EN 0x00000100
-#define MDP5_WB_DST_FORMAT_DST_BPP__MASK 0x00000600
-#define MDP5_WB_DST_FORMAT_DST_BPP__SHIFT 9
-static inline uint32_t MDP5_WB_DST_FORMAT_DST_BPP(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_FORMAT_DST_BPP__SHIFT) & MDP5_WB_DST_FORMAT_DST_BPP__MASK;
-}
-#define MDP5_WB_DST_FORMAT_PACK_COUNT__MASK 0x00003000
-#define MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT 12
-static inline uint32_t MDP5_WB_DST_FORMAT_PACK_COUNT(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_FORMAT_PACK_COUNT__SHIFT) & MDP5_WB_DST_FORMAT_PACK_COUNT__MASK;
-}
-#define MDP5_WB_DST_FORMAT_DST_ALPHA_X 0x00004000
-#define MDP5_WB_DST_FORMAT_PACK_TIGHT 0x00020000
-#define MDP5_WB_DST_FORMAT_PACK_ALIGN_MSB 0x00040000
-#define MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK 0x00180000
-#define MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT 19
-static inline uint32_t MDP5_WB_DST_FORMAT_WRITE_PLANES(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_FORMAT_WRITE_PLANES__SHIFT) & MDP5_WB_DST_FORMAT_WRITE_PLANES__MASK;
-}
-#define MDP5_WB_DST_FORMAT_DST_DITHER_EN 0x00400000
-#define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK 0x03800000
-#define MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT 23
-static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SAMP__MASK;
-}
-#define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK 0x3c000000
-#define MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT 26
-static inline uint32_t MDP5_WB_DST_FORMAT_DST_CHROMA_SITE(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__SHIFT) & MDP5_WB_DST_FORMAT_DST_CHROMA_SITE__MASK;
-}
-#define MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK 0xc0000000
-#define MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT 30
-static inline uint32_t MDP5_WB_DST_FORMAT_FRAME_FORMAT(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_FORMAT_FRAME_FORMAT__SHIFT) & MDP5_WB_DST_FORMAT_FRAME_FORMAT__MASK;
-}
-
-static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); }
-#define MDP5_WB_DST_OP_MODE_BWC_ENC_EN 0x00000001
-#define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK 0x00000006
-#define MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT 1
-static inline uint32_t MDP5_WB_DST_OP_MODE_BWC_ENC_OP(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_OP_MODE_BWC_ENC_OP__SHIFT) & MDP5_WB_DST_OP_MODE_BWC_ENC_OP__MASK;
-}
-#define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK 0x00000010
-#define MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT 4
-static inline uint32_t MDP5_WB_DST_OP_MODE_BLOCK_SIZE(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_OP_MODE_BLOCK_SIZE__SHIFT) & MDP5_WB_DST_OP_MODE_BLOCK_SIZE__MASK;
-}
-#define MDP5_WB_DST_OP_MODE_ROT_MODE__MASK 0x00000020
-#define MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT 5
-static inline uint32_t MDP5_WB_DST_OP_MODE_ROT_MODE(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_OP_MODE_ROT_MODE__SHIFT) & MDP5_WB_DST_OP_MODE_ROT_MODE__MASK;
-}
-#define MDP5_WB_DST_OP_MODE_ROT_EN 0x00000040
-#define MDP5_WB_DST_OP_MODE_CSC_EN 0x00000100
-#define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK 0x00000200
-#define MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT 9
-static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_SRC_DATA_FORMAT__MASK;
-}
-#define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK 0x00000400
-#define MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT 10
-static inline uint32_t MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CSC_DST_DATA_FORMAT__MASK;
-}
-#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_EN 0x00000800
-#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK 0x00001000
-#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT 12
-static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_FORMAT__MASK;
-}
-#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK 0x00002000
-#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT 13
-static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_H_MTHD__MASK;
-}
-#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK 0x00004000
-#define MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT 14
-static inline uint32_t MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__SHIFT) & MDP5_WB_DST_OP_MODE_CHROMA_DWN_SAMPLE_V_MTHD__MASK;
-}
-
-static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); }
-#define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK 0x00000003
-#define MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT 0
-static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT0(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT0__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT0__MASK;
-}
-#define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK 0x00000300
-#define MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT 8
-static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT1(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT1__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT1__MASK;
-}
-#define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK 0x00030000
-#define MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT 16
-static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT2(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT2__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT2__MASK;
-}
-#define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK 0x03000000
-#define MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT 24
-static inline uint32_t MDP5_WB_DST_PACK_PATTERN_ELEMENT3(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_PACK_PATTERN_ELEMENT3__SHIFT) & MDP5_WB_DST_PACK_PATTERN_ELEMENT3__MASK;
-}
-
-static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); }
-#define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK 0x0000ffff
-#define MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT 0
-static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST0_YSTRIDE__MASK;
-}
-#define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK 0xffff0000
-#define MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT 16
-static inline uint32_t MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE0_DST1_YSTRIDE__MASK;
-}
-
-static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); }
-#define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK 0x0000ffff
-#define MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT 0
-static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST2_YSTRIDE__MASK;
-}
-#define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK 0xffff0000
-#define MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT 16
-static inline uint32_t MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE(uint32_t val)
-{
- return ((val) << MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__SHIFT) & MDP5_WB_DST_YSTRIDE1_DST3_YSTRIDE__MASK;
-}
-
-static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); }
-#define MDP5_WB_OUT_SIZE_DST_W__MASK 0x0000ffff
-#define MDP5_WB_OUT_SIZE_DST_W__SHIFT 0
-static inline uint32_t MDP5_WB_OUT_SIZE_DST_W(uint32_t val)
-{
- return ((val) << MDP5_WB_OUT_SIZE_DST_W__SHIFT) & MDP5_WB_OUT_SIZE_DST_W__MASK;
-}
-#define MDP5_WB_OUT_SIZE_DST_H__MASK 0xffff0000
-#define MDP5_WB_OUT_SIZE_DST_H__SHIFT 16
-static inline uint32_t MDP5_WB_OUT_SIZE_DST_H(uint32_t val)
-{
- return ((val) << MDP5_WB_OUT_SIZE_DST_H__SHIFT) & MDP5_WB_OUT_SIZE_DST_H__MASK;
-}
-
-static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); }
-
-static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); }
-#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK 0x00001fff
-#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT 0
-static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11(uint32_t val)
-{
- return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_11__MASK;
-}
-#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK 0x1fff0000
-#define MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT 16
-static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12(uint32_t val)
-{
- return ((val) << MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_0_COEFF_12__MASK;
-}
-
-static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); }
-#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK 0x00001fff
-#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT 0
-static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13(uint32_t val)
-{
- return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_13__MASK;
-}
-#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK 0x1fff0000
-#define MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT 16
-static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21(uint32_t val)
-{
- return ((val) << MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_1_COEFF_21__MASK;
-}
-
-static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); }
-#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK 0x00001fff
-#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT 0
-static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22(uint32_t val)
-{
- return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_22__MASK;
-}
-#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK 0x1fff0000
-#define MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT 16
-static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23(uint32_t val)
-{
- return ((val) << MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_2_COEFF_23__MASK;
-}
-
-static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); }
-#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK 0x00001fff
-#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT 0
-static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31(uint32_t val)
-{
- return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_31__MASK;
-}
-#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK 0x1fff0000
-#define MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT 16
-static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32(uint32_t val)
-{
- return ((val) << MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_3_COEFF_32__MASK;
-}
-
-static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); }
-#define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK 0x00001fff
-#define MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT 0
-static inline uint32_t MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33(uint32_t val)
-{
- return ((val) << MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__SHIFT) & MDP5_WB_CSC_MATRIX_COEFF_4_COEFF_33__MASK;
-}
-
-static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; }
-#define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK 0x000000ff
-#define MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT 0
-static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH(uint32_t val)
-{
- return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_HIGH__MASK;
-}
-#define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK 0x0000ff00
-#define MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT 8
-static inline uint32_t MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW(uint32_t val)
-{
- return ((val) << MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_PRECLAMP_REG_LOW__MASK;
-}
-
-static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; }
-#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK 0x000000ff
-#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT 0
-static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH(uint32_t val)
-{
- return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_HIGH__MASK;
-}
-#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK 0x0000ff00
-#define MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT 8
-static inline uint32_t MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW(uint32_t val)
-{
- return ((val) << MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__SHIFT) & MDP5_WB_CSC_COMP_POSTCLAMP_REG_LOW__MASK;
-}
-
-static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; }
-#define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK 0x000001ff
-#define MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT 0
-static inline uint32_t MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE(uint32_t val)
-{
- return ((val) << MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_PREBIAS_REG_VALUE__MASK;
-}
-
-static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
-
-static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; }
-#define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK 0x000001ff
-#define MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT 0
-static inline uint32_t MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE(uint32_t val)
-{
- return ((val) << MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__SHIFT) & MDP5_WB_CSC_COMP_POSTBIAS_REG_VALUE__MASK;
-}
-
-static inline uint32_t __offset_INTF(uint32_t idx)
-{
- switch (idx) {
- case 0: return (mdp5_cfg->intf.base[0]);
- case 1: return (mdp5_cfg->intf.base[1]);
- case 2: return (mdp5_cfg->intf.base[2]);
- case 3: return (mdp5_cfg->intf.base[3]);
- case 4: return (mdp5_cfg->intf.base[4]);
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); }
-#define MDP5_INTF_HSYNC_CTL_PULSEW__MASK 0x0000ffff
-#define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT 0
-static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
-{
- return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK;
-}
-#define MDP5_INTF_HSYNC_CTL_PERIOD__MASK 0xffff0000
-#define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT 16
-static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
-{
- return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK;
-}
-
-static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); }
-#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK 0x7fffffff
-#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT 0
-static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
-{
- return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK;
-}
-#define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE 0x80000000
-
-static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); }
-#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK 0x7fffffff
-#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT 0
-static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
-{
- return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK;
-}
-
-static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); }
-#define MDP5_INTF_DISPLAY_HCTL_START__MASK 0x0000ffff
-#define MDP5_INTF_DISPLAY_HCTL_START__SHIFT 0
-static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
-{
- return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK;
-}
-#define MDP5_INTF_DISPLAY_HCTL_END__MASK 0xffff0000
-#define MDP5_INTF_DISPLAY_HCTL_END__SHIFT 16
-static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
-{
- return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK;
-}
-
-static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); }
-#define MDP5_INTF_ACTIVE_HCTL_START__MASK 0x00007fff
-#define MDP5_INTF_ACTIVE_HCTL_START__SHIFT 0
-static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
-{
- return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK;
-}
-#define MDP5_INTF_ACTIVE_HCTL_END__MASK 0x7fff0000
-#define MDP5_INTF_ACTIVE_HCTL_END__SHIFT 16
-static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
-{
- return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK;
-}
-#define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE 0x80000000
-
-static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); }
-#define MDP5_INTF_POLARITY_CTL_HSYNC_LOW 0x00000001
-#define MDP5_INTF_POLARITY_CTL_VSYNC_LOW 0x00000002
-#define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW 0x00000004
-
-static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); }
-
-static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); }
-
-static inline uint32_t __offset_AD(uint32_t idx)
-{
- switch (idx) {
- case 0: return (mdp5_cfg->ad.base[0]);
- case 1: return (mdp5_cfg->ad.base[1]);
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }
-
-static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }
-
-
-#endif /* MDP5_XML */
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h
index 26c5d8b4ab46..4b988e69fbfc 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h
@@ -69,6 +69,16 @@ struct mdp5_mdp_block {
uint32_t caps; /* MDP capabilities: MDP_CAP_xxx bits */
};
+struct mdp5_wb_instance {
+ int id;
+ int lm;
+};
+
+struct mdp5_wb_block {
+ MDP5_SUB_BLOCK_DEFINITION;
+ struct mdp5_wb_instance instances[MAX_BASES];
+};
+
#define MDP5_INTF_NUM_MAX 5
struct mdp5_intf_block {
@@ -98,6 +108,7 @@ struct mdp5_cfg_hw {
struct mdp5_sub_block pp;
struct mdp5_sub_block dsc;
struct mdp5_sub_block cdm;
+ struct mdp5_wb_block wb;
struct mdp5_intf_block intf;
struct mdp5_perf_block perf;
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
index 4a3db2ea1689..0f653e62b4a0 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c
@@ -216,7 +216,7 @@ static void blend_setup(struct drm_crtc *crtc)
struct mdp5_kms *mdp5_kms = get_kms(crtc);
struct drm_plane *plane;
struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
- const struct mdp_format *format;
+ const struct msm_format *format;
struct mdp5_hw_mixer *mixer = pipeline->mixer;
uint32_t lm = mixer->lm;
struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer;
@@ -274,7 +274,7 @@ static void blend_setup(struct drm_crtc *crtc)
ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT;
DBG("Border Color is enabled");
} else if (plane_cnt) {
- format = to_mdp_format(msm_framebuffer_format(pstates[STAGE_BASE]->base.fb));
+ format = msm_framebuffer_format(pstates[STAGE_BASE]->base.fb);
if (format->alpha_enable)
bg_alpha_enabled = true;
@@ -285,8 +285,7 @@ static void blend_setup(struct drm_crtc *crtc)
if (!pstates[i])
continue;
- format = to_mdp_format(
- msm_framebuffer_format(pstates[i]->base.fb));
+ format = msm_framebuffer_format(pstates[i]->base.fb);
plane = pstates[i]->base.plane;
blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST);
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
index a874fd95cc20..374704cce656 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
@@ -224,7 +224,6 @@ static const struct mdp_kms_funcs kms_funcs = {
.prepare_commit = mdp5_prepare_commit,
.wait_flush = mdp5_wait_flush,
.complete_commit = mdp5_complete_commit,
- .get_format = mdp_get_format,
.destroy = mdp5_kms_destroy,
},
.set_irqmask = mdp5_set_irqmask,
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
index fac9f05aa639..36b6842dfc9c 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
@@ -171,13 +171,13 @@ struct mdp5_encoder {
static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
{
WARN_ON(mdp5_kms->enable_count <= 0);
- msm_writel(data, mdp5_kms->mmio + reg);
+ writel(data, mdp5_kms->mmio + reg);
}
static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
{
WARN_ON(mdp5_kms->enable_count <= 0);
- return msm_readl(mdp5_kms->mmio + reg);
+ return readl(mdp5_kms->mmio + reg);
}
static inline const char *stage2name(enum mdp_mixer_stage_id stage)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
index 0d5ff03cb091..62de248ed1b0 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c
@@ -17,9 +17,6 @@
struct mdp5_plane {
struct drm_plane base;
-
- uint32_t nformats;
- uint32_t formats[32];
};
#define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
@@ -38,15 +35,6 @@ static bool plane_enabled(struct drm_plane_state *state)
return state->visible;
}
-static void mdp5_plane_destroy(struct drm_plane *plane)
-{
- struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
-
- drm_plane_cleanup(plane);
-
- kfree(mdp5_plane);
-}
-
/* helper to install properties which are common to planes and crtcs */
static void mdp5_plane_install_properties(struct drm_plane *plane,
struct drm_mode_object *obj)
@@ -138,7 +126,6 @@ static void mdp5_plane_destroy_state(struct drm_plane *plane,
static const struct drm_plane_funcs mdp5_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
- .destroy = mdp5_plane_destroy,
.reset = mdp5_plane_reset,
.atomic_duplicate_state = mdp5_plane_duplicate_state,
.atomic_destroy_state = mdp5_plane_destroy_state,
@@ -231,12 +218,12 @@ static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
if (plane_enabled(state)) {
unsigned int rotation;
- const struct mdp_format *format;
+ const struct msm_format *format;
struct mdp5_kms *mdp5_kms = get_kms(plane);
uint32_t blkcfg = 0;
- format = to_mdp_format(msm_framebuffer_format(state->fb));
- if (MDP_FORMAT_IS_YUV(format))
+ format = msm_framebuffer_format(state->fb);
+ if (MSM_FORMAT_IS_YUV(format))
caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
if (((state->src_w >> 16) != state->crtc_w) ||
@@ -271,8 +258,8 @@ static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
new_hwpipe = true;
if (mdp5_kms->smp) {
- const struct mdp_format *format =
- to_mdp_format(msm_framebuffer_format(state->fb));
+ const struct msm_format *format =
+ msm_framebuffer_format(state->fb);
blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
state->src_w >> 16, false);
@@ -633,14 +620,14 @@ static int calc_scaley_steps(struct drm_plane *plane,
return 0;
}
-static uint32_t get_scale_config(const struct mdp_format *format,
+static uint32_t get_scale_config(const struct msm_format *format,
uint32_t src, uint32_t dst, bool horz)
{
- const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
- bool scaling = format->is_yuv ? true : (src != dst);
+ const struct drm_format_info *info = drm_format_info(format->pixel_format);
+ bool yuv = MSM_FORMAT_IS_YUV(format);
+ bool scaling = yuv ? true : (src != dst);
uint32_t sub;
uint32_t ya_filter, uv_filter;
- bool yuv = format->is_yuv;
if (!scaling)
return 0;
@@ -664,12 +651,12 @@ static uint32_t get_scale_config(const struct mdp_format *format,
COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
}
-static void calc_pixel_ext(const struct mdp_format *format,
+static void calc_pixel_ext(const struct msm_format *format,
uint32_t src, uint32_t dst, uint32_t phase_step[2],
int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
bool horz)
{
- bool scaling = format->is_yuv ? true : (src != dst);
+ bool scaling = MSM_FORMAT_IS_YUV(format) ? true : (src != dst);
int i;
/*
@@ -687,11 +674,11 @@ static void calc_pixel_ext(const struct mdp_format *format,
}
static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
- const struct mdp_format *format,
+ const struct msm_format *format,
uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
{
- const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
+ const struct drm_format_info *info = drm_format_info(format->pixel_format);
uint32_t lr, tb, req;
int i;
@@ -699,7 +686,7 @@ static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
uint32_t roi_w = src_w;
uint32_t roi_h = src_h;
- if (format->is_yuv && i == COMP_1_2) {
+ if (MSM_FORMAT_IS_YUV(format) && i == COMP_1_2) {
roi_w /= info->hsub;
roi_h /= info->vsub;
}
@@ -773,8 +760,8 @@ static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
{
enum mdp5_pipe pipe = hwpipe->pipe;
bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
- const struct mdp_format *format =
- to_mdp_format(msm_framebuffer_format(fb));
+ const struct msm_format *format =
+ msm_framebuffer_format(fb);
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
@@ -798,21 +785,22 @@ static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
- MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
- MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
- MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
+ MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r_cr) |
+ MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g_y) |
+ MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b_cb) |
COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
- MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
+ MDP5_PIPE_SRC_FORMAT_CPP(format->bpp - 1) |
MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
- COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
+ COND(format->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT,
+ MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
- MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
- MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
- MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
- MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
+ MDP5_PIPE_SRC_UNPACK_ELEM0(format->element[0]) |
+ MDP5_PIPE_SRC_UNPACK_ELEM1(format->element[1]) |
+ MDP5_PIPE_SRC_UNPACK_ELEM2(format->element[2]) |
+ MDP5_PIPE_SRC_UNPACK_ELEM3(format->element[3]));
mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
(hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
@@ -845,7 +833,7 @@ static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
}
if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
- if (MDP_FORMAT_IS_YUV(format))
+ if (MSM_FORMAT_IS_YUV(format))
csc_enable(mdp5_kms, pipe,
mdp_get_default_csc_cfg(CSC_YUV2RGB));
else
@@ -864,7 +852,7 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
struct mdp5_kms *mdp5_kms = get_kms(plane);
enum mdp5_pipe pipe = hwpipe->pipe;
struct mdp5_hw_pipe *right_hwpipe;
- const struct mdp_format *format;
+ const struct msm_format *format;
uint32_t nplanes, config = 0;
struct phase_step step = { { 0 } };
struct pixel_ext pe = { { 0 } };
@@ -885,8 +873,8 @@ static int mdp5_plane_mode_set(struct drm_plane *plane,
if (WARN_ON(nplanes > pipe2nclients(pipe)))
return -EINVAL;
- format = to_mdp_format(msm_framebuffer_format(fb));
- pix_format = format->base.pixel_format;
+ format = msm_framebuffer_format(fb);
+ pix_format = format->pixel_format;
src_x = src->x1;
src_y = src->y1;
@@ -1007,31 +995,48 @@ uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
return mask;
}
+static const uint32_t mdp5_plane_formats[] = {
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_RGBA8888,
+ DRM_FORMAT_BGRA8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_RGBX8888,
+ DRM_FORMAT_BGRX8888,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_NV21,
+ DRM_FORMAT_NV16,
+ DRM_FORMAT_NV61,
+ DRM_FORMAT_VYUY,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_YUV420,
+ DRM_FORMAT_YVU420,
+};
+
/* initialize plane */
struct drm_plane *mdp5_plane_init(struct drm_device *dev,
enum drm_plane_type type)
{
struct drm_plane *plane = NULL;
struct mdp5_plane *mdp5_plane;
- int ret;
- mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
- if (!mdp5_plane) {
- ret = -ENOMEM;
- goto fail;
- }
+ mdp5_plane = drmm_universal_plane_alloc(dev, struct mdp5_plane, base,
+ 0xff, &mdp5_plane_funcs,
+ mdp5_plane_formats, ARRAY_SIZE(mdp5_plane_formats),
+ NULL, type, NULL);
+ if (IS_ERR(mdp5_plane))
+ return ERR_CAST(mdp5_plane);
plane = &mdp5_plane->base;
- mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
- ARRAY_SIZE(mdp5_plane->formats), false);
-
- ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
- mdp5_plane->formats, mdp5_plane->nformats,
- NULL, type, NULL);
- if (ret)
- goto fail;
-
drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
mdp5_plane_install_properties(plane, &plane->base);
@@ -1039,10 +1044,4 @@ struct drm_plane *mdp5_plane_init(struct drm_device *dev,
drm_plane_enable_fb_damage_clips(plane);
return plane;
-
-fail:
- if (plane)
- mdp5_plane_destroy(plane);
-
- return ERR_PTR(ret);
}
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
index b4bebb425d22..3a7f7edda96b 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c
@@ -114,10 +114,10 @@ static void set_fifo_thresholds(struct mdp5_smp *smp,
* presumably happens during the dma from scanout buffer).
*/
uint32_t mdp5_smp_calculate(struct mdp5_smp *smp,
- const struct mdp_format *format,
+ const struct msm_format *format,
u32 width, bool hdecim)
{
- const struct drm_format_info *info = drm_format_info(format->base.pixel_format);
+ const struct drm_format_info *info = drm_format_info(format->pixel_format);
struct mdp5_kms *mdp5_kms = get_kms(smp);
int rev = mdp5_cfg_get_hw_rev(mdp5_kms->cfg);
int i, hsub, nplanes, nlines;
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h
index 21732ed485be..1be9832382d7 100644
--- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h
+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h
@@ -74,7 +74,7 @@ void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p,
struct mdp5_global_state *global_state);
uint32_t mdp5_smp_calculate(struct mdp5_smp *smp,
- const struct mdp_format *format,
+ const struct msm_format *format,
u32 width, bool hdecim);
int mdp5_smp_assign(struct mdp5_smp *smp, struct mdp5_smp_state *state,
diff --git a/drivers/gpu/drm/msm/disp/mdp_common.xml.h b/drivers/gpu/drm/msm/disp/mdp_common.xml.h
deleted file mode 100644
index 4dd8d7db2862..000000000000
--- a/drivers/gpu/drm/msm/disp/mdp_common.xml.h
+++ /dev/null
@@ -1,111 +0,0 @@
-#ifndef MDP_COMMON_XML
-#define MDP_COMMON_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
-
-Copyright (C) 2013-2022 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-enum mdp_chroma_samp_type {
- CHROMA_FULL = 0,
- CHROMA_H2V1 = 1,
- CHROMA_H1V2 = 2,
- CHROMA_420 = 3,
-};
-
-enum mdp_fetch_type {
- MDP_PLANE_INTERLEAVED = 0,
- MDP_PLANE_PLANAR = 1,
- MDP_PLANE_PSEUDO_PLANAR = 2,
-};
-
-enum mdp_mixer_stage_id {
- STAGE_UNUSED = 0,
- STAGE_BASE = 1,
- STAGE0 = 2,
- STAGE1 = 3,
- STAGE2 = 4,
- STAGE3 = 5,
- STAGE4 = 6,
- STAGE5 = 7,
- STAGE6 = 8,
- STAGE_MAX = 8,
-};
-
-enum mdp_alpha_type {
- FG_CONST = 0,
- BG_CONST = 1,
- FG_PIXEL = 2,
- BG_PIXEL = 3,
-};
-
-enum mdp_component_type {
- COMP_0 = 0,
- COMP_1_2 = 1,
- COMP_3 = 2,
- COMP_MAX = 3,
-};
-
-enum mdp_bpc {
- BPC1 = 0,
- BPC5 = 1,
- BPC6 = 2,
- BPC8 = 3,
-};
-
-enum mdp_bpc_alpha {
- BPC1A = 0,
- BPC4A = 1,
- BPC6A = 2,
- BPC8A = 3,
-};
-
-
-#endif /* MDP_COMMON_XML */
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c
index 025595336f26..426782d50cb4 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.c
+++ b/drivers/gpu/drm/msm/disp/mdp_format.c
@@ -62,115 +62,573 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
},
};
-#define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt, fp, cs, yuv) { \
- .base = { .pixel_format = DRM_FORMAT_ ## name }, \
- .bpc_a = BPC ## a ## A, \
- .bpc_r = BPC ## r, \
- .bpc_g = BPC ## g, \
- .bpc_b = BPC ## b, \
- .unpack = { e0, e1, e2, e3 }, \
- .alpha_enable = alpha, \
- .unpack_tight = tight, \
- .cpp = c, \
- .unpack_count = cnt, \
- .fetch_type = fp, \
- .chroma_sample = cs, \
- .is_yuv = yuv, \
+#define MDP_TILE_HEIGHT_DEFAULT 1
+#define MDP_TILE_HEIGHT_UBWC 4
+#define MDP_TILE_HEIGHT_NV12 8
+
+#define INTERLEAVED_RGB_FMT(fmt, a, r, g, b, e0, e1, e2, e3, uc, alpha, \
+bp, flg, fm, np) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
+ .alpha_enable = alpha, \
+ .element = { (e0), (e1), (e2), (e3) }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = CHROMA_FULL, \
+ .unpack_count = uc, \
+ .bpp = bp, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .num_planes = np, \
+ .tile_height = MDP_TILE_HEIGHT_DEFAULT \
}
-#define BPC0A 0
+#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \
+alpha, bp, flg, fm, np, th) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
+ .alpha_enable = alpha, \
+ .element = { (e0), (e1), (e2), (e3) }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = CHROMA_FULL, \
+ .unpack_count = uc, \
+ .bpp = bp, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .num_planes = np, \
+ .tile_height = th \
+}
-/*
- * Note: Keep RGB formats 1st, followed by YUV formats to avoid breaking
- * mdp_get_rgb_formats()'s implementation.
- */
-static const struct mdp_format formats[] = {
- /* name a r g b e0 e1 e2 e3 alpha tight cpp cnt ... */
- FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, true, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, true, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, true, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, true, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(XBGR8888, 8, 8, 8, 8, 2, 0, 1, 3, false, true, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGBX8888, 8, 8, 8, 8, 3, 1, 0, 2, false, true, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGRX8888, 8, 8, 8, 8, 3, 2, 0, 1, false, true, 4, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 3, 3,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGR888, 0, 8, 8, 8, 2, 0, 1, 0, false, true, 3, 3,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(RGB565, 0, 5, 6, 5, 1, 0, 2, 0, false, true, 2, 3,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
- FMT(BGR565, 0, 5, 6, 5, 2, 0, 1, 0, false, true, 2, 3,
- MDP_PLANE_INTERLEAVED, CHROMA_FULL, false),
+#define INTERLEAVED_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, e3, \
+alpha, chroma, count, bp, flg, fm, np) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
+ .alpha_enable = alpha, \
+ .element = { (e0), (e1), (e2), (e3)}, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = count, \
+ .bpp = bp, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .num_planes = np, \
+ .tile_height = MDP_TILE_HEIGHT_DEFAULT \
+}
+
+#define PSEUDO_YUV_FMT(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .alpha_enable = 0, \
+ .element = { (e0), (e1), 0, 0 }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = 2, \
+ .bpp = 2, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .num_planes = np, \
+ .tile_height = MDP_TILE_HEIGHT_DEFAULT \
+}
+
+#define PSEUDO_YUV_FMT_TILED(fmt, a, r, g, b, e0, e1, chroma, \
+flg, fm, np, th) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .alpha_enable = 0, \
+ .element = { (e0), (e1), 0, 0 }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = 2, \
+ .bpp = 2, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .num_planes = np, \
+ .tile_height = th \
+}
+
+#define PSEUDO_YUV_FMT_LOOSE(fmt, a, r, g, b, e0, e1, chroma, flg, fm, np)\
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .alpha_enable = 0, \
+ .element = { (e0), (e1), 0, 0 }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = 2, \
+ .bpp = 2, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
+ .num_planes = np, \
+ .tile_height = MDP_TILE_HEIGHT_DEFAULT \
+}
+
+#define PSEUDO_YUV_FMT_LOOSE_TILED(fmt, a, r, g, b, e0, e1, chroma, \
+flg, fm, np, th) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PSEUDO_PLANAR, \
+ .alpha_enable = 0, \
+ .element = { (e0), (e1), 0, 0 }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = 2, \
+ .bpp = 2, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB | flg, \
+ .num_planes = np, \
+ .tile_height = th \
+}
+
+#define PLANAR_YUV_FMT(fmt, a, r, g, b, e0, e1, e2, alpha, chroma, bp, \
+flg, fm, np) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_PLANAR, \
+ .alpha_enable = alpha, \
+ .element = { (e0), (e1), (e2), 0 }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = chroma, \
+ .unpack_count = 1, \
+ .bpp = bp, \
+ .fetch_mode = fm, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .num_planes = np, \
+ .tile_height = MDP_TILE_HEIGHT_DEFAULT \
+}
+
+static const struct msm_format mdp_formats[] = {
+ INTERLEAVED_RGB_FMT(ARGB8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ true, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ABGR8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XBGR8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBA8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ true, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRA8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ true, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRX8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ false, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XRGB8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ false, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBX8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ false, 4, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGB888,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
+ false, 3, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGR888,
+ 0, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
+ false, 3, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGB565,
+ 0, BPC5, BPC6, BPC5,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, 0, 3,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGR565,
+ 0, BPC5, BPC6, BPC5,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ARGB1555,
+ BPC1A, BPC5, BPC5, BPC5,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ABGR1555,
+ BPC1A, BPC5, BPC5, BPC5,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBA5551,
+ BPC1A, BPC5, BPC5, BPC5,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRA5551,
+ BPC1A, BPC5, BPC5, BPC5,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XRGB1555,
+ BPC1A, BPC5, BPC5, BPC5,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XBGR1555,
+ BPC1A, BPC5, BPC5, BPC5,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBX5551,
+ BPC1A, BPC5, BPC5, BPC5,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRX5551,
+ BPC1A, BPC5, BPC5, BPC5,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ARGB4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ABGR4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBA4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRA4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ true, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XRGB4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XBGR4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBX4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRX4444,
+ BPC4A, BPC4, BPC4, BPC4,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ false, 2, 0,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRA1010102,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ true, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBA1010102,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ true, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ABGR2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(ARGB2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XRGB2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4,
+ false, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(BGRX1010102,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4,
+ false, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(XBGR2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
+
+ INTERLEAVED_RGB_FMT(RGBX1010102,
+ BPC8A, BPC8, BPC8, BPC8,
+ C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4,
+ false, 4, MSM_FORMAT_FLAG_DX,
+ MDP_FETCH_LINEAR, 1),
/* --- RGB formats above / YUV formats below this line --- */
/* 2 plane YUV */
- FMT(NV12, 0, 8, 8, 8, 1, 2, 0, 0, false, true, 2, 2,
- MDP_PLANE_PSEUDO_PLANAR, CHROMA_420, true),
- FMT(NV21, 0, 8, 8, 8, 2, 1, 0, 0, false, true, 2, 2,
- MDP_PLANE_PSEUDO_PLANAR, CHROMA_420, true),
- FMT(NV16, 0, 8, 8, 8, 1, 2, 0, 0, false, true, 2, 2,
- MDP_PLANE_PSEUDO_PLANAR, CHROMA_H2V1, true),
- FMT(NV61, 0, 8, 8, 8, 2, 1, 0, 0, false, true, 2, 2,
- MDP_PLANE_PSEUDO_PLANAR, CHROMA_H2V1, true),
+ PSEUDO_YUV_FMT(NV12,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr,
+ CHROMA_420, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ PSEUDO_YUV_FMT(NV21,
+ 0, BPC8, BPC8, BPC8,
+ C2_R_Cr, C1_B_Cb,
+ CHROMA_420, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ PSEUDO_YUV_FMT(NV16,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr,
+ CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ PSEUDO_YUV_FMT(NV61,
+ 0, BPC8, BPC8, BPC8,
+ C2_R_Cr, C1_B_Cb,
+ CHROMA_H2V1, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ PSEUDO_YUV_FMT_LOOSE(P010,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr,
+ CHROMA_420, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
/* 1 plane YUV */
- FMT(VYUY, 0, 8, 8, 8, 2, 0, 1, 0, false, true, 2, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
- FMT(UYVY, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 2, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
- FMT(YUYV, 0, 8, 8, 8, 0, 1, 0, 2, false, true, 2, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
- FMT(YVYU, 0, 8, 8, 8, 0, 2, 0, 1, false, true, 2, 4,
- MDP_PLANE_INTERLEAVED, CHROMA_H2V1, true),
+ INTERLEAVED_YUV_FMT(VYUY,
+ 0, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ INTERLEAVED_YUV_FMT(UYVY,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ INTERLEAVED_YUV_FMT(YUYV,
+ 0, BPC8, BPC8, BPC8,
+ C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
+ INTERLEAVED_YUV_FMT(YVYU,
+ 0, BPC8, BPC8, BPC8,
+ C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb,
+ false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 2),
+
/* 3 plane YUV */
- FMT(YUV420, 0, 8, 8, 8, 2, 1, 0, 0, false, true, 1, 1,
- MDP_PLANE_PLANAR, CHROMA_420, true),
- FMT(YVU420, 0, 8, 8, 8, 1, 2, 0, 0, false, true, 1, 1,
- MDP_PLANE_PLANAR, CHROMA_420, true),
+ PLANAR_YUV_FMT(YUV420,
+ 0, BPC8, BPC8, BPC8,
+ C2_R_Cr, C1_B_Cb, C0_G_Y,
+ false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 3),
+
+ PLANAR_YUV_FMT(YVU420,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr, C0_G_Y,
+ false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV,
+ MDP_FETCH_LINEAR, 3),
};
/*
- * Note:
- * @rgb_only must be set to true, when requesting
- * supported formats for RGB pipes.
+ * UBWC formats table:
+ * This table holds the UBWC formats supported.
+ * If a compression ratio needs to be used for this or any other format,
+ * the data will be passed by user-space.
*/
-uint32_t mdp_get_formats(uint32_t *pixel_formats, uint32_t max_formats,
- bool rgb_only)
-{
- uint32_t i;
- for (i = 0; i < ARRAY_SIZE(formats); i++) {
- const struct mdp_format *f = &formats[i];
+static const struct msm_format mdp_formats_ubwc[] = {
+ INTERLEAVED_RGB_FMT_TILED(BGR565,
+ 0, BPC5, BPC6, BPC5,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
+ false, 2, MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
- if (i == max_formats)
- break;
+ INTERLEAVED_RGB_FMT_TILED(ABGR8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
- if (rgb_only && MDP_FORMAT_IS_YUV(f))
- break;
+ /* ARGB8888 and ABGR8888 purposely have the same color
+ * ordering. The hardware only supports ABGR8888 UBWC
+ * natively.
+ */
+ INTERLEAVED_RGB_FMT_TILED(ARGB8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
- pixel_formats[i] = f->base.pixel_format;
- }
+ INTERLEAVED_RGB_FMT_TILED(XBGR8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 4, MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
- return i;
-}
+ INTERLEAVED_RGB_FMT_TILED(XRGB8888,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ false, 4, MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ /* XRGB2101010 and ARGB2101010 purposely have the same color
+ * ordering. The hardware only supports ARGB2101010 UBWC
+ * natively.
+ */
+ INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
+ BPC8A, BPC8, BPC8, BPC8,
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
+ true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 2, MDP_TILE_HEIGHT_UBWC),
+
+ PSEUDO_YUV_FMT_TILED(NV12,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr,
+ CHROMA_420, MSM_FORMAT_FLAG_YUV |
+ MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 4, MDP_TILE_HEIGHT_NV12),
+
+ PSEUDO_YUV_FMT_TILED(P010,
+ 0, BPC8, BPC8, BPC8,
+ C1_B_Cb, C2_R_Cr,
+ CHROMA_420, MSM_FORMAT_FLAG_DX |
+ MSM_FORMAT_FLAG_YUV |
+ MSM_FORMAT_FLAG_COMPRESSED,
+ MDP_FETCH_UBWC, 4, MDP_TILE_HEIGHT_UBWC),
+};
const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format,
uint64_t modifier)
{
+ const struct msm_format *map = NULL;
+ ssize_t map_size;
int i;
- for (i = 0; i < ARRAY_SIZE(formats); i++) {
- const struct mdp_format *f = &formats[i];
- if (f->base.pixel_format == format)
- return &f->base;
+
+ switch (modifier) {
+ case 0:
+ map = mdp_formats;
+ map_size = ARRAY_SIZE(mdp_formats);
+ break;
+ case DRM_FORMAT_MOD_QCOM_COMPRESSED:
+ map = mdp_formats_ubwc;
+ map_size = ARRAY_SIZE(mdp_formats_ubwc);
+ break;
+ default:
+ drm_err(kms->dev, "unsupported format modifier %llX\n", modifier);
+ return NULL;
}
+
+ for (i = 0; i < map_size; i++) {
+ const struct msm_format *f = &map[i];
+
+ if (f->pixel_format == format)
+ return f;
+ }
+
+ drm_err(kms->dev, "unsupported fmt: %p4cc modifier 0x%llX\n",
+ &format, modifier);
+
return NULL;
}
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.h b/drivers/gpu/drm/msm/disp/mdp_format.h
new file mode 100644
index 000000000000..a00d646ff4d4
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/mdp_format.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
+ * Copyright (C) 2013 Red Hat
+ * Author: Rob Clark <robdclark@gmail.com>
+ */
+
+#ifndef __MSM_FORMAT_H__
+#define __MSM_FORMAT_H__
+
+#include "mdp_common.xml.h"
+
+enum msm_format_flags {
+ MSM_FORMAT_FLAG_YUV_BIT,
+ MSM_FORMAT_FLAG_DX_BIT,
+ MSM_FORMAT_FLAG_COMPRESSED_BIT,
+ MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT,
+ MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB_BIT,
+};
+
+#define MSM_FORMAT_FLAG_YUV BIT(MSM_FORMAT_FLAG_YUV_BIT)
+#define MSM_FORMAT_FLAG_DX BIT(MSM_FORMAT_FLAG_DX_BIT)
+#define MSM_FORMAT_FLAG_COMPRESSED BIT(MSM_FORMAT_FLAG_COMPRESSED_BIT)
+#define MSM_FORMAT_FLAG_UNPACK_TIGHT BIT(MSM_FORMAT_FLAG_UNPACK_TIGHT_BIT)
+#define MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB BIT(MSM_FORMAT_FLAG_UNPACK_ALIGN_MSB_BIT)
+
+/**
+ * DPU HW,Component order color map
+ */
+enum {
+ C0_G_Y = 0,
+ C1_B_Cb = 1,
+ C2_R_Cr = 2,
+ C3_ALPHA = 3
+};
+
+/**
+ * struct msm_format: defines the format configuration
+ * @pixel_format: format fourcc
+ * @element: element color ordering
+ * @fetch_type: how the color components are packed in pixel format
+ * @chroma_sample: chroma sub-samplng type
+ * @alpha_enable: whether the format has an alpha channel
+ * @unpack_count: number of the components to unpack
+ * @bpp: bytes per pixel
+ * @flags: usage bit flags
+ * @num_planes: number of planes (including meta data planes)
+ * @fetch_mode: linear, tiled, or ubwc hw fetch behavior
+ * @tile_height: format tile height
+ */
+struct msm_format {
+ uint32_t pixel_format;
+ enum mdp_bpc bpc_g_y, bpc_b_cb, bpc_r_cr;
+ enum mdp_bpc_alpha bpc_a;
+ u8 element[4];
+ enum mdp_fetch_type fetch_type;
+ enum mdp_chroma_samp_type chroma_sample;
+ bool alpha_enable;
+ u8 unpack_count;
+ u8 bpp;
+ unsigned long flags;
+ u8 num_planes;
+ enum mdp_fetch_mode fetch_mode;
+ u16 tile_height;
+};
+
+#define MSM_FORMAT_IS_YUV(X) ((X)->flags & MSM_FORMAT_FLAG_YUV)
+#define MSM_FORMAT_IS_DX(X) ((X)->flags & MSM_FORMAT_FLAG_DX)
+#define MSM_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == MDP_FETCH_LINEAR)
+#define MSM_FORMAT_IS_TILE(X) \
+ (((X)->fetch_mode == MDP_FETCH_UBWC) && \
+ !((X)->flags & MSM_FORMAT_FLAG_COMPRESSED))
+#define MSM_FORMAT_IS_UBWC(X) \
+ (((X)->fetch_mode == MDP_FETCH_UBWC) && \
+ ((X)->flags & MSM_FORMAT_FLAG_COMPRESSED))
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/mdp_kms.h b/drivers/gpu/drm/msm/disp/mdp_kms.h
index b0286d5d5130..068fbeac6edb 100644
--- a/drivers/gpu/drm/msm/disp/mdp_kms.h
+++ b/drivers/gpu/drm/msm/disp/mdp_kms.h
@@ -11,6 +11,7 @@
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
+#include "mdp_format.h"
#include "msm_drv.h"
#include "msm_kms.h"
#include "mdp_common.xml.h"
@@ -77,23 +78,6 @@ void mdp_irq_update(struct mdp_kms *mdp_kms);
* pixel format helpers:
*/
-struct mdp_format {
- struct msm_format base;
- enum mdp_bpc bpc_r, bpc_g, bpc_b;
- enum mdp_bpc_alpha bpc_a;
- uint8_t unpack[4];
- bool alpha_enable, unpack_tight;
- uint8_t cpp, unpack_count;
- enum mdp_fetch_type fetch_type;
- enum mdp_chroma_samp_type chroma_sample;
- bool is_yuv;
-};
-#define to_mdp_format(x) container_of(x, struct mdp_format, base)
-#define MDP_FORMAT_IS_YUV(mdp_format) ((mdp_format)->is_yuv)
-
-uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats, bool rgb_only);
-const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
-
/* MDP capabilities */
#define MDP_CAP_SMP BIT(0) /* Shared Memory Pool */
#define MDP_CAP_DSC BIT(1) /* VESA Display Stream Compression */
diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c b/drivers/gpu/drm/msm/dp/dp_audio.c
index 7634e4b74208..a599fc5d63c5 100644
--- a/drivers/gpu/drm/msm/dp/dp_audio.c
+++ b/drivers/gpu/drm/msm/dp/dp_audio.c
@@ -22,9 +22,7 @@ struct dp_audio_private {
struct platform_device *pdev;
struct drm_device *drm_dev;
struct dp_catalog *catalog;
- struct dp_panel *panel;
- bool engine_on;
u32 channels;
struct dp_audio dp_audio;
@@ -34,11 +32,7 @@ static u32 dp_audio_get_header(struct dp_catalog *catalog,
enum dp_catalog_audio_sdp_type sdp,
enum dp_catalog_audio_header_type header)
{
- catalog->sdp_type = sdp;
- catalog->sdp_header = header;
- dp_catalog_audio_get_header(catalog);
-
- return catalog->audio_data;
+ return dp_catalog_audio_get_header(catalog, sdp, header);
}
static void dp_audio_set_header(struct dp_catalog *catalog,
@@ -46,10 +40,7 @@ static void dp_audio_set_header(struct dp_catalog *catalog,
enum dp_catalog_audio_sdp_type sdp,
enum dp_catalog_audio_header_type header)
{
- catalog->sdp_type = sdp;
- catalog->sdp_header = header;
- catalog->audio_data = data;
- dp_catalog_audio_set_header(catalog);
+ dp_catalog_audio_set_header(catalog, sdp, header, data);
}
static void dp_audio_stream_sdp(struct dp_audio_private *audio)
@@ -319,8 +310,7 @@ static void dp_audio_setup_acr(struct dp_audio_private *audio)
break;
}
- catalog->audio_data = select;
- dp_catalog_audio_config_acr(catalog);
+ dp_catalog_audio_config_acr(catalog, select);
}
static void dp_audio_safe_to_exit_level(struct dp_audio_private *audio)
@@ -346,18 +336,14 @@ static void dp_audio_safe_to_exit_level(struct dp_audio_private *audio)
break;
}
- catalog->audio_data = safe_to_exit_level;
- dp_catalog_audio_sfe_level(catalog);
+ dp_catalog_audio_sfe_level(catalog, safe_to_exit_level);
}
static void dp_audio_enable(struct dp_audio_private *audio, bool enable)
{
struct dp_catalog *catalog = audio->catalog;
- catalog->audio_data = enable;
- dp_catalog_audio_enable(catalog);
-
- audio->engine_on = enable;
+ dp_catalog_audio_enable(catalog, enable);
}
static struct dp_audio_private *dp_audio_get_data(struct platform_device *pdev)
@@ -571,7 +557,6 @@ struct dp_audio *dp_audio_get(struct platform_device *pdev,
}
audio->pdev = pdev;
- audio->panel = panel;
audio->catalog = catalog;
dp_audio = &audio->dp_audio;
diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_aux.c
index adbd5a367395..da46a433bf74 100644
--- a/drivers/gpu/drm/msm/dp/dp_aux.c
+++ b/drivers/gpu/drm/msm/dp/dp_aux.c
@@ -38,6 +38,7 @@ struct dp_aux_private {
bool no_send_stop;
bool initted;
bool is_edp;
+ bool enable_xfers;
u32 offset;
u32 segment;
@@ -87,8 +88,7 @@ static ssize_t dp_aux_write(struct dp_aux_private *aux,
/* index = 0, write */
if (i == 0)
reg |= DP_AUX_DATA_INDEX_WRITE;
- aux->catalog->aux_data = reg;
- dp_catalog_aux_write_data(aux->catalog);
+ dp_catalog_aux_write_data(aux->catalog, reg);
}
dp_catalog_aux_clear_trans(aux->catalog, false);
@@ -106,8 +106,7 @@ static ssize_t dp_aux_write(struct dp_aux_private *aux,
}
reg |= DP_AUX_TRANS_CTRL_GO;
- aux->catalog->aux_data = reg;
- dp_catalog_aux_write_trans(aux->catalog);
+ dp_catalog_aux_write_trans(aux->catalog, reg);
return len;
}
@@ -145,8 +144,7 @@ static ssize_t dp_aux_cmd_fifo_rx(struct dp_aux_private *aux,
data = DP_AUX_DATA_INDEX_WRITE; /* INDEX_WRITE */
data |= DP_AUX_DATA_READ; /* read */
- aux->catalog->aux_data = data;
- dp_catalog_aux_write_data(aux->catalog);
+ dp_catalog_aux_write_data(aux->catalog, data);
dp = msg->buffer;
@@ -305,19 +303,14 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux,
}
/*
- * For eDP it's important to give a reasonably long wait here for HPD
- * to be asserted. This is because the panel driver may have _just_
- * turned on the panel and then tried to do an AUX transfer. The panel
- * driver has no way of knowing when the panel is ready, so it's up
- * to us to wait. For DP we never get into this situation so let's
- * avoid ever doing the extra long wait for DP.
+ * If we're using DP and an external display isn't connected then the
+ * transfer won't succeed. Return right away. If we don't do this we
+ * can end up with long timeouts if someone tries to access the DP AUX
+ * character device when no DP device is connected.
*/
- if (aux->is_edp) {
- ret = dp_catalog_aux_wait_for_hpd_connect_state(aux->catalog);
- if (ret) {
- DRM_DEBUG_DP("Panel not ready for aux transactions\n");
- goto exit;
- }
+ if (!aux->is_edp && !aux->enable_xfers) {
+ ret = -ENXIO;
+ goto exit;
}
dp_aux_update_offset_and_segment(aux, msg);
@@ -436,6 +429,14 @@ irqreturn_t dp_aux_isr(struct drm_dp_aux *dp_aux)
return IRQ_HANDLED;
}
+void dp_aux_enable_xfers(struct drm_dp_aux *dp_aux, bool enabled)
+{
+ struct dp_aux_private *aux;
+
+ aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
+ aux->enable_xfers = enabled;
+}
+
void dp_aux_reconfig(struct drm_dp_aux *dp_aux)
{
struct dp_aux_private *aux;
@@ -513,7 +514,7 @@ static int dp_wait_hpd_asserted(struct drm_dp_aux *dp_aux,
aux = container_of(dp_aux, struct dp_aux_private, dp_aux);
pm_runtime_get_sync(aux->dev);
- ret = dp_catalog_aux_wait_for_hpd_connect_state(aux->catalog);
+ ret = dp_catalog_aux_wait_for_hpd_connect_state(aux->catalog, wait_us);
pm_runtime_put_sync(aux->dev);
return ret;
diff --git a/drivers/gpu/drm/msm/dp/dp_aux.h b/drivers/gpu/drm/msm/dp/dp_aux.h
index f47d591c1f54..4f65e892a807 100644
--- a/drivers/gpu/drm/msm/dp/dp_aux.h
+++ b/drivers/gpu/drm/msm/dp/dp_aux.h
@@ -12,6 +12,7 @@
int dp_aux_register(struct drm_dp_aux *dp_aux);
void dp_aux_unregister(struct drm_dp_aux *dp_aux);
irqreturn_t dp_aux_isr(struct drm_dp_aux *dp_aux);
+void dp_aux_enable_xfers(struct drm_dp_aux *dp_aux, bool enabled);
void dp_aux_init(struct drm_dp_aux *dp_aux);
void dp_aux_deinit(struct drm_dp_aux *dp_aux);
void dp_aux_reconfig(struct drm_dp_aux *dp_aux);
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c
index 3e7c84cdef47..6e55cbf69674 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -81,7 +81,6 @@ struct dp_catalog_private {
struct dss_io_data io;
u32 (*audio_map)[DP_AUDIO_SDP_HEADER_MAX];
struct dp_catalog dp_catalog;
- u8 aux_lut_cfg_index[PHY_AUX_CFG_MAX];
};
void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *disp_state)
@@ -170,21 +169,21 @@ u32 dp_catalog_aux_read_data(struct dp_catalog *dp_catalog)
return dp_read_aux(catalog, REG_DP_AUX_DATA);
}
-int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog)
+int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog, u32 data)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
- dp_write_aux(catalog, REG_DP_AUX_DATA, dp_catalog->aux_data);
+ dp_write_aux(catalog, REG_DP_AUX_DATA, data);
return 0;
}
-int dp_catalog_aux_write_trans(struct dp_catalog *dp_catalog)
+int dp_catalog_aux_write_trans(struct dp_catalog *dp_catalog, u32 data)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
- dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, dp_catalog->aux_data);
+ dp_write_aux(catalog, REG_DP_AUX_TRANS_CTRL, data);
return 0;
}
@@ -263,17 +262,18 @@ void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable)
dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl);
}
-int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog)
+int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog,
+ unsigned long wait_us)
{
u32 state;
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
- /* poll for hpd connected status every 2ms and timeout after 500ms */
+ /* poll for hpd connected status every 2ms and timeout after wait_us */
return readl_poll_timeout(catalog->io.aux.base +
REG_DP_DP_HPD_INT_STATUS,
state, state & DP_DP_HPD_STATE_STATUS_CONNECTED,
- 2000, 500000);
+ min(wait_us, 2000), wait_us);
}
static void dump_regs(void __iomem *base, int len)
@@ -469,7 +469,7 @@ void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog)
void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,
u32 rate, u32 stream_rate_khz,
- bool fixed_nvid, bool is_ycbcr_420)
+ bool is_ycbcr_420)
{
u32 pixel_m, pixel_n;
u32 mvid, nvid, pixel_div = 0, dispcc_input_rate;
@@ -881,19 +881,17 @@ u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog *dp_catalog)
}
/* panel related catalog functions */
-int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog)
+int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog, u32 total,
+ u32 sync_start, u32 width_blanking, u32 dp_active)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
u32 reg;
- dp_write_link(catalog, REG_DP_TOTAL_HOR_VER,
- dp_catalog->total);
- dp_write_link(catalog, REG_DP_START_HOR_VER_FROM_SYNC,
- dp_catalog->sync_start);
- dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY,
- dp_catalog->width_blanking);
- dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, dp_catalog->dp_active);
+ dp_write_link(catalog, REG_DP_TOTAL_HOR_VER, total);
+ dp_write_link(catalog, REG_DP_START_HOR_VER_FROM_SYNC, sync_start);
+ dp_write_link(catalog, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blanking);
+ dp_write_link(catalog, REG_DP_ACTIVE_HOR_VER, dp_active);
reg = dp_read_p0(catalog, MMSS_DP_INTF_CONFIG);
@@ -1162,34 +1160,28 @@ struct dp_catalog *dp_catalog_get(struct device *dev)
return &catalog->dp_catalog;
}
-void dp_catalog_audio_get_header(struct dp_catalog *dp_catalog)
+u32 dp_catalog_audio_get_header(struct dp_catalog *dp_catalog,
+ enum dp_catalog_audio_sdp_type sdp,
+ enum dp_catalog_audio_header_type header)
{
struct dp_catalog_private *catalog;
u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
- enum dp_catalog_audio_sdp_type sdp;
- enum dp_catalog_audio_header_type header;
-
- if (!dp_catalog)
- return;
catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
sdp_map = catalog->audio_map;
- sdp = dp_catalog->sdp_type;
- header = dp_catalog->sdp_header;
- dp_catalog->audio_data = dp_read_link(catalog,
- sdp_map[sdp][header]);
+ return dp_read_link(catalog, sdp_map[sdp][header]);
}
-void dp_catalog_audio_set_header(struct dp_catalog *dp_catalog)
+void dp_catalog_audio_set_header(struct dp_catalog *dp_catalog,
+ enum dp_catalog_audio_sdp_type sdp,
+ enum dp_catalog_audio_header_type header,
+ u32 data)
{
struct dp_catalog_private *catalog;
u32 (*sdp_map)[DP_AUDIO_SDP_HEADER_MAX];
- enum dp_catalog_audio_sdp_type sdp;
- enum dp_catalog_audio_header_type header;
- u32 data;
if (!dp_catalog)
return;
@@ -1198,17 +1190,14 @@ void dp_catalog_audio_set_header(struct dp_catalog *dp_catalog)
struct dp_catalog_private, dp_catalog);
sdp_map = catalog->audio_map;
- sdp = dp_catalog->sdp_type;
- header = dp_catalog->sdp_header;
- data = dp_catalog->audio_data;
dp_write_link(catalog, sdp_map[sdp][header], data);
}
-void dp_catalog_audio_config_acr(struct dp_catalog *dp_catalog)
+void dp_catalog_audio_config_acr(struct dp_catalog *dp_catalog, u32 select)
{
struct dp_catalog_private *catalog;
- u32 acr_ctrl, select;
+ u32 acr_ctrl;
if (!dp_catalog)
return;
@@ -1216,7 +1205,6 @@ void dp_catalog_audio_config_acr(struct dp_catalog *dp_catalog)
catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
- select = dp_catalog->audio_data;
acr_ctrl = select << 4 | BIT(31) | BIT(8) | BIT(14);
drm_dbg_dp(catalog->drm_dev, "select: %#x, acr_ctrl: %#x\n",
@@ -1225,10 +1213,9 @@ void dp_catalog_audio_config_acr(struct dp_catalog *dp_catalog)
dp_write_link(catalog, MMSS_DP_AUDIO_ACR_CTRL, acr_ctrl);
}
-void dp_catalog_audio_enable(struct dp_catalog *dp_catalog)
+void dp_catalog_audio_enable(struct dp_catalog *dp_catalog, bool enable)
{
struct dp_catalog_private *catalog;
- bool enable;
u32 audio_ctrl;
if (!dp_catalog)
@@ -1237,7 +1224,6 @@ void dp_catalog_audio_enable(struct dp_catalog *dp_catalog)
catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
- enable = !!dp_catalog->audio_data;
audio_ctrl = dp_read_link(catalog, MMSS_DP_AUDIO_CFG);
if (enable)
@@ -1332,10 +1318,10 @@ void dp_catalog_audio_init(struct dp_catalog *dp_catalog)
catalog->audio_map = sdp_map;
}
-void dp_catalog_audio_sfe_level(struct dp_catalog *dp_catalog)
+void dp_catalog_audio_sfe_level(struct dp_catalog *dp_catalog, u32 safe_to_exit_level)
{
struct dp_catalog_private *catalog;
- u32 mainlink_levels, safe_to_exit_level;
+ u32 mainlink_levels;
if (!dp_catalog)
return;
@@ -1343,7 +1329,6 @@ void dp_catalog_audio_sfe_level(struct dp_catalog *dp_catalog)
catalog = container_of(dp_catalog,
struct dp_catalog_private, dp_catalog);
- safe_to_exit_level = dp_catalog->audio_data;
mainlink_levels = dp_read_link(catalog, REG_DP_MAINLINK_LEVELS);
mainlink_levels &= 0xFE0;
mainlink_levels |= safe_to_exit_level;
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h
index 75ec290127c7..4679d50b8c73 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.h
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
@@ -28,26 +28,9 @@
#define DP_INTR_FRAME_END BIT(6)
#define DP_INTR_CRC_UPDATED BIT(9)
-#define DP_AUX_CFG_MAX_VALUE_CNT 3
-
#define DP_HW_VERSION_1_0 0x10000000
#define DP_HW_VERSION_1_2 0x10020000
-/* PHY AUX config registers */
-enum dp_phy_aux_config_type {
- PHY_AUX_CFG0,
- PHY_AUX_CFG1,
- PHY_AUX_CFG2,
- PHY_AUX_CFG3,
- PHY_AUX_CFG4,
- PHY_AUX_CFG5,
- PHY_AUX_CFG6,
- PHY_AUX_CFG7,
- PHY_AUX_CFG8,
- PHY_AUX_CFG9,
- PHY_AUX_CFG_MAX,
-};
-
enum dp_catalog_audio_sdp_type {
DP_AUDIO_SDP_STREAM,
DP_AUDIO_SDP_TIMESTAMP,
@@ -65,14 +48,6 @@ enum dp_catalog_audio_header_type {
};
struct dp_catalog {
- u32 aux_data;
- u32 total;
- u32 sync_start;
- u32 width_blanking;
- u32 dp_active;
- enum dp_catalog_audio_sdp_type sdp_type;
- enum dp_catalog_audio_header_type sdp_header;
- u32 audio_data;
bool wide_bus_en;
};
@@ -81,13 +56,14 @@ void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *d
/* AUX APIs */
u32 dp_catalog_aux_read_data(struct dp_catalog *dp_catalog);
-int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog);
-int dp_catalog_aux_write_trans(struct dp_catalog *dp_catalog);
+int dp_catalog_aux_write_data(struct dp_catalog *dp_catalog, u32 data);
+int dp_catalog_aux_write_trans(struct dp_catalog *dp_catalog, u32 data);
int dp_catalog_aux_clear_trans(struct dp_catalog *dp_catalog, bool read);
int dp_catalog_aux_clear_hw_interrupts(struct dp_catalog *dp_catalog);
void dp_catalog_aux_reset(struct dp_catalog *dp_catalog);
void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable);
-int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog);
+int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog,
+ unsigned long wait_us);
u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog);
/* DP Controller APIs */
@@ -99,7 +75,7 @@ void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, bool ena
void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog);
void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb);
void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate,
- u32 stream_rate_khz, bool fixed_nvid, bool is_ycbcr_420);
+ u32 stream_rate_khz, bool is_ycbcr_420);
int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, u32 pattern);
u32 dp_catalog_hw_revision(const struct dp_catalog *dp_catalog);
void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog);
@@ -124,7 +100,8 @@ void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog,
u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog *dp_catalog);
/* DP Panel APIs */
-int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog);
+int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog, u32 total,
+ u32 sync_start, u32 width_blanking, u32 dp_active);
void dp_catalog_panel_enable_vsc_sdp(struct dp_catalog *dp_catalog, struct dp_sdp *vsc_sdp);
void dp_catalog_panel_disable_vsc_sdp(struct dp_catalog *dp_catalog);
void dp_catalog_dump_regs(struct dp_catalog *dp_catalog);
@@ -135,12 +112,17 @@ void dp_catalog_panel_tpg_disable(struct dp_catalog *dp_catalog);
struct dp_catalog *dp_catalog_get(struct device *dev);
/* DP Audio APIs */
-void dp_catalog_audio_get_header(struct dp_catalog *catalog);
-void dp_catalog_audio_set_header(struct dp_catalog *catalog);
-void dp_catalog_audio_config_acr(struct dp_catalog *catalog);
-void dp_catalog_audio_enable(struct dp_catalog *catalog);
+u32 dp_catalog_audio_get_header(struct dp_catalog *dp_catalog,
+ enum dp_catalog_audio_sdp_type sdp,
+ enum dp_catalog_audio_header_type header);
+void dp_catalog_audio_set_header(struct dp_catalog *dp_catalog,
+ enum dp_catalog_audio_sdp_type sdp,
+ enum dp_catalog_audio_header_type header,
+ u32 data);
+void dp_catalog_audio_config_acr(struct dp_catalog *catalog, u32 select);
+void dp_catalog_audio_enable(struct dp_catalog *catalog, bool enable);
void dp_catalog_audio_config_sdp(struct dp_catalog *catalog);
void dp_catalog_audio_init(struct dp_catalog *catalog);
-void dp_catalog_audio_sfe_level(struct dp_catalog *catalog);
+void dp_catalog_audio_sfe_level(struct dp_catalog *catalog, u32 safe_to_exit_level);
#endif /* _DP_CATALOG_H_ */
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index c4dda1faef67..7bc8a9f0657a 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -1052,14 +1052,14 @@ static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl)
if (ret)
return ret;
- if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) {
+ if (voltage_swing_level >= DP_TRAIN_LEVEL_MAX) {
drm_dbg_dp(ctrl->drm_dev,
"max. voltage swing level reached %d\n",
voltage_swing_level);
max_level_reached |= DP_TRAIN_MAX_SWING_REACHED;
}
- if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) {
+ if (pre_emphasis_level >= DP_TRAIN_LEVEL_MAX) {
drm_dbg_dp(ctrl->drm_dev,
"max. pre-emphasis level reached %d\n",
pre_emphasis_level);
@@ -1150,7 +1150,7 @@ static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl,
}
if (ctrl->link->phy_params.v_level >=
- DP_TRAIN_VOLTAGE_SWING_MAX) {
+ DP_TRAIN_LEVEL_MAX) {
DRM_ERROR_RATELIMITED("max v_level reached\n");
return -EAGAIN;
}
@@ -1566,21 +1566,6 @@ void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl)
phy, phy->init_count, phy->power_count);
}
-static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl)
-{
- const u8 *dpcd = ctrl->panel->dpcd;
-
- /*
- * For better interop experience, used a fixed NVID=0x8000
- * whenever connected to a VGA dongle downstream.
- */
- if (drm_dp_is_branch(dpcd))
- return (drm_dp_has_quirk(&ctrl->panel->desc,
- DP_DPCD_QUIRK_CONSTANT_N));
-
- return false;
-}
-
static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
{
struct phy *phy = ctrl->phy;
@@ -2022,7 +2007,7 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train)
dp_catalog_ctrl_config_msa(ctrl->catalog,
ctrl->link->link_params.rate,
- pixel_rate_orig, dp_ctrl_use_fixed_nvid(ctrl),
+ pixel_rate_orig,
ctrl->panel->dp_mode.out_fmt_is_yuv_420);
dp_ctrl_setup_tr_unit(ctrl);
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h
index fa014cee7e21..ffcbd9a25748 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.h
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h
@@ -12,7 +12,6 @@
#include "dp_catalog.h"
struct dp_ctrl {
- atomic_t aborted;
bool wide_bus_en;
};
diff --git a/drivers/gpu/drm/msm/dp/dp_debug.c b/drivers/gpu/drm/msm/dp/dp_debug.c
index eca5a02f9003..b8611f6d2296 100644
--- a/drivers/gpu/drm/msm/dp/dp_debug.c
+++ b/drivers/gpu/drm/msm/dp/dp_debug.c
@@ -21,8 +21,6 @@ struct dp_debug_private {
struct dp_link *link;
struct dp_panel *panel;
struct drm_connector *connector;
-
- struct dp_debug dp_debug;
};
static int dp_debug_show(struct seq_file *seq, void *p)
@@ -199,10 +197,24 @@ static const struct file_operations test_active_fops = {
.write = dp_test_active_write
};
-static void dp_debug_init(struct dp_debug *dp_debug, struct dentry *root, bool is_edp)
+int dp_debug_init(struct device *dev, struct dp_panel *panel,
+ struct dp_link *link,
+ struct drm_connector *connector,
+ struct dentry *root, bool is_edp)
{
- struct dp_debug_private *debug = container_of(dp_debug,
- struct dp_debug_private, dp_debug);
+ struct dp_debug_private *debug;
+
+ if (!dev || !panel || !link) {
+ DRM_ERROR("invalid input\n");
+ return -EINVAL;
+ }
+
+ debug = devm_kzalloc(dev, sizeof(*debug), GFP_KERNEL);
+ if (!debug)
+ return -ENOMEM;
+
+ debug->link = link;
+ debug->panel = panel;
debugfs_create_file("dp_debug", 0444, root,
debug, &dp_debug_fops);
@@ -220,41 +232,6 @@ static void dp_debug_init(struct dp_debug *dp_debug, struct dentry *root, bool i
root,
debug, &dp_test_type_fops);
}
-}
-struct dp_debug *dp_debug_get(struct device *dev, struct dp_panel *panel,
- struct dp_link *link,
- struct drm_connector *connector,
- struct dentry *root, bool is_edp)
-{
- struct dp_debug_private *debug;
- struct dp_debug *dp_debug;
- int rc;
-
- if (!dev || !panel || !link) {
- DRM_ERROR("invalid input\n");
- rc = -EINVAL;
- goto error;
- }
-
- debug = devm_kzalloc(dev, sizeof(*debug), GFP_KERNEL);
- if (!debug) {
- rc = -ENOMEM;
- goto error;
- }
-
- debug->dp_debug.debug_en = false;
- debug->link = link;
- debug->panel = panel;
-
- dp_debug = &debug->dp_debug;
- dp_debug->vdisplay = 0;
- dp_debug->hdisplay = 0;
- dp_debug->vrefresh = 0;
-
- dp_debug_init(dp_debug, root, is_edp);
-
- return dp_debug;
- error:
- return ERR_PTR(rc);
+ return 0;
}
diff --git a/drivers/gpu/drm/msm/dp/dp_debug.h b/drivers/gpu/drm/msm/dp/dp_debug.h
index 9b3b2e702f65..7e1aa892fc09 100644
--- a/drivers/gpu/drm/msm/dp/dp_debug.h
+++ b/drivers/gpu/drm/msm/dp/dp_debug.h
@@ -9,22 +9,6 @@
#include "dp_panel.h"
#include "dp_link.h"
-/**
- * struct dp_debug
- * @debug_en: specifies whether debug mode enabled
- * @vdisplay: used to filter out vdisplay value
- * @hdisplay: used to filter out hdisplay value
- * @vrefresh: used to filter out vrefresh value
- * @tpg_state: specifies whether tpg feature is enabled
- */
-struct dp_debug {
- bool debug_en;
- int aspect_ratio;
- int vdisplay;
- int hdisplay;
- int vrefresh;
-};
-
#if defined(CONFIG_DEBUG_FS)
/**
@@ -41,22 +25,22 @@ struct dp_debug {
* This function sets up the debug module and provides a way
* for debugfs input to be communicated with existing modules
*/
-struct dp_debug *dp_debug_get(struct device *dev, struct dp_panel *panel,
- struct dp_link *link,
- struct drm_connector *connector,
- struct dentry *root,
- bool is_edp);
+int dp_debug_init(struct device *dev, struct dp_panel *panel,
+ struct dp_link *link,
+ struct drm_connector *connector,
+ struct dentry *root,
+ bool is_edp);
#else
static inline
-struct dp_debug *dp_debug_get(struct device *dev, struct dp_panel *panel,
- struct dp_link *link,
- struct drm_connector *connector,
- struct dentry *root,
- bool is_edp)
+int dp_debug_init(struct device *dev, struct dp_panel *panel,
+ struct dp_link *link,
+ struct drm_connector *connector,
+ struct dentry *root,
+ bool is_edp)
{
- return ERR_PTR(-EINVAL);
+ return -EINVAL;
}
#endif /* defined(CONFIG_DEBUG_FS) */
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index ffbfde922589..672a7ba52eda 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -74,7 +74,6 @@ struct dp_event {
};
struct dp_display_private {
- char *name;
int irq;
unsigned int id;
@@ -82,18 +81,15 @@ struct dp_display_private {
/* state variables */
bool core_initialized;
bool phy_initialized;
- bool hpd_irq_on;
bool audio_supported;
struct drm_device *drm_dev;
- struct dentry *root;
struct dp_catalog *catalog;
struct drm_dp_aux *aux;
struct dp_link *link;
struct dp_panel *panel;
struct dp_ctrl *ctrl;
- struct dp_debug *debug;
struct dp_display_mode dp_mode;
struct msm_dp dp_display;
@@ -119,55 +115,49 @@ struct dp_display_private {
struct msm_dp_desc {
phys_addr_t io_start;
unsigned int id;
- unsigned int connector_type;
bool wide_bus_supported;
};
static const struct msm_dp_desc sc7180_dp_descs[] = {
- { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
+ { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0 },
{}
};
static const struct msm_dp_desc sc7280_dp_descs[] = {
- { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
- { .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_supported = true },
+ { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true },
+ { .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true },
{}
};
static const struct msm_dp_desc sc8180x_dp_descs[] = {
- { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
- { .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
- { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_eDP },
+ { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0 },
+ { .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1 },
+ { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2 },
{}
};
static const struct msm_dp_desc sc8280xp_dp_descs[] = {
- { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
- { .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
- { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
- { .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
- { .io_start = 0x22090000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
- { .io_start = 0x22098000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
- { .io_start = 0x2209a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
- { .io_start = 0x220a0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true },
+ { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true },
+ { .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true },
+ { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .wide_bus_supported = true },
+ { .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_3, .wide_bus_supported = true },
+ { .io_start = 0x22090000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true },
+ { .io_start = 0x22098000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true },
+ { .io_start = 0x2209a000, .id = MSM_DP_CONTROLLER_2, .wide_bus_supported = true },
+ { .io_start = 0x220a0000, .id = MSM_DP_CONTROLLER_3, .wide_bus_supported = true },
{}
};
-static const struct msm_dp_desc sc8280xp_edp_descs[] = {
- { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_supported = true },
- { .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_supported = true },
- { .io_start = 0x2209a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_supported = true },
- { .io_start = 0x220a0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_supported = true },
- {}
-};
-
-static const struct msm_dp_desc sm8350_dp_descs[] = {
- { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
+static const struct msm_dp_desc sm8650_dp_descs[] = {
+ { .io_start = 0x0af54000, .id = MSM_DP_CONTROLLER_0 },
{}
};
-static const struct msm_dp_desc sm8650_dp_descs[] = {
- { .io_start = 0x0af54000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort },
+static const struct msm_dp_desc x1e80100_dp_descs[] = {
+ { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .wide_bus_supported = true },
+ { .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .wide_bus_supported = true },
+ { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .wide_bus_supported = true },
+ { .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_3, .wide_bus_supported = true },
{}
};
@@ -178,10 +168,11 @@ static const struct of_device_id dp_dt_match[] = {
{ .compatible = "qcom,sc8180x-dp", .data = &sc8180x_dp_descs },
{ .compatible = "qcom,sc8180x-edp", .data = &sc8180x_dp_descs },
{ .compatible = "qcom,sc8280xp-dp", .data = &sc8280xp_dp_descs },
- { .compatible = "qcom,sc8280xp-edp", .data = &sc8280xp_edp_descs },
+ { .compatible = "qcom,sc8280xp-edp", .data = &sc8280xp_dp_descs },
{ .compatible = "qcom,sdm845-dp", .data = &sc7180_dp_descs },
- { .compatible = "qcom,sm8350-dp", .data = &sm8350_dp_descs },
+ { .compatible = "qcom,sm8350-dp", .data = &sc7180_dp_descs },
{ .compatible = "qcom,sm8650-dp", .data = &sm8650_dp_descs },
+ { .compatible = "qcom,x1e80100-dp", .data = &x1e80100_dp_descs },
{}
};
@@ -555,6 +546,8 @@ static int dp_hpd_plug_handle(struct dp_display_private *dp, u32 data)
int ret;
struct platform_device *pdev = dp->dp_display.pdev;
+ dp_aux_enable_xfers(dp->aux, true);
+
mutex_lock(&dp->event_mutex);
state = dp->hpd_state;
@@ -620,6 +613,8 @@ static int dp_hpd_unplug_handle(struct dp_display_private *dp, u32 data)
u32 state;
struct platform_device *pdev = dp->dp_display.pdev;
+ dp_aux_enable_xfers(dp->aux, false);
+
mutex_lock(&dp->event_mutex);
state = dp->hpd_state;
@@ -728,6 +723,14 @@ static int dp_init_sub_modules(struct dp_display_private *dp)
if (IS_ERR(phy))
return PTR_ERR(phy);
+ rc = phy_set_mode_ext(phy, PHY_MODE_DP,
+ dp->dp_display.is_edp ? PHY_SUBMODE_EDP : PHY_SUBMODE_DP);
+ if (rc) {
+ DRM_ERROR("failed to set phy submode, rc = %d\n", rc);
+ dp->catalog = NULL;
+ goto error;
+ }
+
dp->catalog = dp_catalog_get(dev);
if (IS_ERR(dp->catalog)) {
rc = PTR_ERR(dp->catalog);
@@ -803,7 +806,6 @@ static int dp_display_set_mode(struct msm_dp *dp_display,
drm_mode_copy(&dp->panel->dp_mode.drm_mode, &mode->drm_mode);
dp->panel->dp_mode.bpp = mode->bpp;
- dp->panel->dp_mode.capabilities = mode->capabilities;
dp->panel->dp_mode.out_fmt_is_yuv_420 = mode->out_fmt_is_yuv_420;
dp_panel_init_panel_info(dp->panel);
return 0;
@@ -1243,6 +1245,25 @@ static int dp_auxbus_done_probe(struct drm_dp_aux *aux)
return dp_display_probe_tail(aux->dev);
}
+static int dp_display_get_connector_type(struct platform_device *pdev,
+ const struct msm_dp_desc *desc)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct device_node *aux_bus = of_get_child_by_name(node, "aux-bus");
+ struct device_node *panel = of_get_child_by_name(aux_bus, "panel");
+ int connector_type;
+
+ if (panel)
+ connector_type = DRM_MODE_CONNECTOR_eDP;
+ else
+ connector_type = DRM_MODE_SUBCONNECTOR_DisplayPort;
+
+ of_node_put(panel);
+ of_node_put(aux_bus);
+
+ return connector_type;
+}
+
static int dp_display_probe(struct platform_device *pdev)
{
int rc = 0;
@@ -1263,9 +1284,8 @@ static int dp_display_probe(struct platform_device *pdev)
return -EINVAL;
dp->dp_display.pdev = pdev;
- dp->name = "drm_dp";
dp->id = desc->id;
- dp->dp_display.connector_type = desc->connector_type;
+ dp->dp_display.connector_type = dp_display_get_connector_type(pdev, desc);
dp->wide_bus_supported = desc->wide_bus_supported;
dp->dp_display.is_edp =
(dp->dp_display.connector_type == DRM_MODE_CONNECTOR_eDP);
@@ -1433,14 +1453,9 @@ void dp_display_debugfs_init(struct msm_dp *dp_display, struct dentry *root, boo
dp = container_of(dp_display, struct dp_display_private, dp_display);
dev = &dp->dp_display.pdev->dev;
- dp->debug = dp_debug_get(dev, dp->panel,
- dp->link, dp->dp_display.connector,
- root, is_edp);
- if (IS_ERR(dp->debug)) {
- rc = PTR_ERR(dp->debug);
+ rc = dp_debug_init(dev, dp->panel, dp->link, dp->dp_display.connector, root, is_edp);
+ if (rc)
DRM_ERROR("failed to initialize debug, rc = %d\n", rc);
- dp->debug = NULL;
- }
}
int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev,
diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h
index 234dada88687..ec7fa67e0569 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.h
+++ b/drivers/gpu/drm/msm/dp/dp_display.h
@@ -16,7 +16,6 @@ struct msm_dp {
struct drm_device *drm_dev;
struct platform_device *pdev;
struct device *codec_dev;
- struct drm_bridge *bridge;
struct drm_connector *connector;
struct drm_bridge *next_bridge;
bool link_ready;
@@ -28,8 +27,6 @@ struct msm_dp {
hdmi_codec_plugged_cb plugged_cb;
- bool wide_bus_en;
-
struct dp_audio *dp_audio;
bool psr_supported;
};
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
index a819a4ff76a9..1b9be5bd97f1 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.c
+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
@@ -347,8 +347,6 @@ int dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev,
}
}
- dp_display->bridge = bridge;
-
return 0;
}
diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c
index 49dfac1fd1ef..d8967615d84d 100644
--- a/drivers/gpu/drm/msm/dp/dp_link.c
+++ b/drivers/gpu/drm/msm/dp/dp_link.c
@@ -36,7 +36,6 @@ struct dp_link_request {
struct dp_link_private {
u32 prev_sink_count;
- struct device *dev;
struct drm_device *drm_dev;
struct drm_dp_aux *aux;
struct dp_link dp_link;
@@ -804,8 +803,6 @@ int dp_link_psm_config(struct dp_link *dp_link,
if (ret)
DRM_ERROR("Failed to %s low power mode\n", enable ?
"enter" : "exit");
- else
- dp_link->psm_enabled = enable;
mutex_unlock(&link->psm_mutex);
return ret;
@@ -1109,6 +1106,7 @@ int dp_link_get_colorimetry_config(struct dp_link *dp_link)
int dp_link_adjust_levels(struct dp_link *dp_link, u8 *link_status)
{
int i;
+ u8 max_p_level;
int v_max = 0, p_max = 0;
struct dp_link_private *link;
@@ -1140,30 +1138,29 @@ int dp_link_adjust_levels(struct dp_link *dp_link, u8 *link_status)
* Adjust the voltage swing and pre-emphasis level combination to within
* the allowable range.
*/
- if (dp_link->phy_params.v_level > DP_TRAIN_VOLTAGE_SWING_MAX) {
+ if (dp_link->phy_params.v_level > DP_TRAIN_LEVEL_MAX) {
drm_dbg_dp(link->drm_dev,
"Requested vSwingLevel=%d, change to %d\n",
dp_link->phy_params.v_level,
- DP_TRAIN_VOLTAGE_SWING_MAX);
- dp_link->phy_params.v_level = DP_TRAIN_VOLTAGE_SWING_MAX;
+ DP_TRAIN_LEVEL_MAX);
+ dp_link->phy_params.v_level = DP_TRAIN_LEVEL_MAX;
}
- if (dp_link->phy_params.p_level > DP_TRAIN_PRE_EMPHASIS_MAX) {
+ if (dp_link->phy_params.p_level > DP_TRAIN_LEVEL_MAX) {
drm_dbg_dp(link->drm_dev,
"Requested preEmphasisLevel=%d, change to %d\n",
dp_link->phy_params.p_level,
- DP_TRAIN_PRE_EMPHASIS_MAX);
- dp_link->phy_params.p_level = DP_TRAIN_PRE_EMPHASIS_MAX;
+ DP_TRAIN_LEVEL_MAX);
+ dp_link->phy_params.p_level = DP_TRAIN_LEVEL_MAX;
}
- if ((dp_link->phy_params.p_level > DP_TRAIN_PRE_EMPHASIS_LVL_1)
- && (dp_link->phy_params.v_level ==
- DP_TRAIN_VOLTAGE_SWING_LVL_2)) {
+ max_p_level = DP_TRAIN_LEVEL_MAX - dp_link->phy_params.v_level;
+ if (dp_link->phy_params.p_level > max_p_level) {
drm_dbg_dp(link->drm_dev,
"Requested preEmphasisLevel=%d, change to %d\n",
dp_link->phy_params.p_level,
- DP_TRAIN_PRE_EMPHASIS_LVL_1);
- dp_link->phy_params.p_level = DP_TRAIN_PRE_EMPHASIS_LVL_1;
+ max_p_level);
+ dp_link->phy_params.p_level = max_p_level;
}
drm_dbg_dp(link->drm_dev, "adjusted: v_level=%d, p_level=%d\n",
@@ -1226,7 +1223,6 @@ struct dp_link *dp_link_get(struct device *dev, struct drm_dp_aux *aux)
if (!link)
return ERR_PTR(-ENOMEM);
- link->dev = dev;
link->aux = aux;
mutex_init(&link->psm_mutex);
diff --git a/drivers/gpu/drm/msm/dp/dp_link.h b/drivers/gpu/drm/msm/dp/dp_link.h
index 83da170bc56b..5846337bb56f 100644
--- a/drivers/gpu/drm/msm/dp/dp_link.h
+++ b/drivers/gpu/drm/msm/dp/dp_link.h
@@ -19,19 +19,7 @@ struct dp_link_info {
unsigned long capabilities;
};
-enum dp_link_voltage_level {
- DP_TRAIN_VOLTAGE_SWING_LVL_0 = 0,
- DP_TRAIN_VOLTAGE_SWING_LVL_1 = 1,
- DP_TRAIN_VOLTAGE_SWING_LVL_2 = 2,
- DP_TRAIN_VOLTAGE_SWING_MAX = DP_TRAIN_VOLTAGE_SWING_LVL_2,
-};
-
-enum dp_link_preemaphasis_level {
- DP_TRAIN_PRE_EMPHASIS_LVL_0 = 0,
- DP_TRAIN_PRE_EMPHASIS_LVL_1 = 1,
- DP_TRAIN_PRE_EMPHASIS_LVL_2 = 2,
- DP_TRAIN_PRE_EMPHASIS_MAX = DP_TRAIN_PRE_EMPHASIS_LVL_2,
-};
+#define DP_TRAIN_LEVEL_MAX 3
struct dp_link_test_video {
u32 test_video_pattern;
@@ -74,7 +62,6 @@ struct dp_link_phy_params {
struct dp_link {
u32 sink_request;
u32 test_response;
- bool psm_enabled;
u8 sink_count;
struct dp_link_test_video test_video;
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c
index 8e7069453952..07db8f37cd06 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.c
+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
@@ -353,6 +353,10 @@ int dp_panel_timing_cfg(struct dp_panel *dp_panel)
struct dp_catalog *catalog;
struct dp_panel_private *panel;
struct drm_display_mode *drm_mode;
+ u32 width_blanking;
+ u32 sync_start;
+ u32 dp_active;
+ u32 total;
panel = container_of(dp_panel, struct dp_panel_private, dp_panel);
catalog = panel->catalog;
@@ -376,13 +380,13 @@ int dp_panel_timing_cfg(struct dp_panel *dp_panel)
data <<= 16;
data |= total_hor;
- catalog->total = data;
+ total = data;
data = (drm_mode->vtotal - drm_mode->vsync_start);
data <<= 16;
data |= (drm_mode->htotal - drm_mode->hsync_start);
- catalog->sync_start = data;
+ sync_start = data;
data = drm_mode->vsync_end - drm_mode->vsync_start;
data <<= 16;
@@ -390,15 +394,15 @@ int dp_panel_timing_cfg(struct dp_panel *dp_panel)
data |= drm_mode->hsync_end - drm_mode->hsync_start;
data |= (panel->dp_panel.dp_mode.h_active_low << 15);
- catalog->width_blanking = data;
+ width_blanking = data;
data = drm_mode->vdisplay;
data <<= 16;
data |= drm_mode->hdisplay;
- catalog->dp_active = data;
+ dp_active = data;
- dp_catalog_panel_timing_cfg(catalog);
+ dp_catalog_panel_timing_cfg(catalog, total, sync_start, width_blanking, dp_active);
if (dp_panel->dp_mode.out_fmt_is_yuv_420)
dp_panel_setup_vsc_sdp_yuv_420(dp_panel);
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h
index e843f5062d1f..4ea42fa936ae 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.h
+++ b/drivers/gpu/drm/msm/dp/dp_panel.h
@@ -15,7 +15,6 @@ struct edid;
struct dp_display_mode {
struct drm_display_mode drm_mode;
- u32 capabilities;
u32 bpp;
u32 h_active_low;
u32 v_active_low;
@@ -40,7 +39,6 @@ struct dp_panel {
u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
struct dp_link_info link_info;
- struct drm_dp_desc desc;
struct edid *edid;
struct drm_connector *connector;
struct dp_display_mode dp_mode;
@@ -48,7 +46,6 @@ struct dp_panel {
bool video_test;
bool vsc_sdp_supported;
- u32 vic;
u32 max_dp_lanes;
u32 max_dp_link_rate;
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index 37c4c07005fe..efd7c23b662f 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -120,6 +120,22 @@ static int dsi_bind(struct device *dev, struct device *master, void *data)
struct msm_drm_private *priv = dev_get_drvdata(master);
struct msm_dsi *msm_dsi = dev_get_drvdata(dev);
+ /*
+ * Next bridge doesn't exist for the secondary DSI host in a bonded
+ * pair.
+ */
+ if (!msm_dsi_is_bonded_dsi(msm_dsi) ||
+ msm_dsi_is_master_dsi(msm_dsi)) {
+ struct drm_bridge *ext_bridge;
+
+ ext_bridge = devm_drm_of_get_bridge(&msm_dsi->pdev->dev,
+ msm_dsi->pdev->dev.of_node, 1, 0);
+ if (IS_ERR(ext_bridge))
+ return PTR_ERR(ext_bridge);
+
+ msm_dsi->next_bridge = ext_bridge;
+ }
+
priv->dsi[msm_dsi->id] = msm_dsi;
return 0;
@@ -216,7 +232,6 @@ void __exit msm_dsi_unregister(void)
int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
struct drm_encoder *encoder)
{
- struct drm_bridge *bridge;
int ret;
msm_dsi->dev = dev;
@@ -236,14 +251,7 @@ int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
return 0;
}
- bridge = msm_dsi_manager_bridge_init(msm_dsi, encoder);
- if (IS_ERR(bridge)) {
- ret = PTR_ERR(bridge);
- DRM_DEV_ERROR(dev->dev, "failed to create dsi bridge: %d\n", ret);
- return ret;
- }
-
- ret = msm_dsi_manager_ext_bridge_init(msm_dsi->id, bridge);
+ ret = msm_dsi_manager_connector_init(msm_dsi, encoder);
if (ret) {
DRM_DEV_ERROR(dev->dev,
"failed to create dsi connector: %d\n", ret);
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 2ad9a842c678..afc290408ba4 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -38,6 +38,8 @@ struct msm_dsi {
struct mipi_dsi_host *host;
struct msm_dsi_phy *phy;
+ struct drm_bridge *next_bridge;
+
struct device *phy_dev;
bool phy_enabled;
@@ -45,9 +47,8 @@ struct msm_dsi {
};
/* dsi manager */
-struct drm_bridge *msm_dsi_manager_bridge_init(struct msm_dsi *msm_dsi,
- struct drm_encoder *encoder);
-int msm_dsi_manager_ext_bridge_init(u8 id, struct drm_bridge *int_bridge);
+int msm_dsi_manager_connector_init(struct msm_dsi *msm_dsi,
+ struct drm_encoder *encoder);
int msm_dsi_manager_cmd_xfer(int id, const struct mipi_dsi_msg *msg);
bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 dma_base, u32 len);
int msm_dsi_manager_register(struct msm_dsi *msm_dsi);
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
deleted file mode 100644
index 2a7d980e12c3..000000000000
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ /dev/null
@@ -1,790 +0,0 @@
-#ifndef DSI_XML
-#define DSI_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
-
-Copyright (C) 2013-2022 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-enum dsi_traffic_mode {
- NON_BURST_SYNCH_PULSE = 0,
- NON_BURST_SYNCH_EVENT = 1,
- BURST_MODE = 2,
-};
-
-enum dsi_vid_dst_format {
- VID_DST_FORMAT_RGB565 = 0,
- VID_DST_FORMAT_RGB666 = 1,
- VID_DST_FORMAT_RGB666_LOOSE = 2,
- VID_DST_FORMAT_RGB888 = 3,
-};
-
-enum dsi_rgb_swap {
- SWAP_RGB = 0,
- SWAP_RBG = 1,
- SWAP_BGR = 2,
- SWAP_BRG = 3,
- SWAP_GRB = 4,
- SWAP_GBR = 5,
-};
-
-enum dsi_cmd_trigger {
- TRIGGER_NONE = 0,
- TRIGGER_SEOF = 1,
- TRIGGER_TE = 2,
- TRIGGER_SW = 4,
- TRIGGER_SW_SEOF = 5,
- TRIGGER_SW_TE = 6,
-};
-
-enum dsi_cmd_dst_format {
- CMD_DST_FORMAT_RGB111 = 0,
- CMD_DST_FORMAT_RGB332 = 3,
- CMD_DST_FORMAT_RGB444 = 4,
- CMD_DST_FORMAT_RGB565 = 6,
- CMD_DST_FORMAT_RGB666 = 7,
- CMD_DST_FORMAT_RGB888 = 8,
-};
-
-enum dsi_lane_swap {
- LANE_SWAP_0123 = 0,
- LANE_SWAP_3012 = 1,
- LANE_SWAP_2301 = 2,
- LANE_SWAP_1230 = 3,
- LANE_SWAP_0321 = 4,
- LANE_SWAP_1032 = 5,
- LANE_SWAP_2103 = 6,
- LANE_SWAP_3210 = 7,
-};
-
-enum video_config_bpp {
- VIDEO_CONFIG_18BPP = 0,
- VIDEO_CONFIG_24BPP = 1,
-};
-
-enum video_pattern_sel {
- VID_PRBS = 0,
- VID_INCREMENTAL = 1,
- VID_FIXED = 2,
- VID_MDSS_GENERAL_PATTERN = 3,
-};
-
-enum cmd_mdp_stream0_pattern_sel {
- CMD_MDP_PRBS = 0,
- CMD_MDP_INCREMENTAL = 1,
- CMD_MDP_FIXED = 2,
- CMD_MDP_MDSS_GENERAL_PATTERN = 3,
-};
-
-enum cmd_dma_pattern_sel {
- CMD_DMA_PRBS = 0,
- CMD_DMA_INCREMENTAL = 1,
- CMD_DMA_FIXED = 2,
- CMD_DMA_CUSTOM_PATTERN_DMA_FIFO = 3,
-};
-
-#define DSI_IRQ_CMD_DMA_DONE 0x00000001
-#define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
-#define DSI_IRQ_CMD_MDP_DONE 0x00000100
-#define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
-#define DSI_IRQ_VIDEO_DONE 0x00010000
-#define DSI_IRQ_MASK_VIDEO_DONE 0x00020000
-#define DSI_IRQ_BTA_DONE 0x00100000
-#define DSI_IRQ_MASK_BTA_DONE 0x00200000
-#define DSI_IRQ_ERROR 0x01000000
-#define DSI_IRQ_MASK_ERROR 0x02000000
-#define REG_DSI_6G_HW_VERSION 0x00000000
-#define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000
-#define DSI_6G_HW_VERSION_MAJOR__SHIFT 28
-static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val)
-{
- return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK;
-}
-#define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000
-#define DSI_6G_HW_VERSION_MINOR__SHIFT 16
-static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val)
-{
- return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK;
-}
-#define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff
-#define DSI_6G_HW_VERSION_STEP__SHIFT 0
-static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val)
-{
- return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK;
-}
-
-#define REG_DSI_CTRL 0x00000000
-#define DSI_CTRL_ENABLE 0x00000001
-#define DSI_CTRL_VID_MODE_EN 0x00000002
-#define DSI_CTRL_CMD_MODE_EN 0x00000004
-#define DSI_CTRL_LANE0 0x00000010
-#define DSI_CTRL_LANE1 0x00000020
-#define DSI_CTRL_LANE2 0x00000040
-#define DSI_CTRL_LANE3 0x00000080
-#define DSI_CTRL_CLK_EN 0x00000100
-#define DSI_CTRL_ECC_CHECK 0x00100000
-#define DSI_CTRL_CRC_CHECK 0x01000000
-
-#define REG_DSI_STATUS0 0x00000004
-#define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001
-#define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002
-#define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004
-#define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008
-#define DSI_STATUS0_DSI_BUSY 0x00000010
-#define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000
-
-#define REG_DSI_FIFO_STATUS 0x00000008
-#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW 0x00000001
-#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW 0x00000008
-#define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080
-#define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH 0x00000100
-#define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH 0x00000200
-#define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW 0x00000400
-#define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY 0x00001000
-#define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL 0x00002000
-#define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW 0x00004000
-#define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY 0x00010000
-#define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL 0x00020000
-#define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW 0x00040000
-#define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW 0x00080000
-#define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY 0x00100000
-#define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL 0x00200000
-#define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW 0x00400000
-#define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW 0x00800000
-#define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY 0x01000000
-#define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL 0x02000000
-#define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW 0x04000000
-#define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW 0x08000000
-#define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY 0x10000000
-#define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL 0x20000000
-#define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW 0x40000000
-#define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW 0x80000000
-
-#define REG_DSI_VID_CFG0 0x0000000c
-#define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003
-#define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0
-static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val)
-{
- return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK;
-}
-#define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030
-#define DSI_VID_CFG0_DST_FORMAT__SHIFT 4
-static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val)
-{
- return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK;
-}
-#define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300
-#define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8
-static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val)
-{
- return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK;
-}
-#define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000
-#define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000
-#define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000
-#define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000
-#define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000
-#define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000
-
-#define REG_DSI_VID_CFG1 0x0000001c
-#define DSI_VID_CFG1_R_SEL 0x00000001
-#define DSI_VID_CFG1_G_SEL 0x00000010
-#define DSI_VID_CFG1_B_SEL 0x00000100
-#define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000
-#define DSI_VID_CFG1_RGB_SWAP__SHIFT 12
-static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val)
-{
- return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK;
-}
-
-#define REG_DSI_ACTIVE_H 0x00000020
-#define DSI_ACTIVE_H_START__MASK 0x00000fff
-#define DSI_ACTIVE_H_START__SHIFT 0
-static inline uint32_t DSI_ACTIVE_H_START(uint32_t val)
-{
- return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK;
-}
-#define DSI_ACTIVE_H_END__MASK 0x0fff0000
-#define DSI_ACTIVE_H_END__SHIFT 16
-static inline uint32_t DSI_ACTIVE_H_END(uint32_t val)
-{
- return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK;
-}
-
-#define REG_DSI_ACTIVE_V 0x00000024
-#define DSI_ACTIVE_V_START__MASK 0x00000fff
-#define DSI_ACTIVE_V_START__SHIFT 0
-static inline uint32_t DSI_ACTIVE_V_START(uint32_t val)
-{
- return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK;
-}
-#define DSI_ACTIVE_V_END__MASK 0x0fff0000
-#define DSI_ACTIVE_V_END__SHIFT 16
-static inline uint32_t DSI_ACTIVE_V_END(uint32_t val)
-{
- return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK;
-}
-
-#define REG_DSI_TOTAL 0x00000028
-#define DSI_TOTAL_H_TOTAL__MASK 0x00000fff
-#define DSI_TOTAL_H_TOTAL__SHIFT 0
-static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val)
-{
- return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK;
-}
-#define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000
-#define DSI_TOTAL_V_TOTAL__SHIFT 16
-static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val)
-{
- return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK;
-}
-
-#define REG_DSI_ACTIVE_HSYNC 0x0000002c
-#define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff
-#define DSI_ACTIVE_HSYNC_START__SHIFT 0
-static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val)
-{
- return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK;
-}
-#define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000
-#define DSI_ACTIVE_HSYNC_END__SHIFT 16
-static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val)
-{
- return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK;
-}
-
-#define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030
-#define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff
-#define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0
-static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val)
-{
- return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK;
-}
-#define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000
-#define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT 16
-static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val)
-{
- return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK;
-}
-
-#define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034
-#define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff
-#define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0
-static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val)
-{
- return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK;
-}
-#define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000
-#define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT 16
-static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val)
-{
- return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK;
-}
-
-#define REG_DSI_CMD_DMA_CTRL 0x00000038
-#define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000
-#define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000
-#define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000
-
-#define REG_DSI_CMD_CFG0 0x0000003c
-#define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f
-#define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0
-static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val)
-{
- return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK;
-}
-#define DSI_CMD_CFG0_R_SEL 0x00000010
-#define DSI_CMD_CFG0_G_SEL 0x00000100
-#define DSI_CMD_CFG0_B_SEL 0x00001000
-#define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000
-#define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT 20
-static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val)
-{
- return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK;
-}
-#define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000
-#define DSI_CMD_CFG0_RGB_SWAP__SHIFT 16
-static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val)
-{
- return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK;
-}
-
-#define REG_DSI_CMD_CFG1 0x00000040
-#define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff
-#define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0
-static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val)
-{
- return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK;
-}
-#define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00
-#define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT 8
-static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val)
-{
- return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK;
-}
-#define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000
-
-#define REG_DSI_DMA_BASE 0x00000044
-
-#define REG_DSI_DMA_LEN 0x00000048
-
-#define REG_DSI_CMD_MDP_STREAM0_CTRL 0x00000054
-#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK 0x0000003f
-#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT 0
-static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val)
-{
- return ((val) << DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK;
-}
-#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
-#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT 8
-static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val)
-{
- return ((val) << DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK;
-}
-#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK 0xffff0000
-#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT 16
-static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val)
-{
- return ((val) << DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK;
-}
-
-#define REG_DSI_CMD_MDP_STREAM0_TOTAL 0x00000058
-#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK 0x00000fff
-#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT 0
-static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val)
-{
- return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK;
-}
-#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK 0x0fff0000
-#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT 16
-static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val)
-{
- return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK;
-}
-
-#define REG_DSI_CMD_MDP_STREAM1_CTRL 0x0000005c
-#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK 0x0000003f
-#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT 0
-static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val)
-{
- return ((val) << DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK;
-}
-#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
-#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT 8
-static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val)
-{
- return ((val) << DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK;
-}
-#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK 0xffff0000
-#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT 16
-static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val)
-{
- return ((val) << DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK;
-}
-
-#define REG_DSI_CMD_MDP_STREAM1_TOTAL 0x00000060
-#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK 0x0000ffff
-#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT 0
-static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val)
-{
- return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK;
-}
-#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK 0xffff0000
-#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT 16
-static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val)
-{
- return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK;
-}
-
-#define REG_DSI_ACK_ERR_STATUS 0x00000064
-
-static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; }
-
-static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; }
-
-#define REG_DSI_TRIG_CTRL 0x00000080
-#define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007
-#define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0
-static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val)
-{
- return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK;
-}
-#define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070
-#define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4
-static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val)
-{
- return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK;
-}
-#define DSI_TRIG_CTRL_STREAM__MASK 0x00000300
-#define DSI_TRIG_CTRL_STREAM__SHIFT 8
-static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val)
-{
- return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK;
-}
-#define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000
-#define DSI_TRIG_CTRL_TE 0x80000000
-
-#define REG_DSI_TRIG_DMA 0x0000008c
-
-#define REG_DSI_DLN0_PHY_ERR 0x000000b0
-#define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001
-#define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010
-#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100
-#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000
-#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000
-
-#define REG_DSI_LP_TIMER_CTRL 0x000000b4
-#define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK 0x0000ffff
-#define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT 0
-static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val)
-{
- return ((val) << DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT) & DSI_LP_TIMER_CTRL_LP_RX_TO__MASK;
-}
-#define DSI_LP_TIMER_CTRL_BTA_TO__MASK 0xffff0000
-#define DSI_LP_TIMER_CTRL_BTA_TO__SHIFT 16
-static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val)
-{
- return ((val) << DSI_LP_TIMER_CTRL_BTA_TO__SHIFT) & DSI_LP_TIMER_CTRL_BTA_TO__MASK;
-}
-
-#define REG_DSI_HS_TIMER_CTRL 0x000000b8
-#define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK 0x0000ffff
-#define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT 0
-static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val)
-{
- return ((val) << DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT) & DSI_HS_TIMER_CTRL_HS_TX_TO__MASK;
-}
-#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK 0x000f0000
-#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT 16
-static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val)
-{
- return ((val) << DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT) & DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK;
-}
-#define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN 0x10000000
-
-#define REG_DSI_TIMEOUT_STATUS 0x000000bc
-
-#define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0
-#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f
-#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0
-static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val)
-{
- return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK;
-}
-#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00
-#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8
-static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
-{
- return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK;
-}
-
-#define REG_DSI_EOT_PACKET_CTRL 0x000000c8
-#define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001
-#define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010
-
-#define REG_DSI_LANE_STATUS 0x000000a4
-#define DSI_LANE_STATUS_DLN0_STOPSTATE 0x00000001
-#define DSI_LANE_STATUS_DLN1_STOPSTATE 0x00000002
-#define DSI_LANE_STATUS_DLN2_STOPSTATE 0x00000004
-#define DSI_LANE_STATUS_DLN3_STOPSTATE 0x00000008
-#define DSI_LANE_STATUS_CLKLN_STOPSTATE 0x00000010
-#define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT 0x00000100
-#define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT 0x00000200
-#define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT 0x00000400
-#define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT 0x00000800
-#define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT 0x00001000
-#define DSI_LANE_STATUS_DLN0_DIRECTION 0x00010000
-
-#define REG_DSI_LANE_CTRL 0x000000a8
-#define DSI_LANE_CTRL_HS_REQ_SEL_PHY 0x01000000
-#define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000
-
-#define REG_DSI_LANE_SWAP_CTRL 0x000000ac
-#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007
-#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0
-static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
-{
- return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK;
-}
-
-#define REG_DSI_ERR_INT_MASK0 0x00000108
-
-#define REG_DSI_INTR_CTRL 0x0000010c
-
-#define REG_DSI_RESET 0x00000114
-
-#define REG_DSI_CLK_CTRL 0x00000118
-#define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001
-#define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002
-#define DSI_CLK_CTRL_PCLK_ON 0x00000004
-#define DSI_CLK_CTRL_DSICLK_ON 0x00000008
-#define DSI_CLK_CTRL_BYTECLK_ON 0x00000010
-#define DSI_CLK_CTRL_ESCCLK_ON 0x00000020
-#define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200
-
-#define REG_DSI_CLK_STATUS 0x0000011c
-#define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE 0x00000001
-#define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE 0x00000002
-#define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE 0x00000004
-#define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE 0x00000008
-#define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE 0x00000010
-#define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE 0x00000020
-#define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE 0x00000040
-#define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE 0x00000080
-#define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE 0x00000100
-#define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE 0x00000200
-#define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE 0x00000400
-#define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE 0x00001000
-#define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE 0x00002000
-#define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE 0x00004000
-#define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT 0x00008000
-#define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000
-
-#define REG_DSI_PHY_RESET 0x00000128
-#define DSI_PHY_RESET_RESET 0x00000001
-
-#define REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL 0x00000160
-
-#define REG_DSI_TPG_MAIN_CONTROL 0x00000198
-#define DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN 0x00000100
-
-#define REG_DSI_TPG_VIDEO_CONFIG 0x000001a0
-#define DSI_TPG_VIDEO_CONFIG_BPP__MASK 0x00000003
-#define DSI_TPG_VIDEO_CONFIG_BPP__SHIFT 0
-static inline uint32_t DSI_TPG_VIDEO_CONFIG_BPP(enum video_config_bpp val)
-{
- return ((val) << DSI_TPG_VIDEO_CONFIG_BPP__SHIFT) & DSI_TPG_VIDEO_CONFIG_BPP__MASK;
-}
-#define DSI_TPG_VIDEO_CONFIG_RGB 0x00000004
-
-#define REG_DSI_TEST_PATTERN_GEN_CTRL 0x00000158
-#define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__MASK 0x00030000
-#define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__SHIFT 16
-static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL(enum cmd_dma_pattern_sel val)
-{
- return ((val) << DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_PATTERN_SEL__MASK;
-}
-#define DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__MASK 0x00000300
-#define DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__SHIFT 8
-static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(enum cmd_mdp_stream0_pattern_sel val)
-{
- return ((val) << DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL__MASK;
-}
-#define DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__MASK 0x00000030
-#define DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__SHIFT 4
-static inline uint32_t DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(enum video_pattern_sel val)
-{
- return ((val) << DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__SHIFT) & DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL__MASK;
-}
-#define DSI_TEST_PATTERN_GEN_CTRL_TPG_DMA_FIFO_MODE 0x00000004
-#define DSI_TEST_PATTERN_GEN_CTRL_CMD_DMA_TPG_EN 0x00000002
-#define DSI_TEST_PATTERN_GEN_CTRL_EN 0x00000001
-
-#define REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0 0x00000168
-
-#define REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER 0x00000180
-#define DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER 0x00000001
-
-#define REG_DSI_TPG_MAIN_CONTROL2 0x0000019c
-#define DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN 0x00000080
-#define DSI_TPG_MAIN_CONTROL2_CMD_MDP1_CHECKERED_RECTANGLE_PATTERN 0x00010000
-#define DSI_TPG_MAIN_CONTROL2_CMD_MDP2_CHECKERED_RECTANGLE_PATTERN 0x02000000
-
-#define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c
-#define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001
-
-#define REG_DSI_CMD_MODE_MDP_CTRL2 0x000001b4
-#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK 0x0000000f
-#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT 0
-static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val)
-{
- return ((val) << DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK;
-}
-#define DSI_CMD_MODE_MDP_CTRL2_R_SEL 0x00000010
-#define DSI_CMD_MODE_MDP_CTRL2_G_SEL 0x00000020
-#define DSI_CMD_MODE_MDP_CTRL2_B_SEL 0x00000040
-#define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP 0x00000080
-#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK 0x00000700
-#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT 8
-static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val)
-{
- return ((val) << DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK;
-}
-#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK 0x00007000
-#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT 12
-static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val)
-{
- return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK;
-}
-#define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000
-#define DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN 0x00100000
-
-#define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8
-#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f
-#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT 0
-static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val)
-{
- return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK;
-}
-#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
-#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT 8
-static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val)
-{
- return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK;
-}
-#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK 0xffff0000
-#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT 16
-static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val)
-{
- return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK;
-}
-
-#define REG_DSI_RDBK_DATA_CTRL 0x000001d0
-#define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000
-#define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16
-static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val)
-{
- return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK;
-}
-#define DSI_RDBK_DATA_CTRL_CLR 0x00000001
-
-#define REG_DSI_VERSION 0x000001f0
-#define DSI_VERSION_MAJOR__MASK 0xff000000
-#define DSI_VERSION_MAJOR__SHIFT 24
-static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
-{
- return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK;
-}
-
-#define REG_DSI_CPHY_MODE_CTRL 0x000002d4
-
-#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
-#define DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__MASK 0xffff0000
-#define DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__SHIFT 16
-static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(uint32_t val)
-{
- return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_WC__MASK;
-}
-#define DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__MASK 0x00003f00
-#define DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__SHIFT 8
-static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(uint32_t val)
-{
- return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE__MASK;
-}
-#define DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__MASK 0x000000c0
-#define DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__SHIFT 6
-static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(uint32_t val)
-{
- return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE__MASK;
-}
-#define DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__MASK 0x00000030
-#define DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__SHIFT 4
-static inline uint32_t DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(uint32_t val)
-{
- return ((val) << DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__SHIFT) & DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM__MASK;
-}
-#define DSI_VIDEO_COMPRESSION_MODE_CTRL_EN 0x00000001
-
-#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__MASK 0x3f000000
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__SHIFT 24
-static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE(uint32_t val)
-{
- return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_DATATYPE__MASK;
-}
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__MASK 0x00c00000
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__SHIFT 22
-static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE(uint32_t val)
-{
- return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_PKT_PER_LINE__MASK;
-}
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__MASK 0x00300000
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__SHIFT 20
-static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM(uint32_t val)
-{
- return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EOL_BYTE_NUM__MASK;
-}
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM1_EN 0x00010000
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__MASK 0x00003f00
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__SHIFT 8
-static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(uint32_t val)
-{
- return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE__MASK;
-}
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__MASK 0x000000c0
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__SHIFT 6
-static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE(uint32_t val)
-{
- return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_PKT_PER_LINE__MASK;
-}
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__MASK 0x00000030
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__SHIFT 4
-static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM(uint32_t val)
-{
- return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EOL_BYTE_NUM__MASK;
-}
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_EN 0x00000001
-
-#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__MASK 0xffff0000
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__SHIFT 16
-static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH(uint32_t val)
-{
- return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM1_SLICE_WIDTH__MASK;
-}
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK 0x0000ffff
-#define DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__SHIFT 0
-static inline uint32_t DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(uint32_t val)
-{
- return ((val) << DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__SHIFT) & DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK;
-}
-
-
-#endif /* DSI_XML */
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 9d86a6aca6f2..a50f4dda5941 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -55,7 +55,7 @@ static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
* scratch register which we never touch)
*/
- ver = msm_readl(base + REG_DSI_VERSION);
+ ver = readl(base + REG_DSI_VERSION);
if (ver) {
/* older dsi host, there is no register shift */
ver = FIELD(ver, DSI_VERSION_MAJOR);
@@ -73,12 +73,12 @@ static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
* registers are shifted down, read DSI_VERSION again with
* the shifted offset
*/
- ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
+ ver = readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
ver = FIELD(ver, DSI_VERSION_MAJOR);
if (ver == MSM_DSI_VER_MAJOR_6G) {
/* 6G version */
*major = ver;
- *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
+ *minor = readl(base + REG_DSI_6G_HW_VERSION);
return 0;
} else {
return -EINVAL;
@@ -186,11 +186,11 @@ struct msm_dsi_host {
static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
{
- return msm_readl(msm_host->ctrl_base + reg);
+ return readl(msm_host->ctrl_base + reg);
}
static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
{
- msm_writel(data, msm_host->ctrl_base + reg);
+ writel(data, msm_host->ctrl_base + reg);
}
static const struct msm_dsi_cfg_handler *dsi_get_config(
@@ -356,8 +356,8 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
{
int ret;
- DBG("Set clk rates: pclk=%d, byteclk=%lu",
- msm_host->mode->clock, msm_host->byte_clk_rate);
+ DBG("Set clk rates: pclk=%lu, byteclk=%lu",
+ msm_host->pixel_clk_rate, msm_host->byte_clk_rate);
ret = dev_pm_opp_set_rate(&msm_host->pdev->dev,
msm_host->byte_clk_rate);
@@ -430,9 +430,9 @@ int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host)
{
int ret;
- DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu",
- msm_host->mode->clock, msm_host->byte_clk_rate,
- msm_host->esc_clk_rate, msm_host->src_clk_rate);
+ DBG("Set clk rates: pclk=%lu, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu",
+ msm_host->pixel_clk_rate, msm_host->byte_clk_rate,
+ msm_host->esc_clk_rate, msm_host->src_clk_rate);
ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
if (ret) {
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index af2a287cb3bd..5b3f3068fd92 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -423,7 +423,18 @@ static enum drm_mode_status dsi_mgr_bridge_mode_valid(struct drm_bridge *bridge,
return msm_dsi_host_check_dsc(host, mode);
}
+static int dsi_mgr_bridge_attach(struct drm_bridge *bridge,
+ enum drm_bridge_attach_flags flags)
+{
+ int id = dsi_mgr_bridge_get_id(bridge);
+ struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
+
+ return drm_bridge_attach(bridge->encoder, msm_dsi->next_bridge,
+ bridge, flags);
+}
+
static const struct drm_bridge_funcs dsi_mgr_bridge_funcs = {
+ .attach = dsi_mgr_bridge_attach,
.pre_enable = dsi_mgr_bridge_pre_enable,
.post_disable = dsi_mgr_bridge_post_disable,
.mode_set = dsi_mgr_bridge_mode_set,
@@ -431,17 +442,19 @@ static const struct drm_bridge_funcs dsi_mgr_bridge_funcs = {
};
/* initialize bridge */
-struct drm_bridge *msm_dsi_manager_bridge_init(struct msm_dsi *msm_dsi,
- struct drm_encoder *encoder)
+int msm_dsi_manager_connector_init(struct msm_dsi *msm_dsi,
+ struct drm_encoder *encoder)
{
+ struct drm_device *dev = msm_dsi->dev;
struct drm_bridge *bridge;
struct dsi_bridge *dsi_bridge;
+ struct drm_connector *connector;
int ret;
dsi_bridge = devm_kzalloc(msm_dsi->dev->dev,
sizeof(*dsi_bridge), GFP_KERNEL);
if (!dsi_bridge)
- return ERR_PTR(-ENOMEM);
+ return -ENOMEM;
dsi_bridge->id = msm_dsi->id;
@@ -450,60 +463,22 @@ struct drm_bridge *msm_dsi_manager_bridge_init(struct msm_dsi *msm_dsi,
ret = devm_drm_bridge_add(msm_dsi->dev->dev, bridge);
if (ret)
- return ERR_PTR(ret);
+ return ret;
- ret = drm_bridge_attach(encoder, bridge, NULL, 0);
+ ret = drm_bridge_attach(encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
if (ret)
- return ERR_PTR(ret);
-
- return bridge;
-}
-
-int msm_dsi_manager_ext_bridge_init(u8 id, struct drm_bridge *int_bridge)
-{
- struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
- struct drm_device *dev = msm_dsi->dev;
- struct drm_encoder *encoder;
- struct drm_bridge *ext_bridge;
- int ret;
+ return ret;
- ext_bridge = devm_drm_of_get_bridge(&msm_dsi->pdev->dev,
- msm_dsi->pdev->dev.of_node, 1, 0);
- if (IS_ERR(ext_bridge))
- return PTR_ERR(ext_bridge);
-
- encoder = int_bridge->encoder;
-
- /*
- * Try first to create the bridge without it creating its own
- * connector.. currently some bridges support this, and others
- * do not (and some support both modes)
- */
- ret = drm_bridge_attach(encoder, ext_bridge, int_bridge,
- DRM_BRIDGE_ATTACH_NO_CONNECTOR);
- if (ret == -EINVAL) {
- /*
- * link the internal dsi bridge to the external bridge,
- * connector is created by the next bridge.
- */
- ret = drm_bridge_attach(encoder, ext_bridge, int_bridge, 0);
- if (ret < 0)
- return ret;
- } else {
- struct drm_connector *connector;
-
- /* We are in charge of the connector, create one now. */
- connector = drm_bridge_connector_init(dev, encoder);
- if (IS_ERR(connector)) {
- DRM_ERROR("Unable to create bridge connector\n");
- return PTR_ERR(connector);
- }
-
- ret = drm_connector_attach_encoder(connector, encoder);
- if (ret < 0)
- return ret;
+ connector = drm_bridge_connector_init(dev, encoder);
+ if (IS_ERR(connector)) {
+ DRM_ERROR("Unable to create bridge connector\n");
+ return PTR_ERR(connector);
}
+ ret = drm_connector_attach_encoder(connector, encoder);
+ if (ret < 0)
+ return ret;
+
return 0;
}
diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h
deleted file mode 100644
index a2ae8777e59e..000000000000
--- a/drivers/gpu/drm/msm/dsi/dsi_phy_10nm.xml.h
+++ /dev/null
@@ -1,227 +0,0 @@
-#ifndef DSI_PHY_10NM_XML
-#define DSI_PHY_10NM_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
-
-Copyright (C) 2013-2022 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-#define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000
-
-#define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004
-
-#define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008
-
-#define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c
-
-#define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010
-
-#define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014
-
-#define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018
-
-#define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c
-
-#define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020
-
-#define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024
-
-#define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028
-
-#define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c
-
-#define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030
-
-#define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034
-
-#define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038
-
-#define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098
-
-#define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c
-
-#define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0
-
-#define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4
-
-#define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8
-
-#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac
-
-#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0
-
-#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4
-
-#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8
-
-#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc
-
-#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0
-
-#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4
-
-#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8
-
-#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc
-
-#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0
-
-#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4
-
-#define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8
-
-#define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec
-
-#define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4
-
-#define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8
-
-static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
-
-static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; }
-
-static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }
-
-#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
-
-#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
-
-#define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
-
-#define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c
-
-#define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020
-
-#define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024
-
-#define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c
-
-#define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030
-
-#define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054
-
-#define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064
-
-#define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c
-
-#define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080
-
-#define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094
-
-#define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4
-
-#define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8
-
-#define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4
-
-#define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc
-
-#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0
-
-#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4
-
-#define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8
-
-#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c
-
-#define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110
-
-#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114
-
-#define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118
-
-#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c
-
-#define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120
-
-#define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c
-
-#define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140
-
-#define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144
-
-#define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c
-
-#define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154
-
-#define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c
-
-#define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164
-
-#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180
-
-#define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184
-
-#define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c
-
-#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0
-
-
-#endif /* DSI_PHY_10NM_XML */
diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h
deleted file mode 100644
index 24e2fdc0cde1..000000000000
--- a/drivers/gpu/drm/msm/dsi/dsi_phy_14nm.xml.h
+++ /dev/null
@@ -1,309 +0,0 @@
-#ifndef DSI_PHY_14NM_XML
-#define DSI_PHY_14NM_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
-
-Copyright (C) 2013-2022 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-#define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
-
-#define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
-
-#define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
-
-#define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
-
-#define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
-#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
-#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT 4
-static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
-{
- return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
-}
-#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
-#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT 4
-static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
-{
- return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
-}
-
-#define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
-#define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
-
-#define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
-#define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004
-
-#define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c
-
-#define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020
-
-#define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024
-
-#define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028
-
-#define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c
-
-#define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030
-
-#define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034
-
-#define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038
-
-#define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c
-
-#define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040
-
-#define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044
-
-#define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048
-#define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001
-
-#define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c
-#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f
-#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0
-static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
-{
- return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
-}
-
-static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
-#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0
-#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT 6
-static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
-{
- return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
-}
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
-#define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; }
-#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
-#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0
-static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
-{
- return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
-}
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; }
-#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
-#define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0
-static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)
-{
- return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK;
-}
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; }
-#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
-#define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
-static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
-{
- return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK;
-}
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; }
-#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
-#define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
-static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
-{
- return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK;
-}
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; }
-#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
-#define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0
-static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)
-{
- return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK;
-}
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; }
-#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007
-#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0
-static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)
-{
- return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK;
-}
-#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
-#define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT 4
-static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)
-{
- return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK;
-}
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; }
-#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007
-#define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0
-static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)
-{
- return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK;
-}
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; }
-#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
-#define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
-static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
-{
- return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK;
-}
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; }
-
-static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }
-
-#define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000
-
-#define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004
-
-#define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010
-
-#define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c
-
-#define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028
-
-#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c
-
-#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030
-
-#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034
-
-#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038
-
-#define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c
-
-#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040
-
-#define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044
-
-#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048
-
-#define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c
-
-#define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c
-
-#define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058
-
-#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c
-
-#define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070
-
-#define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074
-
-#define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078
-
-#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c
-
-#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080
-
-#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084
-
-#define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088
-
-#define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c
-
-#define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090
-
-#define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094
-
-#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098
-
-#define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c
-
-#define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0
-
-#define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4
-
-#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8
-
-#define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac
-
-#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4
-
-#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8
-
-#define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc
-
-#define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0
-
-#define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4
-
-#define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc
-
-#define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8
-
-#define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0
-
-#define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4
-
-#define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8
-
-#define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc
-
-#define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100
-
-#define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104
-
-#define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108
-
-
-#endif /* DSI_PHY_14NM_XML */
diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h
deleted file mode 100644
index 6352541f37e9..000000000000
--- a/drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h
+++ /dev/null
@@ -1,237 +0,0 @@
-#ifndef DSI_PHY_20NM_XML
-#define DSI_PHY_20NM_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
-
-Copyright (C) 2013-2022 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
-
-static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
-
-static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
-
-#define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100
-
-#define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104
-
-#define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108
-
-#define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c
-
-#define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110
-
-#define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114
-
-#define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118
-
-#define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c
-
-#define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120
-
-#define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140
-#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
-#define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
-static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
-{
- return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
-}
-
-#define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144
-#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
-#define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
-static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
-{
- return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
-}
-
-#define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148
-#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
-#define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
-static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
-{
- return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
-}
-
-#define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c
-#define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
-
-#define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150
-#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
-#define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
-static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
-{
- return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
-}
-
-#define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154
-#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
-#define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
-static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
-{
- return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
-}
-
-#define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158
-#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
-#define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
-static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
-{
- return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
-}
-
-#define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c
-#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
-#define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
-static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
-{
- return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
-}
-
-#define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160
-#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
-#define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
-static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
-{
- return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
-}
-
-#define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164
-#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
-#define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
-static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
-{
- return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
-}
-#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
-#define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
-static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
-{
- return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
-}
-
-#define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168
-#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
-#define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
-static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
-{
- return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
-}
-
-#define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c
-#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
-#define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
-static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
-{
- return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
-}
-
-#define REG_DSI_20nm_PHY_CTRL_0 0x00000170
-
-#define REG_DSI_20nm_PHY_CTRL_1 0x00000174
-
-#define REG_DSI_20nm_PHY_CTRL_2 0x00000178
-
-#define REG_DSI_20nm_PHY_CTRL_3 0x0000017c
-
-#define REG_DSI_20nm_PHY_CTRL_4 0x00000180
-
-#define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184
-
-#define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188
-
-#define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4
-
-#define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8
-
-#define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc
-
-#define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0
-
-#define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4
-
-#define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8
-
-#define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4
-#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
-
-#define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc
-
-#define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000
-
-#define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004
-
-#define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008
-
-#define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c
-
-#define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010
-
-#define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014
-
-#define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
-
-
-#endif /* DSI_PHY_20NM_XML */
diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h
deleted file mode 100644
index 178bd4fd7893..000000000000
--- a/drivers/gpu/drm/msm/dsi/dsi_phy_28nm.xml.h
+++ /dev/null
@@ -1,384 +0,0 @@
-#ifndef DSI_PHY_28NM_XML
-#define DSI_PHY_28NM_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
-
-Copyright (C) 2013-2022 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
-
-static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
-
-static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
-
-#define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
-
-#define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
-
-#define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
-
-#define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
-
-#define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
-
-#define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
-
-#define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
-
-#define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
-
-#define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
-
-#define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
-#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
-#define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
-static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
-}
-
-#define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
-#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
-#define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
-static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
-}
-
-#define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
-#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
-#define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
-static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
-}
-
-#define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
-#define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
-
-#define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
-#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
-#define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
-static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
-}
-
-#define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
-#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
-#define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
-static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
-}
-
-#define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
-#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
-#define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
-static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
-}
-
-#define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
-#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
-#define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
-static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
-}
-
-#define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
-#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
-#define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
-static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
-}
-
-#define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
-#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
-#define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
-static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
-}
-#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
-#define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
-static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
-}
-
-#define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
-#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
-#define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
-static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
-}
-
-#define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
-#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
-#define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
-static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
-}
-
-#define REG_DSI_28nm_PHY_CTRL_0 0x00000170
-
-#define REG_DSI_28nm_PHY_CTRL_1 0x00000174
-
-#define REG_DSI_28nm_PHY_CTRL_2 0x00000178
-
-#define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
-
-#define REG_DSI_28nm_PHY_CTRL_4 0x00000180
-
-#define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
-
-#define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
-
-#define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
-
-#define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
-
-#define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
-
-#define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
-
-#define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
-
-#define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
-
-#define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
-#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
-
-#define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
-
-#define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
-
-#define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
-
-#define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
-
-#define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
-
-#define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
-
-#define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
-
-#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
-
-#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
-#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
-
-#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
-
-#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
-
-#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
-
-#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
-#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
-
-#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
-
-#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
-
-#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
-
-#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
-#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
-#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
-#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
-#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
-
-#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
-
-#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
-
-#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
-
-#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
-
-#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
-
-#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
-#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
-#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
-static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
-}
-#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
-
-#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
-#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
-#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
-static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
-}
-#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
-#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
-static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
-}
-
-#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
-#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
-#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
-static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
-}
-
-#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
-#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
-#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
-static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
-{
- return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
-}
-
-#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
-
-#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
-
-#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
-
-#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
-
-#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
-
-#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
-
-#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
-
-#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
-
-#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
-#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
-
-#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
-
-#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
-
-#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
-
-#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
-
-#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
-
-#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
-
-#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
-
-#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
-
-#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
-
-#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
-
-#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
-
-#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
-
-#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
-
-#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
-
-#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
-
-#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
-
-#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
-
-#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
-
-#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
-
-#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
-
-#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
-
-#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
-#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
-
-#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
-
-#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
-
-#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
-
-#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
-
-#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
-
-
-#endif /* DSI_PHY_28NM_XML */
diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h
deleted file mode 100644
index 5f900bb53519..000000000000
--- a/drivers/gpu/drm/msm/dsi/dsi_phy_28nm_8960.xml.h
+++ /dev/null
@@ -1,286 +0,0 @@
-#ifndef DSI_PHY_28NM_8960_XML
-#define DSI_PHY_28NM_8960_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
-
-Copyright (C) 2013-2022 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; }
-
-static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; }
-
-static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; }
-
-#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
-
-#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
-
-#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
-
-#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c
-
-#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114
-
-#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118
-
-#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140
-#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
-#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
-static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
-{
- return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
-}
-
-#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144
-#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
-#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
-static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
-{
- return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
-}
-
-#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148
-#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
-#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
-static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
-{
- return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
-}
-
-#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c
-
-#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150
-#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
-#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
-static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
-{
- return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
-}
-
-#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154
-#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
-#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
-static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
-{
- return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
-}
-
-#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158
-#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
-#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
-static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
-{
- return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
-}
-
-#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c
-#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
-#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
-static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
-{
- return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
-}
-
-#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160
-#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
-#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
-static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
-{
- return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK;
-}
-
-#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164
-#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
-#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
-static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
-{
- return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK;
-}
-#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
-#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4
-static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
-{
- return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK;
-}
-
-#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168
-#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
-#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
-static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
-{
- return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK;
-}
-
-#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c
-#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
-#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
-static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
-{
- return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
-}
-
-#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170
-
-#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174
-
-#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178
-
-#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c
-
-#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180
-
-#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184
-
-#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188
-
-#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c
-
-#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190
-
-#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194
-
-#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198
-
-#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c
-
-#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0
-
-#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000
-
-#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004
-
-#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008
-
-#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c
-
-#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010
-
-#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014
-
-#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018
-
-#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028
-
-#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c
-
-#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030
-
-#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034
-
-#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038
-
-#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c
-
-#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040
-
-#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044
-
-#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048
-
-#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050
-#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000
-#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c
-
-#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050
-
-#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080
-#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001
-
-
-#endif /* DSI_PHY_28NM_8960_XML */
diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h b/drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h
deleted file mode 100644
index 584cbd0205ef..000000000000
--- a/drivers/gpu/drm/msm/dsi/dsi_phy_7nm.xml.h
+++ /dev/null
@@ -1,483 +0,0 @@
-#ifndef DSI_PHY_7NM_XML
-#define DSI_PHY_7NM_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
-
-Copyright (C) 2013-2022 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-#define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x00000000
-
-#define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x00000004
-
-#define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x00000008
-
-#define REG_DSI_7nm_PHY_CMN_REVISION_ID3 0x0000000c
-
-#define REG_DSI_7nm_PHY_CMN_CLK_CFG0 0x00000010
-
-#define REG_DSI_7nm_PHY_CMN_CLK_CFG1 0x00000014
-
-#define REG_DSI_7nm_PHY_CMN_GLBL_CTRL 0x00000018
-
-#define REG_DSI_7nm_PHY_CMN_RBUF_CTRL 0x0000001c
-
-#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_0 0x00000020
-
-#define REG_DSI_7nm_PHY_CMN_CTRL_0 0x00000024
-
-#define REG_DSI_7nm_PHY_CMN_CTRL_1 0x00000028
-
-#define REG_DSI_7nm_PHY_CMN_CTRL_2 0x0000002c
-
-#define REG_DSI_7nm_PHY_CMN_CTRL_3 0x00000030
-
-#define REG_DSI_7nm_PHY_CMN_LANE_CFG0 0x00000034
-
-#define REG_DSI_7nm_PHY_CMN_LANE_CFG1 0x00000038
-
-#define REG_DSI_7nm_PHY_CMN_PLL_CNTRL 0x0000003c
-
-#define REG_DSI_7nm_PHY_CMN_DPHY_SOT 0x00000040
-
-#define REG_DSI_7nm_PHY_CMN_LANE_CTRL0 0x000000a0
-
-#define REG_DSI_7nm_PHY_CMN_LANE_CTRL1 0x000000a4
-
-#define REG_DSI_7nm_PHY_CMN_LANE_CTRL2 0x000000a8
-
-#define REG_DSI_7nm_PHY_CMN_LANE_CTRL3 0x000000ac
-
-#define REG_DSI_7nm_PHY_CMN_LANE_CTRL4 0x000000b0
-
-#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_0 0x000000b4
-
-#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_1 0x000000b8
-
-#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_2 0x000000bc
-
-#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_3 0x000000c0
-
-#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_4 0x000000c4
-
-#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_5 0x000000c8
-
-#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_6 0x000000cc
-
-#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_7 0x000000d0
-
-#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_8 0x000000d4
-
-#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_9 0x000000d8
-
-#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_10 0x000000dc
-
-#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_11 0x000000e0
-
-#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_12 0x000000e4
-
-#define REG_DSI_7nm_PHY_CMN_TIMING_CTRL_13 0x000000e8
-
-#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_0 0x000000ec
-
-#define REG_DSI_7nm_PHY_CMN_GLBL_HSTX_STR_CTRL_1 0x000000f0
-
-#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL 0x000000f4
-
-#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL 0x000000f8
-
-#define REG_DSI_7nm_PHY_CMN_GLBL_RESCODE_OFFSET_MID_CTRL 0x000000fc
-
-#define REG_DSI_7nm_PHY_CMN_GLBL_LPTX_STR_CTRL 0x00000100
-
-#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_0 0x00000104
-
-#define REG_DSI_7nm_PHY_CMN_GLBL_PEMPH_CTRL_1 0x00000108
-
-#define REG_DSI_7nm_PHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL 0x0000010c
-
-#define REG_DSI_7nm_PHY_CMN_VREG_CTRL_1 0x00000110
-
-#define REG_DSI_7nm_PHY_CMN_CTRL_4 0x00000114
-
-#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE4 0x00000128
-
-#define REG_DSI_7nm_PHY_CMN_PHY_STATUS 0x00000140
-
-#define REG_DSI_7nm_PHY_CMN_LANE_STATUS0 0x00000148
-
-#define REG_DSI_7nm_PHY_CMN_LANE_STATUS1 0x0000014c
-
-#define REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10 0x000001ac
-
-static inline uint32_t REG_DSI_7nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x80*i0; }
-
-static inline uint32_t REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000010 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000014 + 0x80*i0; }
-
-static inline uint32_t REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; }
-
-#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
-
-#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
-
-#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS 0x00000008
-
-#define REG_DSI_7nm_PHY_PLL_INT_LOOP_SETTINGS_TWO 0x0000000c
-
-#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
-
-#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FOUR 0x00000014
-
-#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE 0x00000018
-
-#define REG_DSI_7nm_PHY_PLL_INT_LOOP_CONTROLS 0x0000001c
-
-#define REG_DSI_7nm_PHY_PLL_DSM_DIVIDER 0x00000020
-
-#define REG_DSI_7nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000024
-
-#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES 0x00000028
-
-#define REG_DSI_7nm_PHY_PLL_FREQ_UPDATE_CONTROL_OVERRIDES 0x0000002c
-
-#define REG_DSI_7nm_PHY_PLL_CMODE 0x00000030
-
-#define REG_DSI_7nm_PHY_PLL_PSM_CTRL 0x00000034
-
-#define REG_DSI_7nm_PHY_PLL_RSM_CTRL 0x00000038
-
-#define REG_DSI_7nm_PHY_PLL_VCO_TUNE_MAP 0x0000003c
-
-#define REG_DSI_7nm_PHY_PLL_PLL_CNTRL 0x00000040
-
-#define REG_DSI_7nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000044
-
-#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_LOW 0x00000048
-
-#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_TIMER_HIGH 0x0000004c
-
-#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS 0x00000050
-
-#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MIN 0x00000054
-
-#define REG_DSI_7nm_PHY_PLL_BAND_SEL_MAX 0x00000058
-
-#define REG_DSI_7nm_PHY_PLL_BAND_SEL_PFILT 0x0000005c
-
-#define REG_DSI_7nm_PHY_PLL_BAND_SEL_IFILT 0x00000060
-
-#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_TWO 0x00000064
-
-#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000068
-
-#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_FOUR 0x0000006c
-
-#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_HIGH 0x00000070
-
-#define REG_DSI_7nm_PHY_PLL_BAND_SEL_ICODE_LOW 0x00000074
-
-#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000078
-
-#define REG_DSI_7nm_PHY_PLL_FREQ_DETECT_THRESH 0x0000007c
-
-#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_HIGH 0x00000080
-
-#define REG_DSI_7nm_PHY_PLL_FREQ_DET_REFCLK_LOW 0x00000084
-
-#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_HIGH 0x00000088
-
-#define REG_DSI_7nm_PHY_PLL_FREQ_DET_PLLCLK_LOW 0x0000008c
-
-#define REG_DSI_7nm_PHY_PLL_PFILT 0x00000090
-
-#define REG_DSI_7nm_PHY_PLL_IFILT 0x00000094
-
-#define REG_DSI_7nm_PHY_PLL_PLL_GAIN 0x00000098
-
-#define REG_DSI_7nm_PHY_PLL_ICODE_LOW 0x0000009c
-
-#define REG_DSI_7nm_PHY_PLL_ICODE_HIGH 0x000000a0
-
-#define REG_DSI_7nm_PHY_PLL_LOCKDET 0x000000a4
-
-#define REG_DSI_7nm_PHY_PLL_OUTDIV 0x000000a8
-
-#define REG_DSI_7nm_PHY_PLL_FASTLOCK_CONTROL 0x000000ac
-
-#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_ONE 0x000000b0
-
-#define REG_DSI_7nm_PHY_PLL_PASS_OUT_OVERRIDE_TWO 0x000000b4
-
-#define REG_DSI_7nm_PHY_PLL_CORE_OVERRIDE 0x000000b8
-
-#define REG_DSI_7nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000bc
-
-#define REG_DSI_7nm_PHY_PLL_RATE_CHANGE 0x000000c0
-
-#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS 0x000000c4
-
-#define REG_DSI_7nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000c8
-
-#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START 0x000000cc
-
-#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW 0x000000d0
-
-#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID 0x000000d4
-
-#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH 0x000000d8
-
-#define REG_DSI_7nm_PHY_PLL_DEC_FRAC_MUXES 0x000000dc
-
-#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000e0
-
-#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000e4
-
-#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000e8
-
-#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000ec
-
-#define REG_DSI_7nm_PHY_PLL_DECIMAL_DIV_START_2 0x000000f0
-
-#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_LOW_2 0x000000f4
-
-#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_MID_2 0x000000f8
-
-#define REG_DSI_7nm_PHY_PLL_FRAC_DIV_START_HIGH_2 0x000000fc
-
-#define REG_DSI_7nm_PHY_PLL_MASH_CONTROL 0x00000100
-
-#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW 0x00000104
-
-#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH 0x00000108
-
-#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW 0x0000010c
-
-#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH 0x00000110
-
-#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW 0x00000114
-
-#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH 0x00000118
-
-#define REG_DSI_7nm_PHY_PLL_SSC_MUX_CONTROL 0x0000011c
-
-#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x00000120
-
-#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000124
-
-#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000128
-
-#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x0000012c
-
-#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_1 0x00000130
-
-#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_1 0x00000134
-
-#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_LOW_2 0x00000138
-
-#define REG_DSI_7nm_PHY_PLL_SSC_STEPSIZE_HIGH_2 0x0000013c
-
-#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_LOW_2 0x00000140
-
-#define REG_DSI_7nm_PHY_PLL_SSC_DIV_PER_HIGH_2 0x00000144
-
-#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_LOW_2 0x00000148
-
-#define REG_DSI_7nm_PHY_PLL_SSC_ADJPER_HIGH_2 0x0000014c
-
-#define REG_DSI_7nm_PHY_PLL_SSC_CONTROL 0x00000150
-
-#define REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000154
-
-#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000158
-
-#define REG_DSI_7nm_PHY_PLL_PLL_LOCKDET_RATE_2 0x0000015c
-
-#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x00000160
-
-#define REG_DSI_7nm_PHY_PLL_PLL_PROP_GAIN_RATE_2 0x00000164
-
-#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_1 0x00000168
-
-#define REG_DSI_7nm_PHY_PLL_PLL_BAND_SEL_RATE_2 0x0000016c
-
-#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x00000170
-
-#define REG_DSI_7nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_2 0x00000174
-
-#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000178
-
-#define REG_DSI_7nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_2 0x0000017c
-
-#define REG_DSI_7nm_PHY_PLL_PLL_FASTLOCK_EN_BAND 0x00000180
-
-#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MID 0x00000184
-
-#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x00000188
-
-#define REG_DSI_7nm_PHY_PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x0000018c
-
-#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000190
-
-#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_DELAY 0x00000194
-
-#define REG_DSI_7nm_PHY_PLL_PLL_LOCK_MIN_DELAY 0x00000198
-
-#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS 0x0000019c
-
-#define REG_DSI_7nm_PHY_PLL_SPARE_AND_JPC_OVERRIDES 0x000001a0
-
-#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_1 0x000001a4
-
-#define REG_DSI_7nm_PHY_PLL_BIAS_CONTROL_2 0x000001a8
-
-#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_CTRL_1 0x000001ac
-
-#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_ONE 0x000001b0
-
-#define REG_DSI_7nm_PHY_PLL_COMMON_STATUS_TWO 0x000001b4
-
-#define REG_DSI_7nm_PHY_PLL_BAND_SEL_CAL 0x000001b8
-
-#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_LOW 0x000001bc
-
-#define REG_DSI_7nm_PHY_PLL_ICODE_ACCUM_STATUS_HIGH 0x000001c0
-
-#define REG_DSI_7nm_PHY_PLL_FD_OUT_LOW 0x000001c4
-
-#define REG_DSI_7nm_PHY_PLL_FD_OUT_HIGH 0x000001c8
-
-#define REG_DSI_7nm_PHY_PLL_ALOG_OBSV_BUS_STATUS_1 0x000001cc
-
-#define REG_DSI_7nm_PHY_PLL_PLL_MISC_CONFIG 0x000001d0
-
-#define REG_DSI_7nm_PHY_PLL_FLL_CONFIG 0x000001d4
-
-#define REG_DSI_7nm_PHY_PLL_FLL_FREQ_ACQ_TIME 0x000001d8
-
-#define REG_DSI_7nm_PHY_PLL_FLL_CODE0 0x000001dc
-
-#define REG_DSI_7nm_PHY_PLL_FLL_CODE1 0x000001e0
-
-#define REG_DSI_7nm_PHY_PLL_FLL_GAIN0 0x000001e4
-
-#define REG_DSI_7nm_PHY_PLL_FLL_GAIN1 0x000001e8
-
-#define REG_DSI_7nm_PHY_PLL_SW_RESET 0x000001ec
-
-#define REG_DSI_7nm_PHY_PLL_FAST_PWRUP 0x000001f0
-
-#define REG_DSI_7nm_PHY_PLL_LOCKTIME0 0x000001f4
-
-#define REG_DSI_7nm_PHY_PLL_LOCKTIME1 0x000001f8
-
-#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS_SEL 0x000001fc
-
-#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS0 0x00000200
-
-#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS1 0x00000204
-
-#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS2 0x00000208
-
-#define REG_DSI_7nm_PHY_PLL_DEBUG_BUS3 0x0000020c
-
-#define REG_DSI_7nm_PHY_PLL_ANALOG_FLL_CONTROL_OVERRIDES 0x00000210
-
-#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG 0x00000214
-
-#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE0_STATUS 0x00000218
-
-#define REG_DSI_7nm_PHY_PLL_VCO_CAL_CODE1_MODE1_STATUS 0x0000021c
-
-#define REG_DSI_7nm_PHY_PLL_RESET_SM_STATUS 0x00000220
-
-#define REG_DSI_7nm_PHY_PLL_TDC_OFFSET 0x00000224
-
-#define REG_DSI_7nm_PHY_PLL_PS3_PWRDOWN_CONTROLS 0x00000228
-
-#define REG_DSI_7nm_PHY_PLL_PS4_PWRDOWN_CONTROLS 0x0000022c
-
-#define REG_DSI_7nm_PHY_PLL_PLL_RST_CONTROLS 0x00000230
-
-#define REG_DSI_7nm_PHY_PLL_GEAR_BAND_SELECT_CONTROLS 0x00000234
-
-#define REG_DSI_7nm_PHY_PLL_PSM_CLK_CONTROLS 0x00000238
-
-#define REG_DSI_7nm_PHY_PLL_SYSTEM_MUXES_2 0x0000023c
-
-#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1 0x00000240
-
-#define REG_DSI_7nm_PHY_PLL_VCO_CONFIG_2 0x00000244
-
-#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_1 0x00000248
-
-#define REG_DSI_7nm_PHY_PLL_CLOCK_INVERTERS_2 0x0000024c
-
-#define REG_DSI_7nm_PHY_PLL_CMODE_1 0x00000250
-
-#define REG_DSI_7nm_PHY_PLL_CMODE_2 0x00000254
-
-#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1 0x00000258
-
-#define REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_2 0x0000025c
-
-#define REG_DSI_7nm_PHY_PLL_PERF_OPTIMIZE 0x00000260
-
-
-#endif /* DSI_PHY_7NM_XML */
diff --git a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
deleted file mode 100644
index 7062f7164216..000000000000
--- a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
+++ /dev/null
@@ -1,131 +0,0 @@
-#ifndef MMSS_CC_XML
-#define MMSS_CC_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
-
-Copyright (C) 2013-2022 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-enum mmss_cc_clk {
- CLK = 0,
- PCLK = 1,
-};
-
-#define REG_MMSS_CC_AHB 0x00000008
-
-static inline uint32_t __offset_CLK(enum mmss_cc_clk idx)
-{
- switch (idx) {
- case CLK: return 0x0000004c;
- case PCLK: return 0x00000130;
- default: return INVALID_IDX(idx);
- }
-}
-static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); }
-
-static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); }
-#define MMSS_CC_CLK_CC_CLK_EN 0x00000001
-#define MMSS_CC_CLK_CC_ROOT_EN 0x00000004
-#define MMSS_CC_CLK_CC_MND_EN 0x00000020
-#define MMSS_CC_CLK_CC_MND_MODE__MASK 0x000000c0
-#define MMSS_CC_CLK_CC_MND_MODE__SHIFT 6
-static inline uint32_t MMSS_CC_CLK_CC_MND_MODE(uint32_t val)
-{
- return ((val) << MMSS_CC_CLK_CC_MND_MODE__SHIFT) & MMSS_CC_CLK_CC_MND_MODE__MASK;
-}
-#define MMSS_CC_CLK_CC_PMXO_SEL__MASK 0x00000300
-#define MMSS_CC_CLK_CC_PMXO_SEL__SHIFT 8
-static inline uint32_t MMSS_CC_CLK_CC_PMXO_SEL(uint32_t val)
-{
- return ((val) << MMSS_CC_CLK_CC_PMXO_SEL__SHIFT) & MMSS_CC_CLK_CC_PMXO_SEL__MASK;
-}
-
-static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); }
-#define MMSS_CC_CLK_MD_D__MASK 0x000000ff
-#define MMSS_CC_CLK_MD_D__SHIFT 0
-static inline uint32_t MMSS_CC_CLK_MD_D(uint32_t val)
-{
- return ((val) << MMSS_CC_CLK_MD_D__SHIFT) & MMSS_CC_CLK_MD_D__MASK;
-}
-#define MMSS_CC_CLK_MD_M__MASK 0x0000ff00
-#define MMSS_CC_CLK_MD_M__SHIFT 8
-static inline uint32_t MMSS_CC_CLK_MD_M(uint32_t val)
-{
- return ((val) << MMSS_CC_CLK_MD_M__SHIFT) & MMSS_CC_CLK_MD_M__MASK;
-}
-
-static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); }
-#define MMSS_CC_CLK_NS_SRC__MASK 0x0000000f
-#define MMSS_CC_CLK_NS_SRC__SHIFT 0
-static inline uint32_t MMSS_CC_CLK_NS_SRC(uint32_t val)
-{
- return ((val) << MMSS_CC_CLK_NS_SRC__SHIFT) & MMSS_CC_CLK_NS_SRC__MASK;
-}
-#define MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK 0x00fff000
-#define MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT 12
-static inline uint32_t MMSS_CC_CLK_NS_PRE_DIV_FUNC(uint32_t val)
-{
- return ((val) << MMSS_CC_CLK_NS_PRE_DIV_FUNC__SHIFT) & MMSS_CC_CLK_NS_PRE_DIV_FUNC__MASK;
-}
-#define MMSS_CC_CLK_NS_VAL__MASK 0xff000000
-#define MMSS_CC_CLK_NS_VAL__SHIFT 24
-static inline uint32_t MMSS_CC_CLK_NS_VAL(uint32_t val)
-{
- return ((val) << MMSS_CC_CLK_NS_VAL__SHIFT) & MMSS_CC_CLK_NS_VAL__MASK;
-}
-
-#define REG_MMSS_CC_DSI2_PIXEL_CC 0x00000094
-
-#define REG_MMSS_CC_DSI2_PIXEL_NS 0x000000e4
-
-#define REG_MMSS_CC_DSI2_PIXEL_CC2 0x00000264
-
-
-#endif /* MMSS_CC_XML */
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index e4275d3ad581..5a5dc3faa971 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -12,10 +12,10 @@
#include "dsi.h"
-#define dsi_phy_read(offset) msm_readl((offset))
-#define dsi_phy_write(offset, data) msm_writel((data), (offset))
-#define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); }
-#define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); }
+#define dsi_phy_read(offset) readl((offset))
+#define dsi_phy_write(offset, data) writel((data), (offset))
+#define dsi_phy_write_udelay(offset, data, delay_us) { writel((data), (offset)); udelay(delay_us); }
+#define dsi_phy_write_ndelay(offset, data, delay_ns) { writel((data), (offset)); ndelay(delay_ns); }
struct msm_dsi_phy_ops {
int (*pll_init)(struct msm_dsi_phy *phy);
diff --git a/drivers/gpu/drm/msm/dsi/sfpb.xml.h b/drivers/gpu/drm/msm/dsi/sfpb.xml.h
deleted file mode 100644
index 344a1a1620cd..000000000000
--- a/drivers/gpu/drm/msm/dsi/sfpb.xml.h
+++ /dev/null
@@ -1,70 +0,0 @@
-#ifndef SFPB_XML
-#define SFPB_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
-
-Copyright (C) 2013-2022 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-enum sfpb_ahb_arb_master_port_en {
- SFPB_MASTER_PORT_ENABLE = 3,
- SFPB_MASTER_PORT_DISABLE = 0,
-};
-
-#define REG_SFPB_GPREG 0x00000058
-#define SFPB_GPREG_MASTER_PORT_EN__MASK 0x00001800
-#define SFPB_GPREG_MASTER_PORT_EN__SHIFT 11
-static inline uint32_t SFPB_GPREG_MASTER_PORT_EN(enum sfpb_ahb_arb_master_port_en val)
-{
- return ((val) << SFPB_GPREG_MASTER_PORT_EN__SHIFT) & SFPB_GPREG_MASTER_PORT_EN__MASK;
-}
-
-
-#endif /* SFPB_XML */
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c
index c8ebd75176bb..24abcb7254cc 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.c
@@ -5,8 +5,8 @@
* Author: Rob Clark <robdclark@gmail.com>
*/
+#include <linux/gpio/consumer.h>
#include <linux/of_irq.h>
-#include <linux/of_gpio.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
index ec5786440391..4586baf36415 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -115,17 +115,17 @@ void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data)
{
- msm_writel(data, hdmi->mmio + reg);
+ writel(data, hdmi->mmio + reg);
}
static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg)
{
- return msm_readl(hdmi->mmio + reg);
+ return readl(hdmi->mmio + reg);
}
static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg)
{
- return msm_readl(hdmi->qfprom_mmio + reg);
+ return readl(hdmi->qfprom_mmio + reg);
}
/*
@@ -166,12 +166,12 @@ struct hdmi_phy {
static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data)
{
- msm_writel(data, phy->mmio + reg);
+ writel(data, phy->mmio + reg);
}
static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg)
{
- return msm_readl(phy->mmio + reg);
+ return readl(phy->mmio + reg);
}
int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy);
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
deleted file mode 100644
index 973b460486a5..000000000000
--- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
+++ /dev/null
@@ -1,1399 +0,0 @@
-#ifndef HDMI_XML
-#define HDMI_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
-
-Copyright (C) 2013-2022 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-enum hdmi_hdcp_key_state {
- HDCP_KEYS_STATE_NO_KEYS = 0,
- HDCP_KEYS_STATE_NOT_CHECKED = 1,
- HDCP_KEYS_STATE_CHECKING = 2,
- HDCP_KEYS_STATE_VALID = 3,
- HDCP_KEYS_STATE_AKSV_NOT_VALID = 4,
- HDCP_KEYS_STATE_CHKSUM_MISMATCH = 5,
- HDCP_KEYS_STATE_PROD_AKSV = 6,
- HDCP_KEYS_STATE_RESERVED = 7,
-};
-
-enum hdmi_ddc_read_write {
- DDC_WRITE = 0,
- DDC_READ = 1,
-};
-
-enum hdmi_acr_cts {
- ACR_NONE = 0,
- ACR_32 = 1,
- ACR_44 = 2,
- ACR_48 = 3,
-};
-
-#define REG_HDMI_CTRL 0x00000000
-#define HDMI_CTRL_ENABLE 0x00000001
-#define HDMI_CTRL_HDMI 0x00000002
-#define HDMI_CTRL_ENCRYPTED 0x00000004
-
-#define REG_HDMI_AUDIO_PKT_CTRL1 0x00000020
-#define HDMI_AUDIO_PKT_CTRL1_AUDIO_SAMPLE_SEND 0x00000001
-
-#define REG_HDMI_ACR_PKT_CTRL 0x00000024
-#define HDMI_ACR_PKT_CTRL_CONT 0x00000001
-#define HDMI_ACR_PKT_CTRL_SEND 0x00000002
-#define HDMI_ACR_PKT_CTRL_SELECT__MASK 0x00000030
-#define HDMI_ACR_PKT_CTRL_SELECT__SHIFT 4
-static inline uint32_t HDMI_ACR_PKT_CTRL_SELECT(enum hdmi_acr_cts val)
-{
- return ((val) << HDMI_ACR_PKT_CTRL_SELECT__SHIFT) & HDMI_ACR_PKT_CTRL_SELECT__MASK;
-}
-#define HDMI_ACR_PKT_CTRL_SOURCE 0x00000100
-#define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK 0x00070000
-#define HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT 16
-static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val)
-{
- return ((val) << HDMI_ACR_PKT_CTRL_N_MULTIPLIER__SHIFT) & HDMI_ACR_PKT_CTRL_N_MULTIPLIER__MASK;
-}
-#define HDMI_ACR_PKT_CTRL_AUDIO_PRIORITY 0x80000000
-
-#define REG_HDMI_VBI_PKT_CTRL 0x00000028
-#define HDMI_VBI_PKT_CTRL_GC_ENABLE 0x00000010
-#define HDMI_VBI_PKT_CTRL_GC_EVERY_FRAME 0x00000020
-#define HDMI_VBI_PKT_CTRL_ISRC_SEND 0x00000100
-#define HDMI_VBI_PKT_CTRL_ISRC_CONTINUOUS 0x00000200
-#define HDMI_VBI_PKT_CTRL_ACP_SEND 0x00001000
-#define HDMI_VBI_PKT_CTRL_ACP_SRC_SW 0x00002000
-
-#define REG_HDMI_INFOFRAME_CTRL0 0x0000002c
-#define HDMI_INFOFRAME_CTRL0_AVI_SEND 0x00000001
-#define HDMI_INFOFRAME_CTRL0_AVI_CONT 0x00000002
-#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND 0x00000010
-#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT 0x00000020
-#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040
-#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080
-
-#define REG_HDMI_INFOFRAME_CTRL1 0x00000030
-#define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK 0x0000003f
-#define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT 0
-static inline uint32_t HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(uint32_t val)
-{
- return ((val) << HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK;
-}
-#define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK 0x00003f00
-#define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT 8
-static inline uint32_t HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE(uint32_t val)
-{
- return ((val) << HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK;
-}
-#define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK 0x003f0000
-#define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT 16
-static inline uint32_t HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE(uint32_t val)
-{
- return ((val) << HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK;
-}
-#define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK 0x3f000000
-#define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT 24
-static inline uint32_t HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE(uint32_t val)
-{
- return ((val) << HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK;
-}
-
-#define REG_HDMI_GEN_PKT_CTRL 0x00000034
-#define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001
-#define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002
-#define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK 0x0000000c
-#define HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT 2
-static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE(uint32_t val)
-{
- return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE__MASK;
-}
-#define HDMI_GEN_PKT_CTRL_GENERIC1_SEND 0x00000010
-#define HDMI_GEN_PKT_CTRL_GENERIC1_CONT 0x00000020
-#define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK 0x003f0000
-#define HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT 16
-static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC0_LINE(uint32_t val)
-{
- return ((val) << HDMI_GEN_PKT_CTRL_GENERIC0_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK;
-}
-#define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK 0x3f000000
-#define HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT 24
-static inline uint32_t HDMI_GEN_PKT_CTRL_GENERIC1_LINE(uint32_t val)
-{
- return ((val) << HDMI_GEN_PKT_CTRL_GENERIC1_LINE__SHIFT) & HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK;
-}
-
-#define REG_HDMI_GC 0x00000040
-#define HDMI_GC_MUTE 0x00000001
-
-#define REG_HDMI_AUDIO_PKT_CTRL2 0x00000044
-#define HDMI_AUDIO_PKT_CTRL2_OVERRIDE 0x00000001
-#define HDMI_AUDIO_PKT_CTRL2_LAYOUT 0x00000002
-
-static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; }
-
-#define REG_HDMI_GENERIC0_HDR 0x00000084
-
-static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; }
-
-#define REG_HDMI_GENERIC1_HDR 0x000000a4
-
-static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; }
-
-static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
-
-static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
-#define HDMI_ACR_0_CTS__MASK 0xfffff000
-#define HDMI_ACR_0_CTS__SHIFT 12
-static inline uint32_t HDMI_ACR_0_CTS(uint32_t val)
-{
- return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK;
-}
-
-static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; }
-#define HDMI_ACR_1_N__MASK 0xffffffff
-#define HDMI_ACR_1_N__SHIFT 0
-static inline uint32_t HDMI_ACR_1_N(uint32_t val)
-{
- return ((val) << HDMI_ACR_1_N__SHIFT) & HDMI_ACR_1_N__MASK;
-}
-
-#define REG_HDMI_AUDIO_INFO0 0x000000e4
-#define HDMI_AUDIO_INFO0_CHECKSUM__MASK 0x000000ff
-#define HDMI_AUDIO_INFO0_CHECKSUM__SHIFT 0
-static inline uint32_t HDMI_AUDIO_INFO0_CHECKSUM(uint32_t val)
-{
- return ((val) << HDMI_AUDIO_INFO0_CHECKSUM__SHIFT) & HDMI_AUDIO_INFO0_CHECKSUM__MASK;
-}
-#define HDMI_AUDIO_INFO0_CC__MASK 0x00000700
-#define HDMI_AUDIO_INFO0_CC__SHIFT 8
-static inline uint32_t HDMI_AUDIO_INFO0_CC(uint32_t val)
-{
- return ((val) << HDMI_AUDIO_INFO0_CC__SHIFT) & HDMI_AUDIO_INFO0_CC__MASK;
-}
-
-#define REG_HDMI_AUDIO_INFO1 0x000000e8
-#define HDMI_AUDIO_INFO1_CA__MASK 0x000000ff
-#define HDMI_AUDIO_INFO1_CA__SHIFT 0
-static inline uint32_t HDMI_AUDIO_INFO1_CA(uint32_t val)
-{
- return ((val) << HDMI_AUDIO_INFO1_CA__SHIFT) & HDMI_AUDIO_INFO1_CA__MASK;
-}
-#define HDMI_AUDIO_INFO1_LSV__MASK 0x00007800
-#define HDMI_AUDIO_INFO1_LSV__SHIFT 11
-static inline uint32_t HDMI_AUDIO_INFO1_LSV(uint32_t val)
-{
- return ((val) << HDMI_AUDIO_INFO1_LSV__SHIFT) & HDMI_AUDIO_INFO1_LSV__MASK;
-}
-#define HDMI_AUDIO_INFO1_DM_INH 0x00008000
-
-#define REG_HDMI_HDCP_CTRL 0x00000110
-#define HDMI_HDCP_CTRL_ENABLE 0x00000001
-#define HDMI_HDCP_CTRL_ENCRYPTION_ENABLE 0x00000100
-
-#define REG_HDMI_HDCP_DEBUG_CTRL 0x00000114
-#define HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER 0x00000004
-
-#define REG_HDMI_HDCP_INT_CTRL 0x00000118
-#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT 0x00000001
-#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK 0x00000002
-#define HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK 0x00000004
-#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT 0x00000010
-#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK 0x00000020
-#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK 0x00000040
-#define HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK 0x00000080
-#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT 0x00000100
-#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_ACK 0x00000200
-#define HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_MASK 0x00000400
-#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT 0x00001000
-#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_ACK 0x00002000
-#define HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_MASK 0x00004000
-
-#define REG_HDMI_HDCP_LINK0_STATUS 0x0000011c
-#define HDMI_HDCP_LINK0_STATUS_AN_0_READY 0x00000100
-#define HDMI_HDCP_LINK0_STATUS_AN_1_READY 0x00000200
-#define HDMI_HDCP_LINK0_STATUS_RI_MATCHES 0x00001000
-#define HDMI_HDCP_LINK0_STATUS_V_MATCHES 0x00100000
-#define HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK 0x70000000
-#define HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT 28
-static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state val)
-{
- return ((val) << HDMI_HDCP_LINK0_STATUS_KEY_STATE__SHIFT) & HDMI_HDCP_LINK0_STATUS_KEY_STATE__MASK;
-}
-
-#define REG_HDMI_HDCP_DDC_CTRL_0 0x00000120
-#define HDMI_HDCP_DDC_CTRL_0_DISABLE 0x00000001
-
-#define REG_HDMI_HDCP_DDC_CTRL_1 0x00000124
-#define HDMI_HDCP_DDC_CTRL_1_FAILED_ACK 0x00000001
-
-#define REG_HDMI_HDCP_DDC_STATUS 0x00000128
-#define HDMI_HDCP_DDC_STATUS_XFER_REQ 0x00000010
-#define HDMI_HDCP_DDC_STATUS_XFER_DONE 0x00000400
-#define HDMI_HDCP_DDC_STATUS_ABORTED 0x00001000
-#define HDMI_HDCP_DDC_STATUS_TIMEOUT 0x00002000
-#define HDMI_HDCP_DDC_STATUS_NACK0 0x00004000
-#define HDMI_HDCP_DDC_STATUS_NACK1 0x00008000
-#define HDMI_HDCP_DDC_STATUS_FAILED 0x00010000
-
-#define REG_HDMI_HDCP_ENTROPY_CTRL0 0x0000012c
-
-#define REG_HDMI_HDCP_ENTROPY_CTRL1 0x0000025c
-
-#define REG_HDMI_HDCP_RESET 0x00000130
-#define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001
-
-#define REG_HDMI_HDCP_RCVPORT_DATA0 0x00000134
-
-#define REG_HDMI_HDCP_RCVPORT_DATA1 0x00000138
-
-#define REG_HDMI_HDCP_RCVPORT_DATA2_0 0x0000013c
-
-#define REG_HDMI_HDCP_RCVPORT_DATA2_1 0x00000140
-
-#define REG_HDMI_HDCP_RCVPORT_DATA3 0x00000144
-
-#define REG_HDMI_HDCP_RCVPORT_DATA4 0x00000148
-
-#define REG_HDMI_HDCP_RCVPORT_DATA5 0x0000014c
-
-#define REG_HDMI_HDCP_RCVPORT_DATA6 0x00000150
-
-#define REG_HDMI_HDCP_RCVPORT_DATA7 0x00000154
-
-#define REG_HDMI_HDCP_RCVPORT_DATA8 0x00000158
-
-#define REG_HDMI_HDCP_RCVPORT_DATA9 0x0000015c
-
-#define REG_HDMI_HDCP_RCVPORT_DATA10 0x00000160
-
-#define REG_HDMI_HDCP_RCVPORT_DATA11 0x00000164
-
-#define REG_HDMI_HDCP_RCVPORT_DATA12 0x00000168
-
-#define REG_HDMI_VENSPEC_INFO0 0x0000016c
-
-#define REG_HDMI_VENSPEC_INFO1 0x00000170
-
-#define REG_HDMI_VENSPEC_INFO2 0x00000174
-
-#define REG_HDMI_VENSPEC_INFO3 0x00000178
-
-#define REG_HDMI_VENSPEC_INFO4 0x0000017c
-
-#define REG_HDMI_VENSPEC_INFO5 0x00000180
-
-#define REG_HDMI_VENSPEC_INFO6 0x00000184
-
-#define REG_HDMI_AUDIO_CFG 0x000001d0
-#define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001
-#define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0
-#define HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT 4
-static inline uint32_t HDMI_AUDIO_CFG_FIFO_WATERMARK(uint32_t val)
-{
- return ((val) << HDMI_AUDIO_CFG_FIFO_WATERMARK__SHIFT) & HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK;
-}
-
-#define REG_HDMI_USEC_REFTIMER 0x00000208
-
-#define REG_HDMI_DDC_CTRL 0x0000020c
-#define HDMI_DDC_CTRL_GO 0x00000001
-#define HDMI_DDC_CTRL_SOFT_RESET 0x00000002
-#define HDMI_DDC_CTRL_SEND_RESET 0x00000004
-#define HDMI_DDC_CTRL_SW_STATUS_RESET 0x00000008
-#define HDMI_DDC_CTRL_TRANSACTION_CNT__MASK 0x00300000
-#define HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT 20
-static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val)
-{
- return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK;
-}
-
-#define REG_HDMI_DDC_ARBITRATION 0x00000210
-#define HDMI_DDC_ARBITRATION_HW_ARBITRATION 0x00000010
-
-#define REG_HDMI_DDC_INT_CTRL 0x00000214
-#define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001
-#define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002
-#define HDMI_DDC_INT_CTRL_SW_DONE_MASK 0x00000004
-
-#define REG_HDMI_DDC_SW_STATUS 0x00000218
-#define HDMI_DDC_SW_STATUS_NACK0 0x00001000
-#define HDMI_DDC_SW_STATUS_NACK1 0x00002000
-#define HDMI_DDC_SW_STATUS_NACK2 0x00004000
-#define HDMI_DDC_SW_STATUS_NACK3 0x00008000
-
-#define REG_HDMI_DDC_HW_STATUS 0x0000021c
-#define HDMI_DDC_HW_STATUS_DONE 0x00000008
-
-#define REG_HDMI_DDC_SPEED 0x00000220
-#define HDMI_DDC_SPEED_THRESHOLD__MASK 0x00000003
-#define HDMI_DDC_SPEED_THRESHOLD__SHIFT 0
-static inline uint32_t HDMI_DDC_SPEED_THRESHOLD(uint32_t val)
-{
- return ((val) << HDMI_DDC_SPEED_THRESHOLD__SHIFT) & HDMI_DDC_SPEED_THRESHOLD__MASK;
-}
-#define HDMI_DDC_SPEED_PRESCALE__MASK 0xffff0000
-#define HDMI_DDC_SPEED_PRESCALE__SHIFT 16
-static inline uint32_t HDMI_DDC_SPEED_PRESCALE(uint32_t val)
-{
- return ((val) << HDMI_DDC_SPEED_PRESCALE__SHIFT) & HDMI_DDC_SPEED_PRESCALE__MASK;
-}
-
-#define REG_HDMI_DDC_SETUP 0x00000224
-#define HDMI_DDC_SETUP_TIMEOUT__MASK 0xff000000
-#define HDMI_DDC_SETUP_TIMEOUT__SHIFT 24
-static inline uint32_t HDMI_DDC_SETUP_TIMEOUT(uint32_t val)
-{
- return ((val) << HDMI_DDC_SETUP_TIMEOUT__SHIFT) & HDMI_DDC_SETUP_TIMEOUT__MASK;
-}
-
-static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; }
-
-static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; }
-#define HDMI_I2C_TRANSACTION_REG_RW__MASK 0x00000001
-#define HDMI_I2C_TRANSACTION_REG_RW__SHIFT 0
-static inline uint32_t HDMI_I2C_TRANSACTION_REG_RW(enum hdmi_ddc_read_write val)
-{
- return ((val) << HDMI_I2C_TRANSACTION_REG_RW__SHIFT) & HDMI_I2C_TRANSACTION_REG_RW__MASK;
-}
-#define HDMI_I2C_TRANSACTION_REG_STOP_ON_NACK 0x00000100
-#define HDMI_I2C_TRANSACTION_REG_START 0x00001000
-#define HDMI_I2C_TRANSACTION_REG_STOP 0x00002000
-#define HDMI_I2C_TRANSACTION_REG_CNT__MASK 0x00ff0000
-#define HDMI_I2C_TRANSACTION_REG_CNT__SHIFT 16
-static inline uint32_t HDMI_I2C_TRANSACTION_REG_CNT(uint32_t val)
-{
- return ((val) << HDMI_I2C_TRANSACTION_REG_CNT__SHIFT) & HDMI_I2C_TRANSACTION_REG_CNT__MASK;
-}
-
-#define REG_HDMI_DDC_DATA 0x00000238
-#define HDMI_DDC_DATA_DATA_RW__MASK 0x00000001
-#define HDMI_DDC_DATA_DATA_RW__SHIFT 0
-static inline uint32_t HDMI_DDC_DATA_DATA_RW(enum hdmi_ddc_read_write val)
-{
- return ((val) << HDMI_DDC_DATA_DATA_RW__SHIFT) & HDMI_DDC_DATA_DATA_RW__MASK;
-}
-#define HDMI_DDC_DATA_DATA__MASK 0x0000ff00
-#define HDMI_DDC_DATA_DATA__SHIFT 8
-static inline uint32_t HDMI_DDC_DATA_DATA(uint32_t val)
-{
- return ((val) << HDMI_DDC_DATA_DATA__SHIFT) & HDMI_DDC_DATA_DATA__MASK;
-}
-#define HDMI_DDC_DATA_INDEX__MASK 0x00ff0000
-#define HDMI_DDC_DATA_INDEX__SHIFT 16
-static inline uint32_t HDMI_DDC_DATA_INDEX(uint32_t val)
-{
- return ((val) << HDMI_DDC_DATA_INDEX__SHIFT) & HDMI_DDC_DATA_INDEX__MASK;
-}
-#define HDMI_DDC_DATA_INDEX_WRITE 0x80000000
-
-#define REG_HDMI_HDCP_SHA_CTRL 0x0000023c
-
-#define REG_HDMI_HDCP_SHA_STATUS 0x00000240
-#define HDMI_HDCP_SHA_STATUS_BLOCK_DONE 0x00000001
-#define HDMI_HDCP_SHA_STATUS_COMP_DONE 0x00000010
-
-#define REG_HDMI_HDCP_SHA_DATA 0x00000244
-#define HDMI_HDCP_SHA_DATA_DONE 0x00000001
-
-#define REG_HDMI_HPD_INT_STATUS 0x00000250
-#define HDMI_HPD_INT_STATUS_INT 0x00000001
-#define HDMI_HPD_INT_STATUS_CABLE_DETECTED 0x00000002
-
-#define REG_HDMI_HPD_INT_CTRL 0x00000254
-#define HDMI_HPD_INT_CTRL_INT_ACK 0x00000001
-#define HDMI_HPD_INT_CTRL_INT_CONNECT 0x00000002
-#define HDMI_HPD_INT_CTRL_INT_EN 0x00000004
-#define HDMI_HPD_INT_CTRL_RX_INT_ACK 0x00000010
-#define HDMI_HPD_INT_CTRL_RX_INT_EN 0x00000020
-#define HDMI_HPD_INT_CTRL_RCV_PLUGIN_DET_MASK 0x00000200
-
-#define REG_HDMI_HPD_CTRL 0x00000258
-#define HDMI_HPD_CTRL_TIMEOUT__MASK 0x00001fff
-#define HDMI_HPD_CTRL_TIMEOUT__SHIFT 0
-static inline uint32_t HDMI_HPD_CTRL_TIMEOUT(uint32_t val)
-{
- return ((val) << HDMI_HPD_CTRL_TIMEOUT__SHIFT) & HDMI_HPD_CTRL_TIMEOUT__MASK;
-}
-#define HDMI_HPD_CTRL_ENABLE 0x10000000
-
-#define REG_HDMI_DDC_REF 0x0000027c
-#define HDMI_DDC_REF_REFTIMER_ENABLE 0x00010000
-#define HDMI_DDC_REF_REFTIMER__MASK 0x0000ffff
-#define HDMI_DDC_REF_REFTIMER__SHIFT 0
-static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
-{
- return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK;
-}
-
-#define REG_HDMI_HDCP_SW_UPPER_AKSV 0x00000284
-
-#define REG_HDMI_HDCP_SW_LOWER_AKSV 0x00000288
-
-#define REG_HDMI_CEC_CTRL 0x0000028c
-
-#define REG_HDMI_CEC_WR_DATA 0x00000290
-
-#define REG_HDMI_CEC_CEC_RETRANSMIT 0x00000294
-
-#define REG_HDMI_CEC_STATUS 0x00000298
-
-#define REG_HDMI_CEC_INT 0x0000029c
-
-#define REG_HDMI_CEC_ADDR 0x000002a0
-
-#define REG_HDMI_CEC_TIME 0x000002a4
-
-#define REG_HDMI_CEC_REFTIMER 0x000002a8
-
-#define REG_HDMI_CEC_RD_DATA 0x000002ac
-
-#define REG_HDMI_CEC_RD_FILTER 0x000002b0
-
-#define REG_HDMI_ACTIVE_HSYNC 0x000002b4
-#define HDMI_ACTIVE_HSYNC_START__MASK 0x00001fff
-#define HDMI_ACTIVE_HSYNC_START__SHIFT 0
-static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val)
-{
- return ((val) << HDMI_ACTIVE_HSYNC_START__SHIFT) & HDMI_ACTIVE_HSYNC_START__MASK;
-}
-#define HDMI_ACTIVE_HSYNC_END__MASK 0x0fff0000
-#define HDMI_ACTIVE_HSYNC_END__SHIFT 16
-static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val)
-{
- return ((val) << HDMI_ACTIVE_HSYNC_END__SHIFT) & HDMI_ACTIVE_HSYNC_END__MASK;
-}
-
-#define REG_HDMI_ACTIVE_VSYNC 0x000002b8
-#define HDMI_ACTIVE_VSYNC_START__MASK 0x00001fff
-#define HDMI_ACTIVE_VSYNC_START__SHIFT 0
-static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val)
-{
- return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK;
-}
-#define HDMI_ACTIVE_VSYNC_END__MASK 0x1fff0000
-#define HDMI_ACTIVE_VSYNC_END__SHIFT 16
-static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val)
-{
- return ((val) << HDMI_ACTIVE_VSYNC_END__SHIFT) & HDMI_ACTIVE_VSYNC_END__MASK;
-}
-
-#define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc
-#define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00001fff
-#define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0
-static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val)
-{
- return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK;
-}
-#define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x1fff0000
-#define HDMI_VSYNC_ACTIVE_F2_END__SHIFT 16
-static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)
-{
- return ((val) << HDMI_VSYNC_ACTIVE_F2_END__SHIFT) & HDMI_VSYNC_ACTIVE_F2_END__MASK;
-}
-
-#define REG_HDMI_TOTAL 0x000002c0
-#define HDMI_TOTAL_H_TOTAL__MASK 0x00001fff
-#define HDMI_TOTAL_H_TOTAL__SHIFT 0
-static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val)
-{
- return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK;
-}
-#define HDMI_TOTAL_V_TOTAL__MASK 0x1fff0000
-#define HDMI_TOTAL_V_TOTAL__SHIFT 16
-static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val)
-{
- return ((val) << HDMI_TOTAL_V_TOTAL__SHIFT) & HDMI_TOTAL_V_TOTAL__MASK;
-}
-
-#define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4
-#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00001fff
-#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0
-static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
-{
- return ((val) << HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT) & HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK;
-}
-
-#define REG_HDMI_FRAME_CTRL 0x000002c8
-#define HDMI_FRAME_CTRL_RGB_MUX_SEL_BGR 0x00001000
-#define HDMI_FRAME_CTRL_VSYNC_LOW 0x10000000
-#define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000
-#define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000
-
-#define REG_HDMI_AUD_INT 0x000002cc
-#define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001
-#define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002
-#define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004
-#define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008
-
-#define REG_HDMI_PHY_CTRL 0x000002d4
-#define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001
-#define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002
-#define HDMI_PHY_CTRL_SW_RESET 0x00000004
-#define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008
-
-#define REG_HDMI_CEC_WR_RANGE 0x000002dc
-
-#define REG_HDMI_CEC_RD_RANGE 0x000002e0
-
-#define REG_HDMI_VERSION 0x000002e4
-
-#define REG_HDMI_CEC_COMPL_CTL 0x00000360
-
-#define REG_HDMI_CEC_RD_START_RANGE 0x00000364
-
-#define REG_HDMI_CEC_RD_TOTAL_RANGE 0x00000368
-
-#define REG_HDMI_CEC_RD_ERR_RESP_LO 0x0000036c
-
-#define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370
-
-#define REG_HDMI_8x60_PHY_REG0 0x00000000
-#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c
-#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT 2
-static inline uint32_t HDMI_8x60_PHY_REG0_DESER_DEL_CTRL(uint32_t val)
-{
- return ((val) << HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__SHIFT) & HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK;
-}
-
-#define REG_HDMI_8x60_PHY_REG1 0x00000004
-#define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK 0x000000f0
-#define HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT 4
-static inline uint32_t HDMI_8x60_PHY_REG1_DTEST_MUX_SEL(uint32_t val)
-{
- return ((val) << HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__SHIFT) & HDMI_8x60_PHY_REG1_DTEST_MUX_SEL__MASK;
-}
-#define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK 0x0000000f
-#define HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT 0
-static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
-{
- return ((val) << HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__SHIFT) & HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL__MASK;
-}
-
-#define REG_HDMI_8x60_PHY_REG2 0x00000008
-#define HDMI_8x60_PHY_REG2_PD_DESER 0x00000001
-#define HDMI_8x60_PHY_REG2_PD_DRIVE_1 0x00000002
-#define HDMI_8x60_PHY_REG2_PD_DRIVE_2 0x00000004
-#define HDMI_8x60_PHY_REG2_PD_DRIVE_3 0x00000008
-#define HDMI_8x60_PHY_REG2_PD_DRIVE_4 0x00000010
-#define HDMI_8x60_PHY_REG2_PD_PLL 0x00000020
-#define HDMI_8x60_PHY_REG2_PD_PWRGEN 0x00000040
-#define HDMI_8x60_PHY_REG2_RCV_SENSE_EN 0x00000080
-
-#define REG_HDMI_8x60_PHY_REG3 0x0000000c
-#define HDMI_8x60_PHY_REG3_PLL_ENABLE 0x00000001
-
-#define REG_HDMI_8x60_PHY_REG4 0x00000010
-
-#define REG_HDMI_8x60_PHY_REG5 0x00000014
-
-#define REG_HDMI_8x60_PHY_REG6 0x00000018
-
-#define REG_HDMI_8x60_PHY_REG7 0x0000001c
-
-#define REG_HDMI_8x60_PHY_REG8 0x00000020
-
-#define REG_HDMI_8x60_PHY_REG9 0x00000024
-
-#define REG_HDMI_8x60_PHY_REG10 0x00000028
-
-#define REG_HDMI_8x60_PHY_REG11 0x0000002c
-
-#define REG_HDMI_8x60_PHY_REG12 0x00000030
-#define HDMI_8x60_PHY_REG12_RETIMING_EN 0x00000001
-#define HDMI_8x60_PHY_REG12_PLL_LOCK_DETECT_EN 0x00000002
-#define HDMI_8x60_PHY_REG12_FORCE_LOCK 0x00000010
-
-#define REG_HDMI_8960_PHY_REG0 0x00000000
-
-#define REG_HDMI_8960_PHY_REG1 0x00000004
-
-#define REG_HDMI_8960_PHY_REG2 0x00000008
-
-#define REG_HDMI_8960_PHY_REG3 0x0000000c
-
-#define REG_HDMI_8960_PHY_REG4 0x00000010
-
-#define REG_HDMI_8960_PHY_REG5 0x00000014
-
-#define REG_HDMI_8960_PHY_REG6 0x00000018
-
-#define REG_HDMI_8960_PHY_REG7 0x0000001c
-
-#define REG_HDMI_8960_PHY_REG8 0x00000020
-
-#define REG_HDMI_8960_PHY_REG9 0x00000024
-
-#define REG_HDMI_8960_PHY_REG10 0x00000028
-
-#define REG_HDMI_8960_PHY_REG11 0x0000002c
-
-#define REG_HDMI_8960_PHY_REG12 0x00000030
-#define HDMI_8960_PHY_REG12_SW_RESET 0x00000020
-#define HDMI_8960_PHY_REG12_PWRDN_B 0x00000080
-
-#define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000034
-
-#define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000038
-
-#define REG_HDMI_8960_PHY_REG_MISC0 0x0000003c
-
-#define REG_HDMI_8960_PHY_REG13 0x00000040
-
-#define REG_HDMI_8960_PHY_REG14 0x00000044
-
-#define REG_HDMI_8960_PHY_REG15 0x00000048
-
-#define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000000
-
-#define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000004
-
-#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000008
-
-#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000000c
-
-#define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000010
-
-#define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000014
-
-#define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000018
-#define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL 0x00000002
-#define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B 0x00000008
-
-#define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000001c
-
-#define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000020
-
-#define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000024
-
-#define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000028
-
-#define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000002c
-
-#define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000030
-
-#define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000034
-
-#define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000038
-
-#define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000003c
-
-#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000040
-
-#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000044
-
-#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000048
-
-#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000004c
-
-#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000050
-
-#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000054
-
-#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000058
-
-#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000005c
-
-#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000060
-
-#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000064
-
-#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000068
-
-#define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000006c
-
-#define REG_HDMI_8960_PHY_PLL_MISC0 0x00000070
-
-#define REG_HDMI_8960_PHY_PLL_MISC1 0x00000074
-
-#define REG_HDMI_8960_PHY_PLL_MISC2 0x00000078
-
-#define REG_HDMI_8960_PHY_PLL_MISC3 0x0000007c
-
-#define REG_HDMI_8960_PHY_PLL_MISC4 0x00000080
-
-#define REG_HDMI_8960_PHY_PLL_MISC5 0x00000084
-
-#define REG_HDMI_8960_PHY_PLL_MISC6 0x00000088
-
-#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000008c
-
-#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000090
-
-#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000094
-
-#define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000098
-#define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK 0x00000001
-
-#define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000009c
-
-#define REG_HDMI_8x74_ANA_CFG0 0x00000000
-
-#define REG_HDMI_8x74_ANA_CFG1 0x00000004
-
-#define REG_HDMI_8x74_ANA_CFG2 0x00000008
-
-#define REG_HDMI_8x74_ANA_CFG3 0x0000000c
-
-#define REG_HDMI_8x74_PD_CTRL0 0x00000010
-
-#define REG_HDMI_8x74_PD_CTRL1 0x00000014
-
-#define REG_HDMI_8x74_GLB_CFG 0x00000018
-
-#define REG_HDMI_8x74_DCC_CFG0 0x0000001c
-
-#define REG_HDMI_8x74_DCC_CFG1 0x00000020
-
-#define REG_HDMI_8x74_TXCAL_CFG0 0x00000024
-
-#define REG_HDMI_8x74_TXCAL_CFG1 0x00000028
-
-#define REG_HDMI_8x74_TXCAL_CFG2 0x0000002c
-
-#define REG_HDMI_8x74_TXCAL_CFG3 0x00000030
-
-#define REG_HDMI_8x74_BIST_CFG0 0x00000034
-
-#define REG_HDMI_8x74_BIST_PATN0 0x0000003c
-
-#define REG_HDMI_8x74_BIST_PATN1 0x00000040
-
-#define REG_HDMI_8x74_BIST_PATN2 0x00000044
-
-#define REG_HDMI_8x74_BIST_PATN3 0x00000048
-
-#define REG_HDMI_8x74_STATUS 0x0000005c
-
-#define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
-
-#define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
-
-#define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
-
-#define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
-
-#define REG_HDMI_28nm_PHY_PLL_VREG_CFG 0x00000010
-
-#define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
-
-#define REG_HDMI_28nm_PHY_PLL_DMUX_CFG 0x00000018
-
-#define REG_HDMI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
-
-#define REG_HDMI_28nm_PHY_PLL_GLB_CFG 0x00000020
-#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
-#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
-#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
-#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
-
-#define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
-
-#define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
-
-#define REG_HDMI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
-
-#define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
-
-#define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
-
-#define REG_HDMI_28nm_PHY_PLL_SDM_CFG0 0x00000038
-
-#define REG_HDMI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
-
-#define REG_HDMI_28nm_PHY_PLL_SDM_CFG2 0x00000040
-
-#define REG_HDMI_28nm_PHY_PLL_SDM_CFG3 0x00000044
-
-#define REG_HDMI_28nm_PHY_PLL_SDM_CFG4 0x00000048
-
-#define REG_HDMI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
-
-#define REG_HDMI_28nm_PHY_PLL_SSC_CFG1 0x00000050
-
-#define REG_HDMI_28nm_PHY_PLL_SSC_CFG2 0x00000054
-
-#define REG_HDMI_28nm_PHY_PLL_SSC_CFG3 0x00000058
-
-#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
-
-#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
-
-#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
-
-#define REG_HDMI_28nm_PHY_PLL_TEST_CFG 0x00000068
-#define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
-
-#define REG_HDMI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
-
-#define REG_HDMI_28nm_PHY_PLL_CAL_CFG1 0x00000070
-
-#define REG_HDMI_28nm_PHY_PLL_CAL_CFG2 0x00000074
-
-#define REG_HDMI_28nm_PHY_PLL_CAL_CFG3 0x00000078
-
-#define REG_HDMI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
-
-#define REG_HDMI_28nm_PHY_PLL_CAL_CFG5 0x00000080
-
-#define REG_HDMI_28nm_PHY_PLL_CAL_CFG6 0x00000084
-
-#define REG_HDMI_28nm_PHY_PLL_CAL_CFG7 0x00000088
-
-#define REG_HDMI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
-
-#define REG_HDMI_28nm_PHY_PLL_CAL_CFG9 0x00000090
-
-#define REG_HDMI_28nm_PHY_PLL_CAL_CFG10 0x00000094
-
-#define REG_HDMI_28nm_PHY_PLL_CAL_CFG11 0x00000098
-
-#define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
-
-#define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
-
-#define REG_HDMI_28nm_PHY_PLL_STATUS 0x000000c0
-
-#define REG_HDMI_8996_PHY_CFG 0x00000000
-
-#define REG_HDMI_8996_PHY_PD_CTL 0x00000004
-
-#define REG_HDMI_8996_PHY_MODE 0x00000008
-
-#define REG_HDMI_8996_PHY_MISR_CLEAR 0x0000000c
-
-#define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG0 0x00000010
-
-#define REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG1 0x00000014
-
-#define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE0 0x00000018
-
-#define REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE1 0x0000001c
-
-#define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN0 0x00000020
-
-#define REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN1 0x00000024
-
-#define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG0 0x00000028
-
-#define REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG1 0x0000002c
-
-#define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE0 0x00000030
-
-#define REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE1 0x00000034
-
-#define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN0 0x00000038
-
-#define REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN1 0x0000003c
-
-#define REG_HDMI_8996_PHY_DEBUG_BUS_SEL 0x00000040
-
-#define REG_HDMI_8996_PHY_TXCAL_CFG0 0x00000044
-
-#define REG_HDMI_8996_PHY_TXCAL_CFG1 0x00000048
-
-#define REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL 0x0000004c
-
-#define REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL 0x00000050
-
-#define REG_HDMI_8996_PHY_LANE_BIST_CONFIG 0x00000054
-
-#define REG_HDMI_8996_PHY_CLOCK 0x00000058
-
-#define REG_HDMI_8996_PHY_MISC1 0x0000005c
-
-#define REG_HDMI_8996_PHY_MISC2 0x00000060
-
-#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS0 0x00000064
-
-#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS1 0x00000068
-
-#define REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS2 0x0000006c
-
-#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS0 0x00000070
-
-#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS1 0x00000074
-
-#define REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS2 0x00000078
-
-#define REG_HDMI_8996_PHY_PRE_MISR_STATUS0 0x0000007c
-
-#define REG_HDMI_8996_PHY_PRE_MISR_STATUS1 0x00000080
-
-#define REG_HDMI_8996_PHY_PRE_MISR_STATUS2 0x00000084
-
-#define REG_HDMI_8996_PHY_PRE_MISR_STATUS3 0x00000088
-
-#define REG_HDMI_8996_PHY_POST_MISR_STATUS0 0x0000008c
-
-#define REG_HDMI_8996_PHY_POST_MISR_STATUS1 0x00000090
-
-#define REG_HDMI_8996_PHY_POST_MISR_STATUS2 0x00000094
-
-#define REG_HDMI_8996_PHY_POST_MISR_STATUS3 0x00000098
-
-#define REG_HDMI_8996_PHY_STATUS 0x0000009c
-
-#define REG_HDMI_8996_PHY_MISC3_STATUS 0x000000a0
-
-#define REG_HDMI_8996_PHY_MISC4_STATUS 0x000000a4
-
-#define REG_HDMI_8996_PHY_DEBUG_BUS0 0x000000a8
-
-#define REG_HDMI_8996_PHY_DEBUG_BUS1 0x000000ac
-
-#define REG_HDMI_8996_PHY_DEBUG_BUS2 0x000000b0
-
-#define REG_HDMI_8996_PHY_DEBUG_BUS3 0x000000b4
-
-#define REG_HDMI_8996_PHY_PHY_REVISION_ID0 0x000000b8
-
-#define REG_HDMI_8996_PHY_PHY_REVISION_ID1 0x000000bc
-
-#define REG_HDMI_8996_PHY_PHY_REVISION_ID2 0x000000c0
-
-#define REG_HDMI_8996_PHY_PHY_REVISION_ID3 0x000000c4
-
-#define REG_HDMI_PHY_QSERDES_COM_ATB_SEL1 0x00000000
-
-#define REG_HDMI_PHY_QSERDES_COM_ATB_SEL2 0x00000004
-
-#define REG_HDMI_PHY_QSERDES_COM_FREQ_UPDATE 0x00000008
-
-#define REG_HDMI_PHY_QSERDES_COM_BG_TIMER 0x0000000c
-
-#define REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER 0x00000010
-
-#define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER1 0x00000014
-
-#define REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER2 0x00000018
-
-#define REG_HDMI_PHY_QSERDES_COM_SSC_PER1 0x0000001c
-
-#define REG_HDMI_PHY_QSERDES_COM_SSC_PER2 0x00000020
-
-#define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1 0x00000024
-
-#define REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2 0x00000028
-
-#define REG_HDMI_PHY_QSERDES_COM_POST_DIV 0x0000002c
-
-#define REG_HDMI_PHY_QSERDES_COM_POST_DIV_MUX 0x00000030
-
-#define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x00000034
-
-#define REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1 0x00000038
-
-#define REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL 0x0000003c
-
-#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE 0x00000040
-
-#define REG_HDMI_PHY_QSERDES_COM_PLL_EN 0x00000044
-
-#define REG_HDMI_PHY_QSERDES_COM_PLL_IVCO 0x00000048
-
-#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x0000004c
-
-#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x00000050
-
-#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00000054
-
-#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE1 0x00000058
-
-#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE1 0x0000005c
-
-#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE1 0x00000060
-
-#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE2 0x00000064
-
-#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD0 0x00000064
-
-#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE2 0x00000068
-
-#define REG_HDMI_PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x00000068
-
-#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE2 0x0000006c
-
-#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x0000006c
-
-#define REG_HDMI_PHY_QSERDES_COM_BG_TRIM 0x00000070
-
-#define REG_HDMI_PHY_QSERDES_COM_CLK_EP_DIV 0x00000074
-
-#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0 0x00000078
-
-#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE1 0x0000007c
-
-#define REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE2 0x00000080
-
-#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD1 0x00000080
-
-#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x00000084
-
-#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE1 0x00000088
-
-#define REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE2 0x0000008c
-
-#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD2 0x0000008c
-
-#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x00000090
-
-#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE1 0x00000094
-
-#define REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE2 0x00000098
-
-#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD3 0x00000098
-
-#define REG_HDMI_PHY_QSERDES_COM_PLL_CNTRL 0x0000009c
-
-#define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_CTRL 0x000000a0
-
-#define REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_DC 0x000000a4
-
-#define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_IN_SYNC_SEL 0x000000a8
-
-#define REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x000000a8
-
-#define REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL 0x000000ac
-
-#define REG_HDMI_PHY_QSERDES_COM_CML_SYSCLK_SEL 0x000000b0
-
-#define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL 0x000000b4
-
-#define REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL2 0x000000b8
-
-#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL 0x000000bc
-
-#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL2 0x000000c0
-
-#define REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM 0x000000c4
-
-#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN 0x000000c8
-
-#define REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_CFG 0x000000cc
-
-#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0 0x000000d0
-
-#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE1 0x000000d4
-
-#define REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE2 0x000000d8
-
-#define REG_HDMI_PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x000000d8
-
-#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x000000dc
-
-#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x000000e0
-
-#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x000000e4
-
-#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE1 0x000000e8
-
-#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE1 0x000000ec
-
-#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE1 0x000000f0
-
-#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE2 0x000000f4
-
-#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL1 0x000000f4
-
-#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE2 0x000000f8
-
-#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL2 0x000000f8
-
-#define REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE2 0x000000fc
-
-#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD4 0x000000fc
-
-#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x00000100
-
-#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_EN 0x00000104
-
-#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00000108
-
-#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x0000010c
-
-#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00000110
-
-#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00000114
-
-#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE2 0x00000118
-
-#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL1 0x00000118
-
-#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE2 0x0000011c
-
-#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL2 0x0000011c
-
-#define REG_HDMI_PHY_QSERDES_COM_RES_TRIM_CONTROL2 0x00000120
-
-#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL 0x00000124
-
-#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP 0x00000128
-
-#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE0 0x0000012c
-
-#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE0 0x00000130
-
-#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE1 0x00000134
-
-#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE1 0x00000138
-
-#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE2 0x0000013c
-
-#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL1 0x0000013c
-
-#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE2 0x00000140
-
-#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL2 0x00000140
-
-#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER1 0x00000144
-
-#define REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER2 0x00000148
-
-#define REG_HDMI_PHY_QSERDES_COM_SAR 0x0000014c
-
-#define REG_HDMI_PHY_QSERDES_COM_SAR_CLK 0x00000150
-
-#define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_OUT_STATUS 0x00000154
-
-#define REG_HDMI_PHY_QSERDES_COM_SAR_CODE_READY_STATUS 0x00000158
-
-#define REG_HDMI_PHY_QSERDES_COM_CMN_STATUS 0x0000015c
-
-#define REG_HDMI_PHY_QSERDES_COM_RESET_SM_STATUS 0x00000160
-
-#define REG_HDMI_PHY_QSERDES_COM_RESTRIM_CODE_STATUS 0x00000164
-
-#define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE1_STATUS 0x00000168
-
-#define REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE2_STATUS 0x0000016c
-
-#define REG_HDMI_PHY_QSERDES_COM_BG_CTRL 0x00000170
-
-#define REG_HDMI_PHY_QSERDES_COM_CLK_SELECT 0x00000174
-
-#define REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL 0x00000178
-
-#define REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x0000017c
-
-#define REG_HDMI_PHY_QSERDES_COM_PLL_ANALOG 0x00000180
-
-#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV 0x00000184
-
-#define REG_HDMI_PHY_QSERDES_COM_SW_RESET 0x00000188
-
-#define REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN 0x0000018c
-
-#define REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS 0x00000190
-
-#define REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG 0x00000194
-
-#define REG_HDMI_PHY_QSERDES_COM_CMN_RATE_OVERRIDE 0x00000198
-
-#define REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x0000019c
-
-#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS0 0x000001a0
-
-#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS1 0x000001a4
-
-#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS2 0x000001a8
-
-#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS3 0x000001ac
-
-#define REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS_SEL 0x000001b0
-
-#define REG_HDMI_PHY_QSERDES_COM_CMN_MISC1 0x000001b4
-
-#define REG_HDMI_PHY_QSERDES_COM_CMN_MISC2 0x000001b8
-
-#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE1 0x000001bc
-
-#define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE2 0x000001c0
-
-#define REG_HDMI_PHY_QSERDES_COM_CMN_RSVD5 0x000001c4
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_MODE_LANENO 0x00000000
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_INVERT 0x00000004
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE 0x00000008
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_ONE 0x0000000c
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_TWO 0x00000010
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_THREE 0x00000014
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL 0x00000018
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_TX_POST2_EMPH 0x0000001c
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_TX_BOOST_LVL_UP_DN 0x00000020
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES 0x00000024
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_TX_IDLE_LVL_LARGE_AMP 0x00000028
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL 0x0000002c
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET 0x00000030
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN 0x00000034
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PRE_STALL_LDO_BOOST_EN 0x00000038
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND 0x0000003c
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_SLEW_CNTL 0x00000040
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_INTERFACE_SELECT 0x00000044
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_LPB_EN 0x00000048
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_TX 0x0000004c
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_RX 0x00000050
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET 0x00000054
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH1 0x00000058
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH2 0x0000005c
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_SERDES_BYP_EN_OUT 0x00000060
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_DEBUG_BUS_SEL 0x00000064
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x00000068
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_TX_POL_INV 0x0000006c
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN 0x00000070
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN1 0x00000074
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN2 0x00000078
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN3 0x0000007c
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN4 0x00000080
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN5 0x00000084
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN6 0x00000088
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN7 0x0000008c
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN8 0x00000090
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE 0x00000094
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE 0x00000098
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE_CONFIGURATION 0x0000009c
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL1 0x000000a0
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL2 0x000000a4
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL 0x000000a8
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL_2 0x000000ac
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED1 0x000000b0
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED2 0x000000b4
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED3 0x000000b8
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED4 0x000000bc
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN 0x000000c0
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN_MUXES 0x000000c4
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN 0x000000c8
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_TX_INTERFACE_MODE 0x000000cc
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_CTRL 0x000000d0
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_ENCODED_OR_DATA 0x000000d4
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND2 0x000000d8
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND2 0x000000dc
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND2 0x000000e0
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND2 0x000000e4
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND0_1 0x000000e8
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND0_1 0x000000ec
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND0_1 0x000000f0
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND0_1 0x000000f4
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1 0x000000f8
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2 0x000000fc
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV_CNTL 0x00000100
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_STATUS 0x00000104
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT1 0x00000108
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT2 0x0000010c
-
-#define REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV 0x00000110
-
-
-#endif /* HDMI_XML */
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
index 4dd055416620..8c8d80b59573 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
@@ -86,18 +86,18 @@ static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll)
static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset,
u32 data)
{
- msm_writel(data, pll->mmio_qserdes_com + offset);
+ writel(data, pll->mmio_qserdes_com + offset);
}
static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset)
{
- return msm_readl(pll->mmio_qserdes_com + offset);
+ return readl(pll->mmio_qserdes_com + offset);
}
static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel,
int offset, int data)
{
- msm_writel(data, pll->mmio_qserdes_tx[channel] + offset);
+ writel(data, pll->mmio_qserdes_tx[channel] + offset);
}
static inline u32 pll_get_cpctrl(u64 frac_start, unsigned long ref_clk,
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c b/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
index cb35a297afbd..83c8781fcc3f 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
@@ -236,12 +236,12 @@ static const struct pll_rate freqtbl[] = {
static inline void pll_write(struct hdmi_pll_8960 *pll, u32 reg, u32 data)
{
- msm_writel(data, pll->mmio + reg);
+ writel(data, pll->mmio + reg);
}
static inline u32 pll_read(struct hdmi_pll_8960 *pll, u32 reg)
{
- return msm_readl(pll->mmio + reg);
+ return readl(pll->mmio + reg);
}
static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8960 *pll)
diff --git a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
deleted file mode 100644
index 498801526695..000000000000
--- a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef QFPROM_XML
-#define QFPROM_XML
-
-/* Autogenerated file, DO NOT EDIT manually!
-
-This file was generated by the rules-ng-ng headergen tool in this git repository:
-http://github.com/freedreno/envytools/
-git clone https://github.com/freedreno/envytools.git
-
-The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml ( 944 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml ( 20912 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml ( 2849 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml ( 37461 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml ( 18746 bytes, from 2022-04-28 17:29:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml ( 3236 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml ( 4935 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml ( 7004 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml ( 3712 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml ( 5381 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml ( 4499 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml ( 11007 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml ( 602 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml ( 1686 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml ( 600 bytes, from 2022-03-08 17:40:42)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml ( 42350 bytes, from 2022-09-20 17:45:56)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml ( 10416 bytes, from 2022-03-08 17:40:42)
-
-Copyright (C) 2013-2022 by the following authors:
-- Rob Clark <robdclark@gmail.com> (robclark)
-- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice (including the
-next paragraph) shall be included in all copies or substantial
-portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
-LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
-OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
-WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-*/
-
-
-#define REG_QFPROM_CONFIG_ROW0_LSB 0x00000238
-#define QFPROM_CONFIG_ROW0_LSB_HDMI_DISABLE 0x00200000
-#define QFPROM_CONFIG_ROW0_LSB_HDCP_DISABLE 0x00400000
-
-
-#endif /* QFPROM_XML */
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 97790faffd23..9c33f4e3f822 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -17,8 +17,9 @@
#include "msm_drv.h"
#include "msm_debugfs.h"
+#include "msm_gem.h"
+#include "msm_gpu.h"
#include "msm_kms.h"
-#include "adreno/adreno_gpu.h"
/*
* MSM driver version:
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 65f213660452..912ebaa5df84 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -239,9 +239,7 @@ struct msm_drm_private {
bool disable_err_irq;
};
-struct msm_format {
- uint32_t pixel_format;
-};
+const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier);
struct msm_pending_timer;
@@ -488,15 +486,12 @@ void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev,
struct icc_path *msm_icc_get(struct device *dev, const char *name);
-#define msm_writel(data, addr) writel((data), (addr))
-#define msm_readl(addr) readl((addr))
-
static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or)
{
- u32 val = msm_readl(addr);
+ u32 val = readl(addr);
val &= ~mask;
- msm_writel(val | or, addr);
+ writel(val | or, addr);
}
/**
diff --git a/drivers/gpu/drm/msm/msm_fb.c b/drivers/gpu/drm/msm/msm_fb.c
index 80166f702a0d..09268e416843 100644
--- a/drivers/gpu/drm/msm/msm_fb.c
+++ b/drivers/gpu/drm/msm/msm_fb.c
@@ -176,16 +176,16 @@ static struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
const struct msm_format *format;
int ret, i, n;
- drm_dbg_state(dev, "create framebuffer: mode_cmd=%p (%dx%d@%4.4s)\n",
- mode_cmd, mode_cmd->width, mode_cmd->height,
- (char *)&mode_cmd->pixel_format);
+ drm_dbg_state(dev, "create framebuffer: mode_cmd=%p (%dx%d@%p4cc)\n",
+ mode_cmd, mode_cmd->width, mode_cmd->height,
+ &mode_cmd->pixel_format);
n = info->num_planes;
- format = kms->funcs->get_format(kms, mode_cmd->pixel_format,
+ format = mdp_get_format(kms, mode_cmd->pixel_format,
mode_cmd->modifier[0]);
if (!format) {
- DRM_DEV_ERROR(dev->dev, "unsupported pixel format: %4.4s\n",
- (char *)&mode_cmd->pixel_format);
+ DRM_DEV_ERROR(dev->dev, "unsupported pixel format: %p4cc\n",
+ &mode_cmd->pixel_format);
ret = -EINVAL;
goto fail;
}
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 655002b21b0d..cd185b9636d2 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -11,7 +11,7 @@
#include "msm_mmu.h"
#include "msm_fence.h"
#include "msm_gpu_trace.h"
-#include "adreno/adreno_gpu.h"
+//#include "adreno/adreno_gpu.h"
#include <generated/utsrelease.h>
#include <linux/string_helpers.h>
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 2bfcb222e353..a0c1bd6d1d5b 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -555,12 +555,12 @@ struct msm_gpu_state {
static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
{
- msm_writel(data, gpu->mmio + (reg << 2));
+ writel(data, gpu->mmio + (reg << 2));
}
static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
{
- return msm_readl(gpu->mmio + (reg << 2));
+ return readl(gpu->mmio + (reg << 2));
}
static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
@@ -586,8 +586,8 @@ static inline u64 gpu_read64(struct msm_gpu *gpu, u32 reg)
* when the lo is read, so make sure to read the lo first to trigger
* that
*/
- val = (u64) msm_readl(gpu->mmio + (reg << 2));
- val |= ((u64) msm_readl(gpu->mmio + ((reg + 1) << 2)) << 32);
+ val = (u64) readl(gpu->mmio + (reg << 2));
+ val |= ((u64) readl(gpu->mmio + ((reg + 1) << 2)) << 32);
return val;
}
@@ -595,8 +595,8 @@ static inline u64 gpu_read64(struct msm_gpu *gpu, u32 reg)
static inline void gpu_write64(struct msm_gpu *gpu, u32 reg, u64 val)
{
/* Why not a writeq here? Read the screed above */
- msm_writel(lower_32_bits(val), gpu->mmio + (reg << 2));
- msm_writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2));
+ writel(lower_32_bits(val), gpu->mmio + (reg << 2));
+ writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2));
}
int msm_gpu_pm_suspend(struct msm_gpu *gpu);
diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h
index 0641f6111b93..1e0c54de3716 100644
--- a/drivers/gpu/drm/msm/msm_kms.h
+++ b/drivers/gpu/drm/msm/msm_kms.h
@@ -92,10 +92,6 @@ struct msm_kms_funcs {
* Format handling:
*/
- /* get msm_format w/ optional format modifiers from drm_mode_fb_cmd2 */
- const struct msm_format *(*get_format)(struct msm_kms *kms,
- const uint32_t format,
- const uint64_t modifiers);
/* do format checking on format modified through fb_cmd2 modifiers */
int (*check_modified_format)(const struct msm_kms *kms,
const struct msm_format *msm_fmt,
diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h
index eb72d3645c1d..88af4f490881 100644
--- a/drivers/gpu/drm/msm/msm_mmu.h
+++ b/drivers/gpu/drm/msm/msm_mmu.h
@@ -42,7 +42,6 @@ static inline void msm_mmu_init(struct msm_mmu *mmu, struct device *dev,
struct msm_mmu *msm_iommu_new(struct device *dev, unsigned long quirks);
struct msm_mmu *msm_iommu_gpu_new(struct device *dev, struct msm_gpu *gpu, unsigned long quirks);
-struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu);
static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg,
int (*handler)(void *arg, unsigned long iova, int flags, void *data))
@@ -53,10 +52,6 @@ static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg,
struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent);
-void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base,
- dma_addr_t *tran_error);
-
-
int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr,
int *asid);
struct iommu_domain_geometry *msm_iommu_get_geometry(struct msm_mmu *mmu);
diff --git a/drivers/gpu/drm/msm/registers/.gitignore b/drivers/gpu/drm/msm/registers/.gitignore
new file mode 100644
index 000000000000..848e0e3efbcb
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/.gitignore
@@ -0,0 +1,4 @@
+# ignore XML files present at Mesa but not used by the kernel
+adreno/adreno_control_regs.xml
+adreno/adreno_pipe_regs.xml
+adreno/ocmem.xml
diff --git a/drivers/gpu/drm/msm/registers/adreno/a2xx.xml b/drivers/gpu/drm/msm/registers/adreno/a2xx.xml
new file mode 100644
index 000000000000..22caddaa0db9
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/adreno/a2xx.xml
@@ -0,0 +1,1865 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+<import file="adreno/adreno_common.xml"/>
+<import file="adreno/adreno_pm4.xml"/>
+
+
+<enum name="a2xx_rb_dither_type">
+ <value name="DITHER_PIXEL" value="0"/>
+ <value name="DITHER_SUBPIXEL" value="1"/>
+</enum>
+
+<enum name="a2xx_colorformatx">
+ <value name="COLORX_4_4_4_4" value="0"/>
+ <value name="COLORX_1_5_5_5" value="1"/>
+ <value name="COLORX_5_6_5" value="2"/>
+ <value name="COLORX_8" value="3"/>
+ <value name="COLORX_8_8" value="4"/>
+ <value name="COLORX_8_8_8_8" value="5"/>
+ <value name="COLORX_S8_8_8_8" value="6"/>
+ <value name="COLORX_16_FLOAT" value="7"/>
+ <value name="COLORX_16_16_FLOAT" value="8"/>
+ <value name="COLORX_16_16_16_16_FLOAT" value="9"/>
+ <value name="COLORX_32_FLOAT" value="10"/>
+ <value name="COLORX_32_32_FLOAT" value="11"/>
+ <value name="COLORX_32_32_32_32_FLOAT" value="12"/>
+ <value name="COLORX_2_3_3" value="13"/>
+ <value name="COLORX_8_8_8" value="14"/>
+</enum>
+
+<enum name="a2xx_sq_surfaceformat">
+ <value name="FMT_1_REVERSE" value="0"/>
+ <value name="FMT_1" value="1"/>
+ <value name="FMT_8" value="2"/>
+ <value name="FMT_1_5_5_5" value="3"/>
+ <value name="FMT_5_6_5" value="4"/>
+ <value name="FMT_6_5_5" value="5"/>
+ <value name="FMT_8_8_8_8" value="6"/>
+ <value name="FMT_2_10_10_10" value="7"/>
+ <value name="FMT_8_A" value="8"/>
+ <value name="FMT_8_B" value="9"/>
+ <value name="FMT_8_8" value="10"/>
+ <value name="FMT_Cr_Y1_Cb_Y0" value="11"/>
+ <value name="FMT_Y1_Cr_Y0_Cb" value="12"/>
+ <value name="FMT_5_5_5_1" value="13"/>
+ <value name="FMT_8_8_8_8_A" value="14"/>
+ <value name="FMT_4_4_4_4" value="15"/>
+ <value name="FMT_8_8_8" value="16"/>
+ <value name="FMT_DXT1" value="18"/>
+ <value name="FMT_DXT2_3" value="19"/>
+ <value name="FMT_DXT4_5" value="20"/>
+ <value name="FMT_10_10_10_2" value="21"/>
+ <value name="FMT_24_8" value="22"/>
+ <value name="FMT_16" value="24"/>
+ <value name="FMT_16_16" value="25"/>
+ <value name="FMT_16_16_16_16" value="26"/>
+ <value name="FMT_16_EXPAND" value="27"/>
+ <value name="FMT_16_16_EXPAND" value="28"/>
+ <value name="FMT_16_16_16_16_EXPAND" value="29"/>
+ <value name="FMT_16_FLOAT" value="30"/>
+ <value name="FMT_16_16_FLOAT" value="31"/>
+ <value name="FMT_16_16_16_16_FLOAT" value="32"/>
+ <value name="FMT_32" value="33"/>
+ <value name="FMT_32_32" value="34"/>
+ <value name="FMT_32_32_32_32" value="35"/>
+ <value name="FMT_32_FLOAT" value="36"/>
+ <value name="FMT_32_32_FLOAT" value="37"/>
+ <value name="FMT_32_32_32_32_FLOAT" value="38"/>
+ <value name="FMT_ATI_TC_RGB" value="39"/>
+ <value name="FMT_ATI_TC_RGBA" value="40"/>
+ <value name="FMT_ATI_TC_555_565_RGB" value="41"/>
+ <value name="FMT_ATI_TC_555_565_RGBA" value="42"/>
+ <value name="FMT_ATI_TC_RGBA_INTERP" value="43"/>
+ <value name="FMT_ATI_TC_555_565_RGBA_INTERP" value="44"/>
+ <value name="FMT_ETC1_RGBA_INTERP" value="46"/>
+ <value name="FMT_ETC1_RGB" value="47"/>
+ <value name="FMT_ETC1_RGBA" value="48"/>
+ <value name="FMT_DXN" value="49"/>
+ <value name="FMT_2_3_3" value="51"/>
+ <value name="FMT_2_10_10_10_AS_16_16_16_16" value="54"/>
+ <value name="FMT_10_10_10_2_AS_16_16_16_16" value="55"/>
+ <value name="FMT_32_32_32_FLOAT" value="57"/>
+ <value name="FMT_DXT3A" value="58"/>
+ <value name="FMT_DXT5A" value="59"/>
+ <value name="FMT_CTX1" value="60"/>
+</enum>
+
+<enum name="a2xx_sq_ps_vtx_mode">
+ <value name="POSITION_1_VECTOR" value="0"/>
+ <value name="POSITION_2_VECTORS_UNUSED" value="1"/>
+ <value name="POSITION_2_VECTORS_SPRITE" value="2"/>
+ <value name="POSITION_2_VECTORS_EDGE" value="3"/>
+ <value name="POSITION_2_VECTORS_KILL" value="4"/>
+ <value name="POSITION_2_VECTORS_SPRITE_KILL" value="5"/>
+ <value name="POSITION_2_VECTORS_EDGE_KILL" value="6"/>
+ <value name="MULTIPASS" value="7"/>
+</enum>
+
+<enum name="a2xx_sq_sample_cntl">
+ <value name="CENTROIDS_ONLY" value="0"/>
+ <value name="CENTERS_ONLY" value="1"/>
+ <value name="CENTROIDS_AND_CENTERS" value="2"/>
+</enum>
+
+<enum name="a2xx_dx_clip_space">
+ <value name="DXCLIP_OPENGL" value="0"/>
+ <value name="DXCLIP_DIRECTX" value="1"/>
+</enum>
+
+<enum name="a2xx_pa_su_sc_polymode">
+ <value name="POLY_DISABLED" value="0"/>
+ <value name="POLY_DUALMODE" value="1"/>
+</enum>
+
+<enum name="a2xx_rb_edram_mode">
+ <value name="EDRAM_NOP" value="0"/>
+ <value name="COLOR_DEPTH" value="4"/>
+ <value name="DEPTH_ONLY" value="5"/>
+ <value name="EDRAM_COPY" value="6"/>
+</enum>
+
+<enum name="a2xx_pa_sc_pattern_bit_order">
+ <value name="LITTLE" value="0"/>
+ <value name="BIG" value="1"/>
+</enum>
+
+<enum name="a2xx_pa_sc_auto_reset_cntl">
+ <value name="NEVER" value="0"/>
+ <value name="EACH_PRIMITIVE" value="1"/>
+ <value name="EACH_PACKET" value="2"/>
+</enum>
+
+<enum name="a2xx_pa_pixcenter">
+ <value name="PIXCENTER_D3D" value="0"/>
+ <value name="PIXCENTER_OGL" value="1"/>
+</enum>
+
+<enum name="a2xx_pa_roundmode">
+ <value name="TRUNCATE" value="0"/>
+ <value name="ROUND" value="1"/>
+ <value name="ROUNDTOEVEN" value="2"/>
+ <value name="ROUNDTOODD" value="3"/>
+</enum>
+
+<enum name="a2xx_pa_quantmode">
+ <value name="ONE_SIXTEENTH" value="0"/>
+ <value name="ONE_EIGTH" value="1"/>
+ <value name="ONE_QUARTER" value="2"/>
+ <value name="ONE_HALF" value="3"/>
+ <value name="ONE" value="4"/>
+</enum>
+
+<enum name="a2xx_rb_copy_sample_select">
+ <value name="SAMPLE_0" value="0"/>
+ <value name="SAMPLE_1" value="1"/>
+ <value name="SAMPLE_2" value="2"/>
+ <value name="SAMPLE_3" value="3"/>
+ <value name="SAMPLE_01" value="4"/>
+ <value name="SAMPLE_23" value="5"/>
+ <value name="SAMPLE_0123" value="6"/>
+</enum>
+
+<enum name="a2xx_rb_blend_opcode">
+ <value name="BLEND2_DST_PLUS_SRC" value="0"/>
+ <value name="BLEND2_SRC_MINUS_DST" value="1"/>
+ <value name="BLEND2_MIN_DST_SRC" value="2"/>
+ <value name="BLEND2_MAX_DST_SRC" value="3"/>
+ <value name="BLEND2_DST_MINUS_SRC" value="4"/>
+ <value name="BLEND2_DST_PLUS_SRC_BIAS" value="5"/>
+</enum>
+
+<enum name="a2xx_su_perfcnt_select">
+ <value value="0" name="PERF_PAPC_PASX_REQ"/>
+ <value value="2" name="PERF_PAPC_PASX_FIRST_VECTOR"/>
+ <value value="3" name="PERF_PAPC_PASX_SECOND_VECTOR"/>
+ <value value="4" name="PERF_PAPC_PASX_FIRST_DEAD"/>
+ <value value="5" name="PERF_PAPC_PASX_SECOND_DEAD"/>
+ <value value="6" name="PERF_PAPC_PASX_VTX_KILL_DISCARD"/>
+ <value value="7" name="PERF_PAPC_PASX_VTX_NAN_DISCARD"/>
+ <value value="8" name="PERF_PAPC_PA_INPUT_PRIM"/>
+ <value value="9" name="PERF_PAPC_PA_INPUT_NULL_PRIM"/>
+ <value value="10" name="PERF_PAPC_PA_INPUT_EVENT_FLAG"/>
+ <value value="11" name="PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT"/>
+ <value value="12" name="PERF_PAPC_PA_INPUT_END_OF_PACKET"/>
+ <value value="13" name="PERF_PAPC_CLPR_CULL_PRIM"/>
+ <value value="15" name="PERF_PAPC_CLPR_VV_CULL_PRIM"/>
+ <value value="17" name="PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM"/>
+ <value value="18" name="PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM"/>
+ <value value="19" name="PERF_PAPC_CLPR_CULL_TO_NULL_PRIM"/>
+ <value value="21" name="PERF_PAPC_CLPR_VV_CLIP_PRIM"/>
+ <value value="23" name="PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE"/>
+ <value value="24" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_1"/>
+ <value value="25" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_2"/>
+ <value value="26" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_3"/>
+ <value value="27" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_4"/>
+ <value value="28" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_5"/>
+ <value value="29" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_6"/>
+ <value value="30" name="PERF_PAPC_CLPR_CLIP_PLANE_NEAR"/>
+ <value value="31" name="PERF_PAPC_CLPR_CLIP_PLANE_FAR"/>
+ <value value="32" name="PERF_PAPC_CLPR_CLIP_PLANE_LEFT"/>
+ <value value="33" name="PERF_PAPC_CLPR_CLIP_PLANE_RIGHT"/>
+ <value value="34" name="PERF_PAPC_CLPR_CLIP_PLANE_TOP"/>
+ <value value="35" name="PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM"/>
+ <value value="36" name="PERF_PAPC_CLSM_NULL_PRIM"/>
+ <value value="37" name="PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM"/>
+ <value value="38" name="PERF_PAPC_CLSM_CLIP_PRIM"/>
+ <value value="39" name="PERF_PAPC_CLSM_CULL_TO_NULL_PRIM"/>
+ <value value="40" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_1"/>
+ <value value="41" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_2"/>
+ <value value="42" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_3"/>
+ <value value="43" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_4"/>
+ <value value="44" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_5"/>
+ <value value="45" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7"/>
+ <value value="46" name="PERF_PAPC_CLSM_NON_TRIVIAL_CULL"/>
+ <value value="47" name="PERF_PAPC_SU_INPUT_PRIM"/>
+ <value value="48" name="PERF_PAPC_SU_INPUT_CLIP_PRIM"/>
+ <value value="49" name="PERF_PAPC_SU_INPUT_NULL_PRIM"/>
+ <value value="50" name="PERF_PAPC_SU_ZERO_AREA_CULL_PRIM"/>
+ <value value="51" name="PERF_PAPC_SU_BACK_FACE_CULL_PRIM"/>
+ <value value="52" name="PERF_PAPC_SU_FRONT_FACE_CULL_PRIM"/>
+ <value value="53" name="PERF_PAPC_SU_POLYMODE_FACE_CULL"/>
+ <value value="54" name="PERF_PAPC_SU_POLYMODE_BACK_CULL"/>
+ <value value="55" name="PERF_PAPC_SU_POLYMODE_FRONT_CULL"/>
+ <value value="56" name="PERF_PAPC_SU_POLYMODE_INVALID_FILL"/>
+ <value value="57" name="PERF_PAPC_SU_OUTPUT_PRIM"/>
+ <value value="58" name="PERF_PAPC_SU_OUTPUT_CLIP_PRIM"/>
+ <value value="59" name="PERF_PAPC_SU_OUTPUT_NULL_PRIM"/>
+ <value value="60" name="PERF_PAPC_SU_OUTPUT_EVENT_FLAG"/>
+ <value value="61" name="PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT"/>
+ <value value="62" name="PERF_PAPC_SU_OUTPUT_END_OF_PACKET"/>
+ <value value="63" name="PERF_PAPC_SU_OUTPUT_POLYMODE_FACE"/>
+ <value value="64" name="PERF_PAPC_SU_OUTPUT_POLYMODE_BACK"/>
+ <value value="65" name="PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT"/>
+ <value value="66" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE"/>
+ <value value="67" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK"/>
+ <value value="68" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT"/>
+ <value value="69" name="PERF_PAPC_PASX_REQ_IDLE"/>
+ <value value="70" name="PERF_PAPC_PASX_REQ_BUSY"/>
+ <value value="71" name="PERF_PAPC_PASX_REQ_STALLED"/>
+ <value value="72" name="PERF_PAPC_PASX_REC_IDLE"/>
+ <value value="73" name="PERF_PAPC_PASX_REC_BUSY"/>
+ <value value="74" name="PERF_PAPC_PASX_REC_STARVED_SX"/>
+ <value value="75" name="PERF_PAPC_PASX_REC_STALLED"/>
+ <value value="76" name="PERF_PAPC_PASX_REC_STALLED_POS_MEM"/>
+ <value value="77" name="PERF_PAPC_PASX_REC_STALLED_CCGSM_IN"/>
+ <value value="78" name="PERF_PAPC_CCGSM_IDLE"/>
+ <value value="79" name="PERF_PAPC_CCGSM_BUSY"/>
+ <value value="80" name="PERF_PAPC_CCGSM_STALLED"/>
+ <value value="81" name="PERF_PAPC_CLPRIM_IDLE"/>
+ <value value="82" name="PERF_PAPC_CLPRIM_BUSY"/>
+ <value value="83" name="PERF_PAPC_CLPRIM_STALLED"/>
+ <value value="84" name="PERF_PAPC_CLPRIM_STARVED_CCGSM"/>
+ <value value="85" name="PERF_PAPC_CLIPSM_IDLE"/>
+ <value value="86" name="PERF_PAPC_CLIPSM_BUSY"/>
+ <value value="87" name="PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH"/>
+ <value value="88" name="PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ"/>
+ <value value="89" name="PERF_PAPC_CLIPSM_WAIT_CLIPGA"/>
+ <value value="90" name="PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP"/>
+ <value value="91" name="PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM"/>
+ <value value="92" name="PERF_PAPC_CLIPGA_IDLE"/>
+ <value value="93" name="PERF_PAPC_CLIPGA_BUSY"/>
+ <value value="94" name="PERF_PAPC_CLIPGA_STARVED_VTE_CLIP"/>
+ <value value="95" name="PERF_PAPC_CLIPGA_STALLED"/>
+ <value value="96" name="PERF_PAPC_CLIP_IDLE"/>
+ <value value="97" name="PERF_PAPC_CLIP_BUSY"/>
+ <value value="98" name="PERF_PAPC_SU_IDLE"/>
+ <value value="99" name="PERF_PAPC_SU_BUSY"/>
+ <value value="100" name="PERF_PAPC_SU_STARVED_CLIP"/>
+ <value value="101" name="PERF_PAPC_SU_STALLED_SC"/>
+ <value value="102" name="PERF_PAPC_SU_FACENESS_CULL"/>
+</enum>
+
+<enum name="a2xx_sc_perfcnt_select">
+ <value value="0" name="SC_SR_WINDOW_VALID"/>
+ <value value="1" name="SC_CW_WINDOW_VALID"/>
+ <value value="2" name="SC_QM_WINDOW_VALID"/>
+ <value value="3" name="SC_FW_WINDOW_VALID"/>
+ <value value="4" name="SC_EZ_WINDOW_VALID"/>
+ <value value="5" name="SC_IT_WINDOW_VALID"/>
+ <value value="6" name="SC_STARVED_BY_PA"/>
+ <value value="7" name="SC_STALLED_BY_RB_TILE"/>
+ <value value="8" name="SC_STALLED_BY_RB_SAMP"/>
+ <value value="9" name="SC_STARVED_BY_RB_EZ"/>
+ <value value="10" name="SC_STALLED_BY_SAMPLE_FF"/>
+ <value value="11" name="SC_STALLED_BY_SQ"/>
+ <value value="12" name="SC_STALLED_BY_SP"/>
+ <value value="13" name="SC_TOTAL_NO_PRIMS"/>
+ <value value="14" name="SC_NON_EMPTY_PRIMS"/>
+ <value value="15" name="SC_NO_TILES_PASSING_QM"/>
+ <value value="16" name="SC_NO_PIXELS_PRE_EZ"/>
+ <value value="17" name="SC_NO_PIXELS_POST_EZ"/>
+</enum>
+
+<enum name="a2xx_vgt_perfcount_select">
+ <value value="0" name="VGT_SQ_EVENT_WINDOW_ACTIVE"/>
+ <value value="1" name="VGT_SQ_SEND"/>
+ <value value="2" name="VGT_SQ_STALLED"/>
+ <value value="3" name="VGT_SQ_STARVED_BUSY"/>
+ <value value="4" name="VGT_SQ_STARVED_IDLE"/>
+ <value value="5" name="VGT_SQ_STATIC"/>
+ <value value="6" name="VGT_PA_EVENT_WINDOW_ACTIVE"/>
+ <value value="7" name="VGT_PA_CLIP_V_SEND"/>
+ <value value="8" name="VGT_PA_CLIP_V_STALLED"/>
+ <value value="9" name="VGT_PA_CLIP_V_STARVED_BUSY"/>
+ <value value="10" name="VGT_PA_CLIP_V_STARVED_IDLE"/>
+ <value value="11" name="VGT_PA_CLIP_V_STATIC"/>
+ <value value="12" name="VGT_PA_CLIP_P_SEND"/>
+ <value value="13" name="VGT_PA_CLIP_P_STALLED"/>
+ <value value="14" name="VGT_PA_CLIP_P_STARVED_BUSY"/>
+ <value value="15" name="VGT_PA_CLIP_P_STARVED_IDLE"/>
+ <value value="16" name="VGT_PA_CLIP_P_STATIC"/>
+ <value value="17" name="VGT_PA_CLIP_S_SEND"/>
+ <value value="18" name="VGT_PA_CLIP_S_STALLED"/>
+ <value value="19" name="VGT_PA_CLIP_S_STARVED_BUSY"/>
+ <value value="20" name="VGT_PA_CLIP_S_STARVED_IDLE"/>
+ <value value="21" name="VGT_PA_CLIP_S_STATIC"/>
+ <value value="22" name="RBIU_FIFOS_EVENT_WINDOW_ACTIVE"/>
+ <value value="23" name="RBIU_IMMED_DATA_FIFO_STARVED"/>
+ <value value="24" name="RBIU_IMMED_DATA_FIFO_STALLED"/>
+ <value value="25" name="RBIU_DMA_REQUEST_FIFO_STARVED"/>
+ <value value="26" name="RBIU_DMA_REQUEST_FIFO_STALLED"/>
+ <value value="27" name="RBIU_DRAW_INITIATOR_FIFO_STARVED"/>
+ <value value="28" name="RBIU_DRAW_INITIATOR_FIFO_STALLED"/>
+ <value value="29" name="BIN_PRIM_NEAR_CULL"/>
+ <value value="30" name="BIN_PRIM_ZERO_CULL"/>
+ <value value="31" name="BIN_PRIM_FAR_CULL"/>
+ <value value="32" name="BIN_PRIM_BIN_CULL"/>
+ <value value="33" name="BIN_PRIM_FACE_CULL"/>
+ <value value="34" name="SPARE34"/>
+ <value value="35" name="SPARE35"/>
+ <value value="36" name="SPARE36"/>
+ <value value="37" name="SPARE37"/>
+ <value value="38" name="SPARE38"/>
+ <value value="39" name="SPARE39"/>
+ <value value="40" name="TE_SU_IN_VALID"/>
+ <value value="41" name="TE_SU_IN_READ"/>
+ <value value="42" name="TE_SU_IN_PRIM"/>
+ <value value="43" name="TE_SU_IN_EOP"/>
+ <value value="44" name="TE_SU_IN_NULL_PRIM"/>
+ <value value="45" name="TE_WK_IN_VALID"/>
+ <value value="46" name="TE_WK_IN_READ"/>
+ <value value="47" name="TE_OUT_PRIM_VALID"/>
+ <value value="48" name="TE_OUT_PRIM_READ"/>
+</enum>
+
+<enum name="a2xx_tcr_perfcount_select">
+ <value value="0" name="DGMMPD_IPMUX0_STALL"/>
+ <value value="4" name="DGMMPD_IPMUX_ALL_STALL"/>
+ <value value="5" name="OPMUX0_L2_WRITES"/>
+</enum>
+
+<enum name="a2xx_tp_perfcount_select">
+ <value value="0" name="POINT_QUADS"/>
+ <value value="1" name="BILIN_QUADS"/>
+ <value value="2" name="ANISO_QUADS"/>
+ <value value="3" name="MIP_QUADS"/>
+ <value value="4" name="VOL_QUADS"/>
+ <value value="5" name="MIP_VOL_QUADS"/>
+ <value value="6" name="MIP_ANISO_QUADS"/>
+ <value value="7" name="VOL_ANISO_QUADS"/>
+ <value value="8" name="ANISO_2_1_QUADS"/>
+ <value value="9" name="ANISO_4_1_QUADS"/>
+ <value value="10" name="ANISO_6_1_QUADS"/>
+ <value value="11" name="ANISO_8_1_QUADS"/>
+ <value value="12" name="ANISO_10_1_QUADS"/>
+ <value value="13" name="ANISO_12_1_QUADS"/>
+ <value value="14" name="ANISO_14_1_QUADS"/>
+ <value value="15" name="ANISO_16_1_QUADS"/>
+ <value value="16" name="MIP_VOL_ANISO_QUADS"/>
+ <value value="17" name="ALIGN_2_QUADS"/>
+ <value value="18" name="ALIGN_4_QUADS"/>
+ <value value="19" name="PIX_0_QUAD"/>
+ <value value="20" name="PIX_1_QUAD"/>
+ <value value="21" name="PIX_2_QUAD"/>
+ <value value="22" name="PIX_3_QUAD"/>
+ <value value="23" name="PIX_4_QUAD"/>
+ <value value="24" name="TP_MIPMAP_LOD0"/>
+ <value value="25" name="TP_MIPMAP_LOD1"/>
+ <value value="26" name="TP_MIPMAP_LOD2"/>
+ <value value="27" name="TP_MIPMAP_LOD3"/>
+ <value value="28" name="TP_MIPMAP_LOD4"/>
+ <value value="29" name="TP_MIPMAP_LOD5"/>
+ <value value="30" name="TP_MIPMAP_LOD6"/>
+ <value value="31" name="TP_MIPMAP_LOD7"/>
+ <value value="32" name="TP_MIPMAP_LOD8"/>
+ <value value="33" name="TP_MIPMAP_LOD9"/>
+ <value value="34" name="TP_MIPMAP_LOD10"/>
+ <value value="35" name="TP_MIPMAP_LOD11"/>
+ <value value="36" name="TP_MIPMAP_LOD12"/>
+ <value value="37" name="TP_MIPMAP_LOD13"/>
+ <value value="38" name="TP_MIPMAP_LOD14"/>
+</enum>
+
+<enum name="a2xx_tcm_perfcount_select">
+ <value value="0" name="QUAD0_RD_LAT_FIFO_EMPTY"/>
+ <value value="3" name="QUAD0_RD_LAT_FIFO_4TH_FULL"/>
+ <value value="4" name="QUAD0_RD_LAT_FIFO_HALF_FULL"/>
+ <value value="5" name="QUAD0_RD_LAT_FIFO_FULL"/>
+ <value value="6" name="QUAD0_RD_LAT_FIFO_LT_4TH_FULL"/>
+ <value value="28" name="READ_STARVED_QUAD0"/>
+ <value value="32" name="READ_STARVED"/>
+ <value value="33" name="READ_STALLED_QUAD0"/>
+ <value value="37" name="READ_STALLED"/>
+ <value value="38" name="VALID_READ_QUAD0"/>
+ <value value="42" name="TC_TP_STARVED_QUAD0"/>
+ <value value="46" name="TC_TP_STARVED"/>
+</enum>
+
+<enum name="a2xx_tcf_perfcount_select">
+ <value value="0" name="VALID_CYCLES"/>
+ <value value="1" name="SINGLE_PHASES"/>
+ <value value="2" name="ANISO_PHASES"/>
+ <value value="3" name="MIP_PHASES"/>
+ <value value="4" name="VOL_PHASES"/>
+ <value value="5" name="MIP_VOL_PHASES"/>
+ <value value="6" name="MIP_ANISO_PHASES"/>
+ <value value="7" name="VOL_ANISO_PHASES"/>
+ <value value="8" name="ANISO_2_1_PHASES"/>
+ <value value="9" name="ANISO_4_1_PHASES"/>
+ <value value="10" name="ANISO_6_1_PHASES"/>
+ <value value="11" name="ANISO_8_1_PHASES"/>
+ <value value="12" name="ANISO_10_1_PHASES"/>
+ <value value="13" name="ANISO_12_1_PHASES"/>
+ <value value="14" name="ANISO_14_1_PHASES"/>
+ <value value="15" name="ANISO_16_1_PHASES"/>
+ <value value="16" name="MIP_VOL_ANISO_PHASES"/>
+ <value value="17" name="ALIGN_2_PHASES"/>
+ <value value="18" name="ALIGN_4_PHASES"/>
+ <value value="19" name="TPC_BUSY"/>
+ <value value="20" name="TPC_STALLED"/>
+ <value value="21" name="TPC_STARVED"/>
+ <value value="22" name="TPC_WORKING"/>
+ <value value="23" name="TPC_WALKER_BUSY"/>
+ <value value="24" name="TPC_WALKER_STALLED"/>
+ <value value="25" name="TPC_WALKER_WORKING"/>
+ <value value="26" name="TPC_ALIGNER_BUSY"/>
+ <value value="27" name="TPC_ALIGNER_STALLED"/>
+ <value value="28" name="TPC_ALIGNER_STALLED_BY_BLEND"/>
+ <value value="29" name="TPC_ALIGNER_STALLED_BY_CACHE"/>
+ <value value="30" name="TPC_ALIGNER_WORKING"/>
+ <value value="31" name="TPC_BLEND_BUSY"/>
+ <value value="32" name="TPC_BLEND_SYNC"/>
+ <value value="33" name="TPC_BLEND_STARVED"/>
+ <value value="34" name="TPC_BLEND_WORKING"/>
+ <value value="35" name="OPCODE_0x00"/>
+ <value value="36" name="OPCODE_0x01"/>
+ <value value="37" name="OPCODE_0x04"/>
+ <value value="38" name="OPCODE_0x10"/>
+ <value value="39" name="OPCODE_0x11"/>
+ <value value="40" name="OPCODE_0x12"/>
+ <value value="41" name="OPCODE_0x13"/>
+ <value value="42" name="OPCODE_0x18"/>
+ <value value="43" name="OPCODE_0x19"/>
+ <value value="44" name="OPCODE_0x1A"/>
+ <value value="45" name="OPCODE_OTHER"/>
+ <value value="56" name="IN_FIFO_0_EMPTY"/>
+ <value value="57" name="IN_FIFO_0_LT_HALF_FULL"/>
+ <value value="58" name="IN_FIFO_0_HALF_FULL"/>
+ <value value="59" name="IN_FIFO_0_FULL"/>
+ <value value="72" name="IN_FIFO_TPC_EMPTY"/>
+ <value value="73" name="IN_FIFO_TPC_LT_HALF_FULL"/>
+ <value value="74" name="IN_FIFO_TPC_HALF_FULL"/>
+ <value value="75" name="IN_FIFO_TPC_FULL"/>
+ <value value="76" name="TPC_TC_XFC"/>
+ <value value="77" name="TPC_TC_STATE"/>
+ <value value="78" name="TC_STALL"/>
+ <value value="79" name="QUAD0_TAPS"/>
+ <value value="83" name="QUADS"/>
+ <value value="84" name="TCA_SYNC_STALL"/>
+ <value value="85" name="TAG_STALL"/>
+ <value value="88" name="TCB_SYNC_STALL"/>
+ <value value="89" name="TCA_VALID"/>
+ <value value="90" name="PROBES_VALID"/>
+ <value value="91" name="MISS_STALL"/>
+ <value value="92" name="FETCH_FIFO_STALL"/>
+ <value value="93" name="TCO_STALL"/>
+ <value value="94" name="ANY_STALL"/>
+ <value value="95" name="TAG_MISSES"/>
+ <value value="96" name="TAG_HITS"/>
+ <value value="97" name="SUB_TAG_MISSES"/>
+ <value value="98" name="SET0_INVALIDATES"/>
+ <value value="99" name="SET1_INVALIDATES"/>
+ <value value="100" name="SET2_INVALIDATES"/>
+ <value value="101" name="SET3_INVALIDATES"/>
+ <value value="102" name="SET0_TAG_MISSES"/>
+ <value value="103" name="SET1_TAG_MISSES"/>
+ <value value="104" name="SET2_TAG_MISSES"/>
+ <value value="105" name="SET3_TAG_MISSES"/>
+ <value value="106" name="SET0_TAG_HITS"/>
+ <value value="107" name="SET1_TAG_HITS"/>
+ <value value="108" name="SET2_TAG_HITS"/>
+ <value value="109" name="SET3_TAG_HITS"/>
+ <value value="110" name="SET0_SUB_TAG_MISSES"/>
+ <value value="111" name="SET1_SUB_TAG_MISSES"/>
+ <value value="112" name="SET2_SUB_TAG_MISSES"/>
+ <value value="113" name="SET3_SUB_TAG_MISSES"/>
+ <value value="114" name="SET0_EVICT1"/>
+ <value value="115" name="SET0_EVICT2"/>
+ <value value="116" name="SET0_EVICT3"/>
+ <value value="117" name="SET0_EVICT4"/>
+ <value value="118" name="SET0_EVICT5"/>
+ <value value="119" name="SET0_EVICT6"/>
+ <value value="120" name="SET0_EVICT7"/>
+ <value value="121" name="SET0_EVICT8"/>
+ <value value="130" name="SET1_EVICT1"/>
+ <value value="131" name="SET1_EVICT2"/>
+ <value value="132" name="SET1_EVICT3"/>
+ <value value="133" name="SET1_EVICT4"/>
+ <value value="134" name="SET1_EVICT5"/>
+ <value value="135" name="SET1_EVICT6"/>
+ <value value="136" name="SET1_EVICT7"/>
+ <value value="137" name="SET1_EVICT8"/>
+ <value value="146" name="SET2_EVICT1"/>
+ <value value="147" name="SET2_EVICT2"/>
+ <value value="148" name="SET2_EVICT3"/>
+ <value value="149" name="SET2_EVICT4"/>
+ <value value="150" name="SET2_EVICT5"/>
+ <value value="151" name="SET2_EVICT6"/>
+ <value value="152" name="SET2_EVICT7"/>
+ <value value="153" name="SET2_EVICT8"/>
+ <value value="162" name="SET3_EVICT1"/>
+ <value value="163" name="SET3_EVICT2"/>
+ <value value="164" name="SET3_EVICT3"/>
+ <value value="165" name="SET3_EVICT4"/>
+ <value value="166" name="SET3_EVICT5"/>
+ <value value="167" name="SET3_EVICT6"/>
+ <value value="168" name="SET3_EVICT7"/>
+ <value value="169" name="SET3_EVICT8"/>
+ <value value="178" name="FF_EMPTY"/>
+ <value value="179" name="FF_LT_HALF_FULL"/>
+ <value value="180" name="FF_HALF_FULL"/>
+ <value value="181" name="FF_FULL"/>
+ <value value="182" name="FF_XFC"/>
+ <value value="183" name="FF_STALLED"/>
+ <value value="184" name="FG_MASKS"/>
+ <value value="185" name="FG_LEFT_MASKS"/>
+ <value value="186" name="FG_LEFT_MASK_STALLED"/>
+ <value value="187" name="FG_LEFT_NOT_DONE_STALL"/>
+ <value value="188" name="FG_LEFT_FG_STALL"/>
+ <value value="189" name="FG_LEFT_SECTORS"/>
+ <value value="195" name="FG0_REQUESTS"/>
+ <value value="196" name="FG0_STALLED"/>
+ <value value="199" name="MEM_REQ512"/>
+ <value value="200" name="MEM_REQ_SENT"/>
+ <value value="202" name="MEM_LOCAL_READ_REQ"/>
+ <value value="203" name="TC0_MH_STALLED"/>
+</enum>
+
+<enum name="a2xx_sq_perfcnt_select">
+ <value value="0" name="SQ_PIXEL_VECTORS_SUB"/>
+ <value value="1" name="SQ_VERTEX_VECTORS_SUB"/>
+ <value value="2" name="SQ_ALU0_ACTIVE_VTX_SIMD0"/>
+ <value value="3" name="SQ_ALU1_ACTIVE_VTX_SIMD0"/>
+ <value value="4" name="SQ_ALU0_ACTIVE_PIX_SIMD0"/>
+ <value value="5" name="SQ_ALU1_ACTIVE_PIX_SIMD0"/>
+ <value value="6" name="SQ_ALU0_ACTIVE_VTX_SIMD1"/>
+ <value value="7" name="SQ_ALU1_ACTIVE_VTX_SIMD1"/>
+ <value value="8" name="SQ_ALU0_ACTIVE_PIX_SIMD1"/>
+ <value value="9" name="SQ_ALU1_ACTIVE_PIX_SIMD1"/>
+ <value value="10" name="SQ_EXPORT_CYCLES"/>
+ <value value="11" name="SQ_ALU_CST_WRITTEN"/>
+ <value value="12" name="SQ_TEX_CST_WRITTEN"/>
+ <value value="13" name="SQ_ALU_CST_STALL"/>
+ <value value="14" name="SQ_ALU_TEX_STALL"/>
+ <value value="15" name="SQ_INST_WRITTEN"/>
+ <value value="16" name="SQ_BOOLEAN_WRITTEN"/>
+ <value value="17" name="SQ_LOOPS_WRITTEN"/>
+ <value value="18" name="SQ_PIXEL_SWAP_IN"/>
+ <value value="19" name="SQ_PIXEL_SWAP_OUT"/>
+ <value value="20" name="SQ_VERTEX_SWAP_IN"/>
+ <value value="21" name="SQ_VERTEX_SWAP_OUT"/>
+ <value value="22" name="SQ_ALU_VTX_INST_ISSUED"/>
+ <value value="23" name="SQ_TEX_VTX_INST_ISSUED"/>
+ <value value="24" name="SQ_VC_VTX_INST_ISSUED"/>
+ <value value="25" name="SQ_CF_VTX_INST_ISSUED"/>
+ <value value="26" name="SQ_ALU_PIX_INST_ISSUED"/>
+ <value value="27" name="SQ_TEX_PIX_INST_ISSUED"/>
+ <value value="28" name="SQ_VC_PIX_INST_ISSUED"/>
+ <value value="29" name="SQ_CF_PIX_INST_ISSUED"/>
+ <value value="30" name="SQ_ALU0_FIFO_EMPTY_SIMD0"/>
+ <value value="31" name="SQ_ALU1_FIFO_EMPTY_SIMD0"/>
+ <value value="32" name="SQ_ALU0_FIFO_EMPTY_SIMD1"/>
+ <value value="33" name="SQ_ALU1_FIFO_EMPTY_SIMD1"/>
+ <value value="34" name="SQ_ALU_NOPS"/>
+ <value value="35" name="SQ_PRED_SKIP"/>
+ <value value="36" name="SQ_SYNC_ALU_STALL_SIMD0_VTX"/>
+ <value value="37" name="SQ_SYNC_ALU_STALL_SIMD1_VTX"/>
+ <value value="38" name="SQ_SYNC_TEX_STALL_VTX"/>
+ <value value="39" name="SQ_SYNC_VC_STALL_VTX"/>
+ <value value="40" name="SQ_CONSTANTS_USED_SIMD0"/>
+ <value value="41" name="SQ_CONSTANTS_SENT_SP_SIMD0"/>
+ <value value="42" name="SQ_GPR_STALL_VTX"/>
+ <value value="43" name="SQ_GPR_STALL_PIX"/>
+ <value value="44" name="SQ_VTX_RS_STALL"/>
+ <value value="45" name="SQ_PIX_RS_STALL"/>
+ <value value="46" name="SQ_SX_PC_FULL"/>
+ <value value="47" name="SQ_SX_EXP_BUFF_FULL"/>
+ <value value="48" name="SQ_SX_POS_BUFF_FULL"/>
+ <value value="49" name="SQ_INTERP_QUADS"/>
+ <value value="50" name="SQ_INTERP_ACTIVE"/>
+ <value value="51" name="SQ_IN_PIXEL_STALL"/>
+ <value value="52" name="SQ_IN_VTX_STALL"/>
+ <value value="53" name="SQ_VTX_CNT"/>
+ <value value="54" name="SQ_VTX_VECTOR2"/>
+ <value value="55" name="SQ_VTX_VECTOR3"/>
+ <value value="56" name="SQ_VTX_VECTOR4"/>
+ <value value="57" name="SQ_PIXEL_VECTOR1"/>
+ <value value="58" name="SQ_PIXEL_VECTOR23"/>
+ <value value="59" name="SQ_PIXEL_VECTOR4"/>
+ <value value="60" name="SQ_CONSTANTS_USED_SIMD1"/>
+ <value value="61" name="SQ_CONSTANTS_SENT_SP_SIMD1"/>
+ <value value="62" name="SQ_SX_MEM_EXP_FULL"/>
+ <value value="63" name="SQ_ALU0_ACTIVE_VTX_SIMD2"/>
+ <value value="64" name="SQ_ALU1_ACTIVE_VTX_SIMD2"/>
+ <value value="65" name="SQ_ALU0_ACTIVE_PIX_SIMD2"/>
+ <value value="66" name="SQ_ALU1_ACTIVE_PIX_SIMD2"/>
+ <value value="67" name="SQ_ALU0_ACTIVE_VTX_SIMD3"/>
+ <value value="68" name="SQ_PERFCOUNT_VTX_QUAL_TP_DONE"/>
+ <value value="69" name="SQ_ALU0_ACTIVE_PIX_SIMD3"/>
+ <value value="70" name="SQ_PERFCOUNT_PIX_QUAL_TP_DONE"/>
+ <value value="71" name="SQ_ALU0_FIFO_EMPTY_SIMD2"/>
+ <value value="72" name="SQ_ALU1_FIFO_EMPTY_SIMD2"/>
+ <value value="73" name="SQ_ALU0_FIFO_EMPTY_SIMD3"/>
+ <value value="74" name="SQ_ALU1_FIFO_EMPTY_SIMD3"/>
+ <value value="75" name="SQ_SYNC_ALU_STALL_SIMD2_VTX"/>
+ <value value="76" name="SQ_PERFCOUNT_VTX_POP_THREAD"/>
+ <value value="77" name="SQ_SYNC_ALU_STALL_SIMD0_PIX"/>
+ <value value="78" name="SQ_SYNC_ALU_STALL_SIMD1_PIX"/>
+ <value value="79" name="SQ_SYNC_ALU_STALL_SIMD2_PIX"/>
+ <value value="80" name="SQ_PERFCOUNT_PIX_POP_THREAD"/>
+ <value value="81" name="SQ_SYNC_TEX_STALL_PIX"/>
+ <value value="82" name="SQ_SYNC_VC_STALL_PIX"/>
+ <value value="83" name="SQ_CONSTANTS_USED_SIMD2"/>
+ <value value="84" name="SQ_CONSTANTS_SENT_SP_SIMD2"/>
+ <value value="85" name="SQ_PERFCOUNT_VTX_DEALLOC_ACK"/>
+ <value value="86" name="SQ_PERFCOUNT_PIX_DEALLOC_ACK"/>
+ <value value="87" name="SQ_ALU0_FIFO_FULL_SIMD0"/>
+ <value value="88" name="SQ_ALU1_FIFO_FULL_SIMD0"/>
+ <value value="89" name="SQ_ALU0_FIFO_FULL_SIMD1"/>
+ <value value="90" name="SQ_ALU1_FIFO_FULL_SIMD1"/>
+ <value value="91" name="SQ_ALU0_FIFO_FULL_SIMD2"/>
+ <value value="92" name="SQ_ALU1_FIFO_FULL_SIMD2"/>
+ <value value="93" name="SQ_ALU0_FIFO_FULL_SIMD3"/>
+ <value value="94" name="SQ_ALU1_FIFO_FULL_SIMD3"/>
+ <value value="95" name="VC_PERF_STATIC"/>
+ <value value="96" name="VC_PERF_STALLED"/>
+ <value value="97" name="VC_PERF_STARVED"/>
+ <value value="98" name="VC_PERF_SEND"/>
+ <value value="99" name="VC_PERF_ACTUAL_STARVED"/>
+ <value value="100" name="PIXEL_THREAD_0_ACTIVE"/>
+ <value value="101" name="VERTEX_THREAD_0_ACTIVE"/>
+ <value value="102" name="PIXEL_THREAD_0_NUMBER"/>
+ <value value="103" name="VERTEX_THREAD_0_NUMBER"/>
+ <value value="104" name="VERTEX_EVENT_NUMBER"/>
+ <value value="105" name="PIXEL_EVENT_NUMBER"/>
+ <value value="106" name="PTRBUFF_EF_PUSH"/>
+ <value value="107" name="PTRBUFF_EF_POP_EVENT"/>
+ <value value="108" name="PTRBUFF_EF_POP_NEW_VTX"/>
+ <value value="109" name="PTRBUFF_EF_POP_DEALLOC"/>
+ <value value="110" name="PTRBUFF_EF_POP_PVECTOR"/>
+ <value value="111" name="PTRBUFF_EF_POP_PVECTOR_X"/>
+ <value value="112" name="PTRBUFF_EF_POP_PVECTOR_VNZ"/>
+ <value value="113" name="PTRBUFF_PB_DEALLOC"/>
+ <value value="114" name="PTRBUFF_PI_STATE_PPB_POP"/>
+ <value value="115" name="PTRBUFF_PI_RTR"/>
+ <value value="116" name="PTRBUFF_PI_READ_EN"/>
+ <value value="117" name="PTRBUFF_PI_BUFF_SWAP"/>
+ <value value="118" name="PTRBUFF_SQ_FREE_BUFF"/>
+ <value value="119" name="PTRBUFF_SQ_DEC"/>
+ <value value="120" name="PTRBUFF_SC_VALID_CNTL_EVENT"/>
+ <value value="121" name="PTRBUFF_SC_VALID_IJ_XFER"/>
+ <value value="122" name="PTRBUFF_SC_NEW_VECTOR_1_Q"/>
+ <value value="123" name="PTRBUFF_QUAL_NEW_VECTOR"/>
+ <value value="124" name="PTRBUFF_QUAL_EVENT"/>
+ <value value="125" name="PTRBUFF_END_BUFFER"/>
+ <value value="126" name="PTRBUFF_FILL_QUAD"/>
+ <value value="127" name="VERTS_WRITTEN_SPI"/>
+ <value value="128" name="TP_FETCH_INSTR_EXEC"/>
+ <value value="129" name="TP_FETCH_INSTR_REQ"/>
+ <value value="130" name="TP_DATA_RETURN"/>
+ <value value="131" name="SPI_WRITE_CYCLES_SP"/>
+ <value value="132" name="SPI_WRITES_SP"/>
+ <value value="133" name="SP_ALU_INSTR_EXEC"/>
+ <value value="134" name="SP_CONST_ADDR_TO_SQ"/>
+ <value value="135" name="SP_PRED_KILLS_TO_SQ"/>
+ <value value="136" name="SP_EXPORT_CYCLES_TO_SX"/>
+ <value value="137" name="SP_EXPORTS_TO_SX"/>
+ <value value="138" name="SQ_CYCLES_ELAPSED"/>
+ <value value="139" name="SQ_TCFS_OPT_ALLOC_EXEC"/>
+ <value value="140" name="SQ_TCFS_NO_OPT_ALLOC"/>
+ <value value="141" name="SQ_ALU0_NO_OPT_ALLOC"/>
+ <value value="142" name="SQ_ALU1_NO_OPT_ALLOC"/>
+ <value value="143" name="SQ_TCFS_ARB_XFC_CNT"/>
+ <value value="144" name="SQ_ALU0_ARB_XFC_CNT"/>
+ <value value="145" name="SQ_ALU1_ARB_XFC_CNT"/>
+ <value value="146" name="SQ_TCFS_CFS_UPDATE_CNT"/>
+ <value value="147" name="SQ_ALU0_CFS_UPDATE_CNT"/>
+ <value value="148" name="SQ_ALU1_CFS_UPDATE_CNT"/>
+ <value value="149" name="SQ_VTX_PUSH_THREAD_CNT"/>
+ <value value="150" name="SQ_VTX_POP_THREAD_CNT"/>
+ <value value="151" name="SQ_PIX_PUSH_THREAD_CNT"/>
+ <value value="152" name="SQ_PIX_POP_THREAD_CNT"/>
+ <value value="153" name="SQ_PIX_TOTAL"/>
+ <value value="154" name="SQ_PIX_KILLED"/>
+</enum>
+
+<enum name="a2xx_sx_perfcnt_select">
+ <value value="0" name="SX_EXPORT_VECTORS"/>
+ <value value="1" name="SX_DUMMY_QUADS"/>
+ <value value="2" name="SX_ALPHA_FAIL"/>
+ <value value="3" name="SX_RB_QUAD_BUSY"/>
+ <value value="4" name="SX_RB_COLOR_BUSY"/>
+ <value value="5" name="SX_RB_QUAD_STALL"/>
+ <value value="6" name="SX_RB_COLOR_STALL"/>
+</enum>
+
+<enum name="a2xx_rbbm_perfcount1_sel">
+ <value value="0" name="RBBM1_COUNT"/>
+ <value value="1" name="RBBM1_NRT_BUSY"/>
+ <value value="2" name="RBBM1_RB_BUSY"/>
+ <value value="3" name="RBBM1_SQ_CNTX0_BUSY"/>
+ <value value="4" name="RBBM1_SQ_CNTX17_BUSY"/>
+ <value value="5" name="RBBM1_VGT_BUSY"/>
+ <value value="6" name="RBBM1_VGT_NODMA_BUSY"/>
+ <value value="7" name="RBBM1_PA_BUSY"/>
+ <value value="8" name="RBBM1_SC_CNTX_BUSY"/>
+ <value value="9" name="RBBM1_TPC_BUSY"/>
+ <value value="10" name="RBBM1_TC_BUSY"/>
+ <value value="11" name="RBBM1_SX_BUSY"/>
+ <value value="12" name="RBBM1_CP_COHER_BUSY"/>
+ <value value="13" name="RBBM1_CP_NRT_BUSY"/>
+ <value value="14" name="RBBM1_GFX_IDLE_STALL"/>
+ <value value="15" name="RBBM1_INTERRUPT"/>
+</enum>
+
+<enum name="a2xx_cp_perfcount_sel">
+ <value value="0" name="ALWAYS_COUNT"/>
+ <value value="1" name="TRANS_FIFO_FULL"/>
+ <value value="2" name="TRANS_FIFO_AF"/>
+ <value value="3" name="RCIU_PFPTRANS_WAIT"/>
+ <value value="6" name="RCIU_NRTTRANS_WAIT"/>
+ <value value="8" name="CSF_NRT_READ_WAIT"/>
+ <value value="9" name="CSF_I1_FIFO_FULL"/>
+ <value value="10" name="CSF_I2_FIFO_FULL"/>
+ <value value="11" name="CSF_ST_FIFO_FULL"/>
+ <value value="13" name="CSF_RING_ROQ_FULL"/>
+ <value value="14" name="CSF_I1_ROQ_FULL"/>
+ <value value="15" name="CSF_I2_ROQ_FULL"/>
+ <value value="16" name="CSF_ST_ROQ_FULL"/>
+ <value value="18" name="MIU_TAG_MEM_FULL"/>
+ <value value="19" name="MIU_WRITECLEAN"/>
+ <value value="22" name="MIU_NRT_WRITE_STALLED"/>
+ <value value="23" name="MIU_NRT_READ_STALLED"/>
+ <value value="24" name="ME_WRITE_CONFIRM_FIFO_FULL"/>
+ <value value="25" name="ME_VS_DEALLOC_FIFO_FULL"/>
+ <value value="26" name="ME_PS_DEALLOC_FIFO_FULL"/>
+ <value value="27" name="ME_REGS_VS_EVENT_FIFO_FULL"/>
+ <value value="28" name="ME_REGS_PS_EVENT_FIFO_FULL"/>
+ <value value="29" name="ME_REGS_CF_EVENT_FIFO_FULL"/>
+ <value value="30" name="ME_MICRO_RB_STARVED"/>
+ <value value="31" name="ME_MICRO_I1_STARVED"/>
+ <value value="32" name="ME_MICRO_I2_STARVED"/>
+ <value value="33" name="ME_MICRO_ST_STARVED"/>
+ <value value="40" name="RCIU_RBBM_DWORD_SENT"/>
+ <value value="41" name="ME_BUSY_CLOCKS"/>
+ <value value="42" name="ME_WAIT_CONTEXT_AVAIL"/>
+ <value value="43" name="PFP_TYPE0_PACKET"/>
+ <value value="44" name="PFP_TYPE3_PACKET"/>
+ <value value="45" name="CSF_RB_WPTR_NEQ_RPTR"/>
+ <value value="46" name="CSF_I1_SIZE_NEQ_ZERO"/>
+ <value value="47" name="CSF_I2_SIZE_NEQ_ZERO"/>
+ <value value="48" name="CSF_RBI1I2_FETCHING"/>
+</enum>
+
+<enum name="a2xx_rb_perfcnt_select">
+ <value value="0" name="RBPERF_CNTX_BUSY"/>
+ <value value="1" name="RBPERF_CNTX_BUSY_MAX"/>
+ <value value="2" name="RBPERF_SX_QUAD_STARVED"/>
+ <value value="3" name="RBPERF_SX_QUAD_STARVED_MAX"/>
+ <value value="4" name="RBPERF_GA_GC_CH0_SYS_REQ"/>
+ <value value="5" name="RBPERF_GA_GC_CH0_SYS_REQ_MAX"/>
+ <value value="6" name="RBPERF_GA_GC_CH1_SYS_REQ"/>
+ <value value="7" name="RBPERF_GA_GC_CH1_SYS_REQ_MAX"/>
+ <value value="8" name="RBPERF_MH_STARVED"/>
+ <value value="9" name="RBPERF_MH_STARVED_MAX"/>
+ <value value="10" name="RBPERF_AZ_BC_COLOR_BUSY"/>
+ <value value="11" name="RBPERF_AZ_BC_COLOR_BUSY_MAX"/>
+ <value value="12" name="RBPERF_AZ_BC_Z_BUSY"/>
+ <value value="13" name="RBPERF_AZ_BC_Z_BUSY_MAX"/>
+ <value value="14" name="RBPERF_RB_SC_TILE_RTR_N"/>
+ <value value="15" name="RBPERF_RB_SC_TILE_RTR_N_MAX"/>
+ <value value="16" name="RBPERF_RB_SC_SAMP_RTR_N"/>
+ <value value="17" name="RBPERF_RB_SC_SAMP_RTR_N_MAX"/>
+ <value value="18" name="RBPERF_RB_SX_QUAD_RTR_N"/>
+ <value value="19" name="RBPERF_RB_SX_QUAD_RTR_N_MAX"/>
+ <value value="20" name="RBPERF_RB_SX_COLOR_RTR_N"/>
+ <value value="21" name="RBPERF_RB_SX_COLOR_RTR_N_MAX"/>
+ <value value="22" name="RBPERF_RB_SC_SAMP_LZ_BUSY"/>
+ <value value="23" name="RBPERF_RB_SC_SAMP_LZ_BUSY_MAX"/>
+ <value value="24" name="RBPERF_ZXP_STALL"/>
+ <value value="25" name="RBPERF_ZXP_STALL_MAX"/>
+ <value value="26" name="RBPERF_EVENT_PENDING"/>
+ <value value="27" name="RBPERF_EVENT_PENDING_MAX"/>
+ <value value="28" name="RBPERF_RB_MH_VALID"/>
+ <value value="29" name="RBPERF_RB_MH_VALID_MAX"/>
+ <value value="30" name="RBPERF_SX_RB_QUAD_SEND"/>
+ <value value="31" name="RBPERF_SX_RB_COLOR_SEND"/>
+ <value value="32" name="RBPERF_SC_RB_TILE_SEND"/>
+ <value value="33" name="RBPERF_SC_RB_SAMPLE_SEND"/>
+ <value value="34" name="RBPERF_SX_RB_MEM_EXPORT"/>
+ <value value="35" name="RBPERF_SX_RB_QUAD_EVENT"/>
+ <value value="36" name="RBPERF_SC_RB_TILE_EVENT_FILTERED"/>
+ <value value="37" name="RBPERF_SC_RB_TILE_EVENT_ALL"/>
+ <value value="38" name="RBPERF_RB_SC_EZ_SEND"/>
+ <value value="39" name="RBPERF_RB_SX_INDEX_SEND"/>
+ <value value="40" name="RBPERF_GMEM_INTFO_RD"/>
+ <value value="41" name="RBPERF_GMEM_INTF1_RD"/>
+ <value value="42" name="RBPERF_GMEM_INTFO_WR"/>
+ <value value="43" name="RBPERF_GMEM_INTF1_WR"/>
+ <value value="44" name="RBPERF_RB_CP_CONTEXT_DONE"/>
+ <value value="45" name="RBPERF_RB_CP_CACHE_FLUSH"/>
+ <value value="46" name="RBPERF_ZPASS_DONE"/>
+ <value value="47" name="RBPERF_ZCMD_VALID"/>
+ <value value="48" name="RBPERF_CCMD_VALID"/>
+ <value value="49" name="RBPERF_ACCUM_GRANT"/>
+ <value value="50" name="RBPERF_ACCUM_C0_GRANT"/>
+ <value value="51" name="RBPERF_ACCUM_C1_GRANT"/>
+ <value value="52" name="RBPERF_ACCUM_FULL_BE_WR"/>
+ <value value="53" name="RBPERF_ACCUM_REQUEST_NO_GRANT"/>
+ <value value="54" name="RBPERF_ACCUM_TIMEOUT_PULSE"/>
+ <value value="55" name="RBPERF_ACCUM_LIN_TIMEOUT_PULSE"/>
+ <value value="56" name="RBPERF_ACCUM_CAM_HIT_FLUSHING"/>
+</enum>
+
+<enum name="a2xx_mh_perfcnt_select">
+ <value value="0" name="CP_R0_REQUESTS"/>
+ <value value="1" name="CP_R1_REQUESTS"/>
+ <value value="2" name="CP_R2_REQUESTS"/>
+ <value value="3" name="CP_R3_REQUESTS"/>
+ <value value="4" name="CP_R4_REQUESTS"/>
+ <value value="5" name="CP_TOTAL_READ_REQUESTS"/>
+ <value value="6" name="CP_TOTAL_WRITE_REQUESTS"/>
+ <value value="7" name="CP_TOTAL_REQUESTS"/>
+ <value value="8" name="CP_DATA_BYTES_WRITTEN"/>
+ <value value="9" name="CP_WRITE_CLEAN_RESPONSES"/>
+ <value value="10" name="CP_R0_READ_BURSTS_RECEIVED"/>
+ <value value="11" name="CP_R1_READ_BURSTS_RECEIVED"/>
+ <value value="12" name="CP_R2_READ_BURSTS_RECEIVED"/>
+ <value value="13" name="CP_R3_READ_BURSTS_RECEIVED"/>
+ <value value="14" name="CP_R4_READ_BURSTS_RECEIVED"/>
+ <value value="15" name="CP_TOTAL_READ_BURSTS_RECEIVED"/>
+ <value value="16" name="CP_R0_DATA_BEATS_READ"/>
+ <value value="17" name="CP_R1_DATA_BEATS_READ"/>
+ <value value="18" name="CP_R2_DATA_BEATS_READ"/>
+ <value value="19" name="CP_R3_DATA_BEATS_READ"/>
+ <value value="20" name="CP_R4_DATA_BEATS_READ"/>
+ <value value="21" name="CP_TOTAL_DATA_BEATS_READ"/>
+ <value value="22" name="VGT_R0_REQUESTS"/>
+ <value value="23" name="VGT_R1_REQUESTS"/>
+ <value value="24" name="VGT_TOTAL_REQUESTS"/>
+ <value value="25" name="VGT_R0_READ_BURSTS_RECEIVED"/>
+ <value value="26" name="VGT_R1_READ_BURSTS_RECEIVED"/>
+ <value value="27" name="VGT_TOTAL_READ_BURSTS_RECEIVED"/>
+ <value value="28" name="VGT_R0_DATA_BEATS_READ"/>
+ <value value="29" name="VGT_R1_DATA_BEATS_READ"/>
+ <value value="30" name="VGT_TOTAL_DATA_BEATS_READ"/>
+ <value value="31" name="TC_TOTAL_REQUESTS"/>
+ <value value="32" name="TC_ROQ_REQUESTS"/>
+ <value value="33" name="TC_INFO_SENT"/>
+ <value value="34" name="TC_READ_BURSTS_RECEIVED"/>
+ <value value="35" name="TC_DATA_BEATS_READ"/>
+ <value value="36" name="TCD_BURSTS_READ"/>
+ <value value="37" name="RB_REQUESTS"/>
+ <value value="38" name="RB_DATA_BYTES_WRITTEN"/>
+ <value value="39" name="RB_WRITE_CLEAN_RESPONSES"/>
+ <value value="40" name="AXI_READ_REQUESTS_ID_0"/>
+ <value value="41" name="AXI_READ_REQUESTS_ID_1"/>
+ <value value="42" name="AXI_READ_REQUESTS_ID_2"/>
+ <value value="43" name="AXI_READ_REQUESTS_ID_3"/>
+ <value value="44" name="AXI_READ_REQUESTS_ID_4"/>
+ <value value="45" name="AXI_READ_REQUESTS_ID_5"/>
+ <value value="46" name="AXI_READ_REQUESTS_ID_6"/>
+ <value value="47" name="AXI_READ_REQUESTS_ID_7"/>
+ <value value="48" name="AXI_TOTAL_READ_REQUESTS"/>
+ <value value="49" name="AXI_WRITE_REQUESTS_ID_0"/>
+ <value value="50" name="AXI_WRITE_REQUESTS_ID_1"/>
+ <value value="51" name="AXI_WRITE_REQUESTS_ID_2"/>
+ <value value="52" name="AXI_WRITE_REQUESTS_ID_3"/>
+ <value value="53" name="AXI_WRITE_REQUESTS_ID_4"/>
+ <value value="54" name="AXI_WRITE_REQUESTS_ID_5"/>
+ <value value="55" name="AXI_WRITE_REQUESTS_ID_6"/>
+ <value value="56" name="AXI_WRITE_REQUESTS_ID_7"/>
+ <value value="57" name="AXI_TOTAL_WRITE_REQUESTS"/>
+ <value value="58" name="AXI_TOTAL_REQUESTS_ID_0"/>
+ <value value="59" name="AXI_TOTAL_REQUESTS_ID_1"/>
+ <value value="60" name="AXI_TOTAL_REQUESTS_ID_2"/>
+ <value value="61" name="AXI_TOTAL_REQUESTS_ID_3"/>
+ <value value="62" name="AXI_TOTAL_REQUESTS_ID_4"/>
+ <value value="63" name="AXI_TOTAL_REQUESTS_ID_5"/>
+ <value value="64" name="AXI_TOTAL_REQUESTS_ID_6"/>
+ <value value="65" name="AXI_TOTAL_REQUESTS_ID_7"/>
+ <value value="66" name="AXI_TOTAL_REQUESTS"/>
+ <value value="67" name="AXI_READ_CHANNEL_BURSTS_ID_0"/>
+ <value value="68" name="AXI_READ_CHANNEL_BURSTS_ID_1"/>
+ <value value="69" name="AXI_READ_CHANNEL_BURSTS_ID_2"/>
+ <value value="70" name="AXI_READ_CHANNEL_BURSTS_ID_3"/>
+ <value value="71" name="AXI_READ_CHANNEL_BURSTS_ID_4"/>
+ <value value="72" name="AXI_READ_CHANNEL_BURSTS_ID_5"/>
+ <value value="73" name="AXI_READ_CHANNEL_BURSTS_ID_6"/>
+ <value value="74" name="AXI_READ_CHANNEL_BURSTS_ID_7"/>
+ <value value="75" name="AXI_READ_CHANNEL_TOTAL_BURSTS"/>
+ <value value="76" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0"/>
+ <value value="77" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1"/>
+ <value value="78" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2"/>
+ <value value="79" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3"/>
+ <value value="80" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4"/>
+ <value value="81" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5"/>
+ <value value="82" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6"/>
+ <value value="83" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7"/>
+ <value value="84" name="AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ"/>
+ <value value="85" name="AXI_WRITE_CHANNEL_BURSTS_ID_0"/>
+ <value value="86" name="AXI_WRITE_CHANNEL_BURSTS_ID_1"/>
+ <value value="87" name="AXI_WRITE_CHANNEL_BURSTS_ID_2"/>
+ <value value="88" name="AXI_WRITE_CHANNEL_BURSTS_ID_3"/>
+ <value value="89" name="AXI_WRITE_CHANNEL_BURSTS_ID_4"/>
+ <value value="90" name="AXI_WRITE_CHANNEL_BURSTS_ID_5"/>
+ <value value="91" name="AXI_WRITE_CHANNEL_BURSTS_ID_6"/>
+ <value value="92" name="AXI_WRITE_CHANNEL_BURSTS_ID_7"/>
+ <value value="93" name="AXI_WRITE_CHANNEL_TOTAL_BURSTS"/>
+ <value value="94" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0"/>
+ <value value="95" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1"/>
+ <value value="96" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2"/>
+ <value value="97" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3"/>
+ <value value="98" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4"/>
+ <value value="99" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5"/>
+ <value value="100" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6"/>
+ <value value="101" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7"/>
+ <value value="102" name="AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN"/>
+ <value value="103" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0"/>
+ <value value="104" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1"/>
+ <value value="105" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2"/>
+ <value value="106" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3"/>
+ <value value="107" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4"/>
+ <value value="108" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5"/>
+ <value value="109" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6"/>
+ <value value="110" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7"/>
+ <value value="111" name="AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES"/>
+ <value value="112" name="TOTAL_MMU_MISSES"/>
+ <value value="113" name="MMU_READ_MISSES"/>
+ <value value="114" name="MMU_WRITE_MISSES"/>
+ <value value="115" name="TOTAL_MMU_HITS"/>
+ <value value="116" name="MMU_READ_HITS"/>
+ <value value="117" name="MMU_WRITE_HITS"/>
+ <value value="118" name="SPLIT_MODE_TC_HITS"/>
+ <value value="119" name="SPLIT_MODE_TC_MISSES"/>
+ <value value="120" name="SPLIT_MODE_NON_TC_HITS"/>
+ <value value="121" name="SPLIT_MODE_NON_TC_MISSES"/>
+ <value value="122" name="STALL_AWAITING_TLB_MISS_FETCH"/>
+ <value value="123" name="MMU_TLB_MISS_READ_BURSTS_RECEIVED"/>
+ <value value="124" name="MMU_TLB_MISS_DATA_BEATS_READ"/>
+ <value value="125" name="CP_CYCLES_HELD_OFF"/>
+ <value value="126" name="VGT_CYCLES_HELD_OFF"/>
+ <value value="127" name="TC_CYCLES_HELD_OFF"/>
+ <value value="128" name="TC_ROQ_CYCLES_HELD_OFF"/>
+ <value value="129" name="TC_CYCLES_HELD_OFF_TCD_FULL"/>
+ <value value="130" name="RB_CYCLES_HELD_OFF"/>
+ <value value="131" name="TOTAL_CYCLES_ANY_CLNT_HELD_OFF"/>
+ <value value="132" name="TLB_MISS_CYCLES_HELD_OFF"/>
+ <value value="133" name="AXI_READ_REQUEST_HELD_OFF"/>
+ <value value="134" name="AXI_WRITE_REQUEST_HELD_OFF"/>
+ <value value="135" name="AXI_REQUEST_HELD_OFF"/>
+ <value value="136" name="AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT"/>
+ <value value="137" name="AXI_WRITE_DATA_HELD_OFF"/>
+ <value value="138" name="CP_SAME_PAGE_BANK_REQUESTS"/>
+ <value value="139" name="VGT_SAME_PAGE_BANK_REQUESTS"/>
+ <value value="140" name="TC_SAME_PAGE_BANK_REQUESTS"/>
+ <value value="141" name="TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS"/>
+ <value value="142" name="RB_SAME_PAGE_BANK_REQUESTS"/>
+ <value value="143" name="TOTAL_SAME_PAGE_BANK_REQUESTS"/>
+ <value value="144" name="CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
+ <value value="145" name="VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
+ <value value="146" name="TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
+ <value value="147" name="RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
+ <value value="148" name="TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT"/>
+ <value value="149" name="TOTAL_MH_READ_REQUESTS"/>
+ <value value="150" name="TOTAL_MH_WRITE_REQUESTS"/>
+ <value value="151" name="TOTAL_MH_REQUESTS"/>
+ <value value="152" name="MH_BUSY"/>
+ <value value="153" name="CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
+ <value value="154" name="VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
+ <value value="155" name="TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
+ <value value="156" name="RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
+ <value value="157" name="TC_ROQ_N_VALID_ENTRIES"/>
+ <value value="158" name="ARQ_N_ENTRIES"/>
+ <value value="159" name="WDB_N_ENTRIES"/>
+ <value value="160" name="MH_READ_LATENCY_OUTST_REQ_SUM"/>
+ <value value="161" name="MC_READ_LATENCY_OUTST_REQ_SUM"/>
+ <value value="162" name="MC_TOTAL_READ_REQUESTS"/>
+ <value value="163" name="ELAPSED_CYCLES_MH_GATED_CLK"/>
+ <value value="164" name="ELAPSED_CLK_CYCLES"/>
+ <value value="165" name="CP_W_16B_REQUESTS"/>
+ <value value="166" name="CP_W_32B_REQUESTS"/>
+ <value value="167" name="TC_16B_REQUESTS"/>
+ <value value="168" name="TC_32B_REQUESTS"/>
+ <value value="169" name="PA_REQUESTS"/>
+ <value value="170" name="PA_DATA_BYTES_WRITTEN"/>
+ <value value="171" name="PA_WRITE_CLEAN_RESPONSES"/>
+ <value value="172" name="PA_CYCLES_HELD_OFF"/>
+ <value value="173" name="AXI_READ_REQUEST_DATA_BEATS_ID_0"/>
+ <value value="174" name="AXI_READ_REQUEST_DATA_BEATS_ID_1"/>
+ <value value="175" name="AXI_READ_REQUEST_DATA_BEATS_ID_2"/>
+ <value value="176" name="AXI_READ_REQUEST_DATA_BEATS_ID_3"/>
+ <value value="177" name="AXI_READ_REQUEST_DATA_BEATS_ID_4"/>
+ <value value="178" name="AXI_READ_REQUEST_DATA_BEATS_ID_5"/>
+ <value value="179" name="AXI_READ_REQUEST_DATA_BEATS_ID_6"/>
+ <value value="180" name="AXI_READ_REQUEST_DATA_BEATS_ID_7"/>
+ <value value="181" name="AXI_TOTAL_READ_REQUEST_DATA_BEATS"/>
+</enum>
+
+<enum name="perf_mode_cnt">
+ <value name="PERF_STATE_RESET" value="0"/>
+ <value name="PERF_STATE_ENABLE" value="1"/>
+ <value name="PERF_STATE_FREEZE" value="2"/>
+</enum>
+
+<domain name="A2XX" width="32">
+
+ <bitset name="a2xx_vgt_current_bin_id_min_max" inline="yes">
+ <bitfield name="COLUMN" low="0" high="2" type="uint"/>
+ <bitfield name="ROW" low="3" high="5" type="uint"/>
+ <bitfield name="GUARD_BAND_MASK" low="6" high="8" type="uint"/>
+ </bitset>
+
+ <reg32 offset="0x0001" name="RBBM_PATCH_RELEASE"/>
+ <reg32 offset="0x003b" name="RBBM_CNTL"/>
+ <reg32 offset="0x003c" name="RBBM_SOFT_RESET"/>
+ <reg32 offset="0x00c0" name="CP_PFP_UCODE_ADDR"/>
+ <reg32 offset="0x00c1" name="CP_PFP_UCODE_DATA"/>
+
+ <enum name="adreno_mmu_clnt_beh">
+ <value name="BEH_NEVR" value="0"/>
+ <value name="BEH_TRAN_RNG" value="1"/>
+ <value name="BEH_TRAN_FLT" value="2"/>
+ </enum>
+
+ <!--
+ Note: these seem applicable only for a2xx devices with gpummu? At
+ any rate, MH_MMU_CONFIG shows up in places in a3xx firmware where
+ it doesn't make sense, so I think offset 0x40 must be a different
+ register on a3xx.. so moving this back into A2XX domain:
+ -->
+ <reg32 offset="0x0040" name="MH_MMU_CONFIG">
+ <bitfield name="MMU_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="SPLIT_MODE_ENABLE" pos="1" type="boolean"/>
+ <bitfield name="RB_W_CLNT_BEHAVIOR" low="4" high="5" type="adreno_mmu_clnt_beh"/>
+ <bitfield name="CP_W_CLNT_BEHAVIOR" low="6" high="7" type="adreno_mmu_clnt_beh"/>
+ <bitfield name="CP_R0_CLNT_BEHAVIOR" low="8" high="9" type="adreno_mmu_clnt_beh"/>
+ <bitfield name="CP_R1_CLNT_BEHAVIOR" low="10" high="11" type="adreno_mmu_clnt_beh"/>
+ <bitfield name="CP_R2_CLNT_BEHAVIOR" low="12" high="13" type="adreno_mmu_clnt_beh"/>
+ <bitfield name="CP_R3_CLNT_BEHAVIOR" low="14" high="15" type="adreno_mmu_clnt_beh"/>
+ <bitfield name="CP_R4_CLNT_BEHAVIOR" low="16" high="17" type="adreno_mmu_clnt_beh"/>
+ <bitfield name="VGT_R0_CLNT_BEHAVIOR" low="18" high="19" type="adreno_mmu_clnt_beh"/>
+ <bitfield name="VGT_R1_CLNT_BEHAVIOR" low="20" high="21" type="adreno_mmu_clnt_beh"/>
+ <bitfield name="TC_R_CLNT_BEHAVIOR" low="22" high="23" type="adreno_mmu_clnt_beh"/>
+ <bitfield name="PA_W_CLNT_BEHAVIOR" low="24" high="25" type="adreno_mmu_clnt_beh"/>
+ </reg32>
+ <reg32 offset="0x0041" name="MH_MMU_VA_RANGE">
+ <bitfield name="NUM_64KB_REGIONS" low="0" high="11" type="uint"/>
+ <bitfield name="VA_BASE" low="12" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0042" name="MH_MMU_PT_BASE"/>
+ <reg32 offset="0x0043" name="MH_MMU_PAGE_FAULT"/>
+ <reg32 offset="0x0044" name="MH_MMU_TRAN_ERROR"/>
+ <reg32 offset="0x0045" name="MH_MMU_INVALIDATE">
+ <bitfield name="INVALIDATE_ALL" pos="0" type="boolean"/>
+ <bitfield name="INVALIDATE_TC" pos="1" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0046" name="MH_MMU_MPU_BASE"/>
+ <reg32 offset="0x0047" name="MH_MMU_MPU_END"/>
+
+ <reg32 offset="0x0394" name="NQWAIT_UNTIL"/>
+ <reg32 offset="0x0395" name="RBBM_PERFCOUNTER0_SELECT"/>
+ <reg32 offset="0x0396" name="RBBM_PERFCOUNTER1_SELECT"/>
+ <reg32 offset="0x0397" name="RBBM_PERFCOUNTER0_LO"/>
+ <reg32 offset="0x0398" name="RBBM_PERFCOUNTER0_HI"/>
+ <reg32 offset="0x0399" name="RBBM_PERFCOUNTER1_LO"/>
+ <reg32 offset="0x039a" name="RBBM_PERFCOUNTER1_HI"/>
+ <reg32 offset="0x039b" name="RBBM_DEBUG"/>
+ <reg32 offset="0x039c" name="RBBM_PM_OVERRIDE1">
+ <bitfield name="RBBM_AHBCLK_PM_OVERRIDE" pos="0" type="boolean"/>
+ <bitfield name="SC_REG_SCLK_PM_OVERRIDE" pos="1" type="boolean"/>
+ <bitfield name="SC_SCLK_PM_OVERRIDE" pos="2" type="boolean"/>
+ <bitfield name="SP_TOP_SCLK_PM_OVERRIDE" pos="3" type="boolean"/>
+ <bitfield name="SP_V0_SCLK_PM_OVERRIDE" pos="4" type="boolean"/>
+ <bitfield name="SQ_REG_SCLK_PM_OVERRIDE" pos="5" type="boolean"/>
+ <bitfield name="SQ_REG_FIFOS_SCLK_PM_OVERRIDE" pos="6" type="boolean"/>
+ <bitfield name="SQ_CONST_MEM_SCLK_PM_OVERRIDE" pos="7" type="boolean"/>
+ <bitfield name="SQ_SQ_SCLK_PM_OVERRIDE" pos="8" type="boolean"/>
+ <bitfield name="SX_SCLK_PM_OVERRIDE" pos="9" type="boolean"/>
+ <bitfield name="SX_REG_SCLK_PM_OVERRIDE" pos="10" type="boolean"/>
+ <bitfield name="TCM_TCO_SCLK_PM_OVERRIDE" pos="11" type="boolean"/>
+ <bitfield name="TCM_TCM_SCLK_PM_OVERRIDE" pos="12" type="boolean"/>
+ <bitfield name="TCM_TCD_SCLK_PM_OVERRIDE" pos="13" type="boolean"/>
+ <bitfield name="TCM_REG_SCLK_PM_OVERRIDE" pos="14" type="boolean"/>
+ <bitfield name="TPC_TPC_SCLK_PM_OVERRIDE" pos="15" type="boolean"/>
+ <bitfield name="TPC_REG_SCLK_PM_OVERRIDE" pos="16" type="boolean"/>
+ <bitfield name="TCF_TCA_SCLK_PM_OVERRIDE" pos="17" type="boolean"/>
+ <bitfield name="TCF_TCB_SCLK_PM_OVERRIDE" pos="18" type="boolean"/>
+ <bitfield name="TCF_TCB_READ_SCLK_PM_OVERRIDE" pos="19" type="boolean"/>
+ <bitfield name="TP_TP_SCLK_PM_OVERRIDE" pos="20" type="boolean"/>
+ <bitfield name="TP_REG_SCLK_PM_OVERRIDE" pos="21" type="boolean"/>
+ <bitfield name="CP_G_SCLK_PM_OVERRIDE" pos="22" type="boolean"/>
+ <bitfield name="CP_REG_SCLK_PM_OVERRIDE" pos="23" type="boolean"/>
+ <bitfield name="CP_G_REG_SCLK_PM_OVERRIDE" pos="24" type="boolean"/>
+ <bitfield name="SPI_SCLK_PM_OVERRIDE" pos="25" type="boolean"/>
+ <bitfield name="RB_REG_SCLK_PM_OVERRIDE" pos="26" type="boolean"/>
+ <bitfield name="RB_SCLK_PM_OVERRIDE" pos="27" type="boolean"/>
+ <bitfield name="MH_MH_SCLK_PM_OVERRIDE" pos="28" type="boolean"/>
+ <bitfield name="MH_REG_SCLK_PM_OVERRIDE" pos="29" type="boolean"/>
+ <bitfield name="MH_MMU_SCLK_PM_OVERRIDE" pos="30" type="boolean"/>
+ <bitfield name="MH_TCROQ_SCLK_PM_OVERRIDE" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x039d" name="RBBM_PM_OVERRIDE2">
+ <bitfield name="PA_REG_SCLK_PM_OVERRIDE" pos="0" type="boolean"/>
+ <bitfield name="PA_PA_SCLK_PM_OVERRIDE" pos="1" type="boolean"/>
+ <bitfield name="PA_AG_SCLK_PM_OVERRIDE" pos="2" type="boolean"/>
+ <bitfield name="VGT_REG_SCLK_PM_OVERRIDE" pos="3" type="boolean"/>
+ <bitfield name="VGT_FIFOS_SCLK_PM_OVERRIDE" pos="4" type="boolean"/>
+ <bitfield name="VGT_VGT_SCLK_PM_OVERRIDE" pos="5" type="boolean"/>
+ <bitfield name="DEBUG_PERF_SCLK_PM_OVERRIDE" pos="6" type="boolean"/>
+ <bitfield name="PERM_SCLK_PM_OVERRIDE" pos="7" type="boolean"/>
+ <bitfield name="GC_GA_GMEM0_PM_OVERRIDE" pos="8" type="boolean"/>
+ <bitfield name="GC_GA_GMEM1_PM_OVERRIDE" pos="9" type="boolean"/>
+ <bitfield name="GC_GA_GMEM2_PM_OVERRIDE" pos="10" type="boolean"/>
+ <bitfield name="GC_GA_GMEM3_PM_OVERRIDE" pos="11" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x03a0" name="RBBM_DEBUG_OUT"/>
+ <reg32 offset="0x03a1" name="RBBM_DEBUG_CNTL"/>
+ <reg32 offset="0x03b3" name="RBBM_READ_ERROR"/>
+ <reg32 offset="0x03b4" name="RBBM_INT_CNTL">
+ <bitfield name="RDERR_INT_MASK" pos="0" type="boolean"/>
+ <bitfield name="DISPLAY_UPDATE_INT_MASK" pos="1" type="boolean"/>
+ <bitfield name="GUI_IDLE_INT_MASK" pos="19" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x03b5" name="RBBM_INT_STATUS"/>
+ <reg32 offset="0x03b6" name="RBBM_INT_ACK"/>
+ <reg32 offset="0x03b7" name="MASTER_INT_SIGNAL">
+ <bitfield name="MH_INT_STAT" pos="5" type="boolean"/>
+ <bitfield name="SQ_INT_STAT" pos="26" type="boolean"/>
+ <bitfield name="CP_INT_STAT" pos="30" type="boolean"/>
+ <bitfield name="RBBM_INT_STAT" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x03f9" name="RBBM_PERIPHID1"/>
+ <reg32 offset="0x03fa" name="RBBM_PERIPHID2"/>
+ <reg32 offset="0x0444" name="CP_PERFMON_CNTL">
+ <!-- The width is uncertain -->
+ <bitfield name="PERF_MODE_CNT" low="0" high="2" type="perf_mode_cnt"/>
+ </reg32>
+ <reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT"/>
+ <reg32 offset="0x0446" name="CP_PERFCOUNTER_LO"/>
+ <reg32 offset="0x0447" name="CP_PERFCOUNTER_HI"/>
+ <reg32 offset="0x05d0" name="RBBM_STATUS">
+ <bitfield name="CMDFIFO_AVAIL" low="0" high="4" type="uint"/>
+ <bitfield name="TC_BUSY" pos="5" type="boolean"/>
+ <bitfield name="HIRQ_PENDING" pos="8" type="boolean"/>
+ <bitfield name="CPRQ_PENDING" pos="9" type="boolean"/>
+ <bitfield name="CFRQ_PENDING" pos="10" type="boolean"/>
+ <bitfield name="PFRQ_PENDING" pos="11" type="boolean"/>
+ <bitfield name="VGT_BUSY_NO_DMA" pos="12" type="boolean"/>
+ <bitfield name="RBBM_WU_BUSY" pos="14" type="boolean"/>
+ <bitfield name="CP_NRT_BUSY" pos="16" type="boolean"/>
+ <bitfield name="MH_BUSY" pos="18" type="boolean"/>
+ <bitfield name="MH_COHERENCY_BUSY" pos="19" type="boolean"/>
+ <bitfield name="SX_BUSY" pos="21" type="boolean"/>
+ <bitfield name="TPC_BUSY" pos="22" type="boolean"/>
+ <bitfield name="SC_CNTX_BUSY" pos="24" type="boolean"/>
+ <bitfield name="PA_BUSY" pos="25" type="boolean"/>
+ <bitfield name="VGT_BUSY" pos="26" type="boolean"/>
+ <bitfield name="SQ_CNTX17_BUSY" pos="27" type="boolean"/>
+ <bitfield name="SQ_CNTX0_BUSY" pos="28" type="boolean"/>
+ <bitfield name="RB_CNTX_BUSY" pos="30" type="boolean"/>
+ <bitfield name="GUI_ACTIVE" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0a40" name="MH_ARBITER_CONFIG">
+ <bitfield name="SAME_PAGE_LIMIT" low="0" high="5" type="uint"/>
+ <bitfield name="SAME_PAGE_GRANULARITY" pos="6" type="boolean"/>
+ <bitfield name="L1_ARB_ENABLE" pos="7" type="boolean"/>
+ <bitfield name="L1_ARB_HOLD_ENABLE" pos="8" type="boolean"/>
+ <bitfield name="L2_ARB_CONTROL" pos="9" type="boolean"/>
+ <bitfield name="PAGE_SIZE" low="10" high="12" type="uint"/>
+ <bitfield name="TC_REORDER_ENABLE" pos="13" type="boolean"/>
+ <bitfield name="TC_ARB_HOLD_ENABLE" pos="14" type="boolean"/>
+ <bitfield name="IN_FLIGHT_LIMIT_ENABLE" pos="15" type="boolean"/>
+ <bitfield name="IN_FLIGHT_LIMIT" low="16" high="21" type="uint"/>
+ <bitfield name="CP_CLNT_ENABLE" pos="22" type="boolean"/>
+ <bitfield name="VGT_CLNT_ENABLE" pos="23" type="boolean"/>
+ <bitfield name="TC_CLNT_ENABLE" pos="24" type="boolean"/>
+ <bitfield name="RB_CLNT_ENABLE" pos="25" type="boolean"/>
+ <bitfield name="PA_CLNT_ENABLE" pos="26" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0a42" name="MH_INTERRUPT_MASK">
+ <bitfield name="AXI_READ_ERROR" pos="0" type="boolean"/>
+ <bitfield name="AXI_WRITE_ERROR" pos="1" type="boolean"/>
+ <bitfield name="MMU_PAGE_FAULT" pos="2" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0a43" name="MH_INTERRUPT_STATUS"/>
+ <reg32 offset="0x0a44" name="MH_INTERRUPT_CLEAR"/>
+ <reg32 offset="0x0a54" name="MH_CLNT_INTF_CTRL_CONFIG1"/>
+ <reg32 offset="0x0a55" name="MH_CLNT_INTF_CTRL_CONFIG2"/>
+ <reg32 offset="0x0c01" name="A220_VSC_BIN_SIZE">
+ <bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>
+ <bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/>
+ </reg32>
+ <array offset="0x0c06" name="VSC_PIPE" stride="3" length="8">
+ <reg32 offset="0x0" name="CONFIG"/>
+ <reg32 offset="0x1" name="DATA_ADDRESS"/>
+ <reg32 offset="0x2" name="DATA_LENGTH"/>
+ </array>
+ <reg32 offset="0x0c38" name="PC_DEBUG_CNTL"/>
+ <reg32 offset="0x0c39" name="PC_DEBUG_DATA"/>
+ <reg32 offset="0x0c44" name="PA_SC_VIZ_QUERY_STATUS"/>
+ <reg32 offset="0x0c80" name="GRAS_DEBUG_CNTL"/>
+ <reg32 offset="0x0c80" name="PA_SU_DEBUG_CNTL"/>
+ <reg32 offset="0x0c81" name="GRAS_DEBUG_DATA"/>
+ <reg32 offset="0x0c81" name="PA_SU_DEBUG_DATA"/>
+ <reg32 offset="0x0c86" name="PA_SU_FACE_DATA">
+ <bitfield name="BASE_ADDR" low="5" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0d00" name="SQ_GPR_MANAGEMENT">
+ <bitfield name="REG_DYNAMIC" pos="0" type="boolean"/>
+ <bitfield name="REG_SIZE_PIX" low="4" high="11" type="uint"/>
+ <bitfield name="REG_SIZE_VTX" low="12" high="19" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0d01" name="SQ_FLOW_CONTROL"/>
+ <reg32 offset="0x0d02" name="SQ_INST_STORE_MANAGMENT">
+ <bitfield name="INST_BASE_PIX" low="0" high="11" type="uint"/>
+ <bitfield name="INST_BASE_VTX" low="16" high="27" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0d05" name="SQ_DEBUG_MISC"/>
+ <reg32 offset="0x0d34" name="SQ_INT_CNTL"/>
+ <reg32 offset="0x0d35" name="SQ_INT_STATUS"/>
+ <reg32 offset="0x0d36" name="SQ_INT_ACK"/>
+ <reg32 offset="0x0dae" name="SQ_DEBUG_INPUT_FSM"/>
+ <reg32 offset="0x0daf" name="SQ_DEBUG_CONST_MGR_FSM"/>
+ <reg32 offset="0x0db0" name="SQ_DEBUG_TP_FSM"/>
+ <reg32 offset="0x0db1" name="SQ_DEBUG_FSM_ALU_0"/>
+ <reg32 offset="0x0db2" name="SQ_DEBUG_FSM_ALU_1"/>
+ <reg32 offset="0x0db3" name="SQ_DEBUG_EXP_ALLOC"/>
+ <reg32 offset="0x0db4" name="SQ_DEBUG_PTR_BUFF"/>
+ <reg32 offset="0x0db5" name="SQ_DEBUG_GPR_VTX"/>
+ <reg32 offset="0x0db6" name="SQ_DEBUG_GPR_PIX"/>
+ <reg32 offset="0x0db7" name="SQ_DEBUG_TB_STATUS_SEL"/>
+ <reg32 offset="0x0db8" name="SQ_DEBUG_VTX_TB_0"/>
+ <reg32 offset="0x0db9" name="SQ_DEBUG_VTX_TB_1"/>
+ <reg32 offset="0x0dba" name="SQ_DEBUG_VTX_TB_STATUS_REG"/>
+ <reg32 offset="0x0dbb" name="SQ_DEBUG_VTX_TB_STATE_MEM"/>
+ <reg32 offset="0x0dbc" name="SQ_DEBUG_PIX_TB_0"/>
+ <reg32 offset="0x0dbd" name="SQ_DEBUG_PIX_TB_STATUS_REG_0"/>
+ <reg32 offset="0x0dbe" name="SQ_DEBUG_PIX_TB_STATUS_REG_1"/>
+ <reg32 offset="0x0dbf" name="SQ_DEBUG_PIX_TB_STATUS_REG_2"/>
+ <reg32 offset="0x0dc0" name="SQ_DEBUG_PIX_TB_STATUS_REG_3"/>
+ <reg32 offset="0x0dc1" name="SQ_DEBUG_PIX_TB_STATE_MEM"/>
+ <reg32 offset="0x0e00" name="TC_CNTL_STATUS">
+ <bitfield name="L2_INVALIDATE" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0e1e" name="TP0_CHICKEN"/>
+ <reg32 offset="0x0f01" name="RB_BC_CONTROL">
+ <bitfield name="ACCUM_LINEAR_MODE_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="ACCUM_TIMEOUT_SELECT" low="1" high="2" type="uint"/>
+ <bitfield name="DISABLE_EDRAM_CAM" pos="3" type="boolean"/>
+ <bitfield name="DISABLE_EZ_FAST_CONTEXT_SWITCH" pos="4" type="boolean"/>
+ <bitfield name="DISABLE_EZ_NULL_ZCMD_DROP" pos="5" type="boolean"/>
+ <bitfield name="DISABLE_LZ_NULL_ZCMD_DROP" pos="6" type="boolean"/>
+ <bitfield name="ENABLE_AZ_THROTTLE" pos="7" type="boolean"/>
+ <bitfield name="AZ_THROTTLE_COUNT" low="8" high="12" type="uint"/>
+ <bitfield name="ENABLE_CRC_UPDATE" pos="14" type="boolean"/>
+ <bitfield name="CRC_MODE" pos="15" type="boolean"/>
+ <bitfield name="DISABLE_SAMPLE_COUNTERS" pos="16" type="boolean"/>
+ <bitfield name="DISABLE_ACCUM" pos="17" type="boolean"/>
+ <bitfield name="ACCUM_ALLOC_MASK" low="18" high="21" type="uint"/>
+ <bitfield name="LINEAR_PERFORMANCE_ENABLE" pos="22" type="boolean"/>
+ <bitfield name="ACCUM_DATA_FIFO_LIMIT" low="23" high="26" type="uint"/>
+ <bitfield name="MEM_EXPORT_TIMEOUT_SELECT" low="27" high="28" type="uint"/>
+ <bitfield name="MEM_EXPORT_LINEAR_MODE_ENABLE" pos="29" type="boolean"/>
+ <bitfield name="CRC_SYSTEM" pos="30" type="boolean"/>
+ <bitfield name="RESERVED6" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0f02" name="RB_EDRAM_INFO"/>
+ <reg32 offset="0x0f26" name="RB_DEBUG_CNTL"/>
+ <reg32 offset="0x0f27" name="RB_DEBUG_DATA"/>
+ <reg32 offset="0x2000" name="RB_SURFACE_INFO">
+ <bitfield name="SURFACE_PITCH" low="0" high="13" type="uint"/>
+ <bitfield name="MSAA_SAMPLES" low="14" high="15" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2001" name="RB_COLOR_INFO">
+ <bitfield name="FORMAT" low="0" high="3" type="a2xx_colorformatx"/>
+ <bitfield name="ROUND_MODE" low="4" high="5" type="uint"/>
+ <bitfield name="LINEAR" pos="6" type="boolean"/>
+ <bitfield name="ENDIAN" low="7" high="8" type="uint"/>
+ <bitfield name="SWAP" low="9" high="10" type="uint"/>
+ <bitfield name="BASE" low="12" high="31" shr="12"/>
+ </reg32>
+ <reg32 offset="0x2002" name="RB_DEPTH_INFO">
+ <bitfield name="DEPTH_FORMAT" pos="0" type="adreno_rb_depth_format"/>
+ <bitfield name="DEPTH_BASE" low="12" high="31" type="uint" shr="12"/>
+ </reg32>
+ <reg32 offset="0x2005" name="A225_RB_COLOR_INFO3"/>
+ <reg32 offset="0x2006" name="COHER_DEST_BASE_0"/>
+ <reg32 offset="0x200e" name="PA_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>
+ <reg32 offset="0x200f" name="PA_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>
+ <reg32 offset="0x2080" name="PA_SC_WINDOW_OFFSET">
+ <bitfield name="X" low="0" high="14" type="int"/>
+ <bitfield name="Y" low="16" high="30" type="int"/>
+ <bitfield name="DISABLE" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2081" name="PA_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
+ <reg32 offset="0x2082" name="PA_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
+ <reg32 offset="0x2010" name="UNKNOWN_2010"/>
+ <reg32 offset="0x2100" name="VGT_MAX_VTX_INDX"/>
+ <reg32 offset="0x2101" name="VGT_MIN_VTX_INDX"/>
+ <reg32 offset="0x2102" name="VGT_INDX_OFFSET"/>
+ <reg32 offset="0x2103" name="A225_PC_MULTI_PRIM_IB_RESET_INDX"/>
+ <reg32 offset="0x2104" name="RB_COLOR_MASK">
+ <bitfield name="WRITE_RED" pos="0" type="boolean"/>
+ <bitfield name="WRITE_GREEN" pos="1" type="boolean"/>
+ <bitfield name="WRITE_BLUE" pos="2" type="boolean"/>
+ <bitfield name="WRITE_ALPHA" pos="3" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2105" name="RB_BLEND_RED"/>
+ <reg32 offset="0x2106" name="RB_BLEND_GREEN"/>
+ <reg32 offset="0x2107" name="RB_BLEND_BLUE"/>
+ <reg32 offset="0x2108" name="RB_BLEND_ALPHA"/>
+ <reg32 offset="0x2109" name="RB_FOG_COLOR">
+ <bitfield name="FOG_RED" low="0" high="7" type="uint"/>
+ <bitfield name="FOG_GREEN" low="8" high="15" type="uint"/>
+ <bitfield name="FOG_BLUE" low="16" high="23" type="uint"/>
+ </reg32>
+ <reg32 offset="0x210c" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
+ <reg32 offset="0x210d" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
+ <reg32 offset="0x210e" name="RB_ALPHA_REF"/>
+ <reg32 offset="0x210f" name="PA_CL_VPORT_XSCALE" type="float"/>
+ <reg32 offset="0x2110" name="PA_CL_VPORT_XOFFSET" type="float"/>
+ <reg32 offset="0x2111" name="PA_CL_VPORT_YSCALE" type="float"/>
+ <reg32 offset="0x2112" name="PA_CL_VPORT_YOFFSET" type="float"/>
+ <reg32 offset="0x2113" name="PA_CL_VPORT_ZSCALE" type="float"/>
+ <reg32 offset="0x2114" name="PA_CL_VPORT_ZOFFSET" type="float"/>
+ <reg32 offset="0x2180" name="SQ_PROGRAM_CNTL">
+ <doc>
+ note: only 0x3f worth of valid register values for VS_REGS and
+ PS_REGS, but high bit is set to indicate '0 registers used':
+ </doc>
+ <bitfield name="VS_REGS" low="0" high="7" type="uint"/>
+ <bitfield name="PS_REGS" low="8" high="15" type="uint"/>
+ <bitfield name="VS_RESOURCE" pos="16" type="boolean"/>
+ <bitfield name="PS_RESOURCE" pos="17" type="boolean"/>
+ <bitfield name="PARAM_GEN" pos="18" type="boolean"/>
+ <bitfield name="GEN_INDEX_PIX" pos="19" type="boolean"/>
+ <bitfield name="VS_EXPORT_COUNT" low="20" high="23" type="uint"/>
+ <bitfield name="VS_EXPORT_MODE" low="24" high="26" type="a2xx_sq_ps_vtx_mode"/>
+ <bitfield name="PS_EXPORT_MODE" low="27" high="30" type="uint"/>
+ <bitfield name="GEN_INDEX_VTX" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2181" name="SQ_CONTEXT_MISC">
+ <bitfield name="INST_PRED_OPTIMIZE" pos="0" type="boolean"/>
+ <bitfield name="SC_OUTPUT_SCREEN_XY" pos="1" type="boolean"/>
+ <bitfield name="SC_SAMPLE_CNTL" low="2" high="3" type="a2xx_sq_sample_cntl"/>
+ <bitfield name="PARAM_GEN_POS" low="8" high="15" type="uint"/>
+ <bitfield name="PERFCOUNTER_REF" pos="16" type="boolean"/>
+ <bitfield name="YEILD_OPTIMIZE" pos="17" type="boolean"/>
+ <bitfield name="TX_CACHE_SEL" pos="18" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2182" name="SQ_INTERPOLATOR_CNTL">
+ <bitfield name="PARAM_SHADE" low="0" high="15" type="uint"/>
+ <bitfield name="SAMPLING_PATTERN" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2183" name="SQ_WRAPPING_0">
+ <bitfield name="PARAM_WRAP_0" low="0" high="3" type="uint"/>
+ <bitfield name="PARAM_WRAP_1" low="4" high="7" type="uint"/>
+ <bitfield name="PARAM_WRAP_2" low="8" high="11" type="uint"/>
+ <bitfield name="PARAM_WRAP_3" low="12" high="15" type="uint"/>
+ <bitfield name="PARAM_WRAP_4" low="16" high="19" type="uint"/>
+ <bitfield name="PARAM_WRAP_5" low="20" high="23" type="uint"/>
+ <bitfield name="PARAM_WRAP_6" low="24" high="27" type="uint"/>
+ <bitfield name="PARAM_WRAP_7" low="28" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2184" name="SQ_WRAPPING_1">
+ <bitfield name="PARAM_WRAP_8" low="0" high="3" type="uint"/>
+ <bitfield name="PARAM_WRAP_9" low="4" high="7" type="uint"/>
+ <bitfield name="PARAM_WRAP_10" low="8" high="11" type="uint"/>
+ <bitfield name="PARAM_WRAP_11" low="12" high="15" type="uint"/>
+ <bitfield name="PARAM_WRAP_12" low="16" high="19" type="uint"/>
+ <bitfield name="PARAM_WRAP_13" low="20" high="23" type="uint"/>
+ <bitfield name="PARAM_WRAP_14" low="24" high="27" type="uint"/>
+ <bitfield name="PARAM_WRAP_15" low="28" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x21f6" name="SQ_PS_PROGRAM">
+ <bitfield name="BASE" low="0" high="11" type="uint"/>
+ <bitfield name="SIZE" low="12" high="23" type="uint"/>
+ </reg32>
+ <reg32 offset="0x21f7" name="SQ_VS_PROGRAM">
+ <bitfield name="BASE" low="0" high="11" type="uint"/>
+ <bitfield name="SIZE" low="12" high="23" type="uint"/>
+ </reg32>
+ <reg32 offset="0x21f9" name="VGT_EVENT_INITIATOR"/>
+ <reg32 offset="0x21fc" name="VGT_DRAW_INITIATOR" type="vgt_draw_initiator"/>
+ <reg32 offset="0x21fd" name="VGT_IMMED_DATA"/>
+ <reg32 offset="0x2200" name="RB_DEPTHCONTROL">
+ <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="Z_ENABLE" pos="1" type="boolean"/>
+ <bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>
+ <bitfield name="EARLY_Z_ENABLE" pos="3" type="boolean"/>
+ <bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>
+ <bitfield name="BACKFACE_ENABLE" pos="7" type="boolean"/>
+ <bitfield name="STENCILFUNC" low="8" high="10" type="adreno_compare_func"/>
+ <bitfield name="STENCILFAIL" low="11" high="13" type="adreno_stencil_op"/>
+ <bitfield name="STENCILZPASS" low="14" high="16" type="adreno_stencil_op"/>
+ <bitfield name="STENCILZFAIL" low="17" high="19" type="adreno_stencil_op"/>
+ <bitfield name="STENCILFUNC_BF" low="20" high="22" type="adreno_compare_func"/>
+ <bitfield name="STENCILFAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
+ <bitfield name="STENCILZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
+ <bitfield name="STENCILZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
+ </reg32>
+ <reg32 offset="0x2201" name="RB_BLEND_CONTROL">
+ <bitfield name="COLOR_SRCBLEND" low="0" high="4" type="adreno_rb_blend_factor"/>
+ <bitfield name="COLOR_COMB_FCN" low="5" high="7" type="a2xx_rb_blend_opcode"/>
+ <bitfield name="COLOR_DESTBLEND" low="8" high="12" type="adreno_rb_blend_factor"/>
+ <bitfield name="ALPHA_SRCBLEND" low="16" high="20" type="adreno_rb_blend_factor"/>
+ <bitfield name="ALPHA_COMB_FCN" low="21" high="23" type="a2xx_rb_blend_opcode"/>
+ <bitfield name="ALPHA_DESTBLEND" low="24" high="28" type="adreno_rb_blend_factor"/>
+ <bitfield name="BLEND_FORCE_ENABLE" pos="29" type="boolean"/>
+ <bitfield name="BLEND_FORCE" pos="30" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2202" name="RB_COLORCONTROL">
+ <bitfield name="ALPHA_FUNC" low="0" high="2" type="adreno_compare_func"/>
+ <bitfield name="ALPHA_TEST_ENABLE" pos="3" type="boolean"/>
+ <bitfield name="ALPHA_TO_MASK_ENABLE" pos="4" type="boolean"/>
+ <bitfield name="BLEND_DISABLE" pos="5" type="boolean"/>
+ <bitfield name="VOB_ENABLE" pos="6" type="boolean"/>
+ <bitfield name="VS_EXPORTS_FOG" pos="7" type="boolean"/>
+ <bitfield name="ROP_CODE" low="8" high="11" type="uint"/>
+ <bitfield name="DITHER_MODE" low="12" high="13" type="adreno_rb_dither_mode"/>
+ <bitfield name="DITHER_TYPE" low="14" high="15" type="a2xx_rb_dither_type"/>
+ <bitfield name="PIXEL_FOG" pos="16" type="boolean"/>
+ <bitfield name="ALPHA_TO_MASK_OFFSET0" low="24" high="25" type="uint"/>
+ <bitfield name="ALPHA_TO_MASK_OFFSET1" low="26" high="27" type="uint"/>
+ <bitfield name="ALPHA_TO_MASK_OFFSET2" low="28" high="29" type="uint"/>
+ <bitfield name="ALPHA_TO_MASK_OFFSET3" low="30" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2203" name="VGT_CURRENT_BIN_ID_MAX" type="a2xx_vgt_current_bin_id_min_max"/>
+ <reg32 offset="0x2204" name="PA_CL_CLIP_CNTL">
+ <bitfield name="CLIP_DISABLE" pos="16" type="boolean"/>
+ <bitfield name="BOUNDARY_EDGE_FLAG_ENA" pos="18" type="boolean"/>
+ <bitfield name="DX_CLIP_SPACE_DEF" pos="19" type="a2xx_dx_clip_space"/>
+ <bitfield name="DIS_CLIP_ERR_DETECT" pos="20" type="boolean"/>
+ <bitfield name="VTX_KILL_OR" pos="21" type="boolean"/>
+ <bitfield name="XY_NAN_RETAIN" pos="22" type="boolean"/>
+ <bitfield name="Z_NAN_RETAIN" pos="23" type="boolean"/>
+ <bitfield name="W_NAN_RETAIN" pos="24" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2205" name="PA_SU_SC_MODE_CNTL">
+ <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
+ <bitfield name="CULL_BACK" pos="1" type="boolean"/>
+ <bitfield name="FACE" pos="2" type="boolean"/>
+ <bitfield name="POLYMODE" low="3" high="4" type="a2xx_pa_su_sc_polymode"/>
+ <bitfield name="FRONT_PTYPE" low="5" high="7" type="adreno_pa_su_sc_draw"/>
+ <bitfield name="BACK_PTYPE" low="8" high="10" type="adreno_pa_su_sc_draw"/>
+ <bitfield name="POLY_OFFSET_FRONT_ENABLE" pos="11" type="boolean"/>
+ <bitfield name="POLY_OFFSET_BACK_ENABLE" pos="12" type="boolean"/>
+ <bitfield name="POLY_OFFSET_PARA_ENABLE" pos="13" type="boolean"/>
+ <bitfield name="MSAA_ENABLE" pos="15" type="boolean"/>
+ <bitfield name="VTX_WINDOW_OFFSET_ENABLE" pos="16" type="boolean"/>
+ <bitfield name="LINE_STIPPLE_ENABLE" pos="18" type="boolean"/>
+ <bitfield name="PROVOKING_VTX_LAST" pos="19" type="boolean"/>
+ <bitfield name="PERSP_CORR_DIS" pos="20" type="boolean"/>
+ <bitfield name="MULTI_PRIM_IB_ENA" pos="21" type="boolean"/>
+ <bitfield name="QUAD_ORDER_ENABLE" pos="23" type="boolean"/>
+ <bitfield name="WAIT_RB_IDLE_ALL_TRI" pos="25" type="boolean"/>
+ <bitfield name="WAIT_RB_IDLE_FIRST_TRI_NEW_STATE" pos="26" type="boolean"/>
+ <bitfield name="CLAMPED_FACENESS" pos="28" type="boolean"/>
+ <bitfield name="ZERO_AREA_FACENESS" pos="29" type="boolean"/>
+ <bitfield name="FACE_KILL_ENABLE" pos="30" type="boolean"/>
+ <bitfield name="FACE_WRITE_ENABLE" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2206" name="PA_CL_VTE_CNTL">
+ <bitfield name="VPORT_X_SCALE_ENA" pos="0" type="boolean"/>
+ <bitfield name="VPORT_X_OFFSET_ENA" pos="1" type="boolean"/>
+ <bitfield name="VPORT_Y_SCALE_ENA" pos="2" type="boolean"/>
+ <bitfield name="VPORT_Y_OFFSET_ENA" pos="3" type="boolean"/>
+ <bitfield name="VPORT_Z_SCALE_ENA" pos="4" type="boolean"/>
+ <bitfield name="VPORT_Z_OFFSET_ENA" pos="5" type="boolean"/>
+ <bitfield name="VTX_XY_FMT" pos="8" type="boolean"/>
+ <bitfield name="VTX_Z_FMT" pos="9" type="boolean"/>
+ <bitfield name="VTX_W0_FMT" pos="10" type="boolean"/>
+ <bitfield name="PERFCOUNTER_REF" pos="11" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2207" name="VGT_CURRENT_BIN_ID_MIN" type="a2xx_vgt_current_bin_id_min_max"/>
+ <reg32 offset="0x2208" name="RB_MODECONTROL">
+ <bitfield name="EDRAM_MODE" low="0" high="2" type="a2xx_rb_edram_mode"/>
+ </reg32>
+ <reg32 offset="0x2209" name="A220_RB_LRZ_VSC_CONTROL"/>
+ <reg32 offset="0x220a" name="RB_SAMPLE_POS"/>
+ <reg32 offset="0x220b" name="CLEAR_COLOR">
+ <bitfield name="RED" low="0" high="7"/>
+ <bitfield name="GREEN" low="8" high="15"/>
+ <bitfield name="BLUE" low="16" high="23"/>
+ <bitfield name="ALPHA" low="24" high="31"/>
+ </reg32>
+ <reg32 offset="0x2210" name="A220_GRAS_CONTROL"/>
+ <reg32 offset="0x2280" name="PA_SU_POINT_SIZE">
+ <bitfield name="HEIGHT" low="0" high="15" type="ufixed" radix="4"/>
+ <bitfield name="WIDTH" low="16" high="31" type="ufixed" radix="4"/>
+ </reg32>
+ <reg32 offset="0x2281" name="PA_SU_POINT_MINMAX">
+ <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
+ <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
+ </reg32>
+ <reg32 offset="0x2282" name="PA_SU_LINE_CNTL">
+ <bitfield name="WIDTH" low="0" high="15" type="ufixed" radix="4"/>
+ </reg32>
+ <reg32 offset="0x2283" name="PA_SC_LINE_STIPPLE">
+ <bitfield name="LINE_PATTERN" low="0" high="15" type="hex"/>
+ <bitfield name="REPEAT_COUNT" low="16" high="23" type="uint"/>
+ <bitfield name="PATTERN_BIT_ORDER" pos="28" type="a2xx_pa_sc_pattern_bit_order"/>
+ <bitfield name="AUTO_RESET_CNTL" low="29" high="30" type="a2xx_pa_sc_auto_reset_cntl"/>
+ </reg32>
+ <reg32 offset="0x2293" name="PA_SC_VIZ_QUERY">
+ <bitfield name="VIZ_QUERY_ENA" pos="0" type="boolean"/>
+ <bitfield name="VIZ_QUERY_ID" low="1" high="6" type="uint"/>
+ <bitfield name="KILL_PIX_POST_EARLY_Z" pos="8" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2294" name="VGT_ENHANCE"/>
+ <reg32 offset="0x2300" name="PA_SC_LINE_CNTL">
+ <bitfield name="BRES_CNTL" low="0" high="15" type="uint"/>
+ <bitfield name="USE_BRES_CNTL" pos="8" type="boolean"/>
+ <bitfield name="EXPAND_LINE_WIDTH" pos="9" type="boolean"/>
+ <bitfield name="LAST_PIXEL" pos="10" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2301" name="PA_SC_AA_CONFIG">
+ <bitfield name="MSAA_NUM_SAMPLES" low="0" high="2" type="uint"/>
+ <bitfield name="MAX_SAMPLE_DIST" low="13" high="16" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2302" name="PA_SU_VTX_CNTL">
+ <bitfield name="PIX_CENTER" pos="0" type="a2xx_pa_pixcenter"/>
+ <bitfield name="ROUND_MODE" low="1" high="2" type="a2xx_pa_roundmode"/>
+ <bitfield name="QUANT_MODE" low="7" high="9" type="a2xx_pa_quantmode"/>
+ </reg32>
+ <reg32 offset="0x2303" name="PA_CL_GB_VERT_CLIP_ADJ" type="float"/>
+ <reg32 offset="0x2304" name="PA_CL_GB_VERT_DISC_ADJ" type="float"/>
+ <reg32 offset="0x2305" name="PA_CL_GB_HORZ_CLIP_ADJ" type="float"/>
+ <reg32 offset="0x2306" name="PA_CL_GB_HORZ_DISC_ADJ" type="float"/>
+ <reg32 offset="0x2307" name="SQ_VS_CONST">
+ <bitfield name="BASE" low="0" high="8" type="uint"/>
+ <bitfield name="SIZE" low="12" high="20" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2308" name="SQ_PS_CONST">
+ <bitfield name="BASE" low="0" high="8" type="uint"/>
+ <bitfield name="SIZE" low="12" high="20" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2309" name="SQ_DEBUG_MISC_0"/>
+ <reg32 offset="0x230a" name="SQ_DEBUG_MISC_1"/>
+ <reg32 offset="0x2312" name="PA_SC_AA_MASK"/>
+ <reg32 offset="0x2316" name="VGT_VERTEX_REUSE_BLOCK_CNTL">
+ <bitfield name="VTX_REUSE_DEPTH" low="0" high="2" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2317" name="VGT_OUT_DEALLOC_CNTL">
+ <bitfield name="DEALLOC_DIST" low="0" high="1" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2318" name="RB_COPY_CONTROL">
+ <bitfield name="COPY_SAMPLE_SELECT" low="0" high="2" type="a2xx_rb_copy_sample_select"/>
+ <bitfield name="DEPTH_CLEAR_ENABLE" pos="3" type="boolean"/>
+ <bitfield name="CLEAR_MASK" low="4" high="7" type="hex"/>
+ </reg32>
+ <reg32 offset="0x2319" name="RB_COPY_DEST_BASE"/>
+ <reg32 offset="0x231a" name="RB_COPY_DEST_PITCH" shr="5" type="uint"/>
+ <reg32 offset="0x231b" name="RB_COPY_DEST_INFO">
+ <bitfield name="DEST_ENDIAN" low="0" high="2" type="adreno_rb_surface_endian"/>
+ <bitfield name="LINEAR" pos="3" type="boolean"/>
+ <bitfield name="FORMAT" low="4" high="7" type="a2xx_colorformatx"/>
+ <bitfield name="SWAP" low="8" high="9" type="uint"/>
+ <bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/>
+ <bitfield name="DITHER_TYPE" low="12" high="13" type="a2xx_rb_dither_type"/>
+ <bitfield name="WRITE_RED" pos="14" type="boolean"/>
+ <bitfield name="WRITE_GREEN" pos="15" type="boolean"/>
+ <bitfield name="WRITE_BLUE" pos="16" type="boolean"/>
+ <bitfield name="WRITE_ALPHA" pos="17" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x231c" name="RB_COPY_DEST_OFFSET">
+ <bitfield name="X" low="0" high="12" type="uint"/>
+ <bitfield name="Y" low="13" high="25" type="uint"/>
+ </reg32>
+ <reg32 offset="0x231d" name="RB_DEPTH_CLEAR"/>
+ <reg32 offset="0x2324" name="RB_SAMPLE_COUNT_CTL"/>
+ <reg32 offset="0x2326" name="RB_COLOR_DEST_MASK"/>
+ <reg32 offset="0x2340" name="A225_GRAS_UCP0X"/>
+ <reg32 offset="0x2357" name="A225_GRAS_UCP5W"/>
+ <reg32 offset="0x2360" name="A225_GRAS_UCP_ENABLED"/>
+ <reg32 offset="0x2380" name="PA_SU_POLY_OFFSET_FRONT_SCALE"/>
+ <reg32 offset="0x2381" name="PA_SU_POLY_OFFSET_FRONT_OFFSET"/>
+ <reg32 offset="0x2382" name="PA_SU_POLY_OFFSET_BACK_SCALE"/>
+ <reg32 offset="0x2383" name="PA_SU_POLY_OFFSET_BACK_OFFSET"/>
+ <reg32 offset="0x4000" name="SQ_CONSTANT_0"/>
+ <reg32 offset="0x4800" name="SQ_FETCH_0"/>
+ <reg32 offset="0x4900" name="SQ_CF_BOOLEANS"/>
+ <reg32 offset="0x4908" name="SQ_CF_LOOP"/>
+ <reg32 offset="0xa29" name="COHER_SIZE_PM4"/>
+ <reg32 offset="0xa2a" name="COHER_BASE_PM4"/>
+ <reg32 offset="0xa2b" name="COHER_STATUS_PM4"/>
+
+ <reg32 offset="0x0c88" name="PA_SU_PERFCOUNTER0_SELECT"/>
+ <reg32 offset="0x0c89" name="PA_SU_PERFCOUNTER1_SELECT"/>
+ <reg32 offset="0x0c8a" name="PA_SU_PERFCOUNTER2_SELECT"/>
+ <reg32 offset="0x0c8b" name="PA_SU_PERFCOUNTER3_SELECT"/>
+ <reg32 offset="0x0c8c" name="PA_SU_PERFCOUNTER0_LOW"/>
+ <reg32 offset="0x0c8d" name="PA_SU_PERFCOUNTER0_HI"/>
+ <reg32 offset="0x0c8e" name="PA_SU_PERFCOUNTER1_LOW"/>
+ <reg32 offset="0x0c8f" name="PA_SU_PERFCOUNTER1_HI"/>
+ <reg32 offset="0x0c90" name="PA_SU_PERFCOUNTER2_LOW"/>
+ <reg32 offset="0x0c91" name="PA_SU_PERFCOUNTER2_HI"/>
+ <reg32 offset="0x0c92" name="PA_SU_PERFCOUNTER3_LOW"/>
+ <reg32 offset="0x0c93" name="PA_SU_PERFCOUNTER3_HI"/>
+ <reg32 offset="0x0c98" name="PA_SC_PERFCOUNTER0_SELECT"/>
+ <reg32 offset="0x0c99" name="PA_SC_PERFCOUNTER0_LOW"/>
+ <reg32 offset="0x0c9a" name="PA_SC_PERFCOUNTER0_HI"/>
+ <reg32 offset="0x0c48" name="VGT_PERFCOUNTER0_SELECT"/>
+ <reg32 offset="0x0c49" name="VGT_PERFCOUNTER1_SELECT"/>
+ <reg32 offset="0x0c4a" name="VGT_PERFCOUNTER2_SELECT"/>
+ <reg32 offset="0x0c4b" name="VGT_PERFCOUNTER3_SELECT"/>
+ <reg32 offset="0x0c4c" name="VGT_PERFCOUNTER0_LOW"/>
+ <reg32 offset="0x0c4e" name="VGT_PERFCOUNTER1_LOW"/>
+ <reg32 offset="0x0c50" name="VGT_PERFCOUNTER2_LOW"/>
+ <reg32 offset="0x0c52" name="VGT_PERFCOUNTER3_LOW"/>
+ <reg32 offset="0x0c4d" name="VGT_PERFCOUNTER0_HI"/>
+ <reg32 offset="0x0c4f" name="VGT_PERFCOUNTER1_HI"/>
+ <reg32 offset="0x0c51" name="VGT_PERFCOUNTER2_HI"/>
+ <reg32 offset="0x0c53" name="VGT_PERFCOUNTER3_HI"/>
+ <reg32 offset="0x0e05" name="TCR_PERFCOUNTER0_SELECT"/>
+ <reg32 offset="0x0e08" name="TCR_PERFCOUNTER1_SELECT"/>
+ <reg32 offset="0x0e06" name="TCR_PERFCOUNTER0_HI"/>
+ <reg32 offset="0x0e09" name="TCR_PERFCOUNTER1_HI"/>
+ <reg32 offset="0x0e07" name="TCR_PERFCOUNTER0_LOW"/>
+ <reg32 offset="0x0e0a" name="TCR_PERFCOUNTER1_LOW"/>
+ <reg32 offset="0x0e1f" name="TP0_PERFCOUNTER0_SELECT"/>
+ <reg32 offset="0x0e20" name="TP0_PERFCOUNTER0_HI"/>
+ <reg32 offset="0x0e21" name="TP0_PERFCOUNTER0_LOW"/>
+ <reg32 offset="0x0e22" name="TP0_PERFCOUNTER1_SELECT"/>
+ <reg32 offset="0x0e23" name="TP0_PERFCOUNTER1_HI"/>
+ <reg32 offset="0x0e24" name="TP0_PERFCOUNTER1_LOW"/>
+ <reg32 offset="0x0e54" name="TCM_PERFCOUNTER0_SELECT"/>
+ <reg32 offset="0x0e57" name="TCM_PERFCOUNTER1_SELECT"/>
+ <reg32 offset="0x0e55" name="TCM_PERFCOUNTER0_HI"/>
+ <reg32 offset="0x0e58" name="TCM_PERFCOUNTER1_HI"/>
+ <reg32 offset="0x0e56" name="TCM_PERFCOUNTER0_LOW"/>
+ <reg32 offset="0x0e59" name="TCM_PERFCOUNTER1_LOW"/>
+ <reg32 offset="0x0e5a" name="TCF_PERFCOUNTER0_SELECT"/>
+ <reg32 offset="0x0e5d" name="TCF_PERFCOUNTER1_SELECT"/>
+ <reg32 offset="0x0e60" name="TCF_PERFCOUNTER2_SELECT"/>
+ <reg32 offset="0x0e63" name="TCF_PERFCOUNTER3_SELECT"/>
+ <reg32 offset="0x0e66" name="TCF_PERFCOUNTER4_SELECT"/>
+ <reg32 offset="0x0e69" name="TCF_PERFCOUNTER5_SELECT"/>
+ <reg32 offset="0x0e6c" name="TCF_PERFCOUNTER6_SELECT"/>
+ <reg32 offset="0x0e6f" name="TCF_PERFCOUNTER7_SELECT"/>
+ <reg32 offset="0x0e72" name="TCF_PERFCOUNTER8_SELECT"/>
+ <reg32 offset="0x0e75" name="TCF_PERFCOUNTER9_SELECT"/>
+ <reg32 offset="0x0e78" name="TCF_PERFCOUNTER10_SELECT"/>
+ <reg32 offset="0x0e7b" name="TCF_PERFCOUNTER11_SELECT"/>
+ <reg32 offset="0x0e5b" name="TCF_PERFCOUNTER0_HI"/>
+ <reg32 offset="0x0e5e" name="TCF_PERFCOUNTER1_HI"/>
+ <reg32 offset="0x0e61" name="TCF_PERFCOUNTER2_HI"/>
+ <reg32 offset="0x0e64" name="TCF_PERFCOUNTER3_HI"/>
+ <reg32 offset="0x0e67" name="TCF_PERFCOUNTER4_HI"/>
+ <reg32 offset="0x0e6a" name="TCF_PERFCOUNTER5_HI"/>
+ <reg32 offset="0x0e6d" name="TCF_PERFCOUNTER6_HI"/>
+ <reg32 offset="0x0e70" name="TCF_PERFCOUNTER7_HI"/>
+ <reg32 offset="0x0e73" name="TCF_PERFCOUNTER8_HI"/>
+ <reg32 offset="0x0e76" name="TCF_PERFCOUNTER9_HI"/>
+ <reg32 offset="0x0e79" name="TCF_PERFCOUNTER10_HI"/>
+ <reg32 offset="0x0e7c" name="TCF_PERFCOUNTER11_HI"/>
+ <reg32 offset="0x0e5c" name="TCF_PERFCOUNTER0_LOW"/>
+ <reg32 offset="0x0e5f" name="TCF_PERFCOUNTER1_LOW"/>
+ <reg32 offset="0x0e62" name="TCF_PERFCOUNTER2_LOW"/>
+ <reg32 offset="0x0e65" name="TCF_PERFCOUNTER3_LOW"/>
+ <reg32 offset="0x0e68" name="TCF_PERFCOUNTER4_LOW"/>
+ <reg32 offset="0x0e6b" name="TCF_PERFCOUNTER5_LOW"/>
+ <reg32 offset="0x0e6e" name="TCF_PERFCOUNTER6_LOW"/>
+ <reg32 offset="0x0e71" name="TCF_PERFCOUNTER7_LOW"/>
+ <reg32 offset="0x0e74" name="TCF_PERFCOUNTER8_LOW"/>
+ <reg32 offset="0x0e77" name="TCF_PERFCOUNTER9_LOW"/>
+ <reg32 offset="0x0e7a" name="TCF_PERFCOUNTER10_LOW"/>
+ <reg32 offset="0x0e7d" name="TCF_PERFCOUNTER11_LOW"/>
+ <reg32 offset="0x0dc8" name="SQ_PERFCOUNTER0_SELECT"/>
+ <reg32 offset="0x0dc9" name="SQ_PERFCOUNTER1_SELECT"/>
+ <reg32 offset="0x0dca" name="SQ_PERFCOUNTER2_SELECT"/>
+ <reg32 offset="0x0dcb" name="SQ_PERFCOUNTER3_SELECT"/>
+ <reg32 offset="0x0dcc" name="SQ_PERFCOUNTER0_LOW"/>
+ <reg32 offset="0x0dcd" name="SQ_PERFCOUNTER0_HI"/>
+ <reg32 offset="0x0dce" name="SQ_PERFCOUNTER1_LOW"/>
+ <reg32 offset="0x0dcf" name="SQ_PERFCOUNTER1_HI"/>
+ <reg32 offset="0x0dd0" name="SQ_PERFCOUNTER2_LOW"/>
+ <reg32 offset="0x0dd1" name="SQ_PERFCOUNTER2_HI"/>
+ <reg32 offset="0x0dd2" name="SQ_PERFCOUNTER3_LOW"/>
+ <reg32 offset="0x0dd3" name="SQ_PERFCOUNTER3_HI"/>
+ <reg32 offset="0x0dd4" name="SX_PERFCOUNTER0_SELECT"/>
+ <reg32 offset="0x0dd8" name="SX_PERFCOUNTER0_LOW"/>
+ <reg32 offset="0x0dd9" name="SX_PERFCOUNTER0_HI"/>
+ <reg32 offset="0x0a46" name="MH_PERFCOUNTER0_SELECT"/>
+ <reg32 offset="0x0a4a" name="MH_PERFCOUNTER1_SELECT"/>
+ <reg32 offset="0x0a47" name="MH_PERFCOUNTER0_CONFIG"/>
+ <reg32 offset="0x0a4b" name="MH_PERFCOUNTER1_CONFIG"/>
+ <reg32 offset="0x0a48" name="MH_PERFCOUNTER0_LOW"/>
+ <reg32 offset="0x0a4c" name="MH_PERFCOUNTER1_LOW"/>
+ <reg32 offset="0x0a49" name="MH_PERFCOUNTER0_HI"/>
+ <reg32 offset="0x0a4d" name="MH_PERFCOUNTER1_HI"/>
+ <reg32 offset="0x0f04" name="RB_PERFCOUNTER0_SELECT"/>
+ <reg32 offset="0x0f05" name="RB_PERFCOUNTER1_SELECT"/>
+ <reg32 offset="0x0f06" name="RB_PERFCOUNTER2_SELECT"/>
+ <reg32 offset="0x0f07" name="RB_PERFCOUNTER3_SELECT"/>
+ <reg32 offset="0x0f08" name="RB_PERFCOUNTER0_LOW"/>
+ <reg32 offset="0x0f09" name="RB_PERFCOUNTER0_HI"/>
+ <reg32 offset="0x0f0a" name="RB_PERFCOUNTER1_LOW"/>
+ <reg32 offset="0x0f0b" name="RB_PERFCOUNTER1_HI"/>
+ <reg32 offset="0x0f0c" name="RB_PERFCOUNTER2_LOW"/>
+ <reg32 offset="0x0f0d" name="RB_PERFCOUNTER2_HI"/>
+ <reg32 offset="0x0f0e" name="RB_PERFCOUNTER3_LOW"/>
+ <reg32 offset="0x0f0f" name="RB_PERFCOUNTER3_HI"/>
+</domain>
+
+<domain name="A2XX_SQ_TEX" width="32">
+ <doc>Texture state dwords</doc>
+ <enum name="sq_tex_clamp">
+ <value name="SQ_TEX_WRAP" value="0"/>
+ <value name="SQ_TEX_MIRROR" value="1"/>
+ <value name="SQ_TEX_CLAMP_LAST_TEXEL" value="2"/>
+ <value name="SQ_TEX_MIRROR_ONCE_LAST_TEXEL" value="3"/>
+ <value name="SQ_TEX_CLAMP_HALF_BORDER" value="4"/>
+ <value name="SQ_TEX_MIRROR_ONCE_HALF_BORDER" value="5"/>
+ <value name="SQ_TEX_CLAMP_BORDER" value="6"/>
+ <value name="SQ_TEX_MIRROR_ONCE_BORDER" value="7"/>
+ </enum>
+ <enum name="sq_tex_swiz">
+ <value name="SQ_TEX_X" value="0"/>
+ <value name="SQ_TEX_Y" value="1"/>
+ <value name="SQ_TEX_Z" value="2"/>
+ <value name="SQ_TEX_W" value="3"/>
+ <value name="SQ_TEX_ZERO" value="4"/>
+ <value name="SQ_TEX_ONE" value="5"/>
+ </enum>
+ <enum name="sq_tex_filter">
+ <value name="SQ_TEX_FILTER_POINT" value="0"/>
+ <value name="SQ_TEX_FILTER_BILINEAR" value="1"/>
+ <value name="SQ_TEX_FILTER_BASEMAP" value="2"/>
+ <value name="SQ_TEX_FILTER_USE_FETCH_CONST" value="3"/>
+ </enum>
+ <enum name="sq_tex_aniso_filter">
+ <value name="SQ_TEX_ANISO_FILTER_DISABLED" value="0"/>
+ <value name="SQ_TEX_ANISO_FILTER_MAX_1_1" value="1"/>
+ <value name="SQ_TEX_ANISO_FILTER_MAX_2_1" value="2"/>
+ <value name="SQ_TEX_ANISO_FILTER_MAX_4_1" value="3"/>
+ <value name="SQ_TEX_ANISO_FILTER_MAX_8_1" value="4"/>
+ <value name="SQ_TEX_ANISO_FILTER_MAX_16_1" value="5"/>
+ <value name="SQ_TEX_ANISO_FILTER_USE_FETCH_CONST" value="7"/>
+ </enum>
+ <enum name="sq_tex_dimension">
+ <value name="SQ_TEX_DIMENSION_1D" value="0"/>
+ <value name="SQ_TEX_DIMENSION_2D" value="1"/>
+ <value name="SQ_TEX_DIMENSION_3D" value="2"/>
+ <value name="SQ_TEX_DIMENSION_CUBE" value="3"/>
+ </enum>
+ <enum name="sq_tex_border_color">
+ <value name="SQ_TEX_BORDER_COLOR_BLACK" value="0"/>
+ <value name="SQ_TEX_BORDER_COLOR_WHITE" value="1"/>
+ <value name="SQ_TEX_BORDER_COLOR_ACBYCR_BLACK" value="2"/>
+ <value name="SQ_TEX_BORDER_COLOR_ACBCRY_BLACK" value="3"/>
+ </enum>
+ <enum name="sq_tex_sign">
+ <value name="SQ_TEX_SIGN_UNSIGNED" value="0"/>
+ <value name="SQ_TEX_SIGN_SIGNED" value="1"/>
+ <!-- biased: 2*color-1 (range -1,1 when sampling) -->
+ <value name="SQ_TEX_SIGN_UNSIGNED_BIASED" value="2"/>
+ <!-- gamma: sRGB to linear - doesn't seem to work on adreno? -->
+ <value name="SQ_TEX_SIGN_GAMMA" value="3"/>
+ </enum>
+ <enum name="sq_tex_endian">
+ <value name="SQ_TEX_ENDIAN_NONE" value="0"/>
+ <value name="SQ_TEX_ENDIAN_8IN16" value="1"/>
+ <value name="SQ_TEX_ENDIAN_8IN32" value="2"/>
+ <value name="SQ_TEX_ENDIAN_16IN32" value="3"/>
+ </enum>
+ <enum name="sq_tex_clamp_policy">
+ <value name="SQ_TEX_CLAMP_POLICY_D3D" value="0"/>
+ <value name="SQ_TEX_CLAMP_POLICY_OGL" value="1"/>
+ </enum>
+ <enum name="sq_tex_num_format">
+ <value name="SQ_TEX_NUM_FORMAT_FRAC" value="0"/>
+ <value name="SQ_TEX_NUM_FORMAT_INT" value="1"/>
+ </enum>
+ <enum name="sq_tex_type">
+ <value name="SQ_TEX_TYPE_0" value="0"/>
+ <value name="SQ_TEX_TYPE_1" value="1"/>
+ <value name="SQ_TEX_TYPE_2" value="2"/>
+ <value name="SQ_TEX_TYPE_3" value="3"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="TYPE" low="0" high="1" type="sq_tex_type"/>
+ <bitfield name="SIGN_X" low="2" high="3" type="sq_tex_sign"/>
+ <bitfield name="SIGN_Y" low="4" high="5" type="sq_tex_sign"/>
+ <bitfield name="SIGN_Z" low="6" high="7" type="sq_tex_sign"/>
+ <bitfield name="SIGN_W" low="8" high="9" type="sq_tex_sign"/>
+ <bitfield name="CLAMP_X" low="10" high="12" type="sq_tex_clamp"/>
+ <bitfield name="CLAMP_Y" low="13" high="15" type="sq_tex_clamp"/>
+ <bitfield name="CLAMP_Z" low="16" high="18" type="sq_tex_clamp"/>
+ <bitfield name="PITCH" low="22" high="30" shr="5" type="uint"/>
+ <bitfield name="TILED" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="FORMAT" low="0" high="5" type="a2xx_sq_surfaceformat"/>
+ <bitfield name="ENDIANNESS" low="6" high="7" type="sq_tex_endian"/>
+ <bitfield name="REQUEST_SIZE" low="8" high="9" type="uint"/>
+ <bitfield name="STACKED" pos="10" type="boolean"/>
+ <bitfield name="CLAMP_POLICY" pos="11" type="sq_tex_clamp_policy"/>
+ <bitfield name="BASE_ADDRESS" low="12" high="31" type="uint" shr="12"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="WIDTH" low="0" high="12" type="uint"/>
+ <bitfield name="HEIGHT" low="13" high="25" type="uint"/>
+ <bitfield name="DEPTH" low="26" high="31" type="uint"/>
+ <!-- 1d/3d have different bit configurations -->
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="NUM_FORMAT" pos="0" type="sq_tex_num_format"/>
+ <bitfield name="SWIZ_X" low="1" high="3" type="sq_tex_swiz"/>
+ <bitfield name="SWIZ_Y" low="4" high="6" type="sq_tex_swiz"/>
+ <bitfield name="SWIZ_Z" low="7" high="9" type="sq_tex_swiz"/>
+ <bitfield name="SWIZ_W" low="10" high="12" type="sq_tex_swiz"/>
+ <bitfield name="EXP_ADJUST" low="13" high="18" type="int"/>
+ <bitfield name="XY_MAG_FILTER" low="19" high="20" type="sq_tex_filter"/>
+ <bitfield name="XY_MIN_FILTER" low="21" high="22" type="sq_tex_filter"/>
+ <bitfield name="MIP_FILTER" low="23" high="24" type="sq_tex_filter"/>
+ <bitfield name="ANISO_FILTER" low="25" high="27" type="sq_tex_aniso_filter"/>
+ <bitfield name="BORDER_SIZE" pos="31" type="uint"/>
+ </reg32>
+ <reg32 offset="4" name="4">
+ <bitfield name="VOL_MAG_FILTER" pos="0" type="sq_tex_filter"/>
+ <bitfield name="VOL_MIN_FILTER" pos="1" type="sq_tex_filter"/>
+ <bitfield name="MIP_MIN_LEVEL" low="2" high="5" type="uint"/>
+ <bitfield name="MIP_MAX_LEVEL" low="6" high="9" type="uint"/>
+ <bitfield name="MAX_ANISO_WALK" pos="10" type="boolean"/>
+ <bitfield name="MIN_ANISO_WALK" pos="11" type="boolean"/>
+ <bitfield name="LOD_BIAS" low="12" high="21" type="fixed" radix="5"/>
+ <bitfield name="GRAD_EXP_ADJUST_H" low="22" high="26" type="uint"/>
+ <bitfield name="GRAD_EXP_ADJUST_V" low="27" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="5" name="5">
+ <bitfield name="BORDER_COLOR" low="0" high="1" type="sq_tex_border_color"/>
+ <bitfield name="FORCE_BCW_MAX" pos="2" type="boolean"/>
+ <bitfield name="TRI_CLAMP" low="3" high="4" type="uint"/>
+ <bitfield name="ANISO_BIAS" low="5" high="8" type="fixed" radix="0"/> <!-- radix unknown -->
+ <bitfield name="DIMENSION" low="9" high="10" type="sq_tex_dimension"/>
+ <bitfield name="PACKED_MIPS" pos="11" type="boolean"/>
+ <bitfield name="MIP_ADDRESS" low="12" high="31" type="uint" shr="12"/>
+ </reg32>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/adreno/a3xx.xml b/drivers/gpu/drm/msm/registers/adreno/a3xx.xml
new file mode 100644
index 000000000000..6717abc0a897
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/adreno/a3xx.xml
@@ -0,0 +1,1751 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+<import file="adreno/adreno_common.xml"/>
+<import file="adreno/adreno_pm4.xml"/>
+
+<enum name="a3xx_tile_mode">
+ <value name="LINEAR" value="0"/>
+ <value name="TILE_4X4" value="1"/> <!-- "normal" case for textures -->
+ <value name="TILE_32X32" value="2"/> <!-- only used in GMEM -->
+ <value name="TILE_4X2" value="3"/> <!-- only used for CrCb -->
+</enum>
+
+<enum name="a3xx_state_block_id">
+ <value name="HLSQ_BLOCK_ID_TP_TEX" value="2"/>
+ <value name="HLSQ_BLOCK_ID_TP_MIPMAP" value="3"/>
+ <value name="HLSQ_BLOCK_ID_SP_VS" value="4"/>
+ <value name="HLSQ_BLOCK_ID_SP_FS" value="6"/>
+</enum>
+
+<enum name="a3xx_cache_opcode">
+ <value name="INVALIDATE" value="1"/>
+</enum>
+
+<enum name="a3xx_vtx_fmt">
+ <value name="VFMT_32_FLOAT" value="0x0"/>
+ <value name="VFMT_32_32_FLOAT" value="0x1"/>
+ <value name="VFMT_32_32_32_FLOAT" value="0x2"/>
+ <value name="VFMT_32_32_32_32_FLOAT" value="0x3"/>
+
+ <value name="VFMT_16_FLOAT" value="0x4"/>
+ <value name="VFMT_16_16_FLOAT" value="0x5"/>
+ <value name="VFMT_16_16_16_FLOAT" value="0x6"/>
+ <value name="VFMT_16_16_16_16_FLOAT" value="0x7"/>
+
+ <value name="VFMT_32_FIXED" value="0x8"/>
+ <value name="VFMT_32_32_FIXED" value="0x9"/>
+ <value name="VFMT_32_32_32_FIXED" value="0xa"/>
+ <value name="VFMT_32_32_32_32_FIXED" value="0xb"/>
+
+ <value name="VFMT_16_SINT" value="0x10"/>
+ <value name="VFMT_16_16_SINT" value="0x11"/>
+ <value name="VFMT_16_16_16_SINT" value="0x12"/>
+ <value name="VFMT_16_16_16_16_SINT" value="0x13"/>
+ <value name="VFMT_16_UINT" value="0x14"/>
+ <value name="VFMT_16_16_UINT" value="0x15"/>
+ <value name="VFMT_16_16_16_UINT" value="0x16"/>
+ <value name="VFMT_16_16_16_16_UINT" value="0x17"/>
+ <value name="VFMT_16_SNORM" value="0x18"/>
+ <value name="VFMT_16_16_SNORM" value="0x19"/>
+ <value name="VFMT_16_16_16_SNORM" value="0x1a"/>
+ <value name="VFMT_16_16_16_16_SNORM" value="0x1b"/>
+ <value name="VFMT_16_UNORM" value="0x1c"/>
+ <value name="VFMT_16_16_UNORM" value="0x1d"/>
+ <value name="VFMT_16_16_16_UNORM" value="0x1e"/>
+ <value name="VFMT_16_16_16_16_UNORM" value="0x1f"/>
+
+ <!-- seems to be no NORM variants for 32bit.. -->
+ <value name="VFMT_32_UINT" value="0x20"/>
+ <value name="VFMT_32_32_UINT" value="0x21"/>
+ <value name="VFMT_32_32_32_UINT" value="0x22"/>
+ <value name="VFMT_32_32_32_32_UINT" value="0x23"/>
+ <value name="VFMT_32_SINT" value="0x24"/>
+ <value name="VFMT_32_32_SINT" value="0x25"/>
+ <value name="VFMT_32_32_32_SINT" value="0x26"/>
+ <value name="VFMT_32_32_32_32_SINT" value="0x27"/>
+
+ <value name="VFMT_8_UINT" value="0x28"/>
+ <value name="VFMT_8_8_UINT" value="0x29"/>
+ <value name="VFMT_8_8_8_UINT" value="0x2a"/>
+ <value name="VFMT_8_8_8_8_UINT" value="0x2b"/>
+ <value name="VFMT_8_UNORM" value="0x2c"/>
+ <value name="VFMT_8_8_UNORM" value="0x2d"/>
+ <value name="VFMT_8_8_8_UNORM" value="0x2e"/>
+ <value name="VFMT_8_8_8_8_UNORM" value="0x2f"/>
+ <value name="VFMT_8_SINT" value="0x30"/>
+ <value name="VFMT_8_8_SINT" value="0x31"/>
+ <value name="VFMT_8_8_8_SINT" value="0x32"/>
+ <value name="VFMT_8_8_8_8_SINT" value="0x33"/>
+ <value name="VFMT_8_SNORM" value="0x34"/>
+ <value name="VFMT_8_8_SNORM" value="0x35"/>
+ <value name="VFMT_8_8_8_SNORM" value="0x36"/>
+ <value name="VFMT_8_8_8_8_SNORM" value="0x37"/>
+ <value name="VFMT_10_10_10_2_UINT" value="0x38"/>
+ <value name="VFMT_10_10_10_2_UNORM" value="0x39"/>
+ <value name="VFMT_10_10_10_2_SINT" value="0x3a"/>
+ <value name="VFMT_10_10_10_2_SNORM" value="0x3b"/>
+ <value name="VFMT_2_10_10_10_UINT" value="0x3c"/>
+ <value name="VFMT_2_10_10_10_UNORM" value="0x3d"/>
+ <value name="VFMT_2_10_10_10_SINT" value="0x3e"/>
+ <value name="VFMT_2_10_10_10_SNORM" value="0x3f"/>
+
+ <value name="VFMT_NONE" value="0xff"/>
+</enum>
+
+<enum name="a3xx_tex_fmt">
+ <value name="TFMT_5_6_5_UNORM" value="0x4"/>
+ <value name="TFMT_5_5_5_1_UNORM" value="0x5"/>
+ <value name="TFMT_4_4_4_4_UNORM" value="0x7"/>
+ <value name="TFMT_Z16_UNORM" value="0x9"/>
+ <value name="TFMT_X8Z24_UNORM" value="0xa"/>
+ <value name="TFMT_Z32_FLOAT" value="0xb"/>
+
+ <!--
+ The NV12 tiled/linear formats seem to require gang'd sampler
+ slots (ie. sampler state N plus N+1) for Y and UV planes.
+ They fetch yuv in single sam instruction, but still require
+ colorspace conversion in the shader.
+ -->
+ <value name="TFMT_UV_64X32" value="0x10"/>
+ <value name="TFMT_VU_64X32" value="0x11"/>
+ <value name="TFMT_Y_64X32" value="0x12"/>
+ <value name="TFMT_NV12_64X32" value="0x13"/>
+ <value name="TFMT_UV_LINEAR" value="0x14"/>
+ <value name="TFMT_VU_LINEAR" value="0x15"/>
+ <value name="TFMT_Y_LINEAR" value="0x16"/>
+ <value name="TFMT_NV12_LINEAR" value="0x17"/>
+ <value name="TFMT_I420_Y" value="0x18"/>
+ <value name="TFMT_I420_U" value="0x1a"/>
+ <value name="TFMT_I420_V" value="0x1b"/>
+
+ <value name="TFMT_ATC_RGB" value="0x20"/>
+ <value name="TFMT_ATC_RGBA_EXPLICIT" value="0x21"/>
+ <value name="TFMT_ETC1" value="0x22"/>
+ <value name="TFMT_ATC_RGBA_INTERPOLATED" value="0x23"/>
+
+ <value name="TFMT_DXT1" value="0x24"/>
+ <value name="TFMT_DXT3" value="0x25"/>
+ <value name="TFMT_DXT5" value="0x26"/>
+
+ <value name="TFMT_2_10_10_10_UNORM" value="0x28"/>
+ <value name="TFMT_10_10_10_2_UNORM" value="0x29"/>
+ <value name="TFMT_9_9_9_E5_FLOAT" value="0x2a"/>
+ <value name="TFMT_11_11_10_FLOAT" value="0x2b"/>
+ <value name="TFMT_A8_UNORM" value="0x2c"/> <!-- GL_ALPHA -->
+ <value name="TFMT_L8_UNORM" value="0x2d"/>
+ <value name="TFMT_L8_A8_UNORM" value="0x2f"/> <!-- GL_LUMINANCE_ALPHA -->
+
+ <!--
+ NOTE: GL_ALPHA and GL_LUMINANCE_ALPHA aren't handled in a similar way
+ to float16, float32.. but they seem to use non-standard swizzle too..
+ perhaps we can ditch that if the pattern follows of 0xn0, 0xn1, 0xn2,
+ 0xn3 for 1, 2, 3, 4 components respectively..
+
+ Only formats filled in below are the ones that have been observed by
+ the blob or tested.. you can guess what the missing ones are..
+ -->
+
+ <value name="TFMT_8_UNORM" value="0x30"/> <!-- GL_LUMINANCE -->
+ <value name="TFMT_8_8_UNORM" value="0x31"/>
+ <value name="TFMT_8_8_8_UNORM" value="0x32"/>
+ <value name="TFMT_8_8_8_8_UNORM" value="0x33"/>
+
+ <value name="TFMT_8_SNORM" value="0x34"/>
+ <value name="TFMT_8_8_SNORM" value="0x35"/>
+ <value name="TFMT_8_8_8_SNORM" value="0x36"/>
+ <value name="TFMT_8_8_8_8_SNORM" value="0x37"/>
+
+ <value name="TFMT_8_UINT" value="0x38"/>
+ <value name="TFMT_8_8_UINT" value="0x39"/>
+ <value name="TFMT_8_8_8_UINT" value="0x3a"/>
+ <value name="TFMT_8_8_8_8_UINT" value="0x3b"/>
+
+ <value name="TFMT_8_SINT" value="0x3c"/>
+ <value name="TFMT_8_8_SINT" value="0x3d"/>
+ <value name="TFMT_8_8_8_SINT" value="0x3e"/>
+ <value name="TFMT_8_8_8_8_SINT" value="0x3f"/>
+
+ <value name="TFMT_16_FLOAT" value="0x40"/>
+ <value name="TFMT_16_16_FLOAT" value="0x41"/>
+ <!-- TFMT_FLOAT_16_16_16 -->
+ <value name="TFMT_16_16_16_16_FLOAT" value="0x43"/>
+
+ <value name="TFMT_16_UINT" value="0x44"/>
+ <value name="TFMT_16_16_UINT" value="0x45"/>
+ <value name="TFMT_16_16_16_16_UINT" value="0x47"/>
+
+ <value name="TFMT_16_SINT" value="0x48"/>
+ <value name="TFMT_16_16_SINT" value="0x49"/>
+ <value name="TFMT_16_16_16_16_SINT" value="0x4b"/>
+
+ <value name="TFMT_16_UNORM" value="0x4c"/>
+ <value name="TFMT_16_16_UNORM" value="0x4d"/>
+ <value name="TFMT_16_16_16_16_UNORM" value="0x4f"/>
+
+ <value name="TFMT_16_SNORM" value="0x50"/>
+ <value name="TFMT_16_16_SNORM" value="0x51"/>
+ <value name="TFMT_16_16_16_16_SNORM" value="0x53"/>
+
+ <value name="TFMT_32_FLOAT" value="0x54"/>
+ <value name="TFMT_32_32_FLOAT" value="0x55"/>
+ <!-- TFMT_32_32_32_FLOAT -->
+ <value name="TFMT_32_32_32_32_FLOAT" value="0x57"/>
+
+ <value name="TFMT_32_UINT" value="0x58"/>
+ <value name="TFMT_32_32_UINT" value="0x59"/>
+ <value name="TFMT_32_32_32_32_UINT" value="0x5b"/>
+
+ <value name="TFMT_32_SINT" value="0x5c"/>
+ <value name="TFMT_32_32_SINT" value="0x5d"/>
+ <value name="TFMT_32_32_32_32_SINT" value="0x5f"/>
+
+ <value name="TFMT_2_10_10_10_UINT" value="0x60"/>
+ <value name="TFMT_10_10_10_2_UINT" value="0x61"/>
+
+ <value name="TFMT_ETC2_RG11_SNORM" value="0x70"/>
+ <value name="TFMT_ETC2_RG11_UNORM" value="0x71"/>
+ <value name="TFMT_ETC2_R11_SNORM" value="0x72"/>
+ <value name="TFMT_ETC2_R11_UNORM" value="0x73"/>
+ <value name="TFMT_ETC2_RGBA8" value="0x74"/>
+ <value name="TFMT_ETC2_RGB8A1" value="0x75"/>
+ <value name="TFMT_ETC2_RGB8" value="0x76"/>
+
+ <value name="TFMT_NONE" value="0xff"/>
+</enum>
+
+<enum name="a3xx_color_fmt">
+ <value name="RB_R5G6B5_UNORM" value="0x00"/>
+ <value name="RB_R5G5B5A1_UNORM" value="0x01"/>
+ <value name="RB_R4G4B4A4_UNORM" value="0x03"/>
+ <value name="RB_R8G8B8_UNORM" value="0x04"/>
+ <value name="RB_R8G8B8A8_UNORM" value="0x08"/>
+ <value name="RB_R8G8B8A8_SNORM" value="0x09"/>
+ <value name="RB_R8G8B8A8_UINT" value="0x0a"/>
+ <value name="RB_R8G8B8A8_SINT" value="0x0b"/>
+ <value name="RB_R8G8_UNORM" value="0x0c"/>
+ <value name="RB_R8G8_SNORM" value="0x0d"/>
+ <value name="RB_R8G8_UINT" value="0x0e"/>
+ <value name="RB_R8G8_SINT" value="0x0f"/>
+ <value name="RB_R10G10B10A2_UNORM" value="0x10"/>
+ <value name="RB_A2R10G10B10_UNORM" value="0x11"/>
+ <value name="RB_R10G10B10A2_UINT" value="0x12"/>
+ <value name="RB_A2R10G10B10_UINT" value="0x13"/>
+
+ <value name="RB_A8_UNORM" value="0x14"/>
+ <value name="RB_R8_UNORM" value="0x15"/>
+
+ <value name="RB_R16_FLOAT" value="0x18"/>
+ <value name="RB_R16G16_FLOAT" value="0x19"/>
+ <value name="RB_R16G16B16A16_FLOAT" value="0x1b"/> <!-- GL_HALF_FLOAT_OES -->
+ <value name="RB_R11G11B10_FLOAT" value="0x1c"/>
+
+ <value name="RB_R16_SNORM" value="0x20"/>
+ <value name="RB_R16G16_SNORM" value="0x21"/>
+ <value name="RB_R16G16B16A16_SNORM" value="0x23"/>
+
+ <value name="RB_R16_UNORM" value="0x24"/>
+ <value name="RB_R16G16_UNORM" value="0x25"/>
+ <value name="RB_R16G16B16A16_UNORM" value="0x27"/>
+
+ <value name="RB_R16_SINT" value="0x28"/>
+ <value name="RB_R16G16_SINT" value="0x29"/>
+ <value name="RB_R16G16B16A16_SINT" value="0x2b"/>
+
+ <value name="RB_R16_UINT" value="0x2c"/>
+ <value name="RB_R16G16_UINT" value="0x2d"/>
+ <value name="RB_R16G16B16A16_UINT" value="0x2f"/>
+
+ <value name="RB_R32_FLOAT" value="0x30"/>
+ <value name="RB_R32G32_FLOAT" value="0x31"/>
+ <value name="RB_R32G32B32A32_FLOAT" value="0x33"/> <!-- GL_FLOAT -->
+
+ <value name="RB_R32_SINT" value="0x34"/>
+ <value name="RB_R32G32_SINT" value="0x35"/>
+ <value name="RB_R32G32B32A32_SINT" value="0x37"/>
+
+ <value name="RB_R32_UINT" value="0x38"/>
+ <value name="RB_R32G32_UINT" value="0x39"/>
+ <value name="RB_R32G32B32A32_UINT" value="0x3b"/>
+
+ <value name="RB_NONE" value="0xff"/>
+</enum>
+
+<enum name="a3xx_cp_perfcounter_select">
+ <value value="0x00" name="CP_ALWAYS_COUNT"/>
+ <value value="0x03" name="CP_AHB_PFPTRANS_WAIT"/>
+ <value value="0x06" name="CP_AHB_NRTTRANS_WAIT"/>
+ <value value="0x08" name="CP_CSF_NRT_READ_WAIT"/>
+ <value value="0x09" name="CP_CSF_I1_FIFO_FULL"/>
+ <value value="0x0a" name="CP_CSF_I2_FIFO_FULL"/>
+ <value value="0x0b" name="CP_CSF_ST_FIFO_FULL"/>
+ <value value="0x0c" name="CP_RESERVED_12"/>
+ <value value="0x0d" name="CP_CSF_RING_ROQ_FULL"/>
+ <value value="0x0e" name="CP_CSF_I1_ROQ_FULL"/>
+ <value value="0x0f" name="CP_CSF_I2_ROQ_FULL"/>
+ <value value="0x10" name="CP_CSF_ST_ROQ_FULL"/>
+ <value value="0x11" name="CP_RESERVED_17"/>
+ <value value="0x12" name="CP_MIU_TAG_MEM_FULL"/>
+ <value value="0x16" name="CP_MIU_NRT_WRITE_STALLED"/>
+ <value value="0x17" name="CP_MIU_NRT_READ_STALLED"/>
+ <value value="0x1a" name="CP_ME_REGS_RB_DONE_FIFO_FULL"/>
+ <value value="0x1b" name="CP_ME_REGS_VS_EVENT_FIFO_FULL"/>
+ <value value="0x1c" name="CP_ME_REGS_PS_EVENT_FIFO_FULL"/>
+ <value value="0x1d" name="CP_ME_REGS_CF_EVENT_FIFO_FULL"/>
+ <value value="0x1e" name="CP_ME_MICRO_RB_STARVED"/>
+ <value value="0x28" name="CP_AHB_RBBM_DWORD_SENT"/>
+ <value value="0x29" name="CP_ME_BUSY_CLOCKS"/>
+ <value value="0x2a" name="CP_ME_WAIT_CONTEXT_AVAIL"/>
+ <value value="0x2b" name="CP_PFP_TYPE0_PACKET"/>
+ <value value="0x2c" name="CP_PFP_TYPE3_PACKET"/>
+ <value value="0x2d" name="CP_CSF_RB_WPTR_NEQ_RPTR"/>
+ <value value="0x2e" name="CP_CSF_I1_SIZE_NEQ_ZERO"/>
+ <value value="0x2f" name="CP_CSF_I2_SIZE_NEQ_ZERO"/>
+ <value value="0x30" name="CP_CSF_RBI1I2_FETCHING"/>
+</enum>
+
+<enum name="a3xx_gras_tse_perfcounter_select">
+ <value value="0x00" name="GRAS_TSEPERF_INPUT_PRIM"/>
+ <value value="0x01" name="GRAS_TSEPERF_INPUT_NULL_PRIM"/>
+ <value value="0x02" name="GRAS_TSEPERF_TRIVAL_REJ_PRIM"/>
+ <value value="0x03" name="GRAS_TSEPERF_CLIPPED_PRIM"/>
+ <value value="0x04" name="GRAS_TSEPERF_NEW_PRIM"/>
+ <value value="0x05" name="GRAS_TSEPERF_ZERO_AREA_PRIM"/>
+ <value value="0x06" name="GRAS_TSEPERF_FACENESS_CULLED_PRIM"/>
+ <value value="0x07" name="GRAS_TSEPERF_ZERO_PIXEL_PRIM"/>
+ <value value="0x08" name="GRAS_TSEPERF_OUTPUT_NULL_PRIM"/>
+ <value value="0x09" name="GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM"/>
+ <value value="0x0a" name="GRAS_TSEPERF_PRE_CLIP_PRIM"/>
+ <value value="0x0b" name="GRAS_TSEPERF_POST_CLIP_PRIM"/>
+ <value value="0x0c" name="GRAS_TSEPERF_WORKING_CYCLES"/>
+ <value value="0x0d" name="GRAS_TSEPERF_PC_STARVE"/>
+ <value value="0x0e" name="GRAS_TSERASPERF_STALL"/>
+</enum>
+
+<enum name="a3xx_gras_ras_perfcounter_select">
+ <value value="0x00" name="GRAS_RASPERF_16X16_TILES"/>
+ <value value="0x01" name="GRAS_RASPERF_8X8_TILES"/>
+ <value value="0x02" name="GRAS_RASPERF_4X4_TILES"/>
+ <value value="0x03" name="GRAS_RASPERF_WORKING_CYCLES"/>
+ <value value="0x04" name="GRAS_RASPERF_STALL_CYCLES_BY_RB"/>
+ <value value="0x05" name="GRAS_RASPERF_STALL_CYCLES_BY_VSC"/>
+ <value value="0x06" name="GRAS_RASPERF_STARVE_CYCLES_BY_TSE"/>
+</enum>
+
+<enum name="a3xx_hlsq_perfcounter_select">
+ <value value="0x00" name="HLSQ_PERF_SP_VS_CONSTANT"/>
+ <value value="0x01" name="HLSQ_PERF_SP_VS_INSTRUCTIONS"/>
+ <value value="0x02" name="HLSQ_PERF_SP_FS_CONSTANT"/>
+ <value value="0x03" name="HLSQ_PERF_SP_FS_INSTRUCTIONS"/>
+ <value value="0x04" name="HLSQ_PERF_TP_STATE"/>
+ <value value="0x05" name="HLSQ_PERF_QUADS"/>
+ <value value="0x06" name="HLSQ_PERF_PIXELS"/>
+ <value value="0x07" name="HLSQ_PERF_VERTICES"/>
+ <value value="0x08" name="HLSQ_PERF_FS8_THREADS"/>
+ <value value="0x09" name="HLSQ_PERF_FS16_THREADS"/>
+ <value value="0x0a" name="HLSQ_PERF_FS32_THREADS"/>
+ <value value="0x0b" name="HLSQ_PERF_VS8_THREADS"/>
+ <value value="0x0c" name="HLSQ_PERF_VS16_THREADS"/>
+ <value value="0x0d" name="HLSQ_PERF_SP_VS_DATA_BYTES"/>
+ <value value="0x0e" name="HLSQ_PERF_SP_FS_DATA_BYTES"/>
+ <value value="0x0f" name="HLSQ_PERF_ACTIVE_CYCLES"/>
+ <value value="0x10" name="HLSQ_PERF_STALL_CYCLES_SP_STATE"/>
+ <value value="0x11" name="HLSQ_PERF_STALL_CYCLES_SP_VS"/>
+ <value value="0x12" name="HLSQ_PERF_STALL_CYCLES_SP_FS"/>
+ <value value="0x13" name="HLSQ_PERF_STALL_CYCLES_UCHE"/>
+ <value value="0x14" name="HLSQ_PERF_RBBM_LOAD_CYCLES"/>
+ <value value="0x15" name="HLSQ_PERF_DI_TO_VS_START_SP0"/>
+ <value value="0x16" name="HLSQ_PERF_DI_TO_FS_START_SP0"/>
+ <value value="0x17" name="HLSQ_PERF_VS_START_TO_DONE_SP0"/>
+ <value value="0x18" name="HLSQ_PERF_FS_START_TO_DONE_SP0"/>
+ <value value="0x19" name="HLSQ_PERF_SP_STATE_COPY_CYCLES_VS"/>
+ <value value="0x1a" name="HLSQ_PERF_SP_STATE_COPY_CYCLES_FS"/>
+ <value value="0x1b" name="HLSQ_PERF_UCHE_LATENCY_CYCLES"/>
+ <value value="0x1c" name="HLSQ_PERF_UCHE_LATENCY_COUNT"/>
+</enum>
+
+<enum name="a3xx_pc_perfcounter_select">
+ <value value="0x00" name="PC_PCPERF_VISIBILITY_STREAMS"/>
+ <value value="0x01" name="PC_PCPERF_TOTAL_INSTANCES"/>
+ <value value="0x02" name="PC_PCPERF_PRIMITIVES_PC_VPC"/>
+ <value value="0x03" name="PC_PCPERF_PRIMITIVES_KILLED_BY_VS"/>
+ <value value="0x04" name="PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS"/>
+ <value value="0x05" name="PC_PCPERF_DRAWCALLS_KILLED_BY_VS"/>
+ <value value="0x06" name="PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS"/>
+ <value value="0x07" name="PC_PCPERF_VERTICES_TO_VFD"/>
+ <value value="0x08" name="PC_PCPERF_REUSED_VERTICES"/>
+ <value value="0x09" name="PC_PCPERF_CYCLES_STALLED_BY_VFD"/>
+ <value value="0x0a" name="PC_PCPERF_CYCLES_STALLED_BY_TSE"/>
+ <value value="0x0b" name="PC_PCPERF_CYCLES_STALLED_BY_VBIF"/>
+ <value value="0x0c" name="PC_PCPERF_CYCLES_IS_WORKING"/>
+</enum>
+
+<enum name="a3xx_rb_perfcounter_select">
+ <value value="0x00" name="RB_RBPERF_ACTIVE_CYCLES_ANY"/>
+ <value value="0x01" name="RB_RBPERF_ACTIVE_CYCLES_ALL"/>
+ <value value="0x02" name="RB_RBPERF_STARVE_CYCLES_BY_SP"/>
+ <value value="0x03" name="RB_RBPERF_STARVE_CYCLES_BY_RAS"/>
+ <value value="0x04" name="RB_RBPERF_STARVE_CYCLES_BY_MARB"/>
+ <value value="0x05" name="RB_RBPERF_STALL_CYCLES_BY_MARB"/>
+ <value value="0x06" name="RB_RBPERF_STALL_CYCLES_BY_HLSQ"/>
+ <value value="0x07" name="RB_RBPERF_RB_MARB_DATA"/>
+ <value value="0x08" name="RB_RBPERF_SP_RB_QUAD"/>
+ <value value="0x09" name="RB_RBPERF_RAS_EARLY_Z_QUADS"/>
+ <value value="0x0a" name="RB_RBPERF_GMEM_CH0_READ"/>
+ <value value="0x0b" name="RB_RBPERF_GMEM_CH1_READ"/>
+ <value value="0x0c" name="RB_RBPERF_GMEM_CH0_WRITE"/>
+ <value value="0x0d" name="RB_RBPERF_GMEM_CH1_WRITE"/>
+ <value value="0x0e" name="RB_RBPERF_CP_CONTEXT_DONE"/>
+ <value value="0x0f" name="RB_RBPERF_CP_CACHE_FLUSH"/>
+ <value value="0x10" name="RB_RBPERF_CP_ZPASS_DONE"/>
+</enum>
+
+<enum name="a3xx_rbbm_perfcounter_select">
+ <value value="0" name="RBBM_ALAWYS_ON"/>
+ <value value="1" name="RBBM_VBIF_BUSY"/>
+ <value value="2" name="RBBM_TSE_BUSY"/>
+ <value value="3" name="RBBM_RAS_BUSY"/>
+ <value value="4" name="RBBM_PC_DCALL_BUSY"/>
+ <value value="5" name="RBBM_PC_VSD_BUSY"/>
+ <value value="6" name="RBBM_VFD_BUSY"/>
+ <value value="7" name="RBBM_VPC_BUSY"/>
+ <value value="8" name="RBBM_UCHE_BUSY"/>
+ <value value="9" name="RBBM_VSC_BUSY"/>
+ <value value="10" name="RBBM_HLSQ_BUSY"/>
+ <value value="11" name="RBBM_ANY_RB_BUSY"/>
+ <value value="12" name="RBBM_ANY_TEX_BUSY"/>
+ <value value="13" name="RBBM_ANY_USP_BUSY"/>
+ <value value="14" name="RBBM_ANY_MARB_BUSY"/>
+ <value value="15" name="RBBM_ANY_ARB_BUSY"/>
+ <value value="16" name="RBBM_AHB_STATUS_BUSY"/>
+ <value value="17" name="RBBM_AHB_STATUS_STALLED"/>
+ <value value="18" name="RBBM_AHB_STATUS_TXFR"/>
+ <value value="19" name="RBBM_AHB_STATUS_TXFR_SPLIT"/>
+ <value value="20" name="RBBM_AHB_STATUS_TXFR_ERROR"/>
+ <value value="21" name="RBBM_AHB_STATUS_LONG_STALL"/>
+ <value value="22" name="RBBM_RBBM_STATUS_MASKED"/>
+</enum>
+
+<enum name="a3xx_sp_perfcounter_select">
+ <value value="0x00" name="SP_LM_LOAD_INSTRUCTIONS"/>
+ <value value="0x01" name="SP_LM_STORE_INSTRUCTIONS"/>
+ <value value="0x02" name="SP_LM_ATOMICS"/>
+ <value value="0x03" name="SP_UCHE_LOAD_INSTRUCTIONS"/>
+ <value value="0x04" name="SP_UCHE_STORE_INSTRUCTIONS"/>
+ <value value="0x05" name="SP_UCHE_ATOMICS"/>
+ <value value="0x06" name="SP_VS_TEX_INSTRUCTIONS"/>
+ <value value="0x07" name="SP_VS_CFLOW_INSTRUCTIONS"/>
+ <value value="0x08" name="SP_VS_EFU_INSTRUCTIONS"/>
+ <value value="0x09" name="SP_VS_FULL_ALU_INSTRUCTIONS"/>
+ <value value="0x0a" name="SP_VS_HALF_ALU_INSTRUCTIONS"/>
+ <value value="0x0b" name="SP_FS_TEX_INSTRUCTIONS"/>
+ <value value="0x0c" name="SP_FS_CFLOW_INSTRUCTIONS"/>
+ <value value="0x0d" name="SP_FS_EFU_INSTRUCTIONS"/>
+ <value value="0x0e" name="SP_FS_FULL_ALU_INSTRUCTIONS"/>
+ <value value="0x0f" name="SP_FS_HALF_ALU_INSTRUCTIONS"/>
+ <value value="0x10" name="SP_FS_BARY_INSTRUCTIONS"/>
+ <value value="0x11" name="SP_VS_INSTRUCTIONS"/>
+ <value value="0x12" name="SP_FS_INSTRUCTIONS"/>
+ <value value="0x13" name="SP_ADDR_LOCK_COUNT"/>
+ <value value="0x14" name="SP_UCHE_READ_TRANS"/>
+ <value value="0x15" name="SP_UCHE_WRITE_TRANS"/>
+ <value value="0x16" name="SP_EXPORT_VPC_TRANS"/>
+ <value value="0x17" name="SP_EXPORT_RB_TRANS"/>
+ <value value="0x18" name="SP_PIXELS_KILLED"/>
+ <value value="0x19" name="SP_ICL1_REQUESTS"/>
+ <value value="0x1a" name="SP_ICL1_MISSES"/>
+ <value value="0x1b" name="SP_ICL0_REQUESTS"/>
+ <value value="0x1c" name="SP_ICL0_MISSES"/>
+ <value value="0x1d" name="SP_ALU_ACTIVE_CYCLES"/>
+ <value value="0x1e" name="SP_EFU_ACTIVE_CYCLES"/>
+ <value value="0x1f" name="SP_STALL_CYCLES_BY_VPC"/>
+ <value value="0x20" name="SP_STALL_CYCLES_BY_TP"/>
+ <value value="0x21" name="SP_STALL_CYCLES_BY_UCHE"/>
+ <value value="0x22" name="SP_STALL_CYCLES_BY_RB"/>
+ <value value="0x23" name="SP_ACTIVE_CYCLES_ANY"/>
+ <value value="0x24" name="SP_ACTIVE_CYCLES_ALL"/>
+</enum>
+
+<enum name="a3xx_tp_perfcounter_select">
+ <value value="0x00" name="TPL1_TPPERF_L1_REQUESTS"/>
+ <value value="0x01" name="TPL1_TPPERF_TP0_L1_REQUESTS"/>
+ <value value="0x02" name="TPL1_TPPERF_TP0_L1_MISSES"/>
+ <value value="0x03" name="TPL1_TPPERF_TP1_L1_REQUESTS"/>
+ <value value="0x04" name="TPL1_TPPERF_TP1_L1_MISSES"/>
+ <value value="0x05" name="TPL1_TPPERF_TP2_L1_REQUESTS"/>
+ <value value="0x06" name="TPL1_TPPERF_TP2_L1_MISSES"/>
+ <value value="0x07" name="TPL1_TPPERF_TP3_L1_REQUESTS"/>
+ <value value="0x08" name="TPL1_TPPERF_TP3_L1_MISSES"/>
+ <value value="0x09" name="TPL1_TPPERF_OUTPUT_TEXELS_POINT"/>
+ <value value="0x0a" name="TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR"/>
+ <value value="0x0b" name="TPL1_TPPERF_OUTPUT_TEXELS_MIP"/>
+ <value value="0x0c" name="TPL1_TPPERF_OUTPUT_TEXELS_ANISO"/>
+ <value value="0x0d" name="TPL1_TPPERF_BILINEAR_OPS"/>
+ <value value="0x0e" name="TPL1_TPPERF_QUADSQUADS_OFFSET"/>
+ <value value="0x0f" name="TPL1_TPPERF_QUADQUADS_SHADOW"/>
+ <value value="0x10" name="TPL1_TPPERF_QUADS_ARRAY"/>
+ <value value="0x11" name="TPL1_TPPERF_QUADS_PROJECTION"/>
+ <value value="0x12" name="TPL1_TPPERF_QUADS_GRADIENT"/>
+ <value value="0x13" name="TPL1_TPPERF_QUADS_1D2D"/>
+ <value value="0x14" name="TPL1_TPPERF_QUADS_3DCUBE"/>
+ <value value="0x15" name="TPL1_TPPERF_ZERO_LOD"/>
+ <value value="0x16" name="TPL1_TPPERF_OUTPUT_TEXELS"/>
+ <value value="0x17" name="TPL1_TPPERF_ACTIVE_CYCLES_ANY"/>
+ <value value="0x18" name="TPL1_TPPERF_ACTIVE_CYCLES_ALL"/>
+ <value value="0x19" name="TPL1_TPPERF_STALL_CYCLES_BY_ARB"/>
+ <value value="0x1a" name="TPL1_TPPERF_LATENCY"/>
+ <value value="0x1b" name="TPL1_TPPERF_LATENCY_TRANS"/>
+</enum>
+
+<enum name="a3xx_vfd_perfcounter_select">
+ <value value="0" name="VFD_PERF_UCHE_BYTE_FETCHED"/>
+ <value value="1" name="VFD_PERF_UCHE_TRANS"/>
+ <value value="2" name="VFD_PERF_VPC_BYPASS_COMPONENTS"/>
+ <value value="3" name="VFD_PERF_FETCH_INSTRUCTIONS"/>
+ <value value="4" name="VFD_PERF_DECODE_INSTRUCTIONS"/>
+ <value value="5" name="VFD_PERF_ACTIVE_CYCLES"/>
+ <value value="6" name="VFD_PERF_STALL_CYCLES_UCHE"/>
+ <value value="7" name="VFD_PERF_STALL_CYCLES_HLSQ"/>
+ <value value="8" name="VFD_PERF_STALL_CYCLES_VPC_BYPASS"/>
+ <value value="9" name="VFD_PERF_STALL_CYCLES_VPC_ALLOC"/>
+</enum>
+
+<enum name="a3xx_vpc_perfcounter_select">
+ <value value="0" name="VPC_PERF_SP_LM_PRIMITIVES"/>
+ <value value="1" name="VPC_PERF_COMPONENTS_FROM_SP"/>
+ <value value="2" name="VPC_PERF_SP_LM_COMPONENTS"/>
+ <value value="3" name="VPC_PERF_ACTIVE_CYCLES"/>
+ <value value="4" name="VPC_PERF_STALL_CYCLES_LM"/>
+ <value value="5" name="VPC_PERF_STALL_CYCLES_RAS"/>
+</enum>
+
+<enum name="a3xx_uche_perfcounter_select">
+ <value value="0x00" name="UCHE_UCHEPERF_VBIF_READ_BEATS_TP"/>
+ <value value="0x01" name="UCHE_UCHEPERF_VBIF_READ_BEATS_VFD"/>
+ <value value="0x02" name="UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ"/>
+ <value value="0x03" name="UCHE_UCHEPERF_VBIF_READ_BEATS_MARB"/>
+ <value value="0x04" name="UCHE_UCHEPERF_VBIF_READ_BEATS_SP"/>
+ <value value="0x08" name="UCHE_UCHEPERF_READ_REQUESTS_TP"/>
+ <value value="0x09" name="UCHE_UCHEPERF_READ_REQUESTS_VFD"/>
+ <value value="0x0a" name="UCHE_UCHEPERF_READ_REQUESTS_HLSQ"/>
+ <value value="0x0b" name="UCHE_UCHEPERF_READ_REQUESTS_MARB"/>
+ <value value="0x0c" name="UCHE_UCHEPERF_READ_REQUESTS_SP"/>
+ <value value="0x0d" name="UCHE_UCHEPERF_WRITE_REQUESTS_MARB"/>
+ <value value="0x0e" name="UCHE_UCHEPERF_WRITE_REQUESTS_SP"/>
+ <value value="0x0f" name="UCHE_UCHEPERF_TAG_CHECK_FAILS"/>
+ <value value="0x10" name="UCHE_UCHEPERF_EVICTS"/>
+ <value value="0x11" name="UCHE_UCHEPERF_FLUSHES"/>
+ <value value="0x12" name="UCHE_UCHEPERF_VBIF_LATENCY_CYCLES"/>
+ <value value="0x13" name="UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES"/>
+ <value value="0x14" name="UCHE_UCHEPERF_ACTIVE_CYCLES"/>
+</enum>
+
+<enum name="a3xx_intp_mode">
+ <value name="SMOOTH" value="0"/>
+ <value name="FLAT" value="1"/>
+ <value name="ZERO" value="2"/>
+ <value name="ONE" value="3"/>
+</enum>
+
+<enum name="a3xx_repl_mode">
+ <value name="S" value="1"/>
+ <value name="T" value="2"/>
+ <value name="ONE_T" value="3"/>
+</enum>
+
+<domain name="A3XX" width="32">
+ <!-- RBBM registers -->
+ <reg32 offset="0x0000" name="RBBM_HW_VERSION"/>
+ <reg32 offset="0x0001" name="RBBM_HW_RELEASE"/>
+ <reg32 offset="0x0002" name="RBBM_HW_CONFIGURATION"/>
+ <reg32 offset="0x0010" name="RBBM_CLOCK_CTL"/>
+ <reg32 offset="0x0012" name="RBBM_SP_HYST_CNT"/>
+ <reg32 offset="0x0018" name="RBBM_SW_RESET_CMD"/>
+ <reg32 offset="0x0020" name="RBBM_AHB_CTL0"/>
+ <reg32 offset="0x0021" name="RBBM_AHB_CTL1"/>
+ <reg32 offset="0x0022" name="RBBM_AHB_CMD"/>
+ <reg32 offset="0x0027" name="RBBM_AHB_ERROR_STATUS"/>
+ <reg32 offset="0x002e" name="RBBM_GPR0_CTL"/>
+ <reg32 offset="0x0030" name="RBBM_STATUS">
+ <bitfield name="HI_BUSY" pos="0" type="boolean"/>
+ <bitfield name="CP_ME_BUSY" pos="1" type="boolean"/>
+ <bitfield name="CP_PFP_BUSY" pos="2" type="boolean"/>
+ <bitfield name="CP_NRT_BUSY" pos="14" type="boolean"/>
+ <bitfield name="VBIF_BUSY" pos="15" type="boolean"/>
+ <bitfield name="TSE_BUSY" pos="16" type="boolean"/>
+ <bitfield name="RAS_BUSY" pos="17" type="boolean"/>
+ <bitfield name="RB_BUSY" pos="18" type="boolean"/>
+ <bitfield name="PC_DCALL_BUSY" pos="19" type="boolean"/>
+ <bitfield name="PC_VSD_BUSY" pos="20" type="boolean"/>
+ <bitfield name="VFD_BUSY" pos="21" type="boolean"/>
+ <bitfield name="VPC_BUSY" pos="22" type="boolean"/>
+ <bitfield name="UCHE_BUSY" pos="23" type="boolean"/>
+ <bitfield name="SP_BUSY" pos="24" type="boolean"/>
+ <bitfield name="TPL1_BUSY" pos="25" type="boolean"/>
+ <bitfield name="MARB_BUSY" pos="26" type="boolean"/>
+ <bitfield name="VSC_BUSY" pos="27" type="boolean"/>
+ <bitfield name="ARB_BUSY" pos="28" type="boolean"/>
+ <bitfield name="HLSQ_BUSY" pos="29" type="boolean"/>
+ <bitfield name="GPU_BUSY_NOHC" pos="30" type="boolean"/>
+ <bitfield name="GPU_BUSY" pos="31" type="boolean"/>
+ </reg32>
+ <!-- used in fw CP_WAIT_FOR_IDLE, similar to NQWAIT_UNTIL on a2xx: -->
+ <reg32 offset="0x0040" name="RBBM_NQWAIT_UNTIL"/>
+ <reg32 offset="0x0033" name="RBBM_WAIT_IDLE_CLOCKS_CTL"/>
+ <reg32 offset="0x0050" name="RBBM_INTERFACE_HANG_INT_CTL"/>
+ <reg32 offset="0x0051" name="RBBM_INTERFACE_HANG_MASK_CTL0"/>
+ <reg32 offset="0x0054" name="RBBM_INTERFACE_HANG_MASK_CTL1"/>
+ <reg32 offset="0x0057" name="RBBM_INTERFACE_HANG_MASK_CTL2"/>
+ <reg32 offset="0x005a" name="RBBM_INTERFACE_HANG_MASK_CTL3"/>
+
+ <bitset name="A3XX_INT0">
+ <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
+ <bitfield name="RBBM_AHB_ERROR" pos="1" type="boolean"/>
+ <bitfield name="RBBM_REG_TIMEOUT" pos="2" type="boolean"/>
+ <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3" type="boolean"/>
+ <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4" type="boolean"/>
+ <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="5" type="boolean"/>
+ <bitfield name="VFD_ERROR" pos="6" type="boolean"/>
+ <bitfield name="CP_SW_INT" pos="7" type="boolean"/>
+ <bitfield name="CP_T0_PACKET_IN_IB" pos="8" type="boolean"/>
+ <bitfield name="CP_OPCODE_ERROR" pos="9" type="boolean"/>
+ <bitfield name="CP_RESERVED_BIT_ERROR" pos="10" type="boolean"/>
+ <bitfield name="CP_HW_FAULT" pos="11" type="boolean"/>
+ <bitfield name="CP_DMA" pos="12" type="boolean"/>
+ <bitfield name="CP_IB2_INT" pos="13" type="boolean"/>
+ <bitfield name="CP_IB1_INT" pos="14" type="boolean"/>
+ <bitfield name="CP_RB_INT" pos="15" type="boolean"/>
+ <bitfield name="CP_REG_PROTECT_FAULT" pos="16" type="boolean"/>
+ <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
+ <bitfield name="CP_VS_DONE_TS" pos="18" type="boolean"/>
+ <bitfield name="CP_PS_DONE_TS" pos="19" type="boolean"/>
+ <bitfield name="CACHE_FLUSH_TS" pos="20" type="boolean"/>
+ <bitfield name="CP_AHB_ERROR_HALT" pos="21" type="boolean"/>
+ <bitfield name="MISC_HANG_DETECT" pos="24" type="boolean"/>
+ <bitfield name="UCHE_OOB_ACCESS" pos="25" type="boolean"/>
+ </bitset>
+
+
+ <!--
+ set in pm4 fw INVALID_JUMP_TABLE_ENTRY and CP_INTERRUPT (compare
+ to CP_INT_STATUS in a2xx firmware), so this seems to be the a3xx
+ way for fw to raise and irq:
+ -->
+ <reg32 offset="0x0060" name="RBBM_INT_SET_CMD" type="A3XX_INT0"/>
+ <reg32 offset="0x0061" name="RBBM_INT_CLEAR_CMD" type="A3XX_INT0"/>
+ <reg32 offset="0x0063" name="RBBM_INT_0_MASK" type="A3XX_INT0"/>
+ <reg32 offset="0x0064" name="RBBM_INT_0_STATUS" type="A3XX_INT0"/>
+ <reg32 offset="0x0080" name="RBBM_PERFCTR_CTL">
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0081" name="RBBM_PERFCTR_LOAD_CMD0"/>
+ <reg32 offset="0x0082" name="RBBM_PERFCTR_LOAD_CMD1"/>
+ <reg32 offset="0x0084" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
+ <reg32 offset="0x0085" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
+ <reg32 offset="0x0086" name="RBBM_PERFCOUNTER0_SELECT" type="a3xx_rbbm_perfcounter_select"/>
+ <reg32 offset="0x0087" name="RBBM_PERFCOUNTER1_SELECT" type="a3xx_rbbm_perfcounter_select"/>
+ <reg32 offset="0x0088" name="RBBM_GPU_BUSY_MASKED"/>
+ <reg32 offset="0x0090" name="RBBM_PERFCTR_CP_0_LO"/>
+ <reg32 offset="0x0091" name="RBBM_PERFCTR_CP_0_HI"/>
+ <reg32 offset="0x0092" name="RBBM_PERFCTR_RBBM_0_LO"/>
+ <reg32 offset="0x0093" name="RBBM_PERFCTR_RBBM_0_HI"/>
+ <reg32 offset="0x0094" name="RBBM_PERFCTR_RBBM_1_LO"/>
+ <reg32 offset="0x0095" name="RBBM_PERFCTR_RBBM_1_HI"/>
+ <reg32 offset="0x0096" name="RBBM_PERFCTR_PC_0_LO"/>
+ <reg32 offset="0x0097" name="RBBM_PERFCTR_PC_0_HI"/>
+ <reg32 offset="0x0098" name="RBBM_PERFCTR_PC_1_LO"/>
+ <reg32 offset="0x0099" name="RBBM_PERFCTR_PC_1_HI"/>
+ <reg32 offset="0x009a" name="RBBM_PERFCTR_PC_2_LO"/>
+ <reg32 offset="0x009b" name="RBBM_PERFCTR_PC_2_HI"/>
+ <reg32 offset="0x009c" name="RBBM_PERFCTR_PC_3_LO"/>
+ <reg32 offset="0x009d" name="RBBM_PERFCTR_PC_3_HI"/>
+ <reg32 offset="0x009e" name="RBBM_PERFCTR_VFD_0_LO"/>
+ <reg32 offset="0x009f" name="RBBM_PERFCTR_VFD_0_HI"/>
+ <reg32 offset="0x00a0" name="RBBM_PERFCTR_VFD_1_LO"/>
+ <reg32 offset="0x00a1" name="RBBM_PERFCTR_VFD_1_HI"/>
+ <reg32 offset="0x00a2" name="RBBM_PERFCTR_HLSQ_0_LO"/>
+ <reg32 offset="0x00a3" name="RBBM_PERFCTR_HLSQ_0_HI"/>
+ <reg32 offset="0x00a4" name="RBBM_PERFCTR_HLSQ_1_LO"/>
+ <reg32 offset="0x00a5" name="RBBM_PERFCTR_HLSQ_1_HI"/>
+ <reg32 offset="0x00a6" name="RBBM_PERFCTR_HLSQ_2_LO"/>
+ <reg32 offset="0x00a7" name="RBBM_PERFCTR_HLSQ_2_HI"/>
+ <reg32 offset="0x00a8" name="RBBM_PERFCTR_HLSQ_3_LO"/>
+ <reg32 offset="0x00a9" name="RBBM_PERFCTR_HLSQ_3_HI"/>
+ <reg32 offset="0x00aa" name="RBBM_PERFCTR_HLSQ_4_LO"/>
+ <reg32 offset="0x00ab" name="RBBM_PERFCTR_HLSQ_4_HI"/>
+ <reg32 offset="0x00ac" name="RBBM_PERFCTR_HLSQ_5_LO"/>
+ <reg32 offset="0x00ad" name="RBBM_PERFCTR_HLSQ_5_HI"/>
+ <reg32 offset="0x00ae" name="RBBM_PERFCTR_VPC_0_LO"/>
+ <reg32 offset="0x00af" name="RBBM_PERFCTR_VPC_0_HI"/>
+ <reg32 offset="0x00b0" name="RBBM_PERFCTR_VPC_1_LO"/>
+ <reg32 offset="0x00b1" name="RBBM_PERFCTR_VPC_1_HI"/>
+ <reg32 offset="0x00b2" name="RBBM_PERFCTR_TSE_0_LO"/>
+ <reg32 offset="0x00b3" name="RBBM_PERFCTR_TSE_0_HI"/>
+ <reg32 offset="0x00b4" name="RBBM_PERFCTR_TSE_1_LO"/>
+ <reg32 offset="0x00b5" name="RBBM_PERFCTR_TSE_1_HI"/>
+ <reg32 offset="0x00b6" name="RBBM_PERFCTR_RAS_0_LO"/>
+ <reg32 offset="0x00b7" name="RBBM_PERFCTR_RAS_0_HI"/>
+ <reg32 offset="0x00b8" name="RBBM_PERFCTR_RAS_1_LO"/>
+ <reg32 offset="0x00b9" name="RBBM_PERFCTR_RAS_1_HI"/>
+ <reg32 offset="0x00ba" name="RBBM_PERFCTR_UCHE_0_LO"/>
+ <reg32 offset="0x00bb" name="RBBM_PERFCTR_UCHE_0_HI"/>
+ <reg32 offset="0x00bc" name="RBBM_PERFCTR_UCHE_1_LO"/>
+ <reg32 offset="0x00bd" name="RBBM_PERFCTR_UCHE_1_HI"/>
+ <reg32 offset="0x00be" name="RBBM_PERFCTR_UCHE_2_LO"/>
+ <reg32 offset="0x00bf" name="RBBM_PERFCTR_UCHE_2_HI"/>
+ <reg32 offset="0x00c0" name="RBBM_PERFCTR_UCHE_3_LO"/>
+ <reg32 offset="0x00c1" name="RBBM_PERFCTR_UCHE_3_HI"/>
+ <reg32 offset="0x00c2" name="RBBM_PERFCTR_UCHE_4_LO"/>
+ <reg32 offset="0x00c3" name="RBBM_PERFCTR_UCHE_4_HI"/>
+ <reg32 offset="0x00c4" name="RBBM_PERFCTR_UCHE_5_LO"/>
+ <reg32 offset="0x00c5" name="RBBM_PERFCTR_UCHE_5_HI"/>
+ <reg32 offset="0x00c6" name="RBBM_PERFCTR_TP_0_LO"/>
+ <reg32 offset="0x00c7" name="RBBM_PERFCTR_TP_0_HI"/>
+ <reg32 offset="0x00c8" name="RBBM_PERFCTR_TP_1_LO"/>
+ <reg32 offset="0x00c9" name="RBBM_PERFCTR_TP_1_HI"/>
+ <reg32 offset="0x00ca" name="RBBM_PERFCTR_TP_2_LO"/>
+ <reg32 offset="0x00cb" name="RBBM_PERFCTR_TP_2_HI"/>
+ <reg32 offset="0x00cc" name="RBBM_PERFCTR_TP_3_LO"/>
+ <reg32 offset="0x00cd" name="RBBM_PERFCTR_TP_3_HI"/>
+ <reg32 offset="0x00ce" name="RBBM_PERFCTR_TP_4_LO"/>
+ <reg32 offset="0x00cf" name="RBBM_PERFCTR_TP_4_HI"/>
+ <reg32 offset="0x00d0" name="RBBM_PERFCTR_TP_5_LO"/>
+ <reg32 offset="0x00d1" name="RBBM_PERFCTR_TP_5_HI"/>
+ <reg32 offset="0x00d2" name="RBBM_PERFCTR_SP_0_LO"/>
+ <reg32 offset="0x00d3" name="RBBM_PERFCTR_SP_0_HI"/>
+ <reg32 offset="0x00d4" name="RBBM_PERFCTR_SP_1_LO"/>
+ <reg32 offset="0x00d5" name="RBBM_PERFCTR_SP_1_HI"/>
+ <reg32 offset="0x00d6" name="RBBM_PERFCTR_SP_2_LO"/>
+ <reg32 offset="0x00d7" name="RBBM_PERFCTR_SP_2_HI"/>
+ <reg32 offset="0x00d8" name="RBBM_PERFCTR_SP_3_LO"/>
+ <reg32 offset="0x00d9" name="RBBM_PERFCTR_SP_3_HI"/>
+ <reg32 offset="0x00da" name="RBBM_PERFCTR_SP_4_LO"/>
+ <reg32 offset="0x00db" name="RBBM_PERFCTR_SP_4_HI"/>
+ <reg32 offset="0x00dc" name="RBBM_PERFCTR_SP_5_LO"/>
+ <reg32 offset="0x00dd" name="RBBM_PERFCTR_SP_5_HI"/>
+ <reg32 offset="0x00de" name="RBBM_PERFCTR_SP_6_LO"/>
+ <reg32 offset="0x00df" name="RBBM_PERFCTR_SP_6_HI"/>
+ <reg32 offset="0x00e0" name="RBBM_PERFCTR_SP_7_LO"/>
+ <reg32 offset="0x00e1" name="RBBM_PERFCTR_SP_7_HI"/>
+ <reg32 offset="0x00e2" name="RBBM_PERFCTR_RB_0_LO"/>
+ <reg32 offset="0x00e3" name="RBBM_PERFCTR_RB_0_HI"/>
+ <reg32 offset="0x00e4" name="RBBM_PERFCTR_RB_1_LO"/>
+ <reg32 offset="0x00e5" name="RBBM_PERFCTR_RB_1_HI"/>
+ <reg32 offset="0x00ea" name="RBBM_PERFCTR_PWR_0_LO"/>
+ <reg32 offset="0x00eb" name="RBBM_PERFCTR_PWR_0_HI"/>
+ <reg32 offset="0x00ec" name="RBBM_PERFCTR_PWR_1_LO"/>
+ <reg32 offset="0x00ed" name="RBBM_PERFCTR_PWR_1_HI"/>
+ <reg32 offset="0x0100" name="RBBM_RBBM_CTL"/>
+ <reg32 offset="0x0111" name="RBBM_DEBUG_BUS_CTL"/>
+ <reg32 offset="0x0112" name="RBBM_DEBUG_BUS_DATA_STATUS"/>
+
+ <!-- CP registers -->
+ <reg32 offset="0x01c9" name="CP_PFP_UCODE_ADDR"/>
+ <reg32 offset="0x01ca" name="CP_PFP_UCODE_DATA"/>
+ <reg32 offset="0x01cc" name="CP_ROQ_ADDR"/>
+ <reg32 offset="0x01cd" name="CP_ROQ_DATA"/>
+ <reg32 offset="0x01d1" name="CP_MERCIU_ADDR"/>
+ <reg32 offset="0x01d2" name="CP_MERCIU_DATA"/>
+ <reg32 offset="0x01d3" name="CP_MERCIU_DATA2"/>
+ <!-- see a3xx_snapshot_cp_meq().. looks like the way to dump queue between pfp and pm4 -->
+ <reg32 offset="0x01da" name="CP_MEQ_ADDR"/>
+ <reg32 offset="0x01db" name="CP_MEQ_DATA"/>
+ <reg32 offset="0x01f5" name="CP_WFI_PEND_CTR"/>
+ <reg32 offset="0x039d" name="RBBM_PM_OVERRIDE2"/>
+
+ <reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT" type="a3xx_cp_perfcounter_select"/>
+ <reg32 offset="0x045c" name="CP_HW_FAULT"/>
+ <reg32 offset="0x045e" name="CP_PROTECT_CTRL"/>
+ <reg32 offset="0x045f" name="CP_PROTECT_STATUS"/>
+ <array offset="0x0460" name="CP_PROTECT" stride="1" length="16">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <reg32 offset="0x054d" name="CP_AHB_FAULT"/>
+
+ <reg32 offset="0x0d00" name="SQ_GPR_MANAGEMENT"/>
+ <reg32 offset="0x0d02" name="SQ_INST_STORE_MANAGMENT"/>
+ <reg32 offset="0x0e1e" name="TP0_CHICKEN"/>
+
+ <!-- these I guess or either SP or HLSQ since related to shader core setup: -->
+ <reg32 offset="0x0e22" name="SP_GLOBAL_MEM_SIZE" type="uint">
+ <doc>
+ The pair of MEM_SIZE/ADDR registers get programmed
+ in sequence with the size/addr of each buffer.
+ </doc>
+ </reg32>
+ <reg32 offset="0x0e23" name="SP_GLOBAL_MEM_ADDR"/>
+
+ <!-- GRAS registers -->
+ <reg32 offset="0x2040" name="GRAS_CL_CLIP_CNTL">
+ <bitfield name="IJ_PERSP_CENTER" pos="12" type="boolean"/>
+ <bitfield name="IJ_NON_PERSP_CENTER" pos="13" type="boolean"/>
+ <bitfield name="IJ_PERSP_CENTROID" pos="14" type="boolean"/>
+ <bitfield name="IJ_NON_PERSP_CENTROID" pos="15" type="boolean"/>
+ <bitfield name="CLIP_DISABLE" pos="16" type="boolean"/>
+ <bitfield name="ZFAR_CLIP_DISABLE" pos="17" type="boolean"/>
+ <bitfield name="VP_CLIP_CODE_IGNORE" pos="19" type="boolean"/>
+ <bitfield name="VP_XFORM_DISABLE" pos="20" type="boolean"/>
+ <bitfield name="PERSP_DIVISION_DISABLE" pos="21" type="boolean"/>
+ <bitfield name="ZERO_GB_SCALE_Z" pos="22" type="boolean">
+ <doc>aka clip_halfz</doc>
+ </bitfield>
+ <!-- set when gl_FragCoord.z is enabled in frag shader: -->
+ <bitfield name="ZCOORD" pos="23" type="boolean"/>
+ <bitfield name="WCOORD" pos="24" type="boolean"/>
+ <!-- set when frag shader writes z (so early z test disabled: -->
+ <bitfield name="ZCLIP_DISABLE" pos="25" type="boolean"/>
+ <bitfield name="NUM_USER_CLIP_PLANES" low="26" high="28" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2044" name="GRAS_CL_GB_CLIP_ADJ">
+ <bitfield name="HORZ" low="0" high="9" type="uint"/>
+ <bitfield name="VERT" low="10" high="19" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2048" name="GRAS_CL_VPORT_XOFFSET" type="float"/>
+ <reg32 offset="0x2049" name="GRAS_CL_VPORT_XSCALE" type="float"/>
+ <reg32 offset="0x204a" name="GRAS_CL_VPORT_YOFFSET" type="float"/>
+ <reg32 offset="0x204b" name="GRAS_CL_VPORT_YSCALE" type="float"/>
+ <reg32 offset="0x204c" name="GRAS_CL_VPORT_ZOFFSET" type="float"/>
+ <reg32 offset="0x204d" name="GRAS_CL_VPORT_ZSCALE" type="float"/>
+ <reg32 offset="0x2068" name="GRAS_SU_POINT_MINMAX">
+ <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
+ <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
+ </reg32>
+ <reg32 offset="0x2069" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
+ <reg32 offset="0x206c" name="GRAS_SU_POLY_OFFSET_SCALE">
+ <bitfield name="VAL" low="0" high="23" type="fixed" radix="20"/>
+ <doc>range of -8.0 to 8.0</doc>
+ </reg32>
+ <reg32 offset="0x206d" name="GRAS_SU_POLY_OFFSET_OFFSET" radix="6" type="fixed">
+ <doc>range of -512.0 to 512.0</doc>
+ </reg32>
+ <reg32 offset="0x2070" name="GRAS_SU_MODE_CONTROL">
+ <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
+ <bitfield name="CULL_BACK" pos="1" type="boolean"/>
+ <bitfield name="FRONT_CW" pos="2" type="boolean"/>
+ <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
+ <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2072" name="GRAS_SC_CONTROL">
+ <!-- complete wild-ass-guess for sizes of these bitfields.. -->
+ <bitfield name="RENDER_MODE" low="4" high="7" type="a3xx_render_mode"/>
+ <bitfield name="MSAA_SAMPLES" low="8" high="11" type="a3xx_msaa_samples"/>
+ <bitfield name="RASTER_MODE" low="12" high="15"/>
+ </reg32>
+
+ <reg32 offset="0x2074" name="GRAS_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>
+ <reg32 offset="0x2075" name="GRAS_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>
+ <reg32 offset="0x2079" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
+ <reg32 offset="0x207a" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
+
+ <!-- RB registers -->
+ <reg32 offset="0x20c0" name="RB_MODE_CONTROL">
+ <!-- guess on the # of bits here.. -->
+ <bitfield name="GMEM_BYPASS" pos="7" type="boolean"/>
+ <doc>
+ RENDER_MODE is RB_RESOLVE_PASS for gmem->mem, otherwise RB_RENDER_PASS
+ </doc>
+ <bitfield name="RENDER_MODE" low="8" high="10" type="a3xx_render_mode"/>
+ <bitfield name="MRT" low="12" high="13" type="uint">
+ <doc>render targets - 1</doc>
+ </bitfield>
+ <bitfield name="MARB_CACHE_SPLIT_MODE" pos="15" type="boolean"/>
+ <bitfield name="PACKER_TIMER_ENABLE" pos="16" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x20c1" name="RB_RENDER_CONTROL">
+ <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="YUV_IN_ENABLE" pos="1" type="boolean"/>
+ <bitfield name="COV_VALUE_INPUT_ENABLE" pos="2" type="boolean"/>
+ <!-- set when gl_FrontFacing is accessed in frag shader: -->
+ <bitfield name="FACENESS" pos="3" type="boolean"/>
+ <bitfield name="BIN_WIDTH" low="4" high="11" shr="5" type="uint"/>
+ <bitfield name="DISABLE_COLOR_PIPE" pos="12" type="boolean"/>
+ <!--
+ ENABLE_GMEM not set on mem2gmem.. so possibly it is actually
+ controlling blend or readback from GMEM??
+ -->
+ <bitfield name="ENABLE_GMEM" pos="13" type="boolean"/>
+ <bitfield name="COORD_MASK" low="14" high="17" type="hex"/>
+ <bitfield name="I_CLAMP_ENABLE" pos="19" type="boolean"/>
+ <bitfield name="COV_VALUE_OUTPUT_ENABLE" pos="20" type="boolean"/>
+ <bitfield name="ALPHA_TEST" pos="22" type="boolean"/>
+ <bitfield name="ALPHA_TEST_FUNC" low="24" high="26" type="adreno_compare_func"/>
+ <bitfield name="ALPHA_TO_COVERAGE" pos="30" type="boolean"/>
+ <bitfield name="ALPHA_TO_ONE" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x20c2" name="RB_MSAA_CONTROL">
+ <bitfield name="DISABLE" pos="10" type="boolean"/>
+ <bitfield name="SAMPLES" low="12" high="15" type="a3xx_msaa_samples"/>
+ <bitfield name="SAMPLE_MASK" low="16" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="0x20c3" name="RB_ALPHA_REF">
+ <bitfield name="UINT" low="8" high="15" type="hex"/>
+ <bitfield name="FLOAT" low="16" high="31" type="float"/>
+ </reg32>
+ <array offset="0x20c4" name="RB_MRT" stride="4" length="4">
+ <reg32 offset="0x0" name="CONTROL">
+ <bitfield name="READ_DEST_ENABLE" pos="3" type="boolean"/>
+ <!-- both these bits seem to get set when enabling GL_BLEND.. -->
+ <bitfield name="BLEND" pos="4" type="boolean"/>
+ <bitfield name="BLEND2" pos="5" type="boolean"/>
+ <bitfield name="ROP_CODE" low="8" high="11" type="a3xx_rop_code"/>
+ <bitfield name="DITHER_MODE" low="12" high="13" type="adreno_rb_dither_mode"/>
+ <bitfield name="COMPONENT_ENABLE" low="24" high="27" type="hex"/>
+ </reg32>
+ <reg32 offset="0x1" name="BUF_INFO">
+ <bitfield name="COLOR_FORMAT" low="0" high="5" type="a3xx_color_fmt"/>
+ <bitfield name="COLOR_TILE_MODE" low="6" high="7" type="a3xx_tile_mode"/>
+ <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
+ <bitfield name="COLOR_SRGB" pos="14" type="boolean"/>
+ <doc>
+ Pitch (actually, appears to be pitch in bytes, so really is a stride)
+ in GMEM, so pitch of the current tile.
+ </doc>
+ <bitfield name="COLOR_BUF_PITCH" low="17" high="31" shr="5" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2" name="BUF_BASE">
+ <doc>offset into GMEM (or system memory address in bypass mode)</doc>
+ <bitfield name="COLOR_BUF_BASE" low="4" high="31" shr="5" type="hex"/>
+ </reg32>
+ <reg32 offset="0x3" name="BLEND_CONTROL">
+ <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
+ <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
+ <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
+ <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
+ <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
+ <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
+ <bitfield name="CLAMP_ENABLE" pos="29" type="boolean"/>
+ </reg32>
+ </array>
+
+ <reg32 offset="0x20e4" name="RB_BLEND_RED">
+ <bitfield name="UINT" low="0" high="7" type="hex"/>
+ <bitfield name="FLOAT" low="16" high="31" type="float"/>
+ </reg32>
+ <reg32 offset="0x20e5" name="RB_BLEND_GREEN">
+ <bitfield name="UINT" low="0" high="7" type="hex"/>
+ <bitfield name="FLOAT" low="16" high="31" type="float"/>
+ </reg32>
+ <reg32 offset="0x20e6" name="RB_BLEND_BLUE">
+ <bitfield name="UINT" low="0" high="7" type="hex"/>
+ <bitfield name="FLOAT" low="16" high="31" type="float"/>
+ </reg32>
+ <reg32 offset="0x20e7" name="RB_BLEND_ALPHA">
+ <bitfield name="UINT" low="0" high="7" type="hex"/>
+ <bitfield name="FLOAT" low="16" high="31" type="float"/>
+ </reg32>
+
+ <reg32 offset="0x20e8" name="RB_CLEAR_COLOR_DW0"/>
+ <reg32 offset="0x20e9" name="RB_CLEAR_COLOR_DW1"/>
+ <reg32 offset="0x20ea" name="RB_CLEAR_COLOR_DW2"/>
+ <reg32 offset="0x20eb" name="RB_CLEAR_COLOR_DW3"/>
+ <reg32 offset="0x20ec" name="RB_COPY_CONTROL">
+ <!-- not sure # of bits -->
+ <bitfield name="MSAA_RESOLVE" low="0" high="1" type="a3xx_msaa_samples"/>
+ <bitfield name="DEPTHCLEAR" pos="3" type="boolean"/>
+ <bitfield name="MODE" low="4" high="6" type="adreno_rb_copy_control_mode"/>
+ <bitfield name="MSAA_SRGB_DOWNSAMPLE" pos="7" type="boolean"/>
+ <bitfield name="FASTCLEAR" low="8" high="11" type="hex"/>
+ <bitfield name="DEPTH32_RESOLVE" pos="12" type="boolean"/> <!-- enabled on a Z32F copy -->
+ <bitfield name="GMEM_BASE" low="14" high="31" shr="14" type="hex"/>
+ </reg32>
+ <reg32 offset="0x20ed" name="RB_COPY_DEST_BASE">
+ <bitfield name="BASE" low="4" high="31" shr="5" type="hex"/>
+ </reg32>
+ <reg32 offset="0x20ee" name="RB_COPY_DEST_PITCH">
+ <doc>actually, appears to be pitch in bytes, so really is a stride</doc>
+ <!-- not actually sure about max pitch... -->
+ <bitfield name="PITCH" low="0" high="31" shr="5" type="uint"/>
+ </reg32>
+ <reg32 offset="0x20ef" name="RB_COPY_DEST_INFO">
+ <bitfield name="TILE" low="0" high="1" type="a3xx_tile_mode"/>
+ <bitfield name="FORMAT" low="2" high="7" type="a3xx_color_fmt"/>
+ <bitfield name="SWAP" low="8" high="9" type="a3xx_color_swap"/>
+ <bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/>
+ <bitfield name="COMPONENT_ENABLE" low="14" high="17" type="hex"/>
+ <bitfield name="ENDIAN" low="18" high="20" type="adreno_rb_surface_endian"/>
+ </reg32>
+ <reg32 offset="0x2100" name="RB_DEPTH_CONTROL">
+ <!--
+ guessing that this matches a2xx with the stencil fields
+ moved out into RB_STENCIL_CONTROL?
+ -->
+ <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
+ <bitfield name="Z_TEST_ENABLE" pos="1" type="boolean"/>
+ <bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>
+ <bitfield name="EARLY_Z_DISABLE" pos="3" type="boolean"/>
+ <bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>
+ <bitfield name="Z_CLAMP_ENABLE" pos="7" type="boolean"/>
+ <doc>Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
+ <bitfield name="Z_READ_ENABLE" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2101" name="RB_DEPTH_CLEAR">
+ <doc>seems to be always set to 0x00000000</doc>
+ </reg32>
+ <reg32 offset="0x2102" name="RB_DEPTH_INFO">
+ <bitfield name="DEPTH_FORMAT" low="0" high="1" type="adreno_rb_depth_format"/>
+ <doc>
+ DEPTH_BASE is offset in GMEM to depth/stencil buffer, ie
+ bin_w * bin_h / 1024 (possible rounded up to multiple of
+ something?? ie. 39 becomes 40, 78 becomes 80.. 75 becomes
+ 80.. so maybe it needs to be multiple of 8??
+ </doc>
+ <bitfield name="DEPTH_BASE" low="11" high="31" shr="12" type="hex"/>
+ </reg32>
+ <reg32 offset="0x2103" name="RB_DEPTH_PITCH" shr="3" type="uint">
+ <doc>
+ Pitch of depth buffer or combined depth+stencil buffer
+ in z24s8 cases.
+ </doc>
+ </reg32>
+ <reg32 offset="0x2104" name="RB_STENCIL_CONTROL">
+ <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
+ <!--
+ set for stencil operations that require read from stencil
+ buffer, but not for example for stencil clear (which does
+ not require read).. so guessing this is analogous to
+ READ_DEST_ENABLE for color buffer..
+ -->
+ <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
+ <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
+ <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
+ <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
+ <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
+ <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
+ <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
+ <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
+ <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
+ </reg32>
+ <reg32 offset="0x2105" name="RB_STENCIL_CLEAR">
+ <doc>seems to be always set to 0x00000000</doc>
+ </reg32>
+ <reg32 offset="0x2106" name="RB_STENCIL_INFO">
+ <doc>Base address for stencil when not using interleaved depth/stencil</doc>
+ <bitfield name="STENCIL_BASE" low="11" high="31" shr="12" type="hex"/>
+ </reg32>
+ <reg32 offset="0x2107" name="RB_STENCIL_PITCH" shr="3" type="uint">
+ <doc>pitch of stencil buffer when not using interleaved depth/stencil</doc>
+ </reg32>
+ <reg32 offset="0x2108" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
+ <reg32 offset="0x2109" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
+ <!-- VSC == visibility stream c?? -->
+ <reg32 offset="0x210c" name="RB_LRZ_VSC_CONTROL">
+ <doc>seems to be set to 0x00000002 during binning pass</doc>
+ <bitfield name="BINNING_ENABLE" pos="1" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x210e" name="RB_WINDOW_OFFSET">
+ <doc>X/Y offset of current bin</doc>
+ <bitfield name="X" low="0" high="15" type="uint"/>
+ <bitfield name="Y" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2110" name="RB_SAMPLE_COUNT_CONTROL">
+ <bitfield name="RESET" pos="0" type="boolean"/>
+ <bitfield name="COPY" pos="1" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2111" name="RB_SAMPLE_COUNT_ADDR"/>
+ <reg32 offset="0x2114" name="RB_Z_CLAMP_MIN"/>
+ <reg32 offset="0x2115" name="RB_Z_CLAMP_MAX"/>
+
+ <!-- PC registers -->
+ <reg32 offset="0x21e1" name="VGT_BIN_BASE">
+ <doc>
+ seems to be where firmware writes BIN_DATA_ADDR from
+ CP_SET_BIN_DATA packet.. probably should be called
+ PC_BIN_BASE (just using name from yamato for now)
+ </doc>
+ </reg32>
+ <reg32 offset="0x21e2" name="VGT_BIN_SIZE">
+ <doc>probably should be PC_BIN_SIZE</doc>
+ </reg32>
+ <reg32 offset="0x21e4" name="PC_VSTREAM_CONTROL">
+ <doc>SIZE is current pipe width * height (in tiles)</doc>
+ <bitfield name="SIZE" low="16" high="21" type="uint"/>
+ <doc>
+ N is some sort of slot # between 0..(SIZE-1). In case
+ multiple tiles use same pipe, each tile gets unique slot #
+ </doc>
+ <bitfield name="N" low="22" high="26" type="uint"/>
+ </reg32>
+ <reg32 offset="0x21ea" name="PC_VERTEX_REUSE_BLOCK_CNTL"/>
+ <reg32 offset="0x21ec" name="PC_PRIM_VTX_CNTL">
+ <doc>
+ STRIDE_IN_VPC: ALIGN(next_outloc - 8, 4) / 4
+ (but, in cases where you'd expect 1, the blob driver uses
+ 2, so possibly 0 (no varying) or minimum of 2)
+ </doc>
+ <bitfield name="STRIDE_IN_VPC" low="0" high="4" type="uint"/>
+ <bitfield name="POLYMODE_FRONT_PTYPE" low="5" high="7" type="adreno_pa_su_sc_draw"/>
+ <bitfield name="POLYMODE_BACK_PTYPE" low="8" high="10" type="adreno_pa_su_sc_draw"/>
+ <bitfield name="POLYMODE_ENABLE" pos="12" type="boolean"/>
+ <bitfield name="PRIMITIVE_RESTART" pos="20" type="boolean"/>
+ <bitfield name="PROVOKING_VTX_LAST" pos="25" type="boolean"/>
+ <!-- PSIZE bit set if gl_PointSize written: -->
+ <bitfield name="PSIZE" pos="26" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x21ed" name="PC_RESTART_INDEX"/>
+
+ <!-- HLSQ registers -->
+ <bitset name="a3xx_hlsq_vs_fs_control_reg" inline="yes">
+ <bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
+ <bitfield name="CONSTSTARTOFFSET" low="12" high="20" type="uint"/>
+ <bitfield name="INSTRLENGTH" low="24" high="31" type="uint"/>
+ </bitset>
+ <bitset name="a3xx_hlsq_const_vs_fs_presv_range_reg" inline="yes">
+ <!-- are these a3xx_regid?? -->
+ <bitfield name="STARTENTRY" low="0" high="8"/>
+ <bitfield name="ENDENTRY" low="16" high="24"/>
+ </bitset>
+
+ <reg32 offset="0x2200" name="HLSQ_CONTROL_0_REG">
+ <bitfield name="FSTHREADSIZE" low="4" high="5" type="a3xx_threadsize"/>
+ <bitfield name="FSSUPERTHREADENABLE" pos="6" type="boolean"/>
+ <bitfield name="COMPUTEMODE" pos="8" type="boolean"/>
+ <bitfield name="SPSHADERRESTART" pos="9" type="boolean"/>
+ <bitfield name="RESERVED2" pos="10" type="boolean"/>
+ <bitfield name="CYCLETIMEOUTLIMITVPC" low="12" high="23" type="uint"/>
+ <bitfield name="FSONLYTEX" pos="25" type="boolean"/>
+ <bitfield name="CHUNKDISABLE" pos="26" type="boolean"/>
+ <bitfield name="CONSTMODE" pos="27" type="uint"/>
+ <bitfield name="LAZYUPDATEDISABLE" pos="28" type="boolean"/>
+ <bitfield name="SPCONSTFULLUPDATE" pos="29" type="boolean"/>
+ <bitfield name="TPFULLUPDATE" pos="30" type="boolean"/>
+ <bitfield name="SINGLECONTEXT" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2201" name="HLSQ_CONTROL_1_REG">
+ <bitfield name="VSTHREADSIZE" low="6" high="7" type="a3xx_threadsize"/>
+ <bitfield name="VSSUPERTHREADENABLE" pos="8" type="boolean"/>
+ <bitfield name="FRAGCOORDXYREGID" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="FRAGCOORDZWREGID" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0x2202" name="HLSQ_CONTROL_2_REG">
+ <bitfield name="FACENESSREGID" low="2" high="9" type="a3xx_regid"/>
+ <bitfield name="COVVALUEREGID" low="18" high="25" type="a3xx_regid"/>
+ <bitfield name="PRIMALLOCTHRESHOLD" low="26" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2203" name="HLSQ_CONTROL_3_REG">
+ <bitfield name="IJPERSPCENTERREGID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="IJNONPERSPCENTERREGID" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="IJPERSPCENTROIDREGID" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="IJNONPERSPCENTROIDREGID" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0x2204" name="HLSQ_VS_CONTROL_REG" type="a3xx_hlsq_vs_fs_control_reg"/>
+ <reg32 offset="0x2205" name="HLSQ_FS_CONTROL_REG" type="a3xx_hlsq_vs_fs_control_reg"/>
+ <reg32 offset="0x2206" name="HLSQ_CONST_VSPRESV_RANGE_REG" type="a3xx_hlsq_const_vs_fs_presv_range_reg"/>
+ <reg32 offset="0x2207" name="HLSQ_CONST_FSPRESV_RANGE_REG" type="a3xx_hlsq_const_vs_fs_presv_range_reg"/>
+ <reg32 offset="0x220a" name="HLSQ_CL_NDRANGE_0_REG">
+ <bitfield name="WORKDIM" low="0" high="1" type="uint"/>
+ <bitfield name="LOCALSIZE0" low="2" high="11" type="uint"/>
+ <bitfield name="LOCALSIZE1" low="12" high="21" type="uint"/>
+ <bitfield name="LOCALSIZE2" low="22" high="31" type="uint"/>
+ </reg32>
+ <array offset="0x220b" name="HLSQ_CL_GLOBAL_WORK" stride="2" length="3">
+ <doc>indexed by dimension</doc>
+ <reg32 offset="0" name="SIZE" type="uint"/>
+ <reg32 offset="1" name="OFFSET" type="uint"/>
+ </array>
+ <reg32 offset="0x2211" name="HLSQ_CL_CONTROL_0_REG"/>
+ <reg32 offset="0x2212" name="HLSQ_CL_CONTROL_1_REG"/>
+ <reg32 offset="0x2214" name="HLSQ_CL_KERNEL_CONST_REG"/>
+ <array offset="0x2215" name="HLSQ_CL_KERNEL_GROUP" stride="1" length="3">
+ <doc>indexed by dimension, global_size / local_size</doc>
+ <reg32 offset="0" name="RATIO" type="uint"/>
+ </array>
+ <reg32 offset="0x2216" name="HLSQ_CL_KERNEL_GROUP_Y_REG" type="uint"/>
+ <reg32 offset="0x2217" name="HLSQ_CL_KERNEL_GROUP_Z_REG" type="uint"/>
+ <reg32 offset="0x221a" name="HLSQ_CL_WG_OFFSET_REG"/>
+
+ <!-- VFD registers -->
+ <reg32 offset="0x2240" name="VFD_CONTROL_0">
+ <doc>
+ TOTALATTRTOVS is # of attributes to vertex shader, in register
+ slots (ie. vec4+vec3 -> 7)
+ </doc>
+ <bitfield name="TOTALATTRTOVS" low="0" high="17" type="uint"/>
+ <bitfield name="PACKETSIZE" low="18" high="21" type="uint"/>
+ <doc>STRMDECINSTRCNT is # of VFD_DECODE_INSTR registers valid</doc>
+ <bitfield name="STRMDECINSTRCNT" low="22" high="26" type="uint"/>
+ <doc>STRMFETCHINSTRCNT is # of VFD_FETCH_INSTR registers valid</doc>
+ <bitfield name="STRMFETCHINSTRCNT" low="27" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2241" name="VFD_CONTROL_1">
+ <doc>MAXSTORAGE could be # of attributes/vbo's</doc>
+ <bitfield name="MAXSTORAGE" low="0" high="3" type="uint"/>
+ <bitfield name="MAXTHRESHOLD" low="4" high="7" type="uint"/>
+ <bitfield name="MINTHRESHOLD" low="8" high="11" type="uint"/>
+ <bitfield name="REGID4VTX" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="REGID4INST" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0x2242" name="VFD_INDEX_MIN" type="uint"/>
+ <reg32 offset="0x2243" name="VFD_INDEX_MAX" type="uint"/>
+ <reg32 offset="0x2244" name="VFD_INSTANCEID_OFFSET" type="uint"/>
+ <reg32 offset="0x2245" name="VFD_INDEX_OFFSET" type="uint"/>
+ <array offset="0x2246" name="VFD_FETCH" stride="2" length="16">
+ <reg32 offset="0x0" name="INSTR_0">
+ <bitfield name="FETCHSIZE" low="0" high="6" type="uint"/>
+ <bitfield name="BUFSTRIDE" low="7" high="15" type="uint"/>
+ <bitfield name="INSTANCED" pos="16" type="boolean"/>
+ <bitfield name="SWITCHNEXT" pos="17" type="boolean"/>
+ <bitfield name="INDEXCODE" low="18" high="23" type="uint"/>
+ <bitfield name="STEPRATE" low="24" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x1" name="INSTR_1"/>
+ </array>
+ <array offset="0x2266" name="VFD_DECODE" stride="1" length="16">
+ <reg32 offset="0x0" name="INSTR">
+ <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
+ <!-- not sure if this is a bit flag and another flag above it, or?? -->
+ <bitfield name="CONSTFILL" pos="4" type="boolean"/>
+ <bitfield name="FORMAT" low="6" high="11" type="a3xx_vtx_fmt"/>
+ <bitfield name="REGID" low="12" high="19" type="a3xx_regid"/>
+ <bitfield name="INT" pos="20" type="boolean"/>
+ <doc>SHIFTCNT appears to be size, ie. FLOAT_32_32_32 is 12, and BYTE_8 is 1</doc>
+ <bitfield name="SWAP" low="22" high="23" type="a3xx_color_swap"/>
+ <bitfield name="SHIFTCNT" low="24" high="28" type="uint"/>
+ <bitfield name="LASTCOMPVALID" pos="29" type="boolean"/>
+ <bitfield name="SWITCHNEXT" pos="30" type="boolean"/>
+ </reg32>
+ </array>
+ <reg32 offset="0x227e" name="VFD_VS_THREADING_THRESHOLD">
+ <bitfield name="REGID_THRESHOLD" low="0" high="3" type="uint"/>
+ <!-- <bitfield name="RESERVED6" low="4" high="7" type="uint"/> -->
+ <bitfield name="REGID_VTXCNT" low="8" high="15" type="a3xx_regid"/>
+ </reg32>
+
+ <!-- VPC registers -->
+ <reg32 offset="0x2280" name="VPC_ATTR">
+ <bitfield name="TOTALATTR" low="0" high="8" type="uint"/>
+ <!-- PSIZE bit set if gl_PointSize written: -->
+ <bitfield name="PSIZE" pos="9" type="boolean"/>
+ <bitfield name="THRDASSIGN" low="12" high="27" type="uint"/>
+ <bitfield name="LMSIZE" low="28" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2281" name="VPC_PACK">
+ <!-- these are always seem to be set to same as TOTALATTR -->
+ <bitfield name="NUMFPNONPOSVAR" low="8" high="15" type="uint"/>
+ <bitfield name="NUMNONPOSVSVAR" low="16" high="23" type="uint"/>
+ </reg32>
+ <!--
+ varying interpolate mode. One field per scalar/component
+ (since varying slots are scalar, so things don't have to
+ be aligned to vec4).
+ 4 regs * 16 scalar components each => 16 vec4
+ -->
+ <array offset="0x2282" name="VPC_VARYING_INTERP" stride="1" length="4">
+ <reg32 offset="0x0" name="MODE">
+ <bitfield name="C0" low="0" high="1" type="a3xx_intp_mode"/>
+ <bitfield name="C1" low="2" high="3" type="a3xx_intp_mode"/>
+ <bitfield name="C2" low="4" high="5" type="a3xx_intp_mode"/>
+ <bitfield name="C3" low="6" high="7" type="a3xx_intp_mode"/>
+ <bitfield name="C4" low="8" high="9" type="a3xx_intp_mode"/>
+ <bitfield name="C5" low="10" high="11" type="a3xx_intp_mode"/>
+ <bitfield name="C6" low="12" high="13" type="a3xx_intp_mode"/>
+ <bitfield name="C7" low="14" high="15" type="a3xx_intp_mode"/>
+ <bitfield name="C8" low="16" high="17" type="a3xx_intp_mode"/>
+ <bitfield name="C9" low="18" high="19" type="a3xx_intp_mode"/>
+ <bitfield name="CA" low="20" high="21" type="a3xx_intp_mode"/>
+ <bitfield name="CB" low="22" high="23" type="a3xx_intp_mode"/>
+ <bitfield name="CC" low="24" high="25" type="a3xx_intp_mode"/>
+ <bitfield name="CD" low="26" high="27" type="a3xx_intp_mode"/>
+ <bitfield name="CE" low="28" high="29" type="a3xx_intp_mode"/>
+ <bitfield name="CF" low="30" high="31" type="a3xx_intp_mode"/>
+ </reg32>
+ </array>
+ <array offset="0x2286" name="VPC_VARYING_PS_REPL" stride="1" length="4">
+ <reg32 offset="0x0" name="MODE">
+ <bitfield name="C0" low="0" high="1" type="a3xx_repl_mode"/>
+ <bitfield name="C1" low="2" high="3" type="a3xx_repl_mode"/>
+ <bitfield name="C2" low="4" high="5" type="a3xx_repl_mode"/>
+ <bitfield name="C3" low="6" high="7" type="a3xx_repl_mode"/>
+ <bitfield name="C4" low="8" high="9" type="a3xx_repl_mode"/>
+ <bitfield name="C5" low="10" high="11" type="a3xx_repl_mode"/>
+ <bitfield name="C6" low="12" high="13" type="a3xx_repl_mode"/>
+ <bitfield name="C7" low="14" high="15" type="a3xx_repl_mode"/>
+ <bitfield name="C8" low="16" high="17" type="a3xx_repl_mode"/>
+ <bitfield name="C9" low="18" high="19" type="a3xx_repl_mode"/>
+ <bitfield name="CA" low="20" high="21" type="a3xx_repl_mode"/>
+ <bitfield name="CB" low="22" high="23" type="a3xx_repl_mode"/>
+ <bitfield name="CC" low="24" high="25" type="a3xx_repl_mode"/>
+ <bitfield name="CD" low="26" high="27" type="a3xx_repl_mode"/>
+ <bitfield name="CE" low="28" high="29" type="a3xx_repl_mode"/>
+ <bitfield name="CF" low="30" high="31" type="a3xx_repl_mode"/>
+ </reg32>
+ </array>
+ <reg32 offset="0x228a" name="VPC_VARY_CYLWRAP_ENABLE_0"/>
+ <reg32 offset="0x228b" name="VPC_VARY_CYLWRAP_ENABLE_1"/>
+
+ <!-- SP registers -->
+ <bitset name="a3xx_vs_fs_length_reg" inline="yes">
+ <bitfield name="SHADERLENGTH" low="0" high="31" type="uint"/>
+ </bitset>
+
+ <bitset name="sp_vs_fs_obj_offset_reg" inline="yes">
+ <bitfield name="FIRSTEXECINSTROFFSET" low="0" high="15" type="uint"/>
+ <doc>
+ From register spec:
+ SP_FS_OBJ_OFFSET_REG.CONSTOBJECTSTARTOFFSET [16:24]: Constant object
+ start offset in on chip RAM,
+ 128bit aligned
+ </doc>
+ <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
+ <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
+ </bitset>
+
+ <reg32 offset="0x22c0" name="SP_SP_CTRL_REG">
+ <!-- this bit is set during resolve pass: -->
+ <bitfield name="RESOLVE" pos="16" type="boolean"/>
+ <bitfield name="CONSTMODE" pos="18" type="uint"/>
+ <bitfield name="BINNING" pos="19" type="boolean"/>
+ <bitfield name="SLEEPMODE" low="20" high="21" type="uint"/>
+ <!-- L0MODE==1 when oxiliForceSpL0ModeBuffer=1 -->
+ <bitfield name="L0MODE" low="22" high="23" type="uint"/>
+ </reg32>
+ <reg32 offset="0x22c4" name="SP_VS_CTRL_REG0">
+ <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
+ <bitfield name="INSTRBUFFERMODE" pos="1" type="a3xx_instrbuffermode"/>
+ <!-- maybe CACHEINVALID is two bits?? -->
+ <bitfield name="CACHEINVALID" pos="2" type="boolean"/>
+ <bitfield name="ALUSCHMODE" pos="3" type="boolean"/>
+ <doc>
+ The full/half register footprint is in units of four components,
+ so if r0.x is used, that counts as all of r0.[xyzw] as used.
+ There are separate full/half register footprint values as the
+ full and half registers are independent (not overlapping).
+ Presumably the thread scheduler hardware allocates the full/half
+ register names from the actual physical register file and
+ handles the register renaming.
+ </doc>
+ <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
+ <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
+ <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
+ <bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/>
+ <doc>
+ From regspec:
+ SP_FS_CTRL_REG0.FS_LENGTH [31:24]: FS length, unit = 256bits.
+ If bit31 is 1, it means overflow
+ or any long shader.
+ </doc>
+ <bitfield name="LENGTH" low="24" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x22c5" name="SP_VS_CTRL_REG1">
+ <bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
+ <!--
+ not sure about full vs half const.. I can't get blob generate
+ something with a mediump/lowp uniform.
+ -->
+ <bitfield name="CONSTFOOTPRINT" low="10" high="19" type="uint"/>
+ <bitfield name="INITIALOUTSTANDING" low="24" high="30" type="uint"/>
+ </reg32>
+ <reg32 offset="0x22c6" name="SP_VS_PARAM_REG">
+ <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="PSIZEREGID" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="POS2DMODE" pos="16" type="boolean"/>
+ <bitfield name="TOTALVSOUTVAR" low="20" high="24" type="uint"/>
+ </reg32>
+ <array offset="0x22c7" name="SP_VS_OUT" stride="1" length="8">
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="A_HALF" pos="8" type="boolean"/>
+ <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
+ <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="B_HALF" pos="24" type="boolean"/>
+ <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
+ </reg32>
+ </array>
+ <array offset="0x22d0" name="SP_VS_VPC_DST" stride="1" length="4">
+ <reg32 offset="0x0" name="REG">
+ <doc>
+ These seem to be offsets for storage of the varyings.
+ Always seems to start from 8, possibly loc 0 and 4
+ are for gl_Position and gl_PointSize?
+ </doc>
+ <bitfield name="OUTLOC0" low="0" high="6" type="uint"/>
+ <bitfield name="OUTLOC1" low="8" high="14" type="uint"/>
+ <bitfield name="OUTLOC2" low="16" high="22" type="uint"/>
+ <bitfield name="OUTLOC3" low="24" high="30" type="uint"/>
+ </reg32>
+ </array>
+ <reg32 offset="0x22d4" name="SP_VS_OBJ_OFFSET_REG" type="sp_vs_fs_obj_offset_reg"/>
+ <doc>
+ SP_VS_OBJ_START_REG contains pointer to the vertex shader program,
+ immediately followed by the binning shader program (although I
+ guess that is probably just re-using the same gpu buffer)
+ </doc>
+ <reg32 offset="0x22d5" name="SP_VS_OBJ_START_REG"/>
+ <reg32 offset="0x22d6" name="SP_VS_PVT_MEM_PARAM_REG">
+ <bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="7">
+ <doc>The size of memory that ldp/stp can address, in 128 byte increments.</doc>
+ </bitfield>
+ <bitfield name="HWSTACKOFFSET" low="8" high="23" type="uint"/>
+ <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x22d7" name="SP_VS_PVT_MEM_ADDR_REG">
+ <bitfield name="BURSTLEN" low="0" high="4"/>
+ <bitfield name="SHADERSTARTADDRESS" shr="5" low="5" high="31"/>
+ </reg32>
+ <reg32 offset="0x22d8" name="SP_VS_PVT_MEM_SIZE_REG"/>
+ <reg32 offset="0x22df" name="SP_VS_LENGTH_REG" type="a3xx_vs_fs_length_reg"/>
+ <reg32 offset="0x22e0" name="SP_FS_CTRL_REG0">
+ <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
+ <bitfield name="INSTRBUFFERMODE" pos="1" type="a3xx_instrbuffermode"/>
+ <!-- maybe CACHEINVALID is two bits?? -->
+ <bitfield name="CACHEINVALID" pos="2" type="boolean"/>
+ <bitfield name="ALUSCHMODE" pos="3" type="boolean"/>
+ <doc>
+ The full/half register footprint is in units of four components,
+ so if r0.x is used, that counts as all of r0.[xyzw] as used.
+ There are separate full/half register footprint values as the
+ full and half registers are independent (not overlapping).
+ Presumably the thread scheduler hardware allocates the full/half
+ register names from the actual physical register file and
+ handles the register renaming.
+ </doc>
+ <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
+ <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
+ <bitfield name="FSBYPASSENABLE" pos="17" type="boolean"/>
+ <bitfield name="INOUTREGOVERLAP" pos="18" type="boolean"/>
+ <bitfield name="OUTORDERED" pos="19" type="boolean"/>
+ <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
+ <bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/>
+ <bitfield name="PIXLODENABLE" pos="22" type="boolean"/>
+ <bitfield name="COMPUTEMODE" pos="23" type="boolean"/>
+ <doc>
+ From regspec:
+ SP_FS_CTRL_REG0.FS_LENGTH [31:24]: FS length, unit = 256bits.
+ If bit31 is 1, it means overflow
+ or any long shader.
+ </doc>
+ <bitfield name="LENGTH" low="24" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x22e1" name="SP_FS_CTRL_REG1">
+ <bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
+ <bitfield name="CONSTFOOTPRINT" low="10" high="19" type="uint"/>
+ <bitfield name="INITIALOUTSTANDING" low="20" high="23" type="uint"/>
+ <bitfield name="HALFPRECVAROFFSET" low="24" high="30" type="uint"/>
+ </reg32>
+ <reg32 offset="0x22e2" name="SP_FS_OBJ_OFFSET_REG" type="sp_vs_fs_obj_offset_reg"/>
+ <doc>SP_FS_OBJ_START_REG contains pointer to fragment shader program</doc>
+ <reg32 offset="0x22e3" name="SP_FS_OBJ_START_REG"/>
+ <reg32 offset="0x22e4" name="SP_FS_PVT_MEM_PARAM_REG">
+ <bitfield name="MEMSIZEPERITEM" low="0" high="7" type="uint"/>
+ <bitfield name="HWSTACKOFFSET" low="8" high="23" type="uint"/>
+ <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x22e5" name="SP_FS_PVT_MEM_ADDR_REG">
+ <bitfield name="BURSTLEN" low="0" high="4"/>
+ <bitfield name="SHADERSTARTADDRESS" shr="5" low="5" high="31"/>
+ </reg32>
+ <reg32 offset="0x22e6" name="SP_FS_PVT_MEM_SIZE_REG"/>
+ <reg32 offset="0x22e8" name="SP_FS_FLAT_SHAD_MODE_REG_0">
+ <doc>seems to be one bit per scalar, '1' for flat, '0' for smooth</doc>
+ </reg32>
+ <reg32 offset="0x22e9" name="SP_FS_FLAT_SHAD_MODE_REG_1">
+ <doc>seems to be one bit per scalar, '1' for flat, '0' for smooth</doc>
+ </reg32>
+ <reg32 offset="0x22ec" name="SP_FS_OUTPUT_REG">
+ <bitfield name="MRT" low="0" high="1" type="uint">
+ <doc>render targets - 1</doc>
+ </bitfield>
+ <bitfield name="DEPTH_ENABLE" pos="7" type="boolean"/>
+ <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
+ </reg32>
+ <array offset="0x22f0" name="SP_FS_MRT" stride="1" length="4">
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
+ <bitfield name="SINT" pos="10" type="boolean"/>
+ <bitfield name="UINT" pos="11" type="boolean"/>
+ </reg32>
+ </array>
+ <array offset="0x22f4" name="SP_FS_IMAGE_OUTPUT" stride="1" length="4">
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="MRTFORMAT" low="0" high="5" type="a3xx_color_fmt"/>
+ </reg32>
+ </array>
+ <reg32 offset="0x22ff" name="SP_FS_LENGTH_REG" type="a3xx_vs_fs_length_reg"/>
+
+ <reg32 offset="0x2301" name="PA_SC_AA_CONFIG"/>
+ <!-- TPL1 registers -->
+ <!-- assume VS/FS_TEX_OFFSET is same -->
+ <bitset name="a3xx_tpl1_tp_vs_fs_tex_offset" inline="yes">
+ <bitfield name="SAMPLEROFFSET" low="0" high="7" type="uint"/>
+ <bitfield name="MEMOBJOFFSET" low="8" high="15" type="uint"/>
+ <!-- not sure the size of this: -->
+ <bitfield name="BASETABLEPTR" low="16" high="31" type="uint"/>
+ </bitset>
+ <reg32 offset="0x2340" name="TPL1_TP_VS_TEX_OFFSET" type="a3xx_tpl1_tp_vs_fs_tex_offset"/>
+ <reg32 offset="0x2341" name="TPL1_TP_VS_BORDER_COLOR_BASE_ADDR"/>
+ <reg32 offset="0x2342" name="TPL1_TP_FS_TEX_OFFSET" type="a3xx_tpl1_tp_vs_fs_tex_offset"/>
+ <reg32 offset="0x2343" name="TPL1_TP_FS_BORDER_COLOR_BASE_ADDR"/>
+
+ <!-- VBIF registers -->
+ <reg32 offset="0x3001" name="VBIF_CLKON"/>
+ <reg32 offset="0x300c" name="VBIF_FIXED_SORT_EN"/>
+ <reg32 offset="0x300d" name="VBIF_FIXED_SORT_SEL0"/>
+ <reg32 offset="0x300e" name="VBIF_FIXED_SORT_SEL1"/>
+ <reg32 offset="0x301c" name="VBIF_ABIT_SORT"/>
+ <reg32 offset="0x301d" name="VBIF_ABIT_SORT_CONF"/>
+ <reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/>
+ <reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/>
+ <reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/>
+ <reg32 offset="0x3030" name="VBIF_IN_WR_LIM_CONF0"/>
+ <reg32 offset="0x3031" name="VBIF_IN_WR_LIM_CONF1"/>
+ <reg32 offset="0x3034" name="VBIF_OUT_RD_LIM_CONF0"/>
+ <reg32 offset="0x3035" name="VBIF_OUT_WR_LIM_CONF0"/>
+ <reg32 offset="0x3036" name="VBIF_DDR_OUT_MAX_BURST"/>
+ <reg32 offset="0x303c" name="VBIF_ARB_CTL"/>
+ <reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/>
+ <reg32 offset="0x3058" name="VBIF_OUT_AXI_AMEMTYPE_CONF0"/>
+ <reg32 offset="0x305e" name="VBIF_OUT_AXI_AOOO_EN"/>
+ <reg32 offset="0x305f" name="VBIF_OUT_AXI_AOOO"/>
+
+ <bitset name="a3xx_vbif_perf_cnt" inline="yes">
+ <bitfield name="CNT0" pos="0" type="boolean"/>
+ <bitfield name="CNT1" pos="1" type="boolean"/>
+ <bitfield name="PWRCNT0" pos="2" type="boolean"/>
+ <bitfield name="PWRCNT1" pos="3" type="boolean"/>
+ <bitfield name="PWRCNT2" pos="4" type="boolean"/>
+ </bitset>
+
+ <reg32 offset="0x3070" name="VBIF_PERF_CNT_EN" type="a3xx_vbif_perf_cnt"/>
+ <reg32 offset="0x3071" name="VBIF_PERF_CNT_CLR" type="a3xx_vbif_perf_cnt"/>
+ <reg32 offset="0x3072" name="VBIF_PERF_CNT_SEL"/>
+ <reg32 offset="0x3073" name="VBIF_PERF_CNT0_LO"/>
+ <reg32 offset="0x3074" name="VBIF_PERF_CNT0_HI"/>
+ <reg32 offset="0x3075" name="VBIF_PERF_CNT1_LO"/>
+ <reg32 offset="0x3076" name="VBIF_PERF_CNT1_HI"/>
+ <reg32 offset="0x3077" name="VBIF_PERF_PWR_CNT0_LO"/>
+ <reg32 offset="0x3078" name="VBIF_PERF_PWR_CNT0_HI"/>
+ <reg32 offset="0x3079" name="VBIF_PERF_PWR_CNT1_LO"/>
+ <reg32 offset="0x307a" name="VBIF_PERF_PWR_CNT1_HI"/>
+ <reg32 offset="0x307b" name="VBIF_PERF_PWR_CNT2_LO"/>
+ <reg32 offset="0x307c" name="VBIF_PERF_PWR_CNT2_HI"/>
+
+
+ <reg32 offset="0x0c01" name="VSC_BIN_SIZE">
+ <bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>
+ <bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x0c02" name="VSC_SIZE_ADDRESS"/>
+ <array offset="0x0c06" name="VSC_PIPE" stride="3" length="8">
+ <reg32 offset="0x0" name="CONFIG">
+ <doc>
+ Configures the mapping between VSC_PIPE buffer and
+ bin, X/Y specify the bin index in the horiz/vert
+ direction (0,0 is upper left, 0,1 is leftmost bin
+ on second row, and so on). W/H specify the number
+ of bins assigned to this VSC_PIPE in the horiz/vert
+ dimension.
+ </doc>
+ <bitfield name="X" low="0" high="9" type="uint"/>
+ <bitfield name="Y" low="10" high="19" type="uint"/>
+ <bitfield name="W" low="20" high="23" type="uint"/>
+ <bitfield name="H" low="24" high="27" type="uint"/>
+ </reg32>
+ <reg32 offset="0x1" name="DATA_ADDRESS"/>
+ <reg32 offset="0x2" name="DATA_LENGTH"/>
+ </array>
+ <reg32 offset="0x0c3c" name="VSC_BIN_CONTROL">
+ <doc>seems to be set to 0x00000001 during binning pass</doc>
+ <bitfield name="BINNING_ENABLE" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0c3d" name="UNKNOWN_0C3D">
+ <doc>seems to be always set to 0x00000001</doc>
+ </reg32>
+ <reg32 offset="0x0c48" name="PC_PERFCOUNTER0_SELECT" type="a3xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0c49" name="PC_PERFCOUNTER1_SELECT" type="a3xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0c4a" name="PC_PERFCOUNTER2_SELECT" type="a3xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0c4b" name="PC_PERFCOUNTER3_SELECT" type="a3xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0c81" name="GRAS_TSE_DEBUG_ECO">
+ <doc>seems to be always set to 0x00000001</doc>
+ </reg32>
+
+ <reg32 offset="0x0c88" name="GRAS_PERFCOUNTER0_SELECT" type="a3xx_gras_tse_perfcounter_select"/>
+ <reg32 offset="0x0c89" name="GRAS_PERFCOUNTER1_SELECT" type="a3xx_gras_tse_perfcounter_select"/>
+ <reg32 offset="0x0c8a" name="GRAS_PERFCOUNTER2_SELECT" type="a3xx_gras_ras_perfcounter_select"/>
+ <reg32 offset="0x0c8b" name="GRAS_PERFCOUNTER3_SELECT" type="a3xx_gras_ras_perfcounter_select"/>
+ <array offset="0x0ca0" name="GRAS_CL_USER_PLANE" stride="4" length="6">
+ <reg32 offset="0x0" name="X"/>
+ <reg32 offset="0x1" name="Y"/>
+ <reg32 offset="0x2" name="Z"/>
+ <reg32 offset="0x3" name="W"/>
+ </array>
+ <reg32 offset="0x0cc0" name="RB_GMEM_BASE_ADDR"/>
+ <reg32 offset="0x0cc1" name="RB_DEBUG_ECO_CONTROLS_ADDR"/>
+ <reg32 offset="0x0cc6" name="RB_PERFCOUNTER0_SELECT" type="a3xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0cc7" name="RB_PERFCOUNTER1_SELECT" type="a3xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0ce0" name="RB_FRAME_BUFFER_DIMENSION">
+ <bitfield name="WIDTH" low="0" high="13" type="uint"/>
+ <bitfield name="HEIGHT" low="14" high="27" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0e00" name="HLSQ_PERFCOUNTER0_SELECT" type="a3xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e01" name="HLSQ_PERFCOUNTER1_SELECT" type="a3xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e02" name="HLSQ_PERFCOUNTER2_SELECT" type="a3xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e03" name="HLSQ_PERFCOUNTER3_SELECT" type="a3xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e04" name="HLSQ_PERFCOUNTER4_SELECT" type="a3xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e05" name="HLSQ_PERFCOUNTER5_SELECT" type="a3xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e43" name="UNKNOWN_0E43">
+ <doc>seems to be always set to 0x00000001</doc>
+ </reg32>
+ <reg32 offset="0x0e44" name="VFD_PERFCOUNTER0_SELECT" type="a3xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e45" name="VFD_PERFCOUNTER1_SELECT" type="a3xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e61" name="VPC_VPC_DEBUG_RAM_SEL"/>
+ <reg32 offset="0x0e62" name="VPC_VPC_DEBUG_RAM_READ"/>
+ <reg32 offset="0x0e64" name="VPC_PERFCOUNTER0_SELECT" type="a3xx_vpc_perfcounter_select"/>
+ <reg32 offset="0x0e65" name="VPC_PERFCOUNTER1_SELECT" type="a3xx_vpc_perfcounter_select"/>
+ <reg32 offset="0x0e82" name="UCHE_CACHE_MODE_CONTROL_REG"/>
+ <reg32 offset="0x0e84" name="UCHE_PERFCOUNTER0_SELECT" type="a3xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0e85" name="UCHE_PERFCOUNTER1_SELECT" type="a3xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0e86" name="UCHE_PERFCOUNTER2_SELECT" type="a3xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0e87" name="UCHE_PERFCOUNTER3_SELECT" type="a3xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0e88" name="UCHE_PERFCOUNTER4_SELECT" type="a3xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0e89" name="UCHE_PERFCOUNTER5_SELECT" type="a3xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0ea0" name="UCHE_CACHE_INVALIDATE0_REG">
+ <!-- might be shifted right by 5, assuming 32byte cache line size.. -->
+ <bitfield name="ADDR" low="0" high="27" type="hex"/>
+ </reg32>
+ <reg32 offset="0x0ea1" name="UCHE_CACHE_INVALIDATE1_REG">
+ <!-- might be shifted right by 5, assuming 32byte cache line size.. -->
+ <bitfield name="ADDR" low="0" high="27" type="hex"/>
+ <!-- I'd assume 2 bits, for FLUSH/INVALIDATE/CLEAN? -->
+ <bitfield name="OPCODE" low="28" high="29" type="a3xx_cache_opcode"/>
+ <bitfield name="ENTIRE_CACHE" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0ea6" name="UNKNOWN_0EA6"/>
+ <reg32 offset="0x0ec4" name="SP_PERFCOUNTER0_SELECT" type="a3xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ec5" name="SP_PERFCOUNTER1_SELECT" type="a3xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ec6" name="SP_PERFCOUNTER2_SELECT" type="a3xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ec7" name="SP_PERFCOUNTER3_SELECT" type="a3xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ec8" name="SP_PERFCOUNTER4_SELECT" type="a3xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ec9" name="SP_PERFCOUNTER5_SELECT" type="a3xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0eca" name="SP_PERFCOUNTER6_SELECT" type="a3xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ecb" name="SP_PERFCOUNTER7_SELECT" type="a3xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ee0" name="UNKNOWN_0EE0">
+ <doc>seems to be always set to 0x00000003</doc>
+ </reg32>
+ <reg32 offset="0x0f03" name="UNKNOWN_0F03">
+ <doc>seems to be always set to 0x00000001</doc>
+ </reg32>
+ <reg32 offset="0x0f04" name="TP_PERFCOUNTER0_SELECT" type="a3xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f05" name="TP_PERFCOUNTER1_SELECT" type="a3xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f06" name="TP_PERFCOUNTER2_SELECT" type="a3xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f07" name="TP_PERFCOUNTER3_SELECT" type="a3xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f08" name="TP_PERFCOUNTER4_SELECT" type="a3xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f09" name="TP_PERFCOUNTER5_SELECT" type="a3xx_tp_perfcounter_select"/>
+
+ <!-- this seems to be the register that CP_RUN_OPENCL writes: -->
+ <reg32 offset="0x21f0" name="VGT_CL_INITIATOR"/>
+
+ <!-- seems to be same as a2xx according to fwdump.. -->
+ <reg32 offset="0x21f9" name="VGT_EVENT_INITIATOR"/>
+ <reg32 offset="0x21fc" name="VGT_DRAW_INITIATOR" type="vgt_draw_initiator"/>
+ <reg32 offset="0x21fd" name="VGT_IMMED_DATA"/>
+</domain>
+
+<domain name="A3XX_TEX_SAMP" width="32">
+ <doc>Texture sampler dwords</doc>
+ <enum name="a3xx_tex_filter">
+ <value name="A3XX_TEX_NEAREST" value="0"/>
+ <value name="A3XX_TEX_LINEAR" value="1"/>
+ <value name="A3XX_TEX_ANISO" value="2"/>
+ </enum>
+ <enum name="a3xx_tex_clamp">
+ <value name="A3XX_TEX_REPEAT" value="0"/>
+ <value name="A3XX_TEX_CLAMP_TO_EDGE" value="1"/>
+ <value name="A3XX_TEX_MIRROR_REPEAT" value="2"/>
+ <value name="A3XX_TEX_CLAMP_TO_BORDER" value="3"/>
+ <value name="A3XX_TEX_MIRROR_CLAMP" value="4"/>
+ </enum>
+ <enum name="a3xx_tex_aniso">
+ <value name="A3XX_TEX_ANISO_1" value="0"/>
+ <value name="A3XX_TEX_ANISO_2" value="1"/>
+ <value name="A3XX_TEX_ANISO_4" value="2"/>
+ <value name="A3XX_TEX_ANISO_8" value="3"/>
+ <value name="A3XX_TEX_ANISO_16" value="4"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="CLAMPENABLE" pos="0" type="boolean"/>
+ <bitfield name="MIPFILTER_LINEAR" pos="1" type="boolean"/>
+ <bitfield name="XY_MAG" low="2" high="3" type="a3xx_tex_filter"/>
+ <bitfield name="XY_MIN" low="4" high="5" type="a3xx_tex_filter"/>
+ <bitfield name="WRAP_S" low="6" high="8" type="a3xx_tex_clamp"/>
+ <bitfield name="WRAP_T" low="9" high="11" type="a3xx_tex_clamp"/>
+ <bitfield name="WRAP_R" low="12" high="14" type="a3xx_tex_clamp"/>
+ <bitfield name="ANISO" low="15" high="17" type="a3xx_tex_aniso"/>
+ <bitfield name="COMPARE_FUNC" low="20" high="22" type="adreno_compare_func"/>
+ <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="24" type="boolean"/>
+ <!-- UNNORM_COORDS == CLK_NORMALIZED_COORDS_FALSE -->
+ <bitfield name="UNNORM_COORDS" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="LOD_BIAS" low="0" high="10" type="fixed" radix="6"/>
+ <bitfield name="MAX_LOD" low="12" high="21" type="ufixed" radix="6"/>
+ <bitfield name="MIN_LOD" low="22" high="31" type="ufixed" radix="6"/>
+ </reg32>
+</domain>
+
+<domain name="A3XX_TEX_CONST" width="32">
+ <doc>Texture constant dwords</doc>
+ <enum name="a3xx_tex_swiz">
+ <!-- same as a2xx? -->
+ <value name="A3XX_TEX_X" value="0"/>
+ <value name="A3XX_TEX_Y" value="1"/>
+ <value name="A3XX_TEX_Z" value="2"/>
+ <value name="A3XX_TEX_W" value="3"/>
+ <value name="A3XX_TEX_ZERO" value="4"/>
+ <value name="A3XX_TEX_ONE" value="5"/>
+ </enum>
+ <enum name="a3xx_tex_type">
+ <value name="A3XX_TEX_1D" value="0"/>
+ <value name="A3XX_TEX_2D" value="1"/>
+ <value name="A3XX_TEX_CUBE" value="2"/>
+ <value name="A3XX_TEX_3D" value="3"/>
+ </enum>
+ <enum name="a3xx_tex_msaa">
+ <value name="A3XX_TPL1_MSAA1X" value="0"/>
+ <value name="A3XX_TPL1_MSAA2X" value="1"/>
+ <value name="A3XX_TPL1_MSAA4X" value="2"/>
+ <value name="A3XX_TPL1_MSAA8X" value="3"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="TILE_MODE" low="0" high="1" type="a3xx_tile_mode"/>
+ <bitfield name="SRGB" pos="2" type="boolean"/>
+ <bitfield name="SWIZ_X" low="4" high="6" type="a3xx_tex_swiz"/>
+ <bitfield name="SWIZ_Y" low="7" high="9" type="a3xx_tex_swiz"/>
+ <bitfield name="SWIZ_Z" low="10" high="12" type="a3xx_tex_swiz"/>
+ <bitfield name="SWIZ_W" low="13" high="15" type="a3xx_tex_swiz"/>
+ <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
+ <bitfield name="MSAATEX" low="20" high="21" type="a3xx_tex_msaa"/>
+ <bitfield name="FMT" low="22" high="28" type="a3xx_tex_fmt"/>
+ <bitfield name="NOCONVERT" pos="29" type="boolean"/>
+ <bitfield name="TYPE" low="30" high="31" type="a3xx_tex_type"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="HEIGHT" low="0" high="13" type="uint"/>
+ <bitfield name="WIDTH" low="14" high="27" type="uint"/>
+ <!-- minimum pitch (for mipmap levels): log2(pitchalign / 16) -->
+ <bitfield name="PITCHALIGN" low="28" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <doc>INDX is index of texture address(es) in MIPMAP state block</doc>
+ <bitfield name="INDX" low="0" high="8" type="uint"/>
+ <doc>Pitch in bytes (so actually stride)</doc>
+ <bitfield name="PITCH" low="12" high="29" type="uint"/>
+ <doc>SWAP bit is set for BGRA instead of RGBA</doc>
+ <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <!--
+ Update: the two LAYERSZn seem not to be the same thing.
+ According to Ilia's experimentation the first one goes up
+ to at *least* bit 14..
+ -->
+ <bitfield name="LAYERSZ1" low="0" high="16" shr="12" type="uint"/>
+ <bitfield name="DEPTH" low="17" high="27" type="uint"/>
+ <bitfield name="LAYERSZ2" low="28" high="31" shr="12" type="uint"/>
+ </reg32>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/adreno/a4xx.xml b/drivers/gpu/drm/msm/registers/adreno/a4xx.xml
new file mode 100644
index 000000000000..69a9f9b02bc9
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/adreno/a4xx.xml
@@ -0,0 +1,2409 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+<import file="adreno/adreno_common.xml"/>
+<import file="adreno/adreno_pm4.xml"/>
+
+<enum name="a4xx_color_fmt">
+ <value name="RB4_A8_UNORM" value="0x01"/>
+ <value name="RB4_R8_UNORM" value="0x02"/>
+ <value name="RB4_R8_SNORM" value="0x03"/>
+ <value name="RB4_R8_UINT" value="0x04"/>
+ <value name="RB4_R8_SINT" value="0x05"/>
+
+ <value name="RB4_R4G4B4A4_UNORM" value="0x08"/>
+ <value name="RB4_R5G5B5A1_UNORM" value="0x0a"/>
+ <value name="RB4_R5G6B5_UNORM" value="0x0e"/>
+ <value name="RB4_R8G8_UNORM" value="0x0f"/>
+ <value name="RB4_R8G8_SNORM" value="0x10"/>
+ <value name="RB4_R8G8_UINT" value="0x11"/>
+ <value name="RB4_R8G8_SINT" value="0x12"/>
+ <value name="RB4_R16_UNORM" value="0x13"/>
+ <value name="RB4_R16_SNORM" value="0x14"/>
+ <value name="RB4_R16_FLOAT" value="0x15"/>
+ <value name="RB4_R16_UINT" value="0x16"/>
+ <value name="RB4_R16_SINT" value="0x17"/>
+
+ <value name="RB4_R8G8B8_UNORM" value="0x19"/>
+
+ <value name="RB4_R8G8B8A8_UNORM" value="0x1a"/>
+ <value name="RB4_R8G8B8A8_SNORM" value="0x1c"/>
+ <value name="RB4_R8G8B8A8_UINT" value="0x1d"/>
+ <value name="RB4_R8G8B8A8_SINT" value="0x1e"/>
+ <value name="RB4_R10G10B10A2_UNORM" value="0x1f"/>
+ <value name="RB4_R10G10B10A2_UINT" value="0x22"/>
+ <value name="RB4_R11G11B10_FLOAT" value="0x27"/>
+ <value name="RB4_R16G16_UNORM" value="0x28"/>
+ <value name="RB4_R16G16_SNORM" value="0x29"/>
+ <value name="RB4_R16G16_FLOAT" value="0x2a"/>
+ <value name="RB4_R16G16_UINT" value="0x2b"/>
+ <value name="RB4_R16G16_SINT" value="0x2c"/>
+ <value name="RB4_R32_FLOAT" value="0x2d"/>
+ <value name="RB4_R32_UINT" value="0x2e"/>
+ <value name="RB4_R32_SINT" value="0x2f"/>
+
+ <value name="RB4_R16G16B16A16_UNORM" value="0x34"/>
+ <value name="RB4_R16G16B16A16_SNORM" value="0x35"/>
+ <value name="RB4_R16G16B16A16_FLOAT" value="0x36"/>
+ <value name="RB4_R16G16B16A16_UINT" value="0x37"/>
+ <value name="RB4_R16G16B16A16_SINT" value="0x38"/>
+ <value name="RB4_R32G32_FLOAT" value="0x39"/>
+ <value name="RB4_R32G32_UINT" value="0x3a"/>
+ <value name="RB4_R32G32_SINT" value="0x3b"/>
+
+ <value name="RB4_R32G32B32A32_FLOAT" value="0x3c"/>
+ <value name="RB4_R32G32B32A32_UINT" value="0x3d"/>
+ <value name="RB4_R32G32B32A32_SINT" value="0x3e"/>
+
+ <value name="RB4_NONE" value="0xff"/>
+</enum>
+
+<enum name="a4xx_tile_mode">
+ <value name="TILE4_LINEAR" value="0"/>
+ <value name="TILE4_2" value="2"/>
+ <value name="TILE4_3" value="3"/>
+</enum>
+
+<enum name="a4xx_vtx_fmt" prefix="chipset">
+ <!-- hmm, shifted one compared to a3xx?!? -->
+ <value name="VFMT4_32_FLOAT" value="0x1"/>
+ <value name="VFMT4_32_32_FLOAT" value="0x2"/>
+ <value name="VFMT4_32_32_32_FLOAT" value="0x3"/>
+ <value name="VFMT4_32_32_32_32_FLOAT" value="0x4"/>
+
+ <value name="VFMT4_16_FLOAT" value="0x5"/>
+ <value name="VFMT4_16_16_FLOAT" value="0x6"/>
+ <value name="VFMT4_16_16_16_FLOAT" value="0x7"/>
+ <value name="VFMT4_16_16_16_16_FLOAT" value="0x8"/>
+
+ <value name="VFMT4_32_FIXED" value="0x9"/>
+ <value name="VFMT4_32_32_FIXED" value="0xa"/>
+ <value name="VFMT4_32_32_32_FIXED" value="0xb"/>
+ <value name="VFMT4_32_32_32_32_FIXED" value="0xc"/>
+
+ <value name="VFMT4_11_11_10_FLOAT" value="0xd"/>
+
+ <!-- beyond here it does not appear to be shifted -->
+ <value name="VFMT4_16_SINT" value="0x10"/>
+ <value name="VFMT4_16_16_SINT" value="0x11"/>
+ <value name="VFMT4_16_16_16_SINT" value="0x12"/>
+ <value name="VFMT4_16_16_16_16_SINT" value="0x13"/>
+ <value name="VFMT4_16_UINT" value="0x14"/>
+ <value name="VFMT4_16_16_UINT" value="0x15"/>
+ <value name="VFMT4_16_16_16_UINT" value="0x16"/>
+ <value name="VFMT4_16_16_16_16_UINT" value="0x17"/>
+ <value name="VFMT4_16_SNORM" value="0x18"/>
+ <value name="VFMT4_16_16_SNORM" value="0x19"/>
+ <value name="VFMT4_16_16_16_SNORM" value="0x1a"/>
+ <value name="VFMT4_16_16_16_16_SNORM" value="0x1b"/>
+ <value name="VFMT4_16_UNORM" value="0x1c"/>
+ <value name="VFMT4_16_16_UNORM" value="0x1d"/>
+ <value name="VFMT4_16_16_16_UNORM" value="0x1e"/>
+ <value name="VFMT4_16_16_16_16_UNORM" value="0x1f"/>
+
+ <value name="VFMT4_32_UINT" value="0x20"/>
+ <value name="VFMT4_32_32_UINT" value="0x21"/>
+ <value name="VFMT4_32_32_32_UINT" value="0x22"/>
+ <value name="VFMT4_32_32_32_32_UINT" value="0x23"/>
+ <value name="VFMT4_32_SINT" value="0x24"/>
+ <value name="VFMT4_32_32_SINT" value="0x25"/>
+ <value name="VFMT4_32_32_32_SINT" value="0x26"/>
+ <value name="VFMT4_32_32_32_32_SINT" value="0x27"/>
+
+ <value name="VFMT4_8_UINT" value="0x28"/>
+ <value name="VFMT4_8_8_UINT" value="0x29"/>
+ <value name="VFMT4_8_8_8_UINT" value="0x2a"/>
+ <value name="VFMT4_8_8_8_8_UINT" value="0x2b"/>
+ <value name="VFMT4_8_UNORM" value="0x2c"/>
+ <value name="VFMT4_8_8_UNORM" value="0x2d"/>
+ <value name="VFMT4_8_8_8_UNORM" value="0x2e"/>
+ <value name="VFMT4_8_8_8_8_UNORM" value="0x2f"/>
+ <value name="VFMT4_8_SINT" value="0x30"/>
+ <value name="VFMT4_8_8_SINT" value="0x31"/>
+ <value name="VFMT4_8_8_8_SINT" value="0x32"/>
+ <value name="VFMT4_8_8_8_8_SINT" value="0x33"/>
+ <value name="VFMT4_8_SNORM" value="0x34"/>
+ <value name="VFMT4_8_8_SNORM" value="0x35"/>
+ <value name="VFMT4_8_8_8_SNORM" value="0x36"/>
+ <value name="VFMT4_8_8_8_8_SNORM" value="0x37"/>
+
+ <value name="VFMT4_10_10_10_2_UINT" value="0x38"/>
+ <value name="VFMT4_10_10_10_2_UNORM" value="0x39"/>
+ <value name="VFMT4_10_10_10_2_SINT" value="0x3a"/>
+ <value name="VFMT4_10_10_10_2_SNORM" value="0x3b"/>
+ <value name="VFMT4_2_10_10_10_UINT" value="0x3c"/>
+ <value name="VFMT4_2_10_10_10_UNORM" value="0x3d"/>
+ <value name="VFMT4_2_10_10_10_SINT" value="0x3e"/>
+ <value name="VFMT4_2_10_10_10_SNORM" value="0x3f"/>
+
+ <value name="VFMT4_NONE" value="0xff"/>
+</enum>
+
+<enum name="a4xx_tex_fmt">
+ <!-- 0x00 .. 0x02 -->
+
+ <!-- 8-bit formats -->
+ <value name="TFMT4_A8_UNORM" value="0x03"/>
+ <value name="TFMT4_8_UNORM" value="0x04"/>
+ <value name="TFMT4_8_SNORM" value="0x05"/>
+ <value name="TFMT4_8_UINT" value="0x06"/>
+ <value name="TFMT4_8_SINT" value="0x07"/>
+
+ <!-- 16-bit formats -->
+ <value name="TFMT4_4_4_4_4_UNORM" value="0x08"/>
+ <value name="TFMT4_5_5_5_1_UNORM" value="0x09"/>
+ <!-- 0x0a -->
+ <value name="TFMT4_5_6_5_UNORM" value="0x0b"/>
+
+ <!-- 0x0c -->
+
+ <value name="TFMT4_L8_A8_UNORM" value="0x0d"/>
+ <value name="TFMT4_8_8_UNORM" value="0x0e"/>
+ <value name="TFMT4_8_8_SNORM" value="0x0f"/>
+ <value name="TFMT4_8_8_UINT" value="0x10"/>
+ <value name="TFMT4_8_8_SINT" value="0x11"/>
+
+ <value name="TFMT4_16_UNORM" value="0x12"/>
+ <value name="TFMT4_16_SNORM" value="0x13"/>
+ <value name="TFMT4_16_FLOAT" value="0x14"/>
+ <value name="TFMT4_16_UINT" value="0x15"/>
+ <value name="TFMT4_16_SINT" value="0x16"/>
+
+ <!-- 0x17 .. 0x1b -->
+
+ <!-- 32-bit formats -->
+ <value name="TFMT4_8_8_8_8_UNORM" value="0x1c"/>
+ <value name="TFMT4_8_8_8_8_SNORM" value="0x1d"/>
+ <value name="TFMT4_8_8_8_8_UINT" value="0x1e"/>
+ <value name="TFMT4_8_8_8_8_SINT" value="0x1f"/>
+
+ <value name="TFMT4_9_9_9_E5_FLOAT" value="0x20"/>
+ <value name="TFMT4_10_10_10_2_UNORM" value="0x21"/>
+ <value name="TFMT4_10_10_10_2_UINT" value="0x22"/>
+ <!-- 0x23 .. 0x24 -->
+ <value name="TFMT4_11_11_10_FLOAT" value="0x25"/>
+
+ <value name="TFMT4_16_16_UNORM" value="0x26"/>
+ <value name="TFMT4_16_16_SNORM" value="0x27"/>
+ <value name="TFMT4_16_16_FLOAT" value="0x28"/>
+ <value name="TFMT4_16_16_UINT" value="0x29"/>
+ <value name="TFMT4_16_16_SINT" value="0x2a"/>
+
+ <value name="TFMT4_32_FLOAT" value="0x2b"/>
+ <value name="TFMT4_32_UINT" value="0x2c"/>
+ <value name="TFMT4_32_SINT" value="0x2d"/>
+
+ <!-- 0x2e .. 0x32 -->
+
+ <!-- 64-bit formats -->
+ <value name="TFMT4_16_16_16_16_UNORM" value="0x33"/>
+ <value name="TFMT4_16_16_16_16_SNORM" value="0x34"/>
+ <value name="TFMT4_16_16_16_16_FLOAT" value="0x35"/>
+ <value name="TFMT4_16_16_16_16_UINT" value="0x36"/>
+ <value name="TFMT4_16_16_16_16_SINT" value="0x37"/>
+
+ <value name="TFMT4_32_32_FLOAT" value="0x38"/>
+ <value name="TFMT4_32_32_UINT" value="0x39"/>
+ <value name="TFMT4_32_32_SINT" value="0x3a"/>
+
+ <!-- 96-bit formats -->
+ <value name="TFMT4_32_32_32_FLOAT" value="0x3b"/>
+ <value name="TFMT4_32_32_32_UINT" value="0x3c"/>
+ <value name="TFMT4_32_32_32_SINT" value="0x3d"/>
+
+ <!-- 0x3e -->
+
+ <!-- 128-bit formats -->
+ <value name="TFMT4_32_32_32_32_FLOAT" value="0x3f"/>
+ <value name="TFMT4_32_32_32_32_UINT" value="0x40"/>
+ <value name="TFMT4_32_32_32_32_SINT" value="0x41"/>
+
+ <!-- 0x42 .. 0x46 -->
+ <value name="TFMT4_X8Z24_UNORM" value="0x47"/>
+ <!-- 0x48 .. 0x55 -->
+
+ <!-- compressed formats -->
+ <value name="TFMT4_DXT1" value="0x56"/>
+ <value name="TFMT4_DXT3" value="0x57"/>
+ <value name="TFMT4_DXT5" value="0x58"/>
+ <!-- 0x59 -->
+ <value name="TFMT4_RGTC1_UNORM" value="0x5a"/>
+ <value name="TFMT4_RGTC1_SNORM" value="0x5b"/>
+ <!-- 0x5c .. 0x5d -->
+ <value name="TFMT4_RGTC2_UNORM" value="0x5e"/>
+ <value name="TFMT4_RGTC2_SNORM" value="0x5f"/>
+ <!-- 0x60 -->
+ <value name="TFMT4_BPTC_UFLOAT" value="0x61"/>
+ <value name="TFMT4_BPTC_FLOAT" value="0x62"/>
+ <value name="TFMT4_BPTC" value="0x63"/>
+ <value name="TFMT4_ATC_RGB" value="0x64"/>
+ <value name="TFMT4_ATC_RGBA_EXPLICIT" value="0x65"/>
+ <value name="TFMT4_ATC_RGBA_INTERPOLATED" value="0x66"/>
+ <value name="TFMT4_ETC2_RG11_UNORM" value="0x67"/>
+ <value name="TFMT4_ETC2_RG11_SNORM" value="0x68"/>
+ <value name="TFMT4_ETC2_R11_UNORM" value="0x69"/>
+ <value name="TFMT4_ETC2_R11_SNORM" value="0x6a"/>
+ <value name="TFMT4_ETC1" value="0x6b"/>
+ <value name="TFMT4_ETC2_RGB8" value="0x6c"/>
+ <value name="TFMT4_ETC2_RGBA8" value="0x6d"/>
+ <value name="TFMT4_ETC2_RGB8A1" value="0x6e"/>
+ <value name="TFMT4_ASTC_4x4" value="0x6f"/>
+ <value name="TFMT4_ASTC_5x4" value="0x70"/>
+ <value name="TFMT4_ASTC_5x5" value="0x71"/>
+ <value name="TFMT4_ASTC_6x5" value="0x72"/>
+ <value name="TFMT4_ASTC_6x6" value="0x73"/>
+ <value name="TFMT4_ASTC_8x5" value="0x74"/>
+ <value name="TFMT4_ASTC_8x6" value="0x75"/>
+ <value name="TFMT4_ASTC_8x8" value="0x76"/>
+ <value name="TFMT4_ASTC_10x5" value="0x77"/>
+ <value name="TFMT4_ASTC_10x6" value="0x78"/>
+ <value name="TFMT4_ASTC_10x8" value="0x79"/>
+ <value name="TFMT4_ASTC_10x10" value="0x7a"/>
+ <value name="TFMT4_ASTC_12x10" value="0x7b"/>
+ <value name="TFMT4_ASTC_12x12" value="0x7c"/>
+ <!-- 0x7d .. 0x7f -->
+
+ <value name="TFMT4_NONE" value="0xff"/>
+</enum>
+
+<enum name="a4xx_depth_format">
+ <value name="DEPTH4_NONE" value="0"/>
+ <value name="DEPTH4_16" value="1"/>
+ <value name="DEPTH4_24_8" value="2"/>
+ <value name="DEPTH4_32" value="3"/>
+</enum>
+
+<!--
+NOTE counters extracted from test-perf log with the following awful
+script:
+##################
+#!/bin/bash
+
+log=$1
+
+grep -F "counter
+countable
+group" $log | grep -v gl > shortlist.txt
+
+countable=""
+IFS=$'\n'; for line in $(cat shortlist.txt); do
+ # parse ######### group[$n]: $name
+ l=${line########### group}
+ if [ $l != $line ]; then
+ group=`echo $line | awk '{print $3}'`
+ echo "Group: $group"
+ continue
+ fi
+ # parse ######### counter[$n]: $name
+ l=${line########### counter}
+ if [ $l != $line ]; then
+ countable=`echo $line | awk '{print $3}'`
+ #echo " Countable: $countable"
+ continue
+ fi
+ # parse countable:
+ l=${line## countable:}
+ if [ $l != $line ]; then
+ val=`echo $line | awk '{print $2}'`
+ echo "<value value=\"$val\" name=\"$countable\"/>"
+ fi
+
+done
+##################
+ -->
+<enum name="a4xx_ccu_perfcounter_select">
+ <value value="0" name="CCU_BUSY_CYCLES"/>
+ <value value="2" name="CCU_RB_DEPTH_RETURN_STALL"/>
+ <value value="3" name="CCU_RB_COLOR_RETURN_STALL"/>
+ <value value="6" name="CCU_DEPTH_BLOCKS"/>
+ <value value="7" name="CCU_COLOR_BLOCKS"/>
+ <value value="8" name="CCU_DEPTH_BLOCK_HIT"/>
+ <value value="9" name="CCU_COLOR_BLOCK_HIT"/>
+ <value value="10" name="CCU_DEPTH_FLAG1_COUNT"/>
+ <value value="11" name="CCU_DEPTH_FLAG2_COUNT"/>
+ <value value="12" name="CCU_DEPTH_FLAG3_COUNT"/>
+ <value value="13" name="CCU_DEPTH_FLAG4_COUNT"/>
+ <value value="14" name="CCU_COLOR_FLAG1_COUNT"/>
+ <value value="15" name="CCU_COLOR_FLAG2_COUNT"/>
+ <value value="16" name="CCU_COLOR_FLAG3_COUNT"/>
+ <value value="17" name="CCU_COLOR_FLAG4_COUNT"/>
+ <value value="18" name="CCU_PARTIAL_BLOCK_READ"/>
+</enum>
+
+<!--
+NOTE other than CP_ALWAYS_COUNT (which is the only one we use so far),
+on a3xx the countable #'s from AMD_performance_monitor disagreed with
+TRM. All these #'s for a4xx come from AMD_performance_monitor, so
+perhaps they should be taken with a grain of salt
+-->
+<enum name="a4xx_cp_perfcounter_select">
+ <!-- first ctr at least seems same as a3xx, so we can measure freq -->
+ <value value="0" name="CP_ALWAYS_COUNT"/>
+ <value value="1" name="CP_BUSY"/>
+ <value value="2" name="CP_PFP_IDLE"/>
+ <value value="3" name="CP_PFP_BUSY_WORKING"/>
+ <value value="4" name="CP_PFP_STALL_CYCLES_ANY"/>
+ <value value="5" name="CP_PFP_STARVE_CYCLES_ANY"/>
+ <value value="6" name="CP_PFP_STARVED_PER_LOAD_ADDR"/>
+ <value value="7" name="CP_PFP_STALLED_PER_STORE_ADDR"/>
+ <value value="8" name="CP_PFP_PC_PROFILE"/>
+ <value value="9" name="CP_PFP_MATCH_PM4_PKT_PROFILE"/>
+ <value value="10" name="CP_PFP_COND_INDIRECT_DISCARDED"/>
+ <value value="11" name="CP_LONG_RESUMPTIONS"/>
+ <value value="12" name="CP_RESUME_CYCLES"/>
+ <value value="13" name="CP_RESUME_TO_BOUNDARY_CYCLES"/>
+ <value value="14" name="CP_LONG_PREEMPTIONS"/>
+ <value value="15" name="CP_PREEMPT_CYCLES"/>
+ <value value="16" name="CP_PREEMPT_TO_BOUNDARY_CYCLES"/>
+ <value value="17" name="CP_ME_FIFO_EMPTY_PFP_IDLE"/>
+ <value value="18" name="CP_ME_FIFO_EMPTY_PFP_BUSY"/>
+ <value value="19" name="CP_ME_FIFO_NOT_EMPTY_NOT_FULL"/>
+ <value value="20" name="CP_ME_FIFO_FULL_ME_BUSY"/>
+ <value value="21" name="CP_ME_FIFO_FULL_ME_NON_WORKING"/>
+ <value value="22" name="CP_ME_WAITING_FOR_PACKETS"/>
+ <value value="23" name="CP_ME_BUSY_WORKING"/>
+ <value value="24" name="CP_ME_STARVE_CYCLES_ANY"/>
+ <value value="25" name="CP_ME_STARVE_CYCLES_PER_PROFILE"/>
+ <value value="26" name="CP_ME_STALL_CYCLES_PER_PROFILE"/>
+ <value value="27" name="CP_ME_PC_PROFILE"/>
+ <value value="28" name="CP_RCIU_FIFO_EMPTY"/>
+ <value value="29" name="CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL"/>
+ <value value="30" name="CP_RCIU_FIFO_FULL"/>
+ <value value="31" name="CP_RCIU_FIFO_FULL_NO_CONTEXT"/>
+ <value value="32" name="CP_RCIU_FIFO_FULL_AHB_MASTER"/>
+ <value value="33" name="CP_RCIU_FIFO_FULL_OTHER"/>
+ <value value="34" name="CP_AHB_IDLE"/>
+ <value value="35" name="CP_AHB_STALL_ON_GRANT_NO_SPLIT"/>
+ <value value="36" name="CP_AHB_STALL_ON_GRANT_SPLIT"/>
+ <value value="37" name="CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE"/>
+ <value value="38" name="CP_AHB_BUSY_WORKING"/>
+ <value value="39" name="CP_AHB_BUSY_STALL_ON_HRDY"/>
+ <value value="40" name="CP_AHB_BUSY_STALL_ON_HRDY_PROFILE"/>
+</enum>
+
+<enum name="a4xx_gras_ras_perfcounter_select">
+ <value value="0" name="RAS_SUPER_TILES"/>
+ <value value="1" name="RAS_8X8_TILES"/>
+ <value value="2" name="RAS_4X4_TILES"/>
+ <value value="3" name="RAS_BUSY_CYCLES"/>
+ <value value="4" name="RAS_STALL_CYCLES_BY_RB"/>
+ <value value="5" name="RAS_STALL_CYCLES_BY_VSC"/>
+ <value value="6" name="RAS_STARVE_CYCLES_BY_TSE"/>
+ <value value="7" name="RAS_SUPERTILE_CYCLES"/>
+ <value value="8" name="RAS_TILE_CYCLES"/>
+ <value value="9" name="RAS_FULLY_COVERED_SUPER_TILES"/>
+ <value value="10" name="RAS_FULLY_COVERED_8X8_TILES"/>
+ <value value="11" name="RAS_4X4_PRIM"/>
+ <value value="12" name="RAS_8X4_4X8_PRIM"/>
+ <value value="13" name="RAS_8X8_PRIM"/>
+</enum>
+
+<enum name="a4xx_gras_tse_perfcounter_select">
+ <value value="0" name="TSE_INPUT_PRIM"/>
+ <value value="1" name="TSE_INPUT_NULL_PRIM"/>
+ <value value="2" name="TSE_TRIVAL_REJ_PRIM"/>
+ <value value="3" name="TSE_CLIPPED_PRIM"/>
+ <value value="4" name="TSE_NEW_PRIM"/>
+ <value value="5" name="TSE_ZERO_AREA_PRIM"/>
+ <value value="6" name="TSE_FACENESS_CULLED_PRIM"/>
+ <value value="7" name="TSE_ZERO_PIXEL_PRIM"/>
+ <value value="8" name="TSE_OUTPUT_NULL_PRIM"/>
+ <value value="9" name="TSE_OUTPUT_VISIBLE_PRIM"/>
+ <value value="10" name="TSE_PRE_CLIP_PRIM"/>
+ <value value="11" name="TSE_POST_CLIP_PRIM"/>
+ <value value="12" name="TSE_BUSY_CYCLES"/>
+ <value value="13" name="TSE_PC_STARVE"/>
+ <value value="14" name="TSE_RAS_STALL"/>
+ <value value="15" name="TSE_STALL_BARYPLANE_FIFO_FULL"/>
+ <value value="16" name="TSE_STALL_ZPLANE_FIFO_FULL"/>
+</enum>
+
+<enum name="a4xx_hlsq_perfcounter_select">
+ <value value="0" name="HLSQ_SP_VS_STAGE_CONSTANT"/>
+ <value value="1" name="HLSQ_SP_VS_STAGE_INSTRUCTIONS"/>
+ <value value="2" name="HLSQ_SP_FS_STAGE_CONSTANT"/>
+ <value value="3" name="HLSQ_SP_FS_STAGE_INSTRUCTIONS"/>
+ <value value="4" name="HLSQ_TP_STATE"/>
+ <value value="5" name="HLSQ_QUADS"/>
+ <value value="6" name="HLSQ_PIXELS"/>
+ <value value="7" name="HLSQ_VERTICES"/>
+ <value value="13" name="HLSQ_SP_VS_STAGE_DATA_BYTES"/>
+ <value value="14" name="HLSQ_SP_FS_STAGE_DATA_BYTES"/>
+ <value value="15" name="HLSQ_BUSY_CYCLES"/>
+ <value value="16" name="HLSQ_STALL_CYCLES_SP_STATE"/>
+ <value value="17" name="HLSQ_STALL_CYCLES_SP_VS_STAGE"/>
+ <value value="18" name="HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
+ <value value="19" name="HLSQ_STALL_CYCLES_UCHE"/>
+ <value value="20" name="HLSQ_RBBM_LOAD_CYCLES"/>
+ <value value="21" name="HLSQ_DI_TO_VS_START_SP"/>
+ <value value="22" name="HLSQ_DI_TO_FS_START_SP"/>
+ <value value="23" name="HLSQ_VS_STAGE_START_TO_DONE_SP"/>
+ <value value="24" name="HLSQ_FS_STAGE_START_TO_DONE_SP"/>
+ <value value="25" name="HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE"/>
+ <value value="26" name="HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE"/>
+ <value value="27" name="HLSQ_UCHE_LATENCY_CYCLES"/>
+ <value value="28" name="HLSQ_UCHE_LATENCY_COUNT"/>
+ <value value="29" name="HLSQ_STARVE_CYCLES_VFD"/>
+</enum>
+
+<enum name="a4xx_pc_perfcounter_select">
+ <value value="0" name="PC_VIS_STREAMS_LOADED"/>
+ <value value="2" name="PC_VPC_PRIMITIVES"/>
+ <value value="3" name="PC_DEAD_PRIM"/>
+ <value value="4" name="PC_LIVE_PRIM"/>
+ <value value="5" name="PC_DEAD_DRAWCALLS"/>
+ <value value="6" name="PC_LIVE_DRAWCALLS"/>
+ <value value="7" name="PC_VERTEX_MISSES"/>
+ <value value="9" name="PC_STALL_CYCLES_VFD"/>
+ <value value="10" name="PC_STALL_CYCLES_TSE"/>
+ <value value="11" name="PC_STALL_CYCLES_UCHE"/>
+ <value value="12" name="PC_WORKING_CYCLES"/>
+ <value value="13" name="PC_IA_VERTICES"/>
+ <value value="14" name="PC_GS_PRIMITIVES"/>
+ <value value="15" name="PC_HS_INVOCATIONS"/>
+ <value value="16" name="PC_DS_INVOCATIONS"/>
+ <value value="17" name="PC_DS_PRIMITIVES"/>
+ <value value="20" name="PC_STARVE_CYCLES_FOR_INDEX"/>
+ <value value="21" name="PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
+ <value value="22" name="PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
+ <value value="23" name="PC_STALL_CYCLES_TESS"/>
+ <value value="24" name="PC_STARVE_CYCLES_FOR_POSITION"/>
+ <value value="25" name="PC_MODE0_DRAWCALL"/>
+ <value value="26" name="PC_MODE1_DRAWCALL"/>
+ <value value="27" name="PC_MODE2_DRAWCALL"/>
+ <value value="28" name="PC_MODE3_DRAWCALL"/>
+ <value value="29" name="PC_MODE4_DRAWCALL"/>
+ <value value="30" name="PC_PREDICATED_DEAD_DRAWCALL"/>
+ <value value="31" name="PC_STALL_CYCLES_BY_TSE_ONLY"/>
+ <value value="32" name="PC_STALL_CYCLES_BY_VPC_ONLY"/>
+ <value value="33" name="PC_VPC_POS_DATA_TRANSACTION"/>
+ <value value="34" name="PC_BUSY_CYCLES"/>
+ <value value="35" name="PC_STARVE_CYCLES_DI"/>
+ <value value="36" name="PC_STALL_CYCLES_VPC"/>
+ <value value="37" name="TESS_WORKING_CYCLES"/>
+ <value value="38" name="TESS_NUM_CYCLES_SETUP_WORKING"/>
+ <value value="39" name="TESS_NUM_CYCLES_PTGEN_WORKING"/>
+ <value value="40" name="TESS_NUM_CYCLES_CONNGEN_WORKING"/>
+ <value value="41" name="TESS_BUSY_CYCLES"/>
+ <value value="42" name="TESS_STARVE_CYCLES_PC"/>
+ <value value="43" name="TESS_STALL_CYCLES_PC"/>
+</enum>
+
+<enum name="a4xx_pwr_perfcounter_select">
+ <!-- NOTE not actually used.. see RBBM_RBBM_CTL.RESET_PWR_CTR0/1 -->
+ <value value="0" name="PWR_CORE_CLOCK_CYCLES"/>
+ <value value="1" name="PWR_BUSY_CLOCK_CYCLES"/>
+</enum>
+
+<enum name="a4xx_rb_perfcounter_select">
+ <value value="0" name="RB_BUSY_CYCLES"/>
+ <value value="1" name="RB_BUSY_CYCLES_BINNING"/>
+ <value value="2" name="RB_BUSY_CYCLES_RENDERING"/>
+ <value value="3" name="RB_BUSY_CYCLES_RESOLVE"/>
+ <value value="4" name="RB_STARVE_CYCLES_BY_SP"/>
+ <value value="5" name="RB_STARVE_CYCLES_BY_RAS"/>
+ <value value="6" name="RB_STARVE_CYCLES_BY_MARB"/>
+ <value value="7" name="RB_STALL_CYCLES_BY_MARB"/>
+ <value value="8" name="RB_STALL_CYCLES_BY_HLSQ"/>
+ <value value="9" name="RB_RB_RB_MARB_DATA"/>
+ <value value="10" name="RB_SP_RB_QUAD"/>
+ <value value="11" name="RB_RAS_RB_Z_QUADS"/>
+ <value value="12" name="RB_GMEM_CH0_READ"/>
+ <value value="13" name="RB_GMEM_CH1_READ"/>
+ <value value="14" name="RB_GMEM_CH0_WRITE"/>
+ <value value="15" name="RB_GMEM_CH1_WRITE"/>
+ <value value="16" name="RB_CP_CONTEXT_DONE"/>
+ <value value="17" name="RB_CP_CACHE_FLUSH"/>
+ <value value="18" name="RB_CP_ZPASS_DONE"/>
+ <value value="19" name="RB_STALL_FIFO0_FULL"/>
+ <value value="20" name="RB_STALL_FIFO1_FULL"/>
+ <value value="21" name="RB_STALL_FIFO2_FULL"/>
+ <value value="22" name="RB_STALL_FIFO3_FULL"/>
+ <value value="23" name="RB_RB_HLSQ_TRANSACTIONS"/>
+ <value value="24" name="RB_Z_READ"/>
+ <value value="25" name="RB_Z_WRITE"/>
+ <value value="26" name="RB_C_READ"/>
+ <value value="27" name="RB_C_WRITE"/>
+ <value value="28" name="RB_C_READ_LATENCY"/>
+ <value value="29" name="RB_Z_READ_LATENCY"/>
+ <value value="30" name="RB_STALL_BY_UCHE"/>
+ <value value="31" name="RB_MARB_UCHE_TRANSACTIONS"/>
+ <value value="32" name="RB_CACHE_STALL_MISS"/>
+ <value value="33" name="RB_CACHE_STALL_FIFO_FULL"/>
+ <value value="34" name="RB_8BIT_BLENDER_UNITS_ACTIVE"/>
+ <value value="35" name="RB_16BIT_BLENDER_UNITS_ACTIVE"/>
+ <value value="36" name="RB_SAMPLER_UNITS_ACTIVE"/>
+ <value value="38" name="RB_TOTAL_PASS"/>
+ <value value="39" name="RB_Z_PASS"/>
+ <value value="40" name="RB_Z_FAIL"/>
+ <value value="41" name="RB_S_FAIL"/>
+ <value value="42" name="RB_POWER0"/>
+ <value value="43" name="RB_POWER1"/>
+ <value value="44" name="RB_POWER2"/>
+ <value value="45" name="RB_POWER3"/>
+ <value value="46" name="RB_POWER4"/>
+ <value value="47" name="RB_POWER5"/>
+ <value value="48" name="RB_POWER6"/>
+ <value value="49" name="RB_POWER7"/>
+</enum>
+
+<enum name="a4xx_rbbm_perfcounter_select">
+ <value value="0" name="RBBM_ALWAYS_ON"/>
+ <value value="1" name="RBBM_VBIF_BUSY"/>
+ <value value="2" name="RBBM_TSE_BUSY"/>
+ <value value="3" name="RBBM_RAS_BUSY"/>
+ <value value="4" name="RBBM_PC_DCALL_BUSY"/>
+ <value value="5" name="RBBM_PC_VSD_BUSY"/>
+ <value value="6" name="RBBM_VFD_BUSY"/>
+ <value value="7" name="RBBM_VPC_BUSY"/>
+ <value value="8" name="RBBM_UCHE_BUSY"/>
+ <value value="9" name="RBBM_VSC_BUSY"/>
+ <value value="10" name="RBBM_HLSQ_BUSY"/>
+ <value value="11" name="RBBM_ANY_RB_BUSY"/>
+ <value value="12" name="RBBM_ANY_TPL1_BUSY"/>
+ <value value="13" name="RBBM_ANY_SP_BUSY"/>
+ <value value="14" name="RBBM_ANY_MARB_BUSY"/>
+ <value value="15" name="RBBM_ANY_ARB_BUSY"/>
+ <value value="16" name="RBBM_AHB_STATUS_BUSY"/>
+ <value value="17" name="RBBM_AHB_STATUS_STALLED"/>
+ <value value="18" name="RBBM_AHB_STATUS_TXFR"/>
+ <value value="19" name="RBBM_AHB_STATUS_TXFR_SPLIT"/>
+ <value value="20" name="RBBM_AHB_STATUS_TXFR_ERROR"/>
+ <value value="21" name="RBBM_AHB_STATUS_LONG_STALL"/>
+ <value value="22" name="RBBM_STATUS_MASKED"/>
+ <value value="23" name="RBBM_CP_BUSY_GFX_CORE_IDLE"/>
+ <value value="24" name="RBBM_TESS_BUSY"/>
+ <value value="25" name="RBBM_COM_BUSY"/>
+ <value value="32" name="RBBM_DCOM_BUSY"/>
+ <value value="33" name="RBBM_ANY_CCU_BUSY"/>
+ <value value="34" name="RBBM_DPM_BUSY"/>
+</enum>
+
+<enum name="a4xx_sp_perfcounter_select">
+ <value value="0" name="SP_LM_LOAD_INSTRUCTIONS"/>
+ <value value="1" name="SP_LM_STORE_INSTRUCTIONS"/>
+ <value value="2" name="SP_LM_ATOMICS"/>
+ <value value="3" name="SP_GM_LOAD_INSTRUCTIONS"/>
+ <value value="4" name="SP_GM_STORE_INSTRUCTIONS"/>
+ <value value="5" name="SP_GM_ATOMICS"/>
+ <value value="6" name="SP_VS_STAGE_TEX_INSTRUCTIONS"/>
+ <value value="7" name="SP_VS_STAGE_CFLOW_INSTRUCTIONS"/>
+ <value value="8" name="SP_VS_STAGE_EFU_INSTRUCTIONS"/>
+ <value value="9" name="SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
+ <value value="10" name="SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
+ <value value="11" name="SP_FS_STAGE_TEX_INSTRUCTIONS"/>
+ <value value="12" name="SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
+ <value value="13" name="SP_FS_STAGE_EFU_INSTRUCTIONS"/>
+ <value value="14" name="SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
+ <value value="15" name="SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
+ <value value="17" name="SP_VS_INSTRUCTIONS"/>
+ <value value="18" name="SP_FS_INSTRUCTIONS"/>
+ <value value="19" name="SP_ADDR_LOCK_COUNT"/>
+ <value value="20" name="SP_UCHE_READ_TRANS"/>
+ <value value="21" name="SP_UCHE_WRITE_TRANS"/>
+ <value value="22" name="SP_EXPORT_VPC_TRANS"/>
+ <value value="23" name="SP_EXPORT_RB_TRANS"/>
+ <value value="24" name="SP_PIXELS_KILLED"/>
+ <value value="25" name="SP_ICL1_REQUESTS"/>
+ <value value="26" name="SP_ICL1_MISSES"/>
+ <value value="27" name="SP_ICL0_REQUESTS"/>
+ <value value="28" name="SP_ICL0_MISSES"/>
+ <value value="29" name="SP_ALU_WORKING_CYCLES"/>
+ <value value="30" name="SP_EFU_WORKING_CYCLES"/>
+ <value value="31" name="SP_STALL_CYCLES_BY_VPC"/>
+ <value value="32" name="SP_STALL_CYCLES_BY_TP"/>
+ <value value="33" name="SP_STALL_CYCLES_BY_UCHE"/>
+ <value value="34" name="SP_STALL_CYCLES_BY_RB"/>
+ <value value="35" name="SP_BUSY_CYCLES"/>
+ <value value="36" name="SP_HS_INSTRUCTIONS"/>
+ <value value="37" name="SP_DS_INSTRUCTIONS"/>
+ <value value="38" name="SP_GS_INSTRUCTIONS"/>
+ <value value="39" name="SP_CS_INSTRUCTIONS"/>
+ <value value="40" name="SP_SCHEDULER_NON_WORKING"/>
+ <value value="41" name="SP_WAVE_CONTEXTS"/>
+ <value value="42" name="SP_WAVE_CONTEXT_CYCLES"/>
+ <value value="43" name="SP_POWER0"/>
+ <value value="44" name="SP_POWER1"/>
+ <value value="45" name="SP_POWER2"/>
+ <value value="46" name="SP_POWER3"/>
+ <value value="47" name="SP_POWER4"/>
+ <value value="48" name="SP_POWER5"/>
+ <value value="49" name="SP_POWER6"/>
+ <value value="50" name="SP_POWER7"/>
+ <value value="51" name="SP_POWER8"/>
+ <value value="52" name="SP_POWER9"/>
+ <value value="53" name="SP_POWER10"/>
+ <value value="54" name="SP_POWER11"/>
+ <value value="55" name="SP_POWER12"/>
+ <value value="56" name="SP_POWER13"/>
+ <value value="57" name="SP_POWER14"/>
+ <value value="58" name="SP_POWER15"/>
+</enum>
+
+<enum name="a4xx_tp_perfcounter_select">
+ <value value="0" name="TP_L1_REQUESTS"/>
+ <value value="1" name="TP_L1_MISSES"/>
+ <value value="8" name="TP_QUADS_OFFSET"/>
+ <value value="9" name="TP_QUAD_SHADOW"/>
+ <value value="10" name="TP_QUADS_ARRAY"/>
+ <value value="11" name="TP_QUADS_GRADIENT"/>
+ <value value="12" name="TP_QUADS_1D2D"/>
+ <value value="13" name="TP_QUADS_3DCUBE"/>
+ <value value="16" name="TP_BUSY_CYCLES"/>
+ <value value="17" name="TP_STALL_CYCLES_BY_ARB"/>
+ <value value="20" name="TP_STATE_CACHE_REQUESTS"/>
+ <value value="21" name="TP_STATE_CACHE_MISSES"/>
+ <value value="22" name="TP_POWER0"/>
+ <value value="23" name="TP_POWER1"/>
+ <value value="24" name="TP_POWER2"/>
+ <value value="25" name="TP_POWER3"/>
+ <value value="26" name="TP_POWER4"/>
+ <value value="27" name="TP_POWER5"/>
+ <value value="28" name="TP_POWER6"/>
+ <value value="29" name="TP_POWER7"/>
+</enum>
+
+<enum name="a4xx_uche_perfcounter_select">
+ <value value="0" name="UCHE_VBIF_READ_BEATS_TP"/>
+ <value value="1" name="UCHE_VBIF_READ_BEATS_VFD"/>
+ <value value="2" name="UCHE_VBIF_READ_BEATS_HLSQ"/>
+ <value value="3" name="UCHE_VBIF_READ_BEATS_MARB"/>
+ <value value="4" name="UCHE_VBIF_READ_BEATS_SP"/>
+ <value value="5" name="UCHE_READ_REQUESTS_TP"/>
+ <value value="6" name="UCHE_READ_REQUESTS_VFD"/>
+ <value value="7" name="UCHE_READ_REQUESTS_HLSQ"/>
+ <value value="8" name="UCHE_READ_REQUESTS_MARB"/>
+ <value value="9" name="UCHE_READ_REQUESTS_SP"/>
+ <value value="10" name="UCHE_WRITE_REQUESTS_MARB"/>
+ <value value="11" name="UCHE_WRITE_REQUESTS_SP"/>
+ <value value="12" name="UCHE_TAG_CHECK_FAILS"/>
+ <value value="13" name="UCHE_EVICTS"/>
+ <value value="14" name="UCHE_FLUSHES"/>
+ <value value="15" name="UCHE_VBIF_LATENCY_CYCLES"/>
+ <value value="16" name="UCHE_VBIF_LATENCY_SAMPLES"/>
+ <value value="17" name="UCHE_BUSY_CYCLES"/>
+ <value value="18" name="UCHE_VBIF_READ_BEATS_PC"/>
+ <value value="19" name="UCHE_READ_REQUESTS_PC"/>
+ <value value="20" name="UCHE_WRITE_REQUESTS_VPC"/>
+ <value value="21" name="UCHE_STALL_BY_VBIF"/>
+ <value value="22" name="UCHE_WRITE_REQUESTS_VSC"/>
+ <value value="23" name="UCHE_POWER0"/>
+ <value value="24" name="UCHE_POWER1"/>
+ <value value="25" name="UCHE_POWER2"/>
+ <value value="26" name="UCHE_POWER3"/>
+ <value value="27" name="UCHE_POWER4"/>
+ <value value="28" name="UCHE_POWER5"/>
+ <value value="29" name="UCHE_POWER6"/>
+ <value value="30" name="UCHE_POWER7"/>
+</enum>
+
+<enum name="a4xx_vbif_perfcounter_select">
+ <value value="0" name="AXI_READ_REQUESTS_ID_0"/>
+ <value value="1" name="AXI_READ_REQUESTS_ID_1"/>
+ <value value="2" name="AXI_READ_REQUESTS_ID_2"/>
+ <value value="3" name="AXI_READ_REQUESTS_ID_3"/>
+ <value value="4" name="AXI_READ_REQUESTS_ID_4"/>
+ <value value="5" name="AXI_READ_REQUESTS_ID_5"/>
+ <value value="6" name="AXI_READ_REQUESTS_ID_6"/>
+ <value value="7" name="AXI_READ_REQUESTS_ID_7"/>
+ <value value="8" name="AXI_READ_REQUESTS_ID_8"/>
+ <value value="9" name="AXI_READ_REQUESTS_ID_9"/>
+ <value value="10" name="AXI_READ_REQUESTS_ID_10"/>
+ <value value="11" name="AXI_READ_REQUESTS_ID_11"/>
+ <value value="12" name="AXI_READ_REQUESTS_ID_12"/>
+ <value value="13" name="AXI_READ_REQUESTS_ID_13"/>
+ <value value="14" name="AXI_READ_REQUESTS_ID_14"/>
+ <value value="15" name="AXI_READ_REQUESTS_ID_15"/>
+ <value value="16" name="AXI0_READ_REQUESTS_TOTAL"/>
+ <value value="17" name="AXI1_READ_REQUESTS_TOTAL"/>
+ <value value="18" name="AXI2_READ_REQUESTS_TOTAL"/>
+ <value value="19" name="AXI3_READ_REQUESTS_TOTAL"/>
+ <value value="20" name="AXI_READ_REQUESTS_TOTAL"/>
+ <value value="21" name="AXI_WRITE_REQUESTS_ID_0"/>
+ <value value="22" name="AXI_WRITE_REQUESTS_ID_1"/>
+ <value value="23" name="AXI_WRITE_REQUESTS_ID_2"/>
+ <value value="24" name="AXI_WRITE_REQUESTS_ID_3"/>
+ <value value="25" name="AXI_WRITE_REQUESTS_ID_4"/>
+ <value value="26" name="AXI_WRITE_REQUESTS_ID_5"/>
+ <value value="27" name="AXI_WRITE_REQUESTS_ID_6"/>
+ <value value="28" name="AXI_WRITE_REQUESTS_ID_7"/>
+ <value value="29" name="AXI_WRITE_REQUESTS_ID_8"/>
+ <value value="30" name="AXI_WRITE_REQUESTS_ID_9"/>
+ <value value="31" name="AXI_WRITE_REQUESTS_ID_10"/>
+ <value value="32" name="AXI_WRITE_REQUESTS_ID_11"/>
+ <value value="33" name="AXI_WRITE_REQUESTS_ID_12"/>
+ <value value="34" name="AXI_WRITE_REQUESTS_ID_13"/>
+ <value value="35" name="AXI_WRITE_REQUESTS_ID_14"/>
+ <value value="36" name="AXI_WRITE_REQUESTS_ID_15"/>
+ <value value="37" name="AXI0_WRITE_REQUESTS_TOTAL"/>
+ <value value="38" name="AXI1_WRITE_REQUESTS_TOTAL"/>
+ <value value="39" name="AXI2_WRITE_REQUESTS_TOTAL"/>
+ <value value="40" name="AXI3_WRITE_REQUESTS_TOTAL"/>
+ <value value="41" name="AXI_WRITE_REQUESTS_TOTAL"/>
+ <value value="42" name="AXI_TOTAL_REQUESTS"/>
+ <value value="43" name="AXI_READ_DATA_BEATS_ID_0"/>
+ <value value="44" name="AXI_READ_DATA_BEATS_ID_1"/>
+ <value value="45" name="AXI_READ_DATA_BEATS_ID_2"/>
+ <value value="46" name="AXI_READ_DATA_BEATS_ID_3"/>
+ <value value="47" name="AXI_READ_DATA_BEATS_ID_4"/>
+ <value value="48" name="AXI_READ_DATA_BEATS_ID_5"/>
+ <value value="49" name="AXI_READ_DATA_BEATS_ID_6"/>
+ <value value="50" name="AXI_READ_DATA_BEATS_ID_7"/>
+ <value value="51" name="AXI_READ_DATA_BEATS_ID_8"/>
+ <value value="52" name="AXI_READ_DATA_BEATS_ID_9"/>
+ <value value="53" name="AXI_READ_DATA_BEATS_ID_10"/>
+ <value value="54" name="AXI_READ_DATA_BEATS_ID_11"/>
+ <value value="55" name="AXI_READ_DATA_BEATS_ID_12"/>
+ <value value="56" name="AXI_READ_DATA_BEATS_ID_13"/>
+ <value value="57" name="AXI_READ_DATA_BEATS_ID_14"/>
+ <value value="58" name="AXI_READ_DATA_BEATS_ID_15"/>
+ <value value="59" name="AXI0_READ_DATA_BEATS_TOTAL"/>
+ <value value="60" name="AXI1_READ_DATA_BEATS_TOTAL"/>
+ <value value="61" name="AXI2_READ_DATA_BEATS_TOTAL"/>
+ <value value="62" name="AXI3_READ_DATA_BEATS_TOTAL"/>
+ <value value="63" name="AXI_READ_DATA_BEATS_TOTAL"/>
+ <value value="64" name="AXI_WRITE_DATA_BEATS_ID_0"/>
+ <value value="65" name="AXI_WRITE_DATA_BEATS_ID_1"/>
+ <value value="66" name="AXI_WRITE_DATA_BEATS_ID_2"/>
+ <value value="67" name="AXI_WRITE_DATA_BEATS_ID_3"/>
+ <value value="68" name="AXI_WRITE_DATA_BEATS_ID_4"/>
+ <value value="69" name="AXI_WRITE_DATA_BEATS_ID_5"/>
+ <value value="70" name="AXI_WRITE_DATA_BEATS_ID_6"/>
+ <value value="71" name="AXI_WRITE_DATA_BEATS_ID_7"/>
+ <value value="72" name="AXI_WRITE_DATA_BEATS_ID_8"/>
+ <value value="73" name="AXI_WRITE_DATA_BEATS_ID_9"/>
+ <value value="74" name="AXI_WRITE_DATA_BEATS_ID_10"/>
+ <value value="75" name="AXI_WRITE_DATA_BEATS_ID_11"/>
+ <value value="76" name="AXI_WRITE_DATA_BEATS_ID_12"/>
+ <value value="77" name="AXI_WRITE_DATA_BEATS_ID_13"/>
+ <value value="78" name="AXI_WRITE_DATA_BEATS_ID_14"/>
+ <value value="79" name="AXI_WRITE_DATA_BEATS_ID_15"/>
+ <value value="80" name="AXI0_WRITE_DATA_BEATS_TOTAL"/>
+ <value value="81" name="AXI1_WRITE_DATA_BEATS_TOTAL"/>
+ <value value="82" name="AXI2_WRITE_DATA_BEATS_TOTAL"/>
+ <value value="83" name="AXI3_WRITE_DATA_BEATS_TOTAL"/>
+ <value value="84" name="AXI_WRITE_DATA_BEATS_TOTAL"/>
+ <value value="85" name="AXI_DATA_BEATS_TOTAL"/>
+ <value value="86" name="CYCLES_HELD_OFF_ID_0"/>
+ <value value="87" name="CYCLES_HELD_OFF_ID_1"/>
+ <value value="88" name="CYCLES_HELD_OFF_ID_2"/>
+ <value value="89" name="CYCLES_HELD_OFF_ID_3"/>
+ <value value="90" name="CYCLES_HELD_OFF_ID_4"/>
+ <value value="91" name="CYCLES_HELD_OFF_ID_5"/>
+ <value value="92" name="CYCLES_HELD_OFF_ID_6"/>
+ <value value="93" name="CYCLES_HELD_OFF_ID_7"/>
+ <value value="94" name="CYCLES_HELD_OFF_ID_8"/>
+ <value value="95" name="CYCLES_HELD_OFF_ID_9"/>
+ <value value="96" name="CYCLES_HELD_OFF_ID_10"/>
+ <value value="97" name="CYCLES_HELD_OFF_ID_11"/>
+ <value value="98" name="CYCLES_HELD_OFF_ID_12"/>
+ <value value="99" name="CYCLES_HELD_OFF_ID_13"/>
+ <value value="100" name="CYCLES_HELD_OFF_ID_14"/>
+ <value value="101" name="CYCLES_HELD_OFF_ID_15"/>
+ <value value="102" name="AXI_READ_REQUEST_HELD_OFF"/>
+ <value value="103" name="AXI_WRITE_REQUEST_HELD_OFF"/>
+ <value value="104" name="AXI_REQUEST_HELD_OFF"/>
+ <value value="105" name="AXI_WRITE_DATA_HELD_OFF"/>
+ <value value="106" name="OCMEM_AXI_READ_REQUEST_HELD_OFF"/>
+ <value value="107" name="OCMEM_AXI_WRITE_REQUEST_HELD_OFF"/>
+ <value value="108" name="OCMEM_AXI_REQUEST_HELD_OFF"/>
+ <value value="109" name="OCMEM_AXI_WRITE_DATA_HELD_OFF"/>
+ <value value="110" name="ELAPSED_CYCLES_DDR"/>
+ <value value="111" name="ELAPSED_CYCLES_OCMEM"/>
+</enum>
+
+<enum name="a4xx_vfd_perfcounter_select">
+ <value value="0" name="VFD_UCHE_BYTE_FETCHED"/>
+ <value value="1" name="VFD_UCHE_TRANS"/>
+ <value value="3" name="VFD_FETCH_INSTRUCTIONS"/>
+ <value value="5" name="VFD_BUSY_CYCLES"/>
+ <value value="6" name="VFD_STALL_CYCLES_UCHE"/>
+ <value value="7" name="VFD_STALL_CYCLES_HLSQ"/>
+ <value value="8" name="VFD_STALL_CYCLES_VPC_BYPASS"/>
+ <value value="9" name="VFD_STALL_CYCLES_VPC_ALLOC"/>
+ <value value="13" name="VFD_MODE_0_FIBERS"/>
+ <value value="14" name="VFD_MODE_1_FIBERS"/>
+ <value value="15" name="VFD_MODE_2_FIBERS"/>
+ <value value="16" name="VFD_MODE_3_FIBERS"/>
+ <value value="17" name="VFD_MODE_4_FIBERS"/>
+ <value value="18" name="VFD_BFIFO_STALL"/>
+ <value value="19" name="VFD_NUM_VERTICES_TOTAL"/>
+ <value value="20" name="VFD_PACKER_FULL"/>
+ <value value="21" name="VFD_UCHE_REQUEST_FIFO_FULL"/>
+ <value value="22" name="VFD_STARVE_CYCLES_PC"/>
+ <value value="23" name="VFD_STARVE_CYCLES_UCHE"/>
+</enum>
+
+<enum name="a4xx_vpc_perfcounter_select">
+ <value value="2" name="VPC_SP_LM_COMPONENTS"/>
+ <value value="3" name="VPC_SP0_LM_BYTES"/>
+ <value value="4" name="VPC_SP1_LM_BYTES"/>
+ <value value="5" name="VPC_SP2_LM_BYTES"/>
+ <value value="6" name="VPC_SP3_LM_BYTES"/>
+ <value value="7" name="VPC_WORKING_CYCLES"/>
+ <value value="8" name="VPC_STALL_CYCLES_LM"/>
+ <value value="9" name="VPC_STARVE_CYCLES_RAS"/>
+ <value value="10" name="VPC_STREAMOUT_CYCLES"/>
+ <value value="12" name="VPC_UCHE_TRANSACTIONS"/>
+ <value value="13" name="VPC_STALL_CYCLES_UCHE"/>
+ <value value="14" name="VPC_BUSY_CYCLES"/>
+ <value value="15" name="VPC_STARVE_CYCLES_SP"/>
+</enum>
+
+<enum name="a4xx_vsc_perfcounter_select">
+ <value value="0" name="VSC_BUSY_CYCLES"/>
+ <value value="1" name="VSC_WORKING_CYCLES"/>
+ <value value="2" name="VSC_STALL_CYCLES_UCHE"/>
+ <value value="3" name="VSC_STARVE_CYCLES_RAS"/>
+ <value value="4" name="VSC_EOT_NUM"/>
+</enum>
+
+<domain name="A4XX" width="32">
+ <!-- RB registers -->
+ <reg32 offset="0x0cc0" name="RB_GMEM_BASE_ADDR"/>
+ <reg32 offset="0x0cc7" name="RB_PERFCTR_RB_SEL_0" type="a4xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0cc8" name="RB_PERFCTR_RB_SEL_1" type="a4xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0cc9" name="RB_PERFCTR_RB_SEL_2" type="a4xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0cca" name="RB_PERFCTR_RB_SEL_3" type="a4xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0ccb" name="RB_PERFCTR_RB_SEL_4" type="a4xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0ccc" name="RB_PERFCTR_RB_SEL_5" type="a4xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0ccd" name="RB_PERFCTR_RB_SEL_6" type="a4xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0cce" name="RB_PERFCTR_RB_SEL_7" type="a4xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0ccf" name="RB_PERFCTR_CCU_SEL_0" type="a4xx_ccu_perfcounter_select"/>
+ <reg32 offset="0x0cd0" name="RB_PERFCTR_CCU_SEL_1" type="a4xx_ccu_perfcounter_select"/>
+ <reg32 offset="0x0cd1" name="RB_PERFCTR_CCU_SEL_2" type="a4xx_ccu_perfcounter_select"/>
+ <reg32 offset="0x0cd2" name="RB_PERFCTR_CCU_SEL_3" type="a4xx_ccu_perfcounter_select"/>
+ <reg32 offset="0x0ce0" name="RB_FRAME_BUFFER_DIMENSION">
+ <bitfield name="WIDTH" low="0" high="13" type="uint"/>
+ <bitfield name="HEIGHT" low="16" high="29" type="uint"/>
+ </reg32>
+ <reg32 offset="0x20cc" name="RB_CLEAR_COLOR_DW0"/>
+ <reg32 offset="0x20cd" name="RB_CLEAR_COLOR_DW1"/>
+ <reg32 offset="0x20ce" name="RB_CLEAR_COLOR_DW2"/>
+ <reg32 offset="0x20cf" name="RB_CLEAR_COLOR_DW3"/>
+ <reg32 offset="0x20a0" name="RB_MODE_CONTROL">
+ <!--
+ for non-bypass mode, these are bin width/height.. although
+ possibly bigger bitfields to hold entire width/height for
+ gmem-bypass?? Either way, it appears to need to be multiple
+ of 32..
+ -->
+ <bitfield name="WIDTH" low="0" high="5" shr="5" type="uint"/>
+ <bitfield name="HEIGHT" low="8" high="13" shr="5" type="uint"/>
+ <bitfield name="ENABLE_GMEM" pos="16" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x20a1" name="RB_RENDER_CONTROL">
+ <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
+ <!-- nearly everything has bit3 set.. -->
+ <!-- bit5 set on resolve and tiling pass -->
+ <bitfield name="DISABLE_COLOR_PIPE" pos="5" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x20a2" name="RB_MSAA_CONTROL">
+ <bitfield name="DISABLE" pos="12" type="boolean"/>
+ <bitfield name="SAMPLES" low="13" high="15" type="uint"/>
+ </reg32>
+ <reg32 offset="0x20a3" name="RB_RENDER_CONTROL2">
+ <bitfield name="COORD_MASK" low="0" high="3" type="hex"/>
+ <bitfield name="SAMPLEMASK" pos="4" type="boolean"/>
+ <bitfield name="FACENESS" pos="5" type="boolean"/>
+ <bitfield name="SAMPLEID" pos="6" type="boolean"/>
+ <bitfield name="MSAA_SAMPLES" low="7" high="9" type="uint"/>
+ <bitfield name="SAMPLEID_HR" pos="11" type="boolean"/>
+ <bitfield name="IJ_PERSP_PIXEL" pos="12" type="boolean"/>
+ <!-- the 2 below are just educated guesses -->
+ <bitfield name="IJ_PERSP_CENTROID" pos="13" type="boolean"/>
+ <bitfield name="IJ_PERSP_SAMPLE" pos="14" type="boolean"/>
+ <!-- needs to be enabled to get nopersp values,
+ perhaps other cases too? -->
+ <bitfield name="SIZE" pos="15" type="boolean"/>
+ </reg32>
+ <array offset="0x20a4" name="RB_MRT" stride="5" length="8">
+ <reg32 offset="0x0" name="CONTROL">
+ <bitfield name="READ_DEST_ENABLE" pos="3" type="boolean"/>
+ <!-- both these bits seem to get set when enabling GL_BLEND.. -->
+ <bitfield name="BLEND" pos="4" type="boolean"/>
+ <bitfield name="BLEND2" pos="5" type="boolean"/>
+ <bitfield name="ROP_ENABLE" pos="6" type="boolean"/>
+ <bitfield name="ROP_CODE" low="8" high="11" type="a3xx_rop_code"/>
+ <bitfield name="COMPONENT_ENABLE" low="24" high="27" type="hex"/>
+ </reg32>
+ <reg32 offset="0x1" name="BUF_INFO">
+ <bitfield name="COLOR_FORMAT" low="0" high="5" type="a4xx_color_fmt"/>
+ <!--
+ guestimate position of COLOR_TILE_MODE.. this works out if
+ common value is 2, like on a3xx..
+ -->
+ <bitfield name="COLOR_TILE_MODE" low="6" high="7" type="a4xx_tile_mode"/>
+ <bitfield name="DITHER_MODE" low="9" high="10" type="adreno_rb_dither_mode"/>
+ <bitfield name="COLOR_SWAP" low="11" high="12" type="a3xx_color_swap"/>
+ <bitfield name="COLOR_SRGB" pos="13" type="boolean"/>
+ <!-- note: possibly some # of lsb's aren't there: -->
+ <doc>
+ Pitch (actually, appears to be pitch in bytes, so really is a stride)
+ in GMEM, so pitch of the current tile.
+ </doc>
+ <bitfield name="COLOR_BUF_PITCH" low="14" high="31" shr="4" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2" name="BASE"/>
+ <reg32 offset="0x3" name="CONTROL3">
+ <!-- probably missing some lsb's.. and guessing upper size -->
+ <!-- pitch * cpp * msaa: -->
+ <bitfield name="STRIDE" low="3" high="25" type="uint"/>
+ </reg32>
+ <reg32 offset="0x4" name="BLEND_CONTROL">
+ <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
+ <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
+ <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
+ <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
+ <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
+ <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
+ </reg32>
+ </array>
+
+ <reg32 offset="0x20f0" name="RB_BLEND_RED">
+ <bitfield name="UINT" low="0" high="7" type="hex"/>
+ <bitfield name="SINT" low="8" high="15" type="hex"/>
+ <bitfield name="FLOAT" low="16" high="31" type="float"/>
+ </reg32>
+ <reg32 offset="0x20f1" name="RB_BLEND_RED_F32" type="float"/>
+
+ <reg32 offset="0x20f2" name="RB_BLEND_GREEN">
+ <bitfield name="UINT" low="0" high="7" type="hex"/>
+ <bitfield name="SINT" low="8" high="15" type="hex"/>
+ <bitfield name="FLOAT" low="16" high="31" type="float"/>
+ </reg32>
+ <reg32 offset="0x20f3" name="RB_BLEND_GREEN_F32" type="float"/>
+
+ <reg32 offset="0x20f4" name="RB_BLEND_BLUE">
+ <bitfield name="UINT" low="0" high="7" type="hex"/>
+ <bitfield name="SINT" low="8" high="15" type="hex"/>
+ <bitfield name="FLOAT" low="16" high="31" type="float"/>
+ </reg32>
+ <reg32 offset="0x20f5" name="RB_BLEND_BLUE_F32" type="float"/>
+
+ <reg32 offset="0x20f6" name="RB_BLEND_ALPHA">
+ <bitfield name="UINT" low="0" high="7" type="hex"/>
+ <bitfield name="SINT" low="8" high="15" type="hex"/>
+ <bitfield name="FLOAT" low="16" high="31" type="float"/>
+ </reg32>
+ <reg32 offset="0x20f7" name="RB_BLEND_ALPHA_F32" type="float"/>
+
+ <reg32 offset="0x20f8" name="RB_ALPHA_CONTROL">
+ <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
+ <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
+ <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
+ </reg32>
+ <reg32 offset="0x20f9" name="RB_FS_OUTPUT">
+ <!-- per-mrt enable bit -->
+ <bitfield name="ENABLE_BLEND" low="0" high="7"/>
+ <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
+ <!-- a guess? -->
+ <bitfield name="SAMPLE_MASK" low="16" high="31"/>
+ </reg32>
+ <reg32 offset="0x20fa" name="RB_SAMPLE_COUNT_CONTROL">
+ <bitfield name="COPY" pos="1" type="boolean"/>
+ <bitfield name="ADDR" low="2" high="31" shr="2"/>
+ </reg32>
+ <!-- always 00000000 for binning pass, else 0000000f: -->
+ <reg32 offset="0x20fb" name="RB_RENDER_COMPONENTS">
+ <bitfield name="RT0" low="0" high="3"/>
+ <bitfield name="RT1" low="4" high="7"/>
+ <bitfield name="RT2" low="8" high="11"/>
+ <bitfield name="RT3" low="12" high="15"/>
+ <bitfield name="RT4" low="16" high="19"/>
+ <bitfield name="RT5" low="20" high="23"/>
+ <bitfield name="RT6" low="24" high="27"/>
+ <bitfield name="RT7" low="28" high="31"/>
+ </reg32>
+
+ <reg32 offset="0x20fc" name="RB_COPY_CONTROL">
+ <!-- not sure # of bits -->
+ <bitfield name="MSAA_RESOLVE" low="0" high="1" type="a3xx_msaa_samples"/>
+ <bitfield name="MODE" low="4" high="6" type="adreno_rb_copy_control_mode"/>
+ <bitfield name="FASTCLEAR" low="8" high="11" type="hex"/>
+ <bitfield name="GMEM_BASE" low="14" high="31" shr="14" type="hex"/>
+ </reg32>
+ <reg32 offset="0x20fd" name="RB_COPY_DEST_BASE">
+ <bitfield name="BASE" low="5" high="31" shr="5" type="hex"/>
+ </reg32>
+ <reg32 offset="0x20fe" name="RB_COPY_DEST_PITCH">
+ <doc>actually, appears to be pitch in bytes, so really is a stride</doc>
+ <!-- not actually sure about max pitch... -->
+ <bitfield name="PITCH" low="0" high="31" shr="5" type="uint"/>
+ </reg32>
+ <reg32 offset="0x20ff" name="RB_COPY_DEST_INFO">
+ <bitfield name="FORMAT" low="2" high="7" type="a4xx_color_fmt"/>
+ <bitfield name="SWAP" low="8" high="9" type="a3xx_color_swap"/>
+ <bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/>
+ <bitfield name="COMPONENT_ENABLE" low="14" high="17" type="hex"/>
+ <bitfield name="ENDIAN" low="18" high="20" type="adreno_rb_surface_endian"/>
+ <bitfield name="TILE" low="24" high="25" type="a4xx_tile_mode"/>
+ </reg32>
+ <reg32 offset="0x2100" name="RB_FS_OUTPUT_REG">
+ <!-- bit0 set except for binning pass.. -->
+ <bitfield name="MRT" low="0" high="3" type="uint"/>
+ <bitfield name="FRAG_WRITES_Z" pos="5" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2101" name="RB_DEPTH_CONTROL">
+ <!--
+ guessing that this matches a2xx with the stencil fields
+ moved out into RB_STENCIL_CONTROL?
+ -->
+ <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
+ <bitfield name="Z_TEST_ENABLE" pos="1" type="boolean"/>
+ <bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>
+ <bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>
+ <bitfield name="Z_CLAMP_ENABLE" pos="7" type="boolean"/>
+ <bitfield name="EARLY_Z_DISABLE" pos="16" type="boolean"/>
+ <bitfield name="FORCE_FRAGZ_TO_FS" pos="17" type="boolean"/>
+ <doc>Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
+ <bitfield name="Z_READ_ENABLE" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2102" name="RB_DEPTH_CLEAR"/>
+ <reg32 offset="0x2103" name="RB_DEPTH_INFO">
+ <bitfield name="DEPTH_FORMAT" low="0" high="1" type="a4xx_depth_format"/>
+ <doc>
+ DEPTH_BASE is offset in GMEM to depth/stencil buffer, ie
+ bin_w * bin_h / 1024 (possible rounded up to multiple of
+ something?? ie. 39 becomes 40, 78 becomes 80.. 75 becomes
+ 80.. so maybe it needs to be multiple of 8??
+ </doc>
+ <bitfield name="DEPTH_BASE" low="12" high="31" shr="12" type="hex"/>
+ </reg32>
+ <reg32 offset="0x2104" name="RB_DEPTH_PITCH" shr="5" type="uint">
+ <doc>stride of depth/stencil buffer</doc>
+ </reg32>
+ <reg32 offset="0x2105" name="RB_DEPTH_PITCH2" shr="5" type="uint">
+ <doc>???</doc>
+ </reg32>
+ <reg32 offset="0x2106" name="RB_STENCIL_CONTROL">
+ <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
+ <!--
+ set for stencil operations that require read from stencil
+ buffer, but not for example for stencil clear (which does
+ not require read).. so guessing this is analogous to
+ READ_DEST_ENABLE for color buffer..
+ -->
+ <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
+ <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
+ <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
+ <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
+ <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
+ <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
+ <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
+ <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
+ <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
+ </reg32>
+ <reg32 offset="0x2107" name="RB_STENCIL_CONTROL2">
+ <!--
+ This seems to be set by blob if there is a stencil buffer
+ at all in GMEM, regardless of whether it is enabled for
+ a particular draw (ie. RB_STENCIL_CONTROL). Not really
+ sure if that is required or just a quirk of the blob
+ -->
+ <bitfield name="STENCIL_BUFFER" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2108" name="RB_STENCIL_INFO">
+ <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
+ <doc>Base address for stencil when not using interleaved depth/stencil</doc>
+ <bitfield name="STENCIL_BASE" low="12" high="31" shr="12" type="hex"/>
+ </reg32>
+ <reg32 offset="0x2109" name="RB_STENCIL_PITCH" shr="5" type="uint">
+ <doc>pitch of stencil buffer when not using interleaved depth/stencil</doc>
+ </reg32>
+
+ <reg32 offset="0x210b" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
+ <reg32 offset="0x210c" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
+ <reg32 offset="0x210d" name="RB_BIN_OFFSET" type="adreno_reg_xy"/>
+ <array offset="0x2120" name="RB_VPORT_Z_CLAMP" stride="2" length="16">
+ <reg32 offset="0x0" name="MIN"/>
+ <reg32 offset="0x1" name="MAX"/>
+ </array>
+
+ <!-- RBBM registers -->
+ <reg32 offset="0x0000" name="RBBM_HW_VERSION"/>
+ <reg32 offset="0x0002" name="RBBM_HW_CONFIGURATION"/>
+ <array offset="0x4" name="RBBM_CLOCK_CTL_TP" stride="1" length="4">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <array offset="0x8" name="RBBM_CLOCK_CTL2_TP" stride="1" length="4">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <array offset="0xc" name="RBBM_CLOCK_HYST_TP" stride="1" length="4">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <array offset="0x10" name="RBBM_CLOCK_DELAY_TP" stride="1" length="4">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <reg32 offset="0x0014" name="RBBM_CLOCK_CTL_UCHE "/>
+ <reg32 offset="0x0015" name="RBBM_CLOCK_CTL2_UCHE"/>
+ <reg32 offset="0x0016" name="RBBM_CLOCK_CTL3_UCHE"/>
+ <reg32 offset="0x0017" name="RBBM_CLOCK_CTL4_UCHE"/>
+ <reg32 offset="0x0018" name="RBBM_CLOCK_HYST_UCHE"/>
+ <reg32 offset="0x0019" name="RBBM_CLOCK_DELAY_UCHE"/>
+ <reg32 offset="0x001a" name="RBBM_CLOCK_MODE_GPC"/>
+ <reg32 offset="0x001b" name="RBBM_CLOCK_DELAY_GPC"/>
+ <reg32 offset="0x001c" name="RBBM_CLOCK_HYST_GPC"/>
+ <reg32 offset="0x001d" name="RBBM_CLOCK_CTL_TSE_RAS_RBBM"/>
+ <reg32 offset="0x001e" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
+ <reg32 offset="0x001f" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
+ <reg32 offset="0x0020" name="RBBM_CLOCK_CTL"/>
+ <reg32 offset="0x0021" name="RBBM_SP_HYST_CNT"/>
+ <reg32 offset="0x0022" name="RBBM_SW_RESET_CMD"/>
+ <reg32 offset="0x0023" name="RBBM_AHB_CTL0"/>
+ <reg32 offset="0x0024" name="RBBM_AHB_CTL1"/>
+ <reg32 offset="0x0025" name="RBBM_AHB_CMD"/>
+ <reg32 offset="0x0026" name="RBBM_RB_SUB_BLOCK_SEL_CTL"/>
+ <reg32 offset="0x0028" name="RBBM_RAM_ACC_63_32"/>
+ <reg32 offset="0x002b" name="RBBM_WAIT_IDLE_CLOCKS_CTL"/>
+ <reg32 offset="0x002f" name="RBBM_INTERFACE_HANG_INT_CTL"/>
+ <reg32 offset="0x0034" name="RBBM_INTERFACE_HANG_MASK_CTL4"/>
+ <reg32 offset="0x0036" name="RBBM_INT_CLEAR_CMD"/>
+ <reg32 offset="0x0037" name="RBBM_INT_0_MASK"/>
+ <reg32 offset="0x003e" name="RBBM_RBBM_CTL"/>
+ <reg32 offset="0x003f" name="RBBM_AHB_DEBUG_CTL"/>
+ <reg32 offset="0x0041" name="RBBM_VBIF_DEBUG_CTL"/>
+ <reg32 offset="0x0042" name="RBBM_CLOCK_CTL2"/>
+ <reg32 offset="0x0045" name="RBBM_BLOCK_SW_RESET_CMD"/>
+ <reg32 offset="0x0047" name="RBBM_RESET_CYCLES"/>
+ <reg32 offset="0x0049" name="RBBM_EXT_TRACE_BUS_CTL"/>
+ <reg32 offset="0x004a" name="RBBM_CFG_DEBBUS_SEL_A"/>
+ <reg32 offset="0x004b" name="RBBM_CFG_DEBBUS_SEL_B"/>
+ <reg32 offset="0x004c" name="RBBM_CFG_DEBBUS_SEL_C"/>
+ <reg32 offset="0x004d" name="RBBM_CFG_DEBBUS_SEL_D"/>
+ <reg32 offset="0x0098" name="RBBM_POWER_CNTL_IP">
+ <bitfield name="SW_COLLAPSE" pos="0" type="boolean"/>
+ <bitfield name="SP_TP_PWR_ON" pos="20" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x009c" name="RBBM_PERFCTR_CP_0_LO"/>
+ <reg32 offset="0x009d" name="RBBM_PERFCTR_CP_0_HI"/>
+ <reg32 offset="0x009e" name="RBBM_PERFCTR_CP_1_LO"/>
+ <reg32 offset="0x009f" name="RBBM_PERFCTR_CP_1_HI"/>
+ <reg32 offset="0x00a0" name="RBBM_PERFCTR_CP_2_LO"/>
+ <reg32 offset="0x00a1" name="RBBM_PERFCTR_CP_2_HI"/>
+ <reg32 offset="0x00a2" name="RBBM_PERFCTR_CP_3_LO"/>
+ <reg32 offset="0x00a3" name="RBBM_PERFCTR_CP_3_HI"/>
+ <reg32 offset="0x00a4" name="RBBM_PERFCTR_CP_4_LO"/>
+ <reg32 offset="0x00a5" name="RBBM_PERFCTR_CP_4_HI"/>
+ <reg32 offset="0x00a6" name="RBBM_PERFCTR_CP_5_LO"/>
+ <reg32 offset="0x00a7" name="RBBM_PERFCTR_CP_5_HI"/>
+ <reg32 offset="0x00a8" name="RBBM_PERFCTR_CP_6_LO"/>
+ <reg32 offset="0x00a9" name="RBBM_PERFCTR_CP_6_HI"/>
+ <reg32 offset="0x00aa" name="RBBM_PERFCTR_CP_7_LO"/>
+ <reg32 offset="0x00ab" name="RBBM_PERFCTR_CP_7_HI"/>
+ <reg32 offset="0x00ac" name="RBBM_PERFCTR_RBBM_0_LO"/>
+ <reg32 offset="0x00ad" name="RBBM_PERFCTR_RBBM_0_HI"/>
+ <reg32 offset="0x00ae" name="RBBM_PERFCTR_RBBM_1_LO"/>
+ <reg32 offset="0x00af" name="RBBM_PERFCTR_RBBM_1_HI"/>
+ <reg32 offset="0x00b0" name="RBBM_PERFCTR_RBBM_2_LO"/>
+ <reg32 offset="0x00b1" name="RBBM_PERFCTR_RBBM_2_HI"/>
+ <reg32 offset="0x00b2" name="RBBM_PERFCTR_RBBM_3_LO"/>
+ <reg32 offset="0x00b3" name="RBBM_PERFCTR_RBBM_3_HI"/>
+ <reg32 offset="0x00b4" name="RBBM_PERFCTR_PC_0_LO"/>
+ <reg32 offset="0x00b5" name="RBBM_PERFCTR_PC_0_HI"/>
+ <reg32 offset="0x00b6" name="RBBM_PERFCTR_PC_1_LO"/>
+ <reg32 offset="0x00b7" name="RBBM_PERFCTR_PC_1_HI"/>
+ <reg32 offset="0x00b8" name="RBBM_PERFCTR_PC_2_LO"/>
+ <reg32 offset="0x00b9" name="RBBM_PERFCTR_PC_2_HI"/>
+ <reg32 offset="0x00ba" name="RBBM_PERFCTR_PC_3_LO"/>
+ <reg32 offset="0x00bb" name="RBBM_PERFCTR_PC_3_HI"/>
+ <reg32 offset="0x00bc" name="RBBM_PERFCTR_PC_4_LO"/>
+ <reg32 offset="0x00bd" name="RBBM_PERFCTR_PC_4_HI"/>
+ <reg32 offset="0x00be" name="RBBM_PERFCTR_PC_5_LO"/>
+ <reg32 offset="0x00bf" name="RBBM_PERFCTR_PC_5_HI"/>
+ <reg32 offset="0x00c0" name="RBBM_PERFCTR_PC_6_LO"/>
+ <reg32 offset="0x00c1" name="RBBM_PERFCTR_PC_6_HI"/>
+ <reg32 offset="0x00c2" name="RBBM_PERFCTR_PC_7_LO"/>
+ <reg32 offset="0x00c3" name="RBBM_PERFCTR_PC_7_HI"/>
+ <reg32 offset="0x00c4" name="RBBM_PERFCTR_VFD_0_LO"/>
+ <reg32 offset="0x00c5" name="RBBM_PERFCTR_VFD_0_HI"/>
+ <reg32 offset="0x00c6" name="RBBM_PERFCTR_VFD_1_LO"/>
+ <reg32 offset="0x00c7" name="RBBM_PERFCTR_VFD_1_HI"/>
+ <reg32 offset="0x00c8" name="RBBM_PERFCTR_VFD_2_LO"/>
+ <reg32 offset="0x00c9" name="RBBM_PERFCTR_VFD_2_HI"/>
+ <reg32 offset="0x00ca" name="RBBM_PERFCTR_VFD_3_LO"/>
+ <reg32 offset="0x00cb" name="RBBM_PERFCTR_VFD_3_HI"/>
+ <reg32 offset="0x00cc" name="RBBM_PERFCTR_VFD_4_LO"/>
+ <reg32 offset="0x00cd" name="RBBM_PERFCTR_VFD_4_HI"/>
+ <reg32 offset="0x00ce" name="RBBM_PERFCTR_VFD_5_LO"/>
+ <reg32 offset="0x00cf" name="RBBM_PERFCTR_VFD_5_HI"/>
+ <reg32 offset="0x00d0" name="RBBM_PERFCTR_VFD_6_LO"/>
+ <reg32 offset="0x00d1" name="RBBM_PERFCTR_VFD_6_HI"/>
+ <reg32 offset="0x00d2" name="RBBM_PERFCTR_VFD_7_LO"/>
+ <reg32 offset="0x00d3" name="RBBM_PERFCTR_VFD_7_HI"/>
+ <reg32 offset="0x00d4" name="RBBM_PERFCTR_HLSQ_0_LO"/>
+ <reg32 offset="0x00d5" name="RBBM_PERFCTR_HLSQ_0_HI"/>
+ <reg32 offset="0x00d6" name="RBBM_PERFCTR_HLSQ_1_LO"/>
+ <reg32 offset="0x00d7" name="RBBM_PERFCTR_HLSQ_1_HI"/>
+ <reg32 offset="0x00d8" name="RBBM_PERFCTR_HLSQ_2_LO"/>
+ <reg32 offset="0x00d9" name="RBBM_PERFCTR_HLSQ_2_HI"/>
+ <reg32 offset="0x00da" name="RBBM_PERFCTR_HLSQ_3_LO"/>
+ <reg32 offset="0x00db" name="RBBM_PERFCTR_HLSQ_3_HI"/>
+ <reg32 offset="0x00dc" name="RBBM_PERFCTR_HLSQ_4_LO"/>
+ <reg32 offset="0x00dd" name="RBBM_PERFCTR_HLSQ_4_HI"/>
+ <reg32 offset="0x00de" name="RBBM_PERFCTR_HLSQ_5_LO"/>
+ <reg32 offset="0x00df" name="RBBM_PERFCTR_HLSQ_5_HI"/>
+ <reg32 offset="0x00e0" name="RBBM_PERFCTR_HLSQ_6_LO"/>
+ <reg32 offset="0x00e1" name="RBBM_PERFCTR_HLSQ_6_HI"/>
+ <reg32 offset="0x00e2" name="RBBM_PERFCTR_HLSQ_7_LO"/>
+ <reg32 offset="0x00e3" name="RBBM_PERFCTR_HLSQ_7_HI"/>
+ <reg32 offset="0x00e4" name="RBBM_PERFCTR_VPC_0_LO"/>
+ <reg32 offset="0x00e5" name="RBBM_PERFCTR_VPC_0_HI"/>
+ <reg32 offset="0x00e6" name="RBBM_PERFCTR_VPC_1_LO"/>
+ <reg32 offset="0x00e7" name="RBBM_PERFCTR_VPC_1_HI"/>
+ <reg32 offset="0x00e8" name="RBBM_PERFCTR_VPC_2_LO"/>
+ <reg32 offset="0x00e9" name="RBBM_PERFCTR_VPC_2_HI"/>
+ <reg32 offset="0x00ea" name="RBBM_PERFCTR_VPC_3_LO"/>
+ <reg32 offset="0x00eb" name="RBBM_PERFCTR_VPC_3_HI"/>
+ <reg32 offset="0x00ec" name="RBBM_PERFCTR_CCU_0_LO"/>
+ <reg32 offset="0x00ed" name="RBBM_PERFCTR_CCU_0_HI"/>
+ <reg32 offset="0x00ee" name="RBBM_PERFCTR_CCU_1_LO"/>
+ <reg32 offset="0x00ef" name="RBBM_PERFCTR_CCU_1_HI"/>
+ <reg32 offset="0x00f0" name="RBBM_PERFCTR_CCU_2_LO"/>
+ <reg32 offset="0x00f1" name="RBBM_PERFCTR_CCU_2_HI"/>
+ <reg32 offset="0x00f2" name="RBBM_PERFCTR_CCU_3_LO"/>
+ <reg32 offset="0x00f3" name="RBBM_PERFCTR_CCU_3_HI"/>
+ <reg32 offset="0x00f4" name="RBBM_PERFCTR_TSE_0_LO"/>
+ <reg32 offset="0x00f5" name="RBBM_PERFCTR_TSE_0_HI"/>
+ <reg32 offset="0x00f6" name="RBBM_PERFCTR_TSE_1_LO"/>
+ <reg32 offset="0x00f7" name="RBBM_PERFCTR_TSE_1_HI"/>
+ <reg32 offset="0x00f8" name="RBBM_PERFCTR_TSE_2_LO"/>
+ <reg32 offset="0x00f9" name="RBBM_PERFCTR_TSE_2_HI"/>
+ <reg32 offset="0x00fa" name="RBBM_PERFCTR_TSE_3_LO"/>
+ <reg32 offset="0x00fb" name="RBBM_PERFCTR_TSE_3_HI"/>
+ <reg32 offset="0x00fc" name="RBBM_PERFCTR_RAS_0_LO"/>
+ <reg32 offset="0x00fd" name="RBBM_PERFCTR_RAS_0_HI"/>
+ <reg32 offset="0x00fe" name="RBBM_PERFCTR_RAS_1_LO"/>
+ <reg32 offset="0x00ff" name="RBBM_PERFCTR_RAS_1_HI"/>
+ <reg32 offset="0x0100" name="RBBM_PERFCTR_RAS_2_LO"/>
+ <reg32 offset="0x0101" name="RBBM_PERFCTR_RAS_2_HI"/>
+ <reg32 offset="0x0102" name="RBBM_PERFCTR_RAS_3_LO"/>
+ <reg32 offset="0x0103" name="RBBM_PERFCTR_RAS_3_HI"/>
+ <reg32 offset="0x0104" name="RBBM_PERFCTR_UCHE_0_LO"/>
+ <reg32 offset="0x0105" name="RBBM_PERFCTR_UCHE_0_HI"/>
+ <reg32 offset="0x0106" name="RBBM_PERFCTR_UCHE_1_LO"/>
+ <reg32 offset="0x0107" name="RBBM_PERFCTR_UCHE_1_HI"/>
+ <reg32 offset="0x0108" name="RBBM_PERFCTR_UCHE_2_LO"/>
+ <reg32 offset="0x0109" name="RBBM_PERFCTR_UCHE_2_HI"/>
+ <reg32 offset="0x010a" name="RBBM_PERFCTR_UCHE_3_LO"/>
+ <reg32 offset="0x010b" name="RBBM_PERFCTR_UCHE_3_HI"/>
+ <reg32 offset="0x010c" name="RBBM_PERFCTR_UCHE_4_LO"/>
+ <reg32 offset="0x010d" name="RBBM_PERFCTR_UCHE_4_HI"/>
+ <reg32 offset="0x010e" name="RBBM_PERFCTR_UCHE_5_LO"/>
+ <reg32 offset="0x010f" name="RBBM_PERFCTR_UCHE_5_HI"/>
+ <reg32 offset="0x0110" name="RBBM_PERFCTR_UCHE_6_LO"/>
+ <reg32 offset="0x0111" name="RBBM_PERFCTR_UCHE_6_HI"/>
+ <reg32 offset="0x0112" name="RBBM_PERFCTR_UCHE_7_LO"/>
+ <reg32 offset="0x0113" name="RBBM_PERFCTR_UCHE_7_HI"/>
+ <reg32 offset="0x0114" name="RBBM_PERFCTR_TP_0_LO"/>
+ <reg32 offset="0x0115" name="RBBM_PERFCTR_TP_0_HI"/>
+ <reg32 offset="0x0116" name="RBBM_PERFCTR_TP_1_LO"/>
+ <reg32 offset="0x0117" name="RBBM_PERFCTR_TP_1_HI"/>
+ <reg32 offset="0x0118" name="RBBM_PERFCTR_TP_2_LO"/>
+ <reg32 offset="0x0119" name="RBBM_PERFCTR_TP_2_HI"/>
+ <reg32 offset="0x011a" name="RBBM_PERFCTR_TP_3_LO"/>
+ <reg32 offset="0x011b" name="RBBM_PERFCTR_TP_3_HI"/>
+ <reg32 offset="0x011c" name="RBBM_PERFCTR_TP_4_LO"/>
+ <reg32 offset="0x011d" name="RBBM_PERFCTR_TP_4_HI"/>
+ <reg32 offset="0x011e" name="RBBM_PERFCTR_TP_5_LO"/>
+ <reg32 offset="0x011f" name="RBBM_PERFCTR_TP_5_HI"/>
+ <reg32 offset="0x0120" name="RBBM_PERFCTR_TP_6_LO"/>
+ <reg32 offset="0x0121" name="RBBM_PERFCTR_TP_6_HI"/>
+ <reg32 offset="0x0122" name="RBBM_PERFCTR_TP_7_LO"/>
+ <reg32 offset="0x0123" name="RBBM_PERFCTR_TP_7_HI"/>
+ <reg32 offset="0x0124" name="RBBM_PERFCTR_SP_0_LO"/>
+ <reg32 offset="0x0125" name="RBBM_PERFCTR_SP_0_HI"/>
+ <reg32 offset="0x0126" name="RBBM_PERFCTR_SP_1_LO"/>
+ <reg32 offset="0x0127" name="RBBM_PERFCTR_SP_1_HI"/>
+ <reg32 offset="0x0128" name="RBBM_PERFCTR_SP_2_LO"/>
+ <reg32 offset="0x0129" name="RBBM_PERFCTR_SP_2_HI"/>
+ <reg32 offset="0x012a" name="RBBM_PERFCTR_SP_3_LO"/>
+ <reg32 offset="0x012b" name="RBBM_PERFCTR_SP_3_HI"/>
+ <reg32 offset="0x012c" name="RBBM_PERFCTR_SP_4_LO"/>
+ <reg32 offset="0x012d" name="RBBM_PERFCTR_SP_4_HI"/>
+ <reg32 offset="0x012e" name="RBBM_PERFCTR_SP_5_LO"/>
+ <reg32 offset="0x012f" name="RBBM_PERFCTR_SP_5_HI"/>
+ <reg32 offset="0x0130" name="RBBM_PERFCTR_SP_6_LO"/>
+ <reg32 offset="0x0131" name="RBBM_PERFCTR_SP_6_HI"/>
+ <reg32 offset="0x0132" name="RBBM_PERFCTR_SP_7_LO"/>
+ <reg32 offset="0x0133" name="RBBM_PERFCTR_SP_7_HI"/>
+ <reg32 offset="0x0134" name="RBBM_PERFCTR_SP_8_LO"/>
+ <reg32 offset="0x0135" name="RBBM_PERFCTR_SP_8_HI"/>
+ <reg32 offset="0x0136" name="RBBM_PERFCTR_SP_9_LO"/>
+ <reg32 offset="0x0137" name="RBBM_PERFCTR_SP_9_HI"/>
+ <reg32 offset="0x0138" name="RBBM_PERFCTR_SP_10_LO"/>
+ <reg32 offset="0x0139" name="RBBM_PERFCTR_SP_10_HI"/>
+ <reg32 offset="0x013a" name="RBBM_PERFCTR_SP_11_LO"/>
+ <reg32 offset="0x013b" name="RBBM_PERFCTR_SP_11_HI"/>
+ <reg32 offset="0x013c" name="RBBM_PERFCTR_RB_0_LO"/>
+ <reg32 offset="0x013d" name="RBBM_PERFCTR_RB_0_HI"/>
+ <reg32 offset="0x013e" name="RBBM_PERFCTR_RB_1_LO"/>
+ <reg32 offset="0x013f" name="RBBM_PERFCTR_RB_1_HI"/>
+ <reg32 offset="0x0140" name="RBBM_PERFCTR_RB_2_LO"/>
+ <reg32 offset="0x0141" name="RBBM_PERFCTR_RB_2_HI"/>
+ <reg32 offset="0x0142" name="RBBM_PERFCTR_RB_3_LO"/>
+ <reg32 offset="0x0143" name="RBBM_PERFCTR_RB_3_HI"/>
+ <reg32 offset="0x0144" name="RBBM_PERFCTR_RB_4_LO"/>
+ <reg32 offset="0x0145" name="RBBM_PERFCTR_RB_4_HI"/>
+ <reg32 offset="0x0146" name="RBBM_PERFCTR_RB_5_LO"/>
+ <reg32 offset="0x0147" name="RBBM_PERFCTR_RB_5_HI"/>
+ <reg32 offset="0x0148" name="RBBM_PERFCTR_RB_6_LO"/>
+ <reg32 offset="0x0149" name="RBBM_PERFCTR_RB_6_HI"/>
+ <reg32 offset="0x014a" name="RBBM_PERFCTR_RB_7_LO"/>
+ <reg32 offset="0x014b" name="RBBM_PERFCTR_RB_7_HI"/>
+ <reg32 offset="0x014c" name="RBBM_PERFCTR_VSC_0_LO"/>
+ <reg32 offset="0x014d" name="RBBM_PERFCTR_VSC_0_HI"/>
+ <reg32 offset="0x014e" name="RBBM_PERFCTR_VSC_1_LO"/>
+ <reg32 offset="0x014f" name="RBBM_PERFCTR_VSC_1_HI"/>
+ <reg32 offset="0x0166" name="RBBM_PERFCTR_PWR_0_LO"/>
+ <reg32 offset="0x0167" name="RBBM_PERFCTR_PWR_0_HI"/>
+ <reg32 offset="0x0168" name="RBBM_PERFCTR_PWR_1_LO"/>
+ <reg32 offset="0x0169" name="RBBM_PERFCTR_PWR_1_HI"/>
+ <reg32 offset="0x016e" name="RBBM_ALWAYSON_COUNTER_LO"/>
+ <reg32 offset="0x016f" name="RBBM_ALWAYSON_COUNTER_HI"/>
+ <array offset="0x0068" name="RBBM_CLOCK_CTL_SP" stride="1" length="4">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <array offset="0x006c" name="RBBM_CLOCK_CTL2_SP" stride="1" length="4">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <array offset="0x0070" name="RBBM_CLOCK_HYST_SP" stride="1" length="4">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <array offset="0x0074" name="RBBM_CLOCK_DELAY_SP" stride="1" length="4">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <array offset="0x0078" name="RBBM_CLOCK_CTL_RB" stride="1" length="4">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <array offset="0x007c" name="RBBM_CLOCK_CTL2_RB" stride="1" length="4">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <array offset="0x0082" name="RBBM_CLOCK_CTL_MARB_CCU" stride="1" length="4">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <array offset="0x0086" name="RBBM_CLOCK_HYST_RB_MARB_CCU" stride="1" length="4">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <reg32 offset="0x0080" name="RBBM_CLOCK_HYST_COM_DCOM"/>
+ <reg32 offset="0x0081" name="RBBM_CLOCK_CTL_COM_DCOM"/>
+ <reg32 offset="0x008a" name="RBBM_CLOCK_CTL_HLSQ"/>
+ <reg32 offset="0x008b" name="RBBM_CLOCK_HYST_HLSQ"/>
+ <reg32 offset="0x008c" name="RBBM_CLOCK_DELAY_HLSQ"/>
+ <bitset name="A4XX_CGC_HLSQ">
+ <bitfield name="EARLY_CYC" low="20" high="22" type="uint"/>
+ </bitset>
+ <reg32 offset="0x008d" name="RBBM_CLOCK_DELAY_COM_DCOM"/>
+ <array offset="0x008e" name="RBBM_CLOCK_DELAY_RB_MARB_CCU_L1" stride="1" length="4">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <bitset name="A4XX_INT0">
+ <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
+ <bitfield name="RBBM_AHB_ERROR" pos="1" type="boolean"/>
+ <bitfield name="RBBM_REG_TIMEOUT" pos="2" type="boolean"/>
+ <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3" type="boolean"/>
+ <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4" type="boolean"/>
+ <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="5" type="boolean"/>
+ <bitfield name="VFD_ERROR" pos="6" type="boolean"/>
+ <bitfield name="CP_SW_INT" pos="7" type="boolean"/>
+ <bitfield name="CP_T0_PACKET_IN_IB" pos="8" type="boolean"/>
+ <bitfield name="CP_OPCODE_ERROR" pos="9" type="boolean"/>
+ <bitfield name="CP_RESERVED_BIT_ERROR" pos="10" type="boolean"/>
+ <bitfield name="CP_HW_FAULT" pos="11" type="boolean"/>
+ <bitfield name="CP_DMA" pos="12" type="boolean"/>
+ <bitfield name="CP_IB2_INT" pos="13" type="boolean"/>
+ <bitfield name="CP_IB1_INT" pos="14" type="boolean"/>
+ <bitfield name="CP_RB_INT" pos="15" type="boolean"/>
+ <bitfield name="CP_REG_PROTECT_FAULT" pos="16" type="boolean"/>
+ <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
+ <bitfield name="CP_VS_DONE_TS" pos="18" type="boolean"/>
+ <bitfield name="CP_PS_DONE_TS" pos="19" type="boolean"/>
+ <bitfield name="CACHE_FLUSH_TS" pos="20" type="boolean"/>
+ <bitfield name="CP_AHB_ERROR_HALT" pos="21" type="boolean"/>
+ <bitfield name="MISC_HANG_DETECT" pos="24" type="boolean"/>
+ <bitfield name="UCHE_OOB_ACCESS" pos="25" type="boolean"/>
+ </bitset>
+
+ <reg32 offset="0x0099" name="RBBM_SP_REGFILE_SLEEP_CNTL_0"/>
+ <reg32 offset="0x009a" name="RBBM_SP_REGFILE_SLEEP_CNTL_1"/>
+ <reg32 offset="0x0170" name="RBBM_PERFCTR_CTL"/>
+ <reg32 offset="0x0171" name="RBBM_PERFCTR_LOAD_CMD0"/>
+ <reg32 offset="0x0172" name="RBBM_PERFCTR_LOAD_CMD1"/>
+ <reg32 offset="0x0173" name="RBBM_PERFCTR_LOAD_CMD2"/>
+ <reg32 offset="0x0174" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
+ <reg32 offset="0x0175" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
+ <reg32 offset="0x0176" name="RBBM_PERFCTR_RBBM_SEL_0" type="a4xx_rbbm_perfcounter_select"/>
+ <reg32 offset="0x0177" name="RBBM_PERFCTR_RBBM_SEL_1" type="a4xx_rbbm_perfcounter_select"/>
+ <reg32 offset="0x0178" name="RBBM_PERFCTR_RBBM_SEL_2" type="a4xx_rbbm_perfcounter_select"/>
+ <reg32 offset="0x0179" name="RBBM_PERFCTR_RBBM_SEL_3" type="a4xx_rbbm_perfcounter_select"/>
+ <reg32 offset="0x017a" name="RBBM_GPU_BUSY_MASKED"/>
+ <reg32 offset="0x017d" name="RBBM_INT_0_STATUS"/>
+ <reg32 offset="0x0182" name="RBBM_CLOCK_STATUS"/>
+ <reg32 offset="0x0189" name="RBBM_AHB_STATUS"/>
+ <reg32 offset="0x018c" name="RBBM_AHB_ME_SPLIT_STATUS"/>
+ <reg32 offset="0x018d" name="RBBM_AHB_PFP_SPLIT_STATUS"/>
+ <reg32 offset="0x018f" name="RBBM_AHB_ERROR_STATUS"/>
+ <reg32 offset="0x0191" name="RBBM_STATUS">
+ <bitfield name="HI_BUSY" pos="0" type="boolean"/>
+ <bitfield name="CP_ME_BUSY" pos="1" type="boolean"/>
+ <bitfield name="CP_PFP_BUSY" pos="2" type="boolean"/>
+ <bitfield name="CP_NRT_BUSY" pos="14" type="boolean"/>
+ <bitfield name="VBIF_BUSY" pos="15" type="boolean"/>
+ <bitfield name="TSE_BUSY" pos="16" type="boolean"/>
+ <bitfield name="RAS_BUSY" pos="17" type="boolean"/>
+ <bitfield name="RB_BUSY" pos="18" type="boolean"/>
+ <bitfield name="PC_DCALL_BUSY" pos="19" type="boolean"/>
+ <bitfield name="PC_VSD_BUSY" pos="20" type="boolean"/>
+ <bitfield name="VFD_BUSY" pos="21" type="boolean"/>
+ <bitfield name="VPC_BUSY" pos="22" type="boolean"/>
+ <bitfield name="UCHE_BUSY" pos="23" type="boolean"/>
+ <bitfield name="SP_BUSY" pos="24" type="boolean"/>
+ <bitfield name="TPL1_BUSY" pos="25" type="boolean"/>
+ <bitfield name="MARB_BUSY" pos="26" type="boolean"/>
+ <bitfield name="VSC_BUSY" pos="27" type="boolean"/>
+ <bitfield name="ARB_BUSY" pos="28" type="boolean"/>
+ <bitfield name="HLSQ_BUSY" pos="29" type="boolean"/>
+ <bitfield name="GPU_BUSY_NOHC" pos="30" type="boolean"/>
+ <bitfield name="GPU_BUSY" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x019f" name="RBBM_INTERFACE_RRDY_STATUS5"/>
+ <reg32 offset="0x01b0" name="RBBM_POWER_STATUS">
+ <bitfield name="SP_TP_PWR_ON" pos="20" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x01b8" name="RBBM_WAIT_IDLE_CLOCKS_CTL2"/>
+
+ <!-- CP registers -->
+ <reg32 offset="0x0228" name="CP_SCRATCH_UMASK"/>
+ <reg32 offset="0x0229" name="CP_SCRATCH_ADDR"/>
+ <reg32 offset="0x0200" name="CP_RB_BASE"/>
+ <reg32 offset="0x0201" name="CP_RB_CNTL"/>
+ <reg32 offset="0x0205" name="CP_RB_WPTR"/>
+ <reg32 offset="0x0203" name="CP_RB_RPTR_ADDR"/>
+ <reg32 offset="0x0204" name="CP_RB_RPTR"/>
+ <reg32 offset="0x0206" name="CP_IB1_BASE"/>
+ <reg32 offset="0x0207" name="CP_IB1_BUFSZ"/>
+ <reg32 offset="0x0208" name="CP_IB2_BASE"/>
+ <reg32 offset="0x0209" name="CP_IB2_BUFSZ"/>
+ <reg32 offset="0x020c" name="CP_ME_NRT_ADDR"/>
+ <reg32 offset="0x020d" name="CP_ME_NRT_DATA"/>
+ <reg32 offset="0x0217" name="CP_ME_RB_DONE_DATA"/>
+ <reg32 offset="0x0219" name="CP_QUEUE_THRESH2"/>
+ <reg32 offset="0x021b" name="CP_MERCIU_SIZE"/>
+ <reg32 offset="0x021c" name="CP_ROQ_ADDR"/>
+ <reg32 offset="0x021d" name="CP_ROQ_DATA"/>
+ <reg32 offset="0x021e" name="CP_MEQ_ADDR"/>
+ <reg32 offset="0x021f" name="CP_MEQ_DATA"/>
+ <reg32 offset="0x0220" name="CP_MERCIU_ADDR"/>
+ <reg32 offset="0x0221" name="CP_MERCIU_DATA"/>
+ <reg32 offset="0x0222" name="CP_MERCIU_DATA2"/>
+ <reg32 offset="0x0223" name="CP_PFP_UCODE_ADDR"/>
+ <reg32 offset="0x0224" name="CP_PFP_UCODE_DATA"/>
+ <reg32 offset="0x0225" name="CP_ME_RAM_WADDR"/>
+ <reg32 offset="0x0226" name="CP_ME_RAM_RADDR"/>
+ <reg32 offset="0x0227" name="CP_ME_RAM_DATA"/>
+ <reg32 offset="0x022a" name="CP_PREEMPT"/>
+ <reg32 offset="0x022c" name="CP_CNTL"/>
+ <reg32 offset="0x022d" name="CP_ME_CNTL"/>
+ <reg32 offset="0x022e" name="CP_DEBUG"/>
+ <reg32 offset="0x0231" name="CP_DEBUG_ECO_CONTROL"/>
+ <reg32 offset="0x0232" name="CP_DRAW_STATE_ADDR"/>
+ <array offset="0x0240" name="CP_PROTECT" stride="1" length="16">
+ <reg32 offset="0x0" name="REG" type="adreno_cp_protect"/>
+ </array>
+ <reg32 offset="0x0250" name="CP_PROTECT_CTRL"/>
+ <reg32 offset="0x04c0" name="CP_ST_BASE"/>
+ <reg32 offset="0x04ce" name="CP_STQ_AVAIL"/>
+ <reg32 offset="0x04d0" name="CP_MERCIU_STAT"/>
+ <reg32 offset="0x04d2" name="CP_WFI_PEND_CTR"/>
+ <reg32 offset="0x04d8" name="CP_HW_FAULT"/>
+ <reg32 offset="0x04da" name="CP_PROTECT_STATUS"/>
+ <reg32 offset="0x04dd" name="CP_EVENTS_IN_FLIGHT"/>
+ <reg32 offset="0x0500" name="CP_PERFCTR_CP_SEL_0" type="a4xx_cp_perfcounter_select"/>
+ <reg32 offset="0x0501" name="CP_PERFCTR_CP_SEL_1" type="a4xx_cp_perfcounter_select"/>
+ <reg32 offset="0x0502" name="CP_PERFCTR_CP_SEL_2" type="a4xx_cp_perfcounter_select"/>
+ <reg32 offset="0x0503" name="CP_PERFCTR_CP_SEL_3" type="a4xx_cp_perfcounter_select"/>
+ <reg32 offset="0x0504" name="CP_PERFCTR_CP_SEL_4" type="a4xx_cp_perfcounter_select"/>
+ <reg32 offset="0x0505" name="CP_PERFCTR_CP_SEL_5" type="a4xx_cp_perfcounter_select"/>
+ <reg32 offset="0x0506" name="CP_PERFCTR_CP_SEL_6" type="a4xx_cp_perfcounter_select"/>
+ <reg32 offset="0x0507" name="CP_PERFCTR_CP_SEL_7" type="a4xx_cp_perfcounter_select"/>
+ <reg32 offset="0x050b" name="CP_PERFCOMBINER_SELECT"/>
+ <array offset="0x0578" name="CP_SCRATCH" stride="1" length="23">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+
+
+ <!-- SP registers -->
+ <reg32 offset="0x0ec0" name="SP_VS_STATUS"/>
+ <reg32 offset="0x0ec3" name="SP_MODE_CONTROL"/>
+
+ <reg32 offset="0x0ec4" name="SP_PERFCTR_SP_SEL_0" type="a4xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ec5" name="SP_PERFCTR_SP_SEL_1" type="a4xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ec6" name="SP_PERFCTR_SP_SEL_2" type="a4xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ec7" name="SP_PERFCTR_SP_SEL_3" type="a4xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ec8" name="SP_PERFCTR_SP_SEL_4" type="a4xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ec9" name="SP_PERFCTR_SP_SEL_5" type="a4xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0eca" name="SP_PERFCTR_SP_SEL_6" type="a4xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ecb" name="SP_PERFCTR_SP_SEL_7" type="a4xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ecc" name="SP_PERFCTR_SP_SEL_8" type="a4xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ecd" name="SP_PERFCTR_SP_SEL_9" type="a4xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ece" name="SP_PERFCTR_SP_SEL_10" type="a4xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ecf" name="SP_PERFCTR_SP_SEL_11" type="a4xx_sp_perfcounter_select"/>
+
+ <reg32 offset="0x22c0" name="SP_SP_CTRL_REG">
+ <bitfield name="BINNING_PASS" pos="19" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x22c1" name="SP_INSTR_CACHE_CTRL">
+ <!-- set when VS in buffer mode: -->
+ <bitfield name="VS_BUFFER" pos="7" type="boolean"/>
+ <!-- set when FS in buffer mode: -->
+ <bitfield name="FS_BUFFER" pos="8" type="boolean"/>
+ <!-- set when both VS or FS in buffer mode: -->
+ <bitfield name="INSTR_BUFFER" pos="10" type="boolean"/>
+ <!-- TODO other bits probably matter when other stages active? -->
+ </reg32>
+
+ <bitset name="a4xx_sp_vs_fs_ctrl_reg0" inline="yes">
+ <!--
+ NOTE that SP_{VS,FS}_CTRL_REG1 are different, but so far REG0
+ appears to be the same..
+ -->
+ <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
+ <!-- VARYING bit only for FS.. think it controls emitting (ei) flag? -->
+ <bitfield name="VARYING" pos="1" type="boolean"/>
+ <!-- maybe CACHEINVALID is two bits?? -->
+ <bitfield name="CACHEINVALID" pos="2" type="boolean"/>
+ <doc>
+ The full/half register footprint is in units of four components,
+ so if r0.x is used, that counts as all of r0.[xyzw] as used.
+ There are separate full/half register footprint values as the
+ full and half registers are independent (not overlapping).
+ Presumably the thread scheduler hardware allocates the full/half
+ register names from the actual physical register file and
+ handles the register renaming.
+ </doc>
+ <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
+ <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
+ <!-- maybe INOUTREGOVERLAP is a bitflag? -->
+ <bitfield name="INOUTREGOVERLAP" low="18" high="19" type="uint"/>
+ <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
+ <bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/>
+ <bitfield name="PIXLODENABLE" pos="22" type="boolean"/>
+ </bitset>
+
+ <reg32 offset="0x22c4" name="SP_VS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/>
+ <reg32 offset="0x22c5" name="SP_VS_CTRL_REG1">
+ <bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/>
+ <bitfield name="INITIALOUTSTANDING" low="24" high="30" type="uint"/>
+ </reg32>
+ <reg32 offset="0x22c6" name="SP_VS_PARAM_REG">
+ <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="PSIZEREGID" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="TOTALVSOUTVAR" low="20" high="31" type="uint"/>
+ </reg32>
+ <array offset="0x22c7" name="SP_VS_OUT" stride="1" length="16">
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/>
+ <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
+ <bitfield name="B_REGID" low="16" high="24" type="a3xx_regid"/>
+ <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
+ </reg32>
+ </array>
+ <array offset="0x22d8" name="SP_VS_VPC_DST" stride="1" length="8">
+ <reg32 offset="0x0" name="REG">
+ <doc>
+ These seem to be offsets for storage of the varyings.
+ Always seems to start from 8, possibly loc 0 and 4
+ are for gl_Position and gl_PointSize?
+ </doc>
+ <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
+ <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
+ <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
+ <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
+ </reg32>
+ </array>
+
+ <reg32 offset="0x22e0" name="SP_VS_OBJ_OFFSET_REG">
+ <!-- always 00000000: -->
+ <doc>
+ From register spec:
+ SP_FS_OBJ_OFFSET_REG.CONSTOBJECTSTARTOFFSET [16:24]: Constant object
+ start offset in on chip RAM,
+ 128bit aligned
+ </doc>
+ <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
+ <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x22e1" name="SP_VS_OBJ_START"/>
+ <reg32 offset="0x22e2" name="SP_VS_PVT_MEM_PARAM"/>
+ <reg32 offset="0x22e3" name="SP_VS_PVT_MEM_ADDR"/>
+ <reg32 offset="0x22e5" name="SP_VS_LENGTH_REG" type="uint"/>
+ <reg32 offset="0x22e8" name="SP_FS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/>
+ <reg32 offset="0x22e9" name="SP_FS_CTRL_REG1">
+ <bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/>
+ <bitfield name="FACENESS" pos="19" type="boolean"/>
+ <bitfield name="VARYING" pos="20" type="boolean"/>
+ <bitfield name="FRAGCOORD" pos="21" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x22ea" name="SP_FS_OBJ_OFFSET_REG">
+ <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
+ <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x22eb" name="SP_FS_OBJ_START"/>
+ <reg32 offset="0x22ec" name="SP_FS_PVT_MEM_PARAM"/>
+ <reg32 offset="0x22ed" name="SP_FS_PVT_MEM_ADDR"/>
+ <reg32 offset="0x22ef" name="SP_FS_LENGTH_REG" type="uint"/>
+ <reg32 offset="0x22f0" name="SP_FS_OUTPUT_REG">
+ <bitfield name="MRT" low="0" high="3" type="uint"/>
+ <bitfield name="DEPTH_ENABLE" pos="7" type="boolean"/>
+ <!-- TODO double check.. for now assume same as a3xx -->
+ <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="SAMPLEMASK_REGID" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <array offset="0x22f1" name="SP_FS_MRT" stride="1" length="8">
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
+ <bitfield name="COLOR_SINT" pos="10" type="boolean"/>
+ <bitfield name="COLOR_UINT" pos="11" type="boolean"/>
+ <bitfield name="MRTFORMAT" low="12" high="17" type="a4xx_color_fmt"/>
+ <bitfield name="COLOR_SRGB" pos="18" type="boolean"/>
+ </reg32>
+ </array>
+ <reg32 offset="0x2300" name="SP_CS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/>
+ <reg32 offset="0x2301" name="SP_CS_OBJ_OFFSET_REG"/>
+ <reg32 offset="0x2302" name="SP_CS_OBJ_START"/>
+ <reg32 offset="0x2303" name="SP_CS_PVT_MEM_PARAM"/>
+ <reg32 offset="0x2304" name="SP_CS_PVT_MEM_ADDR"/>
+ <reg32 offset="0x2305" name="SP_CS_PVT_MEM_SIZE"/>
+ <reg32 offset="0x2306" name="SP_CS_LENGTH_REG" type="uint"/>
+ <reg32 offset="0x230d" name="SP_HS_OBJ_OFFSET_REG">
+ <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
+ <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x230e" name="SP_HS_OBJ_START"/>
+ <reg32 offset="0x230f" name="SP_HS_PVT_MEM_PARAM"/>
+ <reg32 offset="0x2310" name="SP_HS_PVT_MEM_ADDR"/>
+ <reg32 offset="0x2312" name="SP_HS_LENGTH_REG" type="uint"/>
+
+ <reg32 offset="0x231a" name="SP_DS_PARAM_REG">
+ <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="TOTALGSOUTVAR" low="20" high="31" type="uint"/>
+ </reg32>
+ <array offset="0x231b" name="SP_DS_OUT" stride="1" length="16">
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/>
+ <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
+ <bitfield name="B_REGID" low="16" high="24" type="a3xx_regid"/>
+ <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
+ </reg32>
+ </array>
+ <array offset="0x232c" name="SP_DS_VPC_DST" stride="1" length="8">
+ <reg32 offset="0x0" name="REG">
+ <doc>
+ These seem to be offsets for storage of the varyings.
+ Always seems to start from 8, possibly loc 0 and 4
+ are for gl_Position and gl_PointSize?
+ </doc>
+ <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
+ <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
+ <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
+ <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
+ </reg32>
+ </array>
+ <reg32 offset="0x2334" name="SP_DS_OBJ_OFFSET_REG">
+ <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
+ <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2335" name="SP_DS_OBJ_START"/>
+ <reg32 offset="0x2336" name="SP_DS_PVT_MEM_PARAM"/>
+ <reg32 offset="0x2337" name="SP_DS_PVT_MEM_ADDR"/>
+ <reg32 offset="0x2339" name="SP_DS_LENGTH_REG" type="uint"/>
+
+ <reg32 offset="0x2341" name="SP_GS_PARAM_REG">
+ <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="PRIMREGID" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="TOTALGSOUTVAR" low="20" high="31" type="uint"/>
+ </reg32>
+ <array offset="0x2342" name="SP_GS_OUT" stride="1" length="16">
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/>
+ <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
+ <bitfield name="B_REGID" low="16" high="24" type="a3xx_regid"/>
+ <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
+ </reg32>
+ </array>
+ <array offset="0x2353" name="SP_GS_VPC_DST" stride="1" length="8">
+ <reg32 offset="0x0" name="REG">
+ <doc>
+ These seem to be offsets for storage of the varyings.
+ Always seems to start from 8, possibly loc 0 and 4
+ are for gl_Position and gl_PointSize?
+ </doc>
+ <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
+ <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
+ <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
+ <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
+ </reg32>
+ </array>
+ <reg32 offset="0x235b" name="SP_GS_OBJ_OFFSET_REG">
+ <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
+ <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x235c" name="SP_GS_OBJ_START"/>
+ <reg32 offset="0x235d" name="SP_GS_PVT_MEM_PARAM"/>
+ <reg32 offset="0x235e" name="SP_GS_PVT_MEM_ADDR"/>
+ <reg32 offset="0x2360" name="SP_GS_LENGTH_REG" type="uint"/>
+
+ <!-- VPC registers -->
+ <reg32 offset="0x0e60" name="VPC_DEBUG_RAM_SEL"/>
+ <reg32 offset="0x0e61" name="VPC_DEBUG_RAM_READ"/>
+ <reg32 offset="0x0e64" name="VPC_DEBUG_ECO_CONTROL"/>
+ <reg32 offset="0x0e65" name="VPC_PERFCTR_VPC_SEL_0" type="a4xx_vpc_perfcounter_select"/>
+ <reg32 offset="0x0e66" name="VPC_PERFCTR_VPC_SEL_1" type="a4xx_vpc_perfcounter_select"/>
+ <reg32 offset="0x0e67" name="VPC_PERFCTR_VPC_SEL_2" type="a4xx_vpc_perfcounter_select"/>
+ <reg32 offset="0x0e68" name="VPC_PERFCTR_VPC_SEL_3" type="a4xx_vpc_perfcounter_select"/>
+ <reg32 offset="0x2140" name="VPC_ATTR">
+ <bitfield name="TOTALATTR" low="0" high="8" type="uint"/>
+ <!-- PSIZE bit set if gl_PointSize written: -->
+ <bitfield name="PSIZE" pos="9" type="boolean"/>
+ <bitfield name="THRDASSIGN" low="12" high="13" type="uint"/>
+ <bitfield name="ENABLE" pos="25" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2141" name="VPC_PACK">
+ <bitfield name="NUMBYPASSVAR" low="0" high="7" type="uint"/>
+ <bitfield name="NUMFPNONPOSVAR" low="8" high="15" type="uint"/>
+ <bitfield name="NUMNONPOSVSVAR" low="16" high="23" type="uint"/>
+ </reg32>
+ <array offset="0x2142" name="VPC_VARYING_INTERP" stride="1" length="8">
+ <reg32 offset="0x0" name="MODE"/>
+ </array>
+ <array offset="0x214a" name="VPC_VARYING_PS_REPL" stride="1" length="8">
+ <reg32 offset="0x0" name="MODE"/>
+ </array>
+
+ <reg32 offset="0x216e" name="VPC_SO_FLUSH_WADDR_3"/>
+
+ <!-- VSC registers -->
+ <reg32 offset="0x0c00" name="VSC_BIN_SIZE">
+ <bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>
+ <bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0c01" name="VSC_SIZE_ADDRESS"/>
+ <reg32 offset="0x0c02" name="VSC_SIZE_ADDRESS2"/>
+ <reg32 offset="0x0c03" name="VSC_DEBUG_ECO_CONTROL"/>
+ <array offset="0x0c08" name="VSC_PIPE_CONFIG" stride="1" length="8">
+ <reg32 offset="0x0" name="REG">
+ <doc>
+ Configures the mapping between VSC_PIPE buffer and
+ bin, X/Y specify the bin index in the horiz/vert
+ direction (0,0 is upper left, 0,1 is leftmost bin
+ on second row, and so on). W/H specify the number
+ of bins assigned to this VSC_PIPE in the horiz/vert
+ dimension.
+ </doc>
+ <bitfield name="X" low="0" high="9" type="uint"/>
+ <bitfield name="Y" low="10" high="19" type="uint"/>
+ <bitfield name="W" low="20" high="23" type="uint"/>
+ <bitfield name="H" low="24" high="27" type="uint"/>
+ </reg32>
+ </array>
+ <array offset="0x0c10" name="VSC_PIPE_DATA_ADDRESS" stride="1" length="8">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <array offset="0x0c18" name="VSC_PIPE_DATA_LENGTH" stride="1" length="8">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <reg32 offset="0x0c41" name="VSC_PIPE_PARTIAL_POSN_1"/>
+ <reg32 offset="0x0c50" name="VSC_PERFCTR_VSC_SEL_0" type="a4xx_vsc_perfcounter_select"/>
+ <reg32 offset="0x0c51" name="VSC_PERFCTR_VSC_SEL_1" type="a4xx_vsc_perfcounter_select"/>
+
+ <!-- VFD registers -->
+ <reg32 offset="0x0e40" name="VFD_DEBUG_CONTROL"/>
+ <reg32 offset="0x0e43" name="VFD_PERFCTR_VFD_SEL_0" type="a4xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e44" name="VFD_PERFCTR_VFD_SEL_1" type="a4xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e45" name="VFD_PERFCTR_VFD_SEL_2" type="a4xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e46" name="VFD_PERFCTR_VFD_SEL_3" type="a4xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e47" name="VFD_PERFCTR_VFD_SEL_4" type="a4xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e48" name="VFD_PERFCTR_VFD_SEL_5" type="a4xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e49" name="VFD_PERFCTR_VFD_SEL_6" type="a4xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e4a" name="VFD_PERFCTR_VFD_SEL_7" type="a4xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x21d0" name="VGT_CL_INITIATOR"/>
+ <reg32 offset="0x21d9" name="VGT_EVENT_INITIATOR"/>
+ <reg32 offset="0x2200" name="VFD_CONTROL_0">
+ <doc>
+ TOTALATTRTOVS is # of attributes to vertex shader, in register
+ slots (ie. vec4+vec3 -> 7)
+ </doc>
+ <bitfield name="TOTALATTRTOVS" low="0" high="7" type="uint"/>
+ <doc>
+ BYPASSATTROVS seems to count varyings that are just directly
+ assigned from attributes (ie, "vFoo = aFoo;")
+ </doc>
+ <bitfield name="BYPASSATTROVS" low="9" high="16" type="uint"/>
+ <doc>STRMDECINSTRCNT is # of VFD_DECODE_INSTR registers valid</doc>
+ <bitfield name="STRMDECINSTRCNT" low="20" high="25" type="uint"/>
+ <doc>STRMFETCHINSTRCNT is # of VFD_FETCH_INSTR registers valid</doc>
+ <bitfield name="STRMFETCHINSTRCNT" low="26" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2201" name="VFD_CONTROL_1">
+ <doc>MAXSTORAGE could be # of attributes/vbo's</doc>
+ <bitfield name="MAXSTORAGE" low="0" high="15" type="uint"/>
+ <bitfield name="REGID4VTX" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="REGID4INST" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0x2202" name="VFD_CONTROL_2"/>
+ <reg32 offset="0x2203" name="VFD_CONTROL_3">
+ <bitfield name="REGID_VTXCNT" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0x2204" name="VFD_CONTROL_4"/>
+ <reg32 offset="0x2208" name="VFD_INDEX_OFFSET"/>
+ <array offset="0x220a" name="VFD_FETCH" stride="4" length="32">
+ <reg32 offset="0x0" name="INSTR_0">
+ <bitfield name="FETCHSIZE" low="0" high="6" type="uint"/>
+ <bitfield name="BUFSTRIDE" low="7" high="16" type="uint"/>
+ <bitfield name="SWITCHNEXT" pos="19" type="boolean"/>
+ <bitfield name="INSTANCED" pos="20" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x1" name="INSTR_1"/>
+ <reg32 offset="0x2" name="INSTR_2">
+ <bitfield name="SIZE" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="0x3" name="INSTR_3">
+ <!-- might well be bigger.. -->
+ <bitfield name="STEPRATE" low="0" high="8" type="uint"/>
+ </reg32>
+ </array>
+ <array offset="0x228a" name="VFD_DECODE" stride="1" length="32">
+ <reg32 offset="0x0" name="INSTR">
+ <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
+ <!-- not sure if this is a bit flag and another flag above it, or?? -->
+ <bitfield name="CONSTFILL" pos="4" type="boolean"/>
+ <bitfield name="FORMAT" low="6" high="11" type="a4xx_vtx_fmt"/>
+ <bitfield name="REGID" low="12" high="19" type="a3xx_regid"/>
+ <bitfield name="INT" pos="20" type="boolean"/>
+ <doc>SHIFTCNT appears to be size, ie. FLOAT_32_32_32 is 12, and BYTE_8 is 1</doc>
+ <bitfield name="SWAP" low="22" high="23" type="a3xx_color_swap"/>
+ <bitfield name="SHIFTCNT" low="24" high="28" type="uint"/>
+ <bitfield name="LASTCOMPVALID" pos="29" type="boolean"/>
+ <bitfield name="SWITCHNEXT" pos="30" type="boolean"/>
+ </reg32>
+ </array>
+
+ <!-- TPL1 registers -->
+ <reg32 offset="0x0f00" name="TPL1_DEBUG_ECO_CONTROL"/>
+ <!-- always 0000003a: -->
+ <reg32 offset="0x0f03" name="TPL1_TP_MODE_CONTROL"/>
+ <reg32 offset="0x0f04" name="TPL1_PERFCTR_TP_SEL_0" type="a4xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f05" name="TPL1_PERFCTR_TP_SEL_1" type="a4xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f06" name="TPL1_PERFCTR_TP_SEL_2" type="a4xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f07" name="TPL1_PERFCTR_TP_SEL_3" type="a4xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f08" name="TPL1_PERFCTR_TP_SEL_4" type="a4xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f09" name="TPL1_PERFCTR_TP_SEL_5" type="a4xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f0a" name="TPL1_PERFCTR_TP_SEL_6" type="a4xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f0b" name="TPL1_PERFCTR_TP_SEL_7" type="a4xx_tp_perfcounter_select"/>
+ <reg32 offset="0x2380" name="TPL1_TP_TEX_OFFSET"/>
+ <reg32 offset="0x2381" name="TPL1_TP_TEX_COUNT">
+ <bitfield name="VS" low="0" high="7" type="uint"/>
+ <bitfield name="HS" low="8" high="15" type="uint"/>
+ <bitfield name="DS" low="16" high="23" type="uint"/>
+ <bitfield name="GS" low="24" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2384" name="TPL1_TP_VS_BORDER_COLOR_BASE_ADDR"/>
+ <reg32 offset="0x2387" name="TPL1_TP_HS_BORDER_COLOR_BASE_ADDR"/>
+ <reg32 offset="0x238a" name="TPL1_TP_DS_BORDER_COLOR_BASE_ADDR"/>
+ <reg32 offset="0x238d" name="TPL1_TP_GS_BORDER_COLOR_BASE_ADDR"/>
+ <reg32 offset="0x23a0" name="TPL1_TP_FS_TEX_COUNT">
+ <bitfield name="FS" low="0" high="7" type="uint"/>
+ <bitfield name="CS" low="8" high="15" type="uint"/>
+ </reg32>
+ <reg32 offset="0x23a1" name="TPL1_TP_FS_BORDER_COLOR_BASE_ADDR"/>
+ <reg32 offset="0x23a4" name="TPL1_TP_CS_BORDER_COLOR_BASE_ADDR"/>
+ <reg32 offset="0x23a5" name="TPL1_TP_CS_SAMPLER_BASE_ADDR"/>
+ <reg32 offset="0x23a6" name="TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR"/>
+
+ <!-- GRAS registers -->
+ <reg32 offset="0x0c80" name="GRAS_TSE_STATUS"/>
+ <reg32 offset="0x0c81" name="GRAS_DEBUG_ECO_CONTROL"/>
+ <reg32 offset="0x0c88" name="GRAS_PERFCTR_TSE_SEL_0" type="a4xx_gras_tse_perfcounter_select"/>
+ <reg32 offset="0x0c89" name="GRAS_PERFCTR_TSE_SEL_1" type="a4xx_gras_tse_perfcounter_select"/>
+ <reg32 offset="0x0c8a" name="GRAS_PERFCTR_TSE_SEL_2" type="a4xx_gras_tse_perfcounter_select"/>
+ <reg32 offset="0x0c8b" name="GRAS_PERFCTR_TSE_SEL_3" type="a4xx_gras_tse_perfcounter_select"/>
+ <reg32 offset="0x0c8c" name="GRAS_PERFCTR_RAS_SEL_0" type="a4xx_gras_ras_perfcounter_select"/>
+ <reg32 offset="0x0c8d" name="GRAS_PERFCTR_RAS_SEL_1" type="a4xx_gras_ras_perfcounter_select"/>
+ <reg32 offset="0x0c8e" name="GRAS_PERFCTR_RAS_SEL_2" type="a4xx_gras_ras_perfcounter_select"/>
+ <reg32 offset="0x0c8f" name="GRAS_PERFCTR_RAS_SEL_3" type="a4xx_gras_ras_perfcounter_select"/>
+ <reg32 offset="0x2000" name="GRAS_CL_CLIP_CNTL">
+ <bitfield name="CLIP_DISABLE" pos="15" type="boolean"/>
+ <bitfield name="ZNEAR_CLIP_DISABLE" pos="16" type="boolean"/>
+ <bitfield name="ZFAR_CLIP_DISABLE" pos="17" type="boolean"/>
+ <bitfield name="ZERO_GB_SCALE_Z" pos="22" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2003" name="GRAS_CNTL">
+ <bitfield name="IJ_PERSP" pos="0" type="boolean"/>
+ <bitfield name="IJ_LINEAR" pos="1" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2004" name="GRAS_CL_GB_CLIP_ADJ">
+ <bitfield name="HORZ" low="0" high="9" type="uint"/>
+ <bitfield name="VERT" low="10" high="19" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2008" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
+ <reg32 offset="0x2009" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
+ <reg32 offset="0x200a" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
+ <reg32 offset="0x200b" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
+ <reg32 offset="0x200c" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
+ <reg32 offset="0x200d" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
+ <reg32 offset="0x2070" name="GRAS_SU_POINT_MINMAX">
+ <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
+ <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
+ </reg32>
+ <reg32 offset="0x2071" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
+ <reg32 offset="0x2073" name="GRAS_ALPHA_CONTROL">
+ <bitfield name="ALPHA_TEST_ENABLE" pos="2" type="boolean"/>
+ <bitfield name="FORCE_FRAGZ_TO_FS" pos="3" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2074" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
+ <reg32 offset="0x2075" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
+ <reg32 offset="0x2076" name="GRAS_SU_POLY_OFFSET_CLAMP" type="float"/>
+ <reg32 offset="0x2077" name="GRAS_DEPTH_CONTROL">
+ <!-- guestimating that this is GRAS based on addr -->
+ <bitfield name="FORMAT" low="0" high="1" type="a4xx_depth_format"/>
+ </reg32>
+ <reg32 offset="0x2078" name="GRAS_SU_MODE_CONTROL">
+ <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
+ <bitfield name="CULL_BACK" pos="1" type="boolean"/>
+ <bitfield name="FRONT_CW" pos="2" type="boolean"/>
+ <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
+ <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
+ <bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
+ <!-- bit20 set whenever RENDER_MODE = RB_RENDERING_PASS -->
+ <bitfield name="RENDERING_PASS" pos="20" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x207b" name="GRAS_SC_CONTROL">
+ <!-- complete wild-ass-guess for sizes of these bitfields.. -->
+ <bitfield name="RENDER_MODE" low="2" high="3" type="a3xx_render_mode"/>
+ <bitfield name="MSAA_SAMPLES" low="7" high="9" type="uint"/>
+ <bitfield name="MSAA_DISABLE" pos="11" type="boolean"/>
+ <bitfield name="RASTER_MODE" low="12" high="15"/>
+ </reg32>
+ <reg32 offset="0x207c" name="GRAS_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>
+ <reg32 offset="0x207d" name="GRAS_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>
+ <reg32 offset="0x209c" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
+ <reg32 offset="0x209d" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
+ <reg32 offset="0x209e" name="GRAS_SC_EXTENT_WINDOW_BR" type="adreno_reg_xy"/>
+ <reg32 offset="0x209f" name="GRAS_SC_EXTENT_WINDOW_TL" type="adreno_reg_xy"/>
+
+ <!-- UCHE registers -->
+ <reg32 offset="0x0e80" name="UCHE_CACHE_MODE_CONTROL"/>
+ <reg32 offset="0x0e83" name="UCHE_TRAP_BASE_LO"/>
+ <reg32 offset="0x0e84" name="UCHE_TRAP_BASE_HI"/>
+ <reg32 offset="0x0e88" name="UCHE_CACHE_STATUS"/>
+ <reg32 offset="0x0e8a" name="UCHE_INVALIDATE0"/>
+ <reg32 offset="0x0e8b" name="UCHE_INVALIDATE1"/>
+ <reg32 offset="0x0e8c" name="UCHE_CACHE_WAYS_VFD"/>
+ <reg32 offset="0x0e8e" name="UCHE_PERFCTR_UCHE_SEL_0" type="a4xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0e8f" name="UCHE_PERFCTR_UCHE_SEL_1" type="a4xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0e90" name="UCHE_PERFCTR_UCHE_SEL_2" type="a4xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0e91" name="UCHE_PERFCTR_UCHE_SEL_3" type="a4xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0e92" name="UCHE_PERFCTR_UCHE_SEL_4" type="a4xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0e93" name="UCHE_PERFCTR_UCHE_SEL_5" type="a4xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0e94" name="UCHE_PERFCTR_UCHE_SEL_6" type="a4xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0e95" name="UCHE_PERFCTR_UCHE_SEL_7" type="a4xx_uche_perfcounter_select"/>
+
+ <!-- HLSQ registers -->
+ <reg32 offset="0x0e00" name="HLSQ_TIMEOUT_THRESHOLD"/>
+ <reg32 offset="0x0e04" name="HLSQ_DEBUG_ECO_CONTROL"/>
+ <!-- always 00000000: -->
+ <reg32 offset="0x0e05" name="HLSQ_MODE_CONTROL"/>
+ <reg32 offset="0x0e0e" name="HLSQ_PERF_PIPE_MASK"/>
+ <reg32 offset="0x0e06" name="HLSQ_PERFCTR_HLSQ_SEL_0" type="a4xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e07" name="HLSQ_PERFCTR_HLSQ_SEL_1" type="a4xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e08" name="HLSQ_PERFCTR_HLSQ_SEL_2" type="a4xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e09" name="HLSQ_PERFCTR_HLSQ_SEL_3" type="a4xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e0a" name="HLSQ_PERFCTR_HLSQ_SEL_4" type="a4xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e0b" name="HLSQ_PERFCTR_HLSQ_SEL_5" type="a4xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e0c" name="HLSQ_PERFCTR_HLSQ_SEL_6" type="a4xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e0d" name="HLSQ_PERFCTR_HLSQ_SEL_7" type="a4xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x23c0" name="HLSQ_CONTROL_0_REG">
+ <!-- I guess same as a3xx, but so far only seen 08000050 -->
+ <bitfield name="FSTHREADSIZE" pos="4" type="a3xx_threadsize"/>
+ <bitfield name="FSSUPERTHREADENABLE" pos="6" type="boolean"/>
+ <bitfield name="SPSHADERRESTART" pos="9" type="boolean"/>
+ <bitfield name="RESERVED2" pos="10" type="boolean"/>
+ <bitfield name="CHUNKDISABLE" pos="26" type="boolean"/>
+ <bitfield name="CONSTMODE" pos="27" type="uint"/>
+ <bitfield name="LAZYUPDATEDISABLE" pos="28" type="boolean"/>
+ <bitfield name="SPCONSTFULLUPDATE" pos="29" type="boolean"/>
+ <bitfield name="TPFULLUPDATE" pos="30" type="boolean"/>
+ <bitfield name="SINGLECONTEXT" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x23c1" name="HLSQ_CONTROL_1_REG">
+ <bitfield name="VSTHREADSIZE" pos="6" type="a3xx_threadsize"/>
+ <bitfield name="VSSUPERTHREADENABLE" pos="8" type="boolean"/>
+ <bitfield name="RESERVED1" pos="9" type="boolean"/>
+ <bitfield name="COORDREGID" low="16" high="23" type="a3xx_regid"/>
+ <!-- set if gl_FragCoord.[zw] used in frag shader: -->
+ <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0x23c2" name="HLSQ_CONTROL_2_REG">
+ <bitfield name="PRIMALLOCTHRESHOLD" low="26" high="31" type="uint"/>
+ <bitfield name="FACEREGID" low="2" high="9" type="a3xx_regid"/>
+ <bitfield name="SAMPLEID_REGID" low="10" high="17" type="a3xx_regid"/>
+ <bitfield name="SAMPLEMASK_REGID" low="18" high="25" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0x23c3" name="HLSQ_CONTROL_3_REG">
+ <!-- register loaded with position (bary.f) -->
+ <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <!-- 0x23c4 3 regids, lowest one goes to 0 when *not* per-sample shading -->
+ <reg32 offset="0x23c4" name="HLSQ_CONTROL_4_REG">
+ <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
+ </reg32>
+
+ <bitset name="a4xx_xs_control_reg" inline="yes">
+ <bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/>
+ <bitfield name="CONSTOBJECTOFFSET" low="8" high="14" type="uint"/>
+ <bitfield name="SSBO_ENABLE" pos="15" type="boolean"/>
+ <bitfield name="ENABLED" pos="16" type="boolean"/>
+ <bitfield name="SHADEROBJOFFSET" low="17" high="23" type="uint"/>
+ <bitfield name="INSTRLENGTH" low="24" high="31" type="uint"/>
+ </bitset>
+ <reg32 offset="0x23c5" name="HLSQ_VS_CONTROL_REG" type="a4xx_xs_control_reg"/>
+ <reg32 offset="0x23c6" name="HLSQ_FS_CONTROL_REG" type="a4xx_xs_control_reg"/>
+ <reg32 offset="0x23c7" name="HLSQ_HS_CONTROL_REG" type="a4xx_xs_control_reg"/>
+ <reg32 offset="0x23c8" name="HLSQ_DS_CONTROL_REG" type="a4xx_xs_control_reg"/>
+ <reg32 offset="0x23c9" name="HLSQ_GS_CONTROL_REG" type="a4xx_xs_control_reg"/>
+ <reg32 offset="0x23ca" name="HLSQ_CS_CONTROL_REG" type="a4xx_xs_control_reg"/>
+ <reg32 offset="0x23cd" name="HLSQ_CL_NDRANGE_0">
+ <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
+ <!-- localsize is value minus one: -->
+ <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
+ <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
+ <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x23ce" name="HLSQ_CL_NDRANGE_1">
+ <bitfield name="SIZE_X" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x23cf" name="HLSQ_CL_NDRANGE_2"/>
+ <reg32 offset="0x23d0" name="HLSQ_CL_NDRANGE_3">
+ <bitfield name="SIZE_Y" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x23d1" name="HLSQ_CL_NDRANGE_4"/>
+ <reg32 offset="0x23d2" name="HLSQ_CL_NDRANGE_5">
+ <bitfield name="SIZE_Z" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x23d3" name="HLSQ_CL_NDRANGE_6"/>
+ <reg32 offset="0x23d4" name="HLSQ_CL_CONTROL_0">
+ <bitfield name="WGIDCONSTID" low="0" high="11" type="a3xx_regid"/>
+ <bitfield name="KERNELDIMCONSTID" low="12" high="23" type="a3xx_regid"/>
+ <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0x23d5" name="HLSQ_CL_CONTROL_1">
+ <!-- GLOBALSIZECONSTID? "kernel size" -->
+ <bitfield name="UNK0CONSTID" low="0" high="11" type="a3xx_regid"/>
+ <bitfield name="WORKGROUPSIZECONSTID" low="12" high="23" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0x23d6" name="HLSQ_CL_KERNEL_CONST">
+ <!-- GLOBALOFFSETCONSTID -->
+ <bitfield name="UNK0CONSTID" low="0" high="11" type="a3xx_regid"/>
+ <bitfield name="NUMWGCONSTID" low="12" high="23" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0x23d7" name="HLSQ_CL_KERNEL_GROUP_X"/>
+ <reg32 offset="0x23d8" name="HLSQ_CL_KERNEL_GROUP_Y"/>
+ <reg32 offset="0x23d9" name="HLSQ_CL_KERNEL_GROUP_Z"/>
+ <reg32 offset="0x23da" name="HLSQ_CL_WG_OFFSET">
+ <!-- WGOFFSETCONSTID -->
+ <bitfield name="UNK0CONSTID" low="0" high="11" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0x23db" name="HLSQ_UPDATE_CONTROL"/>
+
+ <!-- PC registers -->
+ <reg32 offset="0x0d00" name="PC_BINNING_COMMAND">
+ <bitfield name="BINNING_ENABLE" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0d08" name="PC_TESSFACTOR_ADDR"/>
+ <reg32 offset="0x0d0c" name="PC_DRAWCALL_SETUP_OVERRIDE"/>
+ <reg32 offset="0x0d10" name="PC_PERFCTR_PC_SEL_0" type="a4xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0d11" name="PC_PERFCTR_PC_SEL_1" type="a4xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0d12" name="PC_PERFCTR_PC_SEL_2" type="a4xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0d13" name="PC_PERFCTR_PC_SEL_3" type="a4xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0d14" name="PC_PERFCTR_PC_SEL_4" type="a4xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0d15" name="PC_PERFCTR_PC_SEL_5" type="a4xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0d16" name="PC_PERFCTR_PC_SEL_6" type="a4xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0d17" name="PC_PERFCTR_PC_SEL_7" type="a4xx_pc_perfcounter_select"/>
+ <reg32 offset="0x21c0" name="PC_BIN_BASE"/>
+ <reg32 offset="0x21c2" name="PC_VSTREAM_CONTROL">
+ <doc>SIZE is current pipe width * height (in tiles)</doc>
+ <bitfield name="SIZE" low="16" high="21" type="uint"/>
+ <doc>
+ N is some sort of slot # between 0..(SIZE-1). In case
+ multiple tiles use same pipe, each tile gets unique slot #
+ </doc>
+ <bitfield name="N" low="22" high="26" type="uint"/>
+ </reg32>
+ <reg32 offset="0x21c4" name="PC_PRIM_VTX_CNTL">
+ <!-- bit0 set if there is >= 1 varying (actually used by FS) -->
+ <bitfield name="VAROUT" low="0" high="3" type="uint">
+ <doc>in groups of 4x vec4, blob only uses values
+ 0, 1, 2, 4, 6, 8</doc>
+ </bitfield>
+ <bitfield name="PRIMITIVE_RESTART" pos="20" type="boolean"/>
+ <bitfield name="PROVOKING_VTX_LAST" pos="25" type="boolean"/>
+ <!-- PSIZE bit set if gl_PointSize written: -->
+ <bitfield name="PSIZE" pos="26" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x21c5" name="PC_PRIM_VTX_CNTL2">
+ <bitfield name="POLYMODE_FRONT_PTYPE" low="0" high="2" type="adreno_pa_su_sc_draw"/>
+ <bitfield name="POLYMODE_BACK_PTYPE" low="3" high="5" type="adreno_pa_su_sc_draw"/>
+ <bitfield name="POLYMODE_ENABLE" pos="6" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x21c6" name="PC_RESTART_INDEX"/>
+ <reg32 offset="0x21e5" name="PC_GS_PARAM">
+ <bitfield name="MAX_VERTICES" low="0" high="9" type="uint"/><!-- +1, i.e. max is 1024 -->
+ <bitfield name="INVOCATIONS" low="11" high="15" type="uint"/><!-- +1, i.e. max is 32 -->
+ <bitfield name="PRIMTYPE" low="23" high="24" type="adreno_pa_su_sc_draw"/>
+ <bitfield name="LAYER" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x21e7" name="PC_HS_PARAM">
+ <bitfield name="VERTICES_OUT" low="0" high="5" type="uint"/>
+ <bitfield name="SPACING" low="21" high="22" type="a4xx_tess_spacing"/>
+ <bitfield name="CW" pos="23" type="boolean"/>
+ <bitfield name="CONNECTED" pos="24" type="boolean"/>
+ </reg32>
+
+ <!-- VBIF registers -->
+ <reg32 offset="0x3000" name="VBIF_VERSION"/>
+ <reg32 offset="0x3001" name="VBIF_CLKON">
+ <bitfield name="FORCE_ON_TESTBUS" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x301c" name="VBIF_ABIT_SORT"/>
+ <reg32 offset="0x301d" name="VBIF_ABIT_SORT_CONF"/>
+ <reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/>
+ <reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/>
+ <reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/>
+ <reg32 offset="0x3030" name="VBIF_IN_WR_LIM_CONF0"/>
+ <reg32 offset="0x3031" name="VBIF_IN_WR_LIM_CONF1"/>
+ <reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/>
+ <reg32 offset="0x30c0" name="VBIF_PERF_CNT_EN0"/>
+ <reg32 offset="0x30c1" name="VBIF_PERF_CNT_EN1"/>
+ <reg32 offset="0x30c2" name="VBIF_PERF_CNT_EN2"/>
+ <reg32 offset="0x30c3" name="VBIF_PERF_CNT_EN3"/>
+ <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0" type="a4xx_vbif_perfcounter_select"/>
+ <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1" type="a4xx_vbif_perfcounter_select"/>
+ <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2" type="a4xx_vbif_perfcounter_select"/>
+ <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3" type="a4xx_vbif_perfcounter_select"/>
+ <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
+ <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
+ <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
+ <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
+ <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
+ <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
+ <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
+ <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
+ <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
+ <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
+ <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
+
+ <!--
+ Unknown registers:
+ (mostly related to DX11 features not used yet, I guess?)
+ -->
+
+ <!-- always 00000006: -->
+ <reg32 offset="0x0cc5" name="UNKNOWN_0CC5"/>
+
+ <!-- always 00000000: -->
+ <reg32 offset="0x0cc6" name="UNKNOWN_0CC6"/>
+
+ <!-- always 00000001: -->
+ <reg32 offset="0x0d01" name="UNKNOWN_0D01"/>
+
+ <!-- always 00000000: -->
+ <reg32 offset="0x0e42" name="UNKNOWN_0E42"/>
+
+ <!-- always 00040000: -->
+ <reg32 offset="0x0ec2" name="UNKNOWN_0EC2"/>
+
+ <!-- always 00000000: -->
+ <reg32 offset="0x2001" name="UNKNOWN_2001"/>
+
+ <!-- always 00000000: -->
+ <reg32 offset="0x209b" name="UNKNOWN_209B"/>
+
+ <!-- always 00000000: -->
+ <reg32 offset="0x20ef" name="UNKNOWN_20EF"/>
+
+ <!-- always 00000000: -->
+ <reg32 offset="0x2152" name="UNKNOWN_2152"/>
+
+ <!-- always 00000000: -->
+ <reg32 offset="0x2153" name="UNKNOWN_2153"/>
+
+ <!-- always 00000000: -->
+ <reg32 offset="0x2154" name="UNKNOWN_2154"/>
+
+ <!-- always 00000000: -->
+ <reg32 offset="0x2155" name="UNKNOWN_2155"/>
+
+ <!-- always 00000000: -->
+ <reg32 offset="0x2156" name="UNKNOWN_2156"/>
+
+ <!-- always 00000000: -->
+ <reg32 offset="0x2157" name="UNKNOWN_2157"/>
+
+ <!-- always 0000000b: -->
+ <reg32 offset="0x21c3" name="UNKNOWN_21C3"/>
+
+ <!-- always 00000001: -->
+ <reg32 offset="0x21e6" name="UNKNOWN_21E6"/>
+
+ <!-- always 00000000: -->
+ <reg32 offset="0x2209" name="UNKNOWN_2209"/>
+
+ <!-- always 00000000: -->
+ <reg32 offset="0x22d7" name="UNKNOWN_22D7"/>
+
+ <!-- always 00fcfc00: -->
+ <reg32 offset="0x2352" name="UNKNOWN_2352"/>
+
+</domain>
+
+
+<domain name="A4XX_TEX_SAMP" width="32">
+ <doc>Texture sampler dwords</doc>
+ <enum name="a4xx_tex_filter">
+ <value name="A4XX_TEX_NEAREST" value="0"/>
+ <value name="A4XX_TEX_LINEAR" value="1"/>
+ <value name="A4XX_TEX_ANISO" value="2"/>
+ </enum>
+ <enum name="a4xx_tex_clamp">
+ <value name="A4XX_TEX_REPEAT" value="0"/>
+ <value name="A4XX_TEX_CLAMP_TO_EDGE" value="1"/>
+ <value name="A4XX_TEX_MIRROR_REPEAT" value="2"/>
+ <value name="A4XX_TEX_CLAMP_TO_BORDER" value="3"/>
+ <value name="A4XX_TEX_MIRROR_CLAMP" value="4"/>
+ </enum>
+ <enum name="a4xx_tex_aniso">
+ <value name="A4XX_TEX_ANISO_1" value="0"/>
+ <value name="A4XX_TEX_ANISO_2" value="1"/>
+ <value name="A4XX_TEX_ANISO_4" value="2"/>
+ <value name="A4XX_TEX_ANISO_8" value="3"/>
+ <value name="A4XX_TEX_ANISO_16" value="4"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
+ <bitfield name="XY_MAG" low="1" high="2" type="a4xx_tex_filter"/>
+ <bitfield name="XY_MIN" low="3" high="4" type="a4xx_tex_filter"/>
+ <bitfield name="WRAP_S" low="5" high="7" type="a4xx_tex_clamp"/>
+ <bitfield name="WRAP_T" low="8" high="10" type="a4xx_tex_clamp"/>
+ <bitfield name="WRAP_R" low="11" high="13" type="a4xx_tex_clamp"/>
+ <bitfield name="ANISO" low="14" high="16" type="a4xx_tex_aniso"/>
+ <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
+ <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
+ <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
+ <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
+ <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
+ <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
+ </reg32>
+</domain>
+
+<domain name="A4XX_TEX_CONST" width="32">
+ <doc>Texture constant dwords</doc>
+ <enum name="a4xx_tex_swiz">
+ <!-- same as a2xx? -->
+ <value name="A4XX_TEX_X" value="0"/>
+ <value name="A4XX_TEX_Y" value="1"/>
+ <value name="A4XX_TEX_Z" value="2"/>
+ <value name="A4XX_TEX_W" value="3"/>
+ <value name="A4XX_TEX_ZERO" value="4"/>
+ <value name="A4XX_TEX_ONE" value="5"/>
+ </enum>
+ <enum name="a4xx_tex_type">
+ <value name="A4XX_TEX_1D" value="0"/>
+ <value name="A4XX_TEX_2D" value="1"/>
+ <value name="A4XX_TEX_CUBE" value="2"/>
+ <value name="A4XX_TEX_3D" value="3"/>
+ <value name="A4XX_TEX_BUFFER" value="4"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="TILED" pos="0" type="boolean"/>
+ <bitfield name="SRGB" pos="2" type="boolean"/>
+ <bitfield name="SWIZ_X" low="4" high="6" type="a4xx_tex_swiz"/>
+ <bitfield name="SWIZ_Y" low="7" high="9" type="a4xx_tex_swiz"/>
+ <bitfield name="SWIZ_Z" low="10" high="12" type="a4xx_tex_swiz"/>
+ <bitfield name="SWIZ_W" low="13" high="15" type="a4xx_tex_swiz"/>
+ <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
+ <bitfield name="FMT" low="22" high="28" type="a4xx_tex_fmt"/>
+ <bitfield name="TYPE" low="29" high="31" type="a4xx_tex_type"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="HEIGHT" low="0" high="14" type="uint"/>
+ <bitfield name="WIDTH" low="15" high="29" type="uint"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <!-- minimum pitch (for mipmap levels): log2(pitchalign / 32) -->
+ <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
+ <bitfield name="BUFFER" pos="6" type="boolean"/>
+ <doc>Pitch in bytes (so actually stride)</doc>
+ <bitfield name="PITCH" low="9" high="29" type="uint"/>
+ <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="LAYERSZ" low="0" high="13" shr="12" type="uint"/>
+ <bitfield name="DEPTH" low="18" high="30" type="uint"/>
+ </reg32>
+ <reg32 offset="4" name="4">
+ <!--
+ like a3xx we seem to have two LAYERSZ's.. although this one
+ seems too small to be useful, and when it overflows blob just
+ sets it to zero..
+ -->
+ <bitfield name="LAYERSZ" low="0" high="3" shr="12" type="uint"/>
+ <bitfield name="BASE" low="5" high="31" shr="5"/>
+ </reg32>
+ <reg32 offset="5" name="5"/>
+ <reg32 offset="6" name="6"/>
+ <reg32 offset="7" name="7"/>
+</domain>
+
+<domain name="A4XX_SSBO_0" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="BASE" low="5" high="31" shr="5"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <doc>Pitch in bytes (so actually stride)</doc>
+ <bitfield name="PITCH" low="0" high="21" type="uint"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="ARRAY_PITCH" low="12" high="25" shr="12" type="uint"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <!-- bytes per pixel: -->
+ <bitfield name="CPP" low="0" high="5" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="A4XX_SSBO_1" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="CPP" low="0" high="4" type="uint"/>
+ <bitfield name="FMT" low="8" high="15" type="a4xx_color_fmt"/>
+ <bitfield name="WIDTH" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="HEIGHT" low="0" high="15" type="uint"/>
+ <bitfield name="DEPTH" low="16" high="31" type="uint"/>
+ </reg32>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/adreno/a5xx.xml b/drivers/gpu/drm/msm/registers/adreno/a5xx.xml
new file mode 100644
index 000000000000..bd8df5945166
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/adreno/a5xx.xml
@@ -0,0 +1,3039 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+<import file="adreno/adreno_common.xml"/>
+<import file="adreno/adreno_pm4.xml"/>
+
+<enum name="a5xx_color_fmt">
+ <value value="0x02" name="RB5_A8_UNORM"/>
+ <value value="0x03" name="RB5_R8_UNORM"/>
+ <value value="0x04" name="RB5_R8_SNORM"/>
+ <value value="0x05" name="RB5_R8_UINT"/>
+ <value value="0x06" name="RB5_R8_SINT"/>
+ <value value="0x08" name="RB5_R4G4B4A4_UNORM"/>
+ <value value="0x0a" name="RB5_R5G5B5A1_UNORM"/>
+ <value value="0x0e" name="RB5_R5G6B5_UNORM"/>
+ <value value="0x0f" name="RB5_R8G8_UNORM"/>
+ <value value="0x10" name="RB5_R8G8_SNORM"/>
+ <value value="0x11" name="RB5_R8G8_UINT"/>
+ <value value="0x12" name="RB5_R8G8_SINT"/>
+ <value value="0x15" name="RB5_R16_UNORM"/>
+ <value value="0x16" name="RB5_R16_SNORM"/>
+ <value value="0x17" name="RB5_R16_FLOAT"/>
+ <value value="0x18" name="RB5_R16_UINT"/>
+ <value value="0x19" name="RB5_R16_SINT"/>
+ <value value="0x30" name="RB5_R8G8B8A8_UNORM"/>
+ <value value="0x31" name="RB5_R8G8B8_UNORM"/>
+ <value value="0x32" name="RB5_R8G8B8A8_SNORM"/>
+ <value value="0x33" name="RB5_R8G8B8A8_UINT"/>
+ <value value="0x34" name="RB5_R8G8B8A8_SINT"/>
+ <value value="0x37" name="RB5_R10G10B10A2_UNORM"/> <!-- GL_RGB10_A2 -->
+ <value value="0x3a" name="RB5_R10G10B10A2_UINT"/> <!-- GL_RGB10_A2UI -->
+ <value value="0x42" name="RB5_R11G11B10_FLOAT"/> <!-- GL_R11F_G11F_B10F -->
+ <value value="0x43" name="RB5_R16G16_UNORM"/>
+ <value value="0x44" name="RB5_R16G16_SNORM"/>
+ <value value="0x45" name="RB5_R16G16_FLOAT"/>
+ <value value="0x46" name="RB5_R16G16_UINT"/>
+ <value value="0x47" name="RB5_R16G16_SINT"/>
+ <value value="0x4a" name="RB5_R32_FLOAT"/>
+ <value value="0x4b" name="RB5_R32_UINT"/>
+ <value value="0x4c" name="RB5_R32_SINT"/>
+ <value value="0x60" name="RB5_R16G16B16A16_UNORM"/>
+ <value value="0x61" name="RB5_R16G16B16A16_SNORM"/>
+ <value value="0x62" name="RB5_R16G16B16A16_FLOAT"/>
+ <value value="0x63" name="RB5_R16G16B16A16_UINT"/>
+ <value value="0x64" name="RB5_R16G16B16A16_SINT"/>
+ <value value="0x67" name="RB5_R32G32_FLOAT"/>
+ <value value="0x68" name="RB5_R32G32_UINT"/>
+ <value value="0x69" name="RB5_R32G32_SINT"/>
+ <value value="0x82" name="RB5_R32G32B32A32_FLOAT"/>
+ <value value="0x83" name="RB5_R32G32B32A32_UINT"/>
+ <value value="0x84" name="RB5_R32G32B32A32_SINT"/>
+
+ <value value="0xff" name="RB5_NONE"/>
+</enum>
+
+<enum name="a5xx_tile_mode">
+ <value name="TILE5_LINEAR" value="0"/>
+ <value name="TILE5_2" value="2"/>
+ <value name="TILE5_3" value="3"/>
+</enum>
+
+<enum name="a5xx_vtx_fmt" prefix="chipset">
+ <value value="0x03" name="VFMT5_8_UNORM"/>
+ <value value="0x04" name="VFMT5_8_SNORM"/>
+ <value value="0x05" name="VFMT5_8_UINT"/>
+ <value value="0x06" name="VFMT5_8_SINT"/>
+
+ <value value="0x0f" name="VFMT5_8_8_UNORM"/>
+ <value value="0x10" name="VFMT5_8_8_SNORM"/>
+ <value value="0x11" name="VFMT5_8_8_UINT"/>
+ <value value="0x12" name="VFMT5_8_8_SINT"/>
+
+ <value value="0x15" name="VFMT5_16_UNORM"/>
+ <value value="0x16" name="VFMT5_16_SNORM"/>
+ <value value="0x17" name="VFMT5_16_FLOAT"/>
+ <value value="0x18" name="VFMT5_16_UINT"/>
+ <value value="0x19" name="VFMT5_16_SINT"/>
+
+ <value value="0x21" name="VFMT5_8_8_8_UNORM"/>
+ <value value="0x22" name="VFMT5_8_8_8_SNORM"/>
+ <value value="0x23" name="VFMT5_8_8_8_UINT"/>
+ <value value="0x24" name="VFMT5_8_8_8_SINT"/>
+
+ <value value="0x30" name="VFMT5_8_8_8_8_UNORM"/>
+ <value value="0x32" name="VFMT5_8_8_8_8_SNORM"/>
+ <value value="0x33" name="VFMT5_8_8_8_8_UINT"/>
+ <value value="0x34" name="VFMT5_8_8_8_8_SINT"/>
+
+ <value value="0x36" name="VFMT5_10_10_10_2_UNORM"/>
+ <value value="0x39" name="VFMT5_10_10_10_2_SNORM"/>
+ <value value="0x3a" name="VFMT5_10_10_10_2_UINT"/>
+ <value value="0x3b" name="VFMT5_10_10_10_2_SINT"/>
+
+ <value value="0x42" name="VFMT5_11_11_10_FLOAT"/>
+
+ <value value="0x43" name="VFMT5_16_16_UNORM"/>
+ <value value="0x44" name="VFMT5_16_16_SNORM"/>
+ <value value="0x45" name="VFMT5_16_16_FLOAT"/>
+ <value value="0x46" name="VFMT5_16_16_UINT"/>
+ <value value="0x47" name="VFMT5_16_16_SINT"/>
+
+ <value value="0x48" name="VFMT5_32_UNORM"/>
+ <value value="0x49" name="VFMT5_32_SNORM"/>
+ <value value="0x4a" name="VFMT5_32_FLOAT"/>
+ <value value="0x4b" name="VFMT5_32_UINT"/>
+ <value value="0x4c" name="VFMT5_32_SINT"/>
+ <value value="0x4d" name="VFMT5_32_FIXED"/>
+
+ <value value="0x58" name="VFMT5_16_16_16_UNORM"/>
+ <value value="0x59" name="VFMT5_16_16_16_SNORM"/>
+ <value value="0x5a" name="VFMT5_16_16_16_FLOAT"/>
+ <value value="0x5b" name="VFMT5_16_16_16_UINT"/>
+ <value value="0x5c" name="VFMT5_16_16_16_SINT"/>
+
+ <value value="0x60" name="VFMT5_16_16_16_16_UNORM"/>
+ <value value="0x61" name="VFMT5_16_16_16_16_SNORM"/>
+ <value value="0x62" name="VFMT5_16_16_16_16_FLOAT"/>
+ <value value="0x63" name="VFMT5_16_16_16_16_UINT"/>
+ <value value="0x64" name="VFMT5_16_16_16_16_SINT"/>
+
+ <value value="0x65" name="VFMT5_32_32_UNORM"/>
+ <value value="0x66" name="VFMT5_32_32_SNORM"/>
+ <value value="0x67" name="VFMT5_32_32_FLOAT"/>
+ <value value="0x68" name="VFMT5_32_32_UINT"/>
+ <value value="0x69" name="VFMT5_32_32_SINT"/>
+ <value value="0x6a" name="VFMT5_32_32_FIXED"/>
+
+ <value value="0x70" name="VFMT5_32_32_32_UNORM"/>
+ <value value="0x71" name="VFMT5_32_32_32_SNORM"/>
+ <value value="0x72" name="VFMT5_32_32_32_UINT"/>
+ <value value="0x73" name="VFMT5_32_32_32_SINT"/>
+ <value value="0x74" name="VFMT5_32_32_32_FLOAT"/>
+ <value value="0x75" name="VFMT5_32_32_32_FIXED"/>
+
+ <value value="0x80" name="VFMT5_32_32_32_32_UNORM"/>
+ <value value="0x81" name="VFMT5_32_32_32_32_SNORM"/>
+ <value value="0x82" name="VFMT5_32_32_32_32_FLOAT"/>
+ <value value="0x83" name="VFMT5_32_32_32_32_UINT"/>
+ <value value="0x84" name="VFMT5_32_32_32_32_SINT"/>
+ <value value="0x85" name="VFMT5_32_32_32_32_FIXED"/>
+
+ <value value="0xff" name="VFMT5_NONE"/>
+</enum>
+
+<enum name="a5xx_tex_fmt">
+ <value value="0x02" name="TFMT5_A8_UNORM"/>
+ <value value="0x03" name="TFMT5_8_UNORM"/>
+ <value value="0x04" name="TFMT5_8_SNORM"/>
+ <value value="0x05" name="TFMT5_8_UINT"/>
+ <value value="0x06" name="TFMT5_8_SINT"/>
+ <value value="0x08" name="TFMT5_4_4_4_4_UNORM"/>
+ <value value="0x0a" name="TFMT5_5_5_5_1_UNORM"/>
+ <value value="0x0e" name="TFMT5_5_6_5_UNORM"/>
+ <value value="0x0f" name="TFMT5_8_8_UNORM"/>
+ <value value="0x10" name="TFMT5_8_8_SNORM"/>
+ <value value="0x11" name="TFMT5_8_8_UINT"/>
+ <value value="0x12" name="TFMT5_8_8_SINT"/>
+ <value value="0x13" name="TFMT5_L8_A8_UNORM"/>
+ <value value="0x15" name="TFMT5_16_UNORM"/>
+ <value value="0x16" name="TFMT5_16_SNORM"/>
+ <value value="0x17" name="TFMT5_16_FLOAT"/>
+ <value value="0x18" name="TFMT5_16_UINT"/>
+ <value value="0x19" name="TFMT5_16_SINT"/>
+ <value value="0x30" name="TFMT5_8_8_8_8_UNORM"/>
+ <value value="0x31" name="TFMT5_8_8_8_UNORM"/>
+ <value value="0x32" name="TFMT5_8_8_8_8_SNORM"/>
+ <value value="0x33" name="TFMT5_8_8_8_8_UINT"/>
+ <value value="0x34" name="TFMT5_8_8_8_8_SINT"/>
+ <value value="0x35" name="TFMT5_9_9_9_E5_FLOAT"/>
+ <value value="0x36" name="TFMT5_10_10_10_2_UNORM"/>
+ <value value="0x3a" name="TFMT5_10_10_10_2_UINT"/>
+ <value value="0x42" name="TFMT5_11_11_10_FLOAT"/>
+ <value value="0x43" name="TFMT5_16_16_UNORM"/>
+ <value value="0x44" name="TFMT5_16_16_SNORM"/>
+ <value value="0x45" name="TFMT5_16_16_FLOAT"/>
+ <value value="0x46" name="TFMT5_16_16_UINT"/>
+ <value value="0x47" name="TFMT5_16_16_SINT"/>
+ <value value="0x4a" name="TFMT5_32_FLOAT"/>
+ <value value="0x4b" name="TFMT5_32_UINT"/>
+ <value value="0x4c" name="TFMT5_32_SINT"/>
+ <value value="0x60" name="TFMT5_16_16_16_16_UNORM"/>
+ <value value="0x61" name="TFMT5_16_16_16_16_SNORM"/>
+ <value value="0x62" name="TFMT5_16_16_16_16_FLOAT"/>
+ <value value="0x63" name="TFMT5_16_16_16_16_UINT"/>
+ <value value="0x64" name="TFMT5_16_16_16_16_SINT"/>
+ <value value="0x67" name="TFMT5_32_32_FLOAT"/>
+ <value value="0x68" name="TFMT5_32_32_UINT"/>
+ <value value="0x69" name="TFMT5_32_32_SINT"/>
+ <value value="0x72" name="TFMT5_32_32_32_UINT"/>
+ <value value="0x73" name="TFMT5_32_32_32_SINT"/>
+ <value value="0x74" name="TFMT5_32_32_32_FLOAT"/>
+ <value value="0x82" name="TFMT5_32_32_32_32_FLOAT"/>
+ <value value="0x83" name="TFMT5_32_32_32_32_UINT"/>
+ <value value="0x84" name="TFMT5_32_32_32_32_SINT"/>
+ <value value="0xa0" name="TFMT5_X8Z24_UNORM"/>
+
+ <value value="0xab" name="TFMT5_ETC2_RG11_UNORM"/>
+ <value value="0xac" name="TFMT5_ETC2_RG11_SNORM"/>
+ <value value="0xad" name="TFMT5_ETC2_R11_UNORM"/>
+ <value value="0xae" name="TFMT5_ETC2_R11_SNORM"/>
+ <value value="0xaf" name="TFMT5_ETC1"/>
+ <value value="0xb0" name="TFMT5_ETC2_RGB8"/>
+ <value value="0xb1" name="TFMT5_ETC2_RGBA8"/>
+ <value value="0xb2" name="TFMT5_ETC2_RGB8A1"/>
+ <value value="0xb3" name="TFMT5_DXT1"/>
+ <value value="0xb4" name="TFMT5_DXT3"/>
+ <value value="0xb5" name="TFMT5_DXT5"/>
+ <value value="0xb7" name="TFMT5_RGTC1_UNORM"/>
+ <value value="0xb8" name="TFMT5_RGTC1_SNORM"/>
+ <value value="0xbb" name="TFMT5_RGTC2_UNORM"/>
+ <value value="0xbc" name="TFMT5_RGTC2_SNORM"/>
+ <value value="0xbe" name="TFMT5_BPTC_UFLOAT"/>
+ <value value="0xbf" name="TFMT5_BPTC_FLOAT"/>
+ <value value="0xc0" name="TFMT5_BPTC"/>
+ <value value="0xc1" name="TFMT5_ASTC_4x4"/>
+ <value value="0xc2" name="TFMT5_ASTC_5x4"/>
+ <value value="0xc3" name="TFMT5_ASTC_5x5"/>
+ <value value="0xc4" name="TFMT5_ASTC_6x5"/>
+ <value value="0xc5" name="TFMT5_ASTC_6x6"/>
+ <value value="0xc6" name="TFMT5_ASTC_8x5"/>
+ <value value="0xc7" name="TFMT5_ASTC_8x6"/>
+ <value value="0xc8" name="TFMT5_ASTC_8x8"/>
+ <value value="0xc9" name="TFMT5_ASTC_10x5"/>
+ <value value="0xca" name="TFMT5_ASTC_10x6"/>
+ <value value="0xcb" name="TFMT5_ASTC_10x8"/>
+ <value value="0xcc" name="TFMT5_ASTC_10x10"/>
+ <value value="0xcd" name="TFMT5_ASTC_12x10"/>
+ <value value="0xce" name="TFMT5_ASTC_12x12"/>
+
+ <value value="0xff" name="TFMT5_NONE"/>
+</enum>
+
+<enum name="a5xx_depth_format">
+ <value name="DEPTH5_NONE" value="0"/>
+ <value name="DEPTH5_16" value="1"/>
+ <value name="DEPTH5_24_8" value="2"/>
+ <value name="DEPTH5_32" value="4"/>
+</enum>
+
+<enum name="a5xx_blit_buf">
+ <value value="0" name="BLIT_MRT0"/>
+ <value value="1" name="BLIT_MRT1"/>
+ <value value="2" name="BLIT_MRT2"/>
+ <value value="3" name="BLIT_MRT3"/>
+ <value value="4" name="BLIT_MRT4"/>
+ <value value="5" name="BLIT_MRT5"/>
+ <value value="6" name="BLIT_MRT6"/>
+ <value value="7" name="BLIT_MRT7"/>
+ <value value="8" name="BLIT_ZS"/> <!-- depth or combined depth+stencil -->
+ <value value="9" name="BLIT_S"/> <!-- separate stencil -->
+</enum>
+
+<!-- see comment in a4xx.xml about script to extract countables from test-perf output -->
+<enum name="a5xx_cp_perfcounter_select">
+ <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
+ <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
+ <value value="2" name="PERF_CP_BUSY_CYCLES"/>
+ <value value="3" name="PERF_CP_PFP_IDLE"/>
+ <value value="4" name="PERF_CP_PFP_BUSY_WORKING"/>
+ <value value="5" name="PERF_CP_PFP_STALL_CYCLES_ANY"/>
+ <value value="6" name="PERF_CP_PFP_STARVE_CYCLES_ANY"/>
+ <value value="7" name="PERF_CP_PFP_ICACHE_MISS"/>
+ <value value="8" name="PERF_CP_PFP_ICACHE_HIT"/>
+ <value value="9" name="PERF_CP_PFP_MATCH_PM4_PKT_PROFILE"/>
+ <value value="10" name="PERF_CP_ME_BUSY_WORKING"/>
+ <value value="11" name="PERF_CP_ME_IDLE"/>
+ <value value="12" name="PERF_CP_ME_STARVE_CYCLES_ANY"/>
+ <value value="13" name="PERF_CP_ME_FIFO_EMPTY_PFP_IDLE"/>
+ <value value="14" name="PERF_CP_ME_FIFO_EMPTY_PFP_BUSY"/>
+ <value value="15" name="PERF_CP_ME_FIFO_FULL_ME_BUSY"/>
+ <value value="16" name="PERF_CP_ME_FIFO_FULL_ME_NON_WORKING"/>
+ <value value="17" name="PERF_CP_ME_STALL_CYCLES_ANY"/>
+ <value value="18" name="PERF_CP_ME_ICACHE_MISS"/>
+ <value value="19" name="PERF_CP_ME_ICACHE_HIT"/>
+ <value value="20" name="PERF_CP_NUM_PREEMPTIONS"/>
+ <value value="21" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
+ <value value="22" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
+ <value value="23" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
+ <value value="24" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
+ <value value="25" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
+ <value value="26" name="PERF_CP_MODE_SWITCH"/>
+ <value value="27" name="PERF_CP_ZPASS_DONE"/>
+ <value value="28" name="PERF_CP_CONTEXT_DONE"/>
+ <value value="29" name="PERF_CP_CACHE_FLUSH"/>
+ <value value="30" name="PERF_CP_LONG_PREEMPTIONS"/>
+</enum>
+
+<enum name="a5xx_rbbm_perfcounter_select">
+ <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
+ <value value="1" name="PERF_RBBM_ALWAYS_ON"/>
+ <value value="2" name="PERF_RBBM_TSE_BUSY"/>
+ <value value="3" name="PERF_RBBM_RAS_BUSY"/>
+ <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
+ <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
+ <value value="6" name="PERF_RBBM_STATUS_MASKED"/>
+ <value value="7" name="PERF_RBBM_COM_BUSY"/>
+ <value value="8" name="PERF_RBBM_DCOM_BUSY"/>
+ <value value="9" name="PERF_RBBM_VBIF_BUSY"/>
+ <value value="10" name="PERF_RBBM_VSC_BUSY"/>
+ <value value="11" name="PERF_RBBM_TESS_BUSY"/>
+ <value value="12" name="PERF_RBBM_UCHE_BUSY"/>
+ <value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
+</enum>
+
+<enum name="a5xx_pc_perfcounter_select">
+ <value value="0" name="PERF_PC_BUSY_CYCLES"/>
+ <value value="1" name="PERF_PC_WORKING_CYCLES"/>
+ <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
+ <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
+ <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
+ <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
+ <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
+ <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
+ <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
+ <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
+ <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
+ <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
+ <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
+ <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
+ <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
+ <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
+ <value value="16" name="PERF_PC_INSTANCES"/>
+ <value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
+ <value value="18" name="PERF_PC_DEAD_PRIM"/>
+ <value value="19" name="PERF_PC_LIVE_PRIM"/>
+ <value value="20" name="PERF_PC_VERTEX_HITS"/>
+ <value value="21" name="PERF_PC_IA_VERTICES"/>
+ <value value="22" name="PERF_PC_IA_PRIMITIVES"/>
+ <value value="23" name="PERF_PC_GS_PRIMITIVES"/>
+ <value value="24" name="PERF_PC_HS_INVOCATIONS"/>
+ <value value="25" name="PERF_PC_DS_INVOCATIONS"/>
+ <value value="26" name="PERF_PC_VS_INVOCATIONS"/>
+ <value value="27" name="PERF_PC_GS_INVOCATIONS"/>
+ <value value="28" name="PERF_PC_DS_PRIMITIVES"/>
+ <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
+ <value value="30" name="PERF_PC_3D_DRAWCALLS"/>
+ <value value="31" name="PERF_PC_2D_DRAWCALLS"/>
+ <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
+ <value value="33" name="PERF_TESS_BUSY_CYCLES"/>
+ <value value="34" name="PERF_TESS_WORKING_CYCLES"/>
+ <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
+ <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
+</enum>
+
+<enum name="a5xx_vfd_perfcounter_select">
+ <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
+ <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
+ <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
+ <value value="3" name="PERF_VFD_STALL_CYCLES_MISS_VB"/>
+ <value value="4" name="PERF_VFD_STALL_CYCLES_MISS_Q"/>
+ <value value="5" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
+ <value value="6" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
+ <value value="7" name="PERF_VFD_STALL_CYCLES_VFDP_VB"/>
+ <value value="8" name="PERF_VFD_STALL_CYCLES_VFDP_Q"/>
+ <value value="9" name="PERF_VFD_DECODER_PACKER_STALL"/>
+ <value value="10" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
+ <value value="11" name="PERF_VFD_RBUFFER_FULL"/>
+ <value value="12" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
+ <value value="13" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
+ <value value="14" name="PERF_VFD_NUM_ATTRIBUTES"/>
+ <value value="15" name="PERF_VFD_INSTRUCTIONS"/>
+ <value value="16" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
+ <value value="17" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
+ <value value="18" name="PERF_VFD_MODE_0_FIBERS"/>
+ <value value="19" name="PERF_VFD_MODE_1_FIBERS"/>
+ <value value="20" name="PERF_VFD_MODE_2_FIBERS"/>
+ <value value="21" name="PERF_VFD_MODE_3_FIBERS"/>
+ <value value="22" name="PERF_VFD_MODE_4_FIBERS"/>
+ <value value="23" name="PERF_VFD_TOTAL_VERTICES"/>
+ <value value="24" name="PERF_VFD_NUM_ATTR_MISS"/>
+ <value value="25" name="PERF_VFD_1_BURST_REQ"/>
+ <value value="26" name="PERF_VFDP_STALL_CYCLES_VFD"/>
+ <value value="27" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
+ <value value="28" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
+ <value value="29" name="PERF_VFDP_STARVE_CYCLES_PC"/>
+ <value value="30" name="PERF_VFDP_VS_STAGE_32_WAVES"/>
+</enum>
+
+<enum name="a5xx_hlsq_perfcounter_select">
+ <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
+ <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
+ <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
+ <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
+ <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
+ <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
+ <value value="6" name="PERF_HLSQ_FS_STAGE_32_WAVES"/>
+ <value value="7" name="PERF_HLSQ_FS_STAGE_64_WAVES"/>
+ <value value="8" name="PERF_HLSQ_QUADS"/>
+ <value value="9" name="PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE"/>
+ <value value="10" name="PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE"/>
+ <value value="11" name="PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE"/>
+ <value value="12" name="PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE"/>
+ <value value="13" name="PERF_HLSQ_CS_INVOCATIONS"/>
+ <value value="14" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
+</enum>
+
+<enum name="a5xx_vpc_perfcounter_select">
+ <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
+ <value value="1" name="PERF_VPC_WORKING_CYCLES"/>
+ <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
+ <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
+ <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
+ <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
+ <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
+ <value value="7" name="PERF_VPC_POS_EXPORT_STALL_CYCLES"/>
+ <value value="8" name="PERF_VPC_STARVE_CYCLES_SP"/>
+ <value value="9" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
+ <value value="10" name="PERF_VPC_PC_PRIMITIVES"/>
+ <value value="11" name="PERF_VPC_SP_COMPONENTS"/>
+ <value value="12" name="PERF_VPC_SP_LM_PRIMITIVES"/>
+ <value value="13" name="PERF_VPC_SP_LM_COMPONENTS"/>
+ <value value="14" name="PERF_VPC_SP_LM_DWORDS"/>
+ <value value="15" name="PERF_VPC_STREAMOUT_COMPONENTS"/>
+ <value value="16" name="PERF_VPC_GRANT_PHASES"/>
+</enum>
+
+<enum name="a5xx_tse_perfcounter_select">
+ <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
+ <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
+ <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
+ <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
+ <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
+ <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
+ <value value="6" name="PERF_TSE_INPUT_PRIM"/>
+ <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
+ <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
+ <value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
+ <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
+ <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
+ <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
+ <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
+ <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
+ <value value="15" name="PERF_TSE_CINVOCATION"/>
+ <value value="16" name="PERF_TSE_CPRIMITIVES"/>
+ <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
+ <value value="18" name="PERF_TSE_2D_ALIVE_CLCLES"/>
+</enum>
+
+<enum name="a5xx_ras_perfcounter_select">
+ <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
+ <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
+ <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
+ <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
+ <value value="4" name="PERF_RAS_SUPER_TILES"/>
+ <value value="5" name="PERF_RAS_8X4_TILES"/>
+ <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
+ <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
+ <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
+ <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
+</enum>
+
+<enum name="a5xx_lrz_perfcounter_select">
+ <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
+ <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
+ <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
+ <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
+ <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
+ <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
+ <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
+ <value value="7" name="PERF_LRZ_LRZ_READ"/>
+ <value value="8" name="PERF_LRZ_LRZ_WRITE"/>
+ <value value="9" name="PERF_LRZ_READ_LATENCY"/>
+ <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
+ <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
+ <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
+ <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
+ <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
+ <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
+ <value value="16" name="PERF_LRZ_TILE_KILLED"/>
+ <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
+ <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
+</enum>
+
+<enum name="a5xx_uche_perfcounter_select">
+ <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
+ <value value="1" name="PERF_UCHE_STALL_CYCLES_VBIF"/>
+ <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
+ <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
+ <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
+ <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
+ <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
+ <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
+ <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
+ <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
+ <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
+ <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
+ <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
+ <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
+ <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
+ <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
+ <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
+ <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
+ <value value="18" name="PERF_UCHE_EVICTS"/>
+ <value value="19" name="PERF_UCHE_BANK_REQ0"/>
+ <value value="20" name="PERF_UCHE_BANK_REQ1"/>
+ <value value="21" name="PERF_UCHE_BANK_REQ2"/>
+ <value value="22" name="PERF_UCHE_BANK_REQ3"/>
+ <value value="23" name="PERF_UCHE_BANK_REQ4"/>
+ <value value="24" name="PERF_UCHE_BANK_REQ5"/>
+ <value value="25" name="PERF_UCHE_BANK_REQ6"/>
+ <value value="26" name="PERF_UCHE_BANK_REQ7"/>
+ <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
+ <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
+ <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
+ <value value="30" name="PERF_UCHE_FLAG_COUNT"/>
+</enum>
+
+<enum name="a5xx_tp_perfcounter_select">
+ <value value="0" name="PERF_TP_BUSY_CYCLES"/>
+ <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
+ <value value="2" name="PERF_TP_LATENCY_CYCLES"/>
+ <value value="3" name="PERF_TP_LATENCY_TRANS"/>
+ <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
+ <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
+ <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
+ <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
+ <value value="8" name="PERF_TP_SP_TP_TRANS"/>
+ <value value="9" name="PERF_TP_TP_SP_TRANS"/>
+ <value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
+ <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
+ <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
+ <value value="13" name="PERF_TP_QUADS_RECEIVED"/>
+ <value value="14" name="PERF_TP_QUADS_OFFSET"/>
+ <value value="15" name="PERF_TP_QUADS_SHADOW"/>
+ <value value="16" name="PERF_TP_QUADS_ARRAY"/>
+ <value value="17" name="PERF_TP_QUADS_GRADIENT"/>
+ <value value="18" name="PERF_TP_QUADS_1D"/>
+ <value value="19" name="PERF_TP_QUADS_2D"/>
+ <value value="20" name="PERF_TP_QUADS_BUFFER"/>
+ <value value="21" name="PERF_TP_QUADS_3D"/>
+ <value value="22" name="PERF_TP_QUADS_CUBE"/>
+ <value value="23" name="PERF_TP_STATE_CACHE_REQUESTS"/>
+ <value value="24" name="PERF_TP_STATE_CACHE_MISSES"/>
+ <value value="25" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
+ <value value="26" name="PERF_TP_BINDLESS_STATE_CACHE_REQUESTS"/>
+ <value value="27" name="PERF_TP_BINDLESS_STATE_CACHE_MISSES"/>
+ <value value="28" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
+ <value value="29" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
+ <value value="30" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
+ <value value="31" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
+ <value value="32" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
+ <value value="33" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
+ <value value="34" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
+ <value value="35" name="PERF_TP_FLAG_CACHE_MISSES"/>
+ <value value="36" name="PERF_TP_L1_5_L2_REQUESTS"/>
+ <value value="37" name="PERF_TP_2D_OUTPUT_PIXELS"/>
+ <value value="38" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
+ <value value="39" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
+ <value value="40" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
+ <value value="41" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
+</enum>
+
+<enum name="a5xx_sp_perfcounter_select">
+ <value value="0" name="PERF_SP_BUSY_CYCLES"/>
+ <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
+ <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
+ <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
+ <value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
+ <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
+ <value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
+ <value value="7" name="PERF_SP_SCHEDULER_NON_WORKING"/>
+ <value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
+ <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
+ <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
+ <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
+ <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
+ <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
+ <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
+ <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
+ <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
+ <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
+ <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
+ <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
+ <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
+ <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
+ <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
+ <value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
+ <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
+ <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
+ <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
+ <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
+ <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
+ <value value="29" name="PERF_SP_LM_ATOMICS"/>
+ <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
+ <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
+ <value value="32" name="PERF_SP_GM_ATOMICS"/>
+ <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
+ <value value="34" name="PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS"/>
+ <value value="35" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
+ <value value="36" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
+ <value value="37" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
+ <value value="38" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
+ <value value="39" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
+ <value value="40" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
+ <value value="41" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
+ <value value="42" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
+ <value value="43" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
+ <value value="44" name="PERF_SP_VS_INSTRUCTIONS"/>
+ <value value="45" name="PERF_SP_FS_INSTRUCTIONS"/>
+ <value value="46" name="PERF_SP_ADDR_LOCK_COUNT"/>
+ <value value="47" name="PERF_SP_UCHE_READ_TRANS"/>
+ <value value="48" name="PERF_SP_UCHE_WRITE_TRANS"/>
+ <value value="49" name="PERF_SP_EXPORT_VPC_TRANS"/>
+ <value value="50" name="PERF_SP_EXPORT_RB_TRANS"/>
+ <value value="51" name="PERF_SP_PIXELS_KILLED"/>
+ <value value="52" name="PERF_SP_ICL1_REQUESTS"/>
+ <value value="53" name="PERF_SP_ICL1_MISSES"/>
+ <value value="54" name="PERF_SP_ICL0_REQUESTS"/>
+ <value value="55" name="PERF_SP_ICL0_MISSES"/>
+ <value value="56" name="PERF_SP_HS_INSTRUCTIONS"/>
+ <value value="57" name="PERF_SP_DS_INSTRUCTIONS"/>
+ <value value="58" name="PERF_SP_GS_INSTRUCTIONS"/>
+ <value value="59" name="PERF_SP_CS_INSTRUCTIONS"/>
+ <value value="60" name="PERF_SP_GPR_READ"/>
+ <value value="61" name="PERF_SP_GPR_WRITE"/>
+ <value value="62" name="PERF_SP_LM_CH0_REQUESTS"/>
+ <value value="63" name="PERF_SP_LM_CH1_REQUESTS"/>
+ <value value="64" name="PERF_SP_LM_BANK_CONFLICTS"/>
+</enum>
+
+<enum name="a5xx_rb_perfcounter_select">
+ <value value="0" name="PERF_RB_BUSY_CYCLES"/>
+ <value value="1" name="PERF_RB_STALL_CYCLES_CCU"/>
+ <value value="2" name="PERF_RB_STALL_CYCLES_HLSQ"/>
+ <value value="3" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
+ <value value="4" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
+ <value value="5" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
+ <value value="6" name="PERF_RB_STARVE_CYCLES_SP"/>
+ <value value="7" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
+ <value value="8" name="PERF_RB_STARVE_CYCLES_CCU"/>
+ <value value="9" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
+ <value value="10" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
+ <value value="11" name="PERF_RB_Z_WORKLOAD"/>
+ <value value="12" name="PERF_RB_HLSQ_ACTIVE"/>
+ <value value="13" name="PERF_RB_Z_READ"/>
+ <value value="14" name="PERF_RB_Z_WRITE"/>
+ <value value="15" name="PERF_RB_C_READ"/>
+ <value value="16" name="PERF_RB_C_WRITE"/>
+ <value value="17" name="PERF_RB_TOTAL_PASS"/>
+ <value value="18" name="PERF_RB_Z_PASS"/>
+ <value value="19" name="PERF_RB_Z_FAIL"/>
+ <value value="20" name="PERF_RB_S_FAIL"/>
+ <value value="21" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
+ <value value="22" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
+ <value value="23" name="RB_RESERVED"/>
+ <value value="24" name="PERF_RB_2D_ALIVE_CYCLES"/>
+ <value value="25" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
+ <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
+ <value value="27" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
+ <value value="28" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
+ <value value="29" name="PERF_RB_2D_VALID_PIXELS"/>
+</enum>
+
+<enum name="a5xx_rb_samples_perfcounter_select">
+ <value value="0" name="TOTAL_SAMPLES"/>
+ <value value="1" name="ZPASS_SAMPLES"/>
+ <value value="2" name="ZFAIL_SAMPLES"/>
+ <value value="3" name="SFAIL_SAMPLES"/>
+</enum>
+
+<enum name="a5xx_vsc_perfcounter_select">
+ <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
+ <value value="1" name="PERF_VSC_WORKING_CYCLES"/>
+ <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
+ <value value="3" name="PERF_VSC_EOT_NUM"/>
+</enum>
+
+<enum name="a5xx_ccu_perfcounter_select">
+ <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
+ <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
+ <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
+ <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
+ <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
+ <value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
+ <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
+ <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
+ <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
+ <value value="9" name="PERF_CCU_GMEM_READ"/>
+ <value value="10" name="PERF_CCU_GMEM_WRITE"/>
+ <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
+ <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
+ <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
+ <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
+ <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
+ <value value="16" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
+ <value value="17" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
+ <value value="18" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
+ <value value="19" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
+ <value value="20" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
+ <value value="21" name="PERF_CCU_2D_BUSY_CYCLES"/>
+ <value value="22" name="PERF_CCU_2D_RD_REQ"/>
+ <value value="23" name="PERF_CCU_2D_WR_REQ"/>
+ <value value="24" name="PERF_CCU_2D_REORDER_STARVE_CYCLES"/>
+ <value value="25" name="PERF_CCU_2D_PIXELS"/>
+</enum>
+
+<enum name="a5xx_cmp_perfcounter_select">
+ <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_VBIF"/>
+ <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
+ <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
+ <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
+ <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
+ <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
+ <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
+ <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
+ <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
+ <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
+ <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
+ <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
+ <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
+ <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
+ <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
+ <value value="15" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
+ <value value="16" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
+ <value value="17" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
+ <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
+ <value value="19" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
+ <value value="20" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
+ <value value="21" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
+ <value value="22" name="PERF_CMPDECMP_2D_RD_DATA"/>
+ <value value="23" name="PERF_CMPDECMP_2D_WR_DATA"/>
+</enum>
+
+<enum name="a5xx_vbif_perfcounter_select">
+ <value value="0" name="AXI_READ_REQUESTS_ID_0"/>
+ <value value="1" name="AXI_READ_REQUESTS_ID_1"/>
+ <value value="2" name="AXI_READ_REQUESTS_ID_2"/>
+ <value value="3" name="AXI_READ_REQUESTS_ID_3"/>
+ <value value="4" name="AXI_READ_REQUESTS_ID_4"/>
+ <value value="5" name="AXI_READ_REQUESTS_ID_5"/>
+ <value value="6" name="AXI_READ_REQUESTS_ID_6"/>
+ <value value="7" name="AXI_READ_REQUESTS_ID_7"/>
+ <value value="8" name="AXI_READ_REQUESTS_ID_8"/>
+ <value value="9" name="AXI_READ_REQUESTS_ID_9"/>
+ <value value="10" name="AXI_READ_REQUESTS_ID_10"/>
+ <value value="11" name="AXI_READ_REQUESTS_ID_11"/>
+ <value value="12" name="AXI_READ_REQUESTS_ID_12"/>
+ <value value="13" name="AXI_READ_REQUESTS_ID_13"/>
+ <value value="14" name="AXI_READ_REQUESTS_ID_14"/>
+ <value value="15" name="AXI_READ_REQUESTS_ID_15"/>
+ <value value="16" name="AXI0_READ_REQUESTS_TOTAL"/>
+ <value value="17" name="AXI1_READ_REQUESTS_TOTAL"/>
+ <value value="18" name="AXI2_READ_REQUESTS_TOTAL"/>
+ <value value="19" name="AXI3_READ_REQUESTS_TOTAL"/>
+ <value value="20" name="AXI_READ_REQUESTS_TOTAL"/>
+ <value value="21" name="AXI_WRITE_REQUESTS_ID_0"/>
+ <value value="22" name="AXI_WRITE_REQUESTS_ID_1"/>
+ <value value="23" name="AXI_WRITE_REQUESTS_ID_2"/>
+ <value value="24" name="AXI_WRITE_REQUESTS_ID_3"/>
+ <value value="25" name="AXI_WRITE_REQUESTS_ID_4"/>
+ <value value="26" name="AXI_WRITE_REQUESTS_ID_5"/>
+ <value value="27" name="AXI_WRITE_REQUESTS_ID_6"/>
+ <value value="28" name="AXI_WRITE_REQUESTS_ID_7"/>
+ <value value="29" name="AXI_WRITE_REQUESTS_ID_8"/>
+ <value value="30" name="AXI_WRITE_REQUESTS_ID_9"/>
+ <value value="31" name="AXI_WRITE_REQUESTS_ID_10"/>
+ <value value="32" name="AXI_WRITE_REQUESTS_ID_11"/>
+ <value value="33" name="AXI_WRITE_REQUESTS_ID_12"/>
+ <value value="34" name="AXI_WRITE_REQUESTS_ID_13"/>
+ <value value="35" name="AXI_WRITE_REQUESTS_ID_14"/>
+ <value value="36" name="AXI_WRITE_REQUESTS_ID_15"/>
+ <value value="37" name="AXI0_WRITE_REQUESTS_TOTAL"/>
+ <value value="38" name="AXI1_WRITE_REQUESTS_TOTAL"/>
+ <value value="39" name="AXI2_WRITE_REQUESTS_TOTAL"/>
+ <value value="40" name="AXI3_WRITE_REQUESTS_TOTAL"/>
+ <value value="41" name="AXI_WRITE_REQUESTS_TOTAL"/>
+ <value value="42" name="AXI_TOTAL_REQUESTS"/>
+ <value value="43" name="AXI_READ_DATA_BEATS_ID_0"/>
+ <value value="44" name="AXI_READ_DATA_BEATS_ID_1"/>
+ <value value="45" name="AXI_READ_DATA_BEATS_ID_2"/>
+ <value value="46" name="AXI_READ_DATA_BEATS_ID_3"/>
+ <value value="47" name="AXI_READ_DATA_BEATS_ID_4"/>
+ <value value="48" name="AXI_READ_DATA_BEATS_ID_5"/>
+ <value value="49" name="AXI_READ_DATA_BEATS_ID_6"/>
+ <value value="50" name="AXI_READ_DATA_BEATS_ID_7"/>
+ <value value="51" name="AXI_READ_DATA_BEATS_ID_8"/>
+ <value value="52" name="AXI_READ_DATA_BEATS_ID_9"/>
+ <value value="53" name="AXI_READ_DATA_BEATS_ID_10"/>
+ <value value="54" name="AXI_READ_DATA_BEATS_ID_11"/>
+ <value value="55" name="AXI_READ_DATA_BEATS_ID_12"/>
+ <value value="56" name="AXI_READ_DATA_BEATS_ID_13"/>
+ <value value="57" name="AXI_READ_DATA_BEATS_ID_14"/>
+ <value value="58" name="AXI_READ_DATA_BEATS_ID_15"/>
+ <value value="59" name="AXI0_READ_DATA_BEATS_TOTAL"/>
+ <value value="60" name="AXI1_READ_DATA_BEATS_TOTAL"/>
+ <value value="61" name="AXI2_READ_DATA_BEATS_TOTAL"/>
+ <value value="62" name="AXI3_READ_DATA_BEATS_TOTAL"/>
+ <value value="63" name="AXI_READ_DATA_BEATS_TOTAL"/>
+ <value value="64" name="AXI_WRITE_DATA_BEATS_ID_0"/>
+ <value value="65" name="AXI_WRITE_DATA_BEATS_ID_1"/>
+ <value value="66" name="AXI_WRITE_DATA_BEATS_ID_2"/>
+ <value value="67" name="AXI_WRITE_DATA_BEATS_ID_3"/>
+ <value value="68" name="AXI_WRITE_DATA_BEATS_ID_4"/>
+ <value value="69" name="AXI_WRITE_DATA_BEATS_ID_5"/>
+ <value value="70" name="AXI_WRITE_DATA_BEATS_ID_6"/>
+ <value value="71" name="AXI_WRITE_DATA_BEATS_ID_7"/>
+ <value value="72" name="AXI_WRITE_DATA_BEATS_ID_8"/>
+ <value value="73" name="AXI_WRITE_DATA_BEATS_ID_9"/>
+ <value value="74" name="AXI_WRITE_DATA_BEATS_ID_10"/>
+ <value value="75" name="AXI_WRITE_DATA_BEATS_ID_11"/>
+ <value value="76" name="AXI_WRITE_DATA_BEATS_ID_12"/>
+ <value value="77" name="AXI_WRITE_DATA_BEATS_ID_13"/>
+ <value value="78" name="AXI_WRITE_DATA_BEATS_ID_14"/>
+ <value value="79" name="AXI_WRITE_DATA_BEATS_ID_15"/>
+ <value value="80" name="AXI0_WRITE_DATA_BEATS_TOTAL"/>
+ <value value="81" name="AXI1_WRITE_DATA_BEATS_TOTAL"/>
+ <value value="82" name="AXI2_WRITE_DATA_BEATS_TOTAL"/>
+ <value value="83" name="AXI3_WRITE_DATA_BEATS_TOTAL"/>
+ <value value="84" name="AXI_WRITE_DATA_BEATS_TOTAL"/>
+ <value value="85" name="AXI_DATA_BEATS_TOTAL"/>
+</enum>
+
+<domain name="A5XX" width="32">
+ <bitset name="A5XX_INT0">
+ <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
+ <bitfield name="RBBM_AHB_ERROR" pos="1" type="boolean"/>
+ <bitfield name="RBBM_TRANSFER_TIMEOUT" pos="2" type="boolean"/>
+ <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3" type="boolean"/>
+ <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4" type="boolean"/>
+ <bitfield name="RBBM_ETS_MS_TIMEOUT" pos="5" type="boolean"/>
+ <bitfield name="RBBM_ATB_ASYNC_OVERFLOW" pos="6" type="boolean"/>
+ <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
+ <bitfield name="CP_SW" pos="8" type="boolean"/>
+ <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
+ <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
+ <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
+ <bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
+ <bitfield name="CP_IB2" pos="13" type="boolean"/>
+ <bitfield name="CP_IB1" pos="14" type="boolean"/>
+ <bitfield name="CP_RB" pos="15" type="boolean"/>
+ <bitfield name="CP_UNUSED_1" pos="16" type="boolean"/>
+ <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
+ <bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
+ <bitfield name="UNKNOWN_1" pos="19" type="boolean"/>
+ <bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
+ <bitfield name="UNUSED_2" pos="21" type="boolean"/>
+ <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
+ <bitfield name="MISC_HANG_DETECT" pos="23" type="boolean"/>
+ <bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
+ <bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
+ <bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
+ <bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
+ <bitfield name="GPMU_VOLTAGE_DROOP" pos="28" type="boolean"/>
+ <bitfield name="GPMU_FIRMWARE" pos="29" type="boolean"/>
+ <bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
+ <bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
+ </bitset>
+
+ <!-- CP Interrupt bits -->
+ <bitset name="A5XX_CP_INT">
+ <bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>
+ <bitfield name="CP_RESERVED_BIT_ERROR" pos="1" type="boolean"/>
+ <bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/>
+ <bitfield name="CP_DMA_ERROR" pos="3" type="boolean"/>
+ <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/>
+ <bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/>
+ </bitset>
+
+ <!-- CP registers -->
+ <reg32 offset="0x0800" name="CP_RB_BASE"/>
+ <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
+ <reg32 offset="0x0802" name="CP_RB_CNTL"/>
+ <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
+ <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
+ <reg32 offset="0x0806" name="CP_RB_RPTR"/>
+ <reg32 offset="0x0807" name="CP_RB_WPTR"/>
+ <reg32 offset="0x0808" name="CP_PFP_STAT_ADDR"/>
+ <reg32 offset="0x0809" name="CP_PFP_STAT_DATA"/>
+ <reg32 offset="0x080b" name="CP_DRAW_STATE_ADDR"/>
+ <reg32 offset="0x080c" name="CP_DRAW_STATE_DATA"/>
+ <reg32 offset="0x080d" name="CP_ME_NRT_ADDR_LO"/>
+ <reg32 offset="0x080e" name="CP_ME_NRT_ADDR_HI"/>
+ <reg32 offset="0x0810" name="CP_ME_NRT_DATA"/>
+ <reg32 offset="0x0817" name="CP_CRASH_SCRIPT_BASE_LO"/>
+ <reg32 offset="0x0818" name="CP_CRASH_SCRIPT_BASE_HI"/>
+ <reg32 offset="0x0819" name="CP_CRASH_DUMP_CNTL"/>
+ <reg32 offset="0x081a" name="CP_ME_STAT_ADDR"/>
+ <reg32 offset="0x081f" name="CP_ROQ_THRESHOLDS_1"/>
+ <reg32 offset="0x0820" name="CP_ROQ_THRESHOLDS_2"/>
+ <reg32 offset="0x0821" name="CP_ROQ_DBG_ADDR"/>
+ <reg32 offset="0x0822" name="CP_ROQ_DBG_DATA"/>
+ <reg32 offset="0x0823" name="CP_MEQ_DBG_ADDR"/>
+ <reg32 offset="0x0824" name="CP_MEQ_DBG_DATA"/>
+ <reg32 offset="0x0825" name="CP_MEQ_THRESHOLDS"/>
+ <reg32 offset="0x0826" name="CP_MERCIU_SIZE"/>
+ <reg32 offset="0x0827" name="CP_MERCIU_DBG_ADDR"/>
+ <reg32 offset="0x0828" name="CP_MERCIU_DBG_DATA_1"/>
+ <reg32 offset="0x0829" name="CP_MERCIU_DBG_DATA_2"/>
+ <reg32 offset="0x082a" name="CP_PFP_UCODE_DBG_ADDR"/>
+ <reg32 offset="0x082b" name="CP_PFP_UCODE_DBG_DATA"/>
+ <reg32 offset="0x082f" name="CP_ME_UCODE_DBG_ADDR"/>
+ <reg32 offset="0x0830" name="CP_ME_UCODE_DBG_DATA"/>
+ <reg32 offset="0x0831" name="CP_CNTL"/>
+ <reg32 offset="0x0832" name="CP_PFP_ME_CNTL"/>
+ <reg32 offset="0x0833" name="CP_CHICKEN_DBG"/>
+ <reg32 offset="0x0835" name="CP_PFP_INSTR_BASE_LO"/>
+ <reg32 offset="0x0836" name="CP_PFP_INSTR_BASE_HI"/>
+ <reg32 offset="0x0838" name="CP_ME_INSTR_BASE_LO"/>
+ <reg32 offset="0x0839" name="CP_ME_INSTR_BASE_HI"/>
+ <reg32 offset="0x083b" name="CP_CONTEXT_SWITCH_CNTL"/>
+ <reg32 offset="0x083c" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_LO"/>
+ <reg32 offset="0x083d" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_HI"/>
+ <reg32 offset="0x083e" name="CP_CONTEXT_SWITCH_SAVE_ADDR_LO"/>
+ <reg32 offset="0x083f" name="CP_CONTEXT_SWITCH_SAVE_ADDR_HI"/>
+ <reg32 offset="0x0840" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
+ <reg32 offset="0x0841" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
+ <reg32 offset="0x0860" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0x0b14" name="CP_ME_STAT_DATA"/>
+ <reg32 offset="0x0b15" name="CP_WFI_PEND_CTR"/>
+ <reg32 offset="0x0b18" name="CP_INTERRUPT_STATUS"/>
+ <reg32 offset="0x0b1a" name="CP_HW_FAULT"/>
+ <reg32 offset="0x0b1c" name="CP_PROTECT_STATUS"/>
+ <reg32 offset="0x0b1f" name="CP_IB1_BASE"/>
+ <reg32 offset="0x0b20" name="CP_IB1_BASE_HI"/>
+ <reg32 offset="0x0b21" name="CP_IB1_BUFSZ"/>
+ <reg32 offset="0x0b22" name="CP_IB2_BASE"/>
+ <reg32 offset="0x0b23" name="CP_IB2_BASE_HI"/>
+ <reg32 offset="0x0b24" name="CP_IB2_BUFSZ"/>
+ <array offset="0x0b78" name="CP_SCRATCH" stride="1" length="8">
+ <reg32 offset="0x0" name="REG" type="uint"/>
+ </array>
+ <array offset="0x0880" name="CP_PROTECT" stride="1" length="32">
+ <reg32 offset="0x0" name="REG" type="adreno_cp_protect"/>
+ </array>
+ <reg32 offset="0x08a0" name="CP_PROTECT_CNTL"/>
+ <reg32 offset="0x0b1b" name="CP_AHB_FAULT"/>
+ <reg32 offset="0x0bb0" name="CP_PERFCTR_CP_SEL_0" type="a5xx_cp_perfcounter_select"/>
+ <reg32 offset="0x0bb1" name="CP_PERFCTR_CP_SEL_1" type="a5xx_cp_perfcounter_select"/>
+ <reg32 offset="0x0bb2" name="CP_PERFCTR_CP_SEL_2" type="a5xx_cp_perfcounter_select"/>
+ <reg32 offset="0x0bb3" name="CP_PERFCTR_CP_SEL_3" type="a5xx_cp_perfcounter_select"/>
+ <reg32 offset="0x0bb4" name="CP_PERFCTR_CP_SEL_4" type="a5xx_cp_perfcounter_select"/>
+ <reg32 offset="0x0bb5" name="CP_PERFCTR_CP_SEL_5" type="a5xx_cp_perfcounter_select"/>
+ <reg32 offset="0x0bb6" name="CP_PERFCTR_CP_SEL_6" type="a5xx_cp_perfcounter_select"/>
+ <reg32 offset="0x0bb7" name="CP_PERFCTR_CP_SEL_7" type="a5xx_cp_perfcounter_select"/>
+ <reg32 offset="0x0bc1" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0x0bba" name="CP_POWERCTR_CP_SEL_0"/>
+ <reg32 offset="0x0bbb" name="CP_POWERCTR_CP_SEL_1"/>
+ <reg32 offset="0x0bbc" name="CP_POWERCTR_CP_SEL_2"/>
+ <reg32 offset="0x0bbd" name="CP_POWERCTR_CP_SEL_3"/>
+
+ <!-- RBBM registers -->
+ <reg32 offset="0x0004" name="RBBM_CFG_DBGBUS_SEL_A"/>
+ <reg32 offset="0x0005" name="RBBM_CFG_DBGBUS_SEL_B"/>
+ <reg32 offset="0x0006" name="RBBM_CFG_DBGBUS_SEL_C"/>
+ <reg32 offset="0x0007" name="RBBM_CFG_DBGBUS_SEL_D"/>
+<!--
+#define A5XX_RBBM_CFG_DBGBUS_SEL_PING_INDEX_SHIFT 0x0
+#define A5XX_RBBM_CFG_DBGBUS_SEL_PING_BLK_SEL_SHIFT 0x8
+#define A5XX_RBBM_CFG_DBGBUS_SEL_PONG_INDEX_SHIFT 0x10
+#define A5XX_RBBM_CFG_DBGBUS_SEL_PONG_BLK_SEL_SHIFT 0x18
+ -->
+ <reg32 offset="0x0008" name="RBBM_CFG_DBGBUS_CNTLT"/>
+ <reg32 offset="0x0009" name="RBBM_CFG_DBGBUS_CNTLM"/>
+ <reg32 offset="0x0018" name="RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT"/>
+ <reg32 offset="0x000a" name="RBBM_CFG_DBGBUS_OPL"/>
+ <reg32 offset="0x000b" name="RBBM_CFG_DBGBUS_OPE"/>
+ <reg32 offset="0x000c" name="RBBM_CFG_DBGBUS_IVTL_0"/>
+ <reg32 offset="0x000d" name="RBBM_CFG_DBGBUS_IVTL_1"/>
+ <reg32 offset="0x000e" name="RBBM_CFG_DBGBUS_IVTL_2"/>
+ <reg32 offset="0x000f" name="RBBM_CFG_DBGBUS_IVTL_3"/>
+ <reg32 offset="0x0010" name="RBBM_CFG_DBGBUS_MASKL_0"/>
+ <reg32 offset="0x0011" name="RBBM_CFG_DBGBUS_MASKL_1"/>
+ <reg32 offset="0x0012" name="RBBM_CFG_DBGBUS_MASKL_2"/>
+ <reg32 offset="0x0013" name="RBBM_CFG_DBGBUS_MASKL_3"/>
+ <reg32 offset="0x0014" name="RBBM_CFG_DBGBUS_BYTEL_0"/>
+ <reg32 offset="0x0015" name="RBBM_CFG_DBGBUS_BYTEL_1"/>
+ <reg32 offset="0x0016" name="RBBM_CFG_DBGBUS_IVTE_0"/>
+ <reg32 offset="0x0017" name="RBBM_CFG_DBGBUS_IVTE_1"/>
+ <reg32 offset="0x0018" name="RBBM_CFG_DBGBUS_IVTE_2"/>
+ <reg32 offset="0x0019" name="RBBM_CFG_DBGBUS_IVTE_3"/>
+ <reg32 offset="0x001a" name="RBBM_CFG_DBGBUS_MASKE_0"/>
+ <reg32 offset="0x001b" name="RBBM_CFG_DBGBUS_MASKE_1"/>
+ <reg32 offset="0x001c" name="RBBM_CFG_DBGBUS_MASKE_2"/>
+ <reg32 offset="0x001d" name="RBBM_CFG_DBGBUS_MASKE_3"/>
+ <reg32 offset="0x001e" name="RBBM_CFG_DBGBUS_NIBBLEE"/>
+ <reg32 offset="0x001f" name="RBBM_CFG_DBGBUS_PTRC0"/>
+ <reg32 offset="0x0020" name="RBBM_CFG_DBGBUS_PTRC1"/>
+ <reg32 offset="0x0021" name="RBBM_CFG_DBGBUS_LOADREG"/>
+ <reg32 offset="0x0022" name="RBBM_CFG_DBGBUS_IDX"/>
+ <reg32 offset="0x0023" name="RBBM_CFG_DBGBUS_CLRC"/>
+ <reg32 offset="0x0024" name="RBBM_CFG_DBGBUS_LOADIVT"/>
+ <reg32 offset="0x002f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
+ <reg32 offset="0x0037" name="RBBM_INT_CLEAR_CMD"/>
+ <reg32 offset="0x0038" name="RBBM_INT_0_MASK">
+ <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
+ <bitfield name="RBBM_AHB_ERROR" pos="1" type="boolean"/>
+ <bitfield name="RBBM_TRANSFER_TIMEOUT" pos="2" type="boolean"/>
+ <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3" type="boolean"/>
+ <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4" type="boolean"/>
+ <bitfield name="RBBM_ETS_MS_TIMEOUT" pos="5" type="boolean"/>
+ <bitfield name="RBBM_ATB_ASYNC_OVERFLOW" pos="6" type="boolean"/>
+ <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
+ <bitfield name="CP_SW" pos="8" type="boolean"/>
+ <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
+ <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
+ <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
+ <bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
+ <bitfield name="CP_IB2" pos="13" type="boolean"/>
+ <bitfield name="CP_IB1" pos="14" type="boolean"/>
+ <bitfield name="CP_RB" pos="15" type="boolean"/>
+ <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
+ <bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
+ <bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
+ <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
+ <bitfield name="MISC_HANG_DETECT" pos="23" type="boolean"/>
+ <bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
+ <bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
+ <bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
+ <bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
+ <bitfield name="GPMU_VOLTAGE_DROOP" pos="28" type="boolean"/>
+ <bitfield name="GPMU_FIRMWARE" pos="29" type="boolean"/>
+ <bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
+ <bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x003f" name="RBBM_AHB_DBG_CNTL"/>
+ <reg32 offset="0x0041" name="RBBM_EXT_VBIF_DBG_CNTL"/>
+ <reg32 offset="0x0043" name="RBBM_SW_RESET_CMD"/>
+ <reg32 offset="0x0045" name="RBBM_BLOCK_SW_RESET_CMD"/>
+ <reg32 offset="0x0046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
+ <reg32 offset="0x0048" name="RBBM_DBG_LO_HI_GPIO"/>
+ <reg32 offset="0x0049" name="RBBM_EXT_TRACE_BUS_CNTL"/>
+ <reg32 offset="0x004a" name="RBBM_CLOCK_CNTL_TP0"/>
+ <reg32 offset="0x004b" name="RBBM_CLOCK_CNTL_TP1"/>
+ <reg32 offset="0x004c" name="RBBM_CLOCK_CNTL_TP2"/>
+ <reg32 offset="0x004d" name="RBBM_CLOCK_CNTL_TP3"/>
+ <reg32 offset="0x004e" name="RBBM_CLOCK_CNTL2_TP0"/>
+ <reg32 offset="0x004f" name="RBBM_CLOCK_CNTL2_TP1"/>
+ <reg32 offset="0x0050" name="RBBM_CLOCK_CNTL2_TP2"/>
+ <reg32 offset="0x0051" name="RBBM_CLOCK_CNTL2_TP3"/>
+ <reg32 offset="0x0052" name="RBBM_CLOCK_CNTL3_TP0"/>
+ <reg32 offset="0x0053" name="RBBM_CLOCK_CNTL3_TP1"/>
+ <reg32 offset="0x0054" name="RBBM_CLOCK_CNTL3_TP2"/>
+ <reg32 offset="0x0055" name="RBBM_CLOCK_CNTL3_TP3"/>
+ <reg32 offset="0x0059" name="RBBM_READ_AHB_THROUGH_DBG"/>
+ <reg32 offset="0x005a" name="RBBM_CLOCK_CNTL_UCHE"/>
+ <reg32 offset="0x005b" name="RBBM_CLOCK_CNTL2_UCHE"/>
+ <reg32 offset="0x005c" name="RBBM_CLOCK_CNTL3_UCHE"/>
+ <reg32 offset="0x005d" name="RBBM_CLOCK_CNTL4_UCHE"/>
+ <reg32 offset="0x005e" name="RBBM_CLOCK_HYST_UCHE"/>
+ <reg32 offset="0x005f" name="RBBM_CLOCK_DELAY_UCHE"/>
+ <reg32 offset="0x0060" name="RBBM_CLOCK_MODE_GPC"/>
+ <reg32 offset="0x0061" name="RBBM_CLOCK_DELAY_GPC"/>
+ <reg32 offset="0x0062" name="RBBM_CLOCK_HYST_GPC"/>
+ <reg32 offset="0x0063" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
+ <reg32 offset="0x0064" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
+ <reg32 offset="0x0065" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
+ <reg32 offset="0x0066" name="RBBM_CLOCK_DELAY_HLSQ"/>
+ <reg32 offset="0x0067" name="RBBM_CLOCK_CNTL"/>
+ <reg32 offset="0x0068" name="RBBM_CLOCK_CNTL_SP0"/>
+ <reg32 offset="0x0069" name="RBBM_CLOCK_CNTL_SP1"/>
+ <reg32 offset="0x006a" name="RBBM_CLOCK_CNTL_SP2"/>
+ <reg32 offset="0x006b" name="RBBM_CLOCK_CNTL_SP3"/>
+ <reg32 offset="0x006c" name="RBBM_CLOCK_CNTL2_SP0"/>
+ <reg32 offset="0x006d" name="RBBM_CLOCK_CNTL2_SP1"/>
+ <reg32 offset="0x006e" name="RBBM_CLOCK_CNTL2_SP2"/>
+ <reg32 offset="0x006f" name="RBBM_CLOCK_CNTL2_SP3"/>
+ <reg32 offset="0x0070" name="RBBM_CLOCK_HYST_SP0"/>
+ <reg32 offset="0x0071" name="RBBM_CLOCK_HYST_SP1"/>
+ <reg32 offset="0x0072" name="RBBM_CLOCK_HYST_SP2"/>
+ <reg32 offset="0x0073" name="RBBM_CLOCK_HYST_SP3"/>
+ <reg32 offset="0x0074" name="RBBM_CLOCK_DELAY_SP0"/>
+ <reg32 offset="0x0075" name="RBBM_CLOCK_DELAY_SP1"/>
+ <reg32 offset="0x0076" name="RBBM_CLOCK_DELAY_SP2"/>
+ <reg32 offset="0x0077" name="RBBM_CLOCK_DELAY_SP3"/>
+ <reg32 offset="0x0078" name="RBBM_CLOCK_CNTL_RB0"/>
+ <reg32 offset="0x0079" name="RBBM_CLOCK_CNTL_RB1"/>
+ <reg32 offset="0x007a" name="RBBM_CLOCK_CNTL_RB2"/>
+ <reg32 offset="0x007b" name="RBBM_CLOCK_CNTL_RB3"/>
+ <reg32 offset="0x007c" name="RBBM_CLOCK_CNTL2_RB0"/>
+ <reg32 offset="0x007d" name="RBBM_CLOCK_CNTL2_RB1"/>
+ <reg32 offset="0x007e" name="RBBM_CLOCK_CNTL2_RB2"/>
+ <reg32 offset="0x007f" name="RBBM_CLOCK_CNTL2_RB3"/>
+ <reg32 offset="0x0080" name="RBBM_CLOCK_HYST_RAC"/>
+ <reg32 offset="0x0081" name="RBBM_CLOCK_DELAY_RAC"/>
+ <reg32 offset="0x0082" name="RBBM_CLOCK_CNTL_CCU0"/>
+ <reg32 offset="0x0083" name="RBBM_CLOCK_CNTL_CCU1"/>
+ <reg32 offset="0x0084" name="RBBM_CLOCK_CNTL_CCU2"/>
+ <reg32 offset="0x0085" name="RBBM_CLOCK_CNTL_CCU3"/>
+ <reg32 offset="0x0086" name="RBBM_CLOCK_HYST_RB_CCU0"/>
+ <reg32 offset="0x0087" name="RBBM_CLOCK_HYST_RB_CCU1"/>
+ <reg32 offset="0x0088" name="RBBM_CLOCK_HYST_RB_CCU2"/>
+ <reg32 offset="0x0089" name="RBBM_CLOCK_HYST_RB_CCU3"/>
+ <reg32 offset="0x008a" name="RBBM_CLOCK_CNTL_RAC"/>
+ <reg32 offset="0x008b" name="RBBM_CLOCK_CNTL2_RAC"/>
+ <reg32 offset="0x008c" name="RBBM_CLOCK_DELAY_RB_CCU_L1_0"/>
+ <reg32 offset="0x008d" name="RBBM_CLOCK_DELAY_RB_CCU_L1_1"/>
+ <reg32 offset="0x008e" name="RBBM_CLOCK_DELAY_RB_CCU_L1_2"/>
+ <reg32 offset="0x008f" name="RBBM_CLOCK_DELAY_RB_CCU_L1_3"/>
+ <reg32 offset="0x0090" name="RBBM_CLOCK_HYST_VFD"/>
+ <reg32 offset="0x0091" name="RBBM_CLOCK_MODE_VFD"/>
+ <reg32 offset="0x0092" name="RBBM_CLOCK_DELAY_VFD"/>
+ <reg32 offset="0x0093" name="RBBM_AHB_CNTL0"/>
+ <reg32 offset="0x0094" name="RBBM_AHB_CNTL1"/>
+ <reg32 offset="0x0095" name="RBBM_AHB_CNTL2"/>
+ <reg32 offset="0x0096" name="RBBM_AHB_CMD"/>
+ <reg32 offset="0x009c" name="RBBM_INTERFACE_HANG_MASK_CNTL11"/>
+ <reg32 offset="0x009d" name="RBBM_INTERFACE_HANG_MASK_CNTL12"/>
+ <reg32 offset="0x009e" name="RBBM_INTERFACE_HANG_MASK_CNTL13"/>
+ <reg32 offset="0x009f" name="RBBM_INTERFACE_HANG_MASK_CNTL14"/>
+ <reg32 offset="0x00a0" name="RBBM_INTERFACE_HANG_MASK_CNTL15"/>
+ <reg32 offset="0x00a1" name="RBBM_INTERFACE_HANG_MASK_CNTL16"/>
+ <reg32 offset="0x00a2" name="RBBM_INTERFACE_HANG_MASK_CNTL17"/>
+ <reg32 offset="0x00a3" name="RBBM_INTERFACE_HANG_MASK_CNTL18"/>
+ <reg32 offset="0x00a4" name="RBBM_CLOCK_DELAY_TP0"/>
+ <reg32 offset="0x00a5" name="RBBM_CLOCK_DELAY_TP1"/>
+ <reg32 offset="0x00a6" name="RBBM_CLOCK_DELAY_TP2"/>
+ <reg32 offset="0x00a7" name="RBBM_CLOCK_DELAY_TP3"/>
+ <reg32 offset="0x00a8" name="RBBM_CLOCK_DELAY2_TP0"/>
+ <reg32 offset="0x00a9" name="RBBM_CLOCK_DELAY2_TP1"/>
+ <reg32 offset="0x00aa" name="RBBM_CLOCK_DELAY2_TP2"/>
+ <reg32 offset="0x00ab" name="RBBM_CLOCK_DELAY2_TP3"/>
+ <reg32 offset="0x00ac" name="RBBM_CLOCK_DELAY3_TP0"/>
+ <reg32 offset="0x00ad" name="RBBM_CLOCK_DELAY3_TP1"/>
+ <reg32 offset="0x00ae" name="RBBM_CLOCK_DELAY3_TP2"/>
+ <reg32 offset="0x00af" name="RBBM_CLOCK_DELAY3_TP3"/>
+ <reg32 offset="0x00b0" name="RBBM_CLOCK_HYST_TP0"/>
+ <reg32 offset="0x00b1" name="RBBM_CLOCK_HYST_TP1"/>
+ <reg32 offset="0x00b2" name="RBBM_CLOCK_HYST_TP2"/>
+ <reg32 offset="0x00b3" name="RBBM_CLOCK_HYST_TP3"/>
+ <reg32 offset="0x00b4" name="RBBM_CLOCK_HYST2_TP0"/>
+ <reg32 offset="0x00b5" name="RBBM_CLOCK_HYST2_TP1"/>
+ <reg32 offset="0x00b6" name="RBBM_CLOCK_HYST2_TP2"/>
+ <reg32 offset="0x00b7" name="RBBM_CLOCK_HYST2_TP3"/>
+ <reg32 offset="0x00b8" name="RBBM_CLOCK_HYST3_TP0"/>
+ <reg32 offset="0x00b9" name="RBBM_CLOCK_HYST3_TP1"/>
+ <reg32 offset="0x00ba" name="RBBM_CLOCK_HYST3_TP2"/>
+ <reg32 offset="0x00bb" name="RBBM_CLOCK_HYST3_TP3"/>
+ <reg32 offset="0x00c8" name="RBBM_CLOCK_CNTL_GPMU"/>
+ <reg32 offset="0x00c9" name="RBBM_CLOCK_DELAY_GPMU"/>
+ <reg32 offset="0x00ca" name="RBBM_CLOCK_HYST_GPMU"/>
+ <reg32 offset="0x03a0" name="RBBM_PERFCTR_CP_0_LO"/>
+ <reg32 offset="0x03a1" name="RBBM_PERFCTR_CP_0_HI"/>
+ <reg32 offset="0x03a2" name="RBBM_PERFCTR_CP_1_LO"/>
+ <reg32 offset="0x03a3" name="RBBM_PERFCTR_CP_1_HI"/>
+ <reg32 offset="0x03a4" name="RBBM_PERFCTR_CP_2_LO"/>
+ <reg32 offset="0x03a5" name="RBBM_PERFCTR_CP_2_HI"/>
+ <reg32 offset="0x03a6" name="RBBM_PERFCTR_CP_3_LO"/>
+ <reg32 offset="0x03a7" name="RBBM_PERFCTR_CP_3_HI"/>
+ <reg32 offset="0x03a8" name="RBBM_PERFCTR_CP_4_LO"/>
+ <reg32 offset="0x03a9" name="RBBM_PERFCTR_CP_4_HI"/>
+ <reg32 offset="0x03aa" name="RBBM_PERFCTR_CP_5_LO"/>
+ <reg32 offset="0x03ab" name="RBBM_PERFCTR_CP_5_HI"/>
+ <reg32 offset="0x03ac" name="RBBM_PERFCTR_CP_6_LO"/>
+ <reg32 offset="0x03ad" name="RBBM_PERFCTR_CP_6_HI"/>
+ <reg32 offset="0x03ae" name="RBBM_PERFCTR_CP_7_LO"/>
+ <reg32 offset="0x03af" name="RBBM_PERFCTR_CP_7_HI"/>
+ <reg32 offset="0x03b0" name="RBBM_PERFCTR_RBBM_0_LO"/>
+ <reg32 offset="0x03b1" name="RBBM_PERFCTR_RBBM_0_HI"/>
+ <reg32 offset="0x03b2" name="RBBM_PERFCTR_RBBM_1_LO"/>
+ <reg32 offset="0x03b3" name="RBBM_PERFCTR_RBBM_1_HI"/>
+ <reg32 offset="0x03b4" name="RBBM_PERFCTR_RBBM_2_LO"/>
+ <reg32 offset="0x03b5" name="RBBM_PERFCTR_RBBM_2_HI"/>
+ <reg32 offset="0x03b6" name="RBBM_PERFCTR_RBBM_3_LO"/>
+ <reg32 offset="0x03b7" name="RBBM_PERFCTR_RBBM_3_HI"/>
+ <reg32 offset="0x03b8" name="RBBM_PERFCTR_PC_0_LO"/>
+ <reg32 offset="0x03b9" name="RBBM_PERFCTR_PC_0_HI"/>
+ <reg32 offset="0x03ba" name="RBBM_PERFCTR_PC_1_LO"/>
+ <reg32 offset="0x03bb" name="RBBM_PERFCTR_PC_1_HI"/>
+ <reg32 offset="0x03bc" name="RBBM_PERFCTR_PC_2_LO"/>
+ <reg32 offset="0x03bd" name="RBBM_PERFCTR_PC_2_HI"/>
+ <reg32 offset="0x03be" name="RBBM_PERFCTR_PC_3_LO"/>
+ <reg32 offset="0x03bf" name="RBBM_PERFCTR_PC_3_HI"/>
+ <reg32 offset="0x03c0" name="RBBM_PERFCTR_PC_4_LO"/>
+ <reg32 offset="0x03c1" name="RBBM_PERFCTR_PC_4_HI"/>
+ <reg32 offset="0x03c2" name="RBBM_PERFCTR_PC_5_LO"/>
+ <reg32 offset="0x03c3" name="RBBM_PERFCTR_PC_5_HI"/>
+ <reg32 offset="0x03c4" name="RBBM_PERFCTR_PC_6_LO"/>
+ <reg32 offset="0x03c5" name="RBBM_PERFCTR_PC_6_HI"/>
+ <reg32 offset="0x03c6" name="RBBM_PERFCTR_PC_7_LO"/>
+ <reg32 offset="0x03c7" name="RBBM_PERFCTR_PC_7_HI"/>
+ <reg32 offset="0x03c8" name="RBBM_PERFCTR_VFD_0_LO"/>
+ <reg32 offset="0x03c9" name="RBBM_PERFCTR_VFD_0_HI"/>
+ <reg32 offset="0x03ca" name="RBBM_PERFCTR_VFD_1_LO"/>
+ <reg32 offset="0x03cb" name="RBBM_PERFCTR_VFD_1_HI"/>
+ <reg32 offset="0x03cc" name="RBBM_PERFCTR_VFD_2_LO"/>
+ <reg32 offset="0x03cd" name="RBBM_PERFCTR_VFD_2_HI"/>
+ <reg32 offset="0x03ce" name="RBBM_PERFCTR_VFD_3_LO"/>
+ <reg32 offset="0x03cf" name="RBBM_PERFCTR_VFD_3_HI"/>
+ <reg32 offset="0x03d0" name="RBBM_PERFCTR_VFD_4_LO"/>
+ <reg32 offset="0x03d1" name="RBBM_PERFCTR_VFD_4_HI"/>
+ <reg32 offset="0x03d2" name="RBBM_PERFCTR_VFD_5_LO"/>
+ <reg32 offset="0x03d3" name="RBBM_PERFCTR_VFD_5_HI"/>
+ <reg32 offset="0x03d4" name="RBBM_PERFCTR_VFD_6_LO"/>
+ <reg32 offset="0x03d5" name="RBBM_PERFCTR_VFD_6_HI"/>
+ <reg32 offset="0x03d6" name="RBBM_PERFCTR_VFD_7_LO"/>
+ <reg32 offset="0x03d7" name="RBBM_PERFCTR_VFD_7_HI"/>
+ <reg32 offset="0x03d8" name="RBBM_PERFCTR_HLSQ_0_LO"/>
+ <reg32 offset="0x03d9" name="RBBM_PERFCTR_HLSQ_0_HI"/>
+ <reg32 offset="0x03da" name="RBBM_PERFCTR_HLSQ_1_LO"/>
+ <reg32 offset="0x03db" name="RBBM_PERFCTR_HLSQ_1_HI"/>
+ <reg32 offset="0x03dc" name="RBBM_PERFCTR_HLSQ_2_LO"/>
+ <reg32 offset="0x03dd" name="RBBM_PERFCTR_HLSQ_2_HI"/>
+ <reg32 offset="0x03de" name="RBBM_PERFCTR_HLSQ_3_LO"/>
+ <reg32 offset="0x03df" name="RBBM_PERFCTR_HLSQ_3_HI"/>
+ <reg32 offset="0x03e0" name="RBBM_PERFCTR_HLSQ_4_LO"/>
+ <reg32 offset="0x03e1" name="RBBM_PERFCTR_HLSQ_4_HI"/>
+ <reg32 offset="0x03e2" name="RBBM_PERFCTR_HLSQ_5_LO"/>
+ <reg32 offset="0x03e3" name="RBBM_PERFCTR_HLSQ_5_HI"/>
+ <reg32 offset="0x03e4" name="RBBM_PERFCTR_HLSQ_6_LO"/>
+ <reg32 offset="0x03e5" name="RBBM_PERFCTR_HLSQ_6_HI"/>
+ <reg32 offset="0x03e6" name="RBBM_PERFCTR_HLSQ_7_LO"/>
+ <reg32 offset="0x03e7" name="RBBM_PERFCTR_HLSQ_7_HI"/>
+ <reg32 offset="0x03e8" name="RBBM_PERFCTR_VPC_0_LO"/>
+ <reg32 offset="0x03e9" name="RBBM_PERFCTR_VPC_0_HI"/>
+ <reg32 offset="0x03ea" name="RBBM_PERFCTR_VPC_1_LO"/>
+ <reg32 offset="0x03eb" name="RBBM_PERFCTR_VPC_1_HI"/>
+ <reg32 offset="0x03ec" name="RBBM_PERFCTR_VPC_2_LO"/>
+ <reg32 offset="0x03ed" name="RBBM_PERFCTR_VPC_2_HI"/>
+ <reg32 offset="0x03ee" name="RBBM_PERFCTR_VPC_3_LO"/>
+ <reg32 offset="0x03ef" name="RBBM_PERFCTR_VPC_3_HI"/>
+ <reg32 offset="0x03f0" name="RBBM_PERFCTR_CCU_0_LO"/>
+ <reg32 offset="0x03f1" name="RBBM_PERFCTR_CCU_0_HI"/>
+ <reg32 offset="0x03f2" name="RBBM_PERFCTR_CCU_1_LO"/>
+ <reg32 offset="0x03f3" name="RBBM_PERFCTR_CCU_1_HI"/>
+ <reg32 offset="0x03f4" name="RBBM_PERFCTR_CCU_2_LO"/>
+ <reg32 offset="0x03f5" name="RBBM_PERFCTR_CCU_2_HI"/>
+ <reg32 offset="0x03f6" name="RBBM_PERFCTR_CCU_3_LO"/>
+ <reg32 offset="0x03f7" name="RBBM_PERFCTR_CCU_3_HI"/>
+ <reg32 offset="0x03f8" name="RBBM_PERFCTR_TSE_0_LO"/>
+ <reg32 offset="0x03f9" name="RBBM_PERFCTR_TSE_0_HI"/>
+ <reg32 offset="0x03fa" name="RBBM_PERFCTR_TSE_1_LO"/>
+ <reg32 offset="0x03fb" name="RBBM_PERFCTR_TSE_1_HI"/>
+ <reg32 offset="0x03fc" name="RBBM_PERFCTR_TSE_2_LO"/>
+ <reg32 offset="0x03fd" name="RBBM_PERFCTR_TSE_2_HI"/>
+ <reg32 offset="0x03fe" name="RBBM_PERFCTR_TSE_3_LO"/>
+ <reg32 offset="0x03ff" name="RBBM_PERFCTR_TSE_3_HI"/>
+ <reg32 offset="0x0400" name="RBBM_PERFCTR_RAS_0_LO"/>
+ <reg32 offset="0x0401" name="RBBM_PERFCTR_RAS_0_HI"/>
+ <reg32 offset="0x0402" name="RBBM_PERFCTR_RAS_1_LO"/>
+ <reg32 offset="0x0403" name="RBBM_PERFCTR_RAS_1_HI"/>
+ <reg32 offset="0x0404" name="RBBM_PERFCTR_RAS_2_LO"/>
+ <reg32 offset="0x0405" name="RBBM_PERFCTR_RAS_2_HI"/>
+ <reg32 offset="0x0406" name="RBBM_PERFCTR_RAS_3_LO"/>
+ <reg32 offset="0x0407" name="RBBM_PERFCTR_RAS_3_HI"/>
+ <reg32 offset="0x0408" name="RBBM_PERFCTR_UCHE_0_LO"/>
+ <reg32 offset="0x0409" name="RBBM_PERFCTR_UCHE_0_HI"/>
+ <reg32 offset="0x040a" name="RBBM_PERFCTR_UCHE_1_LO"/>
+ <reg32 offset="0x040b" name="RBBM_PERFCTR_UCHE_1_HI"/>
+ <reg32 offset="0x040c" name="RBBM_PERFCTR_UCHE_2_LO"/>
+ <reg32 offset="0x040d" name="RBBM_PERFCTR_UCHE_2_HI"/>
+ <reg32 offset="0x040e" name="RBBM_PERFCTR_UCHE_3_LO"/>
+ <reg32 offset="0x040f" name="RBBM_PERFCTR_UCHE_3_HI"/>
+ <reg32 offset="0x0410" name="RBBM_PERFCTR_UCHE_4_LO"/>
+ <reg32 offset="0x0411" name="RBBM_PERFCTR_UCHE_4_HI"/>
+ <reg32 offset="0x0412" name="RBBM_PERFCTR_UCHE_5_LO"/>
+ <reg32 offset="0x0413" name="RBBM_PERFCTR_UCHE_5_HI"/>
+ <reg32 offset="0x0414" name="RBBM_PERFCTR_UCHE_6_LO"/>
+ <reg32 offset="0x0415" name="RBBM_PERFCTR_UCHE_6_HI"/>
+ <reg32 offset="0x0416" name="RBBM_PERFCTR_UCHE_7_LO"/>
+ <reg32 offset="0x0417" name="RBBM_PERFCTR_UCHE_7_HI"/>
+ <reg32 offset="0x0418" name="RBBM_PERFCTR_TP_0_LO"/>
+ <reg32 offset="0x0419" name="RBBM_PERFCTR_TP_0_HI"/>
+ <reg32 offset="0x041a" name="RBBM_PERFCTR_TP_1_LO"/>
+ <reg32 offset="0x041b" name="RBBM_PERFCTR_TP_1_HI"/>
+ <reg32 offset="0x041c" name="RBBM_PERFCTR_TP_2_LO"/>
+ <reg32 offset="0x041d" name="RBBM_PERFCTR_TP_2_HI"/>
+ <reg32 offset="0x041e" name="RBBM_PERFCTR_TP_3_LO"/>
+ <reg32 offset="0x041f" name="RBBM_PERFCTR_TP_3_HI"/>
+ <reg32 offset="0x0420" name="RBBM_PERFCTR_TP_4_LO"/>
+ <reg32 offset="0x0421" name="RBBM_PERFCTR_TP_4_HI"/>
+ <reg32 offset="0x0422" name="RBBM_PERFCTR_TP_5_LO"/>
+ <reg32 offset="0x0423" name="RBBM_PERFCTR_TP_5_HI"/>
+ <reg32 offset="0x0424" name="RBBM_PERFCTR_TP_6_LO"/>
+ <reg32 offset="0x0425" name="RBBM_PERFCTR_TP_6_HI"/>
+ <reg32 offset="0x0426" name="RBBM_PERFCTR_TP_7_LO"/>
+ <reg32 offset="0x0427" name="RBBM_PERFCTR_TP_7_HI"/>
+ <reg32 offset="0x0428" name="RBBM_PERFCTR_SP_0_LO"/>
+ <reg32 offset="0x0429" name="RBBM_PERFCTR_SP_0_HI"/>
+ <reg32 offset="0x042a" name="RBBM_PERFCTR_SP_1_LO"/>
+ <reg32 offset="0x042b" name="RBBM_PERFCTR_SP_1_HI"/>
+ <reg32 offset="0x042c" name="RBBM_PERFCTR_SP_2_LO"/>
+ <reg32 offset="0x042d" name="RBBM_PERFCTR_SP_2_HI"/>
+ <reg32 offset="0x042e" name="RBBM_PERFCTR_SP_3_LO"/>
+ <reg32 offset="0x042f" name="RBBM_PERFCTR_SP_3_HI"/>
+ <reg32 offset="0x0430" name="RBBM_PERFCTR_SP_4_LO"/>
+ <reg32 offset="0x0431" name="RBBM_PERFCTR_SP_4_HI"/>
+ <reg32 offset="0x0432" name="RBBM_PERFCTR_SP_5_LO"/>
+ <reg32 offset="0x0433" name="RBBM_PERFCTR_SP_5_HI"/>
+ <reg32 offset="0x0434" name="RBBM_PERFCTR_SP_6_LO"/>
+ <reg32 offset="0x0435" name="RBBM_PERFCTR_SP_6_HI"/>
+ <reg32 offset="0x0436" name="RBBM_PERFCTR_SP_7_LO"/>
+ <reg32 offset="0x0437" name="RBBM_PERFCTR_SP_7_HI"/>
+ <reg32 offset="0x0438" name="RBBM_PERFCTR_SP_8_LO"/>
+ <reg32 offset="0x0439" name="RBBM_PERFCTR_SP_8_HI"/>
+ <reg32 offset="0x043a" name="RBBM_PERFCTR_SP_9_LO"/>
+ <reg32 offset="0x043b" name="RBBM_PERFCTR_SP_9_HI"/>
+ <reg32 offset="0x043c" name="RBBM_PERFCTR_SP_10_LO"/>
+ <reg32 offset="0x043d" name="RBBM_PERFCTR_SP_10_HI"/>
+ <reg32 offset="0x043e" name="RBBM_PERFCTR_SP_11_LO"/>
+ <reg32 offset="0x043f" name="RBBM_PERFCTR_SP_11_HI"/>
+ <reg32 offset="0x0440" name="RBBM_PERFCTR_RB_0_LO"/>
+ <reg32 offset="0x0441" name="RBBM_PERFCTR_RB_0_HI"/>
+ <reg32 offset="0x0442" name="RBBM_PERFCTR_RB_1_LO"/>
+ <reg32 offset="0x0443" name="RBBM_PERFCTR_RB_1_HI"/>
+ <reg32 offset="0x0444" name="RBBM_PERFCTR_RB_2_LO"/>
+ <reg32 offset="0x0445" name="RBBM_PERFCTR_RB_2_HI"/>
+ <reg32 offset="0x0446" name="RBBM_PERFCTR_RB_3_LO"/>
+ <reg32 offset="0x0447" name="RBBM_PERFCTR_RB_3_HI"/>
+ <reg32 offset="0x0448" name="RBBM_PERFCTR_RB_4_LO"/>
+ <reg32 offset="0x0449" name="RBBM_PERFCTR_RB_4_HI"/>
+ <reg32 offset="0x044a" name="RBBM_PERFCTR_RB_5_LO"/>
+ <reg32 offset="0x044b" name="RBBM_PERFCTR_RB_5_HI"/>
+ <reg32 offset="0x044c" name="RBBM_PERFCTR_RB_6_LO"/>
+ <reg32 offset="0x044d" name="RBBM_PERFCTR_RB_6_HI"/>
+ <reg32 offset="0x044e" name="RBBM_PERFCTR_RB_7_LO"/>
+ <reg32 offset="0x044f" name="RBBM_PERFCTR_RB_7_HI"/>
+ <reg32 offset="0x0450" name="RBBM_PERFCTR_VSC_0_LO"/>
+ <reg32 offset="0x0451" name="RBBM_PERFCTR_VSC_0_HI"/>
+ <reg32 offset="0x0452" name="RBBM_PERFCTR_VSC_1_LO"/>
+ <reg32 offset="0x0453" name="RBBM_PERFCTR_VSC_1_HI"/>
+ <reg32 offset="0x0454" name="RBBM_PERFCTR_LRZ_0_LO"/>
+ <reg32 offset="0x0455" name="RBBM_PERFCTR_LRZ_0_HI"/>
+ <reg32 offset="0x0456" name="RBBM_PERFCTR_LRZ_1_LO"/>
+ <reg32 offset="0x0457" name="RBBM_PERFCTR_LRZ_1_HI"/>
+ <reg32 offset="0x0458" name="RBBM_PERFCTR_LRZ_2_LO"/>
+ <reg32 offset="0x0459" name="RBBM_PERFCTR_LRZ_2_HI"/>
+ <reg32 offset="0x045a" name="RBBM_PERFCTR_LRZ_3_LO"/>
+ <reg32 offset="0x045b" name="RBBM_PERFCTR_LRZ_3_HI"/>
+ <reg32 offset="0x045c" name="RBBM_PERFCTR_CMP_0_LO"/>
+ <reg32 offset="0x045d" name="RBBM_PERFCTR_CMP_0_HI"/>
+ <reg32 offset="0x045e" name="RBBM_PERFCTR_CMP_1_LO"/>
+ <reg32 offset="0x045f" name="RBBM_PERFCTR_CMP_1_HI"/>
+ <reg32 offset="0x0460" name="RBBM_PERFCTR_CMP_2_LO"/>
+ <reg32 offset="0x0461" name="RBBM_PERFCTR_CMP_2_HI"/>
+ <reg32 offset="0x0462" name="RBBM_PERFCTR_CMP_3_LO"/>
+ <reg32 offset="0x0463" name="RBBM_PERFCTR_CMP_3_HI"/>
+ <reg32 offset="0x046b" name="RBBM_PERFCTR_RBBM_SEL_0" type="a5xx_rbbm_perfcounter_select"/>
+ <reg32 offset="0x046c" name="RBBM_PERFCTR_RBBM_SEL_1" type="a5xx_rbbm_perfcounter_select"/>
+ <reg32 offset="0x046d" name="RBBM_PERFCTR_RBBM_SEL_2" type="a5xx_rbbm_perfcounter_select"/>
+ <reg32 offset="0x046e" name="RBBM_PERFCTR_RBBM_SEL_3" type="a5xx_rbbm_perfcounter_select"/>
+ <reg32 offset="0x04d2" name="RBBM_ALWAYSON_COUNTER_LO"/>
+ <reg32 offset="0x04d3" name="RBBM_ALWAYSON_COUNTER_HI"/>
+ <reg32 offset="0x04f5" name="RBBM_STATUS">
+ <bitfield high="31" low="31" name="GPU_BUSY_IGN_AHB" />
+ <bitfield high="30" low="30" name="GPU_BUSY_IGN_AHB_CP" />
+ <bitfield high="29" low="29" name="HLSQ_BUSY" />
+ <bitfield high="28" low="28" name="VSC_BUSY" />
+ <bitfield high="27" low="27" name="TPL1_BUSY" />
+ <bitfield high="26" low="26" name="SP_BUSY" />
+ <bitfield high="25" low="25" name="UCHE_BUSY" />
+ <bitfield high="24" low="24" name="VPC_BUSY" />
+ <bitfield high="23" low="23" name="VFDP_BUSY" />
+ <bitfield high="22" low="22" name="VFD_BUSY" />
+ <bitfield high="21" low="21" name="TESS_BUSY" />
+ <bitfield high="20" low="20" name="PC_VSD_BUSY" />
+ <bitfield high="19" low="19" name="PC_DCALL_BUSY" />
+ <bitfield high="18" low="18" name="GPMU_SLAVE_BUSY" />
+ <bitfield high="17" low="17" name="DCOM_BUSY" />
+ <bitfield high="16" low="16" name="COM_BUSY" />
+ <bitfield high="15" low="15" name="LRZ_BUZY" />
+ <bitfield high="14" low="14" name="A2D_DSP_BUSY" />
+ <bitfield high="13" low="13" name="CCUFCHE_BUSY" />
+ <bitfield high="12" low="12" name="RB_BUSY" />
+ <bitfield high="11" low="11" name="RAS_BUSY" />
+ <bitfield high="10" low="10" name="TSE_BUSY" />
+ <bitfield high="9" low="9" name="VBIF_BUSY" />
+ <bitfield high="8" low="8" name="GPU_BUSY_IGN_AHB_HYST" />
+ <bitfield high="7" low="7" name="CP_BUSY_IGN_HYST" />
+ <bitfield high="6" low="6" name="CP_BUSY" />
+ <bitfield high="5" low="5" name="GPMU_MASTER_BUSY" />
+ <bitfield high="4" low="4" name="CP_CRASH_BUSY" />
+ <bitfield high="3" low="3" name="CP_ETS_BUSY" />
+ <bitfield high="2" low="2" name="CP_PFP_BUSY" />
+ <bitfield high="1" low="1" name="CP_ME_BUSY" />
+ <bitfield high="0" low="0" name="HI_BUSY" />
+ </reg32>
+ <reg32 offset="0x0530" name="RBBM_STATUS3">
+ <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x04e1" name="RBBM_INT_0_STATUS"/>
+ <reg32 offset="0x04f0" name="RBBM_AHB_ME_SPLIT_STATUS"/>
+ <reg32 offset="0x04f1" name="RBBM_AHB_PFP_SPLIT_STATUS"/>
+ <reg32 offset="0x04f3" name="RBBM_AHB_ETS_SPLIT_STATUS"/>
+ <reg32 offset="0x04f4" name="RBBM_AHB_ERROR_STATUS"/>
+ <reg32 offset="0x0464" name="RBBM_PERFCTR_CNTL"/>
+ <reg32 offset="0x0465" name="RBBM_PERFCTR_LOAD_CMD0"/>
+ <reg32 offset="0x0466" name="RBBM_PERFCTR_LOAD_CMD1"/>
+ <reg32 offset="0x0467" name="RBBM_PERFCTR_LOAD_CMD2"/>
+ <reg32 offset="0x0468" name="RBBM_PERFCTR_LOAD_CMD3"/>
+ <reg32 offset="0x0469" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
+ <reg32 offset="0x046a" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
+ <reg32 offset="0x046f" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
+ <reg32 offset="0x04ed" name="RBBM_AHB_ERROR"/>
+ <reg32 offset="0x0504" name="RBBM_CFG_DBGBUS_EVENT_LOGIC"/>
+ <reg32 offset="0x0505" name="RBBM_CFG_DBGBUS_OVER"/>
+ <reg32 offset="0x0506" name="RBBM_CFG_DBGBUS_COUNT0"/>
+ <reg32 offset="0x0507" name="RBBM_CFG_DBGBUS_COUNT1"/>
+ <reg32 offset="0x0508" name="RBBM_CFG_DBGBUS_COUNT2"/>
+ <reg32 offset="0x0509" name="RBBM_CFG_DBGBUS_COUNT3"/>
+ <reg32 offset="0x050a" name="RBBM_CFG_DBGBUS_COUNT4"/>
+ <reg32 offset="0x050b" name="RBBM_CFG_DBGBUS_COUNT5"/>
+ <reg32 offset="0x050c" name="RBBM_CFG_DBGBUS_TRACE_ADDR"/>
+ <reg32 offset="0x050d" name="RBBM_CFG_DBGBUS_TRACE_BUF0"/>
+ <reg32 offset="0x050e" name="RBBM_CFG_DBGBUS_TRACE_BUF1"/>
+ <reg32 offset="0x050f" name="RBBM_CFG_DBGBUS_TRACE_BUF2"/>
+ <reg32 offset="0x0510" name="RBBM_CFG_DBGBUS_TRACE_BUF3"/>
+ <reg32 offset="0x0511" name="RBBM_CFG_DBGBUS_TRACE_BUF4"/>
+ <reg32 offset="0x0512" name="RBBM_CFG_DBGBUS_MISR0"/>
+ <reg32 offset="0x0513" name="RBBM_CFG_DBGBUS_MISR1"/>
+ <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
+ <reg32 offset="0xf000" name="RBBM_SECVID_TRUST_CONFIG"/>
+ <reg32 offset="0xf400" name="RBBM_SECVID_TRUST_CNTL"/>
+ <reg32 offset="0xf800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
+ <reg32 offset="0xf801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
+ <reg32 offset="0xf802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
+ <reg32 offset="0xf803" name="RBBM_SECVID_TSB_CNTL"/>
+ <reg32 offset="0xf804" name="RBBM_SECVID_TSB_COMP_STATUS_LO"/>
+ <reg32 offset="0xf805" name="RBBM_SECVID_TSB_COMP_STATUS_HI"/>
+ <reg32 offset="0xf806" name="RBBM_SECVID_TSB_UCHE_STATUS_LO"/>
+ <reg32 offset="0xf807" name="RBBM_SECVID_TSB_UCHE_STATUS_HI"/>
+ <reg32 offset="0xf810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+
+ <!-- VSC registers -->
+ <reg32 offset="0x0bc2" name="VSC_BIN_SIZE">
+ <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
+ <bitfield name="HEIGHT" low="9" high="16" shr="5" type="uint"/>
+ <!-- b17 maybe BYPASS like RB_CNTL, but reg not written for bypass -->
+ </reg32>
+ <reg32 offset="0x0bc3" name="VSC_SIZE_ADDRESS_LO"/>
+ <reg32 offset="0x0bc4" name="VSC_SIZE_ADDRESS_HI"/>
+ <reg32 offset="0x0bc5" name="UNKNOWN_0BC5"/> <!-- always 00000000? -->
+ <reg32 offset="0x0bc6" name="UNKNOWN_0BC6"/> <!-- always 00000000? -->
+ <array offset="0x0bd0" name="VSC_PIPE_CONFIG" stride="1" length="16">
+ <reg32 offset="0x0" name="REG">
+ <doc>
+ Configures the mapping between VSC_PIPE buffer and
+ bin, X/Y specify the bin index in the horiz/vert
+ direction (0,0 is upper left, 0,1 is leftmost bin
+ on second row, and so on). W/H specify the number
+ of bins assigned to this VSC_PIPE in the horiz/vert
+ dimension.
+ </doc>
+ <bitfield name="X" low="0" high="9" type="uint"/>
+ <bitfield name="Y" low="10" high="19" type="uint"/>
+ <bitfield name="W" low="20" high="23" type="uint"/>
+ <bitfield name="H" low="24" high="27" type="uint"/>
+ </reg32>
+ </array>
+ <array offset="0x0be0" name="VSC_PIPE_DATA_ADDRESS" stride="2" length="16">
+ <reg32 offset="0x0" name="LO"/>
+ <reg32 offset="0x1" name="HI"/>
+ </array>
+ <array offset="0x0c00" name="VSC_PIPE_DATA_LENGTH" stride="1" length="16">
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+ <reg32 offset="0x0c60" name="VSC_PERFCTR_VSC_SEL_0" type="a5xx_vsc_perfcounter_select"/>
+ <reg32 offset="0x0c61" name="VSC_PERFCTR_VSC_SEL_1" type="a5xx_vsc_perfcounter_select"/>
+
+ <!-- used for some blits?? -->
+ <reg32 offset="0x0cdd" name="VSC_RESOLVE_CNTL" type="adreno_reg_xy"/>
+
+ <!-- GRAS registers -->
+ <reg32 offset="0x0c81" name="GRAS_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0x0c90" name="GRAS_PERFCTR_TSE_SEL_0" type="a5xx_tse_perfcounter_select"/>
+ <reg32 offset="0x0c91" name="GRAS_PERFCTR_TSE_SEL_1" type="a5xx_tse_perfcounter_select"/>
+ <reg32 offset="0x0c92" name="GRAS_PERFCTR_TSE_SEL_2" type="a5xx_tse_perfcounter_select"/>
+ <reg32 offset="0x0c93" name="GRAS_PERFCTR_TSE_SEL_3" type="a5xx_tse_perfcounter_select"/>
+ <reg32 offset="0x0c94" name="GRAS_PERFCTR_RAS_SEL_0" type="a5xx_ras_perfcounter_select"/>
+ <reg32 offset="0x0c95" name="GRAS_PERFCTR_RAS_SEL_1" type="a5xx_ras_perfcounter_select"/>
+ <reg32 offset="0x0c96" name="GRAS_PERFCTR_RAS_SEL_2" type="a5xx_ras_perfcounter_select"/>
+ <reg32 offset="0x0c97" name="GRAS_PERFCTR_RAS_SEL_3" type="a5xx_ras_perfcounter_select"/>
+ <reg32 offset="0x0c98" name="GRAS_PERFCTR_LRZ_SEL_0" type="a5xx_lrz_perfcounter_select"/>
+ <reg32 offset="0x0c99" name="GRAS_PERFCTR_LRZ_SEL_1" type="a5xx_lrz_perfcounter_select"/>
+ <reg32 offset="0x0c9a" name="GRAS_PERFCTR_LRZ_SEL_2" type="a5xx_lrz_perfcounter_select"/>
+ <reg32 offset="0x0c9b" name="GRAS_PERFCTR_LRZ_SEL_3" type="a5xx_lrz_perfcounter_select"/>
+
+ <reg32 offset="0x0cc4" name="RB_DBG_ECO_CNTL"/> <!-- always 00100000? -->
+ <reg32 offset="0x0cc5" name="RB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0x0cc6" name="RB_MODE_CNTL"/> <!-- always 00000044? -->
+ <reg32 offset="0x0cc7" name="RB_CCU_CNTL"/> <!-- always b0056080 or 10000000? -->
+ <reg32 offset="0x0cd0" name="RB_PERFCTR_RB_SEL_0" type="a5xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0cd1" name="RB_PERFCTR_RB_SEL_1" type="a5xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0cd2" name="RB_PERFCTR_RB_SEL_2" type="a5xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0cd3" name="RB_PERFCTR_RB_SEL_3" type="a5xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0cd4" name="RB_PERFCTR_RB_SEL_4" type="a5xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0cd5" name="RB_PERFCTR_RB_SEL_5" type="a5xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0cd6" name="RB_PERFCTR_RB_SEL_6" type="a5xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0cd7" name="RB_PERFCTR_RB_SEL_7" type="a5xx_rb_perfcounter_select"/>
+ <reg32 offset="0x0cd8" name="RB_PERFCTR_CCU_SEL_0" type="a5xx_ccu_perfcounter_select"/>
+ <reg32 offset="0x0cd9" name="RB_PERFCTR_CCU_SEL_1" type="a5xx_ccu_perfcounter_select"/>
+ <reg32 offset="0x0cda" name="RB_PERFCTR_CCU_SEL_2" type="a5xx_ccu_perfcounter_select"/>
+ <reg32 offset="0x0cdb" name="RB_PERFCTR_CCU_SEL_3" type="a5xx_ccu_perfcounter_select"/>
+ <reg32 offset="0x0ce0" name="RB_POWERCTR_RB_SEL_0"/>
+ <reg32 offset="0x0ce1" name="RB_POWERCTR_RB_SEL_1"/>
+ <reg32 offset="0x0ce2" name="RB_POWERCTR_RB_SEL_2"/>
+ <reg32 offset="0x0ce3" name="RB_POWERCTR_RB_SEL_3"/>
+ <reg32 offset="0x0ce4" name="RB_POWERCTR_CCU_SEL_0"/>
+ <reg32 offset="0x0ce5" name="RB_POWERCTR_CCU_SEL_1"/>
+ <reg32 offset="0x0cec" name="RB_PERFCTR_CMP_SEL_0" type="a5xx_cmp_perfcounter_select"/>
+ <reg32 offset="0x0ced" name="RB_PERFCTR_CMP_SEL_1" type="a5xx_cmp_perfcounter_select"/>
+ <reg32 offset="0x0cee" name="RB_PERFCTR_CMP_SEL_2" type="a5xx_cmp_perfcounter_select"/>
+ <reg32 offset="0x0cef" name="RB_PERFCTR_CMP_SEL_3" type="a5xx_cmp_perfcounter_select"/>
+
+ <reg32 offset="0x0d00" name="PC_DBG_ECO_CNTL">
+ <bitfield name="TWOPASSUSEWFI" pos="8" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0d01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0x0d02" name="PC_MODE_CNTL"/> <!-- always 0000001f? -->
+ <reg32 offset="0x0d04" name="PC_INDEX_BUF_LO"/>
+ <reg32 offset="0x0d05" name="PC_INDEX_BUF_HI"/>
+ <reg32 offset="0x0d06" name="PC_START_INDEX"/>
+ <reg32 offset="0x0d07" name="PC_MAX_INDEX"/>
+ <reg32 offset="0x0d08" name="PC_TESSFACTOR_ADDR_LO"/>
+ <reg32 offset="0x0d09" name="PC_TESSFACTOR_ADDR_HI"/>
+ <reg32 offset="0x0d10" name="PC_PERFCTR_PC_SEL_0" type="a5xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0d11" name="PC_PERFCTR_PC_SEL_1" type="a5xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0d12" name="PC_PERFCTR_PC_SEL_2" type="a5xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0d13" name="PC_PERFCTR_PC_SEL_3" type="a5xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0d14" name="PC_PERFCTR_PC_SEL_4" type="a5xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0d15" name="PC_PERFCTR_PC_SEL_5" type="a5xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0d16" name="PC_PERFCTR_PC_SEL_6" type="a5xx_pc_perfcounter_select"/>
+ <reg32 offset="0x0d17" name="PC_PERFCTR_PC_SEL_7" type="a5xx_pc_perfcounter_select"/>
+
+ <reg32 offset="0x0e00" name="HLSQ_TIMEOUT_THRESHOLD_0"/>
+ <reg32 offset="0x0e01" name="HLSQ_TIMEOUT_THRESHOLD_1"/>
+ <reg32 offset="0x0e04" name="HLSQ_DBG_ECO_CNTL"/>
+ <reg32 offset="0x0e05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0x0e06" name="HLSQ_MODE_CNTL"/> <!-- always 00000001? -->
+ <reg32 offset="0x0e10" name="HLSQ_PERFCTR_HLSQ_SEL_0" type="a5xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e11" name="HLSQ_PERFCTR_HLSQ_SEL_1" type="a5xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e12" name="HLSQ_PERFCTR_HLSQ_SEL_2" type="a5xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e13" name="HLSQ_PERFCTR_HLSQ_SEL_3" type="a5xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e14" name="HLSQ_PERFCTR_HLSQ_SEL_4" type="a5xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e15" name="HLSQ_PERFCTR_HLSQ_SEL_5" type="a5xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e16" name="HLSQ_PERFCTR_HLSQ_SEL_6" type="a5xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0e17" name="HLSQ_PERFCTR_HLSQ_SEL_7" type="a5xx_hlsq_perfcounter_select"/>
+ <reg32 offset="0x0f08" name="HLSQ_SPTP_RDSEL"/>
+ <reg32 offset="0xbc00" name="HLSQ_DBG_READ_SEL"/>
+ <reg32 offset="0xa000" name="HLSQ_DBG_AHB_READ_APERTURE"/>
+
+ <reg32 offset="0x0e41" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0x0e42" name="VFD_MODE_CNTL"/> <!-- always 00000000? -->
+ <reg32 offset="0x0e50" name="VFD_PERFCTR_VFD_SEL_0" type="a5xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e51" name="VFD_PERFCTR_VFD_SEL_1" type="a5xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e52" name="VFD_PERFCTR_VFD_SEL_2" type="a5xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e53" name="VFD_PERFCTR_VFD_SEL_3" type="a5xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e54" name="VFD_PERFCTR_VFD_SEL_4" type="a5xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e55" name="VFD_PERFCTR_VFD_SEL_5" type="a5xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e56" name="VFD_PERFCTR_VFD_SEL_6" type="a5xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e57" name="VFD_PERFCTR_VFD_SEL_7" type="a5xx_vfd_perfcounter_select"/>
+ <reg32 offset="0x0e60" name="VPC_DBG_ECO_CNTL">
+ <bitfield name="ALLFLATOPTDIS" pos="10" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0e61" name="VPC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0x0e62" name="VPC_MODE_CNTL">
+ <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0e64" name="VPC_PERFCTR_VPC_SEL_0" type="a5xx_vpc_perfcounter_select"/>
+ <reg32 offset="0x0e65" name="VPC_PERFCTR_VPC_SEL_1" type="a5xx_vpc_perfcounter_select"/>
+ <reg32 offset="0x0e66" name="VPC_PERFCTR_VPC_SEL_2" type="a5xx_vpc_perfcounter_select"/>
+ <reg32 offset="0x0e67" name="VPC_PERFCTR_VPC_SEL_3" type="a5xx_vpc_perfcounter_select"/>
+
+ <reg32 offset="0x0e80" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0x0e81" name="UCHE_MODE_CNTL"/>
+ <reg32 offset="0x0e82" name="UCHE_SVM_CNTL"/>
+ <reg32 offset="0x0e87" name="UCHE_WRITE_THRU_BASE_LO"/>
+ <reg32 offset="0x0e88" name="UCHE_WRITE_THRU_BASE_HI"/>
+ <reg32 offset="0x0e89" name="UCHE_TRAP_BASE_LO"/>
+ <reg32 offset="0x0e8a" name="UCHE_TRAP_BASE_HI"/>
+ <reg32 offset="0x0e8b" name="UCHE_GMEM_RANGE_MIN_LO"/>
+ <reg32 offset="0x0e8c" name="UCHE_GMEM_RANGE_MIN_HI"/>
+ <reg32 offset="0x0e8d" name="UCHE_GMEM_RANGE_MAX_LO"/>
+ <reg32 offset="0x0e8e" name="UCHE_GMEM_RANGE_MAX_HI"/>
+ <reg32 offset="0x0e8f" name="UCHE_DBG_ECO_CNTL_2"/>
+ <reg32 offset="0x0e90" name="UCHE_DBG_ECO_CNTL"/>
+ <reg32 offset="0x0e91" name="UCHE_CACHE_INVALIDATE_MIN_LO"/>
+ <reg32 offset="0x0e92" name="UCHE_CACHE_INVALIDATE_MIN_HI"/>
+ <reg32 offset="0x0e93" name="UCHE_CACHE_INVALIDATE_MAX_LO"/>
+ <reg32 offset="0x0e94" name="UCHE_CACHE_INVALIDATE_MAX_HI"/>
+ <reg32 offset="0x0e95" name="UCHE_CACHE_INVALIDATE"/>
+ <reg32 offset="0x0e96" name="UCHE_CACHE_WAYS"/>
+ <reg32 offset="0x0ea0" name="UCHE_PERFCTR_UCHE_SEL_0" type="a5xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0ea1" name="UCHE_PERFCTR_UCHE_SEL_1" type="a5xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0ea2" name="UCHE_PERFCTR_UCHE_SEL_2" type="a5xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0ea3" name="UCHE_PERFCTR_UCHE_SEL_3" type="a5xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0ea4" name="UCHE_PERFCTR_UCHE_SEL_4" type="a5xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0ea5" name="UCHE_PERFCTR_UCHE_SEL_5" type="a5xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0ea6" name="UCHE_PERFCTR_UCHE_SEL_6" type="a5xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0ea7" name="UCHE_PERFCTR_UCHE_SEL_7" type="a5xx_uche_perfcounter_select"/>
+ <reg32 offset="0x0ea8" name="UCHE_POWERCTR_UCHE_SEL_0"/>
+ <reg32 offset="0x0ea9" name="UCHE_POWERCTR_UCHE_SEL_1"/>
+ <reg32 offset="0x0eaa" name="UCHE_POWERCTR_UCHE_SEL_2"/>
+ <reg32 offset="0x0eab" name="UCHE_POWERCTR_UCHE_SEL_3"/>
+ <reg32 offset="0x0eb1" name="UCHE_TRAP_LOG_LO"/>
+ <reg32 offset="0x0eb2" name="UCHE_TRAP_LOG_HI"/>
+
+ <reg32 offset="0x0ec0" name="SP_DBG_ECO_CNTL"/>
+ <reg32 offset="0x0ec1" name="SP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0x0ec2" name="SP_MODE_CNTL"/> <!-- always 0000001e? -->
+ <reg32 offset="0x0ed0" name="SP_PERFCTR_SP_SEL_0" type="a5xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ed1" name="SP_PERFCTR_SP_SEL_1" type="a5xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ed2" name="SP_PERFCTR_SP_SEL_2" type="a5xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ed3" name="SP_PERFCTR_SP_SEL_3" type="a5xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ed4" name="SP_PERFCTR_SP_SEL_4" type="a5xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ed5" name="SP_PERFCTR_SP_SEL_5" type="a5xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ed6" name="SP_PERFCTR_SP_SEL_6" type="a5xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ed7" name="SP_PERFCTR_SP_SEL_7" type="a5xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ed8" name="SP_PERFCTR_SP_SEL_8" type="a5xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0ed9" name="SP_PERFCTR_SP_SEL_9" type="a5xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0eda" name="SP_PERFCTR_SP_SEL_10" type="a5xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0edb" name="SP_PERFCTR_SP_SEL_11" type="a5xx_sp_perfcounter_select"/>
+ <reg32 offset="0x0edc" name="SP_POWERCTR_SP_SEL_0"/>
+ <reg32 offset="0x0edd" name="SP_POWERCTR_SP_SEL_1"/>
+ <reg32 offset="0x0ede" name="SP_POWERCTR_SP_SEL_2"/>
+ <reg32 offset="0x0edf" name="SP_POWERCTR_SP_SEL_3"/>
+
+ <reg32 offset="0x0f01" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0x0f02" name="TPL1_MODE_CNTL"/> <!-- always 00000544? -->
+ <reg32 offset="0x0f10" name="TPL1_PERFCTR_TP_SEL_0" type="a5xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f11" name="TPL1_PERFCTR_TP_SEL_1" type="a5xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f12" name="TPL1_PERFCTR_TP_SEL_2" type="a5xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f13" name="TPL1_PERFCTR_TP_SEL_3" type="a5xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f14" name="TPL1_PERFCTR_TP_SEL_4" type="a5xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f15" name="TPL1_PERFCTR_TP_SEL_5" type="a5xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f16" name="TPL1_PERFCTR_TP_SEL_6" type="a5xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f17" name="TPL1_PERFCTR_TP_SEL_7" type="a5xx_tp_perfcounter_select"/>
+ <reg32 offset="0x0f18" name="TPL1_POWERCTR_TP_SEL_0"/>
+ <reg32 offset="0x0f19" name="TPL1_POWERCTR_TP_SEL_1"/>
+ <reg32 offset="0x0f1a" name="TPL1_POWERCTR_TP_SEL_2"/>
+ <reg32 offset="0x0f1b" name="TPL1_POWERCTR_TP_SEL_3"/>
+
+ <reg32 offset="0x3000" name="VBIF_VERSION"/>
+ <reg32 offset="0x3001" name="VBIF_CLKON"/>
+<!--
+#define A5XX_VBIF_CLKON_FORCE_ON_TESTBUS_MASK 0x1
+#define A5XX_VBIF_CLKON_FORCE_ON_TESTBUS_SHIFT 0x1
+ -->
+ <reg32 offset="0x3028" name="VBIF_ABIT_SORT"/>
+ <reg32 offset="0x3029" name="VBIF_ABIT_SORT_CONF"/>
+ <reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/>
+ <reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/>
+ <reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/>
+ <reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/>
+ <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
+<!--
+#define A5XX_VBIF_XIN_HALT_CTRL0_MASK 0xF
+#define A510_VBIF_XIN_HALT_CTRL0_MASK 0x7
+ -->
+ <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
+ <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
+<!--
+#define A5XX_VBIF_TEST_BUS_OUT_CTRL_EN_MASK 0x1
+#define A5XX_VBIF_TEST_BUS_OUT_CTRL_EN_SHIFT 0x0
+ -->
+ <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
+ <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1"/>
+<!--
+#define A5XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL_MASK 0xF
+#define A5XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL_SHIFT 0x0
+ -->
+ <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
+ <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1"/>
+<!--
+#define A5XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_MASK 0xF
+#define A5XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_SHIFT 0x0
+ -->
+ <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
+ <reg32 offset="0x30c0" name="VBIF_PERF_CNT_EN0"/>
+ <reg32 offset="0x30c1" name="VBIF_PERF_CNT_EN1"/>
+ <reg32 offset="0x30c2" name="VBIF_PERF_CNT_EN2"/>
+ <reg32 offset="0x30c3" name="VBIF_PERF_CNT_EN3"/>
+ <reg32 offset="0x30c8" name="VBIF_PERF_CNT_CLR0"/>
+ <reg32 offset="0x30c9" name="VBIF_PERF_CNT_CLR1"/>
+ <reg32 offset="0x30ca" name="VBIF_PERF_CNT_CLR2"/>
+ <reg32 offset="0x30cb" name="VBIF_PERF_CNT_CLR3"/>
+ <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0" type="a5xx_vbif_perfcounter_select"/>
+ <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1" type="a5xx_vbif_perfcounter_select"/>
+ <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2" type="a5xx_vbif_perfcounter_select"/>
+ <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3" type="a5xx_vbif_perfcounter_select"/>
+ <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
+ <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
+ <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
+ <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
+ <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
+ <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
+ <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
+ <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
+ <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
+ <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
+ <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
+ <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
+ <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
+ <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
+ <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
+ <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
+ <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
+
+ <reg32 offset="0x8800" name="GPMU_INST_RAM_BASE"/>
+ <reg32 offset="0x9800" name="GPMU_DATA_RAM_BASE"/>
+
+<!--
+/* COUNTABLE FOR SP PERFCOUNTER */
+#define A5XX_SP_ALU_ACTIVE_CYCLES 0x1
+#define A5XX_SP0_ICL1_MISSES 0x35
+#define A5XX_SP_FS_CFLOW_INSTRUCTIONS 0x27
+
+/* COUNTABLE FOR TSE PERFCOUNTER */
+#define A5XX_TSE_INPUT_PRIM_NUM 0x6
+ -->
+ <reg32 offset="0xa840" name="SP_POWER_COUNTER_0_LO"/>
+ <reg32 offset="0xa841" name="SP_POWER_COUNTER_0_HI"/>
+ <reg32 offset="0xa842" name="SP_POWER_COUNTER_1_LO"/>
+ <reg32 offset="0xa843" name="SP_POWER_COUNTER_1_HI"/>
+ <reg32 offset="0xa844" name="SP_POWER_COUNTER_2_LO"/>
+ <reg32 offset="0xa845" name="SP_POWER_COUNTER_2_HI"/>
+ <reg32 offset="0xa846" name="SP_POWER_COUNTER_3_LO"/>
+ <reg32 offset="0xa847" name="SP_POWER_COUNTER_3_HI"/>
+ <reg32 offset="0xa848" name="TP_POWER_COUNTER_0_LO"/>
+ <reg32 offset="0xa849" name="TP_POWER_COUNTER_0_HI"/>
+ <reg32 offset="0xa84a" name="TP_POWER_COUNTER_1_LO"/>
+ <reg32 offset="0xa84b" name="TP_POWER_COUNTER_1_HI"/>
+ <reg32 offset="0xa84c" name="TP_POWER_COUNTER_2_LO"/>
+ <reg32 offset="0xa84d" name="TP_POWER_COUNTER_2_HI"/>
+ <reg32 offset="0xa84e" name="TP_POWER_COUNTER_3_LO"/>
+ <reg32 offset="0xa84f" name="TP_POWER_COUNTER_3_HI"/>
+ <reg32 offset="0xa850" name="RB_POWER_COUNTER_0_LO"/>
+ <reg32 offset="0xa851" name="RB_POWER_COUNTER_0_HI"/>
+ <reg32 offset="0xa852" name="RB_POWER_COUNTER_1_LO"/>
+ <reg32 offset="0xa853" name="RB_POWER_COUNTER_1_HI"/>
+ <reg32 offset="0xa854" name="RB_POWER_COUNTER_2_LO"/>
+ <reg32 offset="0xa855" name="RB_POWER_COUNTER_2_HI"/>
+ <reg32 offset="0xa856" name="RB_POWER_COUNTER_3_LO"/>
+ <reg32 offset="0xa857" name="RB_POWER_COUNTER_3_HI"/>
+ <reg32 offset="0xa858" name="CCU_POWER_COUNTER_0_LO"/>
+ <reg32 offset="0xa859" name="CCU_POWER_COUNTER_0_HI"/>
+ <reg32 offset="0xa85a" name="CCU_POWER_COUNTER_1_LO"/>
+ <reg32 offset="0xa85b" name="CCU_POWER_COUNTER_1_HI"/>
+ <reg32 offset="0xa85c" name="UCHE_POWER_COUNTER_0_LO"/>
+ <reg32 offset="0xa85d" name="UCHE_POWER_COUNTER_0_HI"/>
+ <reg32 offset="0xa85e" name="UCHE_POWER_COUNTER_1_LO"/>
+ <reg32 offset="0xa85f" name="UCHE_POWER_COUNTER_1_HI"/>
+ <reg32 offset="0xa860" name="UCHE_POWER_COUNTER_2_LO"/>
+ <reg32 offset="0xa861" name="UCHE_POWER_COUNTER_2_HI"/>
+ <reg32 offset="0xa862" name="UCHE_POWER_COUNTER_3_LO"/>
+ <reg32 offset="0xa863" name="UCHE_POWER_COUNTER_3_HI"/>
+ <reg32 offset="0xa864" name="CP_POWER_COUNTER_0_LO"/>
+ <reg32 offset="0xa865" name="CP_POWER_COUNTER_0_HI"/>
+ <reg32 offset="0xa866" name="CP_POWER_COUNTER_1_LO"/>
+ <reg32 offset="0xa867" name="CP_POWER_COUNTER_1_HI"/>
+ <reg32 offset="0xa868" name="CP_POWER_COUNTER_2_LO"/>
+ <reg32 offset="0xa869" name="CP_POWER_COUNTER_2_HI"/>
+ <reg32 offset="0xa86a" name="CP_POWER_COUNTER_3_LO"/>
+ <reg32 offset="0xa86b" name="CP_POWER_COUNTER_3_HI"/>
+ <reg32 offset="0xa86c" name="GPMU_POWER_COUNTER_0_LO"/>
+ <reg32 offset="0xa86d" name="GPMU_POWER_COUNTER_0_HI"/>
+ <reg32 offset="0xa86e" name="GPMU_POWER_COUNTER_1_LO"/>
+ <reg32 offset="0xa86f" name="GPMU_POWER_COUNTER_1_HI"/>
+ <reg32 offset="0xa870" name="GPMU_POWER_COUNTER_2_LO"/>
+ <reg32 offset="0xa871" name="GPMU_POWER_COUNTER_2_HI"/>
+ <reg32 offset="0xa872" name="GPMU_POWER_COUNTER_3_LO"/>
+ <reg32 offset="0xa873" name="GPMU_POWER_COUNTER_3_HI"/>
+ <reg32 offset="0xa874" name="GPMU_POWER_COUNTER_4_LO"/>
+ <reg32 offset="0xa875" name="GPMU_POWER_COUNTER_4_HI"/>
+ <reg32 offset="0xa876" name="GPMU_POWER_COUNTER_5_LO"/>
+ <reg32 offset="0xa877" name="GPMU_POWER_COUNTER_5_HI"/>
+ <reg32 offset="0xa878" name="GPMU_POWER_COUNTER_ENABLE"/>
+ <reg32 offset="0xa879" name="GPMU_ALWAYS_ON_COUNTER_LO"/>
+ <reg32 offset="0xa87a" name="GPMU_ALWAYS_ON_COUNTER_HI"/>
+ <reg32 offset="0xa87b" name="GPMU_ALWAYS_ON_COUNTER_RESET"/>
+ <reg32 offset="0xa87c" name="GPMU_POWER_COUNTER_SELECT_0"/>
+ <reg32 offset="0xa87d" name="GPMU_POWER_COUNTER_SELECT_1"/>
+
+ <reg32 offset="0xa880" name="GPMU_GPMU_SP_CLOCK_CONTROL"/>
+ <reg32 offset="0xa881" name="GPMU_SP_POWER_CNTL"/>
+ <reg32 offset="0xa886" name="GPMU_RBCCU_CLOCK_CNTL"/>
+ <reg32 offset="0xa887" name="GPMU_RBCCU_POWER_CNTL"/>
+ <reg32 offset="0xa88b" name="GPMU_SP_PWR_CLK_STATUS">
+ <bitfield name="PWR_ON" pos="20" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xa88d" name="GPMU_RBCCU_PWR_CLK_STATUS">
+ <bitfield name="PWR_ON" pos="20" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xa891" name="GPMU_PWR_COL_STAGGER_DELAY"/>
+ <reg32 offset="0xa892" name="GPMU_PWR_COL_INTER_FRAME_CTRL"/>
+ <reg32 offset="0xa893" name="GPMU_PWR_COL_INTER_FRAME_HYST"/>
+ <reg32 offset="0xa894" name="GPMU_PWR_COL_BINNING_CTRL"/>
+ <reg32 offset="0xa8a3" name="GPMU_CLOCK_THROTTLE_CTRL"/>
+ <reg32 offset="0xa8a8" name="GPMU_THROTTLE_UNMASK_FORCE_CTRL"/>
+ <reg32 offset="0xa8c1" name="GPMU_WFI_CONFIG"/>
+ <reg32 offset="0xa8d6" name="GPMU_RBBM_INTR_INFO"/>
+ <reg32 offset="0xa8d8" name="GPMU_CM3_SYSRESET"/>
+ <reg32 offset="0xa8e0" name="GPMU_GENERAL_0"/>
+ <reg32 offset="0xa8e1" name="GPMU_GENERAL_1"/>
+ <reg32 offset="0xac00" name="GPMU_TEMP_SENSOR_ID"/>
+ <reg32 offset="0xac01" name="GPMU_TEMP_SENSOR_CONFIG"/>
+ <reg32 offset="0xac02" name="GPMU_TEMP_VAL"/>
+ <reg32 offset="0xac03" name="GPMU_DELTA_TEMP_THRESHOLD"/>
+ <reg32 offset="0xac05" name="GPMU_TEMP_THRESHOLD_INTR_STATUS"/>
+ <reg32 offset="0xac06" name="GPMU_TEMP_THRESHOLD_INTR_EN_MASK"/>
+ <reg32 offset="0xac40" name="GPMU_LEAKAGE_TEMP_COEFF_0_1"/>
+ <reg32 offset="0xac41" name="GPMU_LEAKAGE_TEMP_COEFF_2_3"/>
+ <reg32 offset="0xac42" name="GPMU_LEAKAGE_VTG_COEFF_0_1"/>
+ <reg32 offset="0xac43" name="GPMU_LEAKAGE_VTG_COEFF_2_3"/>
+ <reg32 offset="0xac46" name="GPMU_BASE_LEAKAGE"/>
+ <reg32 offset="0xac60" name="GPMU_GPMU_VOLTAGE"/>
+ <reg32 offset="0xac61" name="GPMU_GPMU_VOLTAGE_INTR_STATUS"/>
+ <reg32 offset="0xac62" name="GPMU_GPMU_VOLTAGE_INTR_EN_MASK"/>
+ <reg32 offset="0xac80" name="GPMU_GPMU_PWR_THRESHOLD"/>
+ <reg32 offset="0xacc4" name="GPMU_GPMU_LLM_GLM_SLEEP_CTRL"/>
+ <reg32 offset="0xacc5" name="GPMU_GPMU_LLM_GLM_SLEEP_STATUS"/>
+ <reg32 offset="0xb80c" name="GDPM_CONFIG1"/>
+ <reg32 offset="0xb80d" name="GDPM_CONFIG2"/>
+ <reg32 offset="0xb80f" name="GDPM_INT_EN"/>
+ <reg32 offset="0xb811" name="GDPM_INT_MASK"/>
+ <reg32 offset="0xb9a0" name="GPMU_BEC_ENABLE"/>
+ <reg32 offset="0xc41a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
+ <reg32 offset="0xc41d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/>
+ <reg32 offset="0xc41f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/>
+ <reg32 offset="0xc421" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/>
+ <reg32 offset="0xc520" name="GPU_CS_ENABLE_REG"/>
+ <reg32 offset="0xc557" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/>
+
+
+ <reg32 offset="0xe000" name="GRAS_CL_CNTL">
+ <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
+ </reg32>
+ <bitset name="a5xx_gras_xs_cl_cntl" inline="yes">
+ <bitfield name="CLIP_MASK" low="0" high="7"/>
+ <bitfield name="CULL_MASK" low="8" high="15"/>
+ </bitset>
+ <reg32 offset="0xe001" name="GRAS_VS_CL_CNTL" type="a5xx_gras_xs_cl_cntl"/>
+ <reg32 offset="0xe004" name="UNKNOWN_E004"/> <!-- always 00000000? -->
+ <reg32 offset="0xe005" name="GRAS_CNTL">
+ <!-- see also RB_RENDER_CONTROL0 -->
+ <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
+ <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
+ <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
+ <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
+ <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
+ <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
+ <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
+ </reg32>
+ <reg32 offset="0xe006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
+ <bitfield name="HORZ" low="0" high="9" type="uint"/>
+ <bitfield name="VERT" low="10" high="19" type="uint"/>
+ </reg32>
+ <reg32 offset="0xe010" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
+ <reg32 offset="0xe011" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
+ <reg32 offset="0xe012" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
+ <reg32 offset="0xe013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
+ <reg32 offset="0xe014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
+ <reg32 offset="0xe015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
+ <reg32 offset="0xe090" name="GRAS_SU_CNTL">
+ <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
+ <bitfield name="CULL_BACK" pos="1" type="boolean"/>
+ <bitfield name="FRONT_CW" pos="2" type="boolean"/>
+ <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
+ <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
+ <bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/>
+ <!-- probably LINEHALFWIDTH is the same as a4xx.. -->
+ </reg32>
+ <reg32 offset="0xe091" name="GRAS_SU_POINT_MINMAX">
+ <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
+ <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
+ </reg32>
+ <reg32 offset="0xe092" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
+ <reg32 offset="0xe093" name="GRAS_SU_LAYERED"/>
+ <reg32 offset="0xe094" name="GRAS_SU_DEPTH_PLANE_CNTL">
+ <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
+ <bitfield name="UNK1" pos="1" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xe095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
+ <reg32 offset="0xe096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
+ <reg32 offset="0xe097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
+ <!-- duplicates RB_DEPTH_INFO0: -->
+ <reg32 offset="0xe098" name="GRAS_SU_DEPTH_BUFFER_INFO">
+ <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a5xx_depth_format"/>
+ </reg32>
+ <reg32 offset="0xe099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL"/> <!-- always 00000000? -->
+ <!--
+ guessing about window/screen/extent, I think they can in the end be
+ used interchangeably?
+ -->
+ <reg32 offset="0xe0a0" name="GRAS_SC_CNTL">
+ <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
+ <bitfield name="SAMPLES_PASSED" pos="15" type="boolean"/>
+ </reg32>
+ <!-- note, 0x4 for binning pass when frag writes z?? -->
+ <reg32 offset="0xe0a1" name="GRAS_SC_BIN_CNTL"/> <!-- always 00000000? -->
+ <reg32 offset="0xe0a2" name="GRAS_SC_RAS_MSAA_CNTL">
+ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
+ </reg32>
+ <reg32 offset="0xe0a3" name="GRAS_SC_DEST_MSAA_CNTL">
+ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
+ <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xe0a4" name="GRAS_SC_SCREEN_SCISSOR_CNTL"/> <!-- always 00000000? -->
+ <reg32 offset="0xe0aa" name="GRAS_SC_SCREEN_SCISSOR_TL_0" type="adreno_reg_xy"/>
+ <reg32 offset="0xe0ab" name="GRAS_SC_SCREEN_SCISSOR_BR_0" type="adreno_reg_xy"/>
+ <reg32 offset="0xe0ca" name="GRAS_SC_VIEWPORT_SCISSOR_TL_0" type="adreno_reg_xy"/>
+ <reg32 offset="0xe0cb" name="GRAS_SC_VIEWPORT_SCISSOR_BR_0" type="adreno_reg_xy"/>
+ <reg32 offset="0xe0ea" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
+ <reg32 offset="0xe0eb" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
+
+ <doc>
+ LRZ: (Low Resolution Z ??)
+ ----
+
+ I think it serves two functions, early discard of primitives in binning
+ pass without needing full resolution depth buffer, and also functions as
+ a depth-prepass, used during the GMEM draws to discard primitives that
+ would not be visible due to later draws.
+
+ The LRZ buffer always seems to be z16 format, regardless of actual
+ depth buffer format.
+
+ Note that LRZ write should be disabled when blend/stencil/etc is enabled,
+ since the occluded primitive can still contribute to final color value
+ of a fragment.
+
+ Only enabled for GL_LESS/GL_LEQUAL/GL_GREATER/GL_GEQUAL?
+ </doc>
+ <reg32 offset="0xe100" name="GRAS_LRZ_CNTL">
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ <doc>LRZ write also disabled for blend/etc.</doc>
+ <bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
+ <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
+ <bitfield name="GREATER" pos="2" type="boolean"/>
+ <!--
+ b3 set sometimes, when depth buffer isn't cleared.. maybe it
+ invalidates the LRZ buffer? (Or just the covered positions?
+ -->
+ </reg32>
+ <reg32 offset="0xe101" name="GRAS_LRZ_BUFFER_BASE_LO"/>
+ <reg32 offset="0xe102" name="GRAS_LRZ_BUFFER_BASE_HI"/>
+ <!--
+ lzr pitch is depth pitch (in pixels) / 8 (aligned to 32)..
+ -->
+ <doc>
+ Pitch is depth width (in pixels) / 8 (aligned to 32). Height
+ is also divided by 8 (ie. covers 8x8 pixels)
+ </doc>
+ <reg32 offset="0xe103" name="GRAS_LRZ_BUFFER_PITCH" shr="5" type="uint"/>
+ <reg32 offset="0xe104" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
+ <reg32 offset="0xe105" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
+
+ <reg32 offset="0xe140" name="RB_CNTL">
+ <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
+ <bitfield name="HEIGHT" low="9" high="16" shr="5" type="uint"/>
+ <bitfield name="BYPASS" pos="17" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xe141" name="RB_RENDER_CNTL">
+<!--
+bit 3 set for normal draws
+bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
+ for z32 with no stencil, but maybe in that case separate z/s not used?
+ see mrt-fbo-* zs=2)
+ -->
+ <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
+ <bitfield name="SAMPLES_PASSED" pos="6" type="boolean"/>
+ <bitfield name="DISABLE_COLOR_PIPE" pos="7" type="boolean"/>
+ <!-- why everything twice?? maybe read vs write? -->
+ <!-- UBWC flag buffer enabled for depth/stencil: -->
+ <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
+ <bitfield name="FLAG_DEPTH2" pos="15" type="boolean"/>
+ <!-- bitmask of MRTs using UBWC flag buffer: -->
+ <bitfield name="FLAG_MRTS" low="16" high="23"/>
+ <bitfield name="FLAG_MRTS2" low="24" high="31"/>
+ </reg32>
+ <reg32 offset="0xe142" name="RB_RAS_MSAA_CNTL">
+ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
+ </reg32>
+ <reg32 offset="0xe143" name="RB_DEST_MSAA_CNTL">
+ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
+ <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
+ </reg32>
+ <!--
+ note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
+ name comes from kernel and is probably right)
+ -->
+ <reg32 offset="0xe144" name="RB_RENDER_CONTROL0">
+ <!-- see also GRAS_CNTL -->
+ <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
+ <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
+ <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
+ <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
+ <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
+ <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
+ <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
+ </reg32>
+ <reg32 offset="0xe145" name="RB_RENDER_CONTROL1">
+ <bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
+ <bitfield name="FACENESS" pos="1" type="boolean"/>
+ <bitfield name="SAMPLEID" pos="2" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xe146" name="RB_FS_OUTPUT_CNTL">
+ <!-- bit0 set except for binning pass.. -->
+ <bitfield name="MRT" low="0" high="3" type="uint"/>
+ <bitfield name="FRAG_WRITES_Z" pos="5" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xe147" name="RB_RENDER_COMPONENTS">
+ <bitfield name="RT0" low="0" high="3"/>
+ <bitfield name="RT1" low="4" high="7"/>
+ <bitfield name="RT2" low="8" high="11"/>
+ <bitfield name="RT3" low="12" high="15"/>
+ <bitfield name="RT4" low="16" high="19"/>
+ <bitfield name="RT5" low="20" high="23"/>
+ <bitfield name="RT6" low="24" high="27"/>
+ <bitfield name="RT7" low="28" high="31"/>
+ </reg32>
+ <array offset="0xe150" name="RB_MRT" stride="7" length="8">
+ <reg32 offset="0x0" name="CONTROL">
+ <bitfield name="BLEND" pos="0" type="boolean"/>
+ <bitfield name="BLEND2" pos="1" type="boolean"/>
+ <bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
+ <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
+ <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
+ </reg32>
+ <reg32 offset="0x1" name="BLEND_CONTROL">
+ <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
+ <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
+ <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
+ <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
+ <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
+ <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
+ </reg32>
+ <reg32 offset="0x2" name="BUF_INFO">
+ <!--
+ not sure if there is a separate COLOR_SWAP field like on a3xx/a4xx,
+ or if it is inherent in the format. Will have to play with bits
+ once we get things working and see what happens. If it is a diff
+ field, it doesn't seem to have the same encoding as a3xx/a4xx.
+ -->
+ <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
+ <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/>
+ <bitfield name="DITHER_MODE" low="11" high="12" type="adreno_rb_dither_mode"/>
+ <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
+ <bitfield name="COLOR_SRGB" pos="15" type="boolean"/>
+ </reg32>
+ <!--
+ at least in gmem, things seem to be aligned to pitch of 64..
+ maybe an artifact of tiled format used in gmem?
+ -->
+ <reg32 offset="0x3" name="PITCH" shr="6" type="uint"/>
+ <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/>
+ <reg32 offset="0x5" name="BASE_LO"/>
+ <reg32 offset="0x6" name="BASE_HI"/>
+ </array>
+ <reg32 offset="0xe1a0" name="RB_BLEND_RED">
+ <bitfield name="UINT" low="0" high="7" type="hex"/>
+ <bitfield name="SINT" low="8" high="15" type="hex"/>
+ <bitfield name="FLOAT" low="16" high="31" type="float"/>
+ </reg32>
+ <reg32 offset="0xe1a1" name="RB_BLEND_RED_F32" type="float"/>
+ <reg32 offset="0xe1a2" name="RB_BLEND_GREEN">
+ <bitfield name="UINT" low="0" high="7" type="hex"/>
+ <bitfield name="SINT" low="8" high="15" type="hex"/>
+ <bitfield name="FLOAT" low="16" high="31" type="float"/>
+ </reg32>
+ <reg32 offset="0xe1a3" name="RB_BLEND_GREEN_F32" type="float"/>
+ <reg32 offset="0xe1a4" name="RB_BLEND_BLUE">
+ <bitfield name="UINT" low="0" high="7" type="hex"/>
+ <bitfield name="SINT" low="8" high="15" type="hex"/>
+ <bitfield name="FLOAT" low="16" high="31" type="float"/>
+ </reg32>
+ <reg32 offset="0xe1a5" name="RB_BLEND_BLUE_F32" type="float"/>
+ <reg32 offset="0xe1a6" name="RB_BLEND_ALPHA">
+ <bitfield name="UINT" low="0" high="7" type="hex"/>
+ <bitfield name="SINT" low="8" high="15" type="hex"/>
+ <bitfield name="FLOAT" low="16" high="31" type="float"/>
+ </reg32>
+ <reg32 offset="0xe1a7" name="RB_BLEND_ALPHA_F32" type="float"/>
+ <reg32 offset="0xe1a8" name="RB_ALPHA_CONTROL">
+ <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
+ <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
+ <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
+ </reg32>
+ <reg32 offset="0xe1a9" name="RB_BLEND_CNTL">
+ <!-- per-mrt enable bit -->
+ <bitfield name="ENABLE_BLEND" low="0" high="7"/>
+ <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
+ <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
+ <!-- a guess? -->
+ <bitfield name="SAMPLE_MASK" low="16" high="31"/>
+ </reg32>
+ <reg32 offset="0xe1b0" name="RB_DEPTH_PLANE_CNTL">
+ <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
+ <bitfield name="UNK1" pos="1" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xe1b1" name="RB_DEPTH_CNTL">
+ <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
+ <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
+ <doc>Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
+ <bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xe1b2" name="RB_DEPTH_BUFFER_INFO">
+ <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a5xx_depth_format"/>
+ </reg32>
+ <reg32 offset="0xe1b3" name="RB_DEPTH_BUFFER_BASE_LO"/>
+ <reg32 offset="0xe1b4" name="RB_DEPTH_BUFFER_BASE_HI"/>
+ <reg32 offset="0xe1b5" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint">
+ <doc>stride of depth/stencil buffer</doc>
+ </reg32>
+ <reg32 offset="0xe1b6" name="RB_DEPTH_BUFFER_ARRAY_PITCH" shr="6" type="uint">
+ <doc>size of layer</doc>
+ </reg32>
+ <reg32 offset="0xe1c0" name="RB_STENCIL_CONTROL">
+ <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
+ <!--
+ set for stencil operations that require read from stencil
+ buffer, but not for example for stencil clear (which does
+ not require read).. so guessing this is analogous to
+ READ_DEST_ENABLE for color buffer..
+ -->
+ <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
+ <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
+ <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
+ <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
+ <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
+ <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
+ <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
+ <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
+ <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
+ </reg32>
+ <reg32 offset="0xe1c1" name="RB_STENCIL_INFO">
+ <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xe1c2" name="RB_STENCIL_BASE_LO"/>
+ <reg32 offset="0xe1c3" name="RB_STENCIL_BASE_HI"/>
+ <reg32 offset="0xe1c4" name="RB_STENCIL_PITCH" shr="6" type="uint"/>
+ <reg32 offset="0xe1c5" name="RB_STENCIL_ARRAY_PITCH" shr="6" type="uint"/>
+ <reg32 offset="0xe1c6" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
+ <reg32 offset="0xe1c7" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
+ <reg32 offset="0xe1d0" name="RB_WINDOW_OFFSET" type="adreno_reg_xy"/>
+ <reg32 offset="0xe1d1" name="RB_SAMPLE_COUNT_CONTROL">
+ <bitfield name="COPY" pos="1" type="boolean"/>
+ </reg32>
+
+ <doc>
+ Blits:
+ ------
+
+ Blits are triggered by CP_EVENT_WRITE:BLIT, compared to previous
+ generations where they shared most of the gl pipeline and were
+ triggered by CP_DRAW_INDX*
+
+ For gmem->mem blob uses RB_BLIT_CNTL.BUF to specify src of
+ blit (ie MRTn, ZS, etc) and RB_BLIT_DST_LO/HI for destination
+ gpuaddr. The gmem offset is taken from RB_MRT[n].BASE_LO/HI
+
+ For mem->gmem blob uses just MRT0 or ZS and RB_BLIT_DST_LO/HI
+ for the GMEM offset, and gpuaddr from RB_MRT[0].BASE_LO/HI
+ (I suppose this is just to avoid trashing RB_MRT[1..7]??)
+ </doc>
+ <reg32 offset="0xe210" name="RB_BLIT_CNTL">
+ <bitfield name="BUF" low="0" high="3" type="a5xx_blit_buf"/>
+ </reg32>
+ <reg32 offset="0xe211" name="RB_RESOLVE_CNTL_1" type="adreno_reg_xy"/>
+ <reg32 offset="0xe212" name="RB_RESOLVE_CNTL_2" type="adreno_reg_xy"/>
+ <reg32 offset="0xe213" name="RB_RESOLVE_CNTL_3">
+ <!-- if b0 set, output is in TILE5_3 format -->
+ <bitfield name="TILED" pos="0" type="boolean"/>
+ <!--
+ 0xe213:
+ 0x0 mem->gmem
+ 0xf gmem->mem with flag buffer (color)
+ 0x4 gmem->mem without flag buffer (color)
+ 0x7 BYPASS mode flag buffer result (ie. on readpix)
+ also for gmem->mem preserving tiling
+ -->
+ </reg32>
+ <reg32 offset="0xe214" name="RB_BLIT_DST_LO"/>
+ <reg32 offset="0xe215" name="RB_BLIT_DST_HI"/>
+ <reg32 offset="0xe216" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/>
+ <!-- array-pitch is size of layer -->
+ <reg32 offset="0xe217" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/>
+ <reg32 offset="0xe218" name="RB_CLEAR_COLOR_DW0"/>
+ <reg32 offset="0xe219" name="RB_CLEAR_COLOR_DW1"/>
+ <reg32 offset="0xe21a" name="RB_CLEAR_COLOR_DW2"/>
+ <reg32 offset="0xe21b" name="RB_CLEAR_COLOR_DW3"/>
+ <reg32 offset="0xe21c" name="RB_CLEAR_CNTL">
+ <bitfield name="FAST_CLEAR" pos="1" type="boolean"/>
+ <bitfield name="MSAA_RESOLVE" pos="2" type="boolean"/>
+ <doc>
+ For MASK, if RB_BLIT_CNTL.BUF=BLIT_ZS:
+ 1 - depth
+ 2 - stencil
+ 3 - depth+stencil
+ if RB_BLIT_CNTL.BUF=BLIT_MRTn
+ then probably a component mask, I always see 0xf
+ </doc>
+ <bitfield name="MASK" low="4" high="7"/>
+ </reg32>
+
+ <doc>
+ Buffer Metadata (flag buffers):
+ -------------------------------
+
+ Blob seems to stick some metadata at the front of the buffer,
+ both z/s and MRT. I think this is same as UBWC (bandwidth
+ compression) metadata that mdp 1.7 and later supports. See
+ 1d3fae5698ce5358caab87a15383b690941697e8 in downstream kernel.
+ UBWC seems to stand for "universal bandwidth compression".
+
+ Before glReadPixels() it does a pair of BYPASS blits (at least
+ if metadata is used) presumably to resolve metadata.
+
+ NOTES: see: getUBwcBlockSize(), getUBwcMetaBufferSize() at
+ https://android.googlesource.com/platform/hardware/qcom/display/+/android-6.0.1_r40/msm8994/libgralloc/alloc_controller.cpp
+ (note that bpp in bytes, not bits, so really cpp)
+
+ Example Layout 2d w/ mipmap levels:
+
+ 100x2000, ifmt=GL_RG, fmt=GL_RG16F, type=GL_FLOAT, meta=64x512@0x8000 (7x500)
+ base=c072e000, offset=16384, size=1703936
+
+ color flags
+ 0 c073a000 c0732000 - level 0 flags is address
+ 1 c0838000 c0834000 programmed in texture state
+ 2 c0879000 c0877000
+ 3 c089a000 c0899000
+ 4 c08ab000 c08aa000
+ 5 c08b4000 c08b3000
+ 6 c08b9000 c08b8000
+ 7 c08bc000 c08bb000
+ 8 c08be000 c08bd000
+ 9 c08c0000 c08bf000
+ 10 c08c2000 c08c1000
+
+ ARRAY_PITCH is the combined size of all the levels plus flags,
+ so 0xc08c3000 - 0xc0732000 = 0x00191000 (1642496); each level
+ takes up a minimum of 2 pages (since color and flags parts are
+ each page aligned.
+
+ { TILE_MODE = TILE5_3 | SWIZ_X = A5XX_TEX_X | SWIZ_Y = A5XX_TEX_Y | SWIZ_Z = A5XX_TEX_ZERO | SWIZ_W = A5XX_TEX_ONE | MIPLVLS = 0 | FMT = TFMT5_16_16_FLOAT | SWAP = WZYX }
+ { WIDTH = 100 | HEIGHT = 2000 }
+ { FETCHSIZE = TFETCH5_4_BYTE | PITCH = 512 | TYPE = A5XX_TEX_2D }
+ { ARRAY_PITCH = 1642496 | 0x18800000 } - NOTE c2dc always has 0x18800000 but
+ { BASE_LO = 0xc0732000 } this varies for blob gles driver..
+ { BASE_HI = 0 | DEPTH = 1 } not sure what it is
+
+
+ </doc>
+ <reg32 offset="0xe240" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
+ <reg32 offset="0xe241" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
+ <reg32 offset="0xe242" name="RB_DEPTH_FLAG_BUFFER_PITCH">
+ </reg32>
+ <array offset="0xe243" name="RB_MRT_FLAG_BUFFER" stride="4" length="8">
+ <reg32 offset="0" name="ADDR_LO"/>
+ <reg32 offset="1" name="ADDR_HI"/>
+ <reg32 offset="2" name="PITCH" shr="6" type="uint"/>
+ <!-- array-pitch is size of layer -->
+ <reg32 offset="3" name="ARRAY_PITCH" shr="6" type="uint"/>
+ </array>
+ <reg32 offset="0xe263" name="RB_BLIT_FLAG_DST_LO"/>
+ <reg32 offset="0xe264" name="RB_BLIT_FLAG_DST_HI"/>
+ <reg32 offset="0xe265" name="RB_BLIT_FLAG_DST_PITCH" shr="6" type="uint"/>
+ <!-- array-pitch is size of layer -->
+ <reg32 offset="0xe266" name="RB_BLIT_FLAG_DST_ARRAY_PITCH" shr="6" type="uint"/>
+
+ <reg32 offset="0xe267" name="RB_SAMPLE_COUNT_ADDR_LO"/>
+ <reg32 offset="0xe268" name="RB_SAMPLE_COUNT_ADDR_HI"/>
+
+ <reg32 offset="0xe280" name="VPC_CNTL_0">
+ <doc>
+ num of varyings plus four for gl_Position (plus one if gl_PointSize)
+ plus # of transform-feedback (streamout) varyings if using the
+ hw streamout (rather than stg instructions in shader)
+ </doc>
+ <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
+ <bitfield name="VARYING" pos="11" type="boolean"/>
+ </reg32>
+ <array offset="0xe282" name="VPC_VARYING_INTERP" stride="1" length="8">
+ <reg32 offset="0x0" name="MODE"/>
+ </array>
+ <array offset="0xe28a" name="VPC_VARYING_PS_REPL" stride="1" length="8">
+ <reg32 offset="0x0" name="MODE"/>
+ </array>
+ <reg32 offset="0xe292" name="UNKNOWN_E292"/>
+ <reg32 offset="0xe293" name="UNKNOWN_E293"/>
+ <array offset="0xe294" name="VPC_VAR" stride="1" length="4">
+ <!-- one bit per varying component: -->
+ <reg32 offset="0" name="DISABLE"/>
+ </array>
+ <reg32 offset="0xe298" name="VPC_GS_SIV_CNTL"/>
+ <reg32 offset="0xe29a" name="VPC_CLIP_CNTL">
+ <bitfield name="CLIP_MASK" low="0" high="7" type="uint"/>
+ <!-- there can be up to 8 total clip/cull distance outputs,
+ but apparenly VPC can only deal with vec4, so when there are
+ more than 4 outputs a second location needs to be programmed
+ -->
+ <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/>
+ <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0xe29d" name="VPC_PACK">
+ <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
+ <!--
+ This seems to be the OUTLOC for the psize output. It could possibly
+ be the max-OUTLOC position, but it is only set when VS writes psize
+ (and blob always puts psize at highest OUTLOC)
+ -->
+ <bitfield name="PSIZELOC" low="8" high="15" type="uint"/>
+ </reg32>
+ <reg32 offset="0xe2a0" name="VPC_FS_PRIMITIVEID_CNTL"/>
+
+ <doc>
+ Stream-Out:
+ -----------
+
+ VPC_SO[0..3] registers setup details about streamout buffers, and
+ number of components to write to each.
+
+ VPC_SO_PROG provides the mapping between output varyings and the SO
+ buffers. It is written multiple times (via a CP_CONTEXT_REG_BUNCH
+ packet, not sure if that matters), each write can handle up to two
+ components of stream-out output. Order matches up to OUTLOC,
+ including padding. So, if outputting first 3 varyings:
+
+ SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0x7 }
+ SP_VS_OUT[0x1].REG: { A_REGID = r1.w | A_COMPMASK = 0x3 | B_REGID = r2.y | B_COMPMASK = 0xf }
+ SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 4 | OUTLOC2 = 8 | OUTLOC3 = 12 }
+
+ Then:
+
+ VPC_SO_PROG: { A_BUF = 0 | A_OFF = 0 | A_EN | A_BUF = 0 | B_OFF = 4 | B_EN }
+ VPC_SO_PROG: { A_BUF = 0 | A_OFF = 8 | A_EN | A_BUF = 0 | B_OFF = 12 | B_EN }
+ VPC_SO_PROG: { A_BUF = 2 | A_OFF = 0 | A_EN | A_BUF = 2 | B_OFF = 4 | B_EN }
+ VPC_SO_PROG: { A_BUF = 2 | A_OFF = 8 | A_EN | A_BUF = 0 | B_OFF = 0 }
+ VPC_SO_PROG: { A_BUF = 1 | A_OFF = 0 | A_EN | A_BUF = 1 | B_OFF = 4 | B_EN }
+
+ Note that varying order is OUTLOC0, OUTLOC2, OUTLOC1, and note
+ the padding between OUTLOC1 and OUTLOC2.
+
+ The BUF bitfield indicates which of the four streamout buffers
+ to write into at the specified offset.
+
+ The VPC_SO[n].FLUSH_BASE_LO/HI is used for hw to write back next
+ offset which gets loaded back into VPC_SO[n].BUFFER_OFFSET via a
+ CP_MEM_TO_REG. Probably can be ignored until we have GS/etc, at
+ which point we can't calculate the offset on the CPU.
+ </doc>
+ <reg32 offset="0xe2a1" name="VPC_SO_BUF_CNTL">
+ <bitfield name="BUF0" pos="0" type="boolean"/>
+ <bitfield name="BUF1" pos="3" type="boolean"/>
+ <bitfield name="BUF2" pos="6" type="boolean"/>
+ <bitfield name="BUF3" pos="9" type="boolean"/>
+ <bitfield name="ENABLE" pos="15" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xe2a2" name="VPC_SO_OVERRIDE">
+ <bitfield name="SO_DISABLE" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xe2a3" name="VPC_SO_CNTL">
+ <!-- always 0x10000 when SO enabled.. -->
+ <bitfield name="ENABLE" pos="16" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xe2a4" name="VPC_SO_PROG">
+ <bitfield name="A_BUF" low="0" high="1" type="uint"/>
+ <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
+ <bitfield name="A_EN" pos="11" type="boolean"/>
+ <bitfield name="B_BUF" low="12" high="13" type="uint"/>
+ <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
+ <bitfield name="B_EN" pos="23" type="boolean"/>
+ </reg32>
+ <array offset="0xe2a7" name="VPC_SO" stride="7" length="4">
+ <reg32 offset="0" name="BUFFER_BASE_LO"/>
+ <reg32 offset="1" name="BUFFER_BASE_HI"/>
+ <reg32 offset="2" name="BUFFER_SIZE"/>
+ <reg32 offset="3" name="NCOMP"/> <!-- component count -->
+ <reg32 offset="4" name="BUFFER_OFFSET"/>
+ <reg32 offset="5" name="FLUSH_BASE_LO"/>
+ <reg32 offset="6" name="FLUSH_BASE_HI"/>
+ </array>
+
+ <reg32 offset="0xe384" name="PC_PRIMITIVE_CNTL">
+ <!-- # of varyings plus four for gl_Position (plus one if gl_PointSize) -->
+ <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
+ <bitfield name="PRIMITIVE_RESTART" pos="8" type="boolean"/>
+ <bitfield name="COUNT_PRIMITIVES" pos="9" type="boolean"/><!-- enabled when gl_PrimitiveIDIn is used -->
+ <bitfield name="PROVOKING_VTX_LAST" pos="10" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xe385" name="PC_PRIM_VTX_CNTL">
+ <bitfield name="PSIZE" pos="11" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xe388" name="PC_RASTER_CNTL">
+ <bitfield name="POLYMODE_FRONT_PTYPE" low="0" high="2" type="adreno_pa_su_sc_draw"/>
+ <bitfield name="POLYMODE_BACK_PTYPE" low="3" high="5" type="adreno_pa_su_sc_draw"/>
+ <bitfield name="POLYMODE_ENABLE" pos="6" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xe389" name="PC_CLIP_CNTL">
+ <bitfield name="CLIP_MASK" low="0" high="7"/>
+ </reg32>
+ <reg32 offset="0xe38c" name="PC_RESTART_INDEX"/>
+ <reg32 offset="0xe38d" name="PC_GS_LAYERED"/>
+ <reg32 offset="0xe38e" name="PC_GS_PARAM">
+ <bitfield name="MAX_VERTICES" low="0" high="9" type="uint"/><!-- vertices - 1 -->
+ <bitfield name="INVOCATIONS" low="11" high="15" type="uint"/><!-- invoc - 1 -->
+ <bitfield name="PRIMTYPE" low="23" high="24" type="adreno_pa_su_sc_draw"/>
+ </reg32>
+ <reg32 offset="0xe38f" name="PC_HS_PARAM">
+ <bitfield name="VERTICES_OUT" low="0" high="5" type="uint"/>
+ <bitfield name="SPACING" low="21" high="22" type="a4xx_tess_spacing"/>
+ <bitfield name="CW" pos="23" type="boolean"/>
+ <bitfield name="CONNECTED" pos="24" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xe3b0" name="PC_POWER_CNTL"/>
+
+ <reg32 offset="0xe400" name="VFD_CONTROL_0">
+ <bitfield name="VTXCNT" low="0" high="5" type="uint"/>
+ </reg32>
+ <reg32 offset="0xe401" name="VFD_CONTROL_1">
+ <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0xe402" name="VFD_CONTROL_2">
+ <bitfield name="REGID_PATCHID" low="0" high="7" type="a3xx_regid"/><!-- same as VFD_CONTROL_3.REGID_PATCHID? -->
+ </reg32>
+ <reg32 offset="0xe403" name="VFD_CONTROL_3">
+ <bitfield name="REGID_PATCHID" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0xe404" name="VFD_CONTROL_4">
+ </reg32>
+ <reg32 offset="0xe405" name="VFD_CONTROL_5">
+ <!-- b0 set if gl_PrimitiveID used in fs ?? -->
+ </reg32>
+ <reg32 offset="0xe408" name="VFD_INDEX_OFFSET"/>
+ <reg32 offset="0xe409" name="VFD_INSTANCE_START_OFFSET"/>
+ <array offset="0xe40a" name="VFD_FETCH" stride="4" length="32">
+ <reg32 offset="0x0" name="BASE_LO"/>
+ <reg32 offset="0x1" name="BASE_HI"/>
+ <reg32 offset="0x2" name="SIZE" type="uint"/>
+ <reg32 offset="0x3" name="STRIDE" type="uint"/>
+ </array>
+ <array offset="0xe48a" name="VFD_DECODE" stride="2" length="32">
+ <reg32 offset="0x0" name="INSTR">
+ <!-- IDX appears to index into VFD_FETCH[] -->
+ <bitfield name="IDX" low="0" high="4" type="uint"/>
+ <bitfield name="INSTANCED" pos="17" type="boolean"/>
+ <bitfield name="FORMAT" low="20" high="27" type="a5xx_vtx_fmt"/>
+ <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
+ <bitfield name="UNK30" pos="30" type="boolean"/>
+ <bitfield name="FLOAT" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x1" name="STEP_RATE"/> <!-- ??? -->
+ </array>
+ <array offset="0xe4ca" name="VFD_DEST_CNTL" stride="1" length="32">
+ <reg32 offset="0x0" name="INSTR">
+ <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
+ <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
+ </reg32>
+ </array>
+ <reg32 offset="0xe4f0" name="VFD_POWER_CNTL"/>
+
+ <!-- 0x0 for compute, 0x10 for 3d? -->
+ <reg32 offset="0xe580" name="SP_SP_CNTL"/>
+
+ <bitset name="a5xx_xs_config" inline="yes">
+ <bitfield name="ENABLED" pos="0" type="boolean"/>
+ <bitfield name="CONSTOBJECTOFFSET" low="1" high="7" type="uint"/>
+ <bitfield name="SHADEROBJOFFSET" low="8" high="14" type="uint"/>
+ </bitset>
+ <bitset name="a5xx_xs_cntl" inline="yes">
+ <bitfield name="SSBO_ENABLE" pos="0" type="boolean"/>
+ <!--
+ no idea high bit.. could be this is amount of on-chip memory used
+ rather than total size?
+ -->
+ <bitfield name="INSTRLEN" low="1" high="31" type="uint"/>
+ </bitset>
+ <bitset name="a5xx_sp_xs_ctrl_reg0" inline="yes">
+ <!-- bit1 almost always set -->
+ <!-- set for "buffer mode" (ie. shader small enough to fit internally) -->
+ <bitfield name="BUFFER" pos="2" type="boolean"/>
+ <!-- 24 or more (full size) GPRS and blob uses TWO_QUADS instead of FOUR_QUADS -->
+ <bitfield name="THREADSIZE" pos="3" type="a3xx_threadsize"/>
+ <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
+ <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
+ <bitfield name="VARYING" pos="16" type="boolean"/>
+ <bitfield name="PIXLODENABLE" pos="20" type="boolean"/>
+ <!-- seems to be nesting level for flow control:.. -->
+ <bitfield name="BRANCHSTACK" low="25" high="31" type="uint"/>
+ </bitset>
+ <!-- assuming things appear in same relative order as a4xx: -->
+ <!-- duplicated exactly w/ corresponding HLSQ_ regs starting at 0xe78b.. -->
+ <reg32 offset="0xe584" name="SP_VS_CONFIG" type="a5xx_xs_config"/>
+ <reg32 offset="0xe585" name="SP_FS_CONFIG" type="a5xx_xs_config"/>
+ <reg32 offset="0xe586" name="SP_HS_CONFIG" type="a5xx_xs_config"/>
+ <reg32 offset="0xe587" name="SP_DS_CONFIG" type="a5xx_xs_config"/>
+ <reg32 offset="0xe588" name="SP_GS_CONFIG" type="a5xx_xs_config"/>
+ <reg32 offset="0xe589" name="SP_CS_CONFIG" type="a5xx_xs_config"/>
+ <reg32 offset="0xe58a" name="SP_VS_CONFIG_MAX_CONST"/>
+ <reg32 offset="0xe58b" name="SP_FS_CONFIG_MAX_CONST"/>
+ <reg32 offset="0xe590" name="SP_VS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
+ <reg32 offset="0xe592" name="SP_PRIMITIVE_CNTL">
+ <!-- # of VS outputs including pos/psize -->
+ <bitfield name="VSOUT" low="0" high="4" type="uint"/>
+ </reg32>
+ <array offset="0xe593" name="SP_VS_OUT" stride="1" length="16">
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
+ <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
+ </reg32>
+ </array>
+ <!--
+ Starting with a5xx, position/psize outputs from shader end up in the
+ SP_VS_OUT map, with highest OUTLOCn position. (Generally they are
+ the last entries too, except when gl_PointCoord is used, blob inserts
+ an extra varying after, but with a lower OUTLOC position. If present,
+ psize is last, preceded by position.
+ -->
+ <array offset="0xe5a3" name="SP_VS_VPC_DST" stride="1" length="8">
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
+ <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
+ <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
+ <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
+ </reg32>
+ </array>
+ <reg32 offset="0xe5ab" name="UNKNOWN_E5AB"/>
+ <reg32 offset="0xe5ac" name="SP_VS_OBJ_START_LO"/>
+ <reg32 offset="0xe5ad" name="SP_VS_OBJ_START_HI"/>
+
+ <bitset name="a5xx_sp_xs_pvt_mem_param" inline="yes">
+ <bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9">
+ <doc>The size of memory that ldp/stp can address.</doc>
+ </bitfield>
+ <bitfield name="HWSTACKOFFSET" low="8" high="23" shr="11" type="uint"/>
+ <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31">
+ <doc>Guessing that this is the same as a3xx/a6xx.</doc>
+ </bitfield>
+ </bitset>
+
+ <bitset name="a5xx_sp_xs_pvt_mem_size" inline="yes">
+ <bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/>
+ </bitset>
+
+ <reg32 offset="0xe5ae" name="SP_VS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
+ <reg64 offset="0xe5af" name="SP_VS_PVT_MEM_ADDR" type="waddress" align="32"/>
+ <reg32 offset="0xe5b1" name="SP_VS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
+ <reg32 offset="0xe5c0" name="SP_FS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
+ <reg32 offset="0xe5c2" name="UNKNOWN_E5C2"/>
+ <reg32 offset="0xe5c3" name="SP_FS_OBJ_START_LO"/>
+ <reg32 offset="0xe5c4" name="SP_FS_OBJ_START_HI"/>
+ <reg32 offset="0xe5c5" name="SP_FS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
+ <reg64 offset="0xe5c6" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32"/>
+ <reg32 offset="0xe5c8" name="SP_FS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
+ <reg32 offset="0xe5c9" name="SP_BLEND_CNTL">
+ <!-- per-mrt enable bit -->
+ <bitfield name="ENABLE_BLEND" low="0" high="7"/>
+ <bitfield name="UNK8" pos="8" type="boolean"/>
+ <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xe5ca" name="SP_FS_OUTPUT_CNTL">
+ <bitfield name="MRT" low="0" high="3" type="uint"/>
+ <bitfield name="DEPTH_REGID" low="5" high="12" type="a3xx_regid"/>
+ <bitfield name="SAMPLEMASK_REGID" low="13" high="20" type="a3xx_regid"/>
+ </reg32>
+ <array offset="0xe5cb" name="SP_FS_OUTPUT" stride="1" length="8">
+ <doc>per MRT</doc>
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
+ </reg32>
+ </array>
+ <array offset="0xe5d3" name="SP_FS_MRT" stride="1" length="8">
+ <reg32 offset="0" name="REG">
+ <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
+ <bitfield name="COLOR_SINT" pos="8" type="boolean"/>
+ <bitfield name="COLOR_UINT" pos="9" type="boolean"/>
+ <bitfield name="COLOR_SRGB" pos="10" type="boolean"/>
+ </reg32>
+ </array>
+ <!--
+ e5db/e5dc seems to look related to some optimization to do sample from
+ texture using varying value directly before shader thread starts? I
+ guess that could optimize common simple frag shaders..
+ -->
+ <reg32 offset="0xe5db" name="UNKNOWN_E5DB"/>
+ <reg32 offset="0xe5f0" name="SP_CS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
+ <reg32 offset="0xe5f2" name="UNKNOWN_E5F2"/>
+ <reg32 offset="0xe5f3" name="SP_CS_OBJ_START_LO"/>
+ <reg32 offset="0xe5f4" name="SP_CS_OBJ_START_HI"/>
+ <reg32 offset="0xe5f5" name="SP_CS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
+ <reg64 offset="0xe5f6" name="SP_CS_PVT_MEM_ADDR" type="waddress" align="32"/>
+ <reg32 offset="0xe5f8" name="SP_CS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
+
+ <!-- e5f9 something compute related.. seems to change when HLSQ_CS_CNTL_1 changes -->
+
+ <reg32 offset="0xe600" name="SP_HS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
+ <reg32 offset="0xe602" name="UNKNOWN_E602"/>
+ <reg32 offset="0xe603" name="SP_HS_OBJ_START_LO"/>
+ <reg32 offset="0xe604" name="SP_HS_OBJ_START_HI"/>
+ <reg32 offset="0xe605" name="SP_HS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
+ <reg64 offset="0xe606" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32"/>
+ <reg32 offset="0xe608" name="SP_HS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
+ <reg32 offset="0xe610" name="SP_DS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
+ <reg32 offset="0xe62b" name="UNKNOWN_E62B"/>
+ <reg32 offset="0xe62c" name="SP_DS_OBJ_START_LO"/>
+ <reg32 offset="0xe62d" name="SP_DS_OBJ_START_HI"/>
+ <reg32 offset="0xe62e" name="SP_DS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
+ <reg64 offset="0xe62f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32"/>
+ <reg32 offset="0xe631" name="SP_DS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
+ <reg32 offset="0xe640" name="SP_GS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
+ <reg32 offset="0xe65b" name="UNKNOWN_E65B"/>
+ <reg32 offset="0xe65c" name="SP_GS_OBJ_START_LO"/>
+ <reg32 offset="0xe65d" name="SP_GS_OBJ_START_HI"/>
+ <reg32 offset="0xe65e" name="SP_GS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
+ <reg64 offset="0xe65f" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32"/>
+ <reg32 offset="0xe661" name="SP_GS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
+
+ <reg32 offset="0xe704" name="TPL1_TP_RAS_MSAA_CNTL">
+ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
+ </reg32>
+ <reg32 offset="0xe705" name="TPL1_TP_DEST_MSAA_CNTL">
+ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
+ <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
+ </reg32>
+ <!-- either blob is doing it wrong, or this is not per-stage anymore: -->
+ <reg32 offset="0xe706" name="TPL1_TP_BORDER_COLOR_BASE_ADDR_LO"/>
+ <reg32 offset="0xe707" name="TPL1_TP_BORDER_COLOR_BASE_ADDR_HI"/>
+
+ <!--
+ so these have the same info that is normally in the CP_LOAD_STATE
+ packets.. not sure if they are normally written by pm4/me or if the
+ CP_LOAD_STATE mechanism is deprecated?
+ -->
+ <reg32 offset="0xe700" name="TPL1_VS_TEX_COUNT" type="uint"/>
+ <reg32 offset="0xe701" name="TPL1_HS_TEX_COUNT" type="uint"/>
+ <reg32 offset="0xe702" name="TPL1_DS_TEX_COUNT" type="uint"/>
+ <reg32 offset="0xe703" name="TPL1_GS_TEX_COUNT" type="uint"/>
+
+ <reg32 offset="0xe722" name="TPL1_VS_TEX_SAMP_LO"/>
+ <reg32 offset="0xe723" name="TPL1_VS_TEX_SAMP_HI"/>
+ <reg32 offset="0xe724" name="TPL1_HS_TEX_SAMP_LO"/>
+ <reg32 offset="0xe725" name="TPL1_HS_TEX_SAMP_HI"/>
+ <reg32 offset="0xe726" name="TPL1_DS_TEX_SAMP_LO"/>
+ <reg32 offset="0xe727" name="TPL1_DS_TEX_SAMP_HI"/>
+ <reg32 offset="0xe728" name="TPL1_GS_TEX_SAMP_LO"/>
+ <reg32 offset="0xe729" name="TPL1_GS_TEX_SAMP_HI"/>
+
+ <reg32 offset="0xe72a" name="TPL1_VS_TEX_CONST_LO"/>
+ <reg32 offset="0xe72b" name="TPL1_VS_TEX_CONST_HI"/>
+ <reg32 offset="0xe72c" name="TPL1_HS_TEX_CONST_LO"/>
+ <reg32 offset="0xe72d" name="TPL1_HS_TEX_CONST_HI"/>
+ <reg32 offset="0xe72e" name="TPL1_DS_TEX_CONST_LO"/>
+ <reg32 offset="0xe72f" name="TPL1_DS_TEX_CONST_HI"/>
+ <reg32 offset="0xe730" name="TPL1_GS_TEX_CONST_LO"/>
+ <reg32 offset="0xe731" name="TPL1_GS_TEX_CONST_HI"/>
+
+ <reg32 offset="0xe750" name="TPL1_FS_TEX_COUNT" type="uint"/>
+ <reg32 offset="0xe751" name="TPL1_CS_TEX_COUNT" type="uint"/>
+
+ <reg32 offset="0xe75a" name="TPL1_FS_TEX_SAMP_LO"/>
+ <reg32 offset="0xe75b" name="TPL1_FS_TEX_SAMP_HI"/>
+ <reg32 offset="0xe75c" name="TPL1_CS_TEX_SAMP_LO"/>
+ <reg32 offset="0xe75d" name="TPL1_CS_TEX_SAMP_HI"/>
+ <reg32 offset="0xe75e" name="TPL1_FS_TEX_CONST_LO"/>
+ <reg32 offset="0xe75f" name="TPL1_FS_TEX_CONST_HI"/>
+ <reg32 offset="0xe760" name="TPL1_CS_TEX_CONST_LO"/>
+ <reg32 offset="0xe761" name="TPL1_CS_TEX_CONST_HI"/>
+
+ <reg32 offset="0xe764" name="TPL1_TP_FS_ROTATION_CNTL"/>
+
+ <reg32 offset="0xe784" name="HLSQ_CONTROL_0_REG">
+ <!-- 24 or more (full size) GPRS and blob uses TWO_QUADS instead of FOUR_QUADS -->
+ <bitfield name="FSTHREADSIZE" pos="0" type="a3xx_threadsize"/>
+ <bitfield name="CSTHREADSIZE" pos="2" type="a3xx_threadsize"/>
+ </reg32>
+ <reg32 offset="0xe785" name="HLSQ_CONTROL_1_REG">
+ <!-- I guess.. not set exactly same as a4xx, but similar: -->
+ <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="5" type="uint"/>
+ </reg32>
+ <reg32 offset="0xe786" name="HLSQ_CONTROL_2_REG">
+ <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
+ <!-- SAMPLEID is loaded into a half-precision register: -->
+ <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0xe787" name="HLSQ_CONTROL_3_REG">
+ <!-- register loaded with position (bary.f) -->
+ <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0xe788" name="HLSQ_CONTROL_4_REG">
+ <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <!--
+ 0x020fffff for normal draws, 0x1f00000 for compute.. maybe what state
+ is enabled? We could probably try disabling different bits and see
+ what breaks to figure out which is what:
+ -->
+ <reg32 offset="0xe78a" name="HLSQ_UPDATE_CNTL"/>
+ <reg32 offset="0xe78b" name="HLSQ_VS_CONFIG" type="a5xx_xs_config"/>
+ <reg32 offset="0xe78c" name="HLSQ_FS_CONFIG" type="a5xx_xs_config"/>
+ <reg32 offset="0xe78d" name="HLSQ_HS_CONFIG" type="a5xx_xs_config"/>
+ <reg32 offset="0xe78e" name="HLSQ_DS_CONFIG" type="a5xx_xs_config"/>
+ <reg32 offset="0xe78f" name="HLSQ_GS_CONFIG" type="a5xx_xs_config"/>
+ <reg32 offset="0xe790" name="HLSQ_CS_CONFIG" type="a5xx_xs_config"/>
+ <reg32 offset="0xe791" name="HLSQ_VS_CNTL" type="a5xx_xs_cntl"/>
+ <reg32 offset="0xe792" name="HLSQ_FS_CNTL" type="a5xx_xs_cntl"/>
+ <reg32 offset="0xe793" name="HLSQ_HS_CNTL" type="a5xx_xs_cntl"/>
+ <reg32 offset="0xe794" name="HLSQ_DS_CNTL" type="a5xx_xs_cntl"/>
+ <reg32 offset="0xe795" name="HLSQ_GS_CNTL" type="a5xx_xs_cntl"/>
+ <reg32 offset="0xe796" name="HLSQ_CS_CNTL" type="a5xx_xs_cntl"/>
+ <reg32 offset="0xe7b9" name="HLSQ_CS_KERNEL_GROUP_X"/>
+ <reg32 offset="0xe7ba" name="HLSQ_CS_KERNEL_GROUP_Y"/>
+ <reg32 offset="0xe7bb" name="HLSQ_CS_KERNEL_GROUP_Z"/>
+ <reg32 offset="0xe7b0" name="HLSQ_CS_NDRANGE_0">
+ <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
+ <!-- localsize is value minus one: -->
+ <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
+ <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
+ <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xe7b1" name="HLSQ_CS_NDRANGE_1">
+ <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xe7b2" name="HLSQ_CS_NDRANGE_2">
+ <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xe7b3" name="HLSQ_CS_NDRANGE_3">
+ <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xe7b4" name="HLSQ_CS_NDRANGE_4">
+ <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xe7b5" name="HLSQ_CS_NDRANGE_5">
+ <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xe7b6" name="HLSQ_CS_NDRANGE_6">
+ <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xe7b7" name="HLSQ_CS_CNTL_0">
+ <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
+ <!-- possibly one of these is KERNELDIMCONSTID? -->
+ <!--
+ UNK0 appears to be NUMWGCONSTID.. but only works in certain
+ cases? Blob doesn't appear to use it, but instead emits
+ these via const (uniform). Which requires some shenanigans
+ for indirect draws when the offset is not strongly aligned
+ enough to use as EXT_SRC_ADDR in CP_LOAD_STATE
+ -->
+ <bitfield name="UNK0" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="UNK1" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0xe7b8" name="HLSQ_CS_CNTL_1"/>
+ <reg32 offset="0xe7c0" name="UNKNOWN_E7C0"/>
+ <reg32 offset="0xe7c3" name="HLSQ_VS_CONSTLEN" type="uint"/>
+ <reg32 offset="0xe7c4" name="HLSQ_VS_INSTRLEN" type="uint"/>
+ <reg32 offset="0xe7c5" name="UNKNOWN_E7C5"/>
+ <reg32 offset="0xe7c8" name="HLSQ_HS_CONSTLEN" type="uint"/>
+ <reg32 offset="0xe7c9" name="HLSQ_HS_INSTRLEN" type="uint"/>
+ <reg32 offset="0xe7ca" name="UNKNOWN_E7CA"/>
+ <reg32 offset="0xe7cd" name="HLSQ_DS_CONSTLEN" type="uint"/>
+ <reg32 offset="0xe7ce" name="HLSQ_DS_INSTRLEN" type="uint"/>
+ <reg32 offset="0xe7cf" name="UNKNOWN_E7CF"/>
+ <reg32 offset="0xe7d2" name="HLSQ_GS_CONSTLEN" type="uint"/>
+ <reg32 offset="0xe7d3" name="HLSQ_GS_INSTRLEN" type="uint"/>
+ <reg32 offset="0xe7d4" name="UNKNOWN_E7D4"/>
+ <reg32 offset="0xe7d7" name="HLSQ_FS_CONSTLEN" type="uint"/>
+ <reg32 offset="0xe7d8" name="HLSQ_FS_INSTRLEN" type="uint"/>
+ <reg32 offset="0xe7d9" name="UNKNOWN_E7D9"/>
+ <reg32 offset="0xe7dc" name="HLSQ_CS_CONSTLEN" type="uint"/>
+ <reg32 offset="0xe7dd" name="HLSQ_CS_INSTRLEN" type="uint"/>
+
+ <!--
+ Separate blit/2d or dma engine? Seems to get used sometimes for
+ texture uploads, where a4xx blob would use normal draws. Used
+ in render-mode 0x5..
+
+ Note seems mostly to be used for small blits, large blits seem
+ to use the CP_EVENT_WRITE:BLIT style of doing things. See
+ cubemap-0003 (40x40) vs cubemap-0004 (256x256).
+
+ see cube-0000, cubemap-(1..3 but not 4+), quad-textured-10..17
+
+ Other nearby registers are probably color formats, etc. The
+ blit coords are in CP packet. Play more w/ glTexSubImage2D()
+ to work it out.
+
+ Separate this into a different domain?? Would that help to
+ restrict which registers we dump based on mode?
+
+ regs 0x2000 to 0x2004 (plus all-zero regs 0x2005-0x2009) look
+ like 2nd source for blending? Used in mipmap generation.. but
+ maybe layout is a bit different. (Possibly used for reading
+ src via sampler, to enable scaling??) 0x2040 also used in this
+ case.
+ -->
+ <reg32 offset="0x2100" name="RB_2D_BLIT_CNTL"/> <!-- same as 0x2180 -->
+ <reg32 offset="0x2101" name="RB_2D_SRC_SOLID_DW0"/>
+ <reg32 offset="0x2102" name="RB_2D_SRC_SOLID_DW1"/>
+ <reg32 offset="0x2103" name="RB_2D_SRC_SOLID_DW2"/>
+ <reg32 offset="0x2104" name="RB_2D_SRC_SOLID_DW3"/>
+
+ <bitset name="a5xx_2d_surf_info" inline="yes">
+ <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
+ <bitfield name="TILE_MODE" low="8" high="9" type="a5xx_tile_mode"/>
+ <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
+ <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
+ <bitfield name="FLAGS" pos="12" type="boolean"/>
+ <bitfield name="SRGB" pos="13" type="boolean"/>
+ </bitset>
+
+ <reg32 offset="0x2107" name="RB_2D_SRC_INFO" type="a5xx_2d_surf_info"/>
+ <reg32 offset="0x2108" name="RB_2D_SRC_LO"/>
+ <reg32 offset="0x2109" name="RB_2D_SRC_HI"/>
+ <reg32 offset="0x210a" name="RB_2D_SRC_SIZE">
+ <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
+ <bitfield name="ARRAY_PITCH" low="16" high="31" shr="6" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x2110" name="RB_2D_DST_INFO" type="a5xx_2d_surf_info"/>
+ <reg32 offset="0x2111" name="RB_2D_DST_LO"/>
+ <reg32 offset="0x2112" name="RB_2D_DST_HI"/>
+ <reg32 offset="0x2113" name="RB_2D_DST_SIZE">
+ <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
+ <bitfield name="ARRAY_PITCH" low="16" high="31" shr="6" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2140" name="RB_2D_SRC_FLAGS_LO"/>
+ <reg32 offset="0x2141" name="RB_2D_SRC_FLAGS_HI"/>
+ <reg32 offset="0x2142" name="RB_2D_SRC_FLAGS_PITCH" shr="6" type="uint"/>
+ <reg32 offset="0x2143" name="RB_2D_DST_FLAGS_LO"/>
+ <reg32 offset="0x2144" name="RB_2D_DST_FLAGS_HI"/>
+ <reg32 offset="0x2145" name="RB_2D_DST_FLAGS_PITCH" shr="6" type="uint"/>
+ <reg32 offset="0x2180" name="GRAS_2D_BLIT_CNTL"/> <!-- same as 0x2100 -->
+ <!-- looks same as 0x2107: -->
+ <reg32 offset="0x2181" name="GRAS_2D_SRC_INFO" type="a5xx_2d_surf_info"/>
+ <!-- looks same as 0x2110: -->
+ <reg32 offset="0x2182" name="GRAS_2D_DST_INFO" type="a5xx_2d_surf_info"/>
+<!--
+0x2100 and 0x2180 look like same thing (RB and GRAS versions)..
+ 0x86000000 for copy, 0x00000000 for fill?
+
+0x2184 0x9 for copy, 0x1 for blit (maybe bitmask of enabled src/dst???)
+ -->
+ <reg32 offset="0x2184" name="UNKNOWN_2184"/>
+</domain>
+
+<domain name="A5XX_TEX_SAMP" width="32">
+ <doc>Texture sampler dwords</doc>
+ <enum name="a5xx_tex_filter"> <!-- same as a4xx? -->
+ <value name="A5XX_TEX_NEAREST" value="0"/>
+ <value name="A5XX_TEX_LINEAR" value="1"/>
+ <value name="A5XX_TEX_ANISO" value="2"/>
+ </enum>
+ <enum name="a5xx_tex_clamp"> <!-- same as a4xx? -->
+ <value name="A5XX_TEX_REPEAT" value="0"/>
+ <value name="A5XX_TEX_CLAMP_TO_EDGE" value="1"/>
+ <value name="A5XX_TEX_MIRROR_REPEAT" value="2"/>
+ <value name="A5XX_TEX_CLAMP_TO_BORDER" value="3"/>
+ <value name="A5XX_TEX_MIRROR_CLAMP" value="4"/>
+ </enum>
+ <enum name="a5xx_tex_aniso"> <!-- same as a4xx? -->
+ <value name="A5XX_TEX_ANISO_1" value="0"/>
+ <value name="A5XX_TEX_ANISO_2" value="1"/>
+ <value name="A5XX_TEX_ANISO_4" value="2"/>
+ <value name="A5XX_TEX_ANISO_8" value="3"/>
+ <value name="A5XX_TEX_ANISO_16" value="4"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
+ <bitfield name="XY_MAG" low="1" high="2" type="a5xx_tex_filter"/>
+ <bitfield name="XY_MIN" low="3" high="4" type="a5xx_tex_filter"/>
+ <bitfield name="WRAP_S" low="5" high="7" type="a5xx_tex_clamp"/>
+ <bitfield name="WRAP_T" low="8" high="10" type="a5xx_tex_clamp"/>
+ <bitfield name="WRAP_R" low="11" high="13" type="a5xx_tex_clamp"/>
+ <bitfield name="ANISO" low="14" high="16" type="a5xx_tex_aniso"/>
+ <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
+ <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
+ <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
+ <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
+ <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
+ <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <!--
+ offset into border-color buffer? Blob always uses 0x80 for FS state
+ if both VS and FS have border-color.
+Seems like when both VS and FS have bcolor, one starts 0x300 after other..
+and 0x80 in TEX_SAMP.2 .. blob doesn't seem to be able to cope w/ multiple
+different border-color states per texture.. Looks something like:
+0000: 3f000000 00000000 00000000 3f800000 00008000 ffff0000 00004000 7fff0000
+0020: 00003800 3c000000 80100010 0000f008 ff000080 7f000040 c0000200 00800000
+0040: 00003800 3c000000 00000000 00000000 00000000 00000000 00000000 00000000
+*
+0300: 3f800000 3f800000 3f800000 3f800000 ffffffff ffffffff 7fff7fff 7fff7fff
+0320: 3c003c00 3c003c00 ffffffff 0000ffff ffffffff 7f7f7f7f ffffffff 00ffffff
+0340: 3c003c00 3c003c00 00000000 00000000 00000000 00000000 00000000 00000000
+
+ -->
+ <bitfield name="BCOLOR_OFFSET" low="7" high="31"/>
+ </reg32>
+ <reg32 offset="3" name="3"/>
+</domain>
+
+<domain name="A5XX_TEX_CONST" width="32">
+ <doc>Texture constant dwords</doc>
+ <enum name="a5xx_tex_swiz"> <!-- same as a4xx? -->
+ <value name="A5XX_TEX_X" value="0"/>
+ <value name="A5XX_TEX_Y" value="1"/>
+ <value name="A5XX_TEX_Z" value="2"/>
+ <value name="A5XX_TEX_W" value="3"/>
+ <value name="A5XX_TEX_ZERO" value="4"/>
+ <value name="A5XX_TEX_ONE" value="5"/>
+ </enum>
+ <enum name="a5xx_tex_type"> <!-- same as a4xx? -->
+ <value name="A5XX_TEX_1D" value="0"/>
+ <value name="A5XX_TEX_2D" value="1"/>
+ <value name="A5XX_TEX_CUBE" value="2"/>
+ <value name="A5XX_TEX_3D" value="3"/>
+ <value name="A5XX_TEX_BUFFER" value="4"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="TILE_MODE" low="0" high="1" type="a5xx_tile_mode"/>
+ <bitfield name="SRGB" pos="2" type="boolean"/>
+ <bitfield name="SWIZ_X" low="4" high="6" type="a5xx_tex_swiz"/>
+ <bitfield name="SWIZ_Y" low="7" high="9" type="a5xx_tex_swiz"/>
+ <bitfield name="SWIZ_Z" low="10" high="12" type="a5xx_tex_swiz"/>
+ <bitfield name="SWIZ_W" low="13" high="15" type="a5xx_tex_swiz"/>
+ <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
+ <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
+ <bitfield name="FMT" low="22" high="29" type="a5xx_tex_fmt"/>
+ <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="WIDTH" low="0" high="14" type="uint"/>
+ <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <!--
+ b4 and b31 set for buffer/ssbo case, in which case low 15 bits
+ of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
+
+ b31 is probably the 'BUFFER' bit.. it is the one that changes
+ behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071
+ -->
+ <bitfield name="BUFFER" pos="4" type="boolean"/>
+ <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
+ <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
+ <doc>Pitch in bytes (so actually stride)</doc>
+ <bitfield name="PITCH" low="7" high="28" type="uint"/>
+ <bitfield name="TYPE" low="29" high="31" type="a5xx_tex_type"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <!--
+ ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
+ for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
+ layer size at the point that it stops being reduced moving to
+ higher (smaller) mipmap levels
+ -->
+ <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
+ <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
+ <!--
+ by default levels with w < 16 are linear
+ TILE_ALL makes all levels have tiling
+ seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
+ -->
+ <bitfield name="TILE_ALL" pos="27" type="boolean"/>
+ <bitfield name="FLAG" pos="28" type="boolean"/>
+ </reg32>
+ <reg32 offset="4" name="4">
+ <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
+ </reg32>
+ <reg32 offset="5" name="5">
+ <bitfield name="BASE_HI" low="0" high="16"/>
+ <bitfield name="DEPTH" low="17" high="29" type="uint"/>
+ </reg32>
+ <reg32 offset="6" name="6"/>
+ <reg32 offset="7" name="7"/>
+ <reg32 offset="8" name="8"/>
+ <reg32 offset="9" name="9"/>
+ <reg32 offset="10" name="10"/>
+ <reg32 offset="11" name="11"/>
+</domain>
+
+<!--
+Note the "SSBO" state blocks are actually used for both images and SSBOs,
+naming is just because I r/e'd SSBOs first. I should probably come up
+with a better name.
+-->
+<domain name="A5XX_SSBO_0" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <!-- no BASE_HI here? Maybe this is only used for 32b mode? -->
+ <doc>Pitch in bytes (so actually stride)</doc>
+ <bitfield name="PITCH" low="0" high="21" type="uint"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="ARRAY_PITCH" low="12" high="25" shr="12" type="uint"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <!-- bytes per pixel: -->
+ <bitfield name="CPP" low="0" high="5" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="A5XX_SSBO_1" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="FMT" low="8" high="15" type="a5xx_tex_fmt"/>
+ <bitfield name="WIDTH" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="HEIGHT" low="0" high="15" type="uint"/>
+ <bitfield name="DEPTH" low="16" high="31" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="A5XX_SSBO_2" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="BASE_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="BASE_HI" low="0" high="31"/>
+ </reg32>
+</domain>
+
+<domain name="A5XX_UBO" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="BASE_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="BASE_HI" low="0" high="16"/>
+ <!-- size probably in high bits -->
+ </reg32>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
new file mode 100644
index 000000000000..2dfe6913ab4f
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
@@ -0,0 +1,5011 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+<import file="adreno/adreno_common.xml"/>
+<import file="adreno/adreno_pm4.xml"/>
+
+<!--
+Each register that is actually being used by driver should have "usage" defined,
+currently there are following usages:
+- "cmd" - the register is used outside of renderpass and blits,
+ roughly corresponds to registers used in ib1 for Freedreno
+- "rp_blit" - the register is used inside renderpass or blits
+ (ib2 for Freedreno)
+
+It is expected that register with "cmd" usage may be written into only at
+the start of the command buffer (ib1), while "rp_blit" usage indicates that register
+is either overwritten by renderpass/blit (ib2) or not used if not overwritten
+by a particular renderpass/blit.
+-->
+
+<!-- these might be same as a5xx -->
+<enum name="a6xx_tile_mode">
+ <value name="TILE6_LINEAR" value="0"/>
+ <value name="TILE6_2" value="2"/>
+ <value name="TILE6_3" value="3"/>
+</enum>
+
+<enum name="a6xx_format">
+ <value value="0x02" name="FMT6_A8_UNORM"/>
+ <value value="0x03" name="FMT6_8_UNORM"/>
+ <value value="0x04" name="FMT6_8_SNORM"/>
+ <value value="0x05" name="FMT6_8_UINT"/>
+ <value value="0x06" name="FMT6_8_SINT"/>
+
+ <value value="0x08" name="FMT6_4_4_4_4_UNORM"/>
+ <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>
+ <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
+ <value value="0x0e" name="FMT6_5_6_5_UNORM"/>
+
+ <value value="0x0f" name="FMT6_8_8_UNORM"/>
+ <value value="0x10" name="FMT6_8_8_SNORM"/>
+ <value value="0x11" name="FMT6_8_8_UINT"/>
+ <value value="0x12" name="FMT6_8_8_SINT"/>
+ <value value="0x13" name="FMT6_L8_A8_UNORM"/>
+
+ <value value="0x15" name="FMT6_16_UNORM"/>
+ <value value="0x16" name="FMT6_16_SNORM"/>
+ <value value="0x17" name="FMT6_16_FLOAT"/>
+ <value value="0x18" name="FMT6_16_UINT"/>
+ <value value="0x19" name="FMT6_16_SINT"/>
+
+ <value value="0x21" name="FMT6_8_8_8_UNORM"/>
+ <value value="0x22" name="FMT6_8_8_8_SNORM"/>
+ <value value="0x23" name="FMT6_8_8_8_UINT"/>
+ <value value="0x24" name="FMT6_8_8_8_SINT"/>
+
+ <value value="0x30" name="FMT6_8_8_8_8_UNORM"/>
+ <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
+ <value value="0x32" name="FMT6_8_8_8_8_SNORM"/>
+ <value value="0x33" name="FMT6_8_8_8_8_UINT"/>
+ <value value="0x34" name="FMT6_8_8_8_8_SINT"/>
+
+ <value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/>
+
+ <value value="0x36" name="FMT6_10_10_10_2_UNORM"/>
+ <value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/>
+ <value value="0x39" name="FMT6_10_10_10_2_SNORM"/>
+ <value value="0x3a" name="FMT6_10_10_10_2_UINT"/>
+ <value value="0x3b" name="FMT6_10_10_10_2_SINT"/>
+
+ <value value="0x42" name="FMT6_11_11_10_FLOAT"/>
+
+ <value value="0x43" name="FMT6_16_16_UNORM"/>
+ <value value="0x44" name="FMT6_16_16_SNORM"/>
+ <value value="0x45" name="FMT6_16_16_FLOAT"/>
+ <value value="0x46" name="FMT6_16_16_UINT"/>
+ <value value="0x47" name="FMT6_16_16_SINT"/>
+
+ <value value="0x48" name="FMT6_32_UNORM"/>
+ <value value="0x49" name="FMT6_32_SNORM"/>
+ <value value="0x4a" name="FMT6_32_FLOAT"/>
+ <value value="0x4b" name="FMT6_32_UINT"/>
+ <value value="0x4c" name="FMT6_32_SINT"/>
+ <value value="0x4d" name="FMT6_32_FIXED"/>
+
+ <value value="0x58" name="FMT6_16_16_16_UNORM"/>
+ <value value="0x59" name="FMT6_16_16_16_SNORM"/>
+ <value value="0x5a" name="FMT6_16_16_16_FLOAT"/>
+ <value value="0x5b" name="FMT6_16_16_16_UINT"/>
+ <value value="0x5c" name="FMT6_16_16_16_SINT"/>
+
+ <value value="0x60" name="FMT6_16_16_16_16_UNORM"/>
+ <value value="0x61" name="FMT6_16_16_16_16_SNORM"/>
+ <value value="0x62" name="FMT6_16_16_16_16_FLOAT"/>
+ <value value="0x63" name="FMT6_16_16_16_16_UINT"/>
+ <value value="0x64" name="FMT6_16_16_16_16_SINT"/>
+
+ <value value="0x65" name="FMT6_32_32_UNORM"/>
+ <value value="0x66" name="FMT6_32_32_SNORM"/>
+ <value value="0x67" name="FMT6_32_32_FLOAT"/>
+ <value value="0x68" name="FMT6_32_32_UINT"/>
+ <value value="0x69" name="FMT6_32_32_SINT"/>
+ <value value="0x6a" name="FMT6_32_32_FIXED"/>
+
+ <value value="0x70" name="FMT6_32_32_32_UNORM"/>
+ <value value="0x71" name="FMT6_32_32_32_SNORM"/>
+ <value value="0x72" name="FMT6_32_32_32_UINT"/>
+ <value value="0x73" name="FMT6_32_32_32_SINT"/>
+ <value value="0x74" name="FMT6_32_32_32_FLOAT"/>
+ <value value="0x75" name="FMT6_32_32_32_FIXED"/>
+
+ <value value="0x80" name="FMT6_32_32_32_32_UNORM"/>
+ <value value="0x81" name="FMT6_32_32_32_32_SNORM"/>
+ <value value="0x82" name="FMT6_32_32_32_32_FLOAT"/>
+ <value value="0x83" name="FMT6_32_32_32_32_UINT"/>
+ <value value="0x84" name="FMT6_32_32_32_32_SINT"/>
+ <value value="0x85" name="FMT6_32_32_32_32_FIXED"/>
+
+ <value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY -->
+ <value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV -->
+ <value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 -->
+ <value value="0x8f" name="FMT6_NV21"/>
+ <value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 -->
+
+ <value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/>
+
+ <!-- Note: tiling/UBWC for these may be different from equivalent formats
+ For example FMT6_NV12_Y is not compatible with FMT6_8_UNORM
+ -->
+ <value value="0x94" name="FMT6_NV12_Y"/>
+ <value value="0x95" name="FMT6_NV12_UV"/>
+ <value value="0x96" name="FMT6_NV12_VU"/>
+ <value value="0x97" name="FMT6_NV12_4R"/>
+ <value value="0x98" name="FMT6_NV12_4R_Y"/>
+ <value value="0x99" name="FMT6_NV12_4R_UV"/>
+ <value value="0x9a" name="FMT6_P010"/>
+ <value value="0x9b" name="FMT6_P010_Y"/>
+ <value value="0x9c" name="FMT6_P010_UV"/>
+ <value value="0x9d" name="FMT6_TP10"/>
+ <value value="0x9e" name="FMT6_TP10_Y"/>
+ <value value="0x9f" name="FMT6_TP10_UV"/>
+
+ <value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/>
+
+ <value value="0xab" name="FMT6_ETC2_RG11_UNORM"/>
+ <value value="0xac" name="FMT6_ETC2_RG11_SNORM"/>
+ <value value="0xad" name="FMT6_ETC2_R11_UNORM"/>
+ <value value="0xae" name="FMT6_ETC2_R11_SNORM"/>
+ <value value="0xaf" name="FMT6_ETC1"/>
+ <value value="0xb0" name="FMT6_ETC2_RGB8"/>
+ <value value="0xb1" name="FMT6_ETC2_RGBA8"/>
+ <value value="0xb2" name="FMT6_ETC2_RGB8A1"/>
+ <value value="0xb3" name="FMT6_DXT1"/>
+ <value value="0xb4" name="FMT6_DXT3"/>
+ <value value="0xb5" name="FMT6_DXT5"/>
+ <value value="0xb7" name="FMT6_RGTC1_UNORM"/>
+ <value value="0xb8" name="FMT6_RGTC1_SNORM"/>
+ <value value="0xbb" name="FMT6_RGTC2_UNORM"/>
+ <value value="0xbc" name="FMT6_RGTC2_SNORM"/>
+ <value value="0xbe" name="FMT6_BPTC_UFLOAT"/>
+ <value value="0xbf" name="FMT6_BPTC_FLOAT"/>
+ <value value="0xc0" name="FMT6_BPTC"/>
+ <value value="0xc1" name="FMT6_ASTC_4x4"/>
+ <value value="0xc2" name="FMT6_ASTC_5x4"/>
+ <value value="0xc3" name="FMT6_ASTC_5x5"/>
+ <value value="0xc4" name="FMT6_ASTC_6x5"/>
+ <value value="0xc5" name="FMT6_ASTC_6x6"/>
+ <value value="0xc6" name="FMT6_ASTC_8x5"/>
+ <value value="0xc7" name="FMT6_ASTC_8x6"/>
+ <value value="0xc8" name="FMT6_ASTC_8x8"/>
+ <value value="0xc9" name="FMT6_ASTC_10x5"/>
+ <value value="0xca" name="FMT6_ASTC_10x6"/>
+ <value value="0xcb" name="FMT6_ASTC_10x8"/>
+ <value value="0xcc" name="FMT6_ASTC_10x10"/>
+ <value value="0xcd" name="FMT6_ASTC_12x10"/>
+ <value value="0xce" name="FMT6_ASTC_12x12"/>
+
+ <!-- for sampling stencil (integer, 2nd channel), not available on a630 -->
+ <value value="0xea" name="FMT6_Z24_UINT_S8_UINT"/>
+
+ <!-- Not a hw enum, used internally in driver -->
+ <value value="0xff" name="FMT6_NONE"/>
+
+</enum>
+
+<!-- probably same as a5xx -->
+<enum name="a6xx_polygon_mode">
+ <value name="POLYMODE6_POINTS" value="1"/>
+ <value name="POLYMODE6_LINES" value="2"/>
+ <value name="POLYMODE6_TRIANGLES" value="3"/>
+</enum>
+
+<enum name="a6xx_depth_format">
+ <value name="DEPTH6_NONE" value="0"/>
+ <value name="DEPTH6_16" value="1"/>
+ <value name="DEPTH6_24_8" value="2"/>
+ <value name="DEPTH6_32" value="4"/>
+</enum>
+
+<bitset name="a6x_cp_protect" inline="yes">
+ <bitfield name="BASE_ADDR" low="0" high="17"/>
+ <bitfield name="MASK_LEN" low="18" high="30"/>
+ <bitfield name="READ" pos="31" type="boolean"/>
+</bitset>
+
+<enum name="a6xx_shader_id">
+ <value value="0x9" name="A6XX_TP0_TMO_DATA"/>
+ <value value="0xa" name="A6XX_TP0_SMO_DATA"/>
+ <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
+ <value value="0x19" name="A6XX_TP1_TMO_DATA"/>
+ <value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
+ <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
+ <value value="0x29" name="A6XX_SP_INST_DATA"/>
+ <value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
+ <value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
+ <value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
+ <value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
+ <value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
+ <value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
+ <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
+ <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
+ <value value="0x32" name="A6XX_SP_UAV_DATA"/>
+ <value value="0x33" name="A6XX_SP_INST_TAG"/>
+ <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
+ <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
+ <value value="0x36" name="A6XX_SP_SMO_TAG"/>
+ <value value="0x37" name="A6XX_SP_STATE_DATA"/>
+ <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
+ <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
+ <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
+ <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
+ <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
+ <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
+ <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
+ <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
+ <value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
+ <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
+ <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
+ <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
+ <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
+ <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
+ <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
+ <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
+ <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
+ <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
+ <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
+ <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
+ <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
+ <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
+ <value value="0x70" name="A6XX_SP_LB_6_DATA"/>
+ <value value="0x71" name="A6XX_SP_LB_7_DATA"/>
+ <value value="0x73" name="A6XX_HLSQ_INST_RAM_1"/>
+</enum>
+
+<enum name="a7xx_statetype_id">
+ <value value="0" name="A7XX_TP0_NCTX_REG"/>
+ <value value="1" name="A7XX_TP0_CTX0_3D_CVS_REG"/>
+ <value value="2" name="A7XX_TP0_CTX0_3D_CPS_REG"/>
+ <value value="3" name="A7XX_TP0_CTX1_3D_CVS_REG"/>
+ <value value="4" name="A7XX_TP0_CTX1_3D_CPS_REG"/>
+ <value value="5" name="A7XX_TP0_CTX2_3D_CPS_REG"/>
+ <value value="6" name="A7XX_TP0_CTX3_3D_CPS_REG"/>
+ <value value="9" name="A7XX_TP0_TMO_DATA"/>
+ <value value="10" name="A7XX_TP0_SMO_DATA"/>
+ <value value="11" name="A7XX_TP0_MIPMAP_BASE_DATA"/>
+ <value value="32" name="A7XX_SP_NCTX_REG"/>
+ <value value="33" name="A7XX_SP_CTX0_3D_CVS_REG"/>
+ <value value="34" name="A7XX_SP_CTX0_3D_CPS_REG"/>
+ <value value="35" name="A7XX_SP_CTX1_3D_CVS_REG"/>
+ <value value="36" name="A7XX_SP_CTX1_3D_CPS_REG"/>
+ <value value="37" name="A7XX_SP_CTX2_3D_CPS_REG"/>
+ <value value="38" name="A7XX_SP_CTX3_3D_CPS_REG"/>
+ <value value="39" name="A7XX_SP_INST_DATA"/>
+ <value value="40" name="A7XX_SP_INST_DATA_1"/>
+ <value value="41" name="A7XX_SP_LB_0_DATA"/>
+ <value value="42" name="A7XX_SP_LB_1_DATA"/>
+ <value value="43" name="A7XX_SP_LB_2_DATA"/>
+ <value value="44" name="A7XX_SP_LB_3_DATA"/>
+ <value value="45" name="A7XX_SP_LB_4_DATA"/>
+ <value value="46" name="A7XX_SP_LB_5_DATA"/>
+ <value value="47" name="A7XX_SP_LB_6_DATA"/>
+ <value value="48" name="A7XX_SP_LB_7_DATA"/>
+ <value value="49" name="A7XX_SP_CB_RAM"/>
+ <value value="50" name="A7XX_SP_LB_13_DATA"/>
+ <value value="51" name="A7XX_SP_LB_14_DATA"/>
+ <value value="52" name="A7XX_SP_INST_TAG"/>
+ <value value="53" name="A7XX_SP_INST_DATA_2"/>
+ <value value="54" name="A7XX_SP_TMO_TAG"/>
+ <value value="55" name="A7XX_SP_SMO_TAG"/>
+ <value value="56" name="A7XX_SP_STATE_DATA"/>
+ <value value="57" name="A7XX_SP_HWAVE_RAM"/>
+ <value value="58" name="A7XX_SP_L0_INST_BUF"/>
+ <value value="59" name="A7XX_SP_LB_8_DATA"/>
+ <value value="60" name="A7XX_SP_LB_9_DATA"/>
+ <value value="61" name="A7XX_SP_LB_10_DATA"/>
+ <value value="62" name="A7XX_SP_LB_11_DATA"/>
+ <value value="63" name="A7XX_SP_LB_12_DATA"/>
+ <value value="64" name="A7XX_HLSQ_DATAPATH_DSTR_META"/>
+ <value value="67" name="A7XX_HLSQ_L2STC_TAG_RAM"/>
+ <value value="68" name="A7XX_HLSQ_L2STC_INFO_CMD"/>
+ <value value="69" name="A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG"/>
+ <value value="70" name="A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG"/>
+ <value value="71" name="A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM"/>
+ <value value="72" name="A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM"/>
+ <value value="73" name="A7XX_HLSQ_CHUNK_CVS_RAM"/>
+ <value value="74" name="A7XX_HLSQ_CHUNK_CPS_RAM"/>
+ <value value="75" name="A7XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
+ <value value="76" name="A7XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
+ <value value="77" name="A7XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
+ <value value="78" name="A7XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
+ <value value="79" name="A7XX_HLSQ_CVS_MISC_RAM"/>
+ <value value="80" name="A7XX_HLSQ_CPS_MISC_RAM"/>
+ <value value="81" name="A7XX_HLSQ_CPS_MISC_RAM_1"/>
+ <value value="82" name="A7XX_HLSQ_INST_RAM"/>
+ <value value="83" name="A7XX_HLSQ_GFX_CVS_CONST_RAM"/>
+ <value value="84" name="A7XX_HLSQ_GFX_CPS_CONST_RAM"/>
+ <value value="85" name="A7XX_HLSQ_CVS_MISC_RAM_TAG"/>
+ <value value="86" name="A7XX_HLSQ_CPS_MISC_RAM_TAG"/>
+ <value value="87" name="A7XX_HLSQ_INST_RAM_TAG"/>
+ <value value="88" name="A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
+ <value value="89" name="A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
+ <value value="90" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM"/>
+ <value value="91" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG"/>
+ <value value="92" name="A7XX_HLSQ_INST_RAM_1"/>
+ <value value="93" name="A7XX_HLSQ_STPROC_META"/>
+ <value value="94" name="A7XX_HLSQ_BV_BE_META"/>
+ <value value="95" name="A7XX_HLSQ_INST_RAM_2"/>
+ <value value="96" name="A7XX_HLSQ_DATAPATH_META"/>
+ <value value="97" name="A7XX_HLSQ_FRONTEND_META"/>
+ <value value="98" name="A7XX_HLSQ_INDIRECT_META"/>
+ <value value="99" name="A7XX_HLSQ_BACKEND_META"/>
+</enum>
+
+<enum name="a6xx_debugbus_id">
+ <value value="0x1" name="A6XX_DBGBUS_CP"/>
+ <value value="0x2" name="A6XX_DBGBUS_RBBM"/>
+ <value value="0x3" name="A6XX_DBGBUS_VBIF"/>
+ <value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
+ <value value="0x5" name="A6XX_DBGBUS_UCHE"/>
+ <value value="0x6" name="A6XX_DBGBUS_DPM"/>
+ <value value="0x7" name="A6XX_DBGBUS_TESS"/>
+ <value value="0x8" name="A6XX_DBGBUS_PC"/>
+ <value value="0x9" name="A6XX_DBGBUS_VFDP"/>
+ <value value="0xa" name="A6XX_DBGBUS_VPC"/>
+ <value value="0xb" name="A6XX_DBGBUS_TSE"/>
+ <value value="0xc" name="A6XX_DBGBUS_RAS"/>
+ <value value="0xd" name="A6XX_DBGBUS_VSC"/>
+ <value value="0xe" name="A6XX_DBGBUS_COM"/>
+ <value value="0x10" name="A6XX_DBGBUS_LRZ"/>
+ <value value="0x11" name="A6XX_DBGBUS_A2D"/>
+ <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
+ <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
+ <value value="0x14" name="A6XX_DBGBUS_RBP"/>
+ <value value="0x15" name="A6XX_DBGBUS_DCS"/>
+ <value value="0x16" name="A6XX_DBGBUS_DBGC"/>
+ <value value="0x17" name="A6XX_DBGBUS_CX"/>
+ <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
+ <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
+ <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
+ <value value="0x1d" name="A6XX_DBGBUS_GPC"/>
+ <value value="0x1e" name="A6XX_DBGBUS_LARC"/>
+ <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
+ <value value="0x20" name="A6XX_DBGBUS_RB_0"/>
+ <value value="0x21" name="A6XX_DBGBUS_RB_1"/>
+ <value value="0x22" name="A6XX_DBGBUS_RB_2"/>
+ <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
+ <value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
+ <value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
+ <value value="0x2a" name="A6XX_DBGBUS_CCU_2"/>
+ <value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
+ <value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
+ <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
+ <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
+ <value value="0x3c" name="A6XX_DBGBUS_VFD_4"/>
+ <value value="0x3d" name="A6XX_DBGBUS_VFD_5"/>
+ <value value="0x40" name="A6XX_DBGBUS_SP_0"/>
+ <value value="0x41" name="A6XX_DBGBUS_SP_1"/>
+ <value value="0x42" name="A6XX_DBGBUS_SP_2"/>
+ <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
+ <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
+ <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
+ <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
+ <value value="0x4c" name="A6XX_DBGBUS_TPL1_4"/>
+ <value value="0x4d" name="A6XX_DBGBUS_TPL1_5"/>
+ <value value="0x58" name="A6XX_DBGBUS_SPTP_0"/>
+ <value value="0x59" name="A6XX_DBGBUS_SPTP_1"/>
+ <value value="0x5a" name="A6XX_DBGBUS_SPTP_2"/>
+ <value value="0x5b" name="A6XX_DBGBUS_SPTP_3"/>
+ <value value="0x5c" name="A6XX_DBGBUS_SPTP_4"/>
+ <value value="0x5d" name="A6XX_DBGBUS_SPTP_5"/>
+</enum>
+
+<enum name="a7xx_state_location">
+ <value value="0" name="A7XX_HLSQ_STATE"/>
+ <value value="1" name="A7XX_HLSQ_DP"/>
+ <value value="2" name="A7XX_SP_TOP"/>
+ <value value="3" name="A7XX_USPTP"/>
+ <value value="4" name="A7XX_HLSQ_DP_STR"/>
+</enum>
+
+<enum name="a7xx_pipe">
+ <value value="0" name="A7XX_PIPE_NONE"/>
+ <value value="1" name="A7XX_PIPE_BR"/>
+ <value value="2" name="A7XX_PIPE_BV"/>
+ <value value="3" name="A7XX_PIPE_LPAC"/>
+</enum>
+
+<enum name="a7xx_cluster">
+ <value value="0" name="A7XX_CLUSTER_NONE"/>
+ <value value="1" name="A7XX_CLUSTER_FE"/>
+ <value value="2" name="A7XX_CLUSTER_SP_VS"/>
+ <value value="3" name="A7XX_CLUSTER_PC_VS"/>
+ <value value="4" name="A7XX_CLUSTER_GRAS"/>
+ <value value="5" name="A7XX_CLUSTER_SP_PS"/>
+ <value value="6" name="A7XX_CLUSTER_VPC_PS"/>
+ <value value="7" name="A7XX_CLUSTER_PS"/>
+</enum>
+
+<enum name="a7xx_debugbus_id">
+ <value value="1" name="A7XX_DBGBUS_CP_0_0"/>
+ <value value="2" name="A7XX_DBGBUS_CP_0_1"/>
+ <value value="3" name="A7XX_DBGBUS_RBBM"/>
+ <value value="5" name="A7XX_DBGBUS_GBIF_GX"/>
+ <value value="6" name="A7XX_DBGBUS_GBIF_CX"/>
+ <value value="7" name="A7XX_DBGBUS_HLSQ"/>
+ <value value="9" name="A7XX_DBGBUS_UCHE_0"/>
+ <value value="10" name="A7XX_DBGBUS_UCHE_1"/>
+ <value value="13" name="A7XX_DBGBUS_TESS_BR"/>
+ <value value="14" name="A7XX_DBGBUS_TESS_BV"/>
+ <value value="17" name="A7XX_DBGBUS_PC_BR"/>
+ <value value="18" name="A7XX_DBGBUS_PC_BV"/>
+ <value value="21" name="A7XX_DBGBUS_VFDP_BR"/>
+ <value value="22" name="A7XX_DBGBUS_VFDP_BV"/>
+ <value value="25" name="A7XX_DBGBUS_VPC_BR"/>
+ <value value="26" name="A7XX_DBGBUS_VPC_BV"/>
+ <value value="29" name="A7XX_DBGBUS_TSE_BR"/>
+ <value value="30" name="A7XX_DBGBUS_TSE_BV"/>
+ <value value="33" name="A7XX_DBGBUS_RAS_BR"/>
+ <value value="34" name="A7XX_DBGBUS_RAS_BV"/>
+ <value value="37" name="A7XX_DBGBUS_VSC"/>
+ <value value="39" name="A7XX_DBGBUS_COM_0"/>
+ <value value="43" name="A7XX_DBGBUS_LRZ_BR"/>
+ <value value="44" name="A7XX_DBGBUS_LRZ_BV"/>
+ <value value="47" name="A7XX_DBGBUS_UFC_0"/>
+ <value value="48" name="A7XX_DBGBUS_UFC_1"/>
+ <value value="55" name="A7XX_DBGBUS_GMU_GX"/>
+ <value value="59" name="A7XX_DBGBUS_DBGC"/>
+ <value value="60" name="A7XX_DBGBUS_CX"/>
+ <value value="61" name="A7XX_DBGBUS_GMU_CX"/>
+ <value value="62" name="A7XX_DBGBUS_GPC_BR"/>
+ <value value="63" name="A7XX_DBGBUS_GPC_BV"/>
+ <value value="66" name="A7XX_DBGBUS_LARC"/>
+ <value value="68" name="A7XX_DBGBUS_HLSQ_SPTP"/>
+ <value value="70" name="A7XX_DBGBUS_RB_0"/>
+ <value value="71" name="A7XX_DBGBUS_RB_1"/>
+ <value value="72" name="A7XX_DBGBUS_RB_2"/>
+ <value value="73" name="A7XX_DBGBUS_RB_3"/>
+ <value value="74" name="A7XX_DBGBUS_RB_4"/>
+ <value value="75" name="A7XX_DBGBUS_RB_5"/>
+ <value value="102" name="A7XX_DBGBUS_UCHE_WRAPPER"/>
+ <value value="106" name="A7XX_DBGBUS_CCU_0"/>
+ <value value="107" name="A7XX_DBGBUS_CCU_1"/>
+ <value value="108" name="A7XX_DBGBUS_CCU_2"/>
+ <value value="109" name="A7XX_DBGBUS_CCU_3"/>
+ <value value="110" name="A7XX_DBGBUS_CCU_4"/>
+ <value value="111" name="A7XX_DBGBUS_CCU_5"/>
+ <value value="138" name="A7XX_DBGBUS_VFD_BR_0"/>
+ <value value="139" name="A7XX_DBGBUS_VFD_BR_1"/>
+ <value value="140" name="A7XX_DBGBUS_VFD_BR_2"/>
+ <value value="141" name="A7XX_DBGBUS_VFD_BR_3"/>
+ <value value="142" name="A7XX_DBGBUS_VFD_BR_4"/>
+ <value value="143" name="A7XX_DBGBUS_VFD_BR_5"/>
+ <value value="144" name="A7XX_DBGBUS_VFD_BR_6"/>
+ <value value="145" name="A7XX_DBGBUS_VFD_BR_7"/>
+ <value value="202" name="A7XX_DBGBUS_VFD_BV_0"/>
+ <value value="203" name="A7XX_DBGBUS_VFD_BV_1"/>
+ <value value="204" name="A7XX_DBGBUS_VFD_BV_2"/>
+ <value value="205" name="A7XX_DBGBUS_VFD_BV_3"/>
+ <value value="234" name="A7XX_DBGBUS_USP_0"/>
+ <value value="235" name="A7XX_DBGBUS_USP_1"/>
+ <value value="236" name="A7XX_DBGBUS_USP_2"/>
+ <value value="237" name="A7XX_DBGBUS_USP_3"/>
+ <value value="238" name="A7XX_DBGBUS_USP_4"/>
+ <value value="239" name="A7XX_DBGBUS_USP_5"/>
+ <value value="266" name="A7XX_DBGBUS_TP_0"/>
+ <value value="267" name="A7XX_DBGBUS_TP_1"/>
+ <value value="268" name="A7XX_DBGBUS_TP_2"/>
+ <value value="269" name="A7XX_DBGBUS_TP_3"/>
+ <value value="270" name="A7XX_DBGBUS_TP_4"/>
+ <value value="271" name="A7XX_DBGBUS_TP_5"/>
+ <value value="272" name="A7XX_DBGBUS_TP_6"/>
+ <value value="273" name="A7XX_DBGBUS_TP_7"/>
+ <value value="274" name="A7XX_DBGBUS_TP_8"/>
+ <value value="275" name="A7XX_DBGBUS_TP_9"/>
+ <value value="276" name="A7XX_DBGBUS_TP_10"/>
+ <value value="277" name="A7XX_DBGBUS_TP_11"/>
+ <value value="330" name="A7XX_DBGBUS_USPTP_0"/>
+ <value value="331" name="A7XX_DBGBUS_USPTP_1"/>
+ <value value="332" name="A7XX_DBGBUS_USPTP_2"/>
+ <value value="333" name="A7XX_DBGBUS_USPTP_3"/>
+ <value value="334" name="A7XX_DBGBUS_USPTP_4"/>
+ <value value="335" name="A7XX_DBGBUS_USPTP_5"/>
+ <value value="336" name="A7XX_DBGBUS_USPTP_6"/>
+ <value value="337" name="A7XX_DBGBUS_USPTP_7"/>
+ <value value="338" name="A7XX_DBGBUS_USPTP_8"/>
+ <value value="339" name="A7XX_DBGBUS_USPTP_9"/>
+ <value value="340" name="A7XX_DBGBUS_USPTP_10"/>
+ <value value="341" name="A7XX_DBGBUS_USPTP_11"/>
+ <value value="396" name="A7XX_DBGBUS_CCHE_0"/>
+ <value value="397" name="A7XX_DBGBUS_CCHE_1"/>
+ <value value="398" name="A7XX_DBGBUS_CCHE_2"/>
+ <value value="408" name="A7XX_DBGBUS_VPC_DSTR_0"/>
+ <value value="409" name="A7XX_DBGBUS_VPC_DSTR_1"/>
+ <value value="410" name="A7XX_DBGBUS_VPC_DSTR_2"/>
+ <value value="411" name="A7XX_DBGBUS_HLSQ_DP_STR_0"/>
+ <value value="412" name="A7XX_DBGBUS_HLSQ_DP_STR_1"/>
+ <value value="413" name="A7XX_DBGBUS_HLSQ_DP_STR_2"/>
+ <value value="414" name="A7XX_DBGBUS_HLSQ_DP_STR_3"/>
+ <value value="415" name="A7XX_DBGBUS_HLSQ_DP_STR_4"/>
+ <value value="416" name="A7XX_DBGBUS_HLSQ_DP_STR_5"/>
+ <value value="443" name="A7XX_DBGBUS_UFC_DSTR_0"/>
+ <value value="444" name="A7XX_DBGBUS_UFC_DSTR_1"/>
+ <value value="445" name="A7XX_DBGBUS_UFC_DSTR_2"/>
+ <value value="446" name="A7XX_DBGBUS_CGC_SUBCORE"/>
+ <value value="447" name="A7XX_DBGBUS_CGC_CORE"/>
+</enum>
+
+<enum name="a6xx_cp_perfcounter_select">
+ <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
+ <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
+ <value value="2" name="PERF_CP_BUSY_CYCLES"/>
+ <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>
+ <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
+ <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
+ <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
+ <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
+ <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
+ <value value="9" name="PERF_CP_MODE_SWITCH"/>
+ <value value="10" name="PERF_CP_ZPASS_DONE"/>
+ <value value="11" name="PERF_CP_CONTEXT_DONE"/>
+ <value value="12" name="PERF_CP_CACHE_FLUSH"/>
+ <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>
+ <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>
+ <value value="15" name="PERF_CP_SQE_IDLE"/>
+ <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>
+ <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>
+ <value value="18" name="PERF_CP_SQE_MRB_STARVE"/>
+ <value value="19" name="PERF_CP_SQE_RRB_STARVE"/>
+ <value value="20" name="PERF_CP_SQE_VSD_STARVE"/>
+ <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>
+ <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>
+ <value value="23" name="PERF_CP_SQE_SYNC_STALL"/>
+ <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>
+ <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>
+ <value value="26" name="PERF_CP_SQE_T4_EXEC"/>
+ <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>
+ <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>
+ <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>
+ <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
+ <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>
+ <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>
+ <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>
+ <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
+ <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
+ <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>
+ <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
+ <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
+ <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>
+ <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>
+ <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>
+ <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>
+ <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>
+ <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>
+ <value value="45" name="PERF_CP_PM4_DATA"/>
+ <value value="46" name="PERF_CP_PM4_HEADERS"/>
+ <value value="47" name="PERF_CP_VBIF_READ_BEATS"/>
+ <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>
+ <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>
+</enum>
+
+<enum name="a6xx_rbbm_perfcounter_select">
+ <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
+ <value value="1" name="PERF_RBBM_ALWAYS_ON"/>
+ <value value="2" name="PERF_RBBM_TSE_BUSY"/>
+ <value value="3" name="PERF_RBBM_RAS_BUSY"/>
+ <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
+ <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
+ <value value="6" name="PERF_RBBM_STATUS_MASKED"/>
+ <value value="7" name="PERF_RBBM_COM_BUSY"/>
+ <value value="8" name="PERF_RBBM_DCOM_BUSY"/>
+ <value value="9" name="PERF_RBBM_VBIF_BUSY"/>
+ <value value="10" name="PERF_RBBM_VSC_BUSY"/>
+ <value value="11" name="PERF_RBBM_TESS_BUSY"/>
+ <value value="12" name="PERF_RBBM_UCHE_BUSY"/>
+ <value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
+</enum>
+
+<enum name="a6xx_pc_perfcounter_select">
+ <value value="0" name="PERF_PC_BUSY_CYCLES"/>
+ <value value="1" name="PERF_PC_WORKING_CYCLES"/>
+ <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
+ <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
+ <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
+ <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
+ <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
+ <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
+ <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
+ <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
+ <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
+ <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
+ <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
+ <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
+ <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
+ <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
+ <value value="16" name="PERF_PC_INSTANCES"/>
+ <value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
+ <value value="18" name="PERF_PC_DEAD_PRIM"/>
+ <value value="19" name="PERF_PC_LIVE_PRIM"/>
+ <value value="20" name="PERF_PC_VERTEX_HITS"/>
+ <value value="21" name="PERF_PC_IA_VERTICES"/>
+ <value value="22" name="PERF_PC_IA_PRIMITIVES"/>
+ <value value="23" name="PERF_PC_GS_PRIMITIVES"/>
+ <value value="24" name="PERF_PC_HS_INVOCATIONS"/>
+ <value value="25" name="PERF_PC_DS_INVOCATIONS"/>
+ <value value="26" name="PERF_PC_VS_INVOCATIONS"/>
+ <value value="27" name="PERF_PC_GS_INVOCATIONS"/>
+ <value value="28" name="PERF_PC_DS_PRIMITIVES"/>
+ <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
+ <value value="30" name="PERF_PC_3D_DRAWCALLS"/>
+ <value value="31" name="PERF_PC_2D_DRAWCALLS"/>
+ <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
+ <value value="33" name="PERF_TESS_BUSY_CYCLES"/>
+ <value value="34" name="PERF_TESS_WORKING_CYCLES"/>
+ <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
+ <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
+ <value value="37" name="PERF_PC_TSE_TRANSACTION"/>
+ <value value="38" name="PERF_PC_TSE_VERTEX"/>
+ <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>
+ <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>
+ <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>
+</enum>
+
+<enum name="a6xx_vfd_perfcounter_select">
+ <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
+ <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
+ <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
+ <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
+ <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
+ <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
+ <value value="6" name="PERF_VFD_RBUFFER_FULL"/>
+ <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
+ <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
+ <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>
+ <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
+ <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
+ <value value="12" name="PERF_VFD_MODE_0_FIBERS"/>
+ <value value="13" name="PERF_VFD_MODE_1_FIBERS"/>
+ <value value="14" name="PERF_VFD_MODE_2_FIBERS"/>
+ <value value="15" name="PERF_VFD_MODE_3_FIBERS"/>
+ <value value="16" name="PERF_VFD_MODE_4_FIBERS"/>
+ <value value="17" name="PERF_VFD_TOTAL_VERTICES"/>
+ <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>
+ <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
+ <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
+ <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>
+ <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>
+</enum>
+
+<enum name="a6xx_hlsq_perfcounter_select">
+ <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
+ <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
+ <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
+ <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
+ <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
+ <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
+ <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>
+ <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>
+ <value value="8" name="PERF_HLSQ_QUADS"/>
+ <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>
+ <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
+ <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
+ <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
+ <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
+ <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
+ <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
+ <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
+ <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
+ <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>
+ <value value="19" name="PERF_HLSQ_PIXELS"/>
+ <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>
+</enum>
+
+<enum name="a6xx_vpc_perfcounter_select">
+ <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
+ <value value="1" name="PERF_VPC_WORKING_CYCLES"/>
+ <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
+ <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
+ <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
+ <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
+ <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
+ <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>
+ <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
+ <value value="9" name="PERF_VPC_PC_PRIMITIVES"/>
+ <value value="10" name="PERF_VPC_SP_COMPONENTS"/>
+ <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>
+ <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>
+ <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>
+ <value value="14" name="PERF_VPC_LM_TRANSACTION"/>
+ <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>
+ <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>
+ <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>
+ <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>
+ <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>
+ <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>
+ <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>
+ <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>
+ <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>
+ <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>
+ <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>
+ <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>
+ <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>
+</enum>
+
+<enum name="a6xx_tse_perfcounter_select">
+ <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
+ <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
+ <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
+ <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
+ <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
+ <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
+ <value value="6" name="PERF_TSE_INPUT_PRIM"/>
+ <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
+ <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
+ <value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
+ <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
+ <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
+ <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
+ <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
+ <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
+ <value value="15" name="PERF_TSE_CINVOCATION"/>
+ <value value="16" name="PERF_TSE_CPRIMITIVES"/>
+ <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
+ <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>
+ <value value="19" name="PERF_TSE_CLIP_PLANES"/>
+</enum>
+
+<enum name="a6xx_ras_perfcounter_select">
+ <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
+ <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
+ <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
+ <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
+ <value value="4" name="PERF_RAS_SUPER_TILES"/>
+ <value value="5" name="PERF_RAS_8X4_TILES"/>
+ <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
+ <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
+ <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
+ <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
+ <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
+ <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
+ <value value="12" name="PERF_RAS_BLOCKS"/>
+</enum>
+
+<enum name="a6xx_uche_perfcounter_select">
+ <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
+ <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>
+ <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
+ <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
+ <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
+ <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
+ <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
+ <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
+ <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
+ <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
+ <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
+ <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
+ <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
+ <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
+ <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
+ <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
+ <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
+ <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
+ <value value="18" name="PERF_UCHE_EVICTS"/>
+ <value value="19" name="PERF_UCHE_BANK_REQ0"/>
+ <value value="20" name="PERF_UCHE_BANK_REQ1"/>
+ <value value="21" name="PERF_UCHE_BANK_REQ2"/>
+ <value value="22" name="PERF_UCHE_BANK_REQ3"/>
+ <value value="23" name="PERF_UCHE_BANK_REQ4"/>
+ <value value="24" name="PERF_UCHE_BANK_REQ5"/>
+ <value value="25" name="PERF_UCHE_BANK_REQ6"/>
+ <value value="26" name="PERF_UCHE_BANK_REQ7"/>
+ <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
+ <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
+ <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
+ <value value="30" name="PERF_UCHE_TPH_REF_FULL"/>
+ <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>
+ <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>
+ <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
+ <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
+ <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>
+ <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>
+ <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>
+ <value value="38" name="PERF_UCHE_RAM_READ_REQ"/>
+ <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>
+</enum>
+
+<enum name="a6xx_tp_perfcounter_select">
+ <value value="0" name="PERF_TP_BUSY_CYCLES"/>
+ <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
+ <value value="2" name="PERF_TP_LATENCY_CYCLES"/>
+ <value value="3" name="PERF_TP_LATENCY_TRANS"/>
+ <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
+ <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
+ <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
+ <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
+ <value value="8" name="PERF_TP_SP_TP_TRANS"/>
+ <value value="9" name="PERF_TP_TP_SP_TRANS"/>
+ <value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
+ <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
+ <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
+ <value value="13" name="PERF_TP_QUADS_RECEIVED"/>
+ <value value="14" name="PERF_TP_QUADS_OFFSET"/>
+ <value value="15" name="PERF_TP_QUADS_SHADOW"/>
+ <value value="16" name="PERF_TP_QUADS_ARRAY"/>
+ <value value="17" name="PERF_TP_QUADS_GRADIENT"/>
+ <value value="18" name="PERF_TP_QUADS_1D"/>
+ <value value="19" name="PERF_TP_QUADS_2D"/>
+ <value value="20" name="PERF_TP_QUADS_BUFFER"/>
+ <value value="21" name="PERF_TP_QUADS_3D"/>
+ <value value="22" name="PERF_TP_QUADS_CUBE"/>
+ <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
+ <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
+ <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
+ <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
+ <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
+ <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
+ <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
+ <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
+ <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>
+ <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>
+ <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>
+ <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
+ <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
+ <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
+ <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
+ <value value="38" name="PERF_TP_TPA2TPC_TRANS"/>
+ <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>
+ <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>
+ <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>
+ <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>
+ <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>
+ <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>
+ <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
+ <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
+ <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
+ <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>
+ <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>
+ <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
+ <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
+ <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>
+ <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>
+ <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
+ <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>
+ <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>
+</enum>
+
+<enum name="a6xx_sp_perfcounter_select">
+ <value value="0" name="PERF_SP_BUSY_CYCLES"/>
+ <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
+ <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
+ <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
+ <value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
+ <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
+ <value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
+ <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>
+ <value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
+ <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
+ <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
+ <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
+ <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
+ <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
+ <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
+ <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
+ <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
+ <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
+ <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
+ <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
+ <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
+ <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
+ <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
+ <value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
+ <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
+ <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
+ <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
+ <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
+ <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
+ <value value="29" name="PERF_SP_LM_ATOMICS"/>
+ <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
+ <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
+ <value value="32" name="PERF_SP_GM_ATOMICS"/>
+ <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
+ <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
+ <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
+ <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
+ <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
+ <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
+ <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
+ <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
+ <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
+ <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
+ <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>
+ <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>
+ <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>
+ <value value="46" name="PERF_SP_UCHE_READ_TRANS"/>
+ <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>
+ <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>
+ <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>
+ <value value="50" name="PERF_SP_PIXELS_KILLED"/>
+ <value value="51" name="PERF_SP_ICL1_REQUESTS"/>
+ <value value="52" name="PERF_SP_ICL1_MISSES"/>
+ <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>
+ <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>
+ <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>
+ <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>
+ <value value="57" name="PERF_SP_GPR_READ"/>
+ <value value="58" name="PERF_SP_GPR_WRITE"/>
+ <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
+ <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
+ <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>
+ <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
+ <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
+ <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
+ <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>
+ <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>
+ <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>
+ <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
+ <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>
+ <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>
+ <value value="71" name="PERF_SP_WORKING_EU"/>
+ <value value="72" name="PERF_SP_ANY_EU_WORKING"/>
+ <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>
+ <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
+ <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>
+ <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
+ <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>
+ <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
+ <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>
+ <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>
+ <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>
+ <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
+ <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
+ <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>
+</enum>
+
+<enum name="a6xx_rb_perfcounter_select">
+ <value value="0" name="PERF_RB_BUSY_CYCLES"/>
+ <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>
+ <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
+ <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
+ <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
+ <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>
+ <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
+ <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>
+ <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
+ <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
+ <value value="10" name="PERF_RB_Z_WORKLOAD"/>
+ <value value="11" name="PERF_RB_HLSQ_ACTIVE"/>
+ <value value="12" name="PERF_RB_Z_READ"/>
+ <value value="13" name="PERF_RB_Z_WRITE"/>
+ <value value="14" name="PERF_RB_C_READ"/>
+ <value value="15" name="PERF_RB_C_WRITE"/>
+ <value value="16" name="PERF_RB_TOTAL_PASS"/>
+ <value value="17" name="PERF_RB_Z_PASS"/>
+ <value value="18" name="PERF_RB_Z_FAIL"/>
+ <value value="19" name="PERF_RB_S_FAIL"/>
+ <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
+ <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
+ <value value="22" name="PERF_RB_PS_INVOCATIONS"/>
+ <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>
+ <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
+ <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
+ <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
+ <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
+ <value value="28" name="PERF_RB_2D_VALID_PIXELS"/>
+ <value value="29" name="PERF_RB_3D_PIXELS"/>
+ <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>
+ <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>
+ <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>
+ <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>
+ <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
+ <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
+ <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
+ <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
+ <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>
+ <value value="39" name="PERF_RB_2D_INPUT_TRANS"/>
+ <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>
+ <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>
+ <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>
+ <value value="43" name="PERF_RB_COLOR_PIX_TILES"/>
+ <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>
+ <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>
+ <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>
+ <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>
+</enum>
+
+<enum name="a6xx_vsc_perfcounter_select">
+ <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
+ <value value="1" name="PERF_VSC_WORKING_CYCLES"/>
+ <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
+ <value value="3" name="PERF_VSC_EOT_NUM"/>
+ <value value="4" name="PERF_VSC_INPUT_TILES"/>
+</enum>
+
+<enum name="a6xx_ccu_perfcounter_select">
+ <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
+ <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
+ <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
+ <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
+ <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
+ <value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
+ <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
+ <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
+ <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
+ <value value="9" name="PERF_CCU_GMEM_READ"/>
+ <value value="10" name="PERF_CCU_GMEM_WRITE"/>
+ <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
+ <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
+ <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
+ <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
+ <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
+ <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>
+ <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>
+ <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>
+ <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
+ <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
+ <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
+ <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
+ <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
+ <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>
+ <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>
+ <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>
+ <value value="27" name="PERF_CCU_2D_RD_REQ"/>
+ <value value="28" name="PERF_CCU_2D_WR_REQ"/>
+</enum>
+
+<enum name="a6xx_lrz_perfcounter_select">
+ <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
+ <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
+ <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
+ <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
+ <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
+ <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
+ <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
+ <value value="7" name="PERF_LRZ_LRZ_READ"/>
+ <value value="8" name="PERF_LRZ_LRZ_WRITE"/>
+ <value value="9" name="PERF_LRZ_READ_LATENCY"/>
+ <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
+ <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
+ <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
+ <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
+ <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
+ <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
+ <value value="16" name="PERF_LRZ_TILE_KILLED"/>
+ <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
+ <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
+ <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>
+ <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>
+ <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>
+ <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>
+ <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>
+ <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
+ <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
+ <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>
+ <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>
+</enum>
+
+<enum name="a6xx_cmp_perfcounter_select">
+ <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
+ <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
+ <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
+ <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
+ <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
+ <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
+ <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
+ <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
+ <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
+ <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
+ <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
+ <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
+ <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
+ <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
+ <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
+ <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
+ <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
+ <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
+ <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
+ <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
+ <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
+ <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
+ <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
+ <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
+ <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
+ <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
+ <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
+ <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
+ <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>
+ <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>
+ <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
+ <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
+ <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>
+ <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
+ <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
+ <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
+ <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
+ <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>
+ <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>
+ <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>
+</enum>
+
+<!--
+Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the
+component type/size, so I think it relates to internal format used for
+blending? The one exception is that 16b unorm and 32b float use the
+same value... maybe 16b unorm is uncommon enough that it was just easier
+to upconvert to 32b float internally?
+
+ 8b unorm: 10 (sometimes 0, is the high bit part of something else?)
+16b unorm: 4
+
+32b int: 7
+16b int: 6
+ 8b int: 5
+
+32b float: 4
+16b float: 3
+ -->
+<enum name="a6xx_2d_ifmt">
+ <value value="0x10" name="R2D_UNORM8"/>
+ <value value="0x7" name="R2D_INT32"/>
+ <value value="0x6" name="R2D_INT16"/>
+ <value value="0x5" name="R2D_INT8"/>
+ <value value="0x4" name="R2D_FLOAT32"/>
+ <value value="0x3" name="R2D_FLOAT16"/>
+ <value value="0x1" name="R2D_UNORM8_SRGB"/>
+ <value value="0x0" name="R2D_RAW"/>
+</enum>
+
+<enum name="a6xx_ztest_mode">
+ <doc>Allow early z-test and early-lrz (if applicable)</doc>
+ <value value="0x0" name="A6XX_EARLY_Z"/>
+ <doc>Disable early z-test and early-lrz test (if applicable)</doc>
+ <value value="0x1" name="A6XX_LATE_Z"/>
+ <doc>
+ A special mode that allows early-lrz test but disables
+ early-z test. Which might sound a bit funny, since
+ lrz-test happens before z-test. But as long as a couple
+ conditions are maintained this allows using lrz-test in
+ cases where fragment shader has kill/discard:
+
+ 1) Disable lrz-write in cases where it is uncertain during
+ binning pass that a fragment will pass. Ie. if frag
+ shader has-kill, writes-z, or alpha/stencil test is
+ enabled. (For correctness, lrz-write must be disabled
+ when blend is enabled.) This is analogous to how a
+ z-prepass works.
+
+ 2) Disable lrz-write and test if a depth-test direction
+ reversal is detected. Due to condition (1), the contents
+ of the lrz buffer are a conservative estimation of the
+ depth buffer during the draw pass. Meaning that geometry
+ that we know for certain will not be visible will not pass
+ lrz-test. But geometry which may be (or contributes to
+ blend) will pass the lrz-test.
+
+ This allows us to keep early-lrz-test in cases where the frag
+ shader does not write-z (ie. we know the z-value before FS)
+ and does not have side-effects (image/ssbo writes, etc), but
+ does have kill/discard. Which turns out to be a common
+ enough case that it is useful to keep early-lrz test against
+ the conservative lrz buffer to discard fragments that we
+ know will definitely not be visible.
+ </doc>
+ <value value="0x2" name="A6XX_EARLY_LRZ_LATE_Z"/>
+ <doc>Not a real hw value, used internally by mesa</doc>
+ <value value="0x3" name="A6XX_INVALID_ZTEST"/>
+</enum>
+
+<enum name="a6xx_tess_spacing">
+ <value value="0x0" name="TESS_EQUAL"/>
+ <value value="0x2" name="TESS_FRACTIONAL_ODD"/>
+ <value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
+</enum>
+<enum name="a6xx_tess_output">
+ <value value="0x0" name="TESS_POINTS"/>
+ <value value="0x1" name="TESS_LINES"/>
+ <value value="0x2" name="TESS_CW_TRIS"/>
+ <value value="0x3" name="TESS_CCW_TRIS"/>
+</enum>
+
+<domain name="A6XX" width="32" prefix="variant" varset="chip">
+ <bitset name="A6XX_RBBM_INT_0_MASK" inline="no" varset="chip">
+ <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
+ <bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/>
+ <bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX-"/>
+ <bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX-"/>
+ <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/>
+ <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
+ <bitfield name="CP_SW" pos="8" type="boolean"/>
+ <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
+ <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
+ <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
+ <bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
+ <bitfield name="CP_IB2" pos="13" type="boolean"/>
+ <bitfield name="CP_IB1" pos="14" type="boolean"/>
+ <bitfield name="CP_RB" pos="15" type="boolean" variants="A6XX"/>
+ <!-- Same as above but different name??: -->
+ <bitfield name="PM4CPINTERRUPT" pos="15" type="boolean" variants="A7XX-"/>
+ <bitfield name="PM4CPINTERRUPTLPAC" pos="16" type="boolean" variants="A7XX-"/>
+ <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
+ <bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
+ <bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
+ <bitfield name="CP_CACHE_FLUSH_TS_LPAC" pos="21" type="boolean" variants="A7XX-"/>
+ <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
+ <bitfield name="RBBM_HANG_DETECT" pos="23" type="boolean"/>
+ <bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
+ <bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
+ <bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
+ <bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
+ <bitfield name="TSBWRITEERROR" pos="28" type="boolean" variants="A7XX-"/>
+ <bitfield name="SWFUSEVIOLATION" pos="29" type="boolean" variants="A7XX-"/>
+ <bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
+ <bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
+ </bitset>
+
+ <!--
+ Note the _LPAC bits probably *actually* first appeared in a660, but the
+ _BV bits are new in a7xx
+ -->
+ <bitset name="A6XX_CP_INT" varset="chip">
+ <bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>
+ <bitfield name="CP_UCODE_ERROR" pos="1" type="boolean"/>
+ <bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/>
+ <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/>
+ <bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/>
+ <bitfield name="CP_VSD_PARITY_ERROR" pos="6" type="boolean"/>
+ <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7" type="boolean"/>
+ <bitfield name="CP_OPCODE_ERROR_LPAC" pos="8" type="boolean" variants="A7XX-"/>
+ <bitfield name="CP_UCODE_ERROR_LPAC" pos="9" type="boolean" variants="A7XX-"/>
+ <bitfield name="CP_HW_FAULT_ERROR_LPAC" pos="10" type="boolean" variants="A7XX-"/>
+ <bitfield name="CP_REGISTER_PROTECTION_ERROR_LPAC" pos="11" type="boolean" variants="A7XX-"/>
+ <bitfield name="CP_ILLEGAL_INSTR_ERROR_LPAC" pos="12" type="boolean" variants="A7XX-"/>
+ <bitfield name="CP_OPCODE_ERROR_BV" pos="13" type="boolean" variants="A7XX-"/>
+ <bitfield name="CP_UCODE_ERROR_BV" pos="14" type="boolean" variants="A7XX-"/>
+ <bitfield name="CP_HW_FAULT_ERROR_BV" pos="15" type="boolean" variants="A7XX-"/>
+ <bitfield name="CP_REGISTER_PROTECTION_ERROR_BV" pos="16" type="boolean" variants="A7XX-"/>
+ <bitfield name="CP_ILLEGAL_INSTR_ERROR_BV" pos="17" type="boolean" variants="A7XX-"/>
+ </bitset>
+
+ <reg64 offset="0x0800" name="CP_RB_BASE"/>
+ <reg32 offset="0x0802" name="CP_RB_CNTL"/>
+ <reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
+ <reg32 offset="0x0806" name="CP_RB_RPTR"/>
+ <reg32 offset="0x0807" name="CP_RB_WPTR"/>
+ <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
+ <reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
+ <bitfield name="IFPC" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0821" name="CP_HW_FAULT"/>
+ <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT"/>
+ <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
+ <reg32 offset="0x0825" name="CP_STATUS_1"/>
+ <reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/>
+ <reg32 offset="0x0840" name="CP_MISC_CNTL"/>
+ <reg32 offset="0x0844" name="CP_APRIV_CNTL">
+ <!-- Crashdumper writes -->
+ <bitfield pos="6" name="CDWRITE" type="boolean"/>
+ <!-- Crashdumper reads -->
+ <bitfield pos="5" name="CDREAD" type="boolean"/>
+
+ <!-- 4 is unknown -->
+
+ <!-- RPTR shadow writes -->
+ <bitfield pos="3" name="RBRPWB" type="boolean"/>
+ <!-- Memory accesses from PM4 packets in the ringbuffer -->
+ <bitfield pos="2" name="RBPRIVLEVEL" type="boolean"/>
+ <!-- Ringbuffer reads -->
+ <bitfield pos="1" name="RBFETCH" type="boolean"/>
+ <!-- Instruction cache fetches -->
+ <bitfield pos="0" name="ICACHE" type="boolean"/>
+ </reg32>
+ <!-- Preemptions taking longer than this threshold increment PERF_CP_LONG_PREEMPTIONS: -->
+ <reg32 offset="0x08C0" name="CP_PREEMPT_THRESHOLD"/>
+ <!-- all the threshold values seem to be in units of quad-dwords: -->
+ <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">
+ <doc>
+ b0..7 identifies where MRB data starts (and RB data ends)
+ b8.15 identifies where VSD data starts (and MRB data ends)
+ b16..23 identifies where IB1 data starts (and RB data ends)
+ b24..31 identifies where IB2 data starts (and IB1 data ends)
+ </doc>
+ <bitfield name="MRB_START" low="0" high="7" shr="2"/>
+ <bitfield name="VSD_START" low="8" high="15" shr="2"/>
+ <bitfield name="IB1_START" low="16" high="23" shr="2"/>
+ <bitfield name="IB2_START" low="24" high="31" shr="2"/>
+ </reg32>
+ <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">
+ <doc>
+ low bits identify where CP_SET_DRAW_STATE stateobj
+ processing starts (and IB2 data ends). I'm guessing
+ b8 is part of this since (from downstream kgsl):
+
+ /* ROQ sizes are twice as big on a640/a680 than on a630 */
+ if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) {
+ kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
+ kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);
+ } ...
+ </doc>
+ <bitfield name="SDS_START" low="0" high="8" shr="2"/>
+ <!-- total ROQ size: -->
+ <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
+ </reg32>
+ <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
+ <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
+ <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
+ <reg32 offset="0x084F" name="CP_PROTECT_CNTL">
+ <bitfield pos="3" name="LAST_SPAN_INF_RANGE" type="boolean"/>
+ <bitfield pos="1" name="ACCESS_FAULT_ON_VIOL_EN" type="boolean"/>
+ <bitfield pos="0" name="ACCESS_PROT_EN" type="boolean"/>
+ </reg32>
+
+ <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
+ <reg32 offset="0x0" name="REG" type="uint"/>
+ </array>
+ <array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
+ <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
+ </array>
+
+ <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
+ <reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/>
+ <reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/>
+ <reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/>
+ <reg64 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR"/>
+ <reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX-"/>
+ <array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/>
+ <array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX-"/>
+ <reg64 offset="0x0900" name="CP_CRASH_SCRIPT_BASE"/>
+ <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
+ <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
+ <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
+ <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
+ <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
+ <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
+ <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
+ <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
+ <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
+ <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
+ <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
+ <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
+ <reg64 offset="0x0928" name="CP_IB1_BASE"/>
+ <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
+ <reg64 offset="0x092B" name="CP_IB2_BASE"/>
+ <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
+ <!-- SDS == CP_SET_DRAW_STATE: -->
+ <reg64 offset="0x092e" name="CP_SDS_BASE"/>
+ <reg32 offset="0x0930" name="CP_SDS_REM_SIZE"/>
+ <!-- MRB == MEM_READ_ADDR/$addr in SQE firmware -->
+ <reg64 offset="0x0931" name="CP_MRB_BASE"/>
+ <reg32 offset="0x0933" name="CP_MRB_REM_SIZE"/>
+ <!--
+ VSD == Visibility Stream Decode
+ This is used by CP to read the draw stream and skip empty draws
+ -->
+ <reg64 offset="0x0934" name="CP_VSD_BASE"/>
+
+ <bitset name="a6xx_roq_stat" inline="yes">
+ <bitfield name="RPTR" low="0" high="9"/>
+ <bitfield name="WPTR" low="16" high="25"/>
+ </bitset>
+ <reg32 offset="0x0939" name="CP_ROQ_RB_STAT" type="a6xx_roq_stat"/>
+ <reg32 offset="0x093a" name="CP_ROQ_IB1_STAT" type="a6xx_roq_stat"/>
+ <reg32 offset="0x093b" name="CP_ROQ_IB2_STAT" type="a6xx_roq_stat"/>
+ <reg32 offset="0x093c" name="CP_ROQ_SDS_STAT" type="a6xx_roq_stat"/>
+ <reg32 offset="0x093d" name="CP_ROQ_MRB_STAT" type="a6xx_roq_stat"/>
+ <reg32 offset="0x093e" name="CP_ROQ_VSD_STAT" type="a6xx_roq_stat"/>
+
+ <reg32 offset="0x0943" name="CP_IB1_DWORDS"/>
+ <reg32 offset="0x0944" name="CP_IB2_DWORDS"/>
+ <reg32 offset="0x0945" name="CP_SDS_DWORDS"/>
+ <reg32 offset="0x0946" name="CP_MRB_DWORDS"/>
+ <reg32 offset="0x0947" name="CP_VSD_DWORDS"/>
+
+ <reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB">
+ <doc>number of remaining dwords incl current dword being consumed?</doc>
+ <bitfield name="REM" low="16" high="31"/>
+ </reg32>
+ <reg32 offset="0x0949" name="CP_ROQ_AVAIL_IB1">
+ <doc>number of remaining dwords incl current dword being consumed?</doc>
+ <bitfield name="REM" low="16" high="31"/>
+ </reg32>
+ <reg32 offset="0x094a" name="CP_ROQ_AVAIL_IB2">
+ <doc>number of remaining dwords incl current dword being consumed?</doc>
+ <bitfield name="REM" low="16" high="31"/>
+ </reg32>
+ <reg32 offset="0x094b" name="CP_ROQ_AVAIL_SDS">
+ <doc>number of remaining dwords incl current dword being consumed?</doc>
+ <bitfield name="REM" low="16" high="31"/>
+ </reg32>
+ <reg32 offset="0x094c" name="CP_ROQ_AVAIL_MRB">
+ <doc>number of dwords that have already been read but haven't been consumed by $addr</doc>
+ <bitfield name="REM" low="16" high="31"/>
+ </reg32>
+ <reg32 offset="0x094d" name="CP_ROQ_AVAIL_VSD">
+ <doc>number of remaining dwords incl current dword being consumed?</doc>
+ <bitfield name="REM" low="16" high="31"/>
+ </reg32>
+
+ <bitset name="a7xx_aperture_cntl" inline="yes">
+ <bitfield name="PIPE" low="12" high="13" type="a7xx_pipe"/>
+ <bitfield name="CLUSTER" low="8" high="10" type="a7xx_cluster"/>
+ <bitfield name="CONTEXT" low="4" high="5"/>
+ </bitset>
+ <reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER"/>
+ <reg32 offset="0x098D" name="CP_AHB_CNTL"/>
+ <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/>
+ <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX-"/>
+ <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" variants="A6XX"/>
+ <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX-"/>
+
+ <reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX-"/>
+ <reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX-"/>
+ <reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX-"/>
+ <reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX-"/>
+ <reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX-"/>
+ <reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX-"/>
+ <reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX-"/>
+ <reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX-"/>
+ <reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX-"/>
+ <reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX-"/>
+ <reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX-"/>
+ <reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX-"/>
+ <reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX-"/>
+
+ <reg32 offset="0x0a9a" name="CP_RESOURCE_TBL_DBG_ADDR" variants="A7XX-"/>
+ <reg32 offset="0x0a9b" name="CP_RESOURCE_TBL_DBG_DATA" variants="A7XX-"/>
+ <reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX-"/>
+ <reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX-"/>
+
+ <reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX-"/>
+ <reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX-"/>
+ <reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX-"/>
+ <reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX-"/>
+ <reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX-"/>
+ <reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX-"/>
+ <reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX-"/>
+
+ <reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX-"/>
+ <reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/>
+ <reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX-"/>
+ <reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX-"/>
+ <reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX-"/>
+ <reg32 offset="0x0b81" name="CP_LPAC_SQE_CNTL"/>
+ <reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/>
+
+ <reg64 offset="0x0b70" name="CP_AQE_INSTR_BASE_0" variants="A7XX-"/>
+ <reg64 offset="0x0b72" name="CP_AQE_INSTR_BASE_1" variants="A7XX-"/>
+ <reg32 offset="0x0b78" name="CP_AQE_APRIV_CNTL" variants="A7XX-"/>
+
+ <reg32 offset="0x0ba8" name="CP_AQE_ROQ_DBG_ADDR_0" variants="A7XX-"/>
+ <reg32 offset="0x0ba9" name="CP_AQE_ROQ_DBG_ADDR_1" variants="A7XX-"/>
+ <reg32 offset="0x0bac" name="CP_AQE_ROQ_DBG_DATA_0" variants="A7XX-"/>
+ <reg32 offset="0x0bad" name="CP_AQE_ROQ_DBG_DATA_1" variants="A7XX-"/>
+ <reg32 offset="0x0bb0" name="CP_AQE_UCODE_DBG_ADDR_0" variants="A7XX-"/>
+ <reg32 offset="0x0bb1" name="CP_AQE_UCODE_DBG_ADDR_1" variants="A7XX-"/>
+ <reg32 offset="0x0bb4" name="CP_AQE_UCODE_DBG_DATA_0" variants="A7XX-"/>
+ <reg32 offset="0x0bb5" name="CP_AQE_UCODE_DBG_DATA_1" variants="A7XX-"/>
+ <reg32 offset="0x0bb8" name="CP_AQE_STAT_ADDR_0" variants="A7XX-"/>
+ <reg32 offset="0x0bb9" name="CP_AQE_STAT_ADDR_1" variants="A7XX-"/>
+ <reg32 offset="0x0bbc" name="CP_AQE_STAT_DATA_0" variants="A7XX-"/>
+ <reg32 offset="0x0bbd" name="CP_AQE_STAT_DATA_1" variants="A7XX-"/>
+
+ <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0x0018" name="RBBM_GPR0_CNTL"/>
+ <reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>
+ <reg32 offset="0x0210" name="RBBM_STATUS">
+ <bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/>
+ <bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/>
+ <bitfield pos="21" name="HLSQ_BUSY" type="boolean"/>
+ <bitfield pos="20" name="VSC_BUSY" type="boolean"/>
+ <bitfield pos="19" name="TPL1_BUSY" type="boolean"/>
+ <bitfield pos="18" name="SP_BUSY" type="boolean"/>
+ <bitfield pos="17" name="UCHE_BUSY" type="boolean"/>
+ <bitfield pos="16" name="VPC_BUSY" type="boolean"/>
+ <bitfield pos="15" name="VFD_BUSY" type="boolean"/>
+ <bitfield pos="14" name="TESS_BUSY" type="boolean"/>
+ <bitfield pos="13" name="PC_VSD_BUSY" type="boolean"/>
+ <bitfield pos="12" name="PC_DCALL_BUSY" type="boolean"/>
+ <bitfield pos="11" name="COM_DCOM_BUSY" type="boolean"/>
+ <bitfield pos="10" name="LRZ_BUSY" type="boolean"/>
+ <bitfield pos="9" name="A2D_BUSY" type="boolean"/>
+ <bitfield pos="8" name="CCU_BUSY" type="boolean"/>
+ <bitfield pos="7" name="RB_BUSY" type="boolean"/>
+ <bitfield pos="6" name="RAS_BUSY" type="boolean"/>
+ <bitfield pos="5" name="TSE_BUSY" type="boolean"/>
+ <bitfield pos="4" name="VBIF_BUSY" type="boolean"/>
+ <bitfield pos="3" name="GFX_DBGC_BUSY" type="boolean"/>
+ <bitfield pos="2" name="CP_BUSY" type="boolean"/>
+ <bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/>
+ <bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0211" name="RBBM_STATUS1"/>
+ <reg32 offset="0x0212" name="RBBM_STATUS2"/>
+ <reg32 offset="0x0213" name="RBBM_STATUS3">
+ <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
+
+ <reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX-"/>
+ <reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX-"/>
+ <reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX-"/>
+ <reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX-"/>
+ <reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX-"/>
+ <reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX-"/>
+
+ <reg32 offset="0x02c0" name="RBBM_SW_FUSE_INT_STATUS" variants="A7XX-"/>
+ <reg32 offset="0x02c1" name="RBBM_SW_FUSE_INT_MASK" variants="A7XX-"/>
+
+ <array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A6XX"/>
+ <array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A6XX"/>
+ <array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A6XX"/>
+ <array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A6XX"/>
+ <array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A6XX"/>
+ <array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A6XX"/>
+ <array offset="0x045c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A6XX"/>
+ <array offset="0x0466" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A6XX"/>
+ <array offset="0x046e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A6XX"/>
+ <array offset="0x0476" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A6XX"/>
+ <array offset="0x048e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A6XX"/>
+ <array offset="0x04a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A6XX"/>
+ <array offset="0x04d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A6XX"/>
+ <array offset="0x04e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A6XX"/>
+ <array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A6XX"/>
+ <array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A6XX"/>
+
+ <array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX-"/>
+ <array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX-"/>
+ <array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX-"/>
+ <array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX-"/>
+ <array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX-"/>
+ <array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX-"/>
+ <array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX-"/>
+ <array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX-"/>
+ <array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX-"/>
+ <array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX-"/>
+ <array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX-"/>
+ <array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX-"/>
+ <array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX-"/>
+ <array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX-"/>
+ <array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX-"/>
+ <array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX-"/>
+ <array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX-"/>
+ <array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX-"/>
+ <array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX-"/>
+ <array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX-"/>
+ <array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX-"/>
+ <array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX-"/>
+ <array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX-"/>
+ <array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX-"/>
+ <array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX-"/>
+ <array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX-"/>
+ <array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX-"/>
+ <array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX-"/>
+
+ <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
+ <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
+ <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
+ <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
+ <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
+ <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
+ <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
+ <array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/>
+ <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
+ <reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD"/>
+ <reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS"/>
+ <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
+ <reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL" variants="A7XX-"/>
+ <reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX-"/>
+
+ <!---
+ This block of registers aren't tied to perf counters. They
+ count various geometry stats, for example number of
+ vertices in, number of primnitives assembled etc.
+ -->
+
+ <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in -->
+ <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
+ <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out -->
+ <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
+ <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in -->
+ <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
+ <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out -->
+ <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
+ <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in -->
+ <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
+ <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out -->
+ <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
+ <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in -->
+ <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
+ <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out -->
+ <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
+ <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out -->
+ <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
+ <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in -->
+ <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
+ <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
+ <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
+
+ <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
+ <reg64 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/>
+ <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
+ <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
+ <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS" variants="A7XX-"/>
+ <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
+ <reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
+ <reg32 offset="0x00016" name="RBBM_GBIF_HALT"/>
+ <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK"/>
+ <reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD">
+ <bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A7XX-"/>
+ <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A7XX-"/>
+ <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
+ <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/>
+ <reg32 offset="0x00038" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK"/>
+ <reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX-"/>
+ <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
+ <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
+ <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
+ <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
+ <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
+ <reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX-"/>
+ <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
+ <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
+ <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
+ <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
+ <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
+ <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
+ <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
+ <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
+ <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
+ <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
+ <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
+ <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
+ <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
+ <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
+ <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
+ <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
+ <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
+ <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
+ <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
+ <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
+ <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
+ <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
+ <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
+ <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
+ <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
+ <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
+ <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
+ <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
+ <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
+ <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
+ <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
+ <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
+ <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
+ <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
+ <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
+ <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
+ <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
+ <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
+ <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
+ <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
+ <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
+ <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
+ <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
+ <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
+ <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
+ <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
+ <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
+ <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
+ <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
+ <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
+ <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
+ <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
+ <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
+ <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
+ <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
+ <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
+ <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
+ <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
+ <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
+ <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
+ <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
+ <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
+ <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
+ <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
+ <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
+ <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
+ <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
+ <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
+ <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
+ <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
+ <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
+ <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
+ <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
+ <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
+ <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
+ <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
+ <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
+ <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
+ <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
+ <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
+ <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
+ <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
+ <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
+ <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
+ <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
+ <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
+ <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
+ <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
+ <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
+ <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
+ <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
+ <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
+ <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
+ <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
+ <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
+ <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
+ <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
+ <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
+ <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
+ <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
+ <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
+ <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
+ <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
+ <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
+ <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
+ <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
+ <reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ"/>
+ <reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX-"/>
+ <reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX-"/>
+ <reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/>
+ <reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/>
+ <reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE"/>
+ <reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX-">
+ <bitfield name="TXDONE" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00123" name="RBBM_CLOCK_CNTL_FCHE"/>
+ <reg32 offset="0x00124" name="RBBM_CLOCK_DELAY_FCHE"/>
+ <reg32 offset="0x00125" name="RBBM_CLOCK_HYST_FCHE"/>
+ <reg32 offset="0x00126" name="RBBM_CLOCK_CNTL_MHUB"/>
+ <reg32 offset="0x00127" name="RBBM_CLOCK_DELAY_MHUB"/>
+ <reg32 offset="0x00128" name="RBBM_CLOCK_HYST_MHUB"/>
+ <reg32 offset="0x00129" name="RBBM_CLOCK_DELAY_GLC"/>
+ <reg32 offset="0x0012a" name="RBBM_CLOCK_HYST_GLC"/>
+ <reg32 offset="0x0012b" name="RBBM_CLOCK_CNTL_GLC"/>
+ <reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX-"/>
+ <reg32 offset="0x005ff" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL"/>
+
+ <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
+ <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
+ <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
+ <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
+ <bitfield high="7" low="0" name="PING_INDEX"/>
+ <bitfield high="15" low="8" name="PING_BLK_SEL"/>
+ </reg32>
+ <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
+ <bitfield high="5" low="0" name="TRACEEN"/>
+ <bitfield high="14" low="12" name="GRANU"/>
+ <bitfield high="31" low="28" name="SEGT"/>
+ </reg32>
+ <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
+ <bitfield high="27" low="24" name="ENABLE"/>
+ </reg32>
+ <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
+ <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
+ <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
+ <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
+ <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
+ <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
+ <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
+ <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
+ <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
+ <bitfield high="3" low="0" name="BYTEL0"/>
+ <bitfield high="7" low="4" name="BYTEL1"/>
+ <bitfield high="11" low="8" name="BYTEL2"/>
+ <bitfield high="15" low="12" name="BYTEL3"/>
+ <bitfield high="19" low="16" name="BYTEL4"/>
+ <bitfield high="23" low="20" name="BYTEL5"/>
+ <bitfield high="27" low="24" name="BYTEL6"/>
+ <bitfield high="31" low="28" name="BYTEL7"/>
+ </reg32>
+ <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
+ <bitfield high="3" low="0" name="BYTEL8"/>
+ <bitfield high="7" low="4" name="BYTEL9"/>
+ <bitfield high="11" low="8" name="BYTEL10"/>
+ <bitfield high="15" low="12" name="BYTEL11"/>
+ <bitfield high="19" low="16" name="BYTEL12"/>
+ <bitfield high="23" low="20" name="BYTEL13"/>
+ <bitfield high="27" low="24" name="BYTEL14"/>
+ <bitfield high="31" low="28" name="BYTEL15"/>
+ </reg32>
+ <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
+ <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
+ <array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/>
+ <reg32 offset="0x0CD8" name="VSC_UNKNOWN_0CD8" variants="A7XX">
+ <doc>
+ Set to true when binning, isn't changed afterwards
+ </doc>
+ <bitfield name="BINNING" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
+ <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
+ <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
+ <reg64 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX"/>
+ <reg64 offset="0x0E07" name="UCHE_WRITE_THRU_BASE"/>
+ <reg64 offset="0x0E09" name="UCHE_TRAP_BASE"/>
+ <reg64 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN"/>
+ <reg64 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX"/>
+ <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS" usage="cmd"/>
+ <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
+ <reg32 offset="0x0E19" name="UCHE_CLIENT_PF" usage="cmd">
+ <bitfield high="7" low="0" name="PERFSEL"/>
+ </reg32>
+ <array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/>
+ <reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG"/>
+ <reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/>
+
+ <reg32 offset="0x3000" name="VBIF_VERSION"/>
+ <reg32 offset="0x3001" name="VBIF_CLKON">
+ <bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
+ <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
+ <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
+ <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
+ <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
+ <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
+ <bitfield low="0" high="3" name="DATA_SEL"/>
+ </reg32>
+ <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
+ <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
+ <bitfield low="0" high="8" name="DATA_SEL"/>
+ </reg32>
+ <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
+ <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
+ <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
+ <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
+ <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
+ <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
+ <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
+ <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
+ <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
+ <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
+ <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
+ <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
+ <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
+ <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
+ <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
+ <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
+ <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
+ <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
+ <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
+ <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
+ <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
+ <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
+
+ <reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/>
+ <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
+ <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
+ <reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
+ <reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/>
+ <reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>
+ <reg32 offset="0x3c45" name="GBIF_HALT"/>
+ <reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
+ <reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
+ <reg32 offset="0x3cc1" name="GBIF_PERF_PWR_CNT_CLR"/>
+ <reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
+ <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
+ <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
+ <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>
+ <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>
+ <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>
+ <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>
+ <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>
+ <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>
+ <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>
+ <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>
+ <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>
+ <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>
+ <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>
+ <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
+ <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>
+
+ <reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/>
+ <reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="rp_blit">
+ <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
+ <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
+ </reg32>
+ <reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress" usage="cmd"/>
+ <reg32 offset="0x0c06" name="VSC_BIN_COUNT" usage="rp_blit">
+ <bitfield name="NX" low="1" high="10" type="uint"/>
+ <bitfield name="NY" low="11" high="20" type="uint"/>
+ </reg32>
+ <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32" usage="rp_blit">
+ <reg32 offset="0x0" name="REG">
+ <doc>
+ Configures the mapping between VSC_PIPE buffer and
+ bin, X/Y specify the bin index in the horiz/vert
+ direction (0,0 is upper left, 0,1 is leftmost bin
+ on second row, and so on). W/H specify the number
+ of bins assigned to this VSC_PIPE in the horiz/vert
+ dimension.
+ </doc>
+ <bitfield name="X" low="0" high="9" type="uint"/>
+ <bitfield name="Y" low="10" high="19" type="uint"/>
+ <bitfield name="W" low="20" high="25" type="uint"/>
+ <bitfield name="H" low="26" high="31" type="uint"/>
+ </reg32>
+ </array>
+ <!--
+ HW binning primitive & draw streams, which enable draws and primitives
+ within a draw to be skipped in the main tile pass. See:
+ https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format
+
+ Compared to a5xx and earlier, we just program the address of the first
+ stream and hw adds (pipe_num * VSC_*_STRM_PITCH)
+
+ LIMIT is set to PITCH - 64, to make room for a bit of overflow
+ -->
+ <reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress" usage="cmd"/>
+ <reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH" usage="cmd"/>
+ <reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT" usage="cmd"/>
+ <reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress" usage="cmd"/>
+ <reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH" usage="cmd"/>
+ <reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT" usage="cmd"/>
+
+ <array offset="0x0c38" name="VSC_STATE" stride="1" length="32" usage="rp_blit">
+ <doc>
+ Seems to be a bitmap of which tiles mapped to the VSC
+ pipe contain geometry.
+
+ I suppose we can connect a maximum of 32 tiles to a
+ single VSC pipe.
+ </doc>
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+
+ <array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit">
+ <doc>
+ Has the size of data written to corresponding VSC_PRIM_STRM
+ buffer.
+ </doc>
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+
+ <array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit">
+ <doc>
+ Has the size of data written to corresponding VSC pipe, ie.
+ same thing that is written out to VSC_DRAW_STRM_SIZE_ADDRESS_LO/HI
+ </doc>
+ <reg32 offset="0x0" name="REG"/>
+ </array>
+
+ <reg32 offset="0x0d08" name="VSC_UNKNOWN_0D08" variants="A7XX-" usage="rp_blit"/>
+
+ <reg32 offset="0x0E10" name="UCHE_UNKNOWN_0E10" variants="A7XX-" usage="cmd"/>
+ <reg32 offset="0x0E11" name="UCHE_UNKNOWN_0E11" variants="A7XX-" usage="cmd"/>
+ <!-- always 0x03200000 ? -->
+ <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12" usage="cmd"/>
+
+ <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->
+ <bitset name="a6xx_reg_xy" inline="yes">
+ <bitfield name="X" low="0" high="13" type="uint"/>
+ <bitfield name="Y" low="16" high="29" type="uint"/>
+ </bitset>
+
+ <reg32 offset="0x8000" name="GRAS_CL_CNTL" usage="rp_blit">
+ <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
+ <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>
+ <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/>
+ <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
+ <!-- controls near z clip behavior (set for vulkan) -->
+ <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
+ <!-- guess based on a3xx and meaning of bits 8 and 9
+ if the guess is right then this is related to point sprite clipping -->
+ <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>
+ <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>
+ <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>
+ </reg32>
+
+ <bitset name="a6xx_gras_xs_cl_cntl" inline="yes">
+ <bitfield name="CLIP_MASK" low="0" high="7"/>
+ <bitfield name="CULL_MASK" low="8" high="15"/>
+ </bitset>
+ <reg32 offset="0x8001" name="GRAS_VS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/>
+ <reg32 offset="0x8002" name="GRAS_DS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/>
+ <reg32 offset="0x8003" name="GRAS_GS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/>
+ <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" low="0" high="10" type="uint" usage="rp_blit"/>
+
+ <reg32 offset="0x8005" name="GRAS_CNTL" usage="rp_blit">
+ <!-- see also RB_RENDER_CONTROL0 -->
+ <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
+ <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
+ <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
+ <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
+ <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
+ <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
+ <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
+ <bitfield name="UNK10" pos="10" type="boolean" variants="A7XX-"/>
+ <bitfield name="UNK11" pos="11" type="boolean" variants="A7XX-"/>
+ </reg32>
+ <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ" usage="rp_blit">
+ <bitfield name="HORZ" low="0" high="8" type="uint"/>
+ <bitfield name="VERT" low="10" high="18" type="uint"/>
+ </reg32>
+
+ <!-- Something connected to depth-stencil attachment size -->
+ <reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/>
+
+ <reg32 offset="0x8008" name="GRAS_UNKNOWN_8008" variants="A7XX-" usage="cmd"/>
+
+ <reg32 offset="0x8009" name="GRAS_UNKNOWN_8009" variants="A7XX-" usage="cmd"/>
+ <reg32 offset="0x800a" name="GRAS_UNKNOWN_800A" variants="A7XX-" usage="cmd"/>
+ <reg32 offset="0x800b" name="GRAS_UNKNOWN_800B" variants="A7XX-" usage="cmd"/>
+ <reg32 offset="0x800c" name="GRAS_UNKNOWN_800C" variants="A7XX-" usage="cmd"/>
+
+ <!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> -->
+
+ <!-- 0x8006-0x800f invalid -->
+ <array offset="0x8010" name="GRAS_CL_VPORT" stride="6" length="16" usage="rp_blit">
+ <reg32 offset="0" name="XOFFSET" type="float"/>
+ <reg32 offset="1" name="XSCALE" type="float"/>
+ <reg32 offset="2" name="YOFFSET" type="float"/>
+ <reg32 offset="3" name="YSCALE" type="float"/>
+ <reg32 offset="4" name="ZOFFSET" type="float"/>
+ <reg32 offset="5" name="ZSCALE" type="float"/>
+ </array>
+ <array offset="0x8070" name="GRAS_CL_Z_CLAMP" stride="2" length="16" usage="rp_blit">
+ <reg32 offset="0" name="MIN" type="float"/>
+ <reg32 offset="1" name="MAX" type="float"/>
+ </array>
+
+ <reg32 offset="0x8090" name="GRAS_SU_CNTL" usage="rp_blit">
+ <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
+ <bitfield name="CULL_BACK" pos="1" type="boolean"/>
+ <bitfield name="FRONT_CW" pos="2" type="boolean"/>
+ <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
+ <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
+ <bitfield name="UNK12" pos="12"/>
+ <bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/>
+ <bitfield name="UNK15" low="15" high="16"/>
+ <!--
+ On gen1 only MULTIVIEW_ENABLE exists. On gen3 we have
+ the ability to add the view index to either the RT array
+ index or the viewport index, and it seems that
+ MULTIVIEW_ENABLE doesn't do anything, instead we need to
+ set at least one of RENDERTARGETINDEXINCR or
+ VIEWPORTINDEXINCR to enable multiview. The blob still
+ sets MULTIVIEW_ENABLE regardless.
+ TODO: what about gen2 (a640)?
+ -->
+ <bitfield name="MULTIVIEW_ENABLE" pos="17" type="boolean"/>
+ <bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean"/>
+ <bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean"/>
+ <bitfield name="UNK20" low="20" high="22"/>
+ </reg32>
+ <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX" usage="rp_blit">
+ <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
+ <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
+ </reg32>
+ <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" usage="rp_blit"/>
+ <!-- 0x8093 invalid -->
+ <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL" usage="rp_blit">
+ <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
+ </reg32>
+ <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" usage="rp_blit"/>
+ <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" usage="rp_blit"/>
+ <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" usage="rp_blit"/>
+ <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
+ <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO" usage="rp_blit">
+ <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
+ <bitfield name="UNK3" pos="3"/>
+ </reg32>
+
+ <reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" usage="cmd">
+ <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
+ <bitfield name="SHIFTAMOUNT" low="1" high="2"/>
+ <bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/>
+ <bitfield name="UNK4" low="4" high="5"/>
+ </reg32>
+ <reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL">
+ <bitfield name="UNK0" pos="0" type="boolean"/>
+ <bitfield name="LINELENGTHEN" pos="1" type="boolean"/>
+ </reg32>
+
+ <bitset name="a6xx_gras_layer_cntl" inline="yes">
+ <bitfield name="WRITES_LAYER" pos="0" type="boolean"/>
+ <bitfield name="WRITES_VIEW" pos="1" type="boolean"/>
+ </bitset>
+ <reg32 offset="0x809b" name="GRAS_VS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/>
+ <reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/>
+ <reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/>
+ <!-- 0x809e/0x809f invalid -->
+
+ <enum name="a6xx_sequenced_thread_dist">
+ <value value="0x0" name="DIST_SCREEN_COORD"/>
+ <value value="0x1" name="DIST_ALL_TO_RB0"/>
+ </enum>
+
+ <enum name="a6xx_single_prim_mode">
+ <value value="0x0" name="NO_FLUSH"/>
+ <doc>
+ In addition to FLUSH_PER_OVERLAP, guarantee that UCHE
+ and CCU don't get out of sync when fetching the previous
+ value for the current pixel. With NO_FLUSH, there's the
+ possibility that the flags for the current pixel are
+ flushed before the data or vice-versa, leading to
+ texture fetches via UCHE getting out of sync values.
+ This mode should eliminate that. It's used in bypass
+ mode for coherent blending
+ (GL_KHR_blend_equation_advanced_coherent) as well as
+ non-coherent blending.
+ </doc>
+ <value value="0x1" name="FLUSH_PER_OVERLAP_AND_OVERWRITE"/>
+ <doc>
+ Invalidate UCHE and wait for any pending work to finish
+ if there was possibly an overlapping primitive prior to
+ the current one. This is similar to a combination of
+ GRAS_SC_CONTROL::INJECT_L2_INVALIDATE_EVENT and
+ WAIT_RB_IDLE_ALL_TRI on a3xx. It's used in GMEM mode for
+ coherent blending
+ (GL_KHR_blend_equation_advanced_coherent).
+ </doc>
+ <value value="0x3" name="FLUSH_PER_OVERLAP"/>
+ </enum>
+
+ <!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE -->
+ <enum name="a6xx_raster_mode">
+ <value value="0x0" name="TYPE_TILED"/>
+ <value value="0x1" name="TYPE_WRITER"/>
+ </enum>
+
+ <!-- I'm guessing this is the same as a3xx -->
+ <enum name="a6xx_raster_direction">
+ <value value="0x0" name="LR_TB"/>
+ <value value="0x1" name="RL_TB"/>
+ <value value="0x2" name="LR_BT"/>
+ <value value="0x3" name="RB_BT"/>
+ </enum>
+
+ <reg32 offset="0x80a0" name="GRAS_SC_CNTL" usage="rp_blit">
+ <bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/>
+ <bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/>
+ <bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/>
+ <bitfield name="RASTER_DIRECTION" low="6" high="7" type="a6xx_raster_direction"/>
+ <bitfield name="SEQUENCED_THREAD_DISTRIBUTION" pos="8" type="a6xx_sequenced_thread_dist"/>
+ <!-- CCUSINGLECACHELINESIZE is ignored unless bit 9 is set -->
+ <bitfield name="UNK9" pos="9" type="boolean"/>
+ <bitfield name="ROTATION" low="10" high="11" type="uint"/>
+ <bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/>
+ </reg32>
+
+ <enum name="a6xx_render_mode">
+ <value value="0x0" name="RENDERING_PASS"/>
+ <value value="0x1" name="BINNING_PASS"/>
+ </enum>
+
+ <enum name="a6xx_buffers_location">
+ <value value="0" name="BUFFERS_IN_GMEM"/>
+ <value value="3" name="BUFFERS_IN_SYSMEM"/>
+ </enum>
+
+ <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL" usage="rp_blit">
+ <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
+ <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
+ <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
+ <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
+ <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location" variants="A6XX"/>
+ <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/>
+ <bitfield name="UNK27" pos="27"/>
+ </reg32>
+
+ <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL" usage="rp_blit">
+ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
+ <bitfield name="UNK2" pos="2"/>
+ <bitfield name="UNK3" pos="3"/>
+ </reg32>
+ <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL" usage="rp_blit">
+ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
+ <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
+ </reg32>
+
+ <bitset name="a6xx_sample_config" inline="yes">
+ <bitfield name="UNK0" pos="0"/>
+ <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/>
+ </bitset>
+
+ <bitset name="a6xx_sample_locations" inline="yes">
+ <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>
+ <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/>
+ <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/>
+ <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/>
+ <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/>
+ <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/>
+ <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/>
+ <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/>
+ </bitset>
+
+ <reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/>
+ <reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/>
+ <reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/>
+
+ <reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="cmd"/>
+
+ <!-- 0x80a7-0x80ae invalid -->
+ <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0" usage="cmd"/>
+
+ <bitset name="a6xx_scissor_xy" inline="yes">
+ <bitfield name="X" low="0" high="15" type="uint"/>
+ <bitfield name="Y" low="16" high="31" type="uint"/>
+ </bitset>
+ <array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" usage="rp_blit">
+ <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
+ <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
+ </array>
+ <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" usage="rp_blit">
+ <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
+ <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
+ </array>
+
+ <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/>
+ <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/>
+
+ <!-- 0x80f4 - 0x80fa are used for VK_KHR_fragment_shading_rate -->
+ <reg64 offset="0x80f4" name="GRAS_UNKNOWN_80F4" variants="A7XX-" usage="cmd"/>
+ <reg64 offset="0x80f5" name="GRAS_UNKNOWN_80F5" variants="A7XX-" usage="cmd"/>
+ <reg64 offset="0x80f6" name="GRAS_UNKNOWN_80F6" variants="A7XX-" usage="cmd"/>
+ <reg64 offset="0x80f8" name="GRAS_UNKNOWN_80F8" variants="A7XX-" usage="cmd"/>
+ <reg64 offset="0x80f9" name="GRAS_UNKNOWN_80F9" variants="A7XX-" usage="cmd"/>
+ <reg64 offset="0x80fa" name="GRAS_UNKNOWN_80FA" variants="A7XX-" usage="cmd"/>
+
+ <enum name="a6xx_lrz_dir_status">
+ <value value="0x1" name="LRZ_DIR_LE"/>
+ <value value="0x2" name="LRZ_DIR_GE"/>
+ <value value="0x3" name="LRZ_DIR_INVALID"/>
+ </enum>
+
+ <reg32 offset="0x8100" name="GRAS_LRZ_CNTL" usage="rp_blit">
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ <doc>LRZ write also disabled for blend/etc.</doc>
+ <bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
+ <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
+ <bitfield name="GREATER" pos="2" type="boolean"/>
+ <doc>
+ Clears the LRZ block being touched to:
+ - 0.0 if GREATER
+ - 1.0 if LESS
+ </doc>
+ <bitfield name="FC_ENABLE" pos="3" type="boolean"/>
+ <!-- set when depth-test + depth-write enabled -->
+ <bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>
+ <bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/>
+ <bitfield name="DIR" low="6" high="7" type="a6xx_lrz_dir_status"/>
+ <doc>
+ If DISABLE_ON_WRONG_DIR enabled - write new LRZ direction into
+ buffer, in case of mismatched direction writes 0 (disables LRZ).
+ </doc>
+ <bitfield name="DIR_WRITE" pos="8" type="boolean"/>
+ <doc>
+ Disable LRZ based on previous direction and the current one.
+ If DIR_WRITE is not enabled - there is no write to direction buffer.
+ </doc>
+ <bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean"/>
+ <bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/>
+ </reg32>
+
+ <enum name="a6xx_fragcoord_sample_mode">
+ <value value="0" name="FRAGCOORD_CENTER"/>
+ <value value="3" name="FRAGCOORD_SAMPLE"/>
+ </enum>
+
+ <reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" low="0" high="2" usage="rp_blit">
+ <bitfield name="SAMPLEID" pos="0" type="boolean"/>
+ <bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/>
+ </reg32>
+
+ <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUF_INFO_0" usage="rp_blit">
+ <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
+ </reg32>
+ <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit"/>
+ <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" usage="rp_blit">
+ <!-- TODO: fix the shr fields -->
+ <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/>
+ <bitfield name="ARRAY_PITCH" low="10" high="28" shr="4" type="uint"/>
+ </reg32>
+
+ <!--
+ The LRZ "fast clear" buffer is initialized to zero's by blob, and
+ read/written when GRAS_LRZ_CNTL.FC_ENABLE (b3) is set. It appears
+ to store 1b/block. It appears that '0' means block has original
+ depth clear value, and '1' means that the corresponding block in
+ LRZ has been modified. Ignoring alignment/padding, the size is
+ given by the formula:
+
+ // calculate LRZ size from depth size:
+ if (nr_samples == 4) {
+ width *= 2;
+ height *= 2;
+ } else if (nr_samples == 2) {
+ height *= 2;
+ }
+
+ lrz_width = div_round_up(width, 8);
+ lrz_heigh = div_round_up(height, 8);
+
+ // calculate # of blocks:
+ nblocksx = div_round_up(lrz_width, 16);
+ nblocksy = div_round_up(lrz_height, 4);
+
+ // fast-clear buffer is 1bit/block:
+ fc_sz = div_round_up(nblocksx * nblocksy, 8);
+
+ In practice the blob seems to switch off FC_ENABLE once the size
+ increases beyond 1 page. Not sure if that is an actual limit or
+ not.
+ -->
+ <reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress" usage="rp_blit"/>
+ <!-- 0x8108 invalid -->
+ <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL" usage="rp_blit">
+ <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
+ </reg32>
+ <!--
+ LRZ buffer represents a single array layer + mip level, and there is
+ a single buffer per depth image. Thus to reuse LRZ between renderpasses
+ it is necessary to track the depth view used in the past renderpass, which
+ GRAS_LRZ_DEPTH_VIEW is for.
+ GRAS_LRZ_CNTL checks if current value of GRAS_LRZ_DEPTH_VIEW is equal to
+ the value stored in the LRZ buffer, if not - LRZ is disabled.
+ -->
+ <reg32 offset="0x810a" name="GRAS_LRZ_DEPTH_VIEW" usage="cmd">
+ <bitfield name="BASE_LAYER" low="0" high="10" type="uint"/>
+ <bitfield name="LAYER_COUNT" low="16" high="26" type="uint"/>
+ <bitfield name="BASE_MIP_LEVEL" low="28" high="31" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x810b" name="GRAS_UNKNOWN_810B" variants="A7XX-" usage="cmd"/>
+
+ <!-- 0x810c-0x810f invalid -->
+
+ <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1" usage="cmd"/>
+
+ <!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR -->
+ <reg32 offset="0x8111" name="GRAS_LRZ_CLEAR_DEPTH_F32" type="float" variants="A7XX-"/>
+
+ <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit"/>
+
+ <!-- Always written together and always equal 09510840 00000a62 -->
+ <reg32 offset="0x8120" name="GRAS_UNKNOWN_8120" variants="A7XX-" usage="cmd"/>
+ <reg32 offset="0x8121" name="GRAS_UNKNOWN_8121" variants="A7XX-" usage="cmd"/>
+
+ <!-- 0x8112-0x83ff invalid -->
+
+ <enum name="a6xx_rotation">
+ <value value="0x0" name="ROTATE_0"/>
+ <value value="0x1" name="ROTATE_90"/>
+ <value value="0x2" name="ROTATE_180"/>
+ <value value="0x3" name="ROTATE_270"/>
+ <value value="0x4" name="ROTATE_HFLIP"/>
+ <value value="0x5" name="ROTATE_VFLIP"/>
+ </enum>
+
+ <bitset name="a6xx_2d_blit_cntl" inline="yes">
+ <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
+ <bitfield name="OVERWRITEEN" pos="3" type="boolean"/>
+ <bitfield name="UNK4" low="4" high="6"/>
+ <bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
+ <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
+ <bitfield name="SCISSOR" pos="16" type="boolean"/>
+ <bitfield name="UNK17" low="17" high="18"/>
+ <!-- required when blitting D24S8/D24X8 -->
+ <bitfield name="D24S8" pos="19" type="boolean"/>
+ <!-- some sort of channel mask, disabled channels are set to zero ? -->
+ <bitfield name="MASK" low="20" high="23"/>
+ <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
+ <bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/>
+ <bitfield name="UNK30" pos="30" type="boolean" variants="A7XX-"/>
+ </bitset>
+
+ <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl" usage="rp_blit"/>
+ <!-- note: the low 8 bits for src coords are valid, probably fixed point
+ it would be a bit weird though, since we subtract 1 from BR coords
+ apparently signed, gallium driver uses negative coords and it works?
+ -->
+ <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X" low="8" high="24" type="int" usage="rp_blit"/>
+ <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X" low="8" high="24" type="int" usage="rp_blit"/>
+ <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y" low="8" high="24" type="int" usage="rp_blit"/>
+ <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y" low="8" high="24" type="int" usage="rp_blit"/>
+ <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="a6xx_reg_xy" usage="rp_blit"/>
+ <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="a6xx_reg_xy" usage="rp_blit"/>
+ <reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/>
+ <reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/>
+ <reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/>
+ <reg32 offset="0x840a" name="GRAS_2D_RESOLVE_CNTL_1" type="a6xx_reg_xy" usage="rp_blit"/>
+ <reg32 offset="0x840b" name="GRAS_2D_RESOLVE_CNTL_2" type="a6xx_reg_xy" usage="rp_blit"/>
+ <!-- 0x840c-0x85ff invalid -->
+
+ <!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
+ <reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="cmd">
+ <bitfield name="UNK7" pos="7" type="boolean"/>
+ <bitfield name="LRZCACHELOCKDIS" pos="11" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
+ <reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX-"/>
+ <array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/>
+ <array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/>
+ <array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/>
+
+ <!-- note 0x8620-0x87ff are not all invalid
+ (in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords)
+ -->
+
+ <!-- same as GRAS_BIN_CONTROL, but without bit 27: -->
+ <reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A6XX" usage="rp_blit">
+ <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
+ <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
+ <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
+ <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
+ <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location"/>
+ <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/>
+ </reg32>
+
+ <reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A7XX-" usage="rp_blit">
+ <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
+ <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
+ <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
+ <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/>
+ <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/>
+ </reg32>
+
+ <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A6XX" usage="rp_blit">
+ <bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/>
+ <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/>
+ <!-- set during binning pass: -->
+ <bitfield name="BINNING" pos="7" type="boolean"/>
+ <bitfield name="UNK8" low="8" high="10"/>
+ <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/>
+ <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/>
+ <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/>
+ <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/>
+ <!-- bit seems to be set whenever depth buffer enabled: -->
+ <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
+ <!-- bitmask of MRTs using UBWC flag buffer: -->
+ <bitfield name="FLAG_MRTS" low="16" high="23"/>
+ </reg32>
+ <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A7XX-" usage="rp_blit">
+ <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/>
+ <!-- set during binning pass: -->
+ <bitfield name="BINNING" pos="7" type="boolean"/>
+ <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/>
+ <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/>
+ <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/>
+ <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" variants="A7XX-" usage="rp_blit">
+ <bitfield name="BINNING" pos="7" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL" usage="rp_blit">
+ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
+ <bitfield name="UNK2" pos="2"/>
+ <bitfield name="UNK3" pos="3"/>
+ </reg32>
+ <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL" usage="rp_blit">
+ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
+ <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/>
+ <reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/>
+ <reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/>
+ <!-- 0x8807-0x8808 invalid -->
+ <!--
+ note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
+ name comes from kernel and is probably right)
+ -->
+ <reg32 offset="0x8809" name="RB_RENDER_CONTROL0" usage="rp_blit">
+ <!-- see also GRAS_CNTL -->
+ <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
+ <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
+ <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
+ <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/>
+ <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/>
+ <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/>
+ <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
+ <bitfield name="UNK10" pos="10" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x880a" name="RB_RENDER_CONTROL1" usage="rp_blit">
+ <!-- enable bits for various FS sysvalue regs: -->
+ <bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
+ <bitfield name="POSTDEPTHCOVERAGE" pos="1" type="boolean"/>
+ <bitfield name="FACENESS" pos="2" type="boolean"/>
+ <bitfield name="SAMPLEID" pos="3" type="boolean"/>
+ <bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/>
+ <bitfield name="CENTERRHW" pos="6" type="boolean"/>
+ <bitfield name="LINELENGTHEN" pos="7" type="boolean"/>
+ <bitfield name="FOVEATION" pos="8" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0" usage="rp_blit">
+ <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
+ <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
+ <bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1" usage="rp_blit">
+ <bitfield name="MRT" low="0" high="3" type="uint"/>
+ </reg32>
+ <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS" usage="rp_blit">
+ <bitfield name="RT0" low="0" high="3"/>
+ <bitfield name="RT1" low="4" high="7"/>
+ <bitfield name="RT2" low="8" high="11"/>
+ <bitfield name="RT3" low="12" high="15"/>
+ <bitfield name="RT4" low="16" high="19"/>
+ <bitfield name="RT5" low="20" high="23"/>
+ <bitfield name="RT6" low="24" high="27"/>
+ <bitfield name="RT7" low="28" high="31"/>
+ </reg32>
+ <reg32 offset="0x880e" name="RB_DITHER_CNTL" usage="cmd">
+ <bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/>
+ <bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/>
+ <bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/>
+ <bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/>
+ <bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/>
+ <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
+ <bitfield name="DITHER_MODE_MRT6" low="12" high="13" type="adreno_rb_dither_mode"/>
+ <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
+ </reg32>
+ <reg32 offset="0x880f" name="RB_SRGB_CNTL" usage="rp_blit">
+ <!-- Same as SP_SRGB_CNTL -->
+ <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
+ <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
+ <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
+ <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
+ <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
+ <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
+ <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
+ <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x8810" name="RB_SAMPLE_CNTL" usage="rp_blit">
+ <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6" usage="cmd"/>
+ <reg32 offset="0x8812" name="RB_UNKNOWN_8812" variants="A7XX-" usage="rp_blit"/>
+ <!-- 0x8813-0x8817 invalid -->
+ <!-- always 0x0 ? -->
+ <reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6" usage="cmd"/>
+ <!-- 0x8819-0x881e all 32 bits -->
+ <reg32 offset="0x8819" name="RB_UNKNOWN_8819" usage="cmd"/>
+ <reg32 offset="0x881a" name="RB_UNKNOWN_881A" usage="cmd"/>
+ <reg32 offset="0x881b" name="RB_UNKNOWN_881B" usage="cmd"/>
+ <reg32 offset="0x881c" name="RB_UNKNOWN_881C" usage="cmd"/>
+ <reg32 offset="0x881d" name="RB_UNKNOWN_881D" usage="cmd"/>
+ <reg32 offset="0x881e" name="RB_UNKNOWN_881E" usage="cmd"/>
+ <!-- 0x881f invalid -->
+ <array offset="0x8820" name="RB_MRT" stride="8" length="8" usage="rp_blit">
+ <reg32 offset="0x0" name="CONTROL">
+ <bitfield name="BLEND" pos="0" type="boolean"/>
+ <bitfield name="BLEND2" pos="1" type="boolean"/>
+ <bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
+ <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
+ <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
+ </reg32>
+ <reg32 offset="0x1" name="BLEND_CONTROL">
+ <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
+ <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
+ <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
+ <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
+ <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
+ <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
+ </reg32>
+ <reg32 offset="0x2" name="BUF_INFO" variants="A6XX">
+ <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
+ <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
+ <bitfield name="UNK10" pos="10"/>
+ <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
+ </reg32>
+ <reg32 offset="0x2" name="BUF_INFO" variants="A7XX-">
+ <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
+ <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
+ <bitfield name="UNK10" pos="10"/>
+ <bitfield name="LOSSLESSCOMPEN" pos="11" type="boolean"/>
+ <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
+ </reg32>
+ <!--
+ at least in gmem, things seem to be aligned to pitch of 64..
+ maybe an artifact of tiled format used in gmem?
+ -->
+ <reg32 offset="0x3" name="PITCH" shr="6" high="15" type="uint"/>
+ <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" high="28" type="uint"/>
+ <!--
+ Compared to a5xx and before, we configure both a GMEM base and
+ external base. Not sure if this is to facilitate GMEM save/
+ restore for context switch, or just to simplify state setup to
+ not have to care about GMEM vs BYPASS mode.
+ -->
+ <!-- maybe something in low bits since alignment of 1 doesn't make sense? -->
+ <reg64 offset="0x5" name="BASE" type="waddress" align="1"/>
+
+ <reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/>
+ </array>
+
+ <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float" usage="rp_blit"/>
+ <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float" usage="rp_blit"/>
+ <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float" usage="rp_blit"/>
+ <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float" usage="rp_blit"/>
+ <reg32 offset="0x8864" name="RB_ALPHA_CONTROL" usage="cmd">
+ <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
+ <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
+ <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
+ </reg32>
+ <reg32 offset="0x8865" name="RB_BLEND_CNTL" usage="rp_blit">
+ <!-- per-mrt enable bit -->
+ <bitfield name="ENABLE_BLEND" low="0" high="7"/>
+ <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
+ <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
+ <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
+ <bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/>
+ <bitfield name="SAMPLE_MASK" low="16" high="31"/>
+ </reg32>
+ <!-- 0x8866-0x886f invalid -->
+ <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL" usage="rp_blit">
+ <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
+ </reg32>
+
+ <reg32 offset="0x8871" name="RB_DEPTH_CNTL" usage="rp_blit">
+ <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
+ <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
+ <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
+ <doc>
+ Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER
+ also set when Z_BOUNDS_ENABLE is set
+ </doc>
+ <bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/>
+ <bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x8114" name="GRAS_SU_DEPTH_CNTL" usage="rp_blit">
+ <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
+ </reg32>
+ <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
+ <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A6XX" usage="rp_blit">
+ <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
+ <bitfield name="UNK3" low="3" high="4"/>
+ </reg32>
+ <!-- first 4 bits duplicates GRAS_SU_DEPTH_BUFFER_INFO -->
+ <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit">
+ <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
+ <bitfield name="UNK3" low="3" high="4"/>
+ <bitfield name="TILEMODE" low="5" high="6" type="a6xx_tile_mode"/>
+ <bitfield name="LOSSLESSCOMPEN" pos="7" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint" usage="rp_blit"/>
+ <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint" usage="rp_blit"/>
+ <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/>
+ <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/>
+
+ <reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float" usage="rp_blit"/>
+ <reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float" usage="rp_blit"/>
+ <!-- 0x887a-0x887f invalid -->
+ <reg32 offset="0x8880" name="RB_STENCIL_CONTROL" usage="rp_blit">
+ <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
+ <!--
+ set for stencil operations that require read from stencil
+ buffer, but not for example for stencil clear (which does
+ not require read).. so guessing this is analogous to
+ READ_DEST_ENABLE for color buffer..
+ -->
+ <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
+ <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
+ <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
+ <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
+ <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
+ <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
+ <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
+ <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
+ <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
+ </reg32>
+ <reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" usage="rp_blit">
+ <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A6XX" usage="rp_blit">
+ <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
+ <bitfield name="UNK1" pos="1" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A7XX-" usage="rp_blit">
+ <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
+ <bitfield name="UNK1" pos="1" type="boolean"/>
+ <bitfield name="TILEMODE" low="2" high="3" type="a6xx_tile_mode"/>
+ </reg32>
+ <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint" usage="rp_blit"/>
+ <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint" usage="rp_blit"/>
+ <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/>
+ <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/>
+ <reg32 offset="0x8887" name="RB_STENCILREF" usage="rp_blit">
+ <bitfield name="REF" low="0" high="7"/>
+ <bitfield name="BFREF" low="8" high="15"/>
+ </reg32>
+ <reg32 offset="0x8888" name="RB_STENCILMASK" usage="rp_blit">
+ <bitfield name="MASK" low="0" high="7"/>
+ <bitfield name="BFMASK" low="8" high="15"/>
+ </reg32>
+ <reg32 offset="0x8889" name="RB_STENCILWRMASK" usage="rp_blit">
+ <bitfield name="WRMASK" low="0" high="7"/>
+ <bitfield name="BFWRMASK" low="8" high="15"/>
+ </reg32>
+ <!-- 0x888a-0x888f invalid -->
+ <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/>
+ <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL" usage="cmd">
+ <bitfield name="DISABLE" pos="0" type="boolean"/>
+ <bitfield name="COPY" pos="1" type="boolean"/>
+ </reg32>
+ <!-- 0x8892-0x8897 invalid -->
+ <reg32 offset="0x8898" name="RB_LRZ_CNTL" usage="rp_blit">
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/>
+ <!-- 0x8899-0x88bf invalid -->
+ <!-- clamps depth value for depth test/write -->
+ <reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float" usage="rp_blit"/>
+ <reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float" usage="rp_blit"/>
+ <!-- 0x88c2-0x88cf invalid-->
+ <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0" usage="rp_blit">
+ <bitfield name="UNK0" low="0" high="12"/>
+ <bitfield name="UNK16" low="16" high="26"/>
+ </reg32>
+ <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/>
+ <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/>
+ <!-- weird to duplicate other regs from same block?? -->
+ <reg32 offset="0x88d3" name="RB_BIN_CONTROL2" usage="rp_blit">
+ <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
+ <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
+ </reg32>
+ <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="a6xx_reg_xy" usage="rp_blit"/>
+ <reg32 offset="0x88d5" name="RB_BLIT_GMEM_MSAA_CNTL" usage="rp_blit">
+ <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
+ </reg32>
+ <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/>
+ <!-- s/DST_FORMAT/DST_INFO/ probably: -->
+ <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO" usage="rp_blit">
+ <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
+ <bitfield name="FLAGS" pos="2" type="boolean"/>
+ <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
+ <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
+ <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>
+ <bitfield name="UNK15" pos="15" type="boolean"/>
+ </reg32>
+ <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64" usage="rp_blit"/>
+ <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/>
+ <!-- array-pitch is size of layer -->
+ <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint" usage="rp_blit"/>
+ <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64" usage="rp_blit"/>
+ <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH" usage="rp_blit">
+ <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
+ <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0" usage="rp_blit"/>
+ <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1" usage="rp_blit"/>
+ <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2" usage="rp_blit"/>
+ <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3" usage="rp_blit"/>
+
+ <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
+ <reg32 offset="0x88e3" name="RB_BLIT_INFO" usage="rp_blit">
+ <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color restore? -->
+ <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
+ <bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging -->
+ <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
+ <doc>
+ For clearing depth/stencil
+ 1 - depth
+ 2 - stencil
+ 3 - depth+stencil
+ For clearing color buffer:
+ then probably a component mask, I always see 0xf
+ </doc>
+ <bitfield name="CLEAR_MASK" low="4" high="7"/>
+ <!-- set when this is the last resolve on a650+ -->
+ <bitfield name="LAST" low="8" high="9"/>
+ <!--
+ a618 GLES: color render target number being resolved for RM6_RESOLVE, 0x8 for depth, 0x9 for separate stencil.
+ a618 VK: 0x8 for depth RM6_RESOLVE, 0x9 for separate stencil, 0 otherwise.
+
+ We believe this is related to concurrent resolves
+ -->
+ <bitfield name="BUFFER_ID" low="12" high="15"/>
+ </reg32>
+ <reg32 offset="0x88e4" name="RB_UNKNOWN_88E4" variants="A7XX-" usage="rp_blit">
+ <!-- Value conditioned based on predicate, changed before blits -->
+ <bitfield name="UNK0" pos="0" type="boolean"/>
+ </reg32>
+
+ <enum name="a6xx_ccu_cache_size">
+ <value value="0x0" name="CCU_CACHE_SIZE_FULL"/>
+ <value value="0x1" name="CCU_CACHE_SIZE_HALF"/>
+ <value value="0x2" name="CCU_CACHE_SIZE_QUARTER"/>
+ <value value="0x3" name="CCU_CACHE_SIZE_EIGHTH"/>
+ </enum>
+ <reg32 offset="0x88e5" name="RB_CCU_CNTL2" variants="A7XX-" usage="cmd">
+ <bitfield name="DEPTH_OFFSET_HI" pos="0" type="hex"/>
+ <bitfield name="COLOR_OFFSET_HI" pos="2" type="hex"/>
+ <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/>
+ <!-- GMEM offset of CCU depth cache -->
+ <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/>
+ <bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/>
+ <!-- GMEM offset of CCU color cache
+ for GMEM rendering, we set it to GMEM size minus the minimum
+ CCU color cache size. CCU color cache will be needed in some
+ resolve cases, and in those cases we need to reserve the end
+ of GMEM for color cache.
+ -->
+ <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/>
+ </reg32>
+ <!-- 0x88e6-0x88ef invalid -->
+ <!-- always 0x0 ? -->
+ <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11" usage="cmd"/>
+ <!-- could be for separate stencil? (or may not be a flag buffer at all) -->
+ <reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/>
+ <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH">
+ <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
+ <bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/>
+ <!-- Connected to VK_EXT_fragment_density_map? -->
+ <reg32 offset="0x88f5" name="RB_UNKNOWN_88F5" variants="A7XX-"/>
+ <!-- 0x88f6-0x88ff invalid -->
+ <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/>
+ <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH" usage="rp_blit">
+ <bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/>
+ <!-- TODO: actually part of array pitch -->
+ <bitfield name="UNK8" low="8" high="10"/>
+ <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
+ </reg32>
+ <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8" usage="rp_blit">
+ <reg64 offset="0" name="ADDR" type="waddress" align="64"/>
+ <reg32 offset="2" name="PITCH">
+ <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
+ <bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/>
+ </reg32>
+ </array>
+ <!-- 0x891b-0x8926 invalid -->
+ <doc>
+ RB_SAMPLE_COUNT_ADDR register is used up to (and including) a730. After that
+ the address is specified through CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT.
+ </doc>
+ <reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16" usage="cmd"/>
+ <!-- 0x8929-0x89ff invalid -->
+
+ <!-- TODO: there are some registers in the 0x8a00-0x8bff range -->
+
+ <!--
+ These show up in a6xx gen3+ but so far haven't found an example of
+ blob writing non-zero:
+ -->
+ <reg32 offset="0x8a00" name="RB_UNKNOWN_8A00" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0x8a10" name="RB_UNKNOWN_8A10" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0x8a20" name="RB_UNKNOWN_8A20" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0x8a30" name="RB_UNKNOWN_8A30" variants="A6XX" usage="rp_blit"/>
+
+ <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl" usage="rp_blit"/>
+ <reg32 offset="0x8c01" name="RB_2D_UNKNOWN_8C01" low="0" high="31" usage="rp_blit"/>
+
+ <bitset name="a6xx_2d_surf_info" inline="yes">
+ <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
+ <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
+ <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
+ <bitfield name="FLAGS" pos="12" type="boolean"/>
+ <bitfield name="SRGB" pos="13" type="boolean"/>
+ <!-- the rest is only for src -->
+ <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
+ <bitfield name="FILTER" pos="16" type="boolean"/>
+ <bitfield name="UNK17" pos="17" type="boolean"/>
+ <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>
+ <bitfield name="UNK19" pos="19" type="boolean"/>
+ <bitfield name="UNK20" pos="20" type="boolean"/>
+ <bitfield name="UNK21" pos="21" type="boolean"/>
+ <bitfield name="UNK22" pos="22" type="boolean"/>
+ <bitfield name="UNK23" low="23" high="26"/>
+ <bitfield name="UNK28" pos="28" type="boolean"/>
+ </bitset>
+
+ <!-- 0x8c02-0x8c16 invalid -->
+ <!-- TODO: RB_2D_DST_INFO has 17 valid bits (doesn't match a6xx_2d_surf_info) -->
+ <reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info" usage="rp_blit"/>
+ <reg64 offset="0x8c18" name="RB_2D_DST" type="waddress" align="64" usage="rp_blit"/>
+ <reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/>
+ <!-- this is a guess but seems likely (for NV12/IYUV): -->
+ <reg64 offset="0x8c1b" name="RB_2D_DST_PLANE1" type="waddress" align="64" usage="rp_blit"/>
+ <reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/>
+ <reg64 offset="0x8c1e" name="RB_2D_DST_PLANE2" type="waddress" align="64" usage="rp_blit"/>
+
+ <reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress" align="64" usage="rp_blit"/>
+ <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/>
+ <!-- this is a guess but seems likely (for NV12 with UBWC): -->
+ <reg64 offset="0x8c23" name="RB_2D_DST_FLAGS_PLANE" type="waddress" align="64" usage="rp_blit"/>
+ <reg32 offset="0x8c25" name="RB_2D_DST_FLAGS_PLANE_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/>
+
+ <!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers -->
+ <!-- unlike a5xx, these are per channel values rather than packed -->
+ <reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0" usage="rp_blit"/>
+ <reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1" usage="rp_blit"/>
+ <reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2" usage="rp_blit"/>
+ <reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3" usage="rp_blit"/>
+ <!-- 0x8c34-0x8dff invalid -->
+
+ <!-- always 0x1 ? either doesn't exist for a650 or write-only: -->
+ <reg32 offset="0x8e01" name="RB_UNKNOWN_8E01" usage="cmd"/>
+ <!-- 0x8e00-0x8e03 invalid -->
+ <reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff -->
+ <reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
+ <!-- 0x02080000 in GMEM, zero otherwise? -->
+ <reg32 offset="0x8e06" name="RB_UNKNOWN_8E06" variants="A7XX-" usage="cmd"/>
+
+ <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A6XX">
+ <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/>
+ <!-- concurrent resolves are apparently a 2-bit enum on a650+ -->
+ <bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/>
+ <bitfield name="DEPTH_OFFSET_HI" pos="7" type="hex"/>
+ <bitfield name="COLOR_OFFSET_HI" pos="9" type="hex"/>
+ <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/>
+ <!-- GMEM offset of CCU depth cache -->
+ <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/>
+ <bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/>
+ <!-- GMEM offset of CCU color cache
+ for GMEM rendering, we set it to GMEM size minus the minimum
+ CCU color cache size. CCU color cache will be needed in some
+ resolve cases, and in those cases we need to reserve the end
+ of GMEM for color cache.
+ -->
+ <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/>
+ <!--TODO: valid mask 0xfffffc1f -->
+ </reg32>
+ <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A7XX-">
+ <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/>
+ <bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/>
+ <!-- rest of the bits were moved to RB_CCU_CNTL2 -->
+ </reg32>
+ <reg32 offset="0x8e08" name="RB_NC_MODE_CNTL">
+ <bitfield name="MODE" pos="0" type="boolean"/>
+ <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
+ <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
+ <bitfield name="AMSBC" pos="4" type="boolean"/>
+ <bitfield name="UPPER_BIT" pos="10" type="uint"/>
+ <bitfield name="RGB565_PREDICATOR" pos="11" type="boolean"/>
+ <bitfield name="UNK12" low="12" high="13"/>
+ </reg32>
+ <reg32 offset="0x8e09" name="RB_UNKNOWN_8E09" variants="A7XX-" usage="cmd"/>
+ <!-- 0x8e09-0x8e0f invalid -->
+ <array offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/>
+ <array offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/>
+ <!-- 0x8e1d-0x8e1f invalid -->
+ <!-- 0x8e20-0x8e25 more perfcntr sel? -->
+ <!-- 0x8e26-0x8e27 invalid -->
+ <reg32 offset="0x8e28" name="RB_CMP_DBG_ECO_CNTL"/>
+ <!-- 0x8e29-0x8e2b invalid -->
+ <array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/>
+ <array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX-"/>
+ <reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/>
+ <reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
+ <!-- 0x8e3e-0x8e4f invalid -->
+ <!-- GMEM save/restore for preemption: -->
+ <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE" pos="0" type="boolean"/>
+ <!-- address for GMEM save/restore? -->
+ <reg32 offset="0x8e51" name="RB_UNKNOWN_8E51" type="waddress" align="1"/>
+ <!-- 0x8e53-0x8e7f invalid -->
+ <reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX-" usage="cmd"/>
+ <!-- 0x8e80-0x8e83 are valid -->
+ <!-- 0x8e84-0x90ff invalid -->
+
+ <!-- 0x9000-0x90ff invalid -->
+
+ <reg32 offset="0x9100" name="VPC_GS_PARAM" variants="A6XX" usage="rp_blit">
+ <bitfield name="LINELENGTHLOC" low="0" high="7" type="uint"/>
+ </reg32>
+
+ <bitset name="a6xx_vpc_xs_clip_cntl" inline="yes">
+ <bitfield name="CLIP_MASK" low="0" high="7" type="uint"/>
+ <!-- there can be up to 8 total clip/cull distance outputs,
+ but apparenly VPC can only deal with vec4, so when there are
+ more than 4 outputs a second location needs to be programmed
+ -->
+ <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/>
+ <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/>
+ </bitset>
+ <reg32 offset="0x9101" name="VPC_VS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
+ <reg32 offset="0x9102" name="VPC_GS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
+ <reg32 offset="0x9103" name="VPC_DS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
+
+ <reg32 offset="0x9311" name="VPC_VS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
+ <reg32 offset="0x9312" name="VPC_GS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
+ <reg32 offset="0x9313" name="VPC_DS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
+
+ <bitset name="a6xx_vpc_xs_layer_cntl" inline="yes">
+ <bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
+ <bitfield name="VIEWLOC" low="8" high="15" type="uint"/>
+ <bitfield name="SHADINGRATELOC" low="16" high="23" type="uint" variants="A7XX-"/>
+ </bitset>
+
+ <reg32 offset="0x9104" name="VPC_VS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
+ <reg32 offset="0x9105" name="VPC_GS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
+ <reg32 offset="0x9106" name="VPC_DS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
+
+ <reg32 offset="0x9314" name="VPC_VS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
+ <reg32 offset="0x9315" name="VPC_GS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
+ <reg32 offset="0x9316" name="VPC_DS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
+
+ <reg32 offset="0x9107" name="VPC_UNKNOWN_9107" variants="A6XX" usage="rp_blit">
+ <!-- this mirrors PC_RASTER_CNTL::DISCARD, although it seems it's unused -->
+ <bitfield name="RASTER_DISCARD" pos="0" type="boolean"/>
+ <bitfield name="UNK2" pos="2" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x9108" name="VPC_POLYGON_MODE" usage="rp_blit">
+ <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
+ </reg32>
+
+ <bitset name="a6xx_primitive_cntl_0" inline="yes">
+ <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
+ <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
+ <bitfield name="D3D_VERTEX_ORDERING" pos="2" type="boolean">
+ <doc>
+ Swaps TESS_CW_TRIS/TESS_CCW_TRIS, and also makes
+ triangle fans and triangle strips use the D3D
+ order instead of the OpenGL order.
+ </doc>
+ </bitfield>
+ <bitfield name="UNK3" pos="3" type="boolean"/>
+ </bitset>
+
+ <bitset name="a6xx_primitive_cntl_5" inline="yes">
+ <doc>
+ geometry shader
+ </doc>
+ <!-- TODO: first 16 bits are valid so something is wrong or missing here -->
+ <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
+ <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
+ <bitfield name="LINELENGTHEN" pos="15" type="boolean"/>
+ <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
+ <bitfield name="UNK18" pos="18"/>
+ </bitset>
+
+ <bitset name="a6xx_multiview_cntl" inline="yes">
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ <bitfield name="DISABLEMULTIPOS" pos="1" type="boolean">
+ <doc>
+ Multi-position output lets the last geometry
+ stage shader write multiple copies of
+ gl_Position. If disabled then the VS is run once
+ for each view, and ViewID is passed as a
+ register to the VS.
+ </doc>
+ </bitfield>
+ <bitfield name="VIEWS" low="2" high="6" type="uint"/>
+ </bitset>
+
+ <reg32 offset="0x9109" name="VPC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" variants="A7XX-" usage="rp_blit"/>
+ <reg32 offset="0x910a" name="VPC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" variants="A7XX-" usage="rp_blit"/>
+ <reg32 offset="0x910b" name="VPC_MULTIVIEW_MASK" type="hex" low="0" high="15" variants="A7XX-" usage="rp_blit"/>
+ <reg32 offset="0x910c" name="VPC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" variants="A7XX-" usage="rp_blit"/>
+
+ <enum name="a6xx_varying_interp_mode">
+ <value value="0" name="INTERP_SMOOTH"/>
+ <value value="1" name="INTERP_FLAT"/>
+ <value value="2" name="INTERP_ZERO"/>
+ <value value="3" name="INTERP_ONE"/>
+ </enum>
+
+ <enum name="a6xx_varying_ps_repl_mode">
+ <value value="0" name="PS_REPL_NONE"/>
+ <value value="1" name="PS_REPL_S"/>
+ <value value="2" name="PS_REPL_T"/>
+ <value value="3" name="PS_REPL_ONE_MINUS_T"/>
+ </enum>
+
+ <!-- 0x9109-0x91ff invalid -->
+ <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8" usage="rp_blit">
+ <doc>Packed array of a6xx_varying_interp_mode</doc>
+ <reg32 offset="0x0" name="MODE"/>
+ </array>
+ <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8" usage="rp_blit">
+ <doc>Packed array of a6xx_varying_ps_repl_mode</doc>
+ <reg32 offset="0x0" name="MODE"/>
+ </array>
+
+ <!-- always 0x0 -->
+ <reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31" variants="A6XX" usage="cmd"/>
+ <reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31" variants="A6XX" usage="cmd"/>
+
+ <array offset="0x9212" name="VPC_VAR" stride="1" length="4" usage="rp_blit">
+ <!-- one bit per varying component: -->
+ <reg32 offset="0" name="DISABLE"/>
+ </array>
+
+ <reg32 offset="0x9216" name="VPC_SO_CNTL" usage="rp_blit">
+ <!--
+ Choose which DWORD to write to. There is an array of
+ (4 * 64) DWORD's, dumped in the devcoredump at
+ HLSQ_INST_RAM dword 0x400. Each DWORD corresponds to a
+ (VPC location, stream) pair like so:
+
+ location 0, stream 0
+ location 2, stream 0
+ ...
+ location 126, stream 0
+ location 0, stream 1
+ location 2, stream 1
+ ...
+ location 126, stream 1
+ location 0, stream 2
+ ...
+
+ When EmitStreamVertex(N) happens, the HW goes to DWORD
+ 64 * N and then "executes" the next 64 DWORD's.
+
+ This field is auto-incremented when VPC_SO_PROG is
+ written to.
+ -->
+ <bitfield name="ADDR" low="0" high="7" type="hex"/>
+ <!-- clear all A_EN and B_EN bits for all DWORD's -->
+ <bitfield name="RESET" pos="16" type="boolean"/>
+ </reg32>
+ <!-- special register, write multiple times to load SO program (not readable) -->
+ <reg32 offset="0x9217" name="VPC_SO_PROG" usage="rp_blit">
+ <bitfield name="A_BUF" low="0" high="1" type="uint"/>
+ <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
+ <bitfield name="A_EN" pos="11" type="boolean"/>
+ <bitfield name="B_BUF" low="12" high="13" type="uint"/>
+ <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
+ <bitfield name="B_EN" pos="23" type="boolean"/>
+ </reg32>
+
+ <reg64 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32" usage="cmd"/>
+
+ <array offset="0x921a" name="VPC_SO" stride="7" length="4" usage="cmd">
+ <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/>
+ <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/>
+ <reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/>
+ <reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/>
+ <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/>
+ </array>
+
+ <reg32 offset="0x9236" name="VPC_POINT_COORD_INVERT" usage="cmd">
+ <bitfield name="INVERT" pos="0" type="boolean"/>
+ </reg32>
+ <!-- 0x9237-0x92ff invalid -->
+ <!-- always 0x0 ? -->
+ <reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2" usage="cmd"/>
+
+ <bitset name="a6xx_vpc_xs_pack" inline="yes">
+ <doc>
+ num of varyings plus four for gl_Position (plus one if gl_PointSize)
+ plus # of transform-feedback (streamout) varyings if using the
+ hw streamout (rather than stg instructions in shader)
+ </doc>
+ <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
+ <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
+ <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
+ <bitfield name="EXTRAPOS" low="24" high="27" type="uint">
+ <doc>
+ The number of extra copies of POSITION, i.e.
+ number of views minus one when multi-position
+ output is enabled, otherwise 0.
+ </doc>
+ </bitfield>
+ </bitset>
+ <reg32 offset="0x9301" name="VPC_VS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/>
+ <reg32 offset="0x9302" name="VPC_GS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/>
+ <reg32 offset="0x9303" name="VPC_DS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/>
+
+ <reg32 offset="0x9304" name="VPC_CNTL_0" usage="rp_blit">
+ <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
+ <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->
+ <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/>
+ <bitfield name="VARYING" pos="16" type="boolean"/>
+ <bitfield name="VIEWIDLOC" low="24" high="31" type="uint">
+ <doc>
+ This VPC location will be overwritten with
+ ViewID when multiview is enabled. It's used when
+ fragment shaders read ViewID. It's only
+ strictly required for multi-position output,
+ where the same VS invocation is used for all the
+ views at once, but it can be used when multi-pos
+ output is disabled too, to avoid having to pass
+ ViewID through the VS.
+ </doc>
+ </bitfield>
+ </reg32>
+
+ <reg32 offset="0x9305" name="VPC_SO_STREAM_CNTL" usage="rp_blit">
+ <!--
+ It's offset by 1, and 0 means "disabled"
+ -->
+ <bitfield name="BUF0_STREAM" low="0" high="2" type="uint"/>
+ <bitfield name="BUF1_STREAM" low="3" high="5" type="uint"/>
+ <bitfield name="BUF2_STREAM" low="6" high="8" type="uint"/>
+ <bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/>
+ <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>
+ </reg32>
+ <reg32 offset="0x9306" name="VPC_SO_DISABLE" usage="rp_blit">
+ <bitfield name="DISABLE" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x9307" name="VPC_POLYGON_MODE2" variants="A7XX-" usage="rp_blit">
+ <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
+ </reg32>
+ <reg32 offset="0x9308" name="VPC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit">
+ <bitfield name="SIZE_GMEM" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="0x9309" name="VPC_ATTR_BUF_BASE_GMEM" variants="A7XX-" usage="rp_blit">
+ <bitfield name="BASE_GMEM" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="0x9b09" name="PC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit">
+ <bitfield name="SIZE_GMEM" low="0" high="31"/>
+ </reg32>
+
+ <!-- 0x9307-0x95ff invalid -->
+
+ <!-- TODO: 0x9600-0x97ff range -->
+ <reg32 offset="0x9600" name="VPC_DBG_ECO_CNTL" usage="cmd"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask -->
+ <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" usage="cmd"/>
+ <reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0" usage="cmd"/> <!-- always 0x0 ? -->
+ <reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/>
+ <array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6" variants="A6XX"/>
+ <array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX-"/>
+ <!-- 0x960a-0x9623 invalid -->
+ <!-- TODO: regs from 0x9624-0x963a -->
+ <!-- 0x963b-0x97ff invalid -->
+
+ <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint" usage="rp_blit"/>
+
+ <!-- always 0x0 ? -->
+ <reg32 offset="0x9801" name="PC_HS_INPUT_SIZE" usage="rp_blit">
+ <bitfield name="SIZE" low="0" high="10" type="uint"/>
+ <bitfield name="UNK13" pos="13"/>
+ </reg32>
+
+ <reg32 offset="0x9802" name="PC_TESS_CNTL" usage="rp_blit">
+ <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
+ <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
+ </reg32>
+
+ <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" usage="rp_blit"/>
+ <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" usage="rp_blit"/>
+
+ <reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" usage="rp_blit"/>
+
+ <reg32 offset="0x9806" name="PC_PS_CNTL" usage="rp_blit">
+ <bitfield name="PRIMITIVEIDEN" pos="0" type="boolean"/>
+ </reg32>
+
+ <!-- New in a6xx gen3+ -->
+ <reg32 offset="0x9808" name="PC_SO_STREAM_CNTL" usage="rp_blit">
+ <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>
+ </reg32>
+
+ <reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL">
+ <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
+ </reg32>
+ <!-- 0x980b-0x983f invalid -->
+
+ <!-- 0x9840 - 0x9842 are not readable -->
+ <reg32 offset="0x9840" name="PC_DRAW_CMD">
+ <bitfield name="STATE_ID" low="0" high="7"/>
+ </reg32>
+
+ <reg32 offset="0x9841" name="PC_DISPATCH_CMD">
+ <bitfield name="STATE_ID" low="0" high="7"/>
+ </reg32>
+
+ <reg32 offset="0x9842" name="PC_EVENT_CMD">
+ <!-- I think only the low bit is actually used? -->
+ <bitfield name="STATE_ID" low="16" high="23"/>
+ <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
+ </reg32>
+
+ <!--
+ 0x9880 written in a lot of places by SQE, same value gets written
+ to control reg 0x12a. Set by CP_SET_MARKER, so lets name it after
+ that
+ -->
+ <reg32 offset="0x9880" name="PC_MARKER"/>
+
+ <!-- 0x9843-0x997f invalid -->
+
+ <reg32 offset="0x9981" name="PC_POLYGON_MODE" variants="A6XX" usage="rp_blit">
+ <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
+ </reg32>
+ <reg32 offset="0x9809" name="PC_POLYGON_MODE" variants="A7XX-" usage="rp_blit">
+ <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
+ </reg32>
+
+ <reg32 offset="0x9980" name="PC_RASTER_CNTL" variants="A6XX" usage="rp_blit">
+ <!-- which stream to send to GRAS -->
+ <bitfield name="STREAM" low="0" high="1" type="uint"/>
+ <!-- discard primitives before rasterization -->
+ <bitfield name="DISCARD" pos="2" type="boolean"/>
+ </reg32>
+ <!-- VPC_RASTER_CNTL -->
+ <reg32 offset="0x9107" name="PC_RASTER_CNTL" variants="A7XX-" usage="rp_blit">
+ <!-- which stream to send to GRAS -->
+ <bitfield name="STREAM" low="0" high="1" type="uint"/>
+ <!-- discard primitives before rasterization -->
+ <bitfield name="DISCARD" pos="2" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x9317" name="PC_RASTER_CNTL_V2" variants="A7XX-" usage="rp_blit">
+ <!-- which stream to send to GRAS -->
+ <bitfield name="STREAM" low="0" high="1" type="uint"/>
+ <!-- discard primitives before rasterization -->
+ <bitfield name="DISCARD" pos="2" type="boolean"/>
+ </reg32>
+
+ <!-- Both are a750+.
+ Probably needed to correctly overlap execution of several draws.
+ -->
+ <reg32 offset="0x9885" name="PC_TESS_PARAM_SIZE" variants="A7XX-" usage="cmd"/>
+ <!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of
+ this additional space is not known.
+ -->
+ <reg32 offset="0x9886" name="PC_TESS_FACTOR_SIZE" variants="A7XX-" usage="cmd"/>
+
+ <!-- 0x9982-0x9aff invalid -->
+
+ <reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" usage="rp_blit"/>
+
+ <bitset name="a6xx_xs_out_cntl" inline="yes">
+ <doc>
+ num of varyings plus four for gl_Position (plus one if gl_PointSize)
+ plus # of transform-feedback (streamout) varyings if using the
+ hw streamout (rather than stg instructions in shader)
+ </doc>
+ <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
+ <bitfield name="PSIZE" pos="8" type="boolean"/>
+ <bitfield name="LAYER" pos="9" type="boolean"/>
+ <bitfield name="VIEW" pos="10" type="boolean"/>
+ <!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit -->
+ <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
+ <bitfield name="CLIP_MASK" low="16" high="23" type="uint"/>
+ <bitfield name="SHADINGRATE" pos="24" type="boolean" variants="A7XX-"/>
+ </bitset>
+
+ <reg32 offset="0x9b01" name="PC_VS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>
+ <reg32 offset="0x9b02" name="PC_GS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>
+ <!-- since HS can't output anything, only PRIMITIVE_ID is valid -->
+ <reg32 offset="0x9b03" name="PC_HS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>
+ <reg32 offset="0x9b04" name="PC_DS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>
+
+ <reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" usage="rp_blit"/>
+
+ <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6" variants="A6XX" usage="rp_blit">
+ <doc>
+ size in vec4s of per-primitive storage for gs. TODO: not actually in VPC
+ </doc>
+ <bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x9b07" name="PC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" usage="rp_blit"/>
+ <!-- mask of enabled views, doesn't exist on A630 -->
+ <reg32 offset="0x9b08" name="PC_MULTIVIEW_MASK" type="hex" low="0" high="15" usage="rp_blit"/>
+ <!-- 0x9b09-0x9bff invalid -->
+ <reg32 offset="0x9c00" name="PC_2D_EVENT_CMD">
+ <!-- special register (but note first 8 bits can be written/read) -->
+ <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
+ <bitfield name="STATE_ID" low="8" high="15"/>
+ </reg32>
+ <!-- 0x9c01-0x9dff invalid -->
+ <!-- TODO: 0x9e00-0xa000 range incomplete -->
+ <reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/>
+ <reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg64 offset="0x9e04" name="PC_DRAW_INDX_BASE"/>
+ <reg32 offset="0x9e06" name="PC_DRAW_FIRST_INDX" type="uint"/>
+ <reg32 offset="0x9e07" name="PC_DRAW_MAX_INDICES" type="uint"/>
+ <reg64 offset="0x9e08" name="PC_TESSFACTOR_ADDR" variants="A6XX" type="waddress" align="32" usage="cmd"/>
+ <reg64 offset="0x9810" name="PC_TESSFACTOR_ADDR" variants="A7XX-" type="waddress" align="32" usage="cmd"/>
+
+ <reg32 offset="0x9e0b" name="PC_DRAW_INITIATOR" type="vgt_draw_initiator_a4xx">
+ <doc>
+ Possibly not really "initiating" the draw but the layout is similar
+ to VGT_DRAW_INITIATOR on older gens
+ </doc>
+ </reg32>
+ <reg32 offset="0x9e0c" name="PC_DRAW_NUM_INSTANCES" type="uint"/>
+ <reg32 offset="0x9e0d" name="PC_DRAW_NUM_INDICES" type="uint"/>
+
+ <!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
+ <reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
+ <bitfield name="UNK0" low="0" high="15"/>
+ <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
+ <bitfield name="VSC_N" low="22" high="26" type="uint"/>
+ </reg32>
+ <reg64 offset="0x9e12" name="PC_BIN_PRIM_STRM" type="waddress" align="32"/>
+ <reg64 offset="0x9e14" name="PC_BIN_DRAW_STRM" type="waddress" align="32"/>
+
+ <reg32 offset="0x9e1c" name="PC_VISIBILITY_OVERRIDE">
+ <doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc>
+ <bitfield name="OVERRIDE" pos="0" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="cmd"/>
+
+ <array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8" variants="A6XX"/>
+ <array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX-"/>
+
+ <!-- always 0x0 -->
+ <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72" usage="cmd"/>
+
+ <reg32 offset="0xa000" name="VFD_CONTROL_0" usage="rp_blit">
+ <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>
+ <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/>
+ </reg32>
+ <reg32 offset="0xa001" name="VFD_CONTROL_1" usage="rp_blit">
+ <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
+ <!-- only used for VS in non-multi-position-output case -->
+ <bitfield name="REGID4VIEWID" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0xa002" name="VFD_CONTROL_2" usage="rp_blit">
+ <bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid">
+ <doc>
+ This is the ID of the current patch within the
+ subdraw, used to calculate the offset of the
+ patch within the HS->DS buffers. When a draw is
+ split into multiple subdraws then this differs
+ from gl_PrimitiveID on the second, third, etc.
+ subdraws.
+ </doc>
+ </bitfield>
+ <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0xa003" name="VFD_CONTROL_3" usage="rp_blit">
+ <bitfield name="REGID_DSPRIMID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="REGID_DSRELPATCHID" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0xa004" name="VFD_CONTROL_4" usage="rp_blit">
+ <bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0xa005" name="VFD_CONTROL_5" usage="rp_blit">
+ <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="UNK8" low="8" high="15" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0xa006" name="VFD_CONTROL_6" usage="rp_blit">
+ <!--
+ True if gl_PrimitiveID is read via the FS
+ -->
+ <bitfield name="PRIMID4PSEN" pos="0" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0xa007" name="VFD_MODE_CNTL" usage="cmd">
+ <bitfield name="RENDER_MODE" low="0" high="2" type="a6xx_render_mode"/>
+ </reg32>
+
+ <reg32 offset="0xa008" name="VFD_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" usage="rp_blit"/>
+ <reg32 offset="0xa009" name="VFD_ADD_OFFSET" usage="cmd">
+ <!-- add VFD_INDEX_OFFSET to REGID4VTX -->
+ <bitfield name="VERTEX" pos="0" type="boolean"/>
+ <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
+ <bitfield name="INSTANCE" pos="1" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET" usage="rp_blit"/>
+ <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET" usage="rp_blit"/>
+ <array offset="0xa010" name="VFD_FETCH" stride="4" length="32" usage="rp_blit">
+ <reg64 offset="0x0" name="BASE" type="address" align="1"/>
+ <reg32 offset="0x2" name="SIZE" type="uint"/>
+ <reg32 offset="0x3" name="STRIDE" low="0" high="11" type="uint"/>
+ </array>
+ <array offset="0xa090" name="VFD_DECODE" stride="2" length="32" usage="rp_blit">
+ <reg32 offset="0x0" name="INSTR">
+ <!-- IDX and byte OFFSET into VFD_FETCH -->
+ <bitfield name="IDX" low="0" high="4" type="uint"/>
+ <bitfield name="OFFSET" low="5" high="16"/>
+ <bitfield name="INSTANCED" pos="17" type="boolean"/>
+ <bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/>
+ <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
+ <bitfield name="UNK30" pos="30" type="boolean"/>
+ <bitfield name="FLOAT" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x1" name="STEP_RATE" type="uint"/>
+ </array>
+ <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32" usage="rp_blit">
+ <reg32 offset="0x0" name="INSTR">
+ <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
+ <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
+ </reg32>
+ </array>
+
+ <reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2" usage="rp_blit"/>
+
+ <reg32 offset="0xa600" name="VFD_UNKNOWN_A600" variants="A7XX-" usage="cmd"/>
+
+ <reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8" variants="A6XX"/>
+ <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16" variants="A7XX-"/>
+
+ <!--
+ Note: this seems to always be paired with another bit in another
+ block.
+ -->
+ <enum name="a6xx_threadsize">
+ <value value="0" name="THREAD64"/>
+ <value value="1" name="THREAD128"/>
+ </enum>
+
+ <bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
+ <!-- if set to SINGLE, only use 1 concurrent wave on each SP -->
+ <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
+ <!--
+ When b31 set we just see FULLREGFOOTPRINT set. The pattern of
+ used registers is a bit odd too:
+ - used (half): 0-15 68-179 (cnt=128, max=179)
+ - used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127>
+ whereas we usually see a (mostly) contiguous range of regs used. But if
+ I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)),
+ then:
+ - used (merged): 0-191 (cnt=192, max=191)
+ So I think if b31 is set, then the half precision registers overlap
+ the full precision registers. (Which seems like a pretty sensible
+ feature, actually I'm not sure when you *wouldn't* want to use that,
+ since it gives register allocation more flexibility)
+ -->
+ <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>
+ <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>
+ <!-- could it be a low bit of branchstack? -->
+ <bitfield name="UNK13" pos="13" type="boolean"/>
+ <!-- seems to be nesting level for flow control:.. -->
+ <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
+ </bitset>
+
+ <bitset name="a6xx_sp_xs_config" inline="yes">
+ <!--
+ Each of these are set if the given resource type is used
+ with the Vulkan/bindless binding model.
+ -->
+ <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/>
+ <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/>
+ <bitfield name="BINDLESS_IBO" pos="2" type="boolean"/>
+ <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/>
+
+ <bitfield name="ENABLED" pos="8" type="boolean"/>
+ <!--
+ number of textures and samplers.. these might be swapped, with GL I
+ always see the same value for both.
+ -->
+ <bitfield name="NTEX" low="9" high="16" type="uint"/>
+ <bitfield name="NSAMP" low="17" high="21" type="uint"/>
+ <bitfield name="NIBO" low="22" high="28" type="uint"/>
+ </bitset>
+
+ <bitset name="a6xx_sp_xs_prim_cntl" inline="yes">
+ <!-- # of VS outputs including pos/psize -->
+ <bitfield name="OUT" low="0" high="5" type="uint"/>
+ <!-- FLAGS_REGID only for GS -->
+ <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
+ </bitset>
+
+ <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
+ <!--
+ This field actually controls all geometry stages. TCS, TES, and
+ GS must have the same mergedregs setting as VS.
+ -->
+ <bitfield name="MERGEDREGS" pos="20" type="boolean"/>
+ <!--
+ Creates a separate preamble-only thread?
+
+ Early preamble has the following limitations:
+ - Only shared, a1, and consts regs could be used
+ (accessing other regs would result in GPU fault);
+ - No cat5/cat6, only stc/ldc variants are working;
+ - Values writen to shared regs are not accessible by the rest
+ of the shader;
+ - Instructions before shps are also considered to be a part of
+ early preamble;
+
+ Note, for all shaders from d3d11 games blob produced preambles
+ compatible with early preamble mode.
+ -->
+ <bitfield name="EARLYPREAMBLE" pos="21" type="boolean"/>
+ </reg32>
+ <!-- bitmask of true/false conditions for VS brac.N instructions,
+ bit N corresponds to brac.N -->
+ <reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex"/>
+ <!-- # of VS outputs including pos/psize -->
+ <reg32 offset="0xa802" name="SP_VS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/>
+ <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16" usage="rp_blit">
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
+ <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
+ </reg32>
+ </array>
+ <!--
+ Starting with a5xx, position/psize outputs from shader end up in the
+ SP_VS_OUT map, with highest OUTLOCn position. (Generally they are
+ the last entries too, except when gl_PointCoord is used, blob inserts
+ an extra varying after, but with a lower OUTLOC position. If present,
+ psize is last, preceded by position.
+ -->
+ <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8" usage="rp_blit">
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
+ <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
+ <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
+ <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
+ </reg32>
+ </array>
+
+ <bitset name="a6xx_sp_xs_pvt_mem_param" inline="yes">
+ <bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9">
+ <doc>The size of memory that ldp/stp can address.</doc>
+ </bitfield>
+ <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31">
+ <doc>
+ Seems to be the same as a3xx. The maximum stack
+ size in units of 4 calls, so a call depth of 7
+ would result in a value of 2.
+ TODO: What's the actual size per call, i.e. the
+ size of the PC? a3xx docs say it's 16 bits
+ there, but the length register now takes 28 bits
+ so it's probably been bumped to 32 bits.
+ </doc>
+ </bitfield>
+ </bitset>
+
+ <bitset name="a6xx_sp_xs_pvt_mem_size" inline="yes">
+ <bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/>
+ <bitfield name="PERWAVEMEMLAYOUT" pos="31" type="boolean">
+ <doc>
+ There are four indices used to compute the
+ private memory location for an access:
+
+ - stp/ldp offset
+ - fiber id
+ - wavefront id (a swizzled version of what "getwid" returns)
+ - SP ID (the same as what "getspid" returns)
+
+ The stride for the SP ID is always set by
+ TOTALPVTMEMSIZE. In the per-wave layout, the
+ indices are used in this order:
+
+ - offset % 4 (offset within dword)
+ - fiber id
+ - offset / 4
+ - wavefront id
+ - SP ID
+
+ and the stride for the wavefront ID is
+ MEMSIZEPERITEM, multiplied by 128 (fibers per
+ wavefront). In the per-fiber layout, the indices
+ are used in this order:
+
+ - offset
+ - fiber id % 4
+ - wavefront id
+ - fiber id / 4
+ - SP ID
+
+ and the stride for the fiber id/wavefront id
+ combo is MEMSIZEPERITEM.
+
+ Note: Accesses of more than 1 dword do not work
+ with per-fiber layout. The blob will fall back
+ to per-wave instead.
+ </doc>
+ </bitfield>
+ </bitset>
+
+ <bitset name="a6xx_sp_xs_pvt_mem_hw_stack_offset" inline="yes">
+ <doc>
+ This seems to be be the equivalent of HWSTACKOFFSET in
+ a3xx. The ldp/stp offset formula above isn't affected by
+ HWSTACKSIZEPERTHREAD at all, so the HW return address
+ stack seems to be after all the normal per-SP private
+ memory.
+ </doc>
+ <bitfield name="OFFSET" low="0" high="18" shr="11"/>
+ </bitset>
+
+ <reg32 offset="0xa81b" name="SP_VS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
+ <reg64 offset="0xa81c" name="SP_VS_OBJ_START" type="address" align="32" usage="rp_blit"/>
+ <reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
+ <reg64 offset="0xa81f" name="SP_VS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
+ <reg32 offset="0xa821" name="SP_VS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
+ <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
+ <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
+ <reg32 offset="0xa824" name="SP_VS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
+ <reg32 offset="0xa825" name="SP_VS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>
+ <reg32 offset="0xa82d" name="SP_VS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
+
+ <reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
+ <!-- There is no mergedregs bit, that comes from the VS. -->
+ <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/>
+ </reg32>
+ <!--
+ Total size of local storage in dwords divided by the wave size.
+ The maximum value is 64. With the wave size being always 64 for HS,
+ the maximum size of local storage should be:
+ 64 (wavesize) * 64 (SP_HS_WAVE_INPUT_SIZE) * 4 = 16k
+ -->
+ <reg32 offset="0xa831" name="SP_HS_WAVE_INPUT_SIZE" low="0" high="7" type="uint" usage="rp_blit"/>
+ <reg32 offset="0xa832" name="SP_HS_BRANCH_COND" type="hex" usage="rp_blit"/>
+
+ <!-- TODO: exact same layout as 0xa81b-0xa825 -->
+ <reg32 offset="0xa833" name="SP_HS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
+ <reg64 offset="0xa834" name="SP_HS_OBJ_START" type="address" align="32" usage="rp_blit"/>
+ <reg32 offset="0xa836" name="SP_HS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
+ <reg64 offset="0xa837" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
+ <reg32 offset="0xa839" name="SP_HS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
+ <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
+ <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
+ <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
+ <reg32 offset="0xa83d" name="SP_HS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>
+ <reg32 offset="0xa82f" name="SP_HS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
+
+ <reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
+ <!-- There is no mergedregs bit, that comes from the VS. -->
+ <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xa841" name="SP_DS_BRANCH_COND" type="hex"/>
+
+ <!-- TODO: exact same layout as 0xa802-0xa81a -->
+ <reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/>
+ <array offset="0xa843" name="SP_DS_OUT" stride="1" length="16" usage="rp_blit">
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
+ <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
+ </reg32>
+ </array>
+ <array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8" usage="rp_blit">
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
+ <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
+ <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
+ <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
+ </reg32>
+ </array>
+
+ <!-- TODO: exact same layout as 0xa81b-0xa825 -->
+ <reg32 offset="0xa85b" name="SP_DS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
+ <reg64 offset="0xa85c" name="SP_DS_OBJ_START" type="address" align="32" usage="rp_blit"/>
+ <reg32 offset="0xa85e" name="SP_DS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
+ <reg64 offset="0xa85f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
+ <reg32 offset="0xa861" name="SP_DS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
+ <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
+ <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
+ <reg32 offset="0xa864" name="SP_DS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
+ <reg32 offset="0xa865" name="SP_DS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>
+ <reg32 offset="0xa868" name="SP_DS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
+
+ <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
+ <!-- There is no mergedregs bit, that comes from the VS. -->
+ <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xa871" name="SP_GS_PRIM_SIZE" low="0" high="7" type="uint" usage="rp_blit">
+ <doc>
+ Normally the size of the output of the last stage in
+ dwords. It should be programmed as follows:
+
+ size less than 63 - size
+ size of 63 (?) or 64 - 63
+ size greater than 64 - 64
+
+ What to program when the size is 61-63 is a guess, but
+ both the blob and ir3 align the size to 4 dword's so it
+ doesn't matter in practice.
+ </doc>
+ </reg32>
+ <reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex" usage="rp_blit"/>
+
+ <!-- TODO: exact same layout as 0xa802-0xa81a -->
+ <reg32 offset="0xa873" name="SP_GS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/>
+ <array offset="0xa874" name="SP_GS_OUT" stride="1" length="16" usage="rp_blit">
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
+ <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
+ </reg32>
+ </array>
+
+ <array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8" usage="rp_blit">
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
+ <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
+ <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
+ <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
+ </reg32>
+ </array>
+
+ <!-- TODO: exact same layout as 0xa81b-0xa825 -->
+ <reg32 offset="0xa88c" name="SP_GS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
+ <reg64 offset="0xa88d" name="SP_GS_OBJ_START" type="address" align="32" usage="rp_blit"/>
+ <reg32 offset="0xa88f" name="SP_GS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
+ <reg64 offset="0xa890" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
+ <reg32 offset="0xa892" name="SP_GS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
+ <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
+ <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
+ <reg32 offset="0xa895" name="SP_GS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
+ <reg32 offset="0xa896" name="SP_GS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>
+ <reg32 offset="0xa899" name="SP_GS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
+
+ <reg64 offset="0xa8a0" name="SP_VS_TEX_SAMP" type="address" align="16" usage="cmd"/>
+ <reg64 offset="0xa8a2" name="SP_HS_TEX_SAMP" type="address" align="16" usage="cmd"/>
+ <reg64 offset="0xa8a4" name="SP_DS_TEX_SAMP" type="address" align="16" usage="cmd"/>
+ <reg64 offset="0xa8a6" name="SP_GS_TEX_SAMP" type="address" align="16" usage="cmd"/>
+ <reg64 offset="0xa8a8" name="SP_VS_TEX_CONST" type="address" align="64" usage="cmd"/>
+ <reg64 offset="0xa8aa" name="SP_HS_TEX_CONST" type="address" align="64" usage="cmd"/>
+ <reg64 offset="0xa8ac" name="SP_DS_TEX_CONST" type="address" align="64" usage="cmd"/>
+ <reg64 offset="0xa8ae" name="SP_GS_TEX_CONST" type="address" align="64" usage="cmd"/>
+
+ <!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 -->
+
+ <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
+ <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/>
+ <bitfield name="UNK21" pos="21" type="boolean"/>
+ <bitfield name="VARYING" pos="22" type="boolean"/>
+ <bitfield name="LODPIXMASK" pos="23" type="boolean">
+ <doc>
+ Enable ALL helper invocations in a quad. Necessary for
+ fine derivatives and quad subgroup ops.
+ </doc>
+ </bitfield>
+ <!-- note: vk blob uses bit24 -->
+ <bitfield name="UNK24" pos="24" type="boolean"/>
+ <bitfield name="UNK25" pos="25" type="boolean"/>
+ <bitfield name="PIXLODENABLE" pos="26" type="boolean">
+ <doc>
+ Enable helper invocations. Enables 3 out of 4 fragments,
+ because the coarse derivatives only use half of the quad
+ and so one pixel's value is always unused.
+ </doc>
+ </bitfield>
+ <bitfield name="UNK27" pos="27" type="boolean"/>
+ <bitfield name="EARLYPREAMBLE" pos="28" type="boolean"/>
+ <bitfield name="MERGEDREGS" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex"/>
+ <reg32 offset="0xa982" name="SP_FS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
+ <reg64 offset="0xa983" name="SP_FS_OBJ_START" type="address" align="32" usage="rp_blit"/>
+ <reg32 offset="0xa985" name="SP_FS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
+ <reg64 offset="0xa986" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
+ <reg32 offset="0xa988" name="SP_FS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
+
+ <reg32 offset="0xa989" name="SP_BLEND_CNTL" usage="rp_blit">
+ <!-- per-mrt enable bit -->
+ <bitfield name="ENABLE_BLEND" low="0" high="7"/>
+ <bitfield name="UNK8" pos="8" type="boolean"/>
+ <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
+ <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xa98a" name="SP_SRGB_CNTL" usage="rp_blit">
+ <!-- Same as RB_SRGB_CNTL -->
+ <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
+ <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
+ <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
+ <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
+ <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
+ <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
+ <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
+ <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS" usage="rp_blit">
+ <bitfield name="RT0" low="0" high="3"/>
+ <bitfield name="RT1" low="4" high="7"/>
+ <bitfield name="RT2" low="8" high="11"/>
+ <bitfield name="RT3" low="12" high="15"/>
+ <bitfield name="RT4" low="16" high="19"/>
+ <bitfield name="RT5" low="20" high="23"/>
+ <bitfield name="RT6" low="24" high="27"/>
+ <bitfield name="RT7" low="28" high="31"/>
+ </reg32>
+ <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0" usage="rp_blit">
+ <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1" usage="rp_blit">
+ <bitfield name="MRT" low="0" high="3" type="uint"/>
+ </reg32>
+
+ <array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8" usage="rp_blit">
+ <doc>per MRT</doc>
+ <reg32 offset="0x0" name="REG">
+ <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
+ </reg32>
+ </array>
+
+ <array offset="0xa996" name="SP_FS_MRT" stride="1" length="8" usage="rp_blit">
+ <reg32 offset="0" name="REG">
+ <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
+ <bitfield name="COLOR_SINT" pos="8" type="boolean"/>
+ <bitfield name="COLOR_UINT" pos="9" type="boolean"/>
+ <bitfield name="UNK10" pos="10" type="boolean"/>
+ </reg32>
+ </array>
+
+ <reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL" usage="rp_blit">
+ <bitfield name="COUNT" low="0" high="2" type="uint"/>
+ <bitfield name="IJ_WRITE_DISABLE" pos="3" type="boolean"/>
+ <doc>
+ Similar to "(eq)" flag but disables helper invocations
+ after the texture prefetch.
+ </doc>
+ <bitfield name="ENDOFQUAD" pos="4" type="boolean" />
+ <doc>
+ Bypass writing to regs and overwrite output with color from
+ CONSTSLOTID const regs.
+ </doc>
+ <bitfield name="WRITE_COLOR_TO_OUTPUT" pos="5" type="boolean"/>
+ <bitfield name="CONSTSLOTID" low="6" high="14" type="uint"/>
+ <!-- Blob never uses it -->
+ <bitfield name="CONSTSLOTID4COORD" low="16" high="24" type="uint" variants="A7XX-"/>
+ </reg32>
+ <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A6XX" usage="rp_blit">
+ <reg32 offset="0" name="CMD" variants="A6XX">
+ <bitfield name="SRC" low="0" high="6" type="uint"/>
+ <bitfield name="SAMP_ID" low="7" high="10" type="uint"/>
+ <bitfield name="TEX_ID" low="11" high="15" type="uint"/>
+ <bitfield name="DST" low="16" high="21" type="a3xx_regid"/>
+ <bitfield name="WRMASK" low="22" high="25" type="hex"/>
+ <bitfield name="HALF" pos="26" type="boolean"/>
+ <doc>Results in color being zero</doc>
+ <bitfield name="UNK27" pos="27" type="boolean"/>
+ <bitfield name="BINDLESS" pos="28" type="boolean"/>
+ <bitfield name="CMD" low="29" high="31" type="a6xx_tex_prefetch_cmd"/>
+ </reg32>
+ </array>
+ <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A7XX-" usage="rp_blit">
+ <reg32 offset="0" name="CMD" variants="A7XX-">
+ <bitfield name="SRC" low="0" high="6" type="uint"/>
+ <bitfield name="SAMP_ID" low="7" high="9" type="uint"/>
+ <bitfield name="TEX_ID" low="10" high="12" type="uint"/>
+ <bitfield name="DST" low="13" high="18" type="a3xx_regid"/>
+ <bitfield name="WRMASK" low="19" high="22" type="hex"/>
+ <bitfield name="HALF" pos="23" type="boolean"/>
+ <bitfield name="BINDLESS" pos="25" type="boolean"/>
+ <bitfield name="CMD" low="26" high="29" type="a6xx_tex_prefetch_cmd"/>
+ </reg32>
+ </array>
+ <array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4" usage="rp_blit">
+ <reg32 offset="0" name="CMD">
+ <bitfield name="SAMP_ID" low="0" high="15" type="uint"/>
+ <bitfield name="TEX_ID" low="16" high="31" type="uint"/>
+ </reg32>
+ </array>
+ <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
+ <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? -->
+ <reg32 offset="0xa9a9" name="SP_FS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/>
+
+ <!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS -->
+
+
+
+
+ <reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="cmd">
+ <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/>
+ <!-- seems to make SP use less concurrent threads when possible? -->
+ <bitfield name="UNK21" pos="21" type="boolean"/>
+ <!-- has a small impact on performance, not clear what it does -->
+ <bitfield name="UNK22" pos="22" type="boolean"/>
+ <bitfield name="EARLYPREAMBLE" pos="23" type="boolean"/>
+ <bitfield name="MERGEDREGS" pos="31" type="boolean"/>
+ </reg32>
+
+ <!-- set for compute shaders -->
+ <reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" usage="cmd">
+ <bitfield name="SHARED_SIZE" low="0" high="4" type="uint">
+ <doc>
+ If 0 - all 32k of shared storage is enabled, otherwise
+ (SHARED_SIZE + 1) * 1k is enabled.
+ The ldl/stl offset seems to be rewritten to 0 when it is beyond
+ this limit. This is different from ldlw/stlw, which wraps at
+ 64k (and has 36k of storage on A640 - reads between 36k-64k
+ always return 0)
+ </doc>
+ </bitfield>
+ <bitfield name="UNK5" pos="5" type="boolean"/>
+ <!-- always 1 ? -->
+ <bitfield name="UNK6" pos="6" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xa9b2" name="SP_CS_BRANCH_COND" type="hex" usage="cmd"/>
+ <reg32 offset="0xa9b3" name="SP_CS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="cmd"/>
+ <reg64 offset="0xa9b4" name="SP_CS_OBJ_START" type="address" align="32" usage="cmd"/>
+ <reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="cmd"/>
+ <reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_ADDR" align="32" usage="cmd"/>
+ <reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="cmd"/>
+ <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" low="0" high="7" type="uint" usage="cmd"/>
+ <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config" usage="cmd"/>
+ <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" low="0" high="27" type="uint" usage="cmd"/>
+ <reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="cmd"/>
+ <reg32 offset="0xa9be" name="SP_CS_UNKNOWN_A9BE" variants="A7XX-" usage="cmd"/>
+ <reg32 offset="0xa9c5" name="SP_CS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
+
+ <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_0 -->
+ <reg32 offset="0xa9c2" name="SP_CS_CNTL_0" usage="cmd">
+ <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_1 -->
+ <reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A6XX" usage="cmd">
+ <!-- gl_LocalInvocationIndex -->
+ <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
+ <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
+ one of those 6 "SP cores" -->
+ <bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/>
+ <!-- Must match SP_CS_CTRL -->
+ <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>
+ <!-- 1 thread per wave (ignored if bit9 set) -->
+ <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A7XX-" usage="cmd">
+ <!-- gl_LocalInvocationIndex -->
+ <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
+ <!-- Must match SP_CS_CTRL -->
+ <bitfield name="THREADSIZE" pos="8" type="a6xx_threadsize"/>
+ <!-- 1 thread per wave (would hang if THREAD128 is also set) -->
+ <bitfield name="THREADSIZE_SCALAR" pos="9" type="boolean"/>
+
+ <!-- Affects getone. If enabled, getone sometimes executed 1? less times
+ than there are subgroups.
+ -->
+ <bitfield name="UNK15" pos="15" type="boolean"/>
+ </reg32>
+
+ <!-- TODO: two 64kb aligned addresses at a9d0/a9d2 -->
+
+ <reg64 offset="0xa9e0" name="SP_FS_TEX_SAMP" type="address" align="16" usage="rp_blit"/>
+ <reg64 offset="0xa9e2" name="SP_CS_TEX_SAMP" type="address" align="16" usage="cmd"/>
+ <reg64 offset="0xa9e4" name="SP_FS_TEX_CONST" type="address" align="64" usage="rp_blit"/>
+ <reg64 offset="0xa9e6" name="SP_CS_TEX_CONST" type="address" align="64" usage="cmd"/>
+
+ <enum name="a6xx_bindless_descriptor_size">
+ <doc>
+ This can alternatively be interpreted as a pitch shift, ie, the
+ descriptor size is 2 &lt;&lt; N dwords
+ </doc>
+ <value value="1" name="BINDLESS_DESCRIPTOR_16B"/>
+ <value value="3" name="BINDLESS_DESCRIPTOR_64B"/>
+ </enum>
+
+ <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd">
+ <reg64 offset="0" name="DESCRIPTOR" variants="A6XX">
+ <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
+ <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
+ </reg64>
+ </array>
+ <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="cmd">
+ <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-">
+ <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
+ <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
+ </reg64>
+ </array>
+
+ <!--
+ IBO state for compute shader:
+ -->
+ <reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16"/>
+ <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" low="0" high="6" type="uint"/>
+
+ <!-- Correlated with avgs/uvgs usage in FS -->
+ <reg32 offset="0xaa01" name="SP_FS_VGPR_CONFIG" type="uint" variants="A7XX-" usage="cmd"/>
+
+ <reg32 offset="0xaa02" name="SP_PS_ALIASED_COMPONENTS_CONTROL" variants="A7XX-" usage="cmd">
+ <bitfield name="ENABLED" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0xaa03" name="SP_PS_ALIASED_COMPONENTS" variants="A7XX-" usage="cmd">
+ <doc>
+ Specify for which components the output color should be read
+ from alias, e.g. for:
+
+ alias.1.b32.0 r3.x, c8.x
+ alias.1.b32.0 r2.x, c4.x
+ alias.1.b32.0 r1.x, c4.x
+ alias.1.b32.0 r0.x, c0.x
+
+ the SP_PS_ALIASED_COMPONENTS would be 0x00001111
+ </doc>
+
+ <bitfield name="RT0" low="0" high="3"/>
+ <bitfield name="RT1" low="4" high="7"/>
+ <bitfield name="RT2" low="8" high="11"/>
+ <bitfield name="RT3" low="12" high="15"/>
+ <bitfield name="RT4" low="16" high="19"/>
+ <bitfield name="RT5" low="20" high="23"/>
+ <bitfield name="RT6" low="24" high="27"/>
+ <bitfield name="RT7" low="28" high="31"/>
+ </reg32>
+
+ <reg32 offset="0xaaf2" name="SP_UNKNOWN_AAF2" type="uint" usage="cmd"/>
+
+ <!--
+ This enum is probably similar in purpose to SNORMMODE on a3xx,
+ minus the snorm stuff, i.e. it controls what happens with an
+ out-of-bounds isam/isamm. GL and Vulkan robustness require us to
+ return 0 on out-of-bound textureFetch().
+ -->
+ <enum name="a6xx_isam_mode">
+ <value value="0x1" name="ISAMMODE_CL"/>
+ <value value="0x2" name="ISAMMODE_GL"/>
+ </enum>
+
+ <reg32 offset="0xab00" name="SP_MODE_CONTROL" usage="rp_blit">
+ <!--
+ When set, half register loads from the constant file will
+ load a 32-bit value (so hc0.y loads the same value as c0.y)
+ and implicitly convert it to 16b (f2f16, or u2u16, based on
+ operand type). When unset, half register loads from the
+ constant file will load 16 bits from the packed constant
+ file (so hc0.y loads the top 16 bits of the value of c0.x)
+ -->
+ <bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="ISAMMODE" low="1" high="2" type="a6xx_isam_mode"/>
+ <bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS -->
+ </reg32>
+
+ <reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/>
+ <reg32 offset="0xab02" name="SP_UNKNOWN_AB02" variants="A7XX-" usage="cmd"/>
+
+ <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
+ <reg32 offset="0xab05" name="SP_FS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
+
+ <array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit">
+ <reg64 offset="0" name="DESCRIPTOR" variants="A6XX">
+ <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
+ <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
+ </reg64>
+ </array>
+ <array offset="0xab0a" name="SP_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="rp_blit">
+ <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-">
+ <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
+ <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
+ </reg64>
+ </array>
+
+ <!--
+ Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
+ instructions VS/HS/DS/GS/FS. See SP_CS_IBO_* for compute shaders.
+ -->
+ <reg64 offset="0xab1a" name="SP_IBO" type="address" align="16" usage="cmd"/>
+ <reg32 offset="0xab20" name="SP_IBO_COUNT" low="0" high="6" type="uint" usage="cmd"/>
+
+ <reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX-" usage="cmd"/>
+
+ <bitset name="a6xx_sp_2d_dst_format" inline="yes">
+ <bitfield name="NORM" pos="0" type="boolean"/>
+ <bitfield name="SINT" pos="1" type="boolean"/>
+ <bitfield name="UINT" pos="2" type="boolean"/>
+ <!-- looks like HW only cares about the base type of this format,
+ which matches the ifmt? -->
+ <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/>
+ <!-- set when ifmt is R2D_UNORM8_SRGB -->
+ <bitfield name="SRGB" pos="11" type="boolean"/>
+ <!-- some sort of channel mask, not sure what it is for -->
+ <bitfield name="MASK" low="12" high="15"/>
+ </bitset>
+
+ <reg32 offset="0xacc0" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0xa9bf" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A7XX-" usage="rp_blit"/>
+
+ <reg32 offset="0xae00" name="SP_DBG_ECO_CNTL" usage="cmd"/>
+ <reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
+ <reg32 offset="0xae02" name="SP_NC_MODE_CNTL">
+ <!-- TODO: valid bits 0x3c3f, see kernel -->
+ </reg32>
+ <reg32 offset="0xae03" name="SP_CHICKEN_BITS" usage="cmd"/>
+ <reg32 offset="0xae04" name="SP_FLOAT_CNTL" usage="cmd">
+ <bitfield name="F16_NO_INF" pos="3" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0xae06" name="SP_UNKNOWN_AE06" variants="A7XX-" usage="cmd"/>
+ <reg32 offset="0xae08" name="SP_UNKNOWN_AE08" variants="A7XX-" usage="cmd"/>
+ <reg32 offset="0xae09" name="SP_UNKNOWN_AE09" variants="A7XX-" usage="cmd"/>
+ <reg32 offset="0xae0a" name="SP_UNKNOWN_AE0A" variants="A7XX-" usage="cmd"/>
+
+ <reg32 offset="0xae0f" name="SP_PERFCTR_ENABLE" usage="cmd">
+ <!-- some perfcntrs are affected by a per-stage enable bit
+ (PERF_SP_ALU_WORKING_CYCLES for example)
+ TODO: verify position of HS/DS/GS bits -->
+ <bitfield name="VS" pos="0" type="boolean"/>
+ <bitfield name="HS" pos="1" type="boolean"/>
+ <bitfield name="DS" pos="2" type="boolean"/>
+ <bitfield name="GS" pos="3" type="boolean"/>
+ <bitfield name="FS" pos="4" type="boolean"/>
+ <bitfield name="CS" pos="5" type="boolean"/>
+ </reg32>
+ <array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24"/>
+ <array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/>
+ <reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="cmd"/>
+ <reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="cmd"/>
+ <reg32 offset="0xae6c" name="SP_UNKNOWN_AE6C" variants="A7XX-" usage="cmd"/>
+ <reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-">
+ <bitfield name="LOCATION" low="18" high="19" type="a7xx_state_location"/>
+ <bitfield name="PIPE" low="16" high="17" type="a7xx_pipe"/>
+ <bitfield name="STATETYPE" low="8" high="15" type="a7xx_statetype_id"/>
+ <bitfield name="USPTP" low="4" high="7"/>
+ <bitfield name="SPTP" low="0" high="3"/>
+ </reg32>
+ <reg32 offset="0xae71" name="SP_DBG_CNTL" variants="A7XX-"/>
+ <reg32 offset="0xae73" name="SP_UNKNOWN_AE73" variants="A7XX-" usage="cmd"/>
+ <array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX-"/>
+ <!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) -->
+ <!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range -->
+ <reg32 offset="0xbe22" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
+
+ <!--
+ The downstream kernel calls the debug cluster of registers
+ "a6xx_sp_ps_tp_cluster" but this actually specifies the border
+ color base for compute shaders.
+ -->
+ <reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128" usage="cmd"/>
+ <reg32 offset="0xb182" name="SP_UNKNOWN_B182" low="0" high="2" usage="cmd"/>
+ <reg32 offset="0xb183" name="SP_UNKNOWN_B183" low="0" high="23" usage="cmd"/>
+
+ <reg32 offset="0xb190" name="SP_UNKNOWN_B190"/>
+ <reg32 offset="0xb191" name="SP_UNKNOWN_B191"/>
+
+ <!-- could be all the stuff below here is actually TPL1?? -->
+
+ <reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL" usage="rp_blit">
+ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
+ <bitfield name="UNK2" low="2" high="3"/>
+ </reg32>
+ <reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL" usage="rp_blit">
+ <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
+ <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
+ </reg32>
+
+ <!-- looks to work in the same way as a5xx: -->
+ <reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128" usage="cmd"/>
+ <reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/>
+ <reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/>
+ <reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/>
+ <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/>
+ <reg32 offset="0xb309" name="SP_TP_MODE_CNTL" usage="cmd">
+ <bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/>
+ <bitfield name="UNK3" low="2" high="7"/>
+ </reg32>
+ <reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/>
+
+ <!--
+ Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
+ badly named or the functionality moved in a6xx. But downstream kernel
+ calls this "a6xx_sp_ps_tp_2d_cluster"
+ -->
+ <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE" variants="A6XX" usage="rp_blit">
+ <bitfield name="WIDTH" low="0" high="14" type="uint"/>
+ <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
+ </reg32>
+ <reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH" variants="A6XX" usage="rp_blit">
+ <bitfield name="UNK0" low="0" high="8"/>
+ <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0xb2c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info" variants="A7XX-" usage="rp_blit"/>
+ <reg32 offset="0xb2c1" name="SP_PS_2D_SRC_SIZE" variants="A7XX">
+ <bitfield name="WIDTH" low="0" high="14" type="uint"/>
+ <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
+ </reg32>
+ <reg64 offset="0xb2c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A7XX-" usage="rp_blit"/>
+ <reg32 offset="0xb2c4" name="SP_PS_2D_SRC_PITCH" variants="A7XX">
+ <bitfield name="UNK0" low="0" high="8"/>
+ <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/>
+ </reg32>
+
+ <!-- planes for NV12, etc. (TODO: not tested) -->
+ <reg64 offset="0xb4c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A6XX"/>
+ <reg32 offset="0xb4c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="A6XX"/>
+ <reg64 offset="0xb4c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A6XX"/>
+
+ <reg64 offset="0xb2c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A7XX-"/>
+ <reg32 offset="0xb2c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="A7XX-"/>
+ <reg64 offset="0xb2c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A7XX-"/>
+
+ <reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A6XX" usage="rp_blit"/>
+
+ <reg64 offset="0xb2ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A7XX-" usage="rp_blit"/>
+ <reg32 offset="0xb2cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A7XX-" usage="rp_blit"/>
+
+ <reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A6XX"/>
+ <reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A6XX"/>
+ <reg32 offset="0xb4cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A6XX"/>
+ <reg32 offset="0xb4d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A6XX"/>
+ <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A6XX" usage="rp_blit"/>
+
+ <reg32 offset="0xb2cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A7XX"/>
+ <reg32 offset="0xb2ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A7XX"/>
+ <reg32 offset="0xb2cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A7XX"/>
+ <reg32 offset="0xb2d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A7XX"/>
+ <reg32 offset="0xb2d1" name="SP_PS_2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX"/>
+ <reg32 offset="0xb2d2" name="SP_PS_UNKNOWN_B2D2" variants="A7XX-" usage="rp_blit"/>
+ <reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-" usage="rp_blit"/>
+
+ <!-- always 0x100000 or 0x1000000? -->
+ <reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="cmd"/>
+ <reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0xb602" name="TPL1_DBG_ECO_CNTL1" usage="cmd"/>
+ <reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL">
+ <bitfield name="MODE" pos="0" type="boolean"/>
+ <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
+ <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
+ <bitfield name="UPPER_BIT" pos="4" type="uint"/>
+ <bitfield name="UNK6" low="6" high="7"/>
+ </reg32>
+ <reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="cmd"/> <!-- always 0x0 or 0x44 ? -->
+
+ <reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A6XX"/>
+ <reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A6XX"/>
+ <reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A6XX"/>
+ <reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A6XX"/>
+ <reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A6XX"/>
+
+ <reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A7XX" usage="cmd"/>
+ <reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A7XX" usage="cmd"/>
+ <reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A7XX" usage="cmd"/>
+ <reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A7XX" usage="cmd"/>
+ <reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A7XX" usage="cmd"/>
+
+ <array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12"/>
+
+ <!-- TODO: 4 more perfcntr sel at 0xb620 ? -->
+
+ <bitset name="a6xx_hlsq_xs_cntl" inline="yes">
+ <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
+ <bitfield name="ENABLED" pos="8" type="boolean"/>
+ <bitfield name="READ_IMM_SHARED_CONSTS" pos="9" type="boolean" variants="A7XX-"/>
+ </bitset>
+
+ <reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>
+
+ <reg32 offset="0xa827" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>
+ <reg32 offset="0xa83f" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>
+ <reg32 offset="0xa867" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>
+ <reg32 offset="0xa898" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>
+
+ <reg32 offset="0xa9aa" name="HLSQ_FS_UNKNOWN_A9AA" variants="A7XX-" usage="rp_blit">
+ <!-- Tentatively named, appears to disable consts being loaded via CP_LOAD_STATE6_FRAG -->
+ <bitfield name="CONSTS_LOAD_DISABLE" pos="0" type="boolean"/>
+ </reg32>
+
+ <!-- Always 0 -->
+ <reg32 offset="0xa9ac" name="HLSQ_UNKNOWN_A9AC" variants="A7XX-" usage="cmd"/>
+
+ <!-- Used in VK_KHR_fragment_shading_rate -->
+ <reg32 offset="0xa9ad" name="HLSQ_UNKNOWN_A9AD" variants="A7XX-" usage="cmd"/>
+
+ <reg32 offset="0xa9ae" name="HLSQ_UNKNOWN_A9AE" variants="A7XX-" usage="rp_blit">
+ <bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/>
+ <!-- UNK8 is set on a730/a740 -->
+ <bitfield name="UNK8" pos="8" type="boolean"/>
+ <!-- UNK9 is set on a750 -->
+ <bitfield name="UNK9" pos="9" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/>
+ <reg64 offset="0xb821" name="HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR" align="16" type="address"/>
+ <reg32 offset="0xb823" name="HLSQ_LOAD_STATE_GEOM_DATA"/>
+
+
+ <bitset name="a6xx_hlsq_fs_cntl_0" inline="yes">
+ <!-- must match SP_FS_CTRL -->
+ <bitfield name="THREADSIZE" pos="0" type="a6xx_threadsize"/>
+ <bitfield name="VARYINGS" pos="1" type="boolean"/>
+ <bitfield name="UNK2" low="2" high="11"/>
+ </bitset>
+ <bitset name="a6xx_hlsq_control_3_reg" inline="yes">
+ <!-- register loaded with position (bary.f) -->
+ <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
+ </bitset>
+ <bitset name="a6xx_hlsq_control_4_reg" inline="yes">
+ <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
+ </bitset>
+ <bitset name="a6xx_hlsq_control_5_reg" inline="yes">
+ <bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/>
+ </bitset>
+
+ <reg32 offset="0xb980" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean" variants="A6XX"/> <!-- never used by blob -->
+ <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A6XX" usage="rp_blit">
+ <!-- Sets the maximum number of primitives allowed in one FS wave minus one, similarly to the
+ A3xx field, except that it's not necessary to set it to anything but the maximum, since
+ the hardware will simply emit smaller waves when it runs out of space. -->
+ <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>
+ </reg32>
+ <reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG" variants="A6XX" usage="rp_blit">
+ <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
+ <!-- SAMPLEID is loaded into a half-precision register: -->
+ <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0xb984" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0xb985" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0xb986" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="cmd"/>
+ <reg32 offset="0xa9c6" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A7XX-" usage="rp_blit"/>
+ <reg32 offset="0xa9c7" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A7XX-" usage="rp_blit">
+ <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>
+ </reg32>
+ <reg32 offset="0xa9c8" name="HLSQ_CONTROL_2_REG" variants="A7XX-" usage="rp_blit">
+ <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
+ <!-- SAMPLEID is loaded into a half-precision register: -->
+ <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0xa9c9" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A7XX-" usage="rp_blit"/>
+ <reg32 offset="0xa9ca" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A7XX-" usage="rp_blit"/>
+ <reg32 offset="0xa9cb" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A7XX-" usage="rp_blit"/>
+ <reg32 offset="0xa9cd" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="cmd"/>
+
+ <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->
+ <reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0" variants="A6XX" usage="rp_blit">
+ <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
+ <!-- localsize is value minus one: -->
+ <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
+ <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
+ <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1" variants="A6XX" usage="rp_blit">
+ <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2" variants="A6XX" usage="rp_blit">
+ <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3" variants="A6XX" usage="rp_blit">
+ <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4" variants="A6XX" usage="rp_blit">
+ <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5" variants="A6XX" usage="rp_blit">
+ <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6" variants="A6XX" usage="rp_blit">
+ <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xb997" name="HLSQ_CS_CNTL_0" variants="A6XX" usage="rp_blit">
+ <!-- these are all vec3. first 3 need to be high regs
+ WGSIZECONSTID is the local size (from HLSQ_CS_NDRANGE_0)
+ WGOFFSETCONSTID is WGIDCONSTID*WGSIZECONSTID
+ -->
+ <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
+ <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/>
+ <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/>
+ <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
+ </reg32>
+ <reg32 offset="0xb998" name="HLSQ_CS_CNTL_1" variants="A6XX" usage="rp_blit">
+ <!-- gl_LocalInvocationIndex -->
+ <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
+ <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
+ one of those 6 "SP cores" -->
+ <bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/>
+ <!-- Must match SP_CS_CTRL -->
+ <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>
+ <!-- 1 thread per wave (ignored if bit9 set) -->
+ <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/>
+ </reg32>
+ <!--note: vulkan blob doesn't use these -->
+ <reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A6XX" usage="rp_blit"/>
+
+ <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->
+ <reg32 offset="0xa9d4" name="HLSQ_CS_NDRANGE_0" variants="A7XX-" usage="rp_blit">
+ <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
+ <!-- localsize is value minus one: -->
+ <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
+ <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
+ <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xa9d5" name="HLSQ_CS_NDRANGE_1" variants="A7XX-" usage="rp_blit">
+ <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xa9d6" name="HLSQ_CS_NDRANGE_2" variants="A7XX-" usage="rp_blit">
+ <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xa9d7" name="HLSQ_CS_NDRANGE_3" variants="A7XX-" usage="rp_blit">
+ <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xa9d8" name="HLSQ_CS_NDRANGE_4" variants="A7XX-" usage="rp_blit">
+ <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xa9d9" name="HLSQ_CS_NDRANGE_5" variants="A7XX-" usage="rp_blit">
+ <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0xa9da" name="HLSQ_CS_NDRANGE_6" variants="A7XX-" usage="rp_blit">
+ <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
+ </reg32>
+ <!--note: vulkan blob doesn't use these -->
+ <reg32 offset="0xa9dc" name="HLSQ_CS_KERNEL_GROUP_X" variants="A7XX-" usage="rp_blit"/>
+ <reg32 offset="0xa9dd" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A7XX-" usage="rp_blit"/>
+ <reg32 offset="0xa9de" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A7XX-" usage="rp_blit"/>
+
+ <enum name="a7xx_cs_yalign">
+ <value name="CS_YALIGN_1" value="8"/>
+ <value name="CS_YALIGN_2" value="4"/>
+ <value name="CS_YALIGN_4" value="2"/>
+ <value name="CS_YALIGN_8" value="1"/>
+ </enum>
+
+ <reg32 offset="0xa9db" name="HLSQ_CS_CNTL_1" variants="A7XX-" usage="rp_blit">
+ <!-- gl_LocalInvocationIndex -->
+ <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
+ <!-- Must match SP_CS_CTRL -->
+ <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/>
+ <bitfield name="UNK11" pos="11" type="boolean"/>
+ <bitfield name="UNK22" pos="22" type="boolean"/>
+ <bitfield name="UNK26" pos="26" type="boolean"/>
+ <bitfield name="YALIGN" low="27" high="30" type="a7xx_cs_yalign"/>
+ </reg32>
+
+ <reg32 offset="0xa9df" name="HLSQ_CS_LOCAL_SIZE" variants="A7XX-" usage="cmd">
+ <!-- localsize is value minus one: -->
+ <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
+ <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
+ <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0xb9a0" name="HLSQ_LOAD_STATE_FRAG_CMD"/>
+ <reg64 offset="0xb9a1" name="HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR" align="16" type="address"/>
+ <reg32 offset="0xb9a3" name="HLSQ_LOAD_STATE_FRAG_DATA"/>
+
+ <!-- mirror of SP_CS_BINDLESS_BASE -->
+ <array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit">
+ <reg64 offset="0" name="DESCRIPTOR">
+ <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
+ <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
+ </reg64>
+ </array>
+
+ <!-- new in a6xx gen4, mirror of SP_CS_UNKNOWN_A9B1? -->
+ <reg32 offset="0xb9d0" name="HLSQ_CS_UNKNOWN_B9D0" variants="A6XX" usage="cmd">
+ <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"/>
+ <bitfield name="UNK5" pos="5" type="boolean"/>
+ <!-- always 1 ? -->
+ <bitfield name="UNK6" pos="6" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0xbb00" name="HLSQ_DRAW_CMD">
+ <bitfield name="STATE_ID" low="0" high="7"/>
+ </reg32>
+
+ <reg32 offset="0xbb01" name="HLSQ_DISPATCH_CMD">
+ <bitfield name="STATE_ID" low="0" high="7"/>
+ </reg32>
+
+ <reg32 offset="0xbb02" name="HLSQ_EVENT_CMD">
+ <!-- I think only the low bit is actually used? -->
+ <bitfield name="STATE_ID" low="16" high="23"/>
+ <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
+ </reg32>
+
+ <reg32 offset="0xbb08" name="HLSQ_INVALIDATE_CMD" variants="A6XX" usage="cmd">
+ <doc>
+ This register clears pending loads queued up by
+ CP_LOAD_STATE6. Each bit resets a particular kind(s) of
+ CP_LOAD_STATE6.
+ </doc>
+
+ <!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
+ <bitfield name="VS_STATE" pos="0" type="boolean"/>
+ <bitfield name="HS_STATE" pos="1" type="boolean"/>
+ <bitfield name="DS_STATE" pos="2" type="boolean"/>
+ <bitfield name="GS_STATE" pos="3" type="boolean"/>
+ <bitfield name="FS_STATE" pos="4" type="boolean"/>
+ <bitfield name="CS_STATE" pos="5" type="boolean"/>
+
+ <bitfield name="CS_IBO" pos="6" type="boolean"/>
+ <bitfield name="GFX_IBO" pos="7" type="boolean"/>
+
+ <!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 -->
+ <bitfield name="CS_SHARED_CONST" pos="19" type="boolean"/>
+ <bitfield name="GFX_SHARED_CONST" pos="8" type="boolean"/>
+
+ <!-- SS6_BINDLESS: one bit per bindless base -->
+ <bitfield name="CS_BINDLESS" low="9" high="13" type="hex"/>
+ <bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/>
+ </reg32>
+
+ <reg32 offset="0xab1f" name="HLSQ_INVALIDATE_CMD" variants="A7XX-" usage="cmd">
+ <doc>
+ This register clears pending loads queued up by
+ CP_LOAD_STATE6. Each bit resets a particular kind(s) of
+ CP_LOAD_STATE6.
+ </doc>
+
+ <!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
+ <bitfield name="VS_STATE" pos="0" type="boolean"/>
+ <bitfield name="HS_STATE" pos="1" type="boolean"/>
+ <bitfield name="DS_STATE" pos="2" type="boolean"/>
+ <bitfield name="GS_STATE" pos="3" type="boolean"/>
+ <bitfield name="FS_STATE" pos="4" type="boolean"/>
+ <bitfield name="CS_STATE" pos="5" type="boolean"/>
+
+ <bitfield name="CS_IBO" pos="6" type="boolean"/>
+ <bitfield name="GFX_IBO" pos="7" type="boolean"/>
+
+ <!-- SS6_BINDLESS: one bit per bindless base -->
+ <bitfield name="CS_BINDLESS" low="9" high="16" type="hex"/>
+ <bitfield name="GFX_BINDLESS" low="17" high="24" type="hex"/>
+ </reg32>
+
+ <reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/>
+ <reg32 offset="0xab03" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/>
+
+ <array offset="0xab40" name="HLSQ_SHARED_CONSTS_IMM" stride="1" length="64" variants="A7XX-"/>
+
+ <reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS" variants="A6XX" usage="cmd">
+ <doc>
+ Shared constants are intended to be used for Vulkan push
+ constants. When enabled, 8 vec4's are reserved in the FS
+ const pool and 16 in the geometry const pool although
+ only 8 are actually used (why?) and they are mapped to
+ c504-c511 in each stage. Both VS and FS shared consts
+ are written using ST6_CONSTANTS/SB6_IBO, so that both
+ the geometry and FS shared consts can be written at once
+ by using CP_LOAD_STATE6 rather than
+ CP_LOAD_STATE6_FRAG/CP_LOAD_STATE6_GEOM. In addition
+ DST_OFF and NUM_UNIT are in units of dwords instead of
+ vec4's.
+
+ There is also a separate shared constant pool for CS,
+ which is loaded through CP_LOAD_STATE6_FRAG with
+ ST6_UBO/ST6_IBO. However the only real difference for CS
+ is the dword units.
+ </doc>
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ </reg32>
+
+ <!-- mirror of SP_BINDLESS_BASE -->
+ <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd">
+ <reg64 offset="0" name="DESCRIPTOR">
+ <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
+ <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
+ </reg64>
+ </array>
+
+ <reg32 offset="0xbd80" name="HLSQ_2D_EVENT_CMD">
+ <bitfield name="STATE_ID" low="8" high="15"/>
+ <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
+ </reg32>
+
+ <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00" variants="A6XX" usage="cmd"/> <!-- all bits valid except bit 29 -->
+ <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6" variants="A6XX" usage="cmd"/>
+ <reg32 offset="0xbe04" name="HLSQ_DBG_ECO_CNTL" variants="A6XX" usage="cmd"/>
+ <reg32 offset="0xbe05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0xbe08" name="HLSQ_UNKNOWN_BE08" low="0" high="15"/>
+ <array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/>
+
+ <!-- TODO: some valid registers between 0xbe20 and 0xbe33 -->
+ <reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
+
+ <reg32 offset="0xc000" name="SP_AHB_READ_APERTURE" variants="A7XX-"/>
+
+ <!-- Don't know if these are SP, always 0 -->
+ <reg64 offset="0x0ce2" name="SP_UNKNOWN_0CE2" variants="A7XX-" usage="cmd"/>
+ <reg64 offset="0x0ce4" name="SP_UNKNOWN_0CE4" variants="A7XX-" usage="cmd"/>
+ <reg64 offset="0x0ce6" name="SP_UNKNOWN_0CE6" variants="A7XX-" usage="cmd"/>
+
+ <!--
+ These special registers signal the beginning/end of an event
+ sequence. The sequence used internally for an event looks like:
+ - write EVENT_CMD pipe register
+ - write CP_EVENT_START
+ - write HLSQ_EVENT_CMD with event or HLSQ_DRAW_CMD
+ - write PC_EVENT_CMD with event or PC_DRAW_CMD
+ - write HLSQ_EVENT_CMD(CONTEXT_DONE)
+ - write PC_EVENT_CMD(CONTEXT_DONE)
+ - write CP_EVENT_END
+ Writing to CP_EVENT_END seems to actually trigger the context roll
+ -->
+ <reg32 offset="0xd600" name="CP_EVENT_START">
+ <bitfield name="STATE_ID" low="0" high="7"/>
+ </reg32>
+ <reg32 offset="0xd601" name="CP_EVENT_END">
+ <bitfield name="STATE_ID" low="0" high="7"/>
+ </reg32>
+ <reg32 offset="0xd700" name="CP_2D_EVENT_START">
+ <bitfield name="STATE_ID" low="0" high="7"/>
+ </reg32>
+ <reg32 offset="0xd701" name="CP_2D_EVENT_END">
+ <bitfield name="STATE_ID" low="0" high="7"/>
+ </reg32>
+</domain>
+
+<!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
+<domain name="A6XX_TEX_SAMP" width="32">
+ <doc>Texture sampler dwords</doc>
+ <enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
+ <value name="A6XX_TEX_NEAREST" value="0"/>
+ <value name="A6XX_TEX_LINEAR" value="1"/>
+ <value name="A6XX_TEX_ANISO" value="2"/>
+ <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
+ </enum>
+ <enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
+ <value name="A6XX_TEX_REPEAT" value="0"/>
+ <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>
+ <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>
+ <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>
+ <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>
+ </enum>
+ <enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
+ <value name="A6XX_TEX_ANISO_1" value="0"/>
+ <value name="A6XX_TEX_ANISO_2" value="1"/>
+ <value name="A6XX_TEX_ANISO_4" value="2"/>
+ <value name="A6XX_TEX_ANISO_8" value="3"/>
+ <value name="A6XX_TEX_ANISO_16" value="4"/>
+ </enum>
+ <enum name="a6xx_reduction_mode">
+ <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/>
+ <value name="A6XX_REDUCTION_MODE_MIN" value="1"/>
+ <value name="A6XX_REDUCTION_MODE_MAX" value="2"/>
+ </enum>
+
+ <reg32 offset="0" name="0">
+ <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
+ <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
+ <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
+ <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
+ <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
+ <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
+ <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
+ <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="CLAMPENABLE" pos="0" type="boolean">
+ <doc>
+ clamp result to [0, 1] if the format is unorm or
+ [-1, 1] if the format is snorm, *after*
+ filtering. Has no effect for other formats.
+ </doc>
+ </bitfield>
+ <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
+ <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
+ <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
+ <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
+ <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
+ <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/>
+ <bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/>
+ <bitfield name="BCOLOR" low="7" high="31"/>
+ </reg32>
+ <reg32 offset="3" name="3"/>
+</domain>
+
+<domain name="A6XX_TEX_CONST" width="32">
+ <doc>Texture constant dwords</doc>
+ <enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
+ <value name="A6XX_TEX_X" value="0"/>
+ <value name="A6XX_TEX_Y" value="1"/>
+ <value name="A6XX_TEX_Z" value="2"/>
+ <value name="A6XX_TEX_W" value="3"/>
+ <value name="A6XX_TEX_ZERO" value="4"/>
+ <value name="A6XX_TEX_ONE" value="5"/>
+ </enum>
+ <enum name="a6xx_tex_type"> <!-- same as a4xx? -->
+ <value name="A6XX_TEX_1D" value="0"/>
+ <value name="A6XX_TEX_2D" value="1"/>
+ <value name="A6XX_TEX_CUBE" value="2"/>
+ <value name="A6XX_TEX_3D" value="3"/>
+ <value name="A6XX_TEX_BUFFER" value="4"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
+ <bitfield name="SRGB" pos="2" type="boolean"/>
+ <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
+ <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
+ <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
+ <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
+ <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
+ <!-- overlaps with MIPLVLS -->
+ <bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/>
+ <bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/>
+ <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
+ <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
+ <!--
+ Why is the swap needed in addition to SWIZ_*? The swap
+ is performed before border color replacement, while the
+ swizzle is applied after after it.
+ -->
+ <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="WIDTH" low="0" high="14" type="uint"/>
+ <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <!--
+ These fields overlap PITCH, and are used instead of
+ PITCH/PITCHALIGN when TYPE is A6XX_TEX_BUFFER.
+ -->
+ <doc> probably for D3D structured UAVs, normally set to 1 </doc>
+ <bitfield name="STRUCTSIZETEXELS" low="4" high="15" type="uint"/>
+ <bitfield name="STARTOFFSETTEXELS" low="16" high="21" type="uint"/>
+
+ <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
+ <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
+ <doc>Pitch in bytes (so actually stride)</doc>
+ <bitfield name="PITCH" low="7" high="28" type="uint"/>
+ <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <!--
+ ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
+ for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
+ layer size at the point that it stops being reduced moving to
+ higher (smaller) mipmap levels
+ -->
+ <bitfield name="ARRAY_PITCH" low="0" high="22" shr="12" type="uint"/>
+ <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
+ <!--
+ by default levels with w < 16 are linear
+ TILE_ALL makes all levels have tiling
+ seems required when using UBWC, since all levels have UBWC (can possibly be disabled?)
+ -->
+ <bitfield name="TILE_ALL" pos="27" type="boolean"/>
+ <bitfield name="FLAG" pos="28" type="boolean"/>
+ </reg32>
+ <!-- for 2-3 plane format, BASE is flag buffer address (if enabled)
+ the address of the non-flag base buffer is determined automatically,
+ and must follow the flag buffer
+ -->
+ <reg32 offset="4" name="4">
+ <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
+ </reg32>
+ <reg32 offset="5" name="5">
+ <bitfield name="BASE_HI" low="0" high="16"/>
+ <bitfield name="DEPTH" low="17" high="29" type="uint"/>
+ </reg32>
+ <reg32 offset="6" name="6">
+ <!-- overlaps with PLANE_PITCH -->
+ <bitfield name="MIN_LOD_CLAMP" low="0" high="11" type="ufixed" radix="8"/>
+ <!-- pitch for plane 2 / plane 3 -->
+ <bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/>
+ </reg32>
+ <!-- 7/8 is plane 2 address for planar formats -->
+ <reg32 offset="7" name="7">
+ <bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
+ </reg32>
+ <reg32 offset="8" name="8">
+ <bitfield name="FLAG_HI" low="0" high="16"/>
+ </reg32>
+ <!-- 9/10 is plane 3 address for planar formats -->
+ <reg32 offset="9" name="9">
+ <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
+ </reg32>
+ <reg32 offset="10" name="10">
+ <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
+ <!-- log2 size of the first level, required for mipmapping -->
+ <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
+ <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
+ </reg32>
+ <reg32 offset="11" name="11"/>
+ <reg32 offset="12" name="12"/>
+ <reg32 offset="13" name="13"/>
+ <reg32 offset="14" name="14"/>
+ <reg32 offset="15" name="15"/>
+</domain>
+
+<domain name="A6XX_UBO" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="BASE_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="BASE_HI" low="0" high="16"/>
+ <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->
+ </reg32>
+</domain>
+
+<domain name="A6XX_PDC" width="32">
+ <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
+ <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
+ <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>
+ <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>
+ <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
+ <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>
+ <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>
+ <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>
+ <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>
+ <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>
+ <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
+ <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>
+ <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>
+ <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>
+ <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>
+ <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>
+ <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
+ <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>
+ <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>
+ <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>
+ <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>
+ <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>
+ <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
+ <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>
+ <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>
+ <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>
+</domain>
+
+<domain name="A6XX_PDC_GPU_SEQ" width="32">
+ <reg32 offset="0x0" name="MEM_0"/>
+</domain>
+
+<domain name="A6XX_CX_DBGC" width="32">
+ <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">
+ <bitfield high="7" low="0" name="PING_INDEX"/>
+ <bitfield high="15" low="8" name="PING_BLK_SEL"/>
+ </reg32>
+ <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>
+ <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>
+ <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>
+ <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">
+ <bitfield high="5" low="0" name="TRACEEN"/>
+ <bitfield high="14" low="12" name="GRANU"/>
+ <bitfield high="31" low="28" name="SEGT"/>
+ </reg32>
+ <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">
+ <bitfield high="27" low="24" name="ENABLE"/>
+ </reg32>
+ <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>
+ <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>
+ <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>
+ <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>
+ <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>
+ <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>
+ <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>
+ <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>
+ <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">
+ <bitfield high="3" low="0" name="BYTEL0"/>
+ <bitfield high="7" low="4" name="BYTEL1"/>
+ <bitfield high="11" low="8" name="BYTEL2"/>
+ <bitfield high="15" low="12" name="BYTEL3"/>
+ <bitfield high="19" low="16" name="BYTEL4"/>
+ <bitfield high="23" low="20" name="BYTEL5"/>
+ <bitfield high="27" low="24" name="BYTEL6"/>
+ <bitfield high="31" low="28" name="BYTEL7"/>
+ </reg32>
+ <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">
+ <bitfield high="3" low="0" name="BYTEL8"/>
+ <bitfield high="7" low="4" name="BYTEL9"/>
+ <bitfield high="11" low="8" name="BYTEL10"/>
+ <bitfield high="15" low="12" name="BYTEL11"/>
+ <bitfield high="19" low="16" name="BYTEL12"/>
+ <bitfield high="23" low="20" name="BYTEL13"/>
+ <bitfield high="27" low="24" name="BYTEL14"/>
+ <bitfield high="31" low="28" name="BYTEL15"/>
+ </reg32>
+
+ <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>
+ <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
+</domain>
+
+<domain name="A6XX_CX_MISC" width="32" prefix="variant" varset="chip">
+ <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
+ <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
+ <reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/>
+ <reg32 offset="0x0400" name="CX_MISC_SW_FUSE_VALUE" variants="A7XX-">
+ <bitfield pos="0" name="FASTBLEND" type="boolean"/>
+ <bitfield pos="1" name="LPAC" type="boolean"/>
+ <bitfield pos="2" name="RAYTRACING" type="boolean"/>
+ </reg32>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
new file mode 100644
index 000000000000..6531749d30f4
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml
@@ -0,0 +1,228 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+<import file="adreno/adreno_common.xml"/>
+
+<domain name="A6XX" width="32" prefix="variant" varset="chip">
+
+ <bitset name="A6XX_GMU_GPU_IDLE_STATUS">
+ <bitfield name="BUSY_IGN_AHB" pos="23"/>
+ <bitfield name="CX_GX_CPU_BUSY_IGN_AHB" pos="30"/>
+ </bitset>
+
+ <bitset name="A6XX_GMU_OOB">
+ <bitfield name="BOOT_SLUMBER_SET_MASK" pos="22"/>
+ <bitfield name="BOOT_SLUMBER_CHECK_MASK" pos="30"/>
+ <bitfield name="BOOT_SLUMBER_CLEAR_MASK" pos="30"/>
+ <bitfield name="DCVS_SET_MASK" pos="23"/>
+ <bitfield name="DCVS_CHECK_MASK" pos="31"/>
+ <bitfield name="DCVS_CLEAR_MASK" pos="31"/>
+ <bitfield name="GPU_SET_MASK" pos="18"/>
+ <bitfield name="GPU_CHECK_MASK" pos="26"/>
+ <bitfield name="GPU_CLEAR_MASK" pos="26"/>
+ <bitfield name="PERFCNTR_SET_MASK" pos="17"/>
+ <bitfield name="PERFCNTR_CHECK_MASK" pos="25"/>
+ <bitfield name="PERFCNTR_CLEAR_MASK" pos="25"/>
+ </bitset>
+
+ <bitset name="A6XX_HFI_IRQ">
+ <bitfield name="MSGQ_MASK" pos="0" />
+ <bitfield name="DSGQ_MASK" pos="1"/>
+ <bitfield name="BLOCKED_MSG_MASK" pos="2"/>
+ <bitfield name="CM3_FAULT_MASK" pos="23"/>
+ <bitfield name="GMU_ERR_MASK" low="16" high="22"/>
+ <bitfield name="OOB_MASK" low="24" high="31"/>
+ </bitset>
+
+ <bitset name="A6XX_HFI_H2F">
+ <bitfield name="IRQ_MASK_BIT" pos="0" />
+ </bitset>
+
+ <reg32 offset="0x80" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
+ <reg32 offset="0x81" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
+ <reg32 offset="0xc00" name="GMU_CM3_ITCM_START"/>
+ <reg32 offset="0x1c00" name="GMU_CM3_DTCM_START"/>
+ <reg32 offset="0x23f0" name="GMU_NMI_CONTROL_STATUS"/>
+ <reg32 offset="0x23f8" name="GMU_BOOT_SLUMBER_OPTION"/>
+ <reg32 offset="0x23f9" name="GMU_GX_VOTE_IDX"/>
+ <reg32 offset="0x23fa" name="GMU_MX_VOTE_IDX"/>
+ <reg32 offset="0x23fc" name="GMU_DCVS_ACK_OPTION"/>
+ <reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/>
+ <reg32 offset="0x23fe" name="GMU_DCVS_BW_SETTING"/>
+ <reg32 offset="0x23ff" name="GMU_DCVS_RETURN"/>
+ <reg32 offset="0x4c00" name="GMU_ICACHE_CONFIG"/>
+ <reg32 offset="0x4c01" name="GMU_DCACHE_CONFIG"/>
+ <reg32 offset="0x4c0f" name="GMU_SYS_BUS_CONFIG"/>
+ <reg32 offset="0x5000" name="GMU_CM3_SYSRESET"/>
+ <reg32 offset="0x5001" name="GMU_CM3_BOOT_CONFIG"/>
+ <reg32 offset="0x501a" name="GMU_CM3_FW_BUSY"/>
+ <reg32 offset="0x501c" name="GMU_CM3_FW_INIT_RESULT"/>
+ <reg32 offset="0x502d" name="GMU_CM3_CFG"/>
+ <reg32 offset="0x5040" name="GMU_CX_GMU_POWER_COUNTER_ENABLE"/>
+ <reg32 offset="0x5041" name="GMU_CX_GMU_POWER_COUNTER_SELECT_0"/>
+ <reg32 offset="0x5042" name="GMU_CX_GMU_POWER_COUNTER_SELECT_1"/>
+ <reg32 offset="0x5044" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L"/>
+ <reg32 offset="0x5045" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H"/>
+ <reg32 offset="0x5046" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L"/>
+ <reg32 offset="0x5047" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H"/>
+ <reg32 offset="0x5048" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L"/>
+ <reg32 offset="0x5049" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H"/>
+ <reg32 offset="0x504a" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L"/>
+ <reg32 offset="0x504b" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H"/>
+ <reg32 offset="0x504c" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L"/>
+ <reg32 offset="0x504d" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H"/>
+ <reg32 offset="0x504e" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L"/>
+ <reg32 offset="0x504f" name="GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H"/>
+ <reg32 offset="0x50c0" name="GMU_PWR_COL_INTER_FRAME_CTRL">
+ <bitfield name="IFPC_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="HM_POWER_COLLAPSE_ENABLE" pos="1" type="boolean"/>
+ <bitfield name="SPTPRAC_POWER_CONTROL_ENABLE" pos="2" type="boolean"/>
+ <bitfield name="NUM_PASS_SKIPS" low="10" high="13"/>
+ <bitfield name="MIN_PASS_LENGTH" low="14" high="31"/>
+ </reg32>
+ <reg32 offset="0x50c1" name="GMU_PWR_COL_INTER_FRAME_HYST"/>
+ <reg32 offset="0x50c2" name="GMU_PWR_COL_SPTPRAC_HYST"/>
+ <reg32 offset="0x50d0" name="GMU_SPTPRAC_PWR_CLK_STATUS">
+ <bitfield name="SPTPRAC_GDSC_POWERING_OFF" pos="0" type="boolean"/>
+ <bitfield name="SPTPRAC_GDSC_POWERING_ON" pos="1" type="boolean"/>
+ <bitfield name="SPTPRAC_GDSC_POWER_OFF" pos="2" type="boolean"/>
+ <bitfield name="SPTPRAC_GDSC_POWER_ON" pos="3" type="boolean"/>
+ <bitfield name="SP_CLOCK_OFF" pos="4" type="boolean"/>
+ <bitfield name="GMU_UP_POWER_STATE" pos="5" type="boolean"/>
+ <bitfield name="GX_HM_GDSC_POWER_OFF" pos="6" type="boolean"/>
+ <bitfield name="GX_HM_CLK_OFF" pos="7" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x50e4" name="GMU_GPU_NAP_CTRL">
+ <bitfield name="HW_NAP_ENABLE" pos="0"/>
+ <bitfield name="SID" low="4" high="8"/>
+ </reg32>
+ <reg32 offset="0x50e8" name="GMU_RPMH_CTRL">
+ <bitfield name="RPMH_INTERFACE_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="LLC_VOTE_ENABLE" pos="4" type="boolean"/>
+ <bitfield name="DDR_VOTE_ENABLE" pos="8" type="boolean"/>
+ <bitfield name="MX_VOTE_ENABLE" pos="9" type="boolean"/>
+ <bitfield name="CX_VOTE_ENABLE" pos="10" type="boolean"/>
+ <bitfield name="GFX_VOTE_ENABLE" pos="11" type="boolean"/>
+ <bitfield name="DDR_MIN_VOTE_ENABLE" pos="12" type="boolean"/>
+ <bitfield name="MX_MIN_VOTE_ENABLE" pos="13" type="boolean"/>
+ <bitfield name="CX_MIN_VOTE_ENABLE" pos="14" type="boolean"/>
+ <bitfield name="GFX_MIN_VOTE_ENABLE" pos="15" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x50e9" name="GMU_RPMH_HYST_CTRL"/>
+ <reg32 offset="0x50ec" name="GPU_GMU_CX_GMU_RPMH_POWER_STATE"/>
+ <reg32 offset="0x50f0" name="GPU_GMU_CX_GMU_CX_FAL_INTF"/>
+ <reg32 offset="0x50f1" name="GPU_GMU_CX_GMU_CX_FALNEXT_INTF"/>
+ <reg32 offset="0x5100" name="GPU_GMU_CX_GMU_PWR_COL_CP_MSG"/>
+ <reg32 offset="0x5101" name="GPU_GMU_CX_GMU_PWR_COL_CP_RESP"/>
+ <reg32 offset="0x51f0" name="GMU_BOOT_KMD_LM_HANDSHAKE"/>
+ <reg32 offset="0x5157" name="GMU_LLM_GLM_SLEEP_CTRL"/>
+ <reg32 offset="0x5158" name="GMU_LLM_GLM_SLEEP_STATUS"/>
+ <reg32 offset="0x5088" name="GMU_ALWAYS_ON_COUNTER_L"/>
+ <reg32 offset="0x5089" name="GMU_ALWAYS_ON_COUNTER_H"/>
+ <reg32 offset="0x50c3" name="GMU_GMU_PWR_COL_KEEPALIVE"/>
+ <reg32 offset="0x5180" name="GMU_HFI_CTRL_STATUS"/>
+ <reg32 offset="0x5181" name="GMU_HFI_VERSION_INFO"/>
+ <reg32 offset="0x5182" name="GMU_HFI_SFR_ADDR"/>
+ <reg32 offset="0x5183" name="GMU_HFI_MMAP_ADDR"/>
+ <reg32 offset="0x5184" name="GMU_HFI_QTBL_INFO"/>
+ <reg32 offset="0x5185" name="GMU_HFI_QTBL_ADDR"/>
+ <reg32 offset="0x5186" name="GMU_HFI_CTRL_INIT"/>
+ <reg32 offset="0x5190" name="GMU_GMU2HOST_INTR_SET"/>
+ <reg32 offset="0x5191" name="GMU_GMU2HOST_INTR_CLR"/>
+ <reg32 offset="0x5192" name="GMU_GMU2HOST_INTR_INFO">
+ <bitfield name="MSGQ" pos="0" type="boolean"/>
+ <bitfield name="CM3_FAULT" pos="23" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x5193" name="GMU_GMU2HOST_INTR_MASK"/>
+ <reg32 offset="0x5194" name="GMU_HOST2GMU_INTR_SET"/>
+ <reg32 offset="0x5195" name="GMU_HOST2GMU_INTR_CLR"/>
+ <reg32 offset="0x5196" name="GMU_HOST2GMU_INTR_RAW_INFO"/>
+ <reg32 offset="0x5197" name="GMU_HOST2GMU_INTR_EN_0"/>
+ <reg32 offset="0x5198" name="GMU_HOST2GMU_INTR_EN_1"/>
+ <reg32 offset="0x5199" name="GMU_HOST2GMU_INTR_EN_2"/>
+ <reg32 offset="0x519a" name="GMU_HOST2GMU_INTR_EN_3"/>
+ <reg32 offset="0x519b" name="GMU_HOST2GMU_INTR_INFO_0"/>
+ <reg32 offset="0x519c" name="GMU_HOST2GMU_INTR_INFO_1"/>
+ <reg32 offset="0x519d" name="GMU_HOST2GMU_INTR_INFO_2"/>
+ <reg32 offset="0x519e" name="GMU_HOST2GMU_INTR_INFO_3"/>
+ <reg32 offset="0x51c5" name="GMU_GENERAL_0"/>
+ <reg32 offset="0x51c6" name="GMU_GENERAL_1"/>
+ <reg32 offset="0x51cb" name="GMU_GENERAL_6"/>
+ <reg32 offset="0x51cc" name="GMU_GENERAL_7"/>
+ <reg32 offset="0x51cd" name="GMU_GENERAL_8" variants="A7XX"/>
+ <reg32 offset="0x51ce" name="GMU_GENERAL_9" variants="A7XX"/>
+ <reg32 offset="0x51cf" name="GMU_GENERAL_10" variants="A7XX"/>
+ <reg32 offset="0x515d" name="GMU_ISENSE_CTRL"/>
+ <reg32 offset="0x8920" name="GPU_CS_ENABLE_REG"/>
+ <reg32 offset="0x515d" name="GPU_GMU_CX_GMU_ISENSE_CTRL"/>
+ <reg32 offset="0x8578" name="GPU_CS_AMP_CALIBRATION_CONTROL3"/>
+ <reg32 offset="0x8558" name="GPU_CS_AMP_CALIBRATION_CONTROL2"/>
+ <reg32 offset="0x8580" name="GPU_CS_A_SENSOR_CTRL_0"/>
+ <reg32 offset="0x27ada" name="GPU_CS_A_SENSOR_CTRL_2"/>
+ <reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
+ <reg32 offset="0x8957" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/>
+ <reg32 offset="0x881a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
+ <reg32 offset="0x881d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/>
+ <reg32 offset="0x881f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/>
+ <reg32 offset="0x8821" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/>
+ <reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/>
+ <reg32 offset="0x896d" name="GPU_CS_AMP_PERIOD_CTRL"/>
+ <reg32 offset="0x8965" name="GPU_CS_AMP_CALIBRATION_DONE"/>
+ <reg32 offset="0x514d" name="GPU_GMU_CX_GMU_PWR_THRESHOLD"/>
+ <reg32 offset="0x9303" name="GMU_AO_INTERRUPT_EN"/>
+ <reg32 offset="0x9304" name="GMU_AO_HOST_INTERRUPT_CLR"/>
+ <reg32 offset="0x9305" name="GMU_AO_HOST_INTERRUPT_STATUS">
+ <bitfield name="WDOG_BITE" pos="0" type="boolean"/>
+ <bitfield name="RSCC_COMP" pos="1" type="boolean"/>
+ <bitfield name="VDROOP" pos="2" type="boolean"/>
+ <bitfield name="FENCE_ERR" pos="3" type="boolean"/>
+ <bitfield name="DBD_WAKEUP" pos="4" type="boolean"/>
+ <bitfield name="HOST_AHB_BUS_ERROR" pos="5" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x9306" name="GMU_AO_HOST_INTERRUPT_MASK"/>
+ <reg32 offset="0x9309" name="GPU_GMU_AO_GMU_CGC_MODE_CNTL"/>
+ <reg32 offset="0x930a" name="GPU_GMU_AO_GMU_CGC_DELAY_CNTL"/>
+ <reg32 offset="0x930b" name="GPU_GMU_AO_GMU_CGC_HYST_CNTL"/>
+ <reg32 offset="0x930c" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS">
+ <bitfield name = "GPUBUSYIGNAHB" pos="23" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x930d" name="GPU_GMU_AO_GPU_CX_BUSY_STATUS2"/>
+ <reg32 offset="0x930e" name="GPU_GMU_AO_GPU_CX_BUSY_MASK"/>
+ <reg32 offset="0x9310" name="GMU_AO_AHB_FENCE_CTRL"/>
+ <reg32 offset="0x9313" name="GMU_AHB_FENCE_STATUS"/>
+ <reg32 offset="0x9314" name="GMU_AHB_FENCE_STATUS_CLR"/>
+ <reg32 offset="0x9315" name="GMU_RBBM_INT_UNMASKED_STATUS"/>
+ <reg32 offset="0x9316" name="GMU_AO_SPARE_CNTL"/>
+ <reg32 offset="0x9307" name="GMU_RSCC_CONTROL_REQ"/>
+ <reg32 offset="0x9308" name="GMU_RSCC_CONTROL_ACK"/>
+ <reg32 offset="0x9311" name="GMU_AHB_FENCE_RANGE_0"/>
+ <reg32 offset="0x9312" name="GMU_AHB_FENCE_RANGE_1"/>
+ <reg32 offset="0x9c03" name="GPU_CC_GX_GDSCR"/>
+ <reg32 offset="0x9d42" name="GPU_CC_GX_DOMAIN_MISC"/>
+ <reg32 offset="0xc001" name="GPU_CPR_FSM_CTL"/>
+
+ <!-- starts at offset 0x8c00 on most gpus -->
+ <reg32 offset="0x0004" name="GPU_RSCC_RSC_STATUS0_DRV0"/>
+ <reg32 offset="0x0008" name="RSCC_PDC_SEQ_START_ADDR"/>
+ <reg32 offset="0x0009" name="RSCC_PDC_MATCH_VALUE_LO"/>
+ <reg32 offset="0x000a" name="RSCC_PDC_MATCH_VALUE_HI"/>
+ <reg32 offset="0x000b" name="RSCC_PDC_SLAVE_ID_DRV0"/>
+ <reg32 offset="0x000d" name="RSCC_HIDDEN_TCS_CMD0_ADDR"/>
+ <reg32 offset="0x000e" name="RSCC_HIDDEN_TCS_CMD0_DATA"/>
+ <reg32 offset="0x0082" name="RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0"/>
+ <reg32 offset="0x0083" name="RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0"/>
+ <reg32 offset="0x0089" name="RSCC_TIMESTAMP_UNIT1_EN_DRV0"/>
+ <reg32 offset="0x008c" name="RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0"/>
+ <reg32 offset="0x0100" name="RSCC_OVERRIDE_START_ADDR"/>
+ <reg32 offset="0x0101" name="RSCC_SEQ_BUSY_DRV0"/>
+ <reg32 offset="0x0154" name="RSCC_SEQ_MEM_0_DRV0_A740" variants="A7XX"/>
+ <reg32 offset="0x0180" name="RSCC_SEQ_MEM_0_DRV0"/>
+ <reg32 offset="0x0346" name="RSCC_TCS0_DRV0_STATUS"/>
+ <reg32 offset="0x03ee" name="RSCC_TCS1_DRV0_STATUS"/>
+ <reg32 offset="0x0496" name="RSCC_TCS2_DRV0_STATUS"/>
+ <reg32 offset="0x053e" name="RSCC_TCS3_DRV0_STATUS"/>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml b/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml
new file mode 100644
index 000000000000..218ec8bb966e
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml
@@ -0,0 +1,400 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+
+<enum name="chip" bare="yes">
+ <value name="A2XX" value="2"/>
+ <value name="A3XX" value="3"/>
+ <value name="A4XX" value="4"/>
+ <value name="A5XX" value="5"/>
+ <value name="A6XX" value="6"/>
+ <value name="A7XX" value="7"/>
+</enum>
+
+<enum name="adreno_pa_su_sc_draw">
+ <value name="PC_DRAW_POINTS" value="0"/>
+ <value name="PC_DRAW_LINES" value="1"/>
+ <value name="PC_DRAW_TRIANGLES" value="2"/>
+</enum>
+
+<enum name="adreno_compare_func">
+ <value name="FUNC_NEVER" value="0"/>
+ <value name="FUNC_LESS" value="1"/>
+ <value name="FUNC_EQUAL" value="2"/>
+ <value name="FUNC_LEQUAL" value="3"/>
+ <value name="FUNC_GREATER" value="4"/>
+ <value name="FUNC_NOTEQUAL" value="5"/>
+ <value name="FUNC_GEQUAL" value="6"/>
+ <value name="FUNC_ALWAYS" value="7"/>
+</enum>
+
+<enum name="adreno_stencil_op">
+ <value name="STENCIL_KEEP" value="0"/>
+ <value name="STENCIL_ZERO" value="1"/>
+ <value name="STENCIL_REPLACE" value="2"/>
+ <value name="STENCIL_INCR_CLAMP" value="3"/>
+ <value name="STENCIL_DECR_CLAMP" value="4"/>
+ <value name="STENCIL_INVERT" value="5"/>
+ <value name="STENCIL_INCR_WRAP" value="6"/>
+ <value name="STENCIL_DECR_WRAP" value="7"/>
+</enum>
+
+<enum name="adreno_rb_blend_factor">
+ <value name="FACTOR_ZERO" value="0"/>
+ <value name="FACTOR_ONE" value="1"/>
+ <value name="FACTOR_SRC_COLOR" value="4"/>
+ <value name="FACTOR_ONE_MINUS_SRC_COLOR" value="5"/>
+ <value name="FACTOR_SRC_ALPHA" value="6"/>
+ <value name="FACTOR_ONE_MINUS_SRC_ALPHA" value="7"/>
+ <value name="FACTOR_DST_COLOR" value="8"/>
+ <value name="FACTOR_ONE_MINUS_DST_COLOR" value="9"/>
+ <value name="FACTOR_DST_ALPHA" value="10"/>
+ <value name="FACTOR_ONE_MINUS_DST_ALPHA" value="11"/>
+ <value name="FACTOR_CONSTANT_COLOR" value="12"/>
+ <value name="FACTOR_ONE_MINUS_CONSTANT_COLOR" value="13"/>
+ <value name="FACTOR_CONSTANT_ALPHA" value="14"/>
+ <value name="FACTOR_ONE_MINUS_CONSTANT_ALPHA" value="15"/>
+ <value name="FACTOR_SRC_ALPHA_SATURATE" value="16"/>
+ <value name="FACTOR_SRC1_COLOR" value="20"/>
+ <value name="FACTOR_ONE_MINUS_SRC1_COLOR" value="21"/>
+ <value name="FACTOR_SRC1_ALPHA" value="22"/>
+ <value name="FACTOR_ONE_MINUS_SRC1_ALPHA" value="23"/>
+</enum>
+
+<bitset name="adreno_rb_stencilrefmask" inline="yes">
+ <bitfield name="STENCILREF" low="0" high="7" type="hex"/>
+ <bitfield name="STENCILMASK" low="8" high="15" type="hex"/>
+ <bitfield name="STENCILWRITEMASK" low="16" high="23" type="hex"/>
+</bitset>
+
+<enum name="adreno_rb_surface_endian">
+ <value name="ENDIAN_NONE" value="0"/>
+ <value name="ENDIAN_8IN16" value="1"/>
+ <value name="ENDIAN_8IN32" value="2"/>
+ <value name="ENDIAN_16IN32" value="3"/>
+ <value name="ENDIAN_8IN64" value="4"/>
+ <value name="ENDIAN_8IN128" value="5"/>
+</enum>
+
+<enum name="adreno_rb_dither_mode">
+ <value name="DITHER_DISABLE" value="0"/>
+ <value name="DITHER_ALWAYS" value="1"/>
+ <value name="DITHER_IF_ALPHA_OFF" value="2"/>
+</enum>
+
+<enum name="adreno_rb_depth_format">
+ <value name="DEPTHX_16" value="0"/>
+ <value name="DEPTHX_24_8" value="1"/>
+ <value name="DEPTHX_32" value="2"/>
+</enum>
+
+<enum name="adreno_rb_copy_control_mode">
+ <value name="RB_COPY_RESOLVE" value="1"/>
+ <value name="RB_COPY_CLEAR" value="2"/>
+ <value name="RB_COPY_DEPTH_STENCIL" value="5"/> <!-- not sure if this is part of MODE or another bitfield?? -->
+</enum>
+
+<bitset name="adreno_reg_xy" inline="yes">
+ <bitfield name="WINDOW_OFFSET_DISABLE" pos="31" type="boolean"/>
+ <bitfield name="X" low="0" high="14" type="uint"/>
+ <bitfield name="Y" low="16" high="30" type="uint"/>
+</bitset>
+
+<bitset name="adreno_cp_protect" inline="yes">
+ <bitfield name="BASE_ADDR" low="0" high="16"/>
+ <bitfield name="MASK_LEN" low="24" high="28"/>
+ <bitfield name="TRAP_WRITE" pos="29"/>
+ <bitfield name="TRAP_READ" pos="30"/>
+</bitset>
+
+<domain name="AXXX" width="32">
+ <brief>Registers in common between a2xx and a3xx</brief>
+
+ <reg32 offset="0x01c0" name="CP_RB_BASE"/>
+ <reg32 offset="0x01c1" name="CP_RB_CNTL">
+ <bitfield name="BUFSZ" low="0" high="5"/>
+ <bitfield name="BLKSZ" low="8" high="13"/>
+ <bitfield name="BUF_SWAP" low="16" high="17"/>
+ <bitfield name="POLL_EN" pos="20" type="boolean"/>
+ <bitfield name="NO_UPDATE" pos="27" type="boolean"/>
+ <bitfield name="RPTR_WR_EN" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x01c3" name="CP_RB_RPTR_ADDR">
+ <bitfield name="SWAP" low="0" high="1" type="uint"/>
+ <bitfield name="ADDR" low="2" high="31" shr="2"/>
+ </reg32>
+ <reg32 offset="0x01c4" name="CP_RB_RPTR" type="uint"/>
+ <reg32 offset="0x01c5" name="CP_RB_WPTR" type="uint"/>
+ <reg32 offset="0x01c6" name="CP_RB_WPTR_DELAY"/>
+ <reg32 offset="0x01c7" name="CP_RB_RPTR_WR"/>
+ <reg32 offset="0x01c8" name="CP_RB_WPTR_BASE"/>
+ <reg32 offset="0x01d5" name="CP_QUEUE_THRESHOLDS">
+ <bitfield name="CSQ_IB1_START" low="0" high="3" type="uint"/>
+ <bitfield name="CSQ_IB2_START" low="8" high="11" type="uint"/>
+ <bitfield name="CSQ_ST_START" low="16" high="19" type="uint"/>
+ </reg32>
+ <reg32 offset="0x01d6" name="CP_MEQ_THRESHOLDS">
+ <bitfield name="MEQ_END" low="16" high="20" type="uint"/>
+ <bitfield name="ROQ_END" low="24" high="28" type="uint"/>
+ </reg32>
+ <reg32 offset="0x01d7" name="CP_CSQ_AVAIL">
+ <bitfield name="RING" low="0" high="6" type="uint"/>
+ <bitfield name="IB1" low="8" high="14" type="uint"/>
+ <bitfield name="IB2" low="16" high="22" type="uint"/>
+ </reg32>
+ <reg32 offset="0x01d8" name="CP_STQ_AVAIL">
+ <bitfield name="ST" low="0" high="6" type="uint"/>
+ </reg32>
+ <reg32 offset="0x01d9" name="CP_MEQ_AVAIL">
+ <bitfield name="MEQ" low="0" high="4" type="uint"/>
+ </reg32>
+ <reg32 offset="0x01dc" name="SCRATCH_UMSK">
+ <bitfield name="UMSK" low="0" high="7" type="uint"/>
+ <bitfield name="SWAP" low="16" high="17" type="uint"/>
+ </reg32>
+ <reg32 offset="0x01dd" name="SCRATCH_ADDR"/>
+ <reg32 offset="0x01ea" name="CP_ME_RDADDR"/>
+
+ <reg32 offset="0x01ec" name="CP_STATE_DEBUG_INDEX"/>
+ <reg32 offset="0x01ed" name="CP_STATE_DEBUG_DATA"/>
+ <reg32 offset="0x01f2" name="CP_INT_CNTL">
+ <bitfield name="SW_INT_MASK" pos="19" type="boolean"/>
+ <bitfield name="T0_PACKET_IN_IB_MASK" pos="23" type="boolean"/>
+ <bitfield name="OPCODE_ERROR_MASK" pos="24" type="boolean"/>
+ <bitfield name="PROTECTED_MODE_ERROR_MASK" pos="25" type="boolean"/>
+ <bitfield name="RESERVED_BIT_ERROR_MASK" pos="26" type="boolean"/>
+ <bitfield name="IB_ERROR_MASK" pos="27" type="boolean"/>
+ <bitfield name="IB2_INT_MASK" pos="29" type="boolean"/>
+ <bitfield name="IB1_INT_MASK" pos="30" type="boolean"/>
+ <bitfield name="RB_INT_MASK" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x01f3" name="CP_INT_STATUS"/>
+ <reg32 offset="0x01f4" name="CP_INT_ACK"/>
+ <reg32 offset="0x01f6" name="CP_ME_CNTL">
+ <bitfield name="BUSY" pos="29" type="boolean"/>
+ <bitfield name="HALT" pos="28" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x01f7" name="CP_ME_STATUS"/>
+ <reg32 offset="0x01f8" name="CP_ME_RAM_WADDR"/>
+ <reg32 offset="0x01f9" name="CP_ME_RAM_RADDR"/>
+ <reg32 offset="0x01fa" name="CP_ME_RAM_DATA"/>
+ <reg32 offset="0x01fc" name="CP_DEBUG">
+ <bitfield name="PREDICATE_DISABLE" pos="23" type="boolean"/>
+ <bitfield name="PROG_END_PTR_ENABLE" pos="24" type="boolean"/>
+ <bitfield name="MIU_128BIT_WRITE_ENABLE" pos="25" type="boolean"/>
+ <bitfield name="PREFETCH_PASS_NOPS" pos="26" type="boolean"/>
+ <bitfield name="DYNAMIC_CLK_DISABLE" pos="27" type="boolean"/>
+ <bitfield name="PREFETCH_MATCH_DISABLE" pos="28" type="boolean"/>
+ <bitfield name="SIMPLE_ME_FLOW_CONTROL" pos="30" type="boolean"/>
+ <bitfield name="MIU_WRITE_PACK_DISABLE" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x01fd" name="CP_CSQ_RB_STAT">
+ <bitfield name="RPTR" low="0" high="6" type="uint"/>
+ <bitfield name="WPTR" low="16" high="22" type="uint"/>
+ </reg32>
+ <reg32 offset="0x01fe" name="CP_CSQ_IB1_STAT">
+ <bitfield name="RPTR" low="0" high="6" type="uint"/>
+ <bitfield name="WPTR" low="16" high="22" type="uint"/>
+ </reg32>
+ <reg32 offset="0x01ff" name="CP_CSQ_IB2_STAT">
+ <bitfield name="RPTR" low="0" high="6" type="uint"/>
+ <bitfield name="WPTR" low="16" high="22" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x0440" name="CP_NON_PREFETCH_CNTRS"/>
+ <reg32 offset="0x0443" name="CP_STQ_ST_STAT"/>
+ <reg32 offset="0x044d" name="CP_ST_BASE"/>
+ <reg32 offset="0x044e" name="CP_ST_BUFSZ"/>
+ <reg32 offset="0x044f" name="CP_MEQ_STAT"/>
+ <reg32 offset="0x0452" name="CP_MIU_TAG_STAT"/>
+ <reg32 offset="0x0454" name="CP_BIN_MASK_LO"/>
+ <reg32 offset="0x0455" name="CP_BIN_MASK_HI"/>
+ <reg32 offset="0x0456" name="CP_BIN_SELECT_LO"/>
+ <reg32 offset="0x0457" name="CP_BIN_SELECT_HI"/>
+ <reg32 offset="0x0458" name="CP_IB1_BASE"/>
+ <reg32 offset="0x0459" name="CP_IB1_BUFSZ"/>
+ <reg32 offset="0x045a" name="CP_IB2_BASE"/>
+ <reg32 offset="0x045b" name="CP_IB2_BUFSZ"/>
+ <reg32 offset="0x047f" name="CP_STAT">
+ <bitfield pos="31" name="CP_BUSY"/>
+ <bitfield pos="30" name="VS_EVENT_FIFO_BUSY"/>
+ <bitfield pos="29" name="PS_EVENT_FIFO_BUSY"/>
+ <bitfield pos="28" name="CF_EVENT_FIFO_BUSY"/>
+ <bitfield pos="27" name="RB_EVENT_FIFO_BUSY"/>
+ <bitfield pos="26" name="ME_BUSY"/>
+ <bitfield pos="25" name="MIU_WR_C_BUSY"/>
+ <bitfield pos="23" name="CP_3D_BUSY"/>
+ <bitfield pos="22" name="CP_NRT_BUSY"/>
+ <bitfield pos="21" name="RBIU_SCRATCH_BUSY"/>
+ <bitfield pos="20" name="RCIU_ME_BUSY"/>
+ <bitfield pos="19" name="RCIU_PFP_BUSY"/>
+ <bitfield pos="18" name="MEQ_RING_BUSY"/>
+ <bitfield pos="17" name="PFP_BUSY"/>
+ <bitfield pos="16" name="ST_QUEUE_BUSY"/>
+ <bitfield pos="13" name="INDIRECT2_QUEUE_BUSY"/>
+ <bitfield pos="12" name="INDIRECTS_QUEUE_BUSY"/>
+ <bitfield pos="11" name="RING_QUEUE_BUSY"/>
+ <bitfield pos="10" name="CSF_BUSY"/>
+ <bitfield pos="9" name="CSF_ST_BUSY"/>
+ <bitfield pos="8" name="EVENT_BUSY"/>
+ <bitfield pos="7" name="CSF_INDIRECT2_BUSY"/>
+ <bitfield pos="6" name="CSF_INDIRECTS_BUSY"/>
+ <bitfield pos="5" name="CSF_RING_BUSY"/>
+ <bitfield pos="4" name="RCIU_BUSY"/>
+ <bitfield pos="3" name="RBIU_BUSY"/>
+ <bitfield pos="2" name="MIU_RD_RETURN_BUSY"/>
+ <bitfield pos="1" name="MIU_RD_REQ_BUSY"/>
+ <bitfield pos="0" name="MIU_WR_BUSY"/>
+ </reg32>
+ <reg32 offset="0x0578" name="CP_SCRATCH_REG0" type="uint"/>
+ <reg32 offset="0x0579" name="CP_SCRATCH_REG1" type="uint"/>
+ <reg32 offset="0x057a" name="CP_SCRATCH_REG2" type="uint"/>
+ <reg32 offset="0x057b" name="CP_SCRATCH_REG3" type="uint"/>
+ <reg32 offset="0x057c" name="CP_SCRATCH_REG4" type="uint"/>
+ <reg32 offset="0x057d" name="CP_SCRATCH_REG5" type="uint"/>
+ <reg32 offset="0x057e" name="CP_SCRATCH_REG6" type="uint"/>
+ <reg32 offset="0x057f" name="CP_SCRATCH_REG7" type="uint"/>
+
+ <reg32 offset="0x0600" name="CP_ME_VS_EVENT_SRC"/>
+ <reg32 offset="0x0601" name="CP_ME_VS_EVENT_ADDR"/>
+ <reg32 offset="0x0602" name="CP_ME_VS_EVENT_DATA"/>
+ <reg32 offset="0x0603" name="CP_ME_VS_EVENT_ADDR_SWM"/>
+ <reg32 offset="0x0604" name="CP_ME_VS_EVENT_DATA_SWM"/>
+ <reg32 offset="0x0605" name="CP_ME_PS_EVENT_SRC"/>
+ <reg32 offset="0x0606" name="CP_ME_PS_EVENT_ADDR"/>
+ <reg32 offset="0x0607" name="CP_ME_PS_EVENT_DATA"/>
+ <reg32 offset="0x0608" name="CP_ME_PS_EVENT_ADDR_SWM"/>
+ <reg32 offset="0x0609" name="CP_ME_PS_EVENT_DATA_SWM"/>
+ <reg32 offset="0x060a" name="CP_ME_CF_EVENT_SRC"/>
+ <reg32 offset="0x060b" name="CP_ME_CF_EVENT_ADDR"/>
+ <reg32 offset="0x060c" name="CP_ME_CF_EVENT_DATA" type="uint"/>
+ <reg32 offset="0x060d" name="CP_ME_NRT_ADDR"/>
+ <reg32 offset="0x060e" name="CP_ME_NRT_DATA"/>
+ <reg32 offset="0x0612" name="CP_ME_VS_FETCH_DONE_SRC"/>
+ <reg32 offset="0x0613" name="CP_ME_VS_FETCH_DONE_ADDR"/>
+ <reg32 offset="0x0614" name="CP_ME_VS_FETCH_DONE_DATA"/>
+
+</domain>
+
+<!--
+ Common between A3xx and A4xx:
+ -->
+
+<enum name="a3xx_rop_code">
+ <value name="ROP_CLEAR" value="0"/>
+ <value name="ROP_NOR" value="1"/>
+ <value name="ROP_AND_INVERTED" value="2"/>
+ <value name="ROP_COPY_INVERTED" value="3"/>
+ <value name="ROP_AND_REVERSE" value="4"/>
+ <value name="ROP_INVERT" value="5"/>
+ <value name="ROP_XOR" value="6"/>
+ <value name="ROP_NAND" value="7"/>
+ <value name="ROP_AND" value="8"/>
+ <value name="ROP_EQUIV" value="9"/>
+ <value name="ROP_NOOP" value="10"/>
+ <value name="ROP_OR_INVERTED" value="11"/>
+ <value name="ROP_COPY" value="12"/>
+ <value name="ROP_OR_REVERSE" value="13"/>
+ <value name="ROP_OR" value="14"/>
+ <value name="ROP_SET" value="15"/>
+</enum>
+
+<enum name="a3xx_render_mode">
+ <value name="RB_RENDERING_PASS" value="0"/>
+ <value name="RB_TILING_PASS" value="1"/>
+ <value name="RB_RESOLVE_PASS" value="2"/>
+ <value name="RB_COMPUTE_PASS" value="3"/>
+</enum>
+
+<enum name="a3xx_msaa_samples">
+ <value name="MSAA_ONE" value="0"/>
+ <value name="MSAA_TWO" value="1"/>
+ <value name="MSAA_FOUR" value="2"/>
+ <value name="MSAA_EIGHT" value="3"/>
+</enum>
+
+<enum name="a3xx_threadmode">
+ <value value="0" name="MULTI"/>
+ <value value="1" name="SINGLE"/>
+</enum>
+
+<enum name="a3xx_instrbuffermode">
+ <!--
+ When shader size goes above ~128 or so, blob switches to '0'
+ and doesn't emit shader in cmdstream. When either is '0' it
+ doesn't get emitted via CP_LOAD_STATE. When only one is
+ '0' the other gets size 256-others_size. So I think that:
+ BUFFER => execute out of state memory
+ CACHE => use available state memory as local cache
+ NOTE that when CACHE mode, also set CACHEINVALID flag!
+
+ TODO check if that 256 size is same for all a3xx
+ -->
+ <value value="0" name="CACHE"/>
+ <value value="1" name="BUFFER"/>
+</enum>
+
+<enum name="a3xx_threadsize">
+ <value value="0" name="TWO_QUADS"/>
+ <value value="1" name="FOUR_QUADS"/>
+</enum>
+
+<enum name="a3xx_color_swap">
+ <value name="WZYX" value="0"/>
+ <value name="WXYZ" value="1"/>
+ <value name="ZYXW" value="2"/>
+ <value name="XYZW" value="3"/>
+</enum>
+
+<enum name="a3xx_rb_blend_opcode">
+ <value name="BLEND_DST_PLUS_SRC" value="0"/>
+ <value name="BLEND_SRC_MINUS_DST" value="1"/>
+ <value name="BLEND_DST_MINUS_SRC" value="2"/>
+ <value name="BLEND_MIN_DST_SRC" value="3"/>
+ <value name="BLEND_MAX_DST_SRC" value="4"/>
+</enum>
+
+<enum name="a4xx_tess_spacing">
+ <value name="EQUAL_SPACING" value="0"/>
+ <value name="ODD_SPACING" value="2"/>
+ <value name="EVEN_SPACING" value="3"/>
+</enum>
+
+<doc>Address mode for a5xx+</doc>
+<enum name="a5xx_address_mode">
+ <value name="ADDR_32B" value="0"/>
+ <value name="ADDR_64B" value="1"/>
+</enum>
+
+<doc>
+ Line mode for a5xx+
+ Note that Bresenham lines are only supported with MSAA disabled.
+</doc>
+<enum name="a5xx_line_mode">
+ <value value="0x0" name="BRESENHAM"/>
+ <value value="0x1" name="RECTANGULAR"/>
+</enum>
+
+<doc>
+ Blob (v615) seem to only use SAM and I wasn't able to coerce
+ it to produce any other command.
+ Probably valid for a4xx+ but not enabled or tested on anything
+ but a6xx.
+</doc>
+<enum name="a6xx_tex_prefetch_cmd">
+ <doc> Produces garbage </doc>
+ <value value="0x0" name="TEX_PREFETCH_UNK0"/>
+ <value value="0x1" name="TEX_PREFETCH_SAM"/>
+ <value value="0x2" name="TEX_PREFETCH_GATHER4R"/>
+ <value value="0x3" name="TEX_PREFETCH_GATHER4G"/>
+ <value value="0x4" name="TEX_PREFETCH_GATHER4B"/>
+ <value value="0x5" name="TEX_PREFETCH_GATHER4A"/>
+ <doc> Causes reads from an invalid address </doc>
+ <value value="0x6" name="TEX_PREFETCH_UNK6"/>
+ <doc> Results in color being zero </doc>
+ <value value="0x7" name="TEX_PREFETCH_UNK7"/>
+</enum>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml
new file mode 100644
index 000000000000..cab01af55d22
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml
@@ -0,0 +1,2268 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+<import file="adreno/adreno_common.xml"/>
+
+<enum name="vgt_event_type" varset="chip">
+ <value name="VS_DEALLOC" value="0"/>
+ <value name="PS_DEALLOC" value="1" variants="A2XX-A6XX"/>
+ <value name="VS_DONE_TS" value="2"/>
+ <value name="PS_DONE_TS" value="3"/>
+ <doc>
+ Flushes dirty data from UCHE, and also writes a GPU timestamp to
+ the address if one is provided.
+ </doc>
+ <value name="CACHE_FLUSH_TS" value="4"/>
+ <value name="CONTEXT_DONE" value="5"/>
+ <value name="CACHE_FLUSH" value="6" variants="A2XX-A4XX"/>
+ <value name="VIZQUERY_START" value="7" variants="A2XX"/>
+ <value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/>
+ <value name="VIZQUERY_END" value="8" variants="A2XX"/>
+ <value name="SC_WAIT_WC" value="9" variants="A2XX"/>
+ <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/>
+ <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/>
+ <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/>
+ <!-- Not sure that these 4 events don't have the same meaning as on A5XX+ -->
+ <value name="RST_PIX_CNT" value="13" variants="A2XX-A4XX"/>
+ <value name="RST_VTX_CNT" value="14" variants="A2XX-A4XX"/>
+ <value name="TILE_FLUSH" value="15" variants="A2XX-A4XX"/>
+ <value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/>
+ <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/>
+ <doc>
+ If A6XX_RB_SAMPLE_COUNT_CONTROL.copy is true, writes OQ Z passed
+ sample counts to RB_SAMPLE_COUNT_ADDR. This writes to main
+ memory, skipping UCHE.
+ </doc>
+ <value name="ZPASS_DONE" value="21"/>
+ <value name="CACHE_FLUSH_AND_INV_EVENT" value="22" variants="A2XX"/>
+
+ <doc>
+ Writes the GPU timestamp to the address that follows, once RB
+ access and flushes are complete.
+ </doc>
+ <value name="RB_DONE_TS" value="22" variants="A3XX-"/>
+
+ <value name="PERFCOUNTER_START" value="23" variants="A2XX-A4XX"/>
+ <value name="PERFCOUNTER_STOP" value="24" variants="A2XX-A4XX"/>
+ <value name="VS_FETCH_DONE" value="27"/>
+ <value name="FACENESS_FLUSH" value="28" variants="A2XX-A4XX"/>
+
+ <!-- a5xx events -->
+ <value name="WT_DONE_TS" value="8" variants="A5XX-"/>
+ <value name="START_FRAGMENT_CTRS" value="13" variants="A5XX-"/>
+ <value name="STOP_FRAGMENT_CTRS" value="14" variants="A5XX-"/>
+ <value name="START_COMPUTE_CTRS" value="15" variants="A5XX-"/>
+ <value name="STOP_COMPUTE_CTRS" value="16" variants="A5XX-"/>
+ <value name="FLUSH_SO_0" value="17" variants="A5XX-"/>
+ <value name="FLUSH_SO_1" value="18" variants="A5XX-"/>
+ <value name="FLUSH_SO_2" value="19" variants="A5XX-"/>
+ <value name="FLUSH_SO_3" value="20" variants="A5XX-"/>
+
+ <doc>
+ Invalidates depth attachment data from the CCU. We assume this
+ happens in the last stage.
+ </doc>
+ <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX-"/>
+
+ <doc>
+ Invalidates color attachment data from the CCU. We assume this
+ happens in the last stage.
+ </doc>
+ <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX-"/>
+
+ <doc>
+ Flushes the small cache used by CP_EVENT_WRITE::BLIT (which,
+ along with its registers, would be better named RESOLVE).
+ </doc>
+ <value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/>
+
+ <doc>
+ Flushes depth attachment data from the CCU. We assume this
+ happens in the last stage.
+ </doc>
+ <value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX-"/>
+
+ <doc>
+ Flushes color attachment data from the CCU. We assume this
+ happens in the last stage.
+ </doc>
+ <value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX-"/>
+
+ <doc>
+ 2D blit to resolve GMEM to system memory (skipping CCU) at the
+ end of a render pass. Compare to CP_BLIT's BLIT_OP_SCALE for
+ more general blitting.
+ </doc>
+ <value name="BLIT" value="30" variants="A5XX-"/>
+
+ <doc>
+ Clears based on GRAS_LRZ_CNTL configuration, could clear
+ fast-clear buffer or LRZ direction.
+ LRZ direction is stored at lrz_fc_offset + 0x200, has 1 byte which
+ could be expressed by enum:
+ CUR_DIR_DISABLED = 0x0
+ CUR_DIR_GE = 0x1
+ CUR_DIR_LE = 0x2
+ CUR_DIR_UNSET = 0x3
+ Clear of direction means setting the direction to CUR_DIR_UNSET.
+ </doc>
+ <value name="LRZ_CLEAR" value="37" variants="A5XX-"/>
+
+ <value name="LRZ_FLUSH" value="38" variants="A5XX-"/>
+ <value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/>
+ <value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/>
+ <value name="UNK_40" value="40" variants="A7XX"/>
+ <value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/>
+ <value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/>
+ <value name="UNK_2C" value="44" variants="A5XX-"/>
+ <value name="UNK_2D" value="45" variants="A5XX-"/>
+
+ <!-- a6xx events -->
+ <doc>
+ Invalidates UCHE.
+ </doc>
+ <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
+
+ <value name="LABEL" value="63" variants="A6XX-"/>
+
+ <!-- note, some of these are the same as a6xx, just named differently -->
+
+ <doc> Doesn't seem to do anything </doc>
+ <value name="DUMMY_EVENT" value="1" variants="A7XX"/>
+ <value name="CCU_INVALIDATE_DEPTH" value="24" variants="A7XX"/>
+ <value name="CCU_INVALIDATE_COLOR" value="25" variants="A7XX"/>
+ <value name="CCU_RESOLVE_CLEAN" value="26" variants="A7XX"/>
+ <value name="CCU_FLUSH_DEPTH" value="28" variants="A7XX"/>
+ <value name="CCU_FLUSH_COLOR" value="29" variants="A7XX"/>
+ <value name="CCU_RESOLVE" value="30" variants="A7XX"/>
+ <value name="CCU_END_RESOLVE_GROUP" value="31" variants="A7XX"/>
+ <value name="CCU_CLEAN_DEPTH" value="32" variants="A7XX"/>
+ <value name="CCU_CLEAN_COLOR" value="33" variants="A7XX"/>
+ <value name="CACHE_RESET" value="48" variants="A7XX"/>
+ <value name="CACHE_CLEAN" value="49" variants="A7XX"/>
+ <!-- TODO: deal with name conflicts with other gens -->
+ <value name="CACHE_FLUSH7" value="50" variants="A7XX"/>
+ <value name="CACHE_INVALIDATE7" value="51" variants="A7XX"/>
+</enum>
+
+<enum name="pc_di_primtype">
+ <value name="DI_PT_NONE" value="0"/>
+ <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
+ <value name="DI_PT_POINTLIST_PSIZE" value="1"/>
+ <value name="DI_PT_LINELIST" value="2"/>
+ <value name="DI_PT_LINESTRIP" value="3"/>
+ <value name="DI_PT_TRILIST" value="4"/>
+ <value name="DI_PT_TRIFAN" value="5"/>
+ <value name="DI_PT_TRISTRIP" value="6"/>
+ <value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx -->
+ <value name="DI_PT_RECTLIST" value="8"/>
+ <value name="DI_PT_POINTLIST" value="9"/>
+ <value name="DI_PT_LINE_ADJ" value="0xa"/>
+ <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
+ <value name="DI_PT_TRI_ADJ" value="0xc"/>
+ <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
+
+ <value name="DI_PT_PATCHES0" value="0x1f"/>
+ <value name="DI_PT_PATCHES1" value="0x20"/>
+ <value name="DI_PT_PATCHES2" value="0x21"/>
+ <value name="DI_PT_PATCHES3" value="0x22"/>
+ <value name="DI_PT_PATCHES4" value="0x23"/>
+ <value name="DI_PT_PATCHES5" value="0x24"/>
+ <value name="DI_PT_PATCHES6" value="0x25"/>
+ <value name="DI_PT_PATCHES7" value="0x26"/>
+ <value name="DI_PT_PATCHES8" value="0x27"/>
+ <value name="DI_PT_PATCHES9" value="0x28"/>
+ <value name="DI_PT_PATCHES10" value="0x29"/>
+ <value name="DI_PT_PATCHES11" value="0x2a"/>
+ <value name="DI_PT_PATCHES12" value="0x2b"/>
+ <value name="DI_PT_PATCHES13" value="0x2c"/>
+ <value name="DI_PT_PATCHES14" value="0x2d"/>
+ <value name="DI_PT_PATCHES15" value="0x2e"/>
+ <value name="DI_PT_PATCHES16" value="0x2f"/>
+ <value name="DI_PT_PATCHES17" value="0x30"/>
+ <value name="DI_PT_PATCHES18" value="0x31"/>
+ <value name="DI_PT_PATCHES19" value="0x32"/>
+ <value name="DI_PT_PATCHES20" value="0x33"/>
+ <value name="DI_PT_PATCHES21" value="0x34"/>
+ <value name="DI_PT_PATCHES22" value="0x35"/>
+ <value name="DI_PT_PATCHES23" value="0x36"/>
+ <value name="DI_PT_PATCHES24" value="0x37"/>
+ <value name="DI_PT_PATCHES25" value="0x38"/>
+ <value name="DI_PT_PATCHES26" value="0x39"/>
+ <value name="DI_PT_PATCHES27" value="0x3a"/>
+ <value name="DI_PT_PATCHES28" value="0x3b"/>
+ <value name="DI_PT_PATCHES29" value="0x3c"/>
+ <value name="DI_PT_PATCHES30" value="0x3d"/>
+ <value name="DI_PT_PATCHES31" value="0x3e"/>
+</enum>
+
+<enum name="pc_di_src_sel">
+ <value name="DI_SRC_SEL_DMA" value="0"/>
+ <value name="DI_SRC_SEL_IMMEDIATE" value="1"/>
+ <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/>
+ <value name="DI_SRC_SEL_AUTO_XFB" value="3"/>
+</enum>
+
+<enum name="pc_di_face_cull_sel">
+ <value name="DI_FACE_CULL_NONE" value="0"/>
+ <value name="DI_FACE_CULL_FETCH" value="1"/>
+ <value name="DI_FACE_BACKFACE_CULL" value="2"/>
+ <value name="DI_FACE_FRONTFACE_CULL" value="3"/>
+</enum>
+
+<enum name="pc_di_index_size">
+ <value name="INDEX_SIZE_IGN" value="0"/>
+ <value name="INDEX_SIZE_16_BIT" value="0"/>
+ <value name="INDEX_SIZE_32_BIT" value="1"/>
+ <value name="INDEX_SIZE_8_BIT" value="2"/>
+ <value name="INDEX_SIZE_INVALID"/>
+</enum>
+
+<enum name="pc_di_vis_cull_mode">
+ <value name="IGNORE_VISIBILITY" value="0"/>
+ <value name="USE_VISIBILITY" value="1"/>
+</enum>
+
+<enum name="adreno_pm4_packet_type">
+ <value name="CP_TYPE0_PKT" value="0x00000000"/>
+ <value name="CP_TYPE1_PKT" value="0x40000000"/>
+ <value name="CP_TYPE2_PKT" value="0x80000000"/>
+ <value name="CP_TYPE3_PKT" value="0xc0000000"/>
+ <value name="CP_TYPE4_PKT" value="0x40000000"/>
+ <value name="CP_TYPE7_PKT" value="0x70000000"/>
+</enum>
+
+<!--
+ Note that in some cases, the same packet id is recycled on a later
+ generation, so variants attribute is used to distinguish. They
+ may not be completely accurate, we would probably have to analyze
+ the pfp and me/pm4 firmware to verify the packet is actually
+ handled on a particular generation. But it is at least enough to
+ disambiguate the packet-id's that were re-used for different
+ packets starting with a5xx.
+ -->
+<enum name="adreno_pm4_type3_packets" varset="chip">
+ <doc>initialize CP's micro-engine</doc>
+ <value name="CP_ME_INIT" value="0x48"/>
+ <doc>skip N 32-bit words to get to the next packet</doc>
+ <value name="CP_NOP" value="0x10"/>
+ <doc>
+ indirect buffer dispatch. prefetch parser uses this packet
+ type to determine whether to pre-fetch the IB
+ </doc>
+ <value name="CP_PREEMPT_ENABLE" value="0x1c" variants="A5XX"/>
+ <value name="CP_PREEMPT_TOKEN" value="0x1e" variants="A5XX"/>
+ <value name="CP_INDIRECT_BUFFER" value="0x3f"/>
+ <doc>
+ Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to
+ another buffer at the same level. Must be at the end of IB, and
+ doesn't work with draw state IB's.
+ </doc>
+ <value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/>
+ <doc>indirect buffer dispatch. same as IB, but init is pipelined</doc>
+ <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
+ <doc>
+ Waits for the IDLE state of the engine before further drawing.
+ This is pipelined, so the CP may continue.
+ </doc>
+ <value name="CP_WAIT_FOR_IDLE" value="0x26"/>
+ <doc>wait until a register or memory location is a specific value</doc>
+ <value name="CP_WAIT_REG_MEM" value="0x3c"/>
+ <doc>wait until a register location is equal to a specific value</doc>
+ <value name="CP_WAIT_REG_EQ" value="0x52"/>
+ <doc>wait until a register location is >= a specific value</doc>
+ <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX-A4XX"/>
+ <doc>wait until a read completes</doc>
+ <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX-A4XX"/>
+ <doc>wait until all base/size writes from an IB_PFD packet have completed</doc>
+ <!--
+ NOTE: CP_WAIT_IB_PFD_COMPLETE unimplemented at least since a5xx fw, and
+ recycled for something new on a7xx
+ -->
+ <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d" varset="chip" variants="A2XX-A4XX"/>
+ <doc>register read/modify/write</doc>
+ <value name="CP_REG_RMW" value="0x21"/>
+ <doc>Set binning configuration registers</doc>
+ <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX-A4XX"/>
+ <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX-"/>
+ <doc>reads register in chip and writes to memory</doc>
+ <value name="CP_REG_TO_MEM" value="0x3e"/>
+ <doc>write N 32-bit words to memory</doc>
+ <value name="CP_MEM_WRITE" value="0x3d"/>
+ <doc>write CP_PROG_COUNTER value to memory</doc>
+ <value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
+ <doc>conditional execution of a sequence of packets</doc>
+ <value name="CP_COND_EXEC" value="0x44"/>
+ <doc>conditional write to memory or register</doc>
+ <value name="CP_COND_WRITE" value="0x45" variants="A2XX-A4XX"/>
+ <value name="CP_COND_WRITE5" value="0x45" variants="A5XX-"/>
+ <doc>generate an event that creates a write to memory when completed</doc>
+ <value name="CP_EVENT_WRITE" value="0x46" variants="A2XX-A6XX"/>
+ <value name="CP_EVENT_WRITE7" value="0x46" variants="A7XX-"/>
+ <doc>generate a VS|PS_done event</doc>
+ <value name="CP_EVENT_WRITE_SHD" value="0x58"/>
+ <doc>generate a cache flush done event</doc>
+ <value name="CP_EVENT_WRITE_CFL" value="0x59"/>
+ <doc>generate a z_pass done event</doc>
+ <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
+ <doc>
+ not sure the real name, but this seems to be what is used for
+ opencl, instead of CP_DRAW_INDX..
+ </doc>
+ <value name="CP_RUN_OPENCL" value="0x31"/>
+ <doc>initiate fetch of index buffer and draw</doc>
+ <value name="CP_DRAW_INDX" value="0x22"/>
+ <doc>draw using supplied indices in packet</doc>
+ <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX-A4XX"/> <!-- this is something different on a6xx and unused on a5xx -->
+ <doc>initiate fetch of index buffer and binIDs and draw</doc>
+ <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX-A4XX"/>
+ <doc>initiate fetch of bin IDs and draw using supplied indices</doc>
+ <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX-A4XX"/>
+ <doc>begin/end initiator for viz query extent processing</doc>
+ <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX-A4XX"/>
+ <doc>fetch state sub-blocks and initiate shader code DMAs</doc>
+ <value name="CP_SET_STATE" value="0x25"/>
+ <doc>load constant into chip and to memory</doc>
+ <value name="CP_SET_CONSTANT" value="0x2d" variants="A2XX"/>
+ <doc>load sequencer instruction memory (pointer-based)</doc>
+ <value name="CP_IM_LOAD" value="0x27"/>
+ <doc>load sequencer instruction memory (code embedded in packet)</doc>
+ <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
+ <doc>load constants from a location in memory</doc>
+ <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/>
+ <doc>selective invalidation of state pointers</doc>
+ <value name="CP_INVALIDATE_STATE" value="0x3b"/>
+ <doc>dynamically changes shader instruction memory partition</doc>
+ <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX-A4XX"/>
+ <doc>sets the 64-bit BIN_MASK register in the PFP</doc>
+ <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX-A4XX"/>
+ <doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
+ <value name="CP_SET_BIN_SELECT" value="0x51" variants="A2XX-A4XX"/>
+ <doc>updates the current context, if needed</doc>
+ <value name="CP_CONTEXT_UPDATE" value="0x5e"/>
+ <doc>generate interrupt from the command stream</doc>
+ <value name="CP_INTERRUPT" value="0x40"/>
+ <doc>copy sequencer instruction memory to system memory</doc>
+ <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/>
+
+ <!-- For a20x -->
+<!-- TODO handle variants..
+ <doc>
+ Program an offset that will added to the BIN_BASE value of
+ the 3D_DRAW_INDX_BIN packet
+ </doc>
+ <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
+ -->
+
+ <!-- for a22x -->
+ <doc>
+ sets draw initiator flags register in PFP, gets bitwise-ORed into
+ every draw initiator
+ </doc>
+ <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
+ <doc>sets the register protection mode</doc>
+ <value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
+
+ <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
+
+ <!-- for a3xx -->
+ <doc>load high level sequencer command</doc>
+ <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
+ <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX-A5XX"/>
+ <doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
+ <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
+ <doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
+ <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
+ <doc>Load a buffer with pre-fetch enabled</doc>
+ <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/>
+ <doc>Set bin (?)</doc>
+ <value name="CP_SET_BIN" value="0x4c" variants="A2XX"/>
+
+ <doc>test 2 memory locations to dword values specified</doc>
+ <value name="CP_TEST_TWO_MEMS" value="0x71"/>
+
+ <doc>Write register, ignoring context state for context sensitive registers</doc>
+ <value name="CP_REG_WR_NO_CTXT" value="0x78"/>
+
+ <doc>Record the real-time when this packet is processed by PFP</doc>
+ <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
+
+ <!-- Used to switch GPU between secure and non-secure modes -->
+ <value name="CP_SET_SECURE_MODE" value="0x66"/>
+
+ <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc>
+ <value name="CP_WAIT_FOR_ME" value="0x13"/>
+
+ <!-- for a4xx -->
+ <doc>
+ Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple
+ groups of registers. Looks like it can be used to create state
+ objects in GPU memory, and on state change only emit pointer
+ (via CP_SET_DRAW_STATE), which should be nice for reducing CPU
+ overhead:
+
+ (A4x) save PM4 stream pointers to execute upon a visible draw
+ </doc>
+ <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX-"/>
+ <value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
+ <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX-"/>
+ <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX-"/>
+ <value name="CP_DRAW_INDIRECT_MULTI" value="0x2a" variants="A6XX-"/>
+ <value name="CP_DRAW_AUTO" value="0x24"/>
+
+ <doc>
+ Enable or disable predication globally. Also resets the
+ predicate to "passing" and the local bit to enabled when
+ enabling global predication.
+ </doc>
+ <value name="CP_DRAW_PRED_ENABLE_GLOBAL" value="0x19"/>
+
+ <doc>
+ Enable or disable predication locally. Unlike globally enabling
+ predication, this packet doesn't touch any other state.
+ Predication only happens when enabled globally and locally and a
+ predicate has been set. This should be used for internal draws
+ which aren't supposed to use the predication state:
+
+ CP_DRAW_PRED_ENABLE_LOCAL(0)
+ ... do draw...
+ CP_DRAW_PRED_ENABLE_LOCAL(1)
+ </doc>
+ <value name="CP_DRAW_PRED_ENABLE_LOCAL" value="0x1a"/>
+
+ <doc>
+ Latch a draw predicate into the internal register.
+ </doc>
+ <value name="CP_DRAW_PRED_SET" value="0x4e"/>
+
+ <doc>
+ for A4xx
+ Write to register with address that does not fit into type-0 pkt
+ </doc>
+ <value name="CP_WIDE_REG_WRITE" value="0x74" variants="A4XX"/>
+
+ <doc>copy from ME scratch RAM to a register</doc>
+ <value name="CP_SCRATCH_TO_REG" value="0x4d"/>
+
+ <doc>Copy from REG to ME scratch RAM</doc>
+ <value name="CP_REG_TO_SCRATCH" value="0x4a"/>
+
+ <doc>Wait for memory writes to complete</doc>
+ <value name="CP_WAIT_MEM_WRITES" value="0x12"/>
+
+ <doc>Conditional execution based on register comparison</doc>
+ <value name="CP_COND_REG_EXEC" value="0x47"/>
+
+ <doc>Memory to REG copy</doc>
+ <value name="CP_MEM_TO_REG" value="0x42"/>
+
+ <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX-"/>
+ <value name="CP_EXEC_CS" value="0x33"/>
+
+ <doc>
+ for a5xx
+ </doc>
+ <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/>
+ <!-- switches SMMU pagetable, used on a5xx+ only -->
+ <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX-"/>
+ <!-- for a6xx -->
+ <doc>Tells CP the current mode of GPU operation</doc>
+ <value name="CP_SET_MARKER" value="0x65" variants="A6XX-"/>
+ <doc>Instruct CP to set a few internal CP registers</doc>
+ <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX-"/>
+ <!--
+ pairs of regid and value.. seems to be used to program some TF
+ related regs:
+ -->
+ <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX-"/>
+ <!-- A5XX Enable yield in RB only -->
+ <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/>
+ <doc>
+ Enables IB2 skipping. If both GLOBAL and LOCAL are 1 and
+ nothing is left in the visibility stream, then
+ CP_INDIRECT_BUFFER will be skipped, and draws will early return
+ from their IB.
+ </doc>
+ <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX-"/>
+ <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX-"/>
+ <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX-"/>
+ <value name="CP_WHERE_AM_I" value="0x62" variants="A5XX-"/>
+ <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX-"/>
+ <!-- Enable/Disable/Defer A5x global preemption model -->
+ <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/>
+ <!-- Enable/Disable A5x local preemption model -->
+ <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/>
+ <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
+ <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX-"/>
+ <!-- Inform CP about current render mode (needed for a5xx preemption) -->
+ <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/>
+ <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/>
+ <!-- check if this works on earlier.. -->
+ <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX-"/>
+
+ <doc>
+ General purpose 2D blit engine for image transfers and mipmap
+ generation. Reads through UCHE, writes through the CCU cache in
+ the PS stage.
+ </doc>
+ <value name="CP_BLIT" value="0x2c" variants="A5XX-"/>
+
+ <!-- Test specified bit in specified register and set predicate -->
+ <value name="CP_REG_TEST" value="0x39" variants="A5XX-"/>
+
+ <!--
+ Seems to set the mode flags which control which CP_SET_DRAW_STATE
+ packets are executed, based on their ENABLE_MASK values
+
+ CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE
+ packets w/ ENABLE_MASK & 0x6 to execute immediately
+ -->
+ <value name="CP_SET_MODE" value="0x63" variants="A6XX-"/>
+
+ <!--
+ Seems like there are now separate blocks of state for VS vs FS/CS
+ (probably these amounts to geometry vs fragments so that geometry
+ stage of the pipeline for next draw can start while fragment stage
+ of current draw is still running. The format of the payload of the
+ packets is the same, the only difference is the offsets of the regs
+ the firmware code that handles the packet writes.
+
+ Note that for CL, starting with a6xx, the preferred # of local
+ threads is no longer the same as the max, implying that the shader
+ core can now run warps from unrelated shaders (ie.
+ CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs
+ CL_KERNEL_WORK_GROUP_SIZE)
+ -->
+ <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX-"/>
+ <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX-"/>
+ <!--
+ Note: For IBO state (Image/SSBOs) which have shared state across
+ shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for
+ compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are
+ interchangable.
+ -->
+ <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX-"/>
+
+ <!-- internal packets: -->
+ <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/>
+ <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/>
+ <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/>
+ <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/>
+ <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/>
+ <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/>
+ <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/>
+ <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/>
+
+ <!-- internal jumptable entries on a6xx+, possibly a5xx: -->
+
+ <!-- jmptable entry used to handle type4 packet on a5xx+: -->
+ <value name="PKT4" value="0x04" variants="A5XX-"/>
+ <!-- called when ROQ is empty, "returns" from an IB or merged sequence of IBs -->
+ <value name="IN_IB_END" value="0x0a" variants="A6XX-"/>
+ <!-- handles IFPC save/restore -->
+ <value name="IN_GMU_INTERRUPT" value="0x0b" variants="A6XX-"/>
+ <!-- preemption/context-swtich routine -->
+ <value name="IN_PREEMPT" value="0x0f" variants="A6XX-"/>
+
+ <!-- TODO do these exist on A5xx? -->
+ <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX"/>
+ <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX-"/>
+ <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX-"/>
+ <value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/>
+ <value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/>
+ <value name="CP_MEMCPY" value="0x75" variants="A6XX-"/>
+ <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX-"/>
+ <!-- A750+, set in place of CP_SET_BIN_DATA5_OFFSET but has different values -->
+ <value name="CP_SET_UNK_BIN_DATA" value="0x2d" variants="A7XX-"/>
+ <doc>
+ Write CP_CONTEXT_SWITCH_*_INFO from CP to the following dwords,
+ and forcibly switch to the indicated context.
+ </doc>
+ <value name="CP_CONTEXT_SWITCH" value="0x54" variants="A6XX"/>
+ <!-- Note, kgsl calls this CP_SET_AMBLE: -->
+ <value name="CP_SET_CTXSWITCH_IB" value="0x55" variants="A6XX-"/>
+
+ <!--
+ Seems to always have the payload:
+ 00000002 00008801 00004010
+ or:
+ 00000002 00008801 00004090
+ or:
+ 00000002 00008801 00000010
+ 00000002 00008801 00010010
+ 00000002 00008801 00d64010
+ ...
+ Note set for compute shaders..
+ Is 0x8801 a register offset?
+ This appears to be a special sort of register write packet
+ more or less, but the firmware has some special handling..
+ Seems like it intercepts/modifies certain register offsets,
+ but others are treated like a normal PKT4 reg write. I
+ guess there are some registers that the fw controls certain
+ bits.
+ -->
+ <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/>
+
+ <doc>
+ These first appear in a650_sqe.bin. They can in theory be used
+ to loop any sequence of IB1 commands, but in practice they are
+ used to loop over bins. There is a fixed-size per-iteration
+ prefix, used to set per-bin state, and then the following IB1
+ commands are executed until CP_END_BIN which are always the same
+ for each iteration and usually contain a list of
+ CP_INDIRECT_BUFFER calls to IB2 commands which setup state and
+ execute restore/draw/save commands. This replaces the previous
+ technique of just repeating the CP_INDIRECT_BUFFER calls and
+ "unrolling" the loop.
+ </doc>
+ <value name="CP_START_BIN" value="0x50" variants="A6XX-"/>
+ <value name="CP_END_BIN" value="0x51" variants="A6XX-"/>
+
+ <doc> Make next dword 1 to disable preemption, 0 to re-enable it. </doc>
+ <value name="CP_PREEMPT_DISABLE" value="0x6c" variants="A6XX"/>
+
+ <value name="CP_WAIT_TIMESTAMP" value="0x14" variants="A7XX-"/>
+ <value name="CP_GLOBAL_TIMESTAMP" value="0x15" variants="A7XX-"/> <!-- payload 1 dword -->
+ <value name="CP_LOCAL_TIMESTAMP" value="0x16" variants="A7XX-"/> <!-- payload 1 dword, follows 0x15 -->
+ <value name="CP_THREAD_CONTROL" value="0x17" variants="A7XX-"/>
+ <!-- payload 4 dwords, last two could be render target addr (one pkt per MRT), possibly used for GMEM save/restore?-->
+ <value name="CP_RESOURCE_LIST" value="0x18" variants="A7XX-"/>
+ <doc> Can clear BV/BR counters, or wait until one catches up to another </doc>
+ <value name="CP_BV_BR_COUNT_OPS" value="0x1b" variants="A7XX-"/>
+ <doc> Clears, adds to local, or adds to global timestamp </doc>
+ <value name="CP_MODIFY_TIMESTAMP" value="0x1c" variants="A7XX-"/>
+ <!-- similar to CP_CONTEXT_REG_BUNCH, but discards first two dwords?? -->
+ <value name="CP_CONTEXT_REG_BUNCH2" value="0x5d" variants="A7XX-"/>
+ <doc>
+ Write to a scratch memory that is read by CP_REG_TEST with
+ SOURCE_SCRATCH_MEM set. It's not the same scratch as scratch registers.
+ However it uses the same memory space.
+ </doc>
+ <value name="CP_MEM_TO_SCRATCH_MEM" value="0x49" variants="A7XX-"/>
+
+ <doc>
+ Executes an array of fixed-size command buffers where each
+ buffer is assumed to have one draw call, skipping buffers with
+ non-visible draw calls.
+ </doc>
+ <value name="CP_FIXED_STRIDE_DRAW_TABLE" value="0x7f" variants="A7XX-"/>
+
+ <doc>Reset various on-chip state used for synchronization</doc>
+ <value name="CP_RESET_CONTEXT_STATE" value="0x1f" variants="A7XX-"/>
+</enum>
+
+
+<domain name="CP_LOAD_STATE" width="32">
+ <doc>Load state, a3xx (and later?)</doc>
+ <enum name="adreno_state_block">
+ <value name="SB_VERT_TEX" value="0"/>
+ <value name="SB_VERT_MIPADDR" value="1"/>
+ <value name="SB_FRAG_TEX" value="2"/>
+ <value name="SB_FRAG_MIPADDR" value="3"/>
+ <value name="SB_VERT_SHADER" value="4"/>
+ <value name="SB_GEOM_SHADER" value="5"/>
+ <value name="SB_FRAG_SHADER" value="6"/>
+ <value name="SB_COMPUTE_SHADER" value="7"/>
+ </enum>
+ <enum name="adreno_state_type">
+ <value name="ST_SHADER" value="0"/>
+ <value name="ST_CONSTANTS" value="1"/>
+ </enum>
+ <enum name="adreno_state_src">
+ <value name="SS_DIRECT" value="0">
+ <doc>inline with the CP_LOAD_STATE packet</doc>
+ </value>
+ <value name="SS_INVALID_ALL_IC" value="2"/>
+ <value name="SS_INVALID_PART_IC" value="3"/>
+ <value name="SS_INDIRECT" value="4">
+ <doc>in buffer pointed to by EXT_SRC_ADDR</doc>
+ </value>
+ <value name="SS_INDIRECT_TCM" value="5"/>
+ <value name="SS_INDIRECT_STM" value="6"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="DST_OFF" low="0" high="15" type="uint"/>
+ <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
+ <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
+ <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
+ <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
+ </reg32>
+</domain>
+
+<domain name="CP_LOAD_STATE4" width="32" varset="chip">
+ <doc>Load state, a4xx+</doc>
+ <enum name="a4xx_state_block">
+ <!--
+ unknown: 0x7 and 0xf <- seen in compute shader
+
+ STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption?
+ Seen in some GL shaders. Payload is NUM_UNIT dwords, and it contains
+ the gpuaddr of the following shader constants block. DST_OFF seems
+ to specify which shader stage:
+
+ 16 -> vert
+ 36 -> tcs
+ 56 -> tes
+ 76 -> geom
+ 96 -> frag
+
+ Example:
+
+opcode: CP_LOAD_STATE4 (30) (12 dwords)
+ { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 }
+ { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 }
+ { EXT_SRC_ADDR_HI = 0 }
+ 0000: c0264100 00000000 00000000 00000000
+ 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000
+
+opcode: CP_LOAD_STATE4 (30) (4 dwords)
+ { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
+ { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 }
+ { EXT_SRC_ADDR_HI = 0 }
+ 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
+ 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
+ 0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000
+
+ STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader. NUM_UNITS * 2 dwords.
+
+ -->
+ <value name="SB4_VS_TEX" value="0x0"/>
+ <value name="SB4_HS_TEX" value="0x1"/> <!-- aka. TCS -->
+ <value name="SB4_DS_TEX" value="0x2"/> <!-- aka. TES -->
+ <value name="SB4_GS_TEX" value="0x3"/>
+ <value name="SB4_FS_TEX" value="0x4"/>
+ <value name="SB4_CS_TEX" value="0x5"/>
+ <value name="SB4_VS_SHADER" value="0x8"/>
+ <value name="SB4_HS_SHADER" value="0x9"/>
+ <value name="SB4_DS_SHADER" value="0xa"/>
+ <value name="SB4_GS_SHADER" value="0xb"/>
+ <value name="SB4_FS_SHADER" value="0xc"/>
+ <value name="SB4_CS_SHADER" value="0xd"/>
+ <!--
+ for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each),
+ STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each)
+
+ Compute has it's own dedicated SSBO state, it seems, but the rest
+ of the stages share state
+ -->
+ <value name="SB4_SSBO" value="0xe"/>
+ <value name="SB4_CS_SSBO" value="0xf"/>
+ </enum>
+ <enum name="a4xx_state_type">
+ <value name="ST4_SHADER" value="0"/>
+ <value name="ST4_CONSTANTS" value="1"/>
+ <value name="ST4_UBO" value="2"/>
+ </enum>
+ <enum name="a4xx_state_src">
+ <value name="SS4_DIRECT" value="0"/>
+ <value name="SS4_INDIRECT" value="2"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
+ <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
+ <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
+ <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
+ <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
+ </reg32>
+ <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
+ <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
+ </reg32>
+</domain>
+
+<!-- looks basically same CP_LOAD_STATE4 -->
+<domain name="CP_LOAD_STATE6" width="32" varset="chip">
+ <doc>Load state, a6xx+</doc>
+ <enum name="a6xx_state_block">
+ <value name="SB6_VS_TEX" value="0x0"/>
+ <value name="SB6_HS_TEX" value="0x1"/> <!-- aka. TCS -->
+ <value name="SB6_DS_TEX" value="0x2"/> <!-- aka. TES -->
+ <value name="SB6_GS_TEX" value="0x3"/>
+ <value name="SB6_FS_TEX" value="0x4"/>
+ <value name="SB6_CS_TEX" value="0x5"/>
+ <value name="SB6_VS_SHADER" value="0x8"/>
+ <value name="SB6_HS_SHADER" value="0x9"/>
+ <value name="SB6_DS_SHADER" value="0xa"/>
+ <value name="SB6_GS_SHADER" value="0xb"/>
+ <value name="SB6_FS_SHADER" value="0xc"/>
+ <value name="SB6_CS_SHADER" value="0xd"/>
+ <value name="SB6_IBO" value="0xe"/>
+ <value name="SB6_CS_IBO" value="0xf"/>
+ </enum>
+ <enum name="a6xx_state_type">
+ <value name="ST6_SHADER" value="0"/>
+ <value name="ST6_CONSTANTS" value="1"/>
+ <value name="ST6_UBO" value="2"/>
+ <value name="ST6_IBO" value="3"/>
+ </enum>
+ <enum name="a6xx_state_src">
+ <value name="SS6_DIRECT" value="0"/>
+ <value name="SS6_BINDLESS" value="1"/> <!-- TODO does this exist on a4xx/a5xx? -->
+ <value name="SS6_INDIRECT" value="2"/>
+ <doc>
+ SS6_UBO used by the a6xx vulkan blob with tesselation constants
+ in this case, EXT_SRC_ADDR is (ubo_id shl 16 | offset)
+ to load constants from a UBO loaded with DST_OFF = 14 and offset 0,
+ EXT_SRC_ADDR = 0xe0000
+ (offset is a guess, should be in bytes given that maxUniformBufferRange=64k)
+ </doc>
+ <value name="SS6_UBO" value="3"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
+ <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
+ <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
+ <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
+ <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
+ </reg32>
+ <reg64 offset="1" name="EXT_SRC_ADDR" type="address"/>
+</domain>
+
+<bitset name="vgt_draw_initiator" inline="yes">
+ <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
+ <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
+ <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
+ <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/>
+ <bitfield name="NOT_EOP" pos="12" type="boolean"/>
+ <bitfield name="SMALL_INDEX" pos="13" type="boolean"/>
+ <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/>
+ <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
+</bitset>
+
+<!-- changed on a4xx: -->
+<enum name="a4xx_index_size">
+ <value name="INDEX4_SIZE_8_BIT" value="0"/>
+ <value name="INDEX4_SIZE_16_BIT" value="1"/>
+ <value name="INDEX4_SIZE_32_BIT" value="2"/>
+</enum>
+
+<enum name="a6xx_patch_type">
+ <value name="TESS_QUADS" value="0"/>
+ <value name="TESS_TRIANGLES" value="1"/>
+ <value name="TESS_ISOLINES" value="2"/>
+</enum>
+
+<bitset name="vgt_draw_initiator_a4xx" inline="yes">
+ <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
+ <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
+ <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
+ <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
+ <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
+ <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
+ <bitfield name="GS_ENABLE" pos="16" type="boolean"/>
+ <bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
+</bitset>
+
+<domain name="CP_DRAW_INDX" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="VIZ_QUERY" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
+ <reg32 offset="2" name="2">
+ <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="INDX_BASE" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="4" name="4">
+ <bitfield name="INDX_SIZE" low="0" high="31"/>
+ </reg32>
+</domain>
+
+<domain name="CP_DRAW_INDX_2" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="VIZ_QUERY" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
+ <reg32 offset="2" name="2">
+ <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
+ </reg32>
+ <!-- followed by NUM_INDICES indices.. -->
+</domain>
+
+<domain name="CP_DRAW_INDX_OFFSET" width="32">
+ <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
+ <reg32 offset="1" name="1">
+ <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="FIRST_INDX" low="0" high="31"/>
+ </reg32>
+
+ <stripe varset="chip" variants="A5XX-">
+ <reg32 offset="4" name="4">
+ <bitfield name="INDX_BASE_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="5" name="5">
+ <bitfield name="INDX_BASE_HI" low="0" high="31"/>
+ </reg32>
+ <reg64 offset="4" name="INDX_BASE" type="address"/>
+ <reg32 offset="6" name="6">
+ <!-- max # of elements in index buffer -->
+ <bitfield name="MAX_INDICES" low="0" high="31"/>
+ </reg32>
+ </stripe>
+
+ <reg32 offset="4" name="4">
+ <bitfield name="INDX_BASE" low="0" high="31" type="address"/>
+ </reg32>
+
+ <reg32 offset="5" name="5">
+ <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
+ <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
+ <stripe varset="chip" variants="A4XX">
+ <reg32 offset="1" name="1">
+ <bitfield name="INDIRECT" low="0" high="31"/>
+ </reg32>
+ </stripe>
+ <stripe varset="chip" variants="A5XX-">
+ <reg32 offset="1" name="1">
+ <bitfield name="INDIRECT_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="INDIRECT_HI" low="0" high="31"/>
+ </reg32>
+ <reg64 offset="1" name="INDIRECT" type="address"/>
+ </stripe>
+</domain>
+
+<domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
+ <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
+ <stripe varset="chip" variants="A4XX">
+ <reg32 offset="1" name="1">
+ <bitfield name="INDX_BASE" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <!-- max # of bytes in index buffer -->
+ <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="INDIRECT" low="0" high="31"/>
+ </reg32>
+ </stripe>
+ <stripe varset="chip" variants="A5XX-">
+ <reg32 offset="1" name="1">
+ <bitfield name="INDX_BASE_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="INDX_BASE_HI" low="0" high="31"/>
+ </reg32>
+ <reg64 offset="1" name="INDX_BASE" type="address"/>
+ <reg32 offset="3" name="3">
+ <!-- max # of elements in index buffer -->
+ <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="4" name="4">
+ <bitfield name="INDIRECT_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="5" name="5">
+ <bitfield name="INDIRECT_HI" low="0" high="31"/>
+ </reg32>
+ <reg64 offset="4" name="INDIRECT" type="address"/>
+ </stripe>
+</domain>
+
+<domain name="CP_DRAW_INDIRECT_MULTI" width="32" varset="chip" prefix="chip" variants="A6XX-">
+ <enum name="a6xx_draw_indirect_opcode">
+ <value name="INDIRECT_OP_NORMAL" value="0x2"/>
+ <value name="INDIRECT_OP_INDEXED" value="0x4"/>
+ <value name="INDIRECT_OP_INDIRECT_COUNT" value="0x6"/>
+ <value name="INDIRECT_OP_INDIRECT_COUNT_INDEXED" value="0x7"/>
+ </enum>
+ <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
+ <reg32 offset="1" name="1">
+ <bitfield name="OPCODE" low="0" high="3" type="a6xx_draw_indirect_opcode" addvariant="yes"/>
+ <doc>
+ DST_OFF same as in CP_LOAD_STATE6 - vec4 VS const at this offset will
+ be updated for each draw to {draw_id, first_vertex, first_instance, 0}
+ value of 0 disables it
+ </doc>
+ <bitfield name="DST_OFF" low="8" high="21" type="hex"/>
+ </reg32>
+ <reg32 offset="2" name="DRAW_COUNT" type="uint"/>
+ <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_NORMAL">
+ <reg64 offset="3" name="INDIRECT" type="address"/>
+ <reg32 offset="5" name="STRIDE" type="uint"/>
+ </stripe>
+ <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDEXED" prefix="INDEXED">
+ <reg64 offset="3" name="INDEX" type="address"/>
+ <reg32 offset="5" name="MAX_INDICES" type="uint"/>
+ <reg64 offset="6" name="INDIRECT" type="address"/>
+ <reg32 offset="8" name="STRIDE" type="uint"/>
+ </stripe>
+ <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT" prefix="INDIRECT">
+ <reg64 offset="3" name="INDIRECT" type="address"/>
+ <reg64 offset="5" name="INDIRECT_COUNT" type="address"/>
+ <reg32 offset="7" name="STRIDE" type="uint"/>
+ </stripe>
+ <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT_INDEXED" prefix="INDIRECT_INDEXED">
+ <reg64 offset="3" name="INDEX" type="address"/>
+ <reg32 offset="5" name="MAX_INDICES" type="uint"/>
+ <reg64 offset="6" name="INDIRECT" type="address"/>
+ <reg64 offset="8" name="INDIRECT_COUNT" type="address"/>
+ <reg32 offset="10" name="STRIDE" type="uint"/>
+ </stripe>
+</domain>
+
+<domain name="CP_DRAW_AUTO" width="32">
+ <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
+ <reg32 offset="1" name="1">
+ <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg64 offset="2" name="NUM_VERTICES_BASE" type="address"/>
+ <reg32 offset="4" name="4">
+ <bitfield name="NUM_VERTICES_OFFSET" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="5" name="5">
+ <bitfield name="STRIDE" low="0" high="31" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="CP_DRAW_PRED_ENABLE_GLOBAL" width="32" varset="chip">
+ <reg32 offset="0" name="0">
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ </reg32>
+</domain>
+
+<domain name="CP_DRAW_PRED_ENABLE_LOCAL" width="32" varset="chip">
+ <reg32 offset="0" name="0">
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ </reg32>
+</domain>
+
+<domain name="CP_DRAW_PRED_SET" width="32" varset="chip">
+ <enum name="cp_draw_pred_src">
+ <!--
+ Sources 1-4 seem to be about combining reading
+ SO/primitive queries and setting the predicate, which is
+ a DX11-specific optimization (since in DX11 you can only
+ predicate on the result of queries).
+ -->
+ <value name="PRED_SRC_MEM" value="5">
+ <doc>
+ Read a 64-bit value at the given address and
+ test if it equals/doesn't equal 0.
+ </doc>
+ </value>
+ </enum>
+ <enum name="cp_draw_pred_test">
+ <value name="NE_0_PASS" value="0"/>
+ <value name="EQ_0_PASS" value="1"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="SRC" low="4" high="7" type="cp_draw_pred_src"/>
+ <bitfield name="TEST" pos="8" type="cp_draw_pred_test"/>
+ </reg32>
+ <reg64 offset="1" name="MEM_ADDR" type="address"/>
+</domain>
+
+<domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
+ <array offset="0" stride="3" length="100">
+ <reg32 offset="0" name="0">
+ <bitfield name="COUNT" low="0" high="15" type="uint"/>
+ <bitfield name="DIRTY" pos="16" type="boolean"/>
+ <bitfield name="DISABLE" pos="17" type="boolean"/>
+ <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
+ <bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
+ <bitfield name="BINNING" pos="20" varset="chip" variants="A6XX-" type="boolean"/>
+ <bitfield name="GMEM" pos="21" varset="chip" variants="A6XX-" type="boolean"/>
+ <bitfield name="SYSMEM" pos="22" varset="chip" variants="A6XX-" type="boolean"/>
+ <bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
+ <bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
+ </reg32>
+ </array>
+</domain>
+
+<domain name="CP_SET_BIN" width="32">
+ <doc>value at offset 0 always seems to be 0x00000000..</doc>
+ <reg32 offset="0" name="0"/>
+ <reg32 offset="1" name="1">
+ <bitfield name="X1" low="0" high="15" type="uint"/>
+ <bitfield name="Y1" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="X2" low="0" high="15" type="uint"/>
+ <bitfield name="Y2" low="16" high="31" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="CP_SET_BIN_DATA" width="32">
+ <reg32 offset="0" name="0">
+ <!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
+ <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <!-- seesm to correspond to VSC_SIZE_ADDRESS -->
+ <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
+ </reg32>
+</domain>
+
+<domain name="CP_SET_BIN_DATA5" width="32">
+ <reg32 offset="0" name="0">
+ <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
+ <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
+ <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
+ <bitfield name="VSC_N" low="22" high="26" type="uint"/>
+ </reg32>
+ <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
+ <reg32 offset="1" name="1">
+ <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
+ </reg32>
+ <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
+ <reg32 offset="3" name="3">
+ <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="4" name="4">
+ <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
+ </reg32>
+ <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: -->
+ <reg32 offset="5" name="5">
+ <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="6" name="6">
+ <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/>
+ </reg32>
+ <!--
+ a7xx adds a few more addresses to the end of the pkt
+ -->
+ <reg64 offset="7" name="7"/>
+ <reg64 offset="9" name="9"/>
+</domain>
+
+<domain name="CP_SET_BIN_DATA5_OFFSET" width="32">
+ <doc>
+ Like CP_SET_BIN_DATA5, but set the pointers as offsets from the
+ pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful
+ for Vulkan where these values aren't known when the command
+ stream is recorded.
+ </doc>
+ <reg32 offset="0" name="0">
+ <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
+ <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
+ <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
+ <bitfield name="VSC_N" low="22" high="26" type="uint"/>
+ </reg32>
+ <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
+ <reg32 offset="1" name="1">
+ <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/>
+ </reg32>
+ <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
+ <reg32 offset="2" name="2">
+ <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/>
+ </reg32>
+ <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
+ <reg32 offset="3" name="3">
+ <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="CP_REG_RMW" width="32">
+ <doc>
+ Modifies DST_REG using two sources that can either be registers
+ or immediates. If SRC1_ADD is set, then do the following:
+
+ $dst = (($dst &amp; $src0) rot $rotate) + $src1
+
+ Otherwise:
+
+ $dst = (($dst &amp; $src0) rot $rotate) | $src1
+
+ Here "rot" means rotate left.
+ </doc>
+ <reg32 offset="0" name="0">
+ <bitfield name="DST_REG" low="0" high="17" type="hex"/>
+ <bitfield name="ROTATE" low="24" high="28" type="uint"/>
+ <bitfield name="SRC1_ADD" pos="29" type="boolean"/>
+ <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/>
+ <bitfield name="SRC0_IS_REG" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="SRC0" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="SRC1" low="0" high="31" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="CP_REG_TO_MEM" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="REG" low="0" high="17" type="hex"/>
+ <!-- number of registers/dwords copied is max(CNT, 1). -->
+ <bitfield name="CNT" low="18" high="29" type="uint"/>
+ <bitfield name="64B" pos="30" type="boolean"/>
+ <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="DEST" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
+ <bitfield name="DEST_HI" low="0" high="31"/>
+ </reg32>
+</domain>
+
+<domain name="CP_REG_TO_MEM_OFFSET_REG" width="32">
+ <doc>
+ Like CP_REG_TO_MEM, but the memory address to write to can be
+ offsetted using either one or two registers or scratch
+ registers.
+ </doc>
+ <reg32 offset="0" name="0">
+ <bitfield name="REG" low="0" high="17" type="hex"/>
+ <!-- number of registers/dwords copied is max(CNT, 1). -->
+ <bitfield name="CNT" low="18" high="29" type="uint"/>
+ <bitfield name="64B" pos="30" type="boolean"/>
+ <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="DEST" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
+ <bitfield name="DEST_HI" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="OFFSET0" low="0" high="17" type="hex"/>
+ <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/>
+ </reg32>
+ <!-- followed by an optional identical OFFSET1 dword -->
+</domain>
+
+<domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32">
+ <doc>
+ Like CP_REG_TO_MEM, but the memory address to write to can be
+ offsetted using a DWORD in memory.
+ </doc>
+ <reg32 offset="0" name="0">
+ <bitfield name="REG" low="0" high="17" type="hex"/>
+ <!-- number of registers/dwords copied is max(CNT, 1). -->
+ <bitfield name="CNT" low="18" high="29" type="uint"/>
+ <bitfield name="64B" pos="30" type="boolean"/>
+ <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="DEST" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
+ <bitfield name="DEST_HI" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="4" name="4">
+ <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/>
+ </reg32>
+</domain>
+
+<domain name="CP_MEM_TO_REG" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="REG" low="0" high="17" type="hex"/>
+ <!-- number of registers/dwords copied is max(CNT, 1). -->
+ <bitfield name="CNT" low="19" high="29" type="uint"/>
+ <!-- shift each DWORD left by 2 while copying -->
+ <bitfield name="SHIFT_BY_2" pos="30" type="boolean"/>
+ <!-- does the same thing as CP_MEM_TO_MEM::UNK31 -->
+ <bitfield name="UNK31" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="SRC" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
+ <bitfield name="SRC_HI" low="0" high="31"/>
+ </reg32>
+</domain>
+
+<domain name="CP_MEM_TO_MEM" width="32">
+ <reg32 offset="0" name="0">
+ <!--
+ not sure how many src operands we have, but the low
+ bits negate the n'th src argument.
+ -->
+ <bitfield name="NEG_A" pos="0" type="boolean"/>
+ <bitfield name="NEG_B" pos="1" type="boolean"/>
+ <bitfield name="NEG_C" pos="2" type="boolean"/>
+
+ <!-- if set treat src/dst as 64bit values -->
+ <bitfield name="DOUBLE" pos="29" type="boolean"/>
+ <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand -->
+ <bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/>
+ <!-- some other kind of wait -->
+ <bitfield name="UNK31" pos="31" type="boolean"/>
+ </reg32>
+ <!--
+ followed by sequence of addresses.. the first is the
+ destination and the rest are N src addresses which are
+ summed (after being negated if NEG_x bit set) allowing
+ to do things like 'result += end - start' (which turns
+ out to be useful for queries and accumulating results
+ across multiple tiles)
+ -->
+</domain>
+
+<domain name="CP_MEMCPY" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="DWORDS" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="SRC_LO" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="SRC_HI" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="DST_LO" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="4" name="4">
+ <bitfield name="DST_HI" low="0" high="31" type="hex"/>
+ </reg32>
+</domain>
+
+<domain name="CP_REG_TO_SCRATCH" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="REG" low="0" high="17" type="hex"/>
+ <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
+ <!-- number of registers/dwords copied is CNT + 1. -->
+ <bitfield name="CNT" low="24" high="26" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="CP_SCRATCH_TO_REG" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="REG" low="0" high="17" type="hex"/>
+ <!-- note: CP_MEM_TO_REG always sets this when writing to the register -->
+ <bitfield name="UNK18" pos="18" type="boolean"/>
+ <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
+ <!-- number of registers/dwords copied is CNT + 1. -->
+ <bitfield name="CNT" low="24" high="26" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="CP_SCRATCH_WRITE" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
+ </reg32>
+ <!-- followed by one or more DWORDs to write to scratch registers -->
+</domain>
+
+<domain name="CP_MEM_WRITE" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="ADDR_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="ADDR_HI" low="0" high="31"/>
+ </reg32>
+ <!-- followed by the DWORDs to write -->
+</domain>
+
+<enum name="cp_cond_function">
+ <value value="0" name="WRITE_ALWAYS"/>
+ <value value="1" name="WRITE_LT"/>
+ <value value="2" name="WRITE_LE"/>
+ <value value="3" name="WRITE_EQ"/>
+ <value value="4" name="WRITE_NE"/>
+ <value value="5" name="WRITE_GE"/>
+ <value value="6" name="WRITE_GT"/>
+</enum>
+
+<domain name="CP_COND_WRITE" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
+ <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
+ <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="REF" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="MASK" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="4" name="4">
+ <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="5" name="5">
+ <bitfield name="WRITE_DATA" low="0" high="31"/>
+ </reg32>
+</domain>
+
+<enum name="poll_memory_type">
+ <value value="0" name="POLL_REGISTER"/>
+ <value value="1" name="POLL_MEMORY"/>
+ <value value="2" name="POLL_SCRATCH"/>
+ <value value="3" name="POLL_ON_CHIP" varset="chip" variants="A7XX-"/>
+</enum>
+
+<domain name="CP_COND_WRITE5" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
+ <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
+ <!-- POLL_REGISTER polls a register at POLL_ADDR_LO. -->
+ <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/>
+ <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="REF" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="4" name="4">
+ <bitfield name="MASK" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="5" name="5">
+ <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="6" name="6">
+ <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="7" name="7">
+ <bitfield name="WRITE_DATA" low="0" high="31"/>
+ </reg32>
+</domain>
+
+<domain name="CP_WAIT_MEM_GTE" width="32">
+ <doc>
+ Wait until a memory value is greater than or equal to the
+ reference, using signed comparison.
+ </doc>
+ <reg32 offset="0" name="0">
+ <!-- Reserved for flags, presumably? Unused in FW -->
+ <bitfield name="RESERVED" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="REF" low="0" high="31"/>
+ </reg32>
+</domain>
+
+<domain name="CP_WAIT_REG_MEM" width="32">
+ <doc>
+ This uses the same internal comparison as CP_COND_WRITE,
+ but waits until the comparison is true instead. It busy-loops in
+ the CP for the given number of cycles before trying again.
+ </doc>
+ <reg32 offset="0" name="0">
+ <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
+ <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
+ <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/>
+ <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="REF" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="4" name="4">
+ <bitfield name="MASK" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="5" name="5">
+ <bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/>
+ </reg32>
+</domain>
+
+<domain name="CP_WAIT_TWO_REGS" width="32">
+ <doc>
+ Waits for REG0 to not be 0 or REG1 to not equal REF
+ </doc>
+ <reg32 offset="0" name="0">
+ <bitfield name="REG0" low="0" high="17" type="hex"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="REG1" low="0" high="17" type="hex"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="REF" low="0" high="31" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="CP_DISPATCH_COMPUTE" width="32">
+ <reg32 offset="0" name="0"/>
+ <reg32 offset="1" name="1">
+ <bitfield name="X" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="Y" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="Z" low="0" high="31"/>
+ </reg32>
+</domain>
+
+<domain name="CP_SET_RENDER_MODE" width="32">
+ <enum name="render_mode_cmd">
+ <value value="1" name="BYPASS"/>
+ <value value="2" name="BINNING"/>
+ <value value="3" name="GMEM"/>
+ <value value="5" name="BLIT2D"/>
+ <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
+ <value value="7" name="BLIT2DSCALE"/>
+ <!-- 8 set before going back to BYPASS exiting 2D -->
+ <value value="8" name="END2D"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
+ <!--
+ normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in
+ 0x21xx range.. possibly (at least some) a5xx variants have a
+ 2d core?
+ -->
+ </reg32>
+ <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
+ <reg32 offset="1" name="1">
+ <bitfield name="ADDR_0_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="ADDR_0_HI" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <!--
+ set when in GMEM.. maybe indicates GMEM contents need to be
+ preserved on ctx switch?
+ -->
+ <bitfield name="VSC_ENABLE" pos="3" type="boolean"/>
+ <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/>
+ </reg32>
+ <reg32 offset="4" name="4"/>
+ <!-- second buffer looks like some cmdstream.. length in dwords: -->
+ <reg32 offset="5" name="5">
+ <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="6" name="6">
+ <bitfield name="ADDR_1_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="7" name="7">
+ <bitfield name="ADDR_1_HI" low="0" high="31"/>
+ </reg32>
+</domain>
+
+<!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
+<domain name="CP_COMPUTE_CHECKPOINT" width="32">
+ <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
+ <reg32 offset="0" name="0">
+ <bitfield name="ADDR_0_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="ADDR_0_HI" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ </reg32>
+ <reg32 offset="3" name="3"/>
+ <!-- second buffer looks like some cmdstream.. length in dwords: -->
+ <reg32 offset="4" name="4">
+ <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="5" name="5">
+ <bitfield name="ADDR_1_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="6" name="6">
+ <bitfield name="ADDR_1_HI" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="7" name="7"/>
+</domain>
+
+<domain name="CP_PERFCOUNTER_ACTION" width="32">
+ <reg32 offset="0" name="0">
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="ADDR_0_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="ADDR_0_HI" low="0" high="31"/>
+ </reg32>
+</domain>
+
+<domain varset="chip" name="CP_EVENT_WRITE" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
+ <!-- when set, write back timestamp instead of value from packet: -->
+ <bitfield name="TIMESTAMP" pos="30" type="boolean"/>
+ <bitfield name="IRQ" pos="31" type="boolean"/>
+ </reg32>
+ <!--
+ TODO what is gpuaddr for, seems to be all 0's.. maybe needed for
+ context switch?
+ -->
+ <reg32 offset="1" name="1">
+ <bitfield name="ADDR_0_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="ADDR_0_HI" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <!-- ??? -->
+ </reg32>
+</domain>
+
+<domain varset="chip" name="CP_EVENT_WRITE7" width="32">
+ <enum name="event_write_src">
+ <!-- Write payload[0] -->
+ <value value="0" name="EV_WRITE_USER_32B"/>
+ <!-- Write payload[0] payload[1] -->
+ <value value="1" name="EV_WRITE_USER_64B"/>
+ <!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) -->
+ <value value="2" name="EV_WRITE_TIMESTAMP_SUM"/>
+ <value value="3" name="EV_WRITE_ALWAYSON"/>
+ <!-- Write payload[1] regs starting at payload[0] offset -->
+ <value value="4" name="EV_WRITE_REGS_CONTENT"/>
+ </enum>
+
+ <enum name="event_write_dst">
+ <value value="0" name="EV_DST_RAM"/>
+ <value value="1" name="EV_DST_ONCHIP"/>
+ </enum>
+
+ <reg32 offset="0" name="0">
+ <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
+ <bitfield name="WRITE_SAMPLE_COUNT" pos="12" type="boolean"/>
+ <!-- Write sample count at (iova + 16) -->
+ <bitfield name="SAMPLE_COUNT_END_OFFSET" pos="13" type="boolean"/>
+ <!-- *(iova + 8) = *(iova + 16) - *iova -->
+ <bitfield name="WRITE_SAMPLE_COUNT_DIFF" pos="14" type="boolean"/>
+
+ <!-- Next 4 flags are valid to set only when concurrent binning is enabled -->
+ <!-- Increment 16b BV counter. Valid only in BV pipe -->
+ <bitfield name="INC_BV_COUNT" pos="16" type="boolean"/>
+ <!-- Increment 16b BR counter. Valid only in BR pipe -->
+ <bitfield name="INC_BR_COUNT" pos="17" type="boolean"/>
+ <bitfield name="CLEAR_RENDER_RESOURCE" pos="18" type="boolean"/>
+ <bitfield name="CLEAR_LRZ_RESOURCE" pos="19" type="boolean"/>
+
+ <bitfield name="WRITE_SRC" low="20" high="22" type="event_write_src"/>
+ <bitfield name="WRITE_DST" pos="24" type="event_write_dst" addvariant="yes"/>
+ <!-- Writes into WRITE_DST from WRITE_SRC. RB_DONE_TS requires WRITE_ENABLED. -->
+ <bitfield name="WRITE_ENABLED" pos="27" type="boolean"/>
+ </reg32>
+
+ <stripe varset="event_write_dst" variants="EV_DST_RAM">
+ <reg32 offset="1" name="1">
+ <bitfield name="ADDR_0_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="ADDR_0_HI" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="PAYLOAD_0" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="4" name="4">
+ <bitfield name="PAYLOAD_1" low="0" high="31"/>
+ </reg32>
+ </stripe>
+
+ <stripe varset="event_write_dst" variants="EV_DST_ONCHIP">
+ <reg32 offset="1" name="1">
+ <bitfield name="ONCHIP_ADDR_0" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="PAYLOAD_0" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="4" name="4">
+ <bitfield name="PAYLOAD_1" low="0" high="31"/>
+ </reg32>
+ </stripe>
+</domain>
+
+<domain name="CP_BLIT" width="32">
+ <enum name="cp_blit_cmd">
+ <value value="0" name="BLIT_OP_FILL"/>
+ <value value="1" name="BLIT_OP_COPY"/>
+ <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="SRC_X1" low="0" high="13" type="uint"/>
+ <bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="SRC_X2" low="0" high="13" type="uint"/>
+ <bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="DST_X1" low="0" high="13" type="uint"/>
+ <bitfield name="DST_Y1" low="16" high="29" type="uint"/>
+ </reg32>
+ <reg32 offset="4" name="4">
+ <bitfield name="DST_X2" low="0" high="13" type="uint"/>
+ <bitfield name="DST_Y2" low="16" high="29" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="CP_EXEC_CS" width="32">
+ <reg32 offset="0" name="0">
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
+ <reg32 offset="0" name="0">
+ </reg32>
+ <stripe varset="chip" variants="A4XX">
+ <reg32 offset="1" name="1">
+ <bitfield name="ADDR" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <!-- localsize is value minus one: -->
+ <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
+ <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
+ <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
+ </reg32>
+ </stripe>
+ <stripe varset="chip" variants="A5XX-">
+ <reg32 offset="1" name="1">
+ <bitfield name="ADDR_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="ADDR_HI" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <!-- localsize is value minus one: -->
+ <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
+ <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
+ <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
+ </reg32>
+ </stripe>
+</domain>
+
+<domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
+ <doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
+ <enum name="a6xx_marker">
+ <value value="1" name="RM6_BYPASS"/>
+ <value value="2" name="RM6_BINNING"/>
+ <value value="4" name="RM6_GMEM"/>
+ <value value="5" name="RM6_ENDVIS"/>
+ <value value="6" name="RM6_RESOLVE"/>
+ <value value="7" name="RM6_YIELD"/>
+ <value value="8" name="RM6_COMPUTE"/>
+ <value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) -->
+
+ <!--
+ These values come from a6xx_set_marker() in the
+ downstream kernel, and they can only be set by the kernel
+ -->
+ <value value="0xd" name="RM6_IB1LIST_START"/>
+ <value value="0xe" name="RM6_IB1LIST_END"/>
+ <!-- IFPC - inter-frame power collapse -->
+ <value value="0x100" name="RM6_IFPC_ENABLE"/>
+ <value value="0x101" name="RM6_IFPC_DISABLE"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <!--
+ NOTE: blob driver and some versions of freedreno/turnip set
+ b4, which is unused (at least by current sqe fw), but interferes
+ with parsing if we extend the size of the bitfield to include
+ b8 (only sent by kernel mode driver). Really, the way the
+ parsing works in the firmware, only b0-b3 are considered, but
+ if b8 is set, the low bits are interpreted differently. To
+ model this, without getting confused by spurious b4, this is
+ described as two overlapping bitfields:
+ -->
+ <bitfield name="MODE" low="0" high="8" type="a6xx_marker"/>
+ <bitfield name="MARKER" low="0" high="3" type="a6xx_marker"/>
+ </reg32>
+</domain>
+
+<domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
+ <doc>Set internal CP registers, used to indicate context save data addresses</doc>
+ <enum name="pseudo_reg">
+ <value value="0" name="SMMU_INFO"/>
+ <value value="1" name="NON_SECURE_SAVE_ADDR"/>
+ <value value="2" name="SECURE_SAVE_ADDR"/>
+ <value value="3" name="NON_PRIV_SAVE_ADDR"/>
+ <value value="4" name="COUNTER"/>
+
+ <!--
+ On a6xx the registers are set directly and CP_SET_BIN_DATA5_OFFSET reads them,
+ but that doesn't work with concurrent binning because BR will be reading from
+ a different set of streams than BV is writing, so on a7xx we have these
+ pseudo-regs instead, which do the right thing.
+
+ The corresponding VSC registers exist, and they're written by BV when it
+ encounters CP_SET_PSEUDO_REG. When BR later encounters the same CP_SET_PSEUDO_REG
+ it will only write some private scratch registers which are read by
+ CP_SET_BIN_DATA5_OFFSET.
+
+ If concurrent binning is disabled then BR also does binning so it will also
+ write the "real" registers in BR.
+ -->
+ <value value="8" name="DRAW_STRM_ADDRESS"/>
+ <value value="9" name="DRAW_STRM_SIZE_ADDRESS"/>
+ <value value="10" name="PRIM_STRM_ADDRESS"/>
+ <value value="11" name="UNK_STRM_ADDRESS"/>
+ <value value="12" name="UNK_STRM_SIZE_ADDRESS"/>
+
+ <value value="16" name="BINDLESS_BASE_0_ADDR"/>
+ <value value="17" name="BINDLESS_BASE_1_ADDR"/>
+ <value value="18" name="BINDLESS_BASE_2_ADDR"/>
+ <value value="19" name="BINDLESS_BASE_3_ADDR"/>
+ <value value="20" name="BINDLESS_BASE_4_ADDR"/>
+ <value value="21" name="BINDLESS_BASE_5_ADDR"/>
+ <value value="22" name="BINDLESS_BASE_6_ADDR"/>
+ </enum>
+ <array offset="0" stride="3" length="100">
+ <reg32 offset="0" name="0">
+ <bitfield name="PSEUDO_REG" low="0" high="10" type="pseudo_reg"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="HI" low="0" high="31"/>
+ </reg32>
+ </array>
+</domain>
+
+<domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
+ <doc>
+ Tests bit in specified register and sets predicate for CP_COND_REG_EXEC.
+ So:
+
+ opcode: CP_REG_TEST (39) (2 dwords)
+ { REG = 0xc10 | BIT = 0 }
+ 0000: 70b90001 00000c10
+ opcode: CP_COND_REG_EXEC (47) (3 dwords)
+ 0000: 70c70002 10000000 00000004
+ opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
+
+ Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
+ offset 0x0c10 is 1
+ </doc>
+ <enum name="source_type">
+ <value value="0" name="SOURCE_REG"/>
+ <!-- Don't confuse with scratch registers, this is a separate memory
+ written into by CP_MEM_TO_SCRATCH_MEM. -->
+ <value value="1" name="SOURCE_SCRATCH_MEM" varset="chip" variants="A7XX-"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <!-- the register to test -->
+ <bitfield name="REG" low="0" high="17" varset="source_type" variants="SOURCE_REG"/>
+ <bitfield name="SCRATCH_MEM_OFFSET" low="0" high="17" varset="source_type" variants="SOURCE_SCRATCH_MEM"/>
+ <bitfield name="SOURCE" pos="18" type="source_type" addvariant="yes"/>
+ <!-- the bit to test -->
+ <bitfield name="BIT" low="20" high="24" type="uint"/>
+ <!-- skip implied CP_WAIT_FOR_ME -->
+ <bitfield name="SKIP_WAIT_FOR_ME" pos="25" type="boolean"/>
+ <!-- the predicate bit to set (new in gen3+) -->
+ <bitfield name="PRED_BIT" low="26" high="30" type="uint"/>
+ <!-- update the predicate reg directly (new in gen3+) -->
+ <bitfield name="PRED_UPDATE" pos="31" type="boolean"/>
+ </reg32>
+
+ <!--
+ In PRED_UPDATE mode, the predicate reg is updated directly using two
+ more dwords, ignoring other bits:
+
+ PRED_REG = (PRED_REG & ~PRED_MASK) | (PRED_VAL & PRED_MASK);
+ -->
+ <reg32 offset="1" name="PRED_MASK" type="hex"/>
+ <reg32 offset="2" name="PRED_VAL" type="hex"/>
+</domain>
+
+<!-- I *think* this existed at least as far back as a4xx -->
+<domain name="CP_COND_REG_EXEC" width="32">
+ <enum name="compare_mode">
+ <!-- use the predicate bit set by CP_REG_TEST -->
+ <value value="1" name="PRED_TEST"/>
+ <!-- compare two registers directly for equality -->
+ <value value="2" name="REG_COMPARE"/>
+ <!-- test if certain render modes are set via CP_SET_MARKER -->
+ <value value="3" name="RENDER_MODE" varset="chip" variants="A6XX-"/>
+ <!-- compare REG0 for equality with immediate -->
+ <value value="4" name="REG_COMPARE_IMM" varset="chip" variants="A7XX-"/>
+ <!-- test which of BR/BV are enabled -->
+ <value value="5" name="THREAD_MODE" varset="chip" variants="A7XX-"/>
+ </enum>
+ <reg32 offset="0" name="0" varset="compare_mode">
+ <bitfield name="REG0" low="0" high="17" variants="REG_COMPARE" type="hex"/>
+
+ <!-- the predicate bit to test (new in gen3+) -->
+ <bitfield name="PRED_BIT" low="18" high="22" variants="PRED_TEST" type="uint"/>
+ <bitfield name="SKIP_WAIT_FOR_ME" pos="23" varset="chip" variants="A7XX-" type="boolean"/>
+ <!-- With REG_COMPARE instead of register read from ONCHIP memory -->
+ <bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/>
+
+ <!--
+ Note: these bits have the same meaning, and use the same
+ internal mechanism as the bits in CP_SET_DRAW_STATE.
+ When RENDER_MODE is selected, they're used as
+ a bitmask of which modes pass the test.
+ -->
+
+ <!-- RM6_BINNING -->
+ <bitfield name="BINNING" pos="25" variants="RENDER_MODE" type="boolean"/>
+ <!-- all others -->
+ <bitfield name="GMEM" pos="26" variants="RENDER_MODE" type="boolean"/>
+ <!-- RM6_BYPASS -->
+ <bitfield name="SYSMEM" pos="27" variants="RENDER_MODE" type="boolean"/>
+
+ <bitfield name="BV" pos="25" variants="THREAD_MODE" type="boolean"/>
+ <bitfield name="BR" pos="26" variants="THREAD_MODE" type="boolean"/>
+ <bitfield name="LPAC" pos="27" variants="THREAD_MODE" type="boolean"/>
+
+ <bitfield name="MODE" low="28" high="31" type="compare_mode" addvariant="yes"/>
+ </reg32>
+
+ <stripe varset="compare_mode" variants="PRED_TEST">
+ <reg32 offset="1" name="1">
+ <bitfield name="DWORDS" low="0" high="23" type="uint"/>
+ </reg32>
+ </stripe>
+
+ <stripe varset="compare_mode" variants="REG_COMPARE">
+ <reg32 offset="1" name="1">
+ <bitfield name="REG1" low="0" high="17" type="hex"/>
+ <!-- Instead of register read from ONCHIP memory -->
+ <bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/>
+ </reg32>
+ </stripe>
+
+ <stripe varset="compare_mode" variants="RENDER_MODE">
+ <reg32 offset="1" name="1">
+ <bitfield name="DWORDS" low="0" high="23" type="uint"/>
+ </reg32>
+ </stripe>
+
+ <stripe varset="compare_mode" variants="REG_COMPARE_IMM">
+ <reg32 offset="1" name="1">
+ <bitfield name="IMM" low="0" high="31"/>
+ </reg32>
+ </stripe>
+
+ <stripe varset="compare_mode" variants="THREAD_MODE">
+ <reg32 offset="1" name="1">
+ <bitfield name="DWORDS" low="0" high="23" type="uint"/>
+ </reg32>
+ </stripe>
+
+ <reg32 offset="2" name="2">
+ <bitfield name="DWORDS" low="0" high="23" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="CP_COND_EXEC" width="32">
+ <doc>
+ Executes the following DWORDs of commands if the dword at ADDR0
+ is not equal to 0 and the dword at ADDR1 is less than REF
+ (signed comparison).
+ </doc>
+ <reg32 offset="0" name="0">
+ <bitfield name="ADDR0_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="ADDR0_HI" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="ADDR1_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="ADDR1_HI" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="4" name="4">
+ <bitfield name="REF" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="5" name="5">
+ <bitfield name="DWORDS" low="0" high="31" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="CP_SET_CTXSWITCH_IB" width="32">
+ <doc>
+ Used by the userspace driver to set various IB's which are
+ executed during context save/restore for handling
+ state that isn't restored by the
+ context switch routine itself.
+ </doc>
+ <enum name="ctxswitch_ib">
+ <value name="RESTORE_IB" value="0">
+ <doc>Executed unconditionally when switching back to the context.</doc>
+ </value>
+ <value name="YIELD_RESTORE_IB" value="1">
+ <doc>
+ Executed when switching back after switching
+ away during execution of
+ a CP_SET_MARKER packet with RM6_YIELD as the
+ payload *and* the normal save routine was
+ bypassed for a shorter one. I think this is
+ connected to the "skipsaverestore" bit set by
+ the kernel when preempting.
+ </doc>
+ </value>
+ <value name="SAVE_IB" value="2">
+ <doc>
+ Executed when switching away from the context,
+ except for context switches initiated via
+ CP_YIELD.
+ </doc>
+ </value>
+ <value name="RB_SAVE_IB" value="3">
+ <doc>
+ This can only be set by the RB (i.e. the kernel)
+ and executes with protected mode off, but
+ is otherwise similar to SAVE_IB.
+
+ Note, kgsl calls this CP_KMD_AMBLE_TYPE
+ </doc>
+ </value>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="ADDR_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="ADDR_HI" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="DWORDS" low="0" high="19" type="uint"/>
+ <bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/>
+ </reg32>
+</domain>
+
+<domain name="CP_REG_WRITE" width="32">
+ <enum name="reg_tracker">
+ <doc>
+ Keep shadow copies of these registers and only set them
+ when drawing, avoiding redundant writes:
+ - VPC_CNTL_0
+ - HLSQ_CONTROL_1_REG
+ - HLSQ_UNKNOWN_B980
+ </doc>
+ <value name="TRACK_CNTL_REG" value="0x1"/>
+ <doc>
+ Track RB_RENDER_CNTL, and insert a WFI in the following
+ situation:
+ - There is a write that disables binning
+ - There was a draw with binning left enabled, but in
+ BYPASS mode
+ Presumably this is a hang workaround?
+ </doc>
+ <value name="TRACK_RENDER_CNTL" value="0x2"/>
+ <doc>
+ Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of
+ the data to write is 0. Used by the Vulkan blob with
+ PC_MULTIVIEW_CNTL, but this isn't predicated on particular
+ register(s) like the others.
+ </doc>
+ <value name="UNK_EVENT_WRITE" value="0x4"/>
+ <doc>
+ Tracks GRAS_LRZ_CNTL::GREATER, GRAS_LRZ_CNTL::DIR, and
+ GRAS_LRZ_DEPTH_VIEW with previous values, and if one of
+ the following is true:
+ - GRAS_LRZ_CNTL::GREATER has changed
+ - GRAS_LRZ_CNTL::DIR has changed, the old value is not
+ CUR_DIR_GE, and the new value is not CUR_DIR_DISABLED
+ - GRAS_LRZ_DEPTH_VIEW has changed
+ then it does a LRZ_FLUSH with GRAS_LRZ_CNTL::ENABLE
+ forced to 1.
+ Only exists in a650_sqe.fw.
+ </doc>
+ <value name="TRACK_LRZ" value="0x8"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="TRACKER" low="0" high="3" type="reg_tracker"/>
+ </reg32>
+ <reg32 offset="1" name="1"/>
+ <reg32 offset="2" name="2"/>
+</domain>
+
+<domain name="CP_SMMU_TABLE_UPDATE" width="32">
+ <doc>
+ Note that the SMMU's definition of TTBRn can take different forms
+ depending on the pgtable format. But a5xx+ only uses aarch64
+ format.
+ </doc>
+ <reg32 offset="0" name="0">
+ <bitfield name="TTBR0_LO" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="TTBR0_HI" low="0" high="15"/>
+ <bitfield name="ASID" low="16" high="31"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <doc>Unused, does not apply to aarch64 pgtable format</doc>
+ <bitfield name="CONTEXTIDR" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="CONTEXTBANK" low="0" high="31"/>
+ </reg32>
+</domain>
+
+<domain name="CP_START_BIN" width="32">
+ <reg32 offset="0" name="BIN_COUNT" type="uint"/>
+ <reg64 offset="1" name="PREFIX_ADDR" type="address"/>
+ <reg32 offset="3" name="PREFIX_DWORDS">
+ <doc>
+ Size of prefix for each bin. For each bin index i, the
+ prefix commands at PREFIX_ADDR + i * PREFIX_DWORDS are
+ executed in an IB2 before the IB1 commands following
+ this packet.
+ </doc>
+ </reg32>
+ <reg32 offset="4" name="BODY_DWORDS">
+ <doc>Number of dwords after this packet until CP_END_BIN</doc>
+ </reg32>
+</domain>
+
+<domain name="CP_WAIT_TIMESTAMP" width="32">
+ <enum name="ts_wait_value_src">
+ <!-- Wait for value at memory address to be >= SRC_0 (signed comparison) -->
+ <value value="0" name="TS_WAIT_GE_32B"/>
+ <!-- Wait for value at memory address to be >= SRC_0 (unsigned) -->
+ <value value="1" name="TS_WAIT_GE_64B"/>
+ <!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) -->
+ <value value="2" name="TS_WAIT_GE_TIMESTAMP_SUM"/>
+ </enum>
+
+ <enum name="ts_wait_type">
+ <value value="0" name="TS_WAIT_RAM"/>
+ <value value="1" name="TS_WAIT_ONCHIP"/>
+ </enum>
+
+ <reg32 offset="0" name="0">
+ <bitfield name="WAIT_VALUE_SRC" low="0" high="1" type="ts_wait_value_src"/>
+ <bitfield name="WAIT_DST" pos="4" type="ts_wait_type" addvariant="yes"/>
+ </reg32>
+
+ <stripe varset="ts_wait_type" variants="TS_WAIT_RAM">
+ <reg64 offset="1" name="ADDR" type="address"/>
+ </stripe>
+
+ <stripe varset="ts_wait_type" variants="TS_WAIT_ONCHIP">
+ <reg32 offset="1" name="ONCHIP_ADDR_0" low="0" high="31"/>
+ </stripe>
+
+ <reg32 offset="3" name="SRC_0"/>
+ <reg32 offset="4" name="SRC_1"/>
+</domain>
+
+<domain name="CP_BV_BR_COUNT_OPS" width="32">
+ <enum name="pipe_count_op">
+ <value name="PIPE_CLEAR_BV_BR" value="0x1"/>
+ <value name="PIPE_SET_BR_OFFSET" value="0x2"/>
+ <!-- Wait until for BV_counter > BR_counter -->
+ <value name="PIPE_BR_WAIT_FOR_BV" value="0x3"/>
+ <!-- Wait until (BR_counter + BR_OFFSET) > BV_counter -->
+ <value name="PIPE_BV_WAIT_FOR_BR" value="0x4"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="OP" low="0" high="3" type="pipe_count_op"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <bitfield name="BR_OFFSET" low="0" high="15" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="CP_MODIFY_TIMESTAMP" width="32">
+ <enum name="timestamp_op">
+ <value name="MODIFY_TIMESTAMP_CLEAR" value="0"/>
+ <value name="MODIFY_TIMESTAMP_ADD_GLOBAL" value="1"/>
+ <value name="MODIFY_TIMESTAMP_ADD_LOCAL" value="2"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield name="ADD" low="0" high="7" type="uint"/>
+ <bitfield name="OP" low="28" high="31" type="timestamp_op"/>
+ </reg32>
+</domain>
+
+<domain name="CP_MEM_TO_SCRATCH_MEM" width="32">
+ <doc>
+ Best guess is that it is a faster way to fetch all the VSC_STATE registers
+ and keep them in a local scratch memory instead of fetching every time
+ when skipping IBs.
+ </doc>
+ <reg32 offset="0" name="0">
+ <bitfield name="CNT" low="0" high="5" type="uint"/>
+ </reg32>
+ <reg32 offset="1" name="1">
+ <doc>Scratch memory size is 48 dwords`</doc>
+ <bitfield name="OFFSET" low="0" high="5" type="uint"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="SRC" low="0" high="31"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="SRC_HI" low="0" high="31"/>
+ </reg32>
+</domain>
+
+<domain name="CP_THREAD_CONTROL" width="32">
+ <enum name="cp_thread">
+ <value name="CP_SET_THREAD_BR" value="1"/> <!-- Render -->
+ <value name="CP_SET_THREAD_BV" value="2"/> <!-- Visibility -->
+ <value name="CP_SET_THREAD_BOTH" value="3"/>
+ </enum>
+ <reg32 offset="0" name="0">
+ <bitfield low="0" high="1" name="THREAD" type="cp_thread"/>
+ <bitfield pos="27" name="CONCURRENT_BIN_DISABLE" type="boolean"/>
+ <bitfield pos="31" name="SYNC_THREADS" type="boolean"/>
+ </reg32>
+</domain>
+
+<domain name="CP_FIXED_STRIDE_DRAW_TABLE" width="32">
+ <reg64 offset="0" name="IB_BASE"/>
+ <reg32 offset="2" name="2">
+ <!-- STRIDE * COUNT -->
+ <bitfield name="IB_SIZE" low="0" high="11"/>
+ <bitfield name="STRIDE" low="20" high="31"/>
+ </reg32>
+ <reg32 offset="3" name="3">
+ <bitfield name="COUNT" low="0" high="31"/>
+ </reg32>
+</domain>
+
+<domain name="CP_RESET_CONTEXT_STATE" width="32">
+ <reg32 offset="0" name="0">
+ <bitfield name="CLEAR_ON_CHIP_TS" pos="0" type="boolean"/>
+ <bitfield name="CLEAR_RESOURCE_TABLE" pos="1" type="boolean"/>
+ <bitfield name="CLEAR_GLOBAL_LOCAL_TS" pos="2" type="boolean"/>
+ </reg32>
+</domain>
+
+</database>
+
diff --git a/drivers/gpu/drm/msm/registers/display/dsi.xml b/drivers/gpu/drm/msm/registers/display/dsi.xml
new file mode 100644
index 000000000000..501ffc585a9f
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/display/dsi.xml
@@ -0,0 +1,390 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+
+<domain name="DSI" width="32">
+ <enum name="dsi_traffic_mode">
+ <value name="NON_BURST_SYNCH_PULSE" value="0"/>
+ <value name="NON_BURST_SYNCH_EVENT" value="1"/>
+ <value name="BURST_MODE" value="2"/>
+ </enum>
+ <enum name="dsi_vid_dst_format">
+ <value name="VID_DST_FORMAT_RGB565" value="0"/>
+ <value name="VID_DST_FORMAT_RGB666" value="1"/>
+ <value name="VID_DST_FORMAT_RGB666_LOOSE" value="2"/>
+ <value name="VID_DST_FORMAT_RGB888" value="3"/>
+ </enum>
+ <enum name="dsi_rgb_swap">
+ <value name="SWAP_RGB" value="0"/>
+ <value name="SWAP_RBG" value="1"/>
+ <value name="SWAP_BGR" value="2"/>
+ <value name="SWAP_BRG" value="3"/>
+ <value name="SWAP_GRB" value="4"/>
+ <value name="SWAP_GBR" value="5"/>
+ </enum>
+ <enum name="dsi_cmd_trigger">
+ <value name="TRIGGER_NONE" value="0"/>
+ <value name="TRIGGER_SEOF" value="1"/>
+ <value name="TRIGGER_TE" value="2"/>
+ <value name="TRIGGER_SW" value="4"/>
+ <value name="TRIGGER_SW_SEOF" value="5"/>
+ <value name="TRIGGER_SW_TE" value="6"/>
+ </enum>
+ <enum name="dsi_cmd_dst_format">
+ <value name="CMD_DST_FORMAT_RGB111" value="0"/>
+ <value name="CMD_DST_FORMAT_RGB332" value="3"/>
+ <value name="CMD_DST_FORMAT_RGB444" value="4"/>
+ <value name="CMD_DST_FORMAT_RGB565" value="6"/>
+ <value name="CMD_DST_FORMAT_RGB666" value="7"/>
+ <value name="CMD_DST_FORMAT_RGB888" value="8"/>
+ </enum>
+ <enum name="dsi_lane_swap">
+ <value name="LANE_SWAP_0123" value="0"/>
+ <value name="LANE_SWAP_3012" value="1"/>
+ <value name="LANE_SWAP_2301" value="2"/>
+ <value name="LANE_SWAP_1230" value="3"/>
+ <value name="LANE_SWAP_0321" value="4"/>
+ <value name="LANE_SWAP_1032" value="5"/>
+ <value name="LANE_SWAP_2103" value="6"/>
+ <value name="LANE_SWAP_3210" value="7"/>
+ </enum>
+ <enum name="video_config_bpp">
+ <value name="VIDEO_CONFIG_18BPP" value="0"/>
+ <value name="VIDEO_CONFIG_24BPP" value="1"/>
+ </enum>
+ <enum name="video_pattern_sel">
+ <value name="VID_PRBS" value="0"/>
+ <value name="VID_INCREMENTAL" value="1"/>
+ <value name="VID_FIXED" value="2"/>
+ <value name="VID_MDSS_GENERAL_PATTERN" value="3"/>
+ </enum>
+ <enum name="cmd_mdp_stream0_pattern_sel">
+ <value name="CMD_MDP_PRBS" value="0"/>
+ <value name="CMD_MDP_INCREMENTAL" value="1"/>
+ <value name="CMD_MDP_FIXED" value="2"/>
+ <value name="CMD_MDP_MDSS_GENERAL_PATTERN" value="3"/>
+ </enum>
+ <enum name="cmd_dma_pattern_sel">
+ <value name="CMD_DMA_PRBS" value="0"/>
+ <value name="CMD_DMA_INCREMENTAL" value="1"/>
+ <value name="CMD_DMA_FIXED" value="2"/>
+ <value name="CMD_DMA_CUSTOM_PATTERN_DMA_FIFO" value="3"/>
+ </enum>
+ <bitset name="DSI_IRQ">
+ <bitfield name="CMD_DMA_DONE" pos="0" type="boolean"/>
+ <bitfield name="MASK_CMD_DMA_DONE" pos="1" type="boolean"/>
+ <bitfield name="CMD_MDP_DONE" pos="8" type="boolean"/>
+ <bitfield name="MASK_CMD_MDP_DONE" pos="9" type="boolean"/>
+ <bitfield name="VIDEO_DONE" pos="16" type="boolean"/>
+ <bitfield name="MASK_VIDEO_DONE" pos="17" type="boolean"/>
+ <bitfield name="BTA_DONE" pos="20" type="boolean"/>
+ <bitfield name="MASK_BTA_DONE" pos="21" type="boolean"/>
+ <bitfield name="ERROR" pos="24" type="boolean"/>
+ <bitfield name="MASK_ERROR" pos="25" type="boolean"/>
+ </bitset>
+
+ <reg32 offset="0x00000" name="6G_HW_VERSION">
+ <bitfield name="MAJOR" low="28" high="31" type="uint"/>
+ <bitfield name="MINOR" low="16" high="27" type="uint"/>
+ <bitfield name="STEP" low="0" high="15" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x00000" name="CTRL">
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ <bitfield name="VID_MODE_EN" pos="1" type="boolean"/>
+ <bitfield name="CMD_MODE_EN" pos="2" type="boolean"/>
+ <bitfield name="LANE0" pos="4" type="boolean"/>
+ <bitfield name="LANE1" pos="5" type="boolean"/>
+ <bitfield name="LANE2" pos="6" type="boolean"/>
+ <bitfield name="LANE3" pos="7" type="boolean"/>
+ <bitfield name="CLK_EN" pos="8" type="boolean"/>
+ <bitfield name="ECC_CHECK" pos="20" type="boolean"/>
+ <bitfield name="CRC_CHECK" pos="24" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x00004" name="STATUS0">
+ <bitfield name="CMD_MODE_ENGINE_BUSY" pos="0" type="boolean"/>
+ <bitfield name="CMD_MODE_DMA_BUSY" pos="1" type="boolean"/>
+ <bitfield name="CMD_MODE_MDP_BUSY" pos="2" type="boolean"/>
+ <bitfield name="VIDEO_MODE_ENGINE_BUSY" pos="3" type="boolean"/>
+ <bitfield name="DSI_BUSY" pos="4" type="boolean"/> <!-- see mipi_dsi_cmd_bta_sw_trigger() -->
+ <bitfield name="INTERLEAVE_OP_CONTENTION" pos="31" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x00008" name="FIFO_STATUS">
+ <bitfield name="VIDEO_MDP_FIFO_OVERFLOW" pos="0" type="boolean"/>
+ <bitfield name="VIDEO_MDP_FIFO_UNDERFLOW" pos="3" type="boolean"/>
+ <bitfield name="CMD_MDP_FIFO_UNDERFLOW" pos="7" type="boolean"/>
+ <bitfield name="CMD_DMA_FIFO_RD_WATERMARK_REACH" pos="8" type="boolean"/>
+ <bitfield name="CMD_DMA_FIFO_WR_WATERMARK_REACH" pos="9" type="boolean"/>
+ <bitfield name="CMD_DMA_FIFO_UNDERFLOW" pos="10" type="boolean"/>
+ <bitfield name="DLN0_LP_FIFO_EMPTY" pos="12" type="boolean"/>
+ <bitfield name="DLN0_LP_FIFO_FULL" pos="13" type="boolean"/>
+ <bitfield name="DLN0_LP_FIFO_OVERFLOW" pos="14" type="boolean"/>
+ <bitfield name="DLN0_HS_FIFO_EMPTY" pos="16" type="boolean"/>
+ <bitfield name="DLN0_HS_FIFO_FULL" pos="17" type="boolean"/>
+ <bitfield name="DLN0_HS_FIFO_OVERFLOW" pos="18" type="boolean"/>
+ <bitfield name="DLN0_HS_FIFO_UNDERFLOW" pos="19" type="boolean"/>
+ <bitfield name="DLN1_HS_FIFO_EMPTY" pos="20" type="boolean"/>
+ <bitfield name="DLN1_HS_FIFO_FULL" pos="21" type="boolean"/>
+ <bitfield name="DLN1_HS_FIFO_OVERFLOW" pos="22" type="boolean"/>
+ <bitfield name="DLN1_HS_FIFO_UNDERFLOW" pos="23" type="boolean"/>
+ <bitfield name="DLN2_HS_FIFO_EMPTY" pos="24" type="boolean"/>
+ <bitfield name="DLN2_HS_FIFO_FULL" pos="25" type="boolean"/>
+ <bitfield name="DLN2_HS_FIFO_OVERFLOW" pos="26" type="boolean"/>
+ <bitfield name="DLN2_HS_FIFO_UNDERFLOW" pos="27" type="boolean"/>
+ <bitfield name="DLN3_HS_FIFO_EMPTY" pos="28" type="boolean"/>
+ <bitfield name="DLN3_HS_FIFO_FULL" pos="29" type="boolean"/>
+ <bitfield name="DLN3_HS_FIFO_OVERFLOW" pos="30" type="boolean"/>
+ <bitfield name="DLN3_HS_FIFO_UNDERFLOW" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0000c" name="VID_CFG0">
+ <bitfield name="VIRT_CHANNEL" low="0" high="1" type="uint"/> <!-- always zero? -->
+ <bitfield name="DST_FORMAT" low="4" high="5" type="dsi_vid_dst_format"/>
+ <bitfield name="TRAFFIC_MODE" low="8" high="9" type="dsi_traffic_mode"/>
+ <bitfield name="BLLP_POWER_STOP" pos="12" type="boolean"/>
+ <bitfield name="EOF_BLLP_POWER_STOP" pos="15" type="boolean"/>
+ <bitfield name="HSA_POWER_STOP" pos="16" type="boolean"/>
+ <bitfield name="HBP_POWER_STOP" pos="20" type="boolean"/>
+ <bitfield name="HFP_POWER_STOP" pos="24" type="boolean"/>
+ <bitfield name="DATABUS_WIDEN" pos="25" type="boolean"/>
+ <bitfield name="PULSE_MODE_HSA_HE" pos="28" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0001c" name="VID_CFG1">
+ <bitfield name="R_SEL" pos="0" type="boolean"/>
+ <bitfield name="G_SEL" pos="4" type="boolean"/>
+ <bitfield name="B_SEL" pos="8" type="boolean"/>
+ <bitfield name="RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/>
+ </reg32>
+ <reg32 offset="0x00020" name="ACTIVE_H">
+ <bitfield name="START" low="0" high="11" type="uint"/>
+ <bitfield name="END" low="16" high="27" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00024" name="ACTIVE_V">
+ <bitfield name="START" low="0" high="11" type="uint"/>
+ <bitfield name="END" low="16" high="27" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00028" name="TOTAL">
+ <bitfield name="H_TOTAL" low="0" high="11" type="uint"/>
+ <bitfield name="V_TOTAL" low="16" high="27" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0002c" name="ACTIVE_HSYNC">
+ <bitfield name="START" low="0" high="11" type="uint"/>
+ <bitfield name="END" low="16" high="27" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00030" name="ACTIVE_VSYNC_HPOS">
+ <bitfield name="START" low="0" high="11" type="uint"/>
+ <bitfield name="END" low="16" high="27" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00034" name="ACTIVE_VSYNC_VPOS">
+ <bitfield name="START" low="0" high="11" type="uint"/>
+ <bitfield name="END" low="16" high="27" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x00038" name="CMD_DMA_CTRL">
+ <bitfield name="BROADCAST_EN" pos="31" type="boolean"/>
+ <bitfield name="FROM_FRAME_BUFFER" pos="28" type="boolean"/>
+ <bitfield name="LOW_POWER" pos="26" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0003c" name="CMD_CFG0">
+ <bitfield name="DST_FORMAT" low="0" high="3" type="dsi_cmd_dst_format"/>
+ <bitfield name="R_SEL" pos="4" type="boolean"/>
+ <bitfield name="G_SEL" pos="8" type="boolean"/>
+ <bitfield name="B_SEL" pos="12" type="boolean"/>
+ <bitfield name="INTERLEAVE_MAX" low="20" high="23" type="uint"/>
+ <bitfield name="RGB_SWAP" low="16" high="18" type="dsi_rgb_swap"/>
+ </reg32>
+ <reg32 offset="0x00040" name="CMD_CFG1">
+ <bitfield name="WR_MEM_START" low="0" high="7" type="uint"/>
+ <bitfield name="WR_MEM_CONTINUE" low="8" high="15" type="uint"/>
+ <bitfield name="INSERT_DCS_COMMAND" pos="16" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00044" name="DMA_BASE"/>
+ <reg32 offset="0x00048" name="DMA_LEN"/>
+ <reg32 offset="0x00054" name="CMD_MDP_STREAM0_CTRL">
+ <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
+ <bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>
+ <bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00058" name="CMD_MDP_STREAM0_TOTAL">
+ <bitfield name="H_TOTAL" low="0" high="11" type="uint"/>
+ <bitfield name="V_TOTAL" low="16" high="27" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0005c" name="CMD_MDP_STREAM1_CTRL">
+ <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
+ <bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>
+ <bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00060" name="CMD_MDP_STREAM1_TOTAL">
+ <bitfield name="H_TOTAL" low="0" high="15" type="uint"/>
+ <bitfield name="V_TOTAL" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00064" name="ACK_ERR_STATUS"/>
+ <array offset="0x00068" name="RDBK" length="4" stride="4">
+ <reg32 offset="0x0" name="DATA"/>
+ </array>
+ <reg32 offset="0x00080" name="TRIG_CTRL">
+ <bitfield name="DMA_TRIGGER" low="0" high="2" type="dsi_cmd_trigger"/>
+ <bitfield name="MDP_TRIGGER" low="4" high="6" type="dsi_cmd_trigger"/>
+ <bitfield name="STREAM" low="8" high="9" type="uint"/>
+ <bitfield name="BLOCK_DMA_WITHIN_FRAME" pos="12" type="boolean"/>
+ <bitfield name="TE" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0008c" name="TRIG_DMA"/>
+ <reg32 offset="0x000b0" name="DLN0_PHY_ERR">
+ <bitfield name="DLN0_ERR_ESC" pos="0" type="boolean"/>
+ <bitfield name="DLN0_ERR_SYNC_ESC" pos="4" type="boolean"/>
+ <bitfield name="DLN0_ERR_CONTROL" pos="8" type="boolean"/>
+ <bitfield name="DLN0_ERR_CONTENTION_LP0" pos="12" type="boolean"/>
+ <bitfield name="DLN0_ERR_CONTENTION_LP1" pos="16" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x000b4" name="LP_TIMER_CTRL">
+ <bitfield name="LP_RX_TO" low="0" high="15" type="uint"/>
+ <bitfield name="BTA_TO" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x000b8" name="HS_TIMER_CTRL">
+ <bitfield name="HS_TX_TO" low="0" high="15" type="uint"/>
+ <bitfield name="TIMER_RESOLUTION" low="16" high="19" type="uint"/>
+ <bitfield name="HS_TX_TO_STOP_EN" pos="28" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x000bc" name="TIMEOUT_STATUS"/>
+ <reg32 offset="0x000c0" name="CLKOUT_TIMING_CTRL">
+ <bitfield name="T_CLK_PRE" low="0" high="5" type="uint"/>
+ <bitfield name="T_CLK_POST" low="8" high="13" type="uint"/>
+ </reg32>
+ <reg32 offset="0x000c8" name="EOT_PACKET_CTRL">
+ <bitfield name="TX_EOT_APPEND" pos="0" type="boolean"/>
+ <bitfield name="RX_EOT_IGNORE" pos="4" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x000a4" name="LANE_STATUS">
+ <bitfield name="DLN0_STOPSTATE" pos="0" type="boolean"/>
+ <bitfield name="DLN1_STOPSTATE" pos="1" type="boolean"/>
+ <bitfield name="DLN2_STOPSTATE" pos="2" type="boolean"/>
+ <bitfield name="DLN3_STOPSTATE" pos="3" type="boolean"/>
+ <bitfield name="CLKLN_STOPSTATE" pos="4" type="boolean"/>
+ <bitfield name="DLN0_ULPS_ACTIVE_NOT" pos="8" type="boolean"/>
+ <bitfield name="DLN1_ULPS_ACTIVE_NOT" pos="9" type="boolean"/>
+ <bitfield name="DLN2_ULPS_ACTIVE_NOT" pos="10" type="boolean"/>
+ <bitfield name="DLN3_ULPS_ACTIVE_NOT" pos="11" type="boolean"/>
+ <bitfield name="CLKLN_ULPS_ACTIVE_NOT" pos="12" type="boolean"/>
+ <bitfield name="DLN0_DIRECTION" pos="16" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x000a8" name="LANE_CTRL">
+ <bitfield name="HS_REQ_SEL_PHY" pos="24" type="boolean"/>
+ <bitfield name="CLKLN_HS_FORCE_REQUEST" pos="28" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x000ac" name="LANE_SWAP_CTRL">
+ <bitfield name="DLN_SWAP_SEL" low="0" high="2" type="dsi_lane_swap"/>
+ </reg32>
+ <reg32 offset="0x00108" name="ERR_INT_MASK0"/>
+ <reg32 offset="0x0010c" name="INTR_CTRL" type="DSI_IRQ"/>
+ <reg32 offset="0x00114" name="RESET"/>
+ <reg32 offset="0x00118" name="CLK_CTRL">
+ <bitfield name="AHBS_HCLK_ON" pos="0" type="boolean"/>
+ <bitfield name="AHBM_SCLK_ON" pos="1" type="boolean"/>
+ <bitfield name="PCLK_ON" pos="2" type="boolean"/>
+ <bitfield name="DSICLK_ON" pos="3" type="boolean"/>
+ <bitfield name="BYTECLK_ON" pos="4" type="boolean"/>
+ <bitfield name="ESCCLK_ON" pos="5" type="boolean"/>
+ <bitfield name="FORCE_ON_DYN_AHBM_HCLK" pos="9" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0011c" name="CLK_STATUS">
+ <bitfield name="DSI_AON_AHBM_HCLK_ACTIVE" pos="0" type="boolean"/>
+ <bitfield name="DSI_DYN_AHBM_HCLK_ACTIVE" pos="1" type="boolean"/>
+ <bitfield name="DSI_AON_AHBS_HCLK_ACTIVE" pos="2" type="boolean"/>
+ <bitfield name="DSI_DYN_AHBS_HCLK_ACTIVE" pos="3" type="boolean"/>
+ <bitfield name="DSI_AON_DSICLK_ACTIVE" pos="4" type="boolean"/>
+ <bitfield name="DSI_DYN_DSICLK_ACTIVE" pos="5" type="boolean"/>
+ <bitfield name="DSI_AON_BYTECLK_ACTIVE" pos="6" type="boolean"/>
+ <bitfield name="DSI_DYN_BYTECLK_ACTIVE" pos="7" type="boolean"/>
+ <bitfield name="DSI_AON_ESCCLK_ACTIVE" pos="8" type="boolean"/>
+ <bitfield name="DSI_AON_PCLK_ACTIVE" pos="9" type="boolean"/>
+ <bitfield name="DSI_DYN_PCLK_ACTIVE" pos="10" type="boolean"/>
+ <bitfield name="DSI_DYN_CMD_PCLK_ACTIVE" pos="12" type="boolean"/>
+ <bitfield name="DSI_CMD_PCLK_ACTIVE" pos="13" type="boolean"/>
+ <bitfield name="DSI_VID_PCLK_ACTIVE" pos="14" type="boolean"/>
+ <bitfield name="DSI_CAM_BIST_PCLK_ACT" pos="15" type="boolean"/>
+ <bitfield name="PLL_UNLOCKED" pos="16" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00128" name="PHY_RESET">
+ <bitfield name="RESET" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00160" name="TEST_PATTERN_GEN_VIDEO_INIT_VAL"/>
+ <reg32 offset="0x00198" name="TPG_MAIN_CONTROL">
+ <bitfield name="CHECKERED_RECTANGLE_PATTERN" pos="8" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x001a0" name="TPG_VIDEO_CONFIG">
+ <bitfield name="BPP" low="0" high="1" type="video_config_bpp"/>
+ <bitfield name="RGB" pos="2" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00158" name="TEST_PATTERN_GEN_CTRL">
+ <bitfield name="CMD_DMA_PATTERN_SEL" low="16" high="17" type="cmd_dma_pattern_sel"/>
+ <bitfield name="CMD_MDP_STREAM0_PATTERN_SEL" low="8" high="9" type="cmd_mdp_stream0_pattern_sel"/>
+ <bitfield name="VIDEO_PATTERN_SEL" low="4" high="5" type="video_pattern_sel"/>
+ <bitfield name="TPG_DMA_FIFO_MODE" pos="2" type="boolean"/>
+ <bitfield name="CMD_DMA_TPG_EN" pos="1" type="boolean"/>
+ <bitfield name="EN" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00168" name="TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0"/>
+ <reg32 offset="0x00180" name="TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER">
+ <bitfield name="SW_TRIGGER" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0019c" name="TPG_MAIN_CONTROL2">
+ <bitfield name="CMD_MDP0_CHECKERED_RECTANGLE_PATTERN" pos="7" type="boolean"/>
+ <bitfield name="CMD_MDP1_CHECKERED_RECTANGLE_PATTERN" pos="16" type="boolean"/>
+ <bitfield name="CMD_MDP2_CHECKERED_RECTANGLE_PATTERN" pos="25" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0017c" name="T_CLK_PRE_EXTEND">
+ <bitfield name="INC_BY_2_BYTECLK" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x001b4" name="CMD_MODE_MDP_CTRL2">
+ <bitfield name="DST_FORMAT2" low="0" high="3" type="dsi_cmd_dst_format"/>
+ <bitfield name="R_SEL" pos="4" type="boolean"/>
+ <bitfield name="G_SEL" pos="5" type="boolean"/>
+ <bitfield name="B_SEL" pos="6" type="boolean"/>
+ <bitfield name="BYTE_MSB_LSB_FLIP" pos="7" type="boolean"/>
+ <bitfield name="RGB_SWAP" low="8" high="10" type="dsi_rgb_swap"/>
+ <bitfield name="INPUT_RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/>
+ <bitfield name="BURST_MODE" pos="16" type="boolean"/>
+ <bitfield name="DATABUS_WIDEN" pos="20" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x001b8" name="CMD_MODE_MDP_STREAM2_CTRL">
+ <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
+ <bitfield name="VIRTUAL_CHANNEL" low="8" high="9" type="uint"/>
+ <bitfield name="WORD_COUNT" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x001d0" name="RDBK_DATA_CTRL">
+ <bitfield name="COUNT" low="16" high="23" type="uint"/>
+ <bitfield name="CLR" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x001f0" name="VERSION">
+ <bitfield name="MAJOR" low="24" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x002d4" name="CPHY_MODE_CTRL"/>
+ <reg32 offset="0x0029c" name="VIDEO_COMPRESSION_MODE_CTRL">
+ <bitfield name="WC" low="16" high="31" type="uint"/>
+ <bitfield name="DATATYPE" low="8" high="13" type="uint"/>
+ <bitfield name="PKT_PER_LINE" low="6" high="7" type="uint"/>
+ <bitfield name="EOL_BYTE_NUM" low="4" high="5" type="uint"/>
+ <bitfield name="EN" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x002a4" name="COMMAND_COMPRESSION_MODE_CTRL">
+ <bitfield name="STREAM1_DATATYPE" low="24" high="29" type="uint"/>
+ <bitfield name="STREAM1_PKT_PER_LINE" low="22" high="23" type="uint"/>
+ <bitfield name="STREAM1_EOL_BYTE_NUM" low="20" high="21" type="uint"/>
+ <bitfield name="STREAM1_EN" pos="16" type="boolean"/>
+ <bitfield name="STREAM0_DATATYPE" low="8" high="13" type="uint"/>
+ <bitfield name="STREAM0_PKT_PER_LINE" low="6" high="7" type="uint"/>
+ <bitfield name="STREAM0_EOL_BYTE_NUM" low="4" high="5" type="uint"/>
+ <bitfield name="STREAM0_EN" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x002a8" name="COMMAND_COMPRESSION_MODE_CTRL2">
+ <bitfield name="STREAM1_SLICE_WIDTH" low="16" high="31" type="uint"/>
+ <bitfield name="STREAM0_SLICE_WIDTH" low="0" high="15" type="uint"/>
+ </reg32>
+
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_10nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_10nm.xml
new file mode 100644
index 000000000000..874c3db3e126
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_10nm.xml
@@ -0,0 +1,102 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+
+<domain name="DSI_10nm_PHY_CMN" width="32">
+ <reg32 offset="0x00000" name="REVISION_ID0"/>
+ <reg32 offset="0x00004" name="REVISION_ID1"/>
+ <reg32 offset="0x00008" name="REVISION_ID2"/>
+ <reg32 offset="0x0000c" name="REVISION_ID3"/>
+ <reg32 offset="0x00010" name="CLK_CFG0"/>
+ <reg32 offset="0x00014" name="CLK_CFG1"/>
+ <reg32 offset="0x00018" name="GLBL_CTRL"/>
+ <reg32 offset="0x0001c" name="RBUF_CTRL"/>
+ <reg32 offset="0x00020" name="VREG_CTRL"/>
+ <reg32 offset="0x00024" name="CTRL_0"/>
+ <reg32 offset="0x00028" name="CTRL_1"/>
+ <reg32 offset="0x0002c" name="CTRL_2"/>
+ <reg32 offset="0x00030" name="LANE_CFG0"/>
+ <reg32 offset="0x00034" name="LANE_CFG1"/>
+ <reg32 offset="0x00038" name="PLL_CNTRL"/>
+ <reg32 offset="0x00098" name="LANE_CTRL0"/>
+ <reg32 offset="0x0009c" name="LANE_CTRL1"/>
+ <reg32 offset="0x000a0" name="LANE_CTRL2"/>
+ <reg32 offset="0x000a4" name="LANE_CTRL3"/>
+ <reg32 offset="0x000a8" name="LANE_CTRL4"/>
+ <reg32 offset="0x000ac" name="TIMING_CTRL_0"/>
+ <reg32 offset="0x000b0" name="TIMING_CTRL_1"/>
+ <reg32 offset="0x000b4" name="TIMING_CTRL_2"/>
+ <reg32 offset="0x000b8" name="TIMING_CTRL_3"/>
+ <reg32 offset="0x000bc" name="TIMING_CTRL_4"/>
+ <reg32 offset="0x000c0" name="TIMING_CTRL_5"/>
+ <reg32 offset="0x000c4" name="TIMING_CTRL_6"/>
+ <reg32 offset="0x000c8" name="TIMING_CTRL_7"/>
+ <reg32 offset="0x000cc" name="TIMING_CTRL_8"/>
+ <reg32 offset="0x000d0" name="TIMING_CTRL_9"/>
+ <reg32 offset="0x000d4" name="TIMING_CTRL_10"/>
+ <reg32 offset="0x000d8" name="TIMING_CTRL_11"/>
+ <reg32 offset="0x000ec" name="PHY_STATUS"/>
+ <reg32 offset="0x000f4" name="LANE_STATUS0"/>
+ <reg32 offset="0x000f8" name="LANE_STATUS1"/>
+</domain>
+
+<domain name="DSI_10nm_PHY" width="32">
+ <array offset="0x00000" name="LN" length="5" stride="0x80">
+ <reg32 offset="0x00" name="CFG0"/>
+ <reg32 offset="0x04" name="CFG1"/>
+ <reg32 offset="0x08" name="CFG2"/>
+ <reg32 offset="0x0c" name="CFG3"/>
+ <reg32 offset="0x10" name="TEST_DATAPATH"/>
+ <reg32 offset="0x14" name="PIN_SWAP"/>
+ <reg32 offset="0x18" name="HSTX_STR_CTRL"/>
+ <reg32 offset="0x1c" name="OFFSET_TOP_CTRL"/>
+ <reg32 offset="0x20" name="OFFSET_BOT_CTRL"/>
+ <reg32 offset="0x24" name="LPTX_STR_CTRL"/>
+ <reg32 offset="0x28" name="LPRX_CTRL"/>
+ <reg32 offset="0x2c" name="TX_DCTRL"/>
+ </array>
+</domain>
+
+<domain name="DSI_10nm_PHY_PLL" width="32">
+ <reg32 offset="0x0000" name="ANALOG_CONTROLS_ONE"/>
+ <reg32 offset="0x0004" name="ANALOG_CONTROLS_TWO"/>
+ <reg32 offset="0x0010" name="ANALOG_CONTROLS_THREE"/>
+ <reg32 offset="0x001c" name="DSM_DIVIDER"/>
+ <reg32 offset="0x0020" name="FEEDBACK_DIVIDER"/>
+ <reg32 offset="0x0024" name="SYSTEM_MUXES"/>
+ <reg32 offset="0x002c" name="CMODE"/>
+ <reg32 offset="0x0030" name="CALIBRATION_SETTINGS"/>
+ <reg32 offset="0x0054" name="BAND_SEL_CAL_SETTINGS_THREE"/>
+ <reg32 offset="0x0064" name="FREQ_DETECT_SETTINGS_ONE"/>
+ <reg32 offset="0x007c" name="PFILT"/>
+ <reg32 offset="0x0080" name="IFILT"/>
+ <reg32 offset="0x0094" name="OUTDIV"/>
+ <reg32 offset="0x00a4" name="CORE_OVERRIDE"/>
+ <reg32 offset="0x00a8" name="CORE_INPUT_OVERRIDE"/>
+ <reg32 offset="0x00b4" name="PLL_DIGITAL_TIMERS_TWO"/>
+ <reg32 offset="0x00cc" name="DECIMAL_DIV_START_1"/>
+ <reg32 offset="0x00d0" name="FRAC_DIV_START_LOW_1"/>
+ <reg32 offset="0x00d4" name="FRAC_DIV_START_MID_1"/>
+ <reg32 offset="0x00d8" name="FRAC_DIV_START_HIGH_1"/>
+ <reg32 offset="0x010c" name="SSC_STEPSIZE_LOW_1"/>
+ <reg32 offset="0x0110" name="SSC_STEPSIZE_HIGH_1"/>
+ <reg32 offset="0x0114" name="SSC_DIV_PER_LOW_1"/>
+ <reg32 offset="0x0118" name="SSC_DIV_PER_HIGH_1"/>
+ <reg32 offset="0x011c" name="SSC_DIV_ADJPER_LOW_1"/>
+ <reg32 offset="0x0120" name="SSC_DIV_ADJPER_HIGH_1"/>
+ <reg32 offset="0x013c" name="SSC_CONTROL"/>
+ <reg32 offset="0x0140" name="PLL_OUTDIV_RATE"/>
+ <reg32 offset="0x0144" name="PLL_LOCKDET_RATE_1"/>
+ <reg32 offset="0x014c" name="PLL_PROP_GAIN_RATE_1"/>
+ <reg32 offset="0x0154" name="PLL_BAND_SET_RATE_1"/>
+ <reg32 offset="0x015c" name="PLL_INT_GAIN_IFILT_BAND_1"/>
+ <reg32 offset="0x0164" name="PLL_FL_INT_GAIN_PFILT_BAND_1"/>
+ <reg32 offset="0x0180" name="PLL_LOCK_OVERRIDE"/>
+ <reg32 offset="0x0184" name="PLL_LOCK_DELAY"/>
+ <reg32 offset="0x018c" name="CLOCK_INVERTERS"/>
+ <reg32 offset="0x01a0" name="COMMON_STATUS_ONE"/>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_14nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_14nm.xml
new file mode 100644
index 000000000000..314b74489d49
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_14nm.xml
@@ -0,0 +1,135 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+
+<domain name="DSI_14nm_PHY_CMN" width="32">
+ <reg32 offset="0x00000" name="REVISION_ID0"/>
+ <reg32 offset="0x00004" name="REVISION_ID1"/>
+ <reg32 offset="0x00008" name="REVISION_ID2"/>
+ <reg32 offset="0x0000c" name="REVISION_ID3"/>
+ <reg32 offset="0x00010" name="CLK_CFG0">
+ <bitfield name="DIV_CTRL_3_0" low="4" high="7" type="uint"/>
+ <bitfield name="DIV_CTRL_7_4" low="4" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00014" name="CLK_CFG1">
+ <bitfield name="DSICLK_SEL" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00018" name="GLBL_TEST_CTRL">
+ <bitfield name="BITCLK_HS_SEL" pos="2" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0001C" name="CTRL_0"/>
+ <reg32 offset="0x00020" name="CTRL_1">
+ </reg32>
+ <reg32 offset="0x00024" name="HW_TRIGGER"/>
+ <reg32 offset="0x00028" name="SW_CFG0"/>
+ <reg32 offset="0x0002C" name="SW_CFG1"/>
+ <reg32 offset="0x00030" name="SW_CFG2"/>
+ <reg32 offset="0x00034" name="HW_CFG0"/>
+ <reg32 offset="0x00038" name="HW_CFG1"/>
+ <reg32 offset="0x0003C" name="HW_CFG2"/>
+ <reg32 offset="0x00040" name="HW_CFG3"/>
+ <reg32 offset="0x00044" name="HW_CFG4"/>
+ <reg32 offset="0x00048" name="PLL_CNTRL">
+ <bitfield name="PLL_START" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0004C" name="LDO_CNTRL">
+ <bitfield name="VREG_CTRL" low="0" high="5" type="uint"/>
+ </reg32>
+</domain>
+
+<domain name="DSI_14nm_PHY" width="32">
+ <array offset="0x00000" name="LN" length="5" stride="0x80">
+ <reg32 offset="0x00" name="CFG0">
+ <bitfield name="PREPARE_DLY" low="6" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x04" name="CFG1">
+ <bitfield name="HALFBYTECLK_EN" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x08" name="CFG2"/>
+ <reg32 offset="0x0c" name="CFG3"/>
+ <reg32 offset="0x10" name="TEST_DATAPATH"/>
+ <reg32 offset="0x14" name="TEST_STR"/>
+ <reg32 offset="0x18" name="TIMING_CTRL_4">
+ <bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x1c" name="TIMING_CTRL_5">
+ <bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x20" name="TIMING_CTRL_6">
+ <bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x24" name="TIMING_CTRL_7">
+ <bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x28" name="TIMING_CTRL_8">
+ <bitfield name="HS_RQST" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x2c" name="TIMING_CTRL_9">
+ <bitfield name="TA_GO" low="0" high="2" type="uint"/>
+ <bitfield name="TA_SURE" low="4" high="6" type="uint"/>
+ </reg32>
+ <reg32 offset="0x30" name="TIMING_CTRL_10">
+ <bitfield name="TA_GET" low="0" high="2" type="uint"/>
+ </reg32>
+ <reg32 offset="0x34" name="TIMING_CTRL_11">
+ <bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x38" name="STRENGTH_CTRL_0"/>
+ <reg32 offset="0x3c" name="STRENGTH_CTRL_1"/>
+ <reg32 offset="0x64" name="VREG_CNTRL"/>
+ </array>
+</domain>
+
+<domain name="DSI_14nm_PHY_PLL" width="32">
+ <reg32 offset="0x000" name="IE_TRIM"/>
+ <reg32 offset="0x004" name="IP_TRIM"/>
+ <reg32 offset="0x010" name="IPTAT_TRIM"/>
+ <reg32 offset="0x01c" name="CLKBUFLR_EN"/>
+ <reg32 offset="0x028" name="SYSCLK_EN_RESET"/>
+ <reg32 offset="0x02c" name="RESETSM_CNTRL"/>
+ <reg32 offset="0x030" name="RESETSM_CNTRL2"/>
+ <reg32 offset="0x034" name="RESETSM_CNTRL3"/>
+ <reg32 offset="0x038" name="RESETSM_CNTRL4"/>
+ <reg32 offset="0x03c" name="RESETSM_CNTRL5"/>
+ <reg32 offset="0x040" name="KVCO_DIV_REF1"/>
+ <reg32 offset="0x044" name="KVCO_DIV_REF2"/>
+ <reg32 offset="0x048" name="KVCO_COUNT1"/>
+ <reg32 offset="0x04c" name="KVCO_COUNT2"/>
+ <reg32 offset="0x05c" name="VREF_CFG1"/>
+ <reg32 offset="0x058" name="KVCO_CODE"/>
+ <reg32 offset="0x06c" name="VCO_DIV_REF1"/>
+ <reg32 offset="0x070" name="VCO_DIV_REF2"/>
+ <reg32 offset="0x074" name="VCO_COUNT1"/>
+ <reg32 offset="0x078" name="VCO_COUNT2"/>
+ <reg32 offset="0x07c" name="PLLLOCK_CMP1"/>
+ <reg32 offset="0x080" name="PLLLOCK_CMP2"/>
+ <reg32 offset="0x084" name="PLLLOCK_CMP3"/>
+ <reg32 offset="0x088" name="PLLLOCK_CMP_EN"/>
+ <reg32 offset="0x08c" name="PLL_VCO_TUNE"/>
+ <reg32 offset="0x090" name="DEC_START"/>
+ <reg32 offset="0x094" name="SSC_EN_CENTER"/>
+ <reg32 offset="0x098" name="SSC_ADJ_PER1"/>
+ <reg32 offset="0x09c" name="SSC_ADJ_PER2"/>
+ <reg32 offset="0x0a0" name="SSC_PER1"/>
+ <reg32 offset="0x0a4" name="SSC_PER2"/>
+ <reg32 offset="0x0a8" name="SSC_STEP_SIZE1"/>
+ <reg32 offset="0x0ac" name="SSC_STEP_SIZE2"/>
+ <reg32 offset="0x0b4" name="DIV_FRAC_START1"/>
+ <reg32 offset="0x0b8" name="DIV_FRAC_START2"/>
+ <reg32 offset="0x0bc" name="DIV_FRAC_START3"/>
+ <reg32 offset="0x0c0" name="TXCLK_EN"/>
+ <reg32 offset="0x0c4" name="PLL_CRCTRL"/>
+ <reg32 offset="0x0cc" name="RESET_SM_READY_STATUS"/>
+ <reg32 offset="0x0e8" name="PLL_MISC1"/>
+ <reg32 offset="0x0f0" name="CP_SET_CUR"/>
+ <reg32 offset="0x0f4" name="PLL_ICPMSET"/>
+ <reg32 offset="0x0f8" name="PLL_ICPCSET"/>
+ <reg32 offset="0x0fc" name="PLL_ICP_SET"/>
+ <reg32 offset="0x100" name="PLL_LPF1"/>
+ <reg32 offset="0x104" name="PLL_LPF2_POSTDIV"/>
+ <reg32 offset="0x108" name="PLL_BANDGAP"/>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_20nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_20nm.xml
new file mode 100644
index 000000000000..99e9deb361b6
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_20nm.xml
@@ -0,0 +1,100 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+
+<domain name="DSI_20nm_PHY" width="32">
+ <array offset="0x00000" name="LN" length="4" stride="0x40">
+ <reg32 offset="0x00" name="CFG_0"/>
+ <reg32 offset="0x04" name="CFG_1"/>
+ <reg32 offset="0x08" name="CFG_2"/>
+ <reg32 offset="0x0c" name="CFG_3"/>
+ <reg32 offset="0x10" name="CFG_4"/>
+ <reg32 offset="0x14" name="TEST_DATAPATH"/>
+ <reg32 offset="0x18" name="DEBUG_SEL"/>
+ <reg32 offset="0x1c" name="TEST_STR_0"/>
+ <reg32 offset="0x20" name="TEST_STR_1"/>
+ </array>
+
+ <reg32 offset="0x00100" name="LNCK_CFG_0"/>
+ <reg32 offset="0x00104" name="LNCK_CFG_1"/>
+ <reg32 offset="0x00108" name="LNCK_CFG_2"/>
+ <reg32 offset="0x0010c" name="LNCK_CFG_3"/>
+ <reg32 offset="0x00110" name="LNCK_CFG_4"/>
+ <reg32 offset="0x00114" name="LNCK_TEST_DATAPATH"/>
+ <reg32 offset="0x00118" name="LNCK_DEBUG_SEL"/>
+ <reg32 offset="0x0011c" name="LNCK_TEST_STR0"/>
+ <reg32 offset="0x00120" name="LNCK_TEST_STR1"/>
+
+ <reg32 offset="0x00140" name="TIMING_CTRL_0">
+ <bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00144" name="TIMING_CTRL_1">
+ <bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00148" name="TIMING_CTRL_2">
+ <bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0014c" name="TIMING_CTRL_3">
+ <bitfield name="CLK_ZERO_8" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00150" name="TIMING_CTRL_4">
+ <bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00154" name="TIMING_CTRL_5">
+ <bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00158" name="TIMING_CTRL_6">
+ <bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0015c" name="TIMING_CTRL_7">
+ <bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00160" name="TIMING_CTRL_8">
+ <bitfield name="HS_RQST" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00164" name="TIMING_CTRL_9">
+ <bitfield name="TA_GO" low="0" high="2" type="uint"/>
+ <bitfield name="TA_SURE" low="4" high="6" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00168" name="TIMING_CTRL_10">
+ <bitfield name="TA_GET" low="0" high="2" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0016c" name="TIMING_CTRL_11">
+ <bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x00170" name="CTRL_0"/>
+ <reg32 offset="0x00174" name="CTRL_1"/>
+ <reg32 offset="0x00178" name="CTRL_2"/>
+ <reg32 offset="0x0017c" name="CTRL_3"/>
+ <reg32 offset="0x00180" name="CTRL_4"/>
+
+ <reg32 offset="0x00184" name="STRENGTH_0"/>
+ <reg32 offset="0x00188" name="STRENGTH_1"/>
+
+ <reg32 offset="0x001b4" name="BIST_CTRL_0"/>
+ <reg32 offset="0x001b8" name="BIST_CTRL_1"/>
+ <reg32 offset="0x001bc" name="BIST_CTRL_2"/>
+ <reg32 offset="0x001c0" name="BIST_CTRL_3"/>
+ <reg32 offset="0x001c4" name="BIST_CTRL_4"/>
+ <reg32 offset="0x001c8" name="BIST_CTRL_5"/>
+
+ <reg32 offset="0x001d4" name="GLBL_TEST_CTRL">
+ <bitfield name="BITCLK_HS_SEL" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x001dc" name="LDO_CNTRL"/>
+</domain>
+
+<domain name="DSI_20nm_PHY_REGULATOR" width="32">
+ <reg32 offset="0x00000" name="CTRL_0"/>
+ <reg32 offset="0x00004" name="CTRL_1"/>
+ <reg32 offset="0x00008" name="CTRL_2"/>
+ <reg32 offset="0x0000c" name="CTRL_3"/>
+ <reg32 offset="0x00010" name="CTRL_4"/>
+ <reg32 offset="0x00014" name="CTRL_5"/>
+ <reg32 offset="0x00018" name="CAL_PWR_CFG"/>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_28nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_28nm.xml
new file mode 100644
index 000000000000..81d5b96f18c4
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_28nm.xml
@@ -0,0 +1,180 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+
+<domain name="DSI_28nm_PHY" width="32">
+ <array offset="0x00000" name="LN" length="4" stride="0x40">
+ <reg32 offset="0x00" name="CFG_0"/>
+ <reg32 offset="0x04" name="CFG_1"/>
+ <reg32 offset="0x08" name="CFG_2"/>
+ <reg32 offset="0x0c" name="CFG_3"/>
+ <reg32 offset="0x10" name="CFG_4"/>
+ <reg32 offset="0x14" name="TEST_DATAPATH"/>
+ <reg32 offset="0x18" name="DEBUG_SEL"/>
+ <reg32 offset="0x1c" name="TEST_STR_0"/>
+ <reg32 offset="0x20" name="TEST_STR_1"/>
+ </array>
+
+ <reg32 offset="0x00100" name="LNCK_CFG_0"/>
+ <reg32 offset="0x00104" name="LNCK_CFG_1"/>
+ <reg32 offset="0x00108" name="LNCK_CFG_2"/>
+ <reg32 offset="0x0010c" name="LNCK_CFG_3"/>
+ <reg32 offset="0x00110" name="LNCK_CFG_4"/>
+ <reg32 offset="0x00114" name="LNCK_TEST_DATAPATH"/>
+ <reg32 offset="0x00118" name="LNCK_DEBUG_SEL"/>
+ <reg32 offset="0x0011c" name="LNCK_TEST_STR0"/>
+ <reg32 offset="0x00120" name="LNCK_TEST_STR1"/>
+
+ <reg32 offset="0x00140" name="TIMING_CTRL_0">
+ <bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00144" name="TIMING_CTRL_1">
+ <bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00148" name="TIMING_CTRL_2">
+ <bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0014c" name="TIMING_CTRL_3">
+ <bitfield name="CLK_ZERO_8" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00150" name="TIMING_CTRL_4">
+ <bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00154" name="TIMING_CTRL_5">
+ <bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00158" name="TIMING_CTRL_6">
+ <bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0015c" name="TIMING_CTRL_7">
+ <bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00160" name="TIMING_CTRL_8">
+ <bitfield name="HS_RQST" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00164" name="TIMING_CTRL_9">
+ <bitfield name="TA_GO" low="0" high="2" type="uint"/>
+ <bitfield name="TA_SURE" low="4" high="6" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00168" name="TIMING_CTRL_10">
+ <bitfield name="TA_GET" low="0" high="2" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0016c" name="TIMING_CTRL_11">
+ <bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x00170" name="CTRL_0"/>
+ <reg32 offset="0x00174" name="CTRL_1"/>
+ <reg32 offset="0x00178" name="CTRL_2"/>
+ <reg32 offset="0x0017c" name="CTRL_3"/>
+ <reg32 offset="0x00180" name="CTRL_4"/>
+
+ <reg32 offset="0x00184" name="STRENGTH_0"/>
+ <reg32 offset="0x00188" name="STRENGTH_1"/>
+
+ <reg32 offset="0x001b4" name="BIST_CTRL_0"/>
+ <reg32 offset="0x001b8" name="BIST_CTRL_1"/>
+ <reg32 offset="0x001bc" name="BIST_CTRL_2"/>
+ <reg32 offset="0x001c0" name="BIST_CTRL_3"/>
+ <reg32 offset="0x001c4" name="BIST_CTRL_4"/>
+ <reg32 offset="0x001c8" name="BIST_CTRL_5"/>
+
+ <reg32 offset="0x001d4" name="GLBL_TEST_CTRL">
+ <bitfield name="BITCLK_HS_SEL" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x001dc" name="LDO_CNTRL"/>
+</domain>
+
+<domain name="DSI_28nm_PHY_REGULATOR" width="32">
+ <reg32 offset="0x00000" name="CTRL_0"/>
+ <reg32 offset="0x00004" name="CTRL_1"/>
+ <reg32 offset="0x00008" name="CTRL_2"/>
+ <reg32 offset="0x0000c" name="CTRL_3"/>
+ <reg32 offset="0x00010" name="CTRL_4"/>
+ <reg32 offset="0x00014" name="CTRL_5"/>
+ <reg32 offset="0x00018" name="CAL_PWR_CFG"/>
+</domain>
+
+<domain name="DSI_28nm_PHY_PLL" width="32">
+ <reg32 offset="0x00000" name="REFCLK_CFG">
+ <bitfield name="DBLR" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00004" name="POSTDIV1_CFG"/>
+ <reg32 offset="0x00008" name="CHGPUMP_CFG"/>
+ <reg32 offset="0x0000C" name="VCOLPF_CFG"/>
+ <reg32 offset="0x00010" name="VREG_CFG">
+ <bitfield name="POSTDIV1_BYPASS_B" pos="1" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00014" name="PWRGEN_CFG"/>
+ <reg32 offset="0x00018" name="DMUX_CFG"/>
+ <reg32 offset="0x0001C" name="AMUX_CFG"/>
+ <reg32 offset="0x00020" name="GLB_CFG">
+ <bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/>
+ <bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/>
+ <bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/>
+ <bitfield name="PLL_ENABLE" pos="3" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00024" name="POSTDIV2_CFG"/>
+ <reg32 offset="0x00028" name="POSTDIV3_CFG"/>
+ <reg32 offset="0x0002C" name="LPFR_CFG"/>
+ <reg32 offset="0x00030" name="LPFC1_CFG"/>
+ <reg32 offset="0x00034" name="LPFC2_CFG"/>
+ <reg32 offset="0x00038" name="SDM_CFG0">
+ <bitfield name="BYP_DIV" low="0" high="5" type="uint"/>
+ <bitfield name="BYP" pos="6" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0003C" name="SDM_CFG1">
+ <bitfield name="DC_OFFSET" low="0" high="5" type="uint"/>
+ <bitfield name="DITHER_EN" pos="6" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00040" name="SDM_CFG2">
+ <bitfield name="FREQ_SEED_7_0" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00044" name="SDM_CFG3">
+ <bitfield name="FREQ_SEED_15_8" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00048" name="SDM_CFG4"/>
+ <reg32 offset="0x0004C" name="SSC_CFG0"/>
+ <reg32 offset="0x00050" name="SSC_CFG1"/>
+ <reg32 offset="0x00054" name="SSC_CFG2"/>
+ <reg32 offset="0x00058" name="SSC_CFG3"/>
+ <reg32 offset="0x0005C" name="LKDET_CFG0"/>
+ <reg32 offset="0x00060" name="LKDET_CFG1"/>
+ <reg32 offset="0x00064" name="LKDET_CFG2"/>
+ <reg32 offset="0x00068" name="TEST_CFG">
+ <bitfield name="PLL_SW_RESET" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0006C" name="CAL_CFG0"/>
+ <reg32 offset="0x00070" name="CAL_CFG1"/>
+ <reg32 offset="0x00074" name="CAL_CFG2"/>
+ <reg32 offset="0x00078" name="CAL_CFG3"/>
+ <reg32 offset="0x0007C" name="CAL_CFG4"/>
+ <reg32 offset="0x00080" name="CAL_CFG5"/>
+ <reg32 offset="0x00084" name="CAL_CFG6"/>
+ <reg32 offset="0x00088" name="CAL_CFG7"/>
+ <reg32 offset="0x0008C" name="CAL_CFG8"/>
+ <reg32 offset="0x00090" name="CAL_CFG9"/>
+ <reg32 offset="0x00094" name="CAL_CFG10"/>
+ <reg32 offset="0x00098" name="CAL_CFG11"/>
+ <reg32 offset="0x0009C" name="EFUSE_CFG"/>
+ <reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/>
+ <reg32 offset="0x000A4" name="CTRL_42"/>
+ <reg32 offset="0x000A8" name="CTRL_43"/>
+ <reg32 offset="0x000AC" name="CTRL_44"/>
+ <reg32 offset="0x000B0" name="CTRL_45"/>
+ <reg32 offset="0x000B4" name="CTRL_46"/>
+ <reg32 offset="0x000B8" name="CTRL_47"/>
+ <reg32 offset="0x000BC" name="CTRL_48"/>
+ <reg32 offset="0x000C0" name="STATUS">
+ <bitfield name="PLL_RDY" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x000C4" name="DEBUG_BUS0"/>
+ <reg32 offset="0x000C8" name="DEBUG_BUS1"/>
+ <reg32 offset="0x000CC" name="DEBUG_BUS2"/>
+ <reg32 offset="0x000D0" name="DEBUG_BUS3"/>
+ <reg32 offset="0x000D4" name="CTRL_54"/>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_28nm_8960.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_28nm_8960.xml
new file mode 100644
index 000000000000..4c4de4dda640
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_28nm_8960.xml
@@ -0,0 +1,134 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+
+<domain name="DSI_28nm_8960_PHY" width="32">
+
+ <array offset="0x00000" name="LN" length="4" stride="0x40">
+ <reg32 offset="0x00" name="CFG_0"/>
+ <reg32 offset="0x04" name="CFG_1"/>
+ <reg32 offset="0x08" name="CFG_2"/>
+ <reg32 offset="0x0c" name="TEST_DATAPATH"/>
+ <reg32 offset="0x14" name="TEST_STR_0"/>
+ <reg32 offset="0x18" name="TEST_STR_1"/>
+ </array>
+
+ <reg32 offset="0x00100" name="LNCK_CFG_0"/>
+ <reg32 offset="0x00104" name="LNCK_CFG_1"/>
+ <reg32 offset="0x00108" name="LNCK_CFG_2"/>
+
+ <reg32 offset="0x0010c" name="LNCK_TEST_DATAPATH"/>
+ <reg32 offset="0x00114" name="LNCK_TEST_STR0"/>
+ <reg32 offset="0x00118" name="LNCK_TEST_STR1"/>
+
+ <reg32 offset="0x00140" name="TIMING_CTRL_0">
+ <bitfield name="CLK_ZERO" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00144" name="TIMING_CTRL_1">
+ <bitfield name="CLK_TRAIL" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00148" name="TIMING_CTRL_2">
+ <bitfield name="CLK_PREPARE" low="0" high="7" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x0014c" name="TIMING_CTRL_3"/>
+
+ <reg32 offset="0x00150" name="TIMING_CTRL_4">
+ <bitfield name="HS_EXIT" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00154" name="TIMING_CTRL_5">
+ <bitfield name="HS_ZERO" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00158" name="TIMING_CTRL_6">
+ <bitfield name="HS_PREPARE" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0015c" name="TIMING_CTRL_7">
+ <bitfield name="HS_TRAIL" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00160" name="TIMING_CTRL_8">
+ <bitfield name="HS_RQST" low="0" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00164" name="TIMING_CTRL_9">
+ <bitfield name="TA_GO" low="0" high="2" type="uint"/>
+ <bitfield name="TA_SURE" low="4" high="6" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00168" name="TIMING_CTRL_10">
+ <bitfield name="TA_GET" low="0" high="2" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0016c" name="TIMING_CTRL_11">
+ <bitfield name="TRIG3_CMD" low="0" high="7" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x00170" name="CTRL_0"/>
+ <reg32 offset="0x00174" name="CTRL_1"/>
+ <reg32 offset="0x00178" name="CTRL_2"/>
+ <reg32 offset="0x0017c" name="CTRL_3"/>
+
+ <reg32 offset="0x00180" name="STRENGTH_0"/>
+ <reg32 offset="0x00184" name="STRENGTH_1"/>
+ <reg32 offset="0x00188" name="STRENGTH_2"/>
+
+ <reg32 offset="0x0018c" name="BIST_CTRL_0"/>
+ <reg32 offset="0x00190" name="BIST_CTRL_1"/>
+ <reg32 offset="0x00194" name="BIST_CTRL_2"/>
+ <reg32 offset="0x00198" name="BIST_CTRL_3"/>
+ <reg32 offset="0x0019c" name="BIST_CTRL_4"/>
+
+ <reg32 offset="0x001b0" name="LDO_CTRL"/>
+</domain>
+
+<domain name="DSI_28nm_8960_PHY_MISC" width="32">
+ <reg32 offset="0x00000" name="REGULATOR_CTRL_0"/>
+ <reg32 offset="0x00004" name="REGULATOR_CTRL_1"/>
+ <reg32 offset="0x00008" name="REGULATOR_CTRL_2"/>
+ <reg32 offset="0x0000c" name="REGULATOR_CTRL_3"/>
+ <reg32 offset="0x00010" name="REGULATOR_CTRL_4"/>
+ <reg32 offset="0x00014" name="REGULATOR_CTRL_5"/>
+ <reg32 offset="0x00018" name="REGULATOR_CAL_PWR_CFG"/>
+ <reg32 offset="0x00028" name="CAL_HW_TRIGGER"/>
+ <reg32 offset="0x0002c" name="CAL_SW_CFG_0"/>
+ <reg32 offset="0x00030" name="CAL_SW_CFG_1"/>
+ <reg32 offset="0x00034" name="CAL_SW_CFG_2"/>
+ <reg32 offset="0x00038" name="CAL_HW_CFG_0"/>
+ <reg32 offset="0x0003c" name="CAL_HW_CFG_1"/>
+ <reg32 offset="0x00040" name="CAL_HW_CFG_2"/>
+ <reg32 offset="0x00044" name="CAL_HW_CFG_3"/>
+ <reg32 offset="0x00048" name="CAL_HW_CFG_4"/>
+ <reg32 offset="0x00050" name="CAL_STATUS">
+ <bitfield name="CAL_BUSY" pos="4" type="boolean"/>
+ </reg32>
+</domain>
+
+<domain name="DSI_28nm_8960_PHY_PLL" width="32">
+ <reg32 offset="0x00000" name="CTRL_0">
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00004" name="CTRL_1"/>
+ <reg32 offset="0x00008" name="CTRL_2"/>
+ <reg32 offset="0x0000c" name="CTRL_3"/>
+ <reg32 offset="0x00010" name="CTRL_4"/>
+ <reg32 offset="0x00014" name="CTRL_5"/>
+ <reg32 offset="0x00018" name="CTRL_6"/>
+ <reg32 offset="0x0001c" name="CTRL_7"/>
+ <reg32 offset="0x00020" name="CTRL_8"/>
+ <reg32 offset="0x00024" name="CTRL_9"/>
+ <reg32 offset="0x00028" name="CTRL_10"/>
+ <reg32 offset="0x0002c" name="CTRL_11"/>
+ <reg32 offset="0x00030" name="CTRL_12"/>
+ <reg32 offset="0x00034" name="CTRL_13"/>
+ <reg32 offset="0x00038" name="CTRL_14"/>
+ <reg32 offset="0x0003c" name="CTRL_15"/>
+ <reg32 offset="0x00040" name="CTRL_16"/>
+ <reg32 offset="0x00044" name="CTRL_17"/>
+ <reg32 offset="0x00048" name="CTRL_18"/>
+ <reg32 offset="0x0004c" name="CTRL_19"/>
+ <reg32 offset="0x00050" name="CTRL_20"/>
+
+ <reg32 offset="0x00080" name="RDY">
+ <bitfield name="PLL_RDY" pos="0" type="boolean"/>
+ </reg32>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
new file mode 100644
index 000000000000..d54b72f92449
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
@@ -0,0 +1,230 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+
+<domain name="DSI_7nm_PHY_CMN" width="32">
+ <reg32 offset="0x00000" name="REVISION_ID0"/>
+ <reg32 offset="0x00004" name="REVISION_ID1"/>
+ <reg32 offset="0x00008" name="REVISION_ID2"/>
+ <reg32 offset="0x0000c" name="REVISION_ID3"/>
+ <reg32 offset="0x00010" name="CLK_CFG0"/>
+ <reg32 offset="0x00014" name="CLK_CFG1"/>
+ <reg32 offset="0x00018" name="GLBL_CTRL"/>
+ <reg32 offset="0x0001c" name="RBUF_CTRL"/>
+ <reg32 offset="0x00020" name="VREG_CTRL_0"/>
+ <reg32 offset="0x00024" name="CTRL_0"/>
+ <reg32 offset="0x00028" name="CTRL_1"/>
+ <reg32 offset="0x0002c" name="CTRL_2"/>
+ <reg32 offset="0x00030" name="CTRL_3"/>
+ <reg32 offset="0x00034" name="LANE_CFG0"/>
+ <reg32 offset="0x00038" name="LANE_CFG1"/>
+ <reg32 offset="0x0003c" name="PLL_CNTRL"/>
+ <reg32 offset="0x00040" name="DPHY_SOT"/>
+ <reg32 offset="0x000a0" name="LANE_CTRL0"/>
+ <reg32 offset="0x000a4" name="LANE_CTRL1"/>
+ <reg32 offset="0x000a8" name="LANE_CTRL2"/>
+ <reg32 offset="0x000ac" name="LANE_CTRL3"/>
+ <reg32 offset="0x000b0" name="LANE_CTRL4"/>
+ <reg32 offset="0x000b4" name="TIMING_CTRL_0"/>
+ <reg32 offset="0x000b8" name="TIMING_CTRL_1"/>
+ <reg32 offset="0x000bc" name="TIMING_CTRL_2"/>
+ <reg32 offset="0x000c0" name="TIMING_CTRL_3"/>
+ <reg32 offset="0x000c4" name="TIMING_CTRL_4"/>
+ <reg32 offset="0x000c8" name="TIMING_CTRL_5"/>
+ <reg32 offset="0x000cc" name="TIMING_CTRL_6"/>
+ <reg32 offset="0x000d0" name="TIMING_CTRL_7"/>
+ <reg32 offset="0x000d4" name="TIMING_CTRL_8"/>
+ <reg32 offset="0x000d8" name="TIMING_CTRL_9"/>
+ <reg32 offset="0x000dc" name="TIMING_CTRL_10"/>
+ <reg32 offset="0x000e0" name="TIMING_CTRL_11"/>
+ <reg32 offset="0x000e4" name="TIMING_CTRL_12"/>
+ <reg32 offset="0x000e8" name="TIMING_CTRL_13"/>
+ <reg32 offset="0x000ec" name="GLBL_HSTX_STR_CTRL_0"/>
+ <reg32 offset="0x000f0" name="GLBL_HSTX_STR_CTRL_1"/>
+ <reg32 offset="0x000f4" name="GLBL_RESCODE_OFFSET_TOP_CTRL"/>
+ <reg32 offset="0x000f8" name="GLBL_RESCODE_OFFSET_BOT_CTRL"/>
+ <reg32 offset="0x000fc" name="GLBL_RESCODE_OFFSET_MID_CTRL"/>
+ <reg32 offset="0x00100" name="GLBL_LPTX_STR_CTRL"/>
+ <reg32 offset="0x00104" name="GLBL_PEMPH_CTRL_0"/>
+ <reg32 offset="0x00108" name="GLBL_PEMPH_CTRL_1"/>
+ <reg32 offset="0x0010c" name="GLBL_STR_SWI_CAL_SEL_CTRL"/>
+ <reg32 offset="0x00110" name="VREG_CTRL_1"/>
+ <reg32 offset="0x00114" name="CTRL_4"/>
+ <reg32 offset="0x00128" name="GLBL_DIGTOP_SPARE4"/>
+ <reg32 offset="0x00140" name="PHY_STATUS"/>
+ <reg32 offset="0x00148" name="LANE_STATUS0"/>
+ <reg32 offset="0x0014c" name="LANE_STATUS1"/>
+ <reg32 offset="0x001ac" name="GLBL_DIGTOP_SPARE10"/>
+</domain>
+
+<domain name="DSI_7nm_PHY" width="32">
+ <array offset="0x00000" name="LN" length="5" stride="0x80">
+ <reg32 offset="0x00" name="CFG0"/>
+ <reg32 offset="0x04" name="CFG1"/>
+ <reg32 offset="0x08" name="CFG2"/>
+ <reg32 offset="0x0c" name="TEST_DATAPATH"/>
+ <reg32 offset="0x10" name="PIN_SWAP"/>
+ <reg32 offset="0x14" name="LPRX_CTRL"/>
+ <reg32 offset="0x18" name="TX_DCTRL"/>
+ </array>
+</domain>
+
+<domain name="DSI_7nm_PHY_PLL" width="32">
+ <reg32 offset="0x0000" name="ANALOG_CONTROLS_ONE"/>
+ <reg32 offset="0x0004" name="ANALOG_CONTROLS_TWO"/>
+ <reg32 offset="0x0008" name="INT_LOOP_SETTINGS"/>
+ <reg32 offset="0x000c" name="INT_LOOP_SETTINGS_TWO"/>
+ <reg32 offset="0x0010" name="ANALOG_CONTROLS_THREE"/>
+ <reg32 offset="0x0014" name="ANALOG_CONTROLS_FOUR"/>
+ <reg32 offset="0x0018" name="ANALOG_CONTROLS_FIVE"/>
+ <reg32 offset="0x001c" name="INT_LOOP_CONTROLS"/>
+ <reg32 offset="0x0020" name="DSM_DIVIDER"/>
+ <reg32 offset="0x0024" name="FEEDBACK_DIVIDER"/>
+ <reg32 offset="0x0028" name="SYSTEM_MUXES"/>
+ <reg32 offset="0x002c" name="FREQ_UPDATE_CONTROL_OVERRIDES"/>
+ <reg32 offset="0x0030" name="CMODE"/>
+ <reg32 offset="0x0034" name="PSM_CTRL"/>
+ <reg32 offset="0x0038" name="RSM_CTRL"/>
+ <reg32 offset="0x003c" name="VCO_TUNE_MAP"/>
+ <reg32 offset="0x0040" name="PLL_CNTRL"/>
+ <reg32 offset="0x0044" name="CALIBRATION_SETTINGS"/>
+ <reg32 offset="0x0048" name="BAND_SEL_CAL_TIMER_LOW"/>
+ <reg32 offset="0x004c" name="BAND_SEL_CAL_TIMER_HIGH"/>
+ <reg32 offset="0x0050" name="BAND_SEL_CAL_SETTINGS"/>
+ <reg32 offset="0x0054" name="BAND_SEL_MIN"/>
+ <reg32 offset="0x0058" name="BAND_SEL_MAX"/>
+ <reg32 offset="0x005c" name="BAND_SEL_PFILT"/>
+ <reg32 offset="0x0060" name="BAND_SEL_IFILT"/>
+ <reg32 offset="0x0064" name="BAND_SEL_CAL_SETTINGS_TWO"/>
+ <reg32 offset="0x0068" name="BAND_SEL_CAL_SETTINGS_THREE"/>
+ <reg32 offset="0x006c" name="BAND_SEL_CAL_SETTINGS_FOUR"/>
+ <reg32 offset="0x0070" name="BAND_SEL_ICODE_HIGH"/>
+ <reg32 offset="0x0074" name="BAND_SEL_ICODE_LOW"/>
+ <reg32 offset="0x0078" name="FREQ_DETECT_SETTINGS_ONE"/>
+ <reg32 offset="0x007c" name="FREQ_DETECT_THRESH"/>
+ <reg32 offset="0x0080" name="FREQ_DET_REFCLK_HIGH"/>
+ <reg32 offset="0x0084" name="FREQ_DET_REFCLK_LOW"/>
+ <reg32 offset="0x0088" name="FREQ_DET_PLLCLK_HIGH"/>
+ <reg32 offset="0x008c" name="FREQ_DET_PLLCLK_LOW"/>
+ <reg32 offset="0x0090" name="PFILT"/>
+ <reg32 offset="0x0094" name="IFILT"/>
+ <reg32 offset="0x0098" name="PLL_GAIN"/>
+ <reg32 offset="0x009c" name="ICODE_LOW"/>
+ <reg32 offset="0x00a0" name="ICODE_HIGH"/>
+ <reg32 offset="0x00a4" name="LOCKDET"/>
+ <reg32 offset="0x00a8" name="OUTDIV"/>
+ <reg32 offset="0x00ac" name="FASTLOCK_CONTROL"/>
+ <reg32 offset="0x00b0" name="PASS_OUT_OVERRIDE_ONE"/>
+ <reg32 offset="0x00b4" name="PASS_OUT_OVERRIDE_TWO"/>
+ <reg32 offset="0x00b8" name="CORE_OVERRIDE"/>
+ <reg32 offset="0x00bc" name="CORE_INPUT_OVERRIDE"/>
+ <reg32 offset="0x00c0" name="RATE_CHANGE"/>
+ <reg32 offset="0x00c4" name="PLL_DIGITAL_TIMERS"/>
+ <reg32 offset="0x00c8" name="PLL_DIGITAL_TIMERS_TWO"/>
+ <reg32 offset="0x00cc" name="DECIMAL_DIV_START"/>
+ <reg32 offset="0x00d0" name="FRAC_DIV_START_LOW"/>
+ <reg32 offset="0x00d4" name="FRAC_DIV_START_MID"/>
+ <reg32 offset="0x00d8" name="FRAC_DIV_START_HIGH"/>
+ <reg32 offset="0x00dc" name="DEC_FRAC_MUXES"/>
+ <reg32 offset="0x00e0" name="DECIMAL_DIV_START_1"/>
+ <reg32 offset="0x00e4" name="FRAC_DIV_START_LOW_1"/>
+ <reg32 offset="0x00e8" name="FRAC_DIV_START_MID_1"/>
+ <reg32 offset="0x00ec" name="FRAC_DIV_START_HIGH_1"/>
+ <reg32 offset="0x00f0" name="DECIMAL_DIV_START_2"/>
+ <reg32 offset="0x00f4" name="FRAC_DIV_START_LOW_2"/>
+ <reg32 offset="0x00f8" name="FRAC_DIV_START_MID_2"/>
+ <reg32 offset="0x00fc" name="FRAC_DIV_START_HIGH_2"/>
+ <reg32 offset="0x0100" name="MASH_CONTROL"/>
+ <reg32 offset="0x0104" name="SSC_STEPSIZE_LOW"/>
+ <reg32 offset="0x0108" name="SSC_STEPSIZE_HIGH"/>
+ <reg32 offset="0x010c" name="SSC_DIV_PER_LOW"/>
+ <reg32 offset="0x0110" name="SSC_DIV_PER_HIGH"/>
+ <reg32 offset="0x0114" name="SSC_ADJPER_LOW"/>
+ <reg32 offset="0x0118" name="SSC_ADJPER_HIGH"/>
+ <reg32 offset="0x011c" name="SSC_MUX_CONTROL"/>
+ <reg32 offset="0x0120" name="SSC_STEPSIZE_LOW_1"/>
+ <reg32 offset="0x0124" name="SSC_STEPSIZE_HIGH_1"/>
+ <reg32 offset="0x0128" name="SSC_DIV_PER_LOW_1"/>
+ <reg32 offset="0x012c" name="SSC_DIV_PER_HIGH_1"/>
+ <reg32 offset="0x0130" name="SSC_ADJPER_LOW_1"/>
+ <reg32 offset="0x0134" name="SSC_ADJPER_HIGH_1"/>
+ <reg32 offset="0x0138" name="SSC_STEPSIZE_LOW_2"/>
+ <reg32 offset="0x013c" name="SSC_STEPSIZE_HIGH_2"/>
+ <reg32 offset="0x0140" name="SSC_DIV_PER_LOW_2"/>
+ <reg32 offset="0x0144" name="SSC_DIV_PER_HIGH_2"/>
+ <reg32 offset="0x0148" name="SSC_ADJPER_LOW_2"/>
+ <reg32 offset="0x014c" name="SSC_ADJPER_HIGH_2"/>
+ <reg32 offset="0x0150" name="SSC_CONTROL"/>
+ <reg32 offset="0x0154" name="PLL_OUTDIV_RATE"/>
+ <reg32 offset="0x0158" name="PLL_LOCKDET_RATE_1"/>
+ <reg32 offset="0x015c" name="PLL_LOCKDET_RATE_2"/>
+ <reg32 offset="0x0160" name="PLL_PROP_GAIN_RATE_1"/>
+ <reg32 offset="0x0164" name="PLL_PROP_GAIN_RATE_2"/>
+ <reg32 offset="0x0168" name="PLL_BAND_SEL_RATE_1"/>
+ <reg32 offset="0x016c" name="PLL_BAND_SEL_RATE_2"/>
+ <reg32 offset="0x0170" name="PLL_INT_GAIN_IFILT_BAND_1"/>
+ <reg32 offset="0x0174" name="PLL_INT_GAIN_IFILT_BAND_2"/>
+ <reg32 offset="0x0178" name="PLL_FL_INT_GAIN_PFILT_BAND_1"/>
+ <reg32 offset="0x017c" name="PLL_FL_INT_GAIN_PFILT_BAND_2"/>
+ <reg32 offset="0x0180" name="PLL_FASTLOCK_EN_BAND"/>
+ <reg32 offset="0x0184" name="FREQ_TUNE_ACCUM_INIT_MID"/>
+ <reg32 offset="0x0188" name="FREQ_TUNE_ACCUM_INIT_HIGH"/>
+ <reg32 offset="0x018c" name="FREQ_TUNE_ACCUM_INIT_MUX"/>
+ <reg32 offset="0x0190" name="PLL_LOCK_OVERRIDE"/>
+ <reg32 offset="0x0194" name="PLL_LOCK_DELAY"/>
+ <reg32 offset="0x0198" name="PLL_LOCK_MIN_DELAY"/>
+ <reg32 offset="0x019c" name="CLOCK_INVERTERS"/>
+ <reg32 offset="0x01a0" name="SPARE_AND_JPC_OVERRIDES"/>
+ <reg32 offset="0x01a4" name="BIAS_CONTROL_1"/>
+ <reg32 offset="0x01a8" name="BIAS_CONTROL_2"/>
+ <reg32 offset="0x01ac" name="ALOG_OBSV_BUS_CTRL_1"/>
+ <reg32 offset="0x01b0" name="COMMON_STATUS_ONE"/>
+ <reg32 offset="0x01b4" name="COMMON_STATUS_TWO"/>
+ <reg32 offset="0x01b8" name="BAND_SEL_CAL"/>
+ <reg32 offset="0x01bc" name="ICODE_ACCUM_STATUS_LOW"/>
+ <reg32 offset="0x01c0" name="ICODE_ACCUM_STATUS_HIGH"/>
+ <reg32 offset="0x01c4" name="FD_OUT_LOW"/>
+ <reg32 offset="0x01c8" name="FD_OUT_HIGH"/>
+ <reg32 offset="0x01cc" name="ALOG_OBSV_BUS_STATUS_1"/>
+ <reg32 offset="0x01d0" name="PLL_MISC_CONFIG"/>
+ <reg32 offset="0x01d4" name="FLL_CONFIG"/>
+ <reg32 offset="0x01d8" name="FLL_FREQ_ACQ_TIME"/>
+ <reg32 offset="0x01dc" name="FLL_CODE0"/>
+ <reg32 offset="0x01e0" name="FLL_CODE1"/>
+ <reg32 offset="0x01e4" name="FLL_GAIN0"/>
+ <reg32 offset="0x01e8" name="FLL_GAIN1"/>
+ <reg32 offset="0x01ec" name="SW_RESET"/>
+ <reg32 offset="0x01f0" name="FAST_PWRUP"/>
+ <reg32 offset="0x01f4" name="LOCKTIME0"/>
+ <reg32 offset="0x01f8" name="LOCKTIME1"/>
+ <reg32 offset="0x01fc" name="DEBUG_BUS_SEL"/>
+ <reg32 offset="0x0200" name="DEBUG_BUS0"/>
+ <reg32 offset="0x0204" name="DEBUG_BUS1"/>
+ <reg32 offset="0x0208" name="DEBUG_BUS2"/>
+ <reg32 offset="0x020c" name="DEBUG_BUS3"/>
+ <reg32 offset="0x0210" name="ANALOG_FLL_CONTROL_OVERRIDES"/>
+ <reg32 offset="0x0214" name="VCO_CONFIG"/>
+ <reg32 offset="0x0218" name="VCO_CAL_CODE1_MODE0_STATUS"/>
+ <reg32 offset="0x021c" name="VCO_CAL_CODE1_MODE1_STATUS"/>
+ <reg32 offset="0x0220" name="RESET_SM_STATUS"/>
+ <reg32 offset="0x0224" name="TDC_OFFSET"/>
+ <reg32 offset="0x0228" name="PS3_PWRDOWN_CONTROLS"/>
+ <reg32 offset="0x022c" name="PS4_PWRDOWN_CONTROLS"/>
+ <reg32 offset="0x0230" name="PLL_RST_CONTROLS"/>
+ <reg32 offset="0x0234" name="GEAR_BAND_SELECT_CONTROLS"/>
+ <reg32 offset="0x0238" name="PSM_CLK_CONTROLS"/>
+ <reg32 offset="0x023c" name="SYSTEM_MUXES_2"/>
+ <reg32 offset="0x0240" name="VCO_CONFIG_1"/>
+ <reg32 offset="0x0244" name="VCO_CONFIG_2"/>
+ <reg32 offset="0x0248" name="CLOCK_INVERTERS_1"/>
+ <reg32 offset="0x024c" name="CLOCK_INVERTERS_2"/>
+ <reg32 offset="0x0250" name="CMODE_1"/>
+ <reg32 offset="0x0254" name="CMODE_2"/>
+ <reg32 offset="0x0258" name="ANALOG_CONTROLS_FIVE_1"/>
+ <reg32 offset="0x025c" name="ANALOG_CONTROLS_FIVE_2"/>
+ <reg32 offset="0x0260" name="PERF_OPTIMIZE"/>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/display/edp.xml b/drivers/gpu/drm/msm/registers/display/edp.xml
new file mode 100644
index 000000000000..354f90eb6de5
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/display/edp.xml
@@ -0,0 +1,239 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+
+<domain name="EDP" width="32">
+ <enum name="edp_color_depth">
+ <value name="EDP_6BIT" value="0"/>
+ <value name="EDP_8BIT" value="1"/>
+ <value name="EDP_10BIT" value="2"/>
+ <value name="EDP_12BIT" value="3"/>
+ <value name="EDP_16BIT" value="4"/>
+ </enum>
+
+ <enum name="edp_component_format">
+ <value name="EDP_RGB" value="0"/>
+ <value name="EDP_YUV422" value="1"/>
+ <value name="EDP_YUV444" value="2"/>
+ </enum>
+
+ <reg32 offset="0x0004" name="MAINLINK_CTRL">
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ <bitfield name="RESET" pos="1" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x0008" name="STATE_CTRL">
+ <bitfield name="TRAIN_PATTERN_1" pos="0" type="boolean"/>
+ <bitfield name="TRAIN_PATTERN_2" pos="1" type="boolean"/>
+ <bitfield name="TRAIN_PATTERN_3" pos="2" type="boolean"/>
+ <bitfield name="SYMBOL_ERR_RATE_MEAS" pos="3" type="boolean"/>
+ <bitfield name="PRBS7" pos="4" type="boolean"/>
+ <bitfield name="CUSTOM_80_BIT_PATTERN" pos="5" type="boolean"/>
+ <bitfield name="SEND_VIDEO" pos="6" type="boolean"/>
+ <bitfield name="PUSH_IDLE" pos="7" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x000c" name="CONFIGURATION_CTRL">
+ <!-- next two may be swapped? -->
+ <bitfield name="SYNC_CLK" pos="0" type="boolean"/>
+ <bitfield name="STATIC_MVID" pos="1" type="boolean"/>
+ <bitfield name="PROGRESSIVE" pos="2" type="boolean"/>
+ <!-- # of lanes minus one: -->
+ <bitfield name="LANES" low="4" high="5" type="uint"/>
+ <bitfield name="ENHANCED_FRAMING" pos="6" type="boolean"/>
+ <!--
+ NOTE: only 6bit and 8bit valid
+ -->
+ <bitfield name="COLOR" pos="8" type="edp_color_depth"/>
+ </reg32>
+
+ <reg32 offset="0x0014" name="SOFTWARE_MVID" type="uint"/>
+ <reg32 offset="0x0018" name="SOFTWARE_NVID" type="uint"/>
+
+ <reg32 offset="0x001c" name="TOTAL_HOR_VER">
+ <bitfield name="HORIZ" low="0" high="15" type="uint"/>
+ <bitfield name="VERT" low="16" high="31" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x0020" name="START_HOR_VER_FROM_SYNC">
+ <bitfield name="HORIZ" low="0" high="15" type="uint"/>
+ <bitfield name="VERT" low="16" high="31" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x0024" name="HSYNC_VSYNC_WIDTH_POLARITY">
+ <bitfield name="HORIZ" low="0" high="14" type="uint"/>
+ <bitfield name="NHSYNC" pos="15" type="boolean"/>
+ <bitfield name="VERT" low="16" high="30" type="uint"/>
+ <bitfield name="NVSYNC" pos="31" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x0028" name="ACTIVE_HOR_VER">
+ <bitfield name="HORIZ" low="0" high="15" type="uint"/>
+ <bitfield name="VERT" low="16" high="31" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x002c" name="MISC1_MISC0">
+ <!-- MISC0 from DisplayPort v1.2 spec: -->
+ <bitfield name="MISC0" low="0" high="7"/>
+ <!-- aliased MISC0 bitfields: -->
+ <bitfield name="SYNC" pos="0" type="boolean"/>
+ <bitfield name="COMPONENT_FORMAT" low="1" high="2" type="edp_component_format"/>
+ <!-- CEA (vs VESA) color range: -->
+ <bitfield name="CEA" pos="3" type="boolean"/>
+ <!-- YCbCr Colorimetry ITU-R BT709-5 (vs ITU-R BT601-5): -->
+ <bitfield name="BT709_5" pos="4" type="boolean"/>
+ <bitfield name="COLOR" low="5" high="7" type="edp_color_depth"/>
+
+ <!-- MISC1 from DisplayPort v1.2 spec: -->
+ <bitfield name="MISC1" low="8" high="15"/>
+ <!-- aliased MISC1 bitfields: -->
+ <bitfield name="INTERLACED_ODD" pos="8" type="boolean"/>
+ <bitfield name="STEREO" low="9" high="10" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x0074" name="PHY_CTRL">
+ <bitfield name="SW_RESET_PLL" pos="0" type="boolean"/>
+ <bitfield name="SW_RESET" pos="2" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0084" name="MAINLINK_READY">
+ <bitfield name="TRAIN_PATTERN_1_READY" pos="3" type="boolean"/>
+ <bitfield name="TRAIN_PATTERN_2_READY" pos="4" type="boolean"/>
+ <bitfield name="TRAIN_PATTERN_3_READY" pos="5" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x0300" name="AUX_CTRL">
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ <bitfield name="RESET" pos="1" type="boolean"/>
+ </reg32>
+
+ <!-- interrupt registers come in sets of 3 bits, status/ack/en -->
+ <reg32 offset="0x0308" name="INTERRUPT_REG_1">
+ <bitfield name="HPD" pos="0" type="boolean"/>
+ <bitfield name="HPD_ACK" pos="1" type="boolean"/>
+ <bitfield name="HPD_EN" pos="2" type="boolean"/>
+ <bitfield name="AUX_I2C_DONE" pos="3" type="boolean"/>
+ <bitfield name="AUX_I2C_DONE_ACK" pos="4" type="boolean"/>
+ <bitfield name="AUX_I2C_DONE_EN" pos="5" type="boolean"/>
+ <bitfield name="WRONG_ADDR" pos="6" type="boolean"/>
+ <bitfield name="WRONG_ADDR_ACK" pos="7" type="boolean"/>
+ <bitfield name="WRONG_ADDR_EN" pos="8" type="boolean"/>
+ <bitfield name="TIMEOUT" pos="9" type="boolean"/>
+ <bitfield name="TIMEOUT_ACK" pos="10" type="boolean"/>
+ <bitfield name="TIMEOUT_EN" pos="11" type="boolean"/>
+ <bitfield name="NACK_DEFER" pos="12" type="boolean"/>
+ <bitfield name="NACK_DEFER_ACK" pos="13" type="boolean"/>
+ <bitfield name="NACK_DEFER_EN" pos="14" type="boolean"/>
+ <bitfield name="WRONG_DATA_CNT" pos="15" type="boolean"/>
+ <bitfield name="WRONG_DATA_CNT_ACK" pos="16" type="boolean"/>
+ <bitfield name="WRONG_DATA_CNT_EN" pos="17" type="boolean"/>
+ <bitfield name="I2C_NACK" pos="18" type="boolean"/>
+ <bitfield name="I2C_NACK_ACK" pos="19" type="boolean"/>
+ <bitfield name="I2C_NACK_EN" pos="20" type="boolean"/>
+ <bitfield name="I2C_DEFER" pos="21" type="boolean"/>
+ <bitfield name="I2C_DEFER_ACK" pos="22" type="boolean"/>
+ <bitfield name="I2C_DEFER_EN" pos="23" type="boolean"/>
+ <bitfield name="PLL_UNLOCK" pos="24" type="boolean"/>
+ <bitfield name="PLL_UNLOCK_ACK" pos="25" type="boolean"/>
+ <bitfield name="PLL_UNLOCK_EN" pos="26" type="boolean"/>
+ <bitfield name="AUX_ERROR" pos="27" type="boolean"/>
+ <bitfield name="AUX_ERROR_ACK" pos="28" type="boolean"/>
+ <bitfield name="AUX_ERROR_EN" pos="29" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x030c" name="INTERRUPT_REG_2">
+ <bitfield name="READY_FOR_VIDEO" pos="0" type="boolean"/>
+ <bitfield name="READY_FOR_VIDEO_ACK" pos="1" type="boolean"/>
+ <bitfield name="READY_FOR_VIDEO_EN" pos="2" type="boolean"/>
+ <bitfield name="IDLE_PATTERNs_SENT" pos="3" type="boolean"/>
+ <bitfield name="IDLE_PATTERNs_SENT_ACK" pos="4" type="boolean"/>
+ <bitfield name="IDLE_PATTERNs_SENT_EN" pos="5" type="boolean"/>
+ <bitfield name="FRAME_END" pos="9" type="boolean"/>
+ <bitfield name="FRAME_END_ACK" pos="7" type="boolean"/>
+ <bitfield name="FRAME_END_EN" pos="8" type="boolean"/>
+ <bitfield name="CRC_UPDATED" pos="9" type="boolean"/>
+ <bitfield name="CRC_UPDATED_ACK" pos="10" type="boolean"/>
+ <bitfield name="CRC_UPDATED_EN" pos="11" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x0310" name="INTERRUPT_TRANS_NUM"/>
+ <reg32 offset="0x0314" name="AUX_DATA">
+ <bitfield name="READ" pos="0" type="boolean"/>
+ <bitfield name="DATA" low="8" high="15"/>
+ <bitfield name="INDEX" low="16" high="23"/>
+ <bitfield name="INDEX_WRITE" pos="31" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x0318" name="AUX_TRANS_CTRL">
+ <bitfield name="I2C" pos="8" type="boolean"/>
+ <bitfield name="GO" pos="9" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x0324" name="AUX_STATUS"/>
+</domain>
+
+<domain name="EDP_PHY" width="32">
+ <array offset="0x0400" name="LN" length="4" stride="0x40">
+ <reg32 offset="0x04" name="PD_CTL"/>
+ </array>
+ <reg32 offset="0x0510" name="GLB_VM_CFG0"/>
+ <reg32 offset="0x0514" name="GLB_VM_CFG1"/>
+ <reg32 offset="0x0518" name="GLB_MISC9"/>
+ <reg32 offset="0x0528" name="GLB_CFG"/>
+ <reg32 offset="0x052c" name="GLB_PD_CTL"/>
+ <reg32 offset="0x0598" name="GLB_PHY_STATUS"/>
+</domain>
+
+<domain name="EDP_28nm_PHY_PLL" width="32">
+ <reg32 offset="0x00000" name="REFCLK_CFG"/>
+ <reg32 offset="0x00004" name="POSTDIV1_CFG"/>
+ <reg32 offset="0x00008" name="CHGPUMP_CFG"/>
+ <reg32 offset="0x0000C" name="VCOLPF_CFG"/>
+ <reg32 offset="0x00010" name="VREG_CFG"/>
+ <reg32 offset="0x00014" name="PWRGEN_CFG"/>
+ <reg32 offset="0x00018" name="DMUX_CFG"/>
+ <reg32 offset="0x0001C" name="AMUX_CFG"/>
+ <reg32 offset="0x00020" name="GLB_CFG">
+ <bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/>
+ <bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/>
+ <bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/>
+ <bitfield name="PLL_ENABLE" pos="3" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00024" name="POSTDIV2_CFG"/>
+ <reg32 offset="0x00028" name="POSTDIV3_CFG"/>
+ <reg32 offset="0x0002C" name="LPFR_CFG"/>
+ <reg32 offset="0x00030" name="LPFC1_CFG"/>
+ <reg32 offset="0x00034" name="LPFC2_CFG"/>
+ <reg32 offset="0x00038" name="SDM_CFG0"/>
+ <reg32 offset="0x0003C" name="SDM_CFG1"/>
+ <reg32 offset="0x00040" name="SDM_CFG2"/>
+ <reg32 offset="0x00044" name="SDM_CFG3"/>
+ <reg32 offset="0x00048" name="SDM_CFG4"/>
+ <reg32 offset="0x0004C" name="SSC_CFG0"/>
+ <reg32 offset="0x00050" name="SSC_CFG1"/>
+ <reg32 offset="0x00054" name="SSC_CFG2"/>
+ <reg32 offset="0x00058" name="SSC_CFG3"/>
+ <reg32 offset="0x0005C" name="LKDET_CFG0"/>
+ <reg32 offset="0x00060" name="LKDET_CFG1"/>
+ <reg32 offset="0x00064" name="LKDET_CFG2"/>
+ <reg32 offset="0x00068" name="TEST_CFG">
+ <bitfield name="PLL_SW_RESET" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0006C" name="CAL_CFG0"/>
+ <reg32 offset="0x00070" name="CAL_CFG1"/>
+ <reg32 offset="0x00074" name="CAL_CFG2"/>
+ <reg32 offset="0x00078" name="CAL_CFG3"/>
+ <reg32 offset="0x0007C" name="CAL_CFG4"/>
+ <reg32 offset="0x00080" name="CAL_CFG5"/>
+ <reg32 offset="0x00084" name="CAL_CFG6"/>
+ <reg32 offset="0x00088" name="CAL_CFG7"/>
+ <reg32 offset="0x0008C" name="CAL_CFG8"/>
+ <reg32 offset="0x00090" name="CAL_CFG9"/>
+ <reg32 offset="0x00094" name="CAL_CFG10"/>
+ <reg32 offset="0x00098" name="CAL_CFG11"/>
+ <reg32 offset="0x0009C" name="EFUSE_CFG"/>
+ <reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/display/hdmi.xml b/drivers/gpu/drm/msm/registers/display/hdmi.xml
new file mode 100644
index 000000000000..6c81581016c7
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/display/hdmi.xml
@@ -0,0 +1,1015 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+
+<!--
+ NOTE: also see mdss_hdmi_util.h.. newer devices using MDSS appear
+ to have the same HDMI block (or maybe a newer version?) but for
+ some reason duplicate the code under drivers/video/msm/mdss
+ -->
+
+<domain name="HDMI" width="32">
+ <enum name="hdmi_hdcp_key_state">
+ <value name="HDCP_KEYS_STATE_NO_KEYS" value="0"/>
+ <value name="HDCP_KEYS_STATE_NOT_CHECKED" value="1"/>
+ <value name="HDCP_KEYS_STATE_CHECKING" value="2"/>
+ <value name="HDCP_KEYS_STATE_VALID" value="3"/>
+ <value name="HDCP_KEYS_STATE_AKSV_NOT_VALID" value="4"/>
+ <value name="HDCP_KEYS_STATE_CHKSUM_MISMATCH" value="5"/>
+ <value name="HDCP_KEYS_STATE_PROD_AKSV" value="6"/>
+ <value name="HDCP_KEYS_STATE_RESERVED" value="7"/>
+ </enum>
+ <enum name="hdmi_ddc_read_write">
+ <value name="DDC_WRITE" value="0"/>
+ <value name="DDC_READ" value="1"/>
+ </enum>
+ <enum name="hdmi_acr_cts">
+ <value name="ACR_NONE" value="0"/>
+ <value name="ACR_32" value="1"/>
+ <value name="ACR_44" value="2"/>
+ <value name="ACR_48" value="3"/>
+ </enum>
+
+ <enum name="hdmi_cec_tx_status">
+ <value name="CEC_TX_OK" value="0"/>
+ <value name="CEC_TX_NACK" value="1"/>
+ <value name="CEC_TX_ARB_LOSS" value="2"/>
+ <value name="CEC_TX_MAX_RETRIES" value="3"/>
+ </enum>
+
+ <reg32 offset="0x00000" name="CTRL">
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ <bitfield name="HDMI" pos="1" type="boolean"/>
+ <bitfield name="ENCRYPTED" pos="2" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00020" name="AUDIO_PKT_CTRL1">
+ <bitfield name="AUDIO_SAMPLE_SEND" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00024" name="ACR_PKT_CTRL">
+ <!--
+ Guessing on order of bitfields from these comments:
+ /* AUDIO_PRIORITY | SOURCE */
+ acr_pck_ctrl_reg |= 0x80000100;
+ /* N_MULTIPLE(multiplier) */
+ acr_pck_ctrl_reg |= (multiplier & 7) << 16;
+ /* SEND | CONT */
+ acr_pck_ctrl_reg |= 0x00000003;
+ -->
+ <bitfield name="CONT" pos="0" type="boolean"/>
+ <bitfield name="SEND" pos="1" type="boolean"/>
+ <bitfield name="SELECT" low="4" high="5" type="hdmi_acr_cts"/>
+ <bitfield name="SOURCE" pos="8" type="boolean"/>
+ <bitfield name="N_MULTIPLIER" low="16" high="18" type="uint"/>
+ <bitfield name="AUDIO_PRIORITY" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0028" name="VBI_PKT_CTRL">
+ <!--
+ Guessing on the order of bits from:
+ /* GC packet enable (every frame) */
+ /* HDMI_VBI_PKT_CTRL[0x0028] */
+ hdmi_msm_rmw32or(0x0028, 3 << 4);
+ /* HDMI_VBI_PKT_CTRL[0x0028] */
+ /* ISRC Send + Continuous */
+ hdmi_msm_rmw32or(0x0028, 3 << 8);
+ /* HDMI_VBI_PKT_CTRL[0x0028] */
+ /* ACP send, s/w source */
+ hdmi_msm_rmw32or(0x0028, 3 << 12);
+ -->
+ <bitfield name="GC_ENABLE" pos="4" type="boolean"/>
+ <bitfield name="GC_EVERY_FRAME" pos="5" type="boolean"/>
+ <bitfield name="ISRC_SEND" pos="8" type="boolean"/>
+ <bitfield name="ISRC_CONTINUOUS" pos="9" type="boolean"/>
+ <bitfield name="ACP_SEND" pos="12" type="boolean"/>
+ <bitfield name="ACP_SRC_SW" pos="13" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0002c" name="INFOFRAME_CTRL0">
+ <!--
+ Guessing on the order of these flags, from this comment:
+ /* Set these flags */
+ /* AUDIO_INFO_UPDATE | AUDIO_INFO_SOURCE | AUDIO_INFO_CONT
+ | AUDIO_INFO_SEND */
+ audio_info_ctrl_reg |= 0x000000F0;
+ /* 0x3 for AVI InfFrame enable (every frame) */
+ HDMI_OUTP(0x002C, HDMI_INP(0x002C) | 0x00000003L);
+ -->
+ <bitfield name="AVI_SEND" pos="0" type="boolean"/>
+ <bitfield name="AVI_CONT" pos="1" type="boolean"/> <!-- every frame -->
+ <bitfield name="AUDIO_INFO_SEND" pos="4" type="boolean"/>
+ <bitfield name="AUDIO_INFO_CONT" pos="5" type="boolean"/> <!-- every frame -->
+ <bitfield name="AUDIO_INFO_SOURCE" pos="6" type="boolean"/>
+ <bitfield name="AUDIO_INFO_UPDATE" pos="7" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00030" name="INFOFRAME_CTRL1">
+ <bitfield name="AVI_INFO_LINE" low="0" high="5" type="uint"/>
+ <bitfield name="AUDIO_INFO_LINE" low="8" high="13" type="uint"/>
+ <bitfield name="MPEG_INFO_LINE" low="16" high="21" type="uint"/>
+ <bitfield name="VENSPEC_INFO_LINE" low="24" high="29" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00034" name="GEN_PKT_CTRL">
+ <!--
+ 0x0034 GEN_PKT_CTRL
+ GENERIC0_SEND 0 0 = Disable Generic0 Packet Transmission
+ 1 = Enable Generic0 Packet Transmission
+ GENERIC0_CONT 1 0 = Send Generic0 Packet on next frame only
+ 1 = Send Generic0 Packet on every frame
+ GENERIC0_UPDATE 2 NUM
+ GENERIC1_SEND 4 0 = Disable Generic1 Packet Transmission
+ 1 = Enable Generic1 Packet Transmission
+ GENERIC1_CONT 5 0 = Send Generic1 Packet on next frame only
+ 1 = Send Generic1 Packet on every frame
+ GENERIC0_LINE 21:16 NUM
+ GENERIC1_LINE 29:24 NUM
+
+ GENERIC0_LINE | GENERIC0_UPDATE | GENERIC0_CONT | GENERIC0_SEND
+ Setup HDMI TX generic packet control
+ Enable this packet to transmit every frame
+ Enable this packet to transmit every frame
+ Enable HDMI TX engine to transmit Generic packet 0
+ HDMI_OUTP(0x0034, (1 << 16) | (1 << 2) | BIT(1) | BIT(0));
+ -->
+ <bitfield name="GENERIC0_SEND" pos="0" type="boolean"/>
+ <bitfield name="GENERIC0_CONT" pos="1" type="boolean"/>
+ <bitfield name="GENERIC0_UPDATE" low="2" high="3" type="uint"/> <!-- ??? -->
+ <bitfield name="GENERIC1_SEND" pos="4" type="boolean"/>
+ <bitfield name="GENERIC1_CONT" pos="5" type="boolean"/>
+ <bitfield name="GENERIC0_LINE" low="16" high="21" type="uint"/>
+ <bitfield name="GENERIC1_LINE" low="24" high="29" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00040" name="GC">
+ <bitfield name="MUTE" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00044" name="AUDIO_PKT_CTRL2">
+ <bitfield name="OVERRIDE" pos="0" type="boolean"/>
+ <bitfield name="LAYOUT" pos="1" type="boolean"/> <!-- 1 for >2 channels -->
+ </reg32>
+
+ <!--
+ AVI_INFO appears to be the infoframe in a slightly weird order..
+ starts with PB0 (checksum), and ends with version..
+ -->
+ <reg32 offset="0x0006c" name="AVI_INFO" stride="4" length="4"/>
+
+ <reg32 offset="0x00084" name="GENERIC0_HDR"/>
+ <reg32 offset="0x00088" name="GENERIC0" stride="4" length="7"/>
+
+ <reg32 offset="0x000a4" name="GENERIC1_HDR"/>
+ <reg32 offset="0x000a8" name="GENERIC1" stride="4" length="7"/>
+
+ <!--
+ TODO add a way to show symbolic offsets into array: hdmi_acr_cts-1
+ -->
+ <array offset="0x00c4" name="ACR" length="3" stride="8" index="hdmi_acr_cts">
+ <reg32 offset="0" name="0">
+ <bitfield name="CTS" low="12" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="4" name="1">
+ <!-- not sure the actual # of bits.. -->
+ <bitfield name="N" low="0" high="31" type="uint"/>
+ </reg32>
+ </array>
+
+ <reg32 offset="0x000e4" name="AUDIO_INFO0">
+ <bitfield name="CHECKSUM" low="0" high="7"/>
+ <bitfield name="CC" low="8" high="10" type="uint"/> <!-- channel count -->
+ </reg32>
+ <reg32 offset="0x000e8" name="AUDIO_INFO1">
+ <bitfield name="CA" low="0" high="7"/> <!-- Channel Allocation -->
+ <bitfield name="LSV" low="11" high="14"/> <!-- Level Shift -->
+ <bitfield name="DM_INH" pos="15" type="boolean"/> <!-- down-mix inhibit flag -->
+ </reg32>
+ <reg32 offset="0x00110" name="HDCP_CTRL">
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ <bitfield name="ENCRYPTION_ENABLE" pos="8" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00114" name="HDCP_DEBUG_CTRL">
+ <bitfield name="RNG_CIPHER" pos="2" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00118" name="HDCP_INT_CTRL">
+ <bitfield name="AUTH_SUCCESS_INT" pos="0" type="boolean"/>
+ <bitfield name="AUTH_SUCCESS_ACK" pos="1" type="boolean"/>
+ <bitfield name="AUTH_SUCCESS_MASK" pos="2" type="boolean"/>
+ <bitfield name="AUTH_FAIL_INT" pos="4" type="boolean"/>
+ <bitfield name="AUTH_FAIL_ACK" pos="5" type="boolean"/>
+ <bitfield name="AUTH_FAIL_MASK" pos="6" type="boolean"/>
+ <bitfield name="AUTH_FAIL_INFO_ACK" pos="7" type="boolean"/>
+ <bitfield name="AUTH_XFER_REQ_INT" pos="8" type="boolean"/>
+ <bitfield name="AUTH_XFER_REQ_ACK" pos="9" type="boolean"/>
+ <bitfield name="AUTH_XFER_REQ_MASK" pos="10" type="boolean"/>
+ <bitfield name="AUTH_XFER_DONE_INT" pos="12" type="boolean"/>
+ <bitfield name="AUTH_XFER_DONE_ACK" pos="13" type="boolean"/>
+ <bitfield name="AUTH_XFER_DONE_MASK" pos="14" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0011c" name="HDCP_LINK0_STATUS">
+ <bitfield name="AN_0_READY" pos="8" type="boolean"/>
+ <bitfield name="AN_1_READY" pos="9" type="boolean"/>
+ <bitfield name="RI_MATCHES" pos="12" type="boolean"/>
+ <bitfield name="V_MATCHES" pos="20" type="boolean"/>
+ <bitfield name="KEY_STATE" low="28" high="30" type="hdmi_hdcp_key_state"/>
+ </reg32>
+ <reg32 offset="0x00120" name="HDCP_DDC_CTRL_0">
+ <bitfield name="DISABLE" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00124" name="HDCP_DDC_CTRL_1">
+ <bitfield name="FAILED_ACK" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00128" name="HDCP_DDC_STATUS">
+ <bitfield name="XFER_REQ" pos="4" type="boolean"/>
+ <bitfield name="XFER_DONE" pos="10" type="boolean"/>
+ <bitfield name="ABORTED" pos="12" type="boolean"/>
+ <bitfield name="TIMEOUT" pos="13" type="boolean"/>
+ <bitfield name="NACK0" pos="14" type="boolean"/>
+ <bitfield name="NACK1" pos="15" type="boolean"/>
+ <bitfield name="FAILED" pos="16" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x0012c" name="HDCP_ENTROPY_CTRL0"/>
+ <reg32 offset="0x0025c" name="HDCP_ENTROPY_CTRL1"/>
+
+ <reg32 offset="0x00130" name="HDCP_RESET">
+ <bitfield name="LINK0_DEAUTHENTICATE" pos="0" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x00134" name="HDCP_RCVPORT_DATA0"/>
+ <reg32 offset="0x00138" name="HDCP_RCVPORT_DATA1"/>
+ <reg32 offset="0x0013C" name="HDCP_RCVPORT_DATA2_0"/>
+ <reg32 offset="0x00140" name="HDCP_RCVPORT_DATA2_1"/>
+ <reg32 offset="0x00144" name="HDCP_RCVPORT_DATA3"/>
+ <reg32 offset="0x00148" name="HDCP_RCVPORT_DATA4"/>
+ <reg32 offset="0x0014c" name="HDCP_RCVPORT_DATA5"/>
+ <reg32 offset="0x00150" name="HDCP_RCVPORT_DATA6"/>
+ <reg32 offset="0x00154" name="HDCP_RCVPORT_DATA7"/>
+ <reg32 offset="0x00158" name="HDCP_RCVPORT_DATA8"/>
+ <reg32 offset="0x0015c" name="HDCP_RCVPORT_DATA9"/>
+ <reg32 offset="0x00160" name="HDCP_RCVPORT_DATA10"/>
+ <reg32 offset="0x00164" name="HDCP_RCVPORT_DATA11"/>
+ <reg32 offset="0x00168" name="HDCP_RCVPORT_DATA12"/>
+
+ <reg32 offset="0x0016c" name="VENSPEC_INFO0"/>
+ <reg32 offset="0x00170" name="VENSPEC_INFO1"/>
+ <reg32 offset="0x00174" name="VENSPEC_INFO2"/>
+ <reg32 offset="0x00178" name="VENSPEC_INFO3"/>
+ <reg32 offset="0x0017c" name="VENSPEC_INFO4"/>
+ <reg32 offset="0x00180" name="VENSPEC_INFO5"/>
+ <reg32 offset="0x00184" name="VENSPEC_INFO6"/>
+
+ <reg32 offset="0x001d0" name="AUDIO_CFG">
+ <bitfield name="ENGINE_ENABLE" pos="0" type="boolean"/>
+ <bitfield name="FIFO_WATERMARK" low="4" high="7" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x00208" name="USEC_REFTIMER"/>
+ <reg32 offset="0x0020c" name="DDC_CTRL">
+ <!--
+ 0x020C HDMI_DDC_CTRL
+ [21:20] TRANSACTION_CNT
+ Number of transactions to be done in current transfer.
+ * 0x0: transaction0 only
+ * 0x1: transaction0, transaction1
+ * 0x2: transaction0, transaction1, transaction2
+ * 0x3: transaction0, transaction1, transaction2, transaction3
+ [3] SW_STATUS_RESET
+ Write 1 to reset HDMI_DDC_SW_STATUS flags, will reset SW_DONE,
+ ABORTED, TIMEOUT, SW_INTERRUPTED, BUFFER_OVERFLOW,
+ STOPPED_ON_NACK, NACK0, NACK1, NACK2, NACK3
+ [2] SEND_RESET Set to 1 to send reset sequence (9 clocks with no
+ data) at start of transfer. This sequence is sent after GO is
+ written to 1, before the first transaction only.
+ [1] SOFT_RESET Write 1 to reset DDC controller
+ [0] GO WRITE ONLY. Write 1 to start DDC transfer.
+ -->
+ <bitfield name="GO" pos="0" type="boolean"/>
+ <bitfield name="SOFT_RESET" pos="1" type="boolean"/>
+ <bitfield name="SEND_RESET" pos="2" type="boolean"/>
+ <bitfield name="SW_STATUS_RESET" pos="3" type="boolean"/>
+ <bitfield name="TRANSACTION_CNT" low="20" high="21" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00210" name="DDC_ARBITRATION">
+ <bitfield name="HW_ARBITRATION" pos="4" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00214" name="DDC_INT_CTRL">
+ <!--
+ HDMI_DDC_INT_CTRL[0x0214]
+ [2] SW_DONE_MK Mask bit for SW_DONE_INT. Set to 1 to enable
+ interrupt.
+ [1] SW_DONE_ACK WRITE ONLY. Acknowledge bit for SW_DONE_INT.
+ Write 1 to clear interrupt.
+ [0] SW_DONE_INT READ ONLY. SW_DONE interrupt status */
+ -->
+ <bitfield name="SW_DONE_INT" pos="0" type="boolean"/>
+ <bitfield name="SW_DONE_ACK" pos="1" type="boolean"/>
+ <bitfield name="SW_DONE_MASK" pos="2" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00218" name="DDC_SW_STATUS">
+ <bitfield name="NACK0" pos="12" type="boolean"/>
+ <bitfield name="NACK1" pos="13" type="boolean"/>
+ <bitfield name="NACK2" pos="14" type="boolean"/>
+ <bitfield name="NACK3" pos="15" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0021c" name="DDC_HW_STATUS">
+ <bitfield name="DONE" pos="3" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00220" name="DDC_SPEED">
+ <!--
+ 0x0220 HDMI_DDC_SPEED
+ [31:16] PRESCALE prescale = (m * xtal_frequency) /
+ (desired_i2c_speed), where m is multiply
+ factor, default: m = 1
+ [1:0] THRESHOLD Select threshold to use to determine whether value
+ sampled on SDA is a 1 or 0. Specified in terms of the ratio
+ between the number of sampled ones and the total number of times
+ SDA is sampled.
+ * 0x0: >0
+ * 0x1: 1/4 of total samples
+ * 0x2: 1/2 of total samples
+ * 0x3: 3/4 of total samples */
+ -->
+ <bitfield name="THRESHOLD" low="0" high="1" type="uint"/>
+ <bitfield name="PRESCALE" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00224" name="DDC_SETUP">
+ <!--
+ * 0x0224 HDMI_DDC_SETUP
+ * Setting 31:24 bits : Time units to wait before timeout
+ * when clock is being stalled by external sink device
+ -->
+ <bitfield name="TIMEOUT" low="24" high="31" type="uint"/>
+ </reg32>
+ <!-- Guessing length is 4, as elsewhere the are references to trans0 thru trans3 -->
+ <array offset="0x00228" name="I2C_TRANSACTION" length="4" stride="4">
+ <reg32 offset="0" name="REG">
+ <!--
+ 0x0228 HDMI_DDC_TRANS0
+ [23:16] CNT0 Byte count for first transaction (excluding the first
+ byte, which is usually the address).
+ [13] STOP0 Determines whether a stop bit will be sent after the first
+ transaction
+ * 0: NO STOP
+ * 1: STOP
+ [12] START0 Determines whether a start bit will be sent before the
+ first transaction
+ * 0: NO START
+ * 1: START
+ [8] STOP_ON_NACK0 Determines whether the current transfer will stop
+ if a NACK is received during the first transaction (current
+ transaction always stops).
+ * 0: STOP CURRENT TRANSACTION, GO TO NEXT TRANSACTION
+ * 1: STOP ALL TRANSACTIONS, SEND STOP BIT
+ [0] RW0 Read/write indicator for first transaction - set to 0 for
+ write, 1 for read. This bit only controls HDMI_DDC behaviour -
+ the R/W bit in the transaction is programmed into the DDC buffer
+ as the LSB of the address byte.
+ * 0: WRITE
+ * 1: READ
+ -->
+ <bitfield name="RW" pos="0" type="hdmi_ddc_read_write"/>
+ <bitfield name="STOP_ON_NACK" pos="8" type="boolean"/>
+ <bitfield name="START" pos="12" type="boolean"/>
+ <bitfield name="STOP" pos="13" type="boolean"/>
+ <bitfield name="CNT" low="16" high="23" type="uint"/>
+ </reg32>
+ </array>
+ <reg32 offset="0x00238" name="DDC_DATA">
+ <!--
+ 0x0238 HDMI_DDC_DATA
+ [31] INDEX_WRITE WRITE ONLY. To write index field, set this bit to
+ 1 while writing HDMI_DDC_DATA.
+ [23:16] INDEX Use to set index into DDC buffer for next read or
+ current write, or to read index of current read or next write.
+ Writable only when INDEX_WRITE=1.
+ [15:8] DATA Use to fill or read the DDC buffer
+ [0] DATA_RW Select whether buffer access will be a read or write.
+ For writes, address auto-increments on write to HDMI_DDC_DATA.
+ For reads, address autoincrements on reads to HDMI_DDC_DATA.
+ * 0: Write
+ * 1: Read
+ -->
+ <bitfield name="DATA_RW" pos="0" type="hdmi_ddc_read_write"/>
+ <bitfield name="DATA" low="8" high="15" type="uint"/>
+ <bitfield name="INDEX" low="16" high="23" type="uint"/>
+ <bitfield name="INDEX_WRITE" pos="31" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x0023c" name="HDCP_SHA_CTRL"/>
+ <reg32 offset="0x00240" name="HDCP_SHA_STATUS">
+ <bitfield name="BLOCK_DONE" pos="0" type="boolean"/>
+ <bitfield name="COMP_DONE" pos="4" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00244" name="HDCP_SHA_DATA">
+ <bitfield name="DONE" pos="0" type="boolean"/>
+ </reg32>
+
+ <reg32 offset="0x00250" name="HPD_INT_STATUS">
+ <bitfield name="INT" pos="0" type="boolean"/> <!-- an irq has occurred -->
+ <bitfield name="CABLE_DETECTED" pos="1" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00254" name="HPD_INT_CTRL">
+ <!-- (this useful comment was removed in df6b645.. git archaeology is fun)
+ HPD_INT_CTRL[0x0254]
+ 31:10 Reserved
+ 9 RCV_PLUGIN_DET_MASK receiver plug in interrupt mask.
+ When programmed to 1,
+ RCV_PLUGIN_DET_INT will toggle
+ the interrupt line
+ 8:6 Reserved
+ 5 RX_INT_EN Panel RX interrupt enable
+ 0: Disable
+ 1: Enable
+ 4 RX_INT_ACK WRITE ONLY. Panel RX interrupt
+ ack
+ 3 Reserved
+ 2 INT_EN Panel interrupt control
+ 0: Disable
+ 1: Enable
+ 1 INT_POLARITY Panel interrupt polarity
+ 0: generate interrupt on disconnect
+ 1: generate interrupt on connect
+ 0 INT_ACK WRITE ONLY. Panel interrupt ack
+ -->
+ <bitfield name="INT_ACK" pos="0" type="boolean"/>
+ <bitfield name="INT_CONNECT" pos="1" type="boolean"/>
+ <bitfield name="INT_EN" pos="2" type="boolean"/>
+ <bitfield name="RX_INT_ACK" pos="4" type="boolean"/>
+ <bitfield name="RX_INT_EN" pos="5" type="boolean"/>
+ <bitfield name="RCV_PLUGIN_DET_MASK" pos="9" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00258" name="HPD_CTRL">
+ <bitfield name="TIMEOUT" low="0" high="12" type="uint"/>
+ <bitfield name="ENABLE" pos="28" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0027c" name="DDC_REF">
+ <!--
+ 0x027C HDMI_DDC_REF
+ [16] REFTIMER_ENABLE Enable the timer
+ * 0: Disable
+ * 1: Enable
+ [15:0] REFTIMER Value to set the register in order to generate
+ DDC strobe. This register counts on HDCP application clock
+
+ /* Enable reference timer
+ * 27 micro-seconds */
+ HDMI_OUTP_ND(0x027C, (1 << 16) | (27 << 0));
+ -->
+ <bitfield name="REFTIMER_ENABLE" pos="16" type="boolean"/>
+ <bitfield name="REFTIMER" low="0" high="15" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x00284" name="HDCP_SW_UPPER_AKSV"/>
+ <reg32 offset="0x00288" name="HDCP_SW_LOWER_AKSV"/>
+
+ <reg32 offset="0x0028c" name="CEC_CTRL">
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ <bitfield name="SEND_TRIGGER" pos="1" type="boolean"/>
+ <bitfield name="FRAME_SIZE" low="4" high="8" type="uint"/>
+ <bitfield name="LINE_OE" pos="9" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00290" name="CEC_WR_DATA">
+ <bitfield name="BROADCAST" pos="0" type="boolean"/>
+ <bitfield name="DATA" low="8" high="15" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00294" name="CEC_RETRANSMIT">
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ <bitfield name="COUNT" low="1" high="7" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00298" name="CEC_STATUS">
+ <bitfield name="BUSY" pos="0" type="boolean"/>
+ <bitfield name="TX_FRAME_DONE" pos="3" type="boolean"/>
+ <bitfield name="TX_STATUS" low="4" high="7" type="hdmi_cec_tx_status"/>
+ </reg32>
+ <reg32 offset="0x0029c" name="CEC_INT">
+ <bitfield name="TX_DONE" pos="0" type="boolean"/>
+ <bitfield name="TX_DONE_MASK" pos="1" type="boolean"/>
+ <bitfield name="TX_ERROR" pos="2" type="boolean"/>
+ <bitfield name="TX_ERROR_MASK" pos="3" type="boolean"/>
+ <bitfield name="MONITOR" pos="4" type="boolean"/>
+ <bitfield name="MONITOR_MASK" pos="5" type="boolean"/>
+ <bitfield name="RX_DONE" pos="6" type="boolean"/>
+ <bitfield name="RX_DONE_MASK" pos="7" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x002a0" name="CEC_ADDR"/>
+ <reg32 offset="0x002a4" name="CEC_TIME">
+ <bitfield name="ENABLE" pos="0" type="boolean"/>
+ <bitfield name="SIGNAL_FREE_TIME" low="7" high="15" type="uint"/>
+ </reg32>
+ <reg32 offset="0x002a8" name="CEC_REFTIMER">
+ <bitfield name="REFTIMER" low="0" high="15" type="uint"/>
+ <bitfield name="ENABLE" pos="16" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x002ac" name="CEC_RD_DATA">
+ <bitfield name="DATA" low="0" high="7" type="uint"/>
+ <bitfield name="SIZE" low="8" high="12" type="uint"/>
+ </reg32>
+ <reg32 offset="0x002b0" name="CEC_RD_FILTER"/>
+
+ <reg32 offset="0x002b4" name="ACTIVE_HSYNC">
+ <bitfield name="START" low="0" high="12" type="uint"/>
+ <bitfield name="END" low="16" high="27" type="uint"/>
+ </reg32>
+ <reg32 offset="0x002b8" name="ACTIVE_VSYNC">
+ <bitfield name="START" low="0" high="12" type="uint"/>
+ <bitfield name="END" low="16" high="28" type="uint"/>
+ </reg32>
+ <reg32 offset="0x002bc" name="VSYNC_ACTIVE_F2">
+ <!-- interlaced, frame 2 -->
+ <bitfield name="START" low="0" high="12" type="uint"/>
+ <bitfield name="END" low="16" high="28" type="uint"/>
+ </reg32>
+ <reg32 offset="0x002c0" name="TOTAL">
+ <bitfield name="H_TOTAL" low="0" high="12" type="uint"/>
+ <bitfield name="V_TOTAL" low="16" high="28" type="uint"/>
+ </reg32>
+ <reg32 offset="0x002c4" name="VSYNC_TOTAL_F2">
+ <!-- interlaced, frame 2 -->
+ <bitfield name="V_TOTAL" low="0" high="12" type="uint"/>
+ </reg32>
+ <reg32 offset="0x002c8" name="FRAME_CTRL">
+ <bitfield name="RGB_MUX_SEL_BGR" pos="12" type="boolean"/>
+ <bitfield name="VSYNC_LOW" pos="28" type="boolean"/>
+ <bitfield name="HSYNC_LOW" pos="29" type="boolean"/>
+ <bitfield name="INTERLACED_EN" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x002cc" name="AUD_INT">
+ <!--
+ HDMI_AUD_INT[0x02CC]
+ [3] AUD_SAM_DROP_MASK [R/W]
+ [2] AUD_SAM_DROP_ACK [W], AUD_SAM_DROP_INT [R]
+ [1] AUD_FIFO_URUN_MASK [R/W]
+ [0] AUD_FIFO_URUN_ACK [W], AUD_FIFO_URUN_INT [R]
+ -->
+ <bitfield name="AUD_FIFO_URUN_INT" pos="0" type="boolean"/> <!-- write to ack irq -->
+ <bitfield name="AUD_FIFO_URAN_MASK" pos="1" type="boolean"/> <!-- r/w, enables irq -->
+ <bitfield name="AUD_SAM_DROP_INT" pos="2" type="boolean"/> <!-- write to ack irq -->
+ <bitfield name="AUD_SAM_DROP_MASK" pos="3" type="boolean"/> <!-- r/w, enables irq -->
+ </reg32>
+ <reg32 offset="0x002d4" name="PHY_CTRL">
+ <!--
+ in hdmi_phy_reset() it appears to be toggling SW_RESET/
+ SW_RESET_PLL based on the value of the bit above, so
+ I'm guessing the bit above is a polarit bit
+ -->
+ <bitfield name="SW_RESET_PLL" pos="0" type="boolean"/>
+ <bitfield name="SW_RESET_PLL_LOW" pos="1" type="boolean"/>
+ <bitfield name="SW_RESET" pos="2" type="boolean"/>
+ <bitfield name="SW_RESET_LOW" pos="3" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x002dc" name="CEC_WR_RANGE"/>
+ <reg32 offset="0x002e0" name="CEC_RD_RANGE"/>
+ <reg32 offset="0x002e4" name="VERSION"/>
+ <reg32 offset="0x00360" name="CEC_COMPL_CTL"/>
+ <reg32 offset="0x00364" name="CEC_RD_START_RANGE"/>
+ <reg32 offset="0x00368" name="CEC_RD_TOTAL_RANGE"/>
+ <reg32 offset="0x0036c" name="CEC_RD_ERR_RESP_LO"/>
+ <reg32 offset="0x00370" name="CEC_WR_CHECK_CONFIG"/>
+
+</domain>
+
+<domain name="HDMI_8x60" width="32">
+ <reg32 offset="0x00000" name="PHY_REG0">
+ <bitfield name="DESER_DEL_CTRL" low="2" high="4" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00004" name="PHY_REG1">
+ <bitfield name="DTEST_MUX_SEL" low="4" high="7" type="uint"/>
+ <bitfield name="OUTVOL_SWING_CTRL" low="0" high="3" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00008" name="PHY_REG2">
+ <bitfield name="PD_DESER" pos="0" type="boolean"/>
+ <bitfield name="PD_DRIVE_1" pos="1" type="boolean"/>
+ <bitfield name="PD_DRIVE_2" pos="2" type="boolean"/>
+ <bitfield name="PD_DRIVE_3" pos="3" type="boolean"/>
+ <bitfield name="PD_DRIVE_4" pos="4" type="boolean"/>
+ <bitfield name="PD_PLL" pos="5" type="boolean"/>
+ <bitfield name="PD_PWRGEN" pos="6" type="boolean"/>
+ <bitfield name="RCV_SENSE_EN" pos="7" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0000c" name="PHY_REG3">
+ <bitfield name="PLL_ENABLE" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00010" name="PHY_REG4"/>
+ <reg32 offset="0x00014" name="PHY_REG5"/>
+ <reg32 offset="0x00018" name="PHY_REG6"/>
+ <reg32 offset="0x0001c" name="PHY_REG7"/>
+ <reg32 offset="0x00020" name="PHY_REG8"/>
+ <reg32 offset="0x00024" name="PHY_REG9"/>
+ <reg32 offset="0x00028" name="PHY_REG10"/>
+ <reg32 offset="0x0002c" name="PHY_REG11"/>
+ <reg32 offset="0x00030" name="PHY_REG12">
+ <bitfield name="RETIMING_EN" pos="0" type="boolean"/>
+ <bitfield name="PLL_LOCK_DETECT_EN" pos="1" type="boolean"/>
+ <bitfield name="FORCE_LOCK" pos="4" type="boolean"/>
+ </reg32>
+</domain>
+
+<domain name="HDMI_8960" width="32">
+ <!--
+ some of the bitfields may be same as 8x60.. but no helpful comments
+ in msm_dss_io_8960.c
+ -->
+ <reg32 offset="0x00000" name="PHY_REG0"/>
+ <reg32 offset="0x00004" name="PHY_REG1"/>
+ <reg32 offset="0x00008" name="PHY_REG2"/>
+ <reg32 offset="0x0000c" name="PHY_REG3"/>
+ <reg32 offset="0x00010" name="PHY_REG4"/>
+ <reg32 offset="0x00014" name="PHY_REG5"/>
+ <reg32 offset="0x00018" name="PHY_REG6"/>
+ <reg32 offset="0x0001c" name="PHY_REG7"/>
+ <reg32 offset="0x00020" name="PHY_REG8"/>
+ <reg32 offset="0x00024" name="PHY_REG9"/>
+ <reg32 offset="0x00028" name="PHY_REG10"/>
+ <reg32 offset="0x0002c" name="PHY_REG11"/>
+ <reg32 offset="0x00030" name="PHY_REG12">
+ <bitfield name="SW_RESET" pos="5" type="boolean"/>
+ <bitfield name="PWRDN_B" pos="7" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00034" name="PHY_REG_BIST_CFG"/>
+ <reg32 offset="0x00038" name="PHY_DEBUG_BUS_SEL"/>
+ <reg32 offset="0x0003c" name="PHY_REG_MISC0"/>
+ <reg32 offset="0x00040" name="PHY_REG13"/>
+ <reg32 offset="0x00044" name="PHY_REG14"/>
+ <reg32 offset="0x00048" name="PHY_REG15"/>
+</domain>
+
+<domain name="HDMI_8960_PHY_PLL" width="32">
+ <reg32 offset="0x00000" name="REFCLK_CFG"/>
+ <reg32 offset="0x00004" name="CHRG_PUMP_CFG"/>
+ <reg32 offset="0x00008" name="LOOP_FLT_CFG0"/>
+ <reg32 offset="0x0000c" name="LOOP_FLT_CFG1"/>
+ <reg32 offset="0x00010" name="IDAC_ADJ_CFG"/>
+ <reg32 offset="0x00014" name="I_VI_KVCO_CFG"/>
+ <reg32 offset="0x00018" name="PWRDN_B">
+ <bitfield name="PD_PLL" pos="1" type="boolean"/>
+ <bitfield name="PLL_PWRDN_B" pos="3" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0001c" name="SDM_CFG0"/>
+ <reg32 offset="0x00020" name="SDM_CFG1"/>
+ <reg32 offset="0x00024" name="SDM_CFG2"/>
+ <reg32 offset="0x00028" name="SDM_CFG3"/>
+ <reg32 offset="0x0002c" name="SDM_CFG4"/>
+ <reg32 offset="0x00030" name="SSC_CFG0"/>
+ <reg32 offset="0x00034" name="SSC_CFG1"/>
+ <reg32 offset="0x00038" name="SSC_CFG2"/>
+ <reg32 offset="0x0003c" name="SSC_CFG3"/>
+ <reg32 offset="0x00040" name="LOCKDET_CFG0"/>
+ <reg32 offset="0x00044" name="LOCKDET_CFG1"/>
+ <reg32 offset="0x00048" name="LOCKDET_CFG2"/>
+ <reg32 offset="0x0004c" name="VCOCAL_CFG0"/>
+ <reg32 offset="0x00050" name="VCOCAL_CFG1"/>
+ <reg32 offset="0x00054" name="VCOCAL_CFG2"/>
+ <reg32 offset="0x00058" name="VCOCAL_CFG3"/>
+ <reg32 offset="0x0005c" name="VCOCAL_CFG4"/>
+ <reg32 offset="0x00060" name="VCOCAL_CFG5"/>
+ <reg32 offset="0x00064" name="VCOCAL_CFG6"/>
+ <reg32 offset="0x00068" name="VCOCAL_CFG7"/>
+ <reg32 offset="0x0006c" name="DEBUG_SEL"/>
+ <reg32 offset="0x00070" name="MISC0"/>
+ <reg32 offset="0x00074" name="MISC1"/>
+ <reg32 offset="0x00078" name="MISC2"/>
+ <reg32 offset="0x0007c" name="MISC3"/>
+ <reg32 offset="0x00080" name="MISC4"/>
+ <reg32 offset="0x00084" name="MISC5"/>
+ <reg32 offset="0x00088" name="MISC6"/>
+ <reg32 offset="0x0008c" name="DEBUG_BUS0"/>
+ <reg32 offset="0x00090" name="DEBUG_BUS1"/>
+ <reg32 offset="0x00094" name="DEBUG_BUS2"/>
+ <reg32 offset="0x00098" name="STATUS0">
+ <bitfield name="PLL_LOCK" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0009c" name="STATUS1"/>
+</domain>
+
+<domain name="HDMI_8x74" width="32">
+ <!--
+ seems to be all mdp5+ have same?
+ -->
+ <reg32 offset="0x00000" name="ANA_CFG0"/>
+ <reg32 offset="0x00004" name="ANA_CFG1"/>
+ <reg32 offset="0x00008" name="ANA_CFG2"/>
+ <reg32 offset="0x0000c" name="ANA_CFG3"/>
+ <reg32 offset="0x00010" name="PD_CTRL0"/>
+ <reg32 offset="0x00014" name="PD_CTRL1"/>
+ <reg32 offset="0x00018" name="GLB_CFG"/>
+ <reg32 offset="0x0001c" name="DCC_CFG0"/>
+ <reg32 offset="0x00020" name="DCC_CFG1"/>
+ <reg32 offset="0x00024" name="TXCAL_CFG0"/>
+ <reg32 offset="0x00028" name="TXCAL_CFG1"/>
+ <reg32 offset="0x0002c" name="TXCAL_CFG2"/>
+ <reg32 offset="0x00030" name="TXCAL_CFG3"/>
+ <reg32 offset="0x00034" name="BIST_CFG0"/>
+ <reg32 offset="0x0003c" name="BIST_PATN0"/>
+ <reg32 offset="0x00040" name="BIST_PATN1"/>
+ <reg32 offset="0x00044" name="BIST_PATN2"/>
+ <reg32 offset="0x00048" name="BIST_PATN3"/>
+ <reg32 offset="0x0005c" name="STATUS"/>
+</domain>
+
+<domain name="HDMI_28nm_PHY_PLL" width="32">
+ <reg32 offset="0x00000" name="REFCLK_CFG"/>
+ <reg32 offset="0x00004" name="POSTDIV1_CFG"/>
+ <reg32 offset="0x00008" name="CHGPUMP_CFG"/>
+ <reg32 offset="0x0000C" name="VCOLPF_CFG"/>
+ <reg32 offset="0x00010" name="VREG_CFG"/>
+ <reg32 offset="0x00014" name="PWRGEN_CFG"/>
+ <reg32 offset="0x00018" name="DMUX_CFG"/>
+ <reg32 offset="0x0001C" name="AMUX_CFG"/>
+ <reg32 offset="0x00020" name="GLB_CFG">
+ <bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/>
+ <bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/>
+ <bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/>
+ <bitfield name="PLL_ENABLE" pos="3" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x00024" name="POSTDIV2_CFG"/>
+ <reg32 offset="0x00028" name="POSTDIV3_CFG"/>
+ <reg32 offset="0x0002C" name="LPFR_CFG"/>
+ <reg32 offset="0x00030" name="LPFC1_CFG"/>
+ <reg32 offset="0x00034" name="LPFC2_CFG"/>
+ <reg32 offset="0x00038" name="SDM_CFG0"/>
+ <reg32 offset="0x0003C" name="SDM_CFG1"/>
+ <reg32 offset="0x00040" name="SDM_CFG2"/>
+ <reg32 offset="0x00044" name="SDM_CFG3"/>
+ <reg32 offset="0x00048" name="SDM_CFG4"/>
+ <reg32 offset="0x0004C" name="SSC_CFG0"/>
+ <reg32 offset="0x00050" name="SSC_CFG1"/>
+ <reg32 offset="0x00054" name="SSC_CFG2"/>
+ <reg32 offset="0x00058" name="SSC_CFG3"/>
+ <reg32 offset="0x0005C" name="LKDET_CFG0"/>
+ <reg32 offset="0x00060" name="LKDET_CFG1"/>
+ <reg32 offset="0x00064" name="LKDET_CFG2"/>
+ <reg32 offset="0x00068" name="TEST_CFG">
+ <bitfield name="PLL_SW_RESET" pos="0" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0006C" name="CAL_CFG0"/>
+ <reg32 offset="0x00070" name="CAL_CFG1"/>
+ <reg32 offset="0x00074" name="CAL_CFG2"/>
+ <reg32 offset="0x00078" name="CAL_CFG3"/>
+ <reg32 offset="0x0007C" name="CAL_CFG4"/>
+ <reg32 offset="0x00080" name="CAL_CFG5"/>
+ <reg32 offset="0x00084" name="CAL_CFG6"/>
+ <reg32 offset="0x00088" name="CAL_CFG7"/>
+ <reg32 offset="0x0008C" name="CAL_CFG8"/>
+ <reg32 offset="0x00090" name="CAL_CFG9"/>
+ <reg32 offset="0x00094" name="CAL_CFG10"/>
+ <reg32 offset="0x00098" name="CAL_CFG11"/>
+ <reg32 offset="0x0009C" name="EFUSE_CFG"/>
+ <reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/>
+ <reg32 offset="0x000C0" name="STATUS"/>
+</domain>
+
+<domain name="HDMI_8996_PHY" width="32">
+ <reg32 offset="0x00000" name="CFG"/>
+ <reg32 offset="0x00004" name="PD_CTL"/>
+ <reg32 offset="0x00008" name="MODE"/>
+ <reg32 offset="0x0000C" name="MISR_CLEAR"/>
+ <reg32 offset="0x00010" name="TX0_TX1_BIST_CFG0"/>
+ <reg32 offset="0x00014" name="TX0_TX1_BIST_CFG1"/>
+ <reg32 offset="0x00018" name="TX0_TX1_PRBS_SEED_BYTE0"/>
+ <reg32 offset="0x0001C" name="TX0_TX1_PRBS_SEED_BYTE1"/>
+ <reg32 offset="0x00020" name="TX0_TX1_BIST_PATTERN0"/>
+ <reg32 offset="0x00024" name="TX0_TX1_BIST_PATTERN1"/>
+ <reg32 offset="0x00028" name="TX2_TX3_BIST_CFG0"/>
+ <reg32 offset="0x0002C" name="TX2_TX3_BIST_CFG1"/>
+ <reg32 offset="0x00030" name="TX2_TX3_PRBS_SEED_BYTE0"/>
+ <reg32 offset="0x00034" name="TX2_TX3_PRBS_SEED_BYTE1"/>
+ <reg32 offset="0x00038" name="TX2_TX3_BIST_PATTERN0"/>
+ <reg32 offset="0x0003C" name="TX2_TX3_BIST_PATTERN1"/>
+ <reg32 offset="0x00040" name="DEBUG_BUS_SEL"/>
+ <reg32 offset="0x00044" name="TXCAL_CFG0"/>
+ <reg32 offset="0x00048" name="TXCAL_CFG1"/>
+ <reg32 offset="0x0004C" name="TX0_TX1_LANE_CTL"/>
+ <reg32 offset="0x00050" name="TX2_TX3_LANE_CTL"/>
+ <reg32 offset="0x00054" name="LANE_BIST_CONFIG"/>
+ <reg32 offset="0x00058" name="CLOCK"/>
+ <reg32 offset="0x0005C" name="MISC1"/>
+ <reg32 offset="0x00060" name="MISC2"/>
+ <reg32 offset="0x00064" name="TX0_TX1_BIST_STATUS0"/>
+ <reg32 offset="0x00068" name="TX0_TX1_BIST_STATUS1"/>
+ <reg32 offset="0x0006C" name="TX0_TX1_BIST_STATUS2"/>
+ <reg32 offset="0x00070" name="TX2_TX3_BIST_STATUS0"/>
+ <reg32 offset="0x00074" name="TX2_TX3_BIST_STATUS1"/>
+ <reg32 offset="0x00078" name="TX2_TX3_BIST_STATUS2"/>
+ <reg32 offset="0x0007C" name="PRE_MISR_STATUS0"/>
+ <reg32 offset="0x00080" name="PRE_MISR_STATUS1"/>
+ <reg32 offset="0x00084" name="PRE_MISR_STATUS2"/>
+ <reg32 offset="0x00088" name="PRE_MISR_STATUS3"/>
+ <reg32 offset="0x0008C" name="POST_MISR_STATUS0"/>
+ <reg32 offset="0x00090" name="POST_MISR_STATUS1"/>
+ <reg32 offset="0x00094" name="POST_MISR_STATUS2"/>
+ <reg32 offset="0x00098" name="POST_MISR_STATUS3"/>
+ <reg32 offset="0x0009C" name="STATUS"/>
+ <reg32 offset="0x000A0" name="MISC3_STATUS"/>
+ <reg32 offset="0x000A4" name="MISC4_STATUS"/>
+ <reg32 offset="0x000A8" name="DEBUG_BUS0"/>
+ <reg32 offset="0x000AC" name="DEBUG_BUS1"/>
+ <reg32 offset="0x000B0" name="DEBUG_BUS2"/>
+ <reg32 offset="0x000B4" name="DEBUG_BUS3"/>
+ <reg32 offset="0x000B8" name="PHY_REVISION_ID0"/>
+ <reg32 offset="0x000BC" name="PHY_REVISION_ID1"/>
+ <reg32 offset="0x000C0" name="PHY_REVISION_ID2"/>
+ <reg32 offset="0x000C4" name="PHY_REVISION_ID3"/>
+</domain>
+
+<domain name="HDMI_PHY_QSERDES_COM" width="32">
+ <reg32 offset="0x00000" name="ATB_SEL1"/>
+ <reg32 offset="0x00004" name="ATB_SEL2"/>
+ <reg32 offset="0x00008" name="FREQ_UPDATE"/>
+ <reg32 offset="0x0000C" name="BG_TIMER"/>
+ <reg32 offset="0x00010" name="SSC_EN_CENTER"/>
+ <reg32 offset="0x00014" name="SSC_ADJ_PER1"/>
+ <reg32 offset="0x00018" name="SSC_ADJ_PER2"/>
+ <reg32 offset="0x0001C" name="SSC_PER1"/>
+ <reg32 offset="0x00020" name="SSC_PER2"/>
+ <reg32 offset="0x00024" name="SSC_STEP_SIZE1"/>
+ <reg32 offset="0x00028" name="SSC_STEP_SIZE2"/>
+ <reg32 offset="0x0002C" name="POST_DIV"/>
+ <reg32 offset="0x00030" name="POST_DIV_MUX"/>
+ <reg32 offset="0x00034" name="BIAS_EN_CLKBUFLR_EN"/>
+ <reg32 offset="0x00038" name="CLK_ENABLE1"/>
+ <reg32 offset="0x0003C" name="SYS_CLK_CTRL"/>
+ <reg32 offset="0x00040" name="SYSCLK_BUF_ENABLE"/>
+ <reg32 offset="0x00044" name="PLL_EN"/>
+ <reg32 offset="0x00048" name="PLL_IVCO"/>
+ <reg32 offset="0x0004C" name="LOCK_CMP1_MODE0"/>
+ <reg32 offset="0x00050" name="LOCK_CMP2_MODE0"/>
+ <reg32 offset="0x00054" name="LOCK_CMP3_MODE0"/>
+ <reg32 offset="0x00058" name="LOCK_CMP1_MODE1"/>
+ <reg32 offset="0x0005C" name="LOCK_CMP2_MODE1"/>
+ <reg32 offset="0x00060" name="LOCK_CMP3_MODE1"/>
+ <reg32 offset="0x00064" name="LOCK_CMP1_MODE2"/>
+ <reg32 offset="0x00064" name="CMN_RSVD0"/>
+ <reg32 offset="0x00068" name="LOCK_CMP2_MODE2"/>
+ <reg32 offset="0x00068" name="EP_CLOCK_DETECT_CTRL"/>
+ <reg32 offset="0x0006C" name="LOCK_CMP3_MODE2"/>
+ <reg32 offset="0x0006C" name="SYSCLK_DET_COMP_STATUS"/>
+ <reg32 offset="0x00070" name="BG_TRIM"/>
+ <reg32 offset="0x00074" name="CLK_EP_DIV"/>
+ <reg32 offset="0x00078" name="CP_CTRL_MODE0"/>
+ <reg32 offset="0x0007C" name="CP_CTRL_MODE1"/>
+ <reg32 offset="0x00080" name="CP_CTRL_MODE2"/>
+ <reg32 offset="0x00080" name="CMN_RSVD1"/>
+ <reg32 offset="0x00084" name="PLL_RCTRL_MODE0"/>
+ <reg32 offset="0x00088" name="PLL_RCTRL_MODE1"/>
+ <reg32 offset="0x0008C" name="PLL_RCTRL_MODE2"/>
+ <reg32 offset="0x0008C" name="CMN_RSVD2"/>
+ <reg32 offset="0x00090" name="PLL_CCTRL_MODE0"/>
+ <reg32 offset="0x00094" name="PLL_CCTRL_MODE1"/>
+ <reg32 offset="0x00098" name="PLL_CCTRL_MODE2"/>
+ <reg32 offset="0x00098" name="CMN_RSVD3"/>
+ <reg32 offset="0x0009C" name="PLL_CNTRL"/>
+ <reg32 offset="0x000A0" name="PHASE_SEL_CTRL"/>
+ <reg32 offset="0x000A4" name="PHASE_SEL_DC"/>
+ <reg32 offset="0x000A8" name="CORE_CLK_IN_SYNC_SEL"/>
+ <reg32 offset="0x000A8" name="BIAS_EN_CTRL_BY_PSM"/>
+ <reg32 offset="0x000AC" name="SYSCLK_EN_SEL"/>
+ <reg32 offset="0x000B0" name="CML_SYSCLK_SEL"/>
+ <reg32 offset="0x000B4" name="RESETSM_CNTRL"/>
+ <reg32 offset="0x000B8" name="RESETSM_CNTRL2"/>
+ <reg32 offset="0x000BC" name="RESTRIM_CTRL"/>
+ <reg32 offset="0x000C0" name="RESTRIM_CTRL2"/>
+ <reg32 offset="0x000C4" name="RESCODE_DIV_NUM"/>
+ <reg32 offset="0x000C8" name="LOCK_CMP_EN"/>
+ <reg32 offset="0x000CC" name="LOCK_CMP_CFG"/>
+ <reg32 offset="0x000D0" name="DEC_START_MODE0"/>
+ <reg32 offset="0x000D4" name="DEC_START_MODE1"/>
+ <reg32 offset="0x000D8" name="DEC_START_MODE2"/>
+ <reg32 offset="0x000D8" name="VCOCAL_DEADMAN_CTRL"/>
+ <reg32 offset="0x000DC" name="DIV_FRAC_START1_MODE0"/>
+ <reg32 offset="0x000E0" name="DIV_FRAC_START2_MODE0"/>
+ <reg32 offset="0x000E4" name="DIV_FRAC_START3_MODE0"/>
+ <reg32 offset="0x000E8" name="DIV_FRAC_START1_MODE1"/>
+ <reg32 offset="0x000EC" name="DIV_FRAC_START2_MODE1"/>
+ <reg32 offset="0x000F0" name="DIV_FRAC_START3_MODE1"/>
+ <reg32 offset="0x000F4" name="DIV_FRAC_START1_MODE2"/>
+ <reg32 offset="0x000F4" name="VCO_TUNE_MINVAL1"/>
+ <reg32 offset="0x000F8" name="DIV_FRAC_START2_MODE2"/>
+ <reg32 offset="0x000F8" name="VCO_TUNE_MINVAL2"/>
+ <reg32 offset="0x000FC" name="DIV_FRAC_START3_MODE2"/>
+ <reg32 offset="0x000FC" name="CMN_RSVD4"/>
+ <reg32 offset="0x00100" name="INTEGLOOP_INITVAL"/>
+ <reg32 offset="0x00104" name="INTEGLOOP_EN"/>
+ <reg32 offset="0x00108" name="INTEGLOOP_GAIN0_MODE0"/>
+ <reg32 offset="0x0010C" name="INTEGLOOP_GAIN1_MODE0"/>
+ <reg32 offset="0x00110" name="INTEGLOOP_GAIN0_MODE1"/>
+ <reg32 offset="0x00114" name="INTEGLOOP_GAIN1_MODE1"/>
+ <reg32 offset="0x00118" name="INTEGLOOP_GAIN0_MODE2"/>
+ <reg32 offset="0x00118" name="VCO_TUNE_MAXVAL1"/>
+ <reg32 offset="0x0011C" name="INTEGLOOP_GAIN1_MODE2"/>
+ <reg32 offset="0x0011C" name="VCO_TUNE_MAXVAL2"/>
+ <reg32 offset="0x00120" name="RES_TRIM_CONTROL2"/>
+ <reg32 offset="0x00124" name="VCO_TUNE_CTRL"/>
+ <reg32 offset="0x00128" name="VCO_TUNE_MAP"/>
+ <reg32 offset="0x0012C" name="VCO_TUNE1_MODE0"/>
+ <reg32 offset="0x00130" name="VCO_TUNE2_MODE0"/>
+ <reg32 offset="0x00134" name="VCO_TUNE1_MODE1"/>
+ <reg32 offset="0x00138" name="VCO_TUNE2_MODE1"/>
+ <reg32 offset="0x0013C" name="VCO_TUNE1_MODE2"/>
+ <reg32 offset="0x0013C" name="VCO_TUNE_INITVAL1"/>
+ <reg32 offset="0x00140" name="VCO_TUNE2_MODE2"/>
+ <reg32 offset="0x00140" name="VCO_TUNE_INITVAL2"/>
+ <reg32 offset="0x00144" name="VCO_TUNE_TIMER1"/>
+ <reg32 offset="0x00148" name="VCO_TUNE_TIMER2"/>
+ <reg32 offset="0x0014C" name="SAR"/>
+ <reg32 offset="0x00150" name="SAR_CLK"/>
+ <reg32 offset="0x00154" name="SAR_CODE_OUT_STATUS"/>
+ <reg32 offset="0x00158" name="SAR_CODE_READY_STATUS"/>
+ <reg32 offset="0x0015C" name="CMN_STATUS"/>
+ <reg32 offset="0x00160" name="RESET_SM_STATUS"/>
+ <reg32 offset="0x00164" name="RESTRIM_CODE_STATUS"/>
+ <reg32 offset="0x00168" name="PLLCAL_CODE1_STATUS"/>
+ <reg32 offset="0x0016C" name="PLLCAL_CODE2_STATUS"/>
+ <reg32 offset="0x00170" name="BG_CTRL"/>
+ <reg32 offset="0x00174" name="CLK_SELECT"/>
+ <reg32 offset="0x00178" name="HSCLK_SEL"/>
+ <reg32 offset="0x0017C" name="INTEGLOOP_BINCODE_STATUS"/>
+ <reg32 offset="0x00180" name="PLL_ANALOG"/>
+ <reg32 offset="0x00184" name="CORECLK_DIV"/>
+ <reg32 offset="0x00188" name="SW_RESET"/>
+ <reg32 offset="0x0018C" name="CORE_CLK_EN"/>
+ <reg32 offset="0x00190" name="C_READY_STATUS"/>
+ <reg32 offset="0x00194" name="CMN_CONFIG"/>
+ <reg32 offset="0x00198" name="CMN_RATE_OVERRIDE"/>
+ <reg32 offset="0x0019C" name="SVS_MODE_CLK_SEL"/>
+ <reg32 offset="0x001A0" name="DEBUG_BUS0"/>
+ <reg32 offset="0x001A4" name="DEBUG_BUS1"/>
+ <reg32 offset="0x001A8" name="DEBUG_BUS2"/>
+ <reg32 offset="0x001AC" name="DEBUG_BUS3"/>
+ <reg32 offset="0x001B0" name="DEBUG_BUS_SEL"/>
+ <reg32 offset="0x001B4" name="CMN_MISC1"/>
+ <reg32 offset="0x001B8" name="CMN_MISC2"/>
+ <reg32 offset="0x001BC" name="CORECLK_DIV_MODE1"/>
+ <reg32 offset="0x001C0" name="CORECLK_DIV_MODE2"/>
+ <reg32 offset="0x001C4" name="CMN_RSVD5"/>
+</domain>
+
+
+<domain name="HDMI_PHY_QSERDES_TX_LX" width="32">
+ <reg32 offset="0x00000" name="BIST_MODE_LANENO"/>
+ <reg32 offset="0x00004" name="BIST_INVERT"/>
+ <reg32 offset="0x00008" name="CLKBUF_ENABLE"/>
+ <reg32 offset="0x0000C" name="CMN_CONTROL_ONE"/>
+ <reg32 offset="0x00010" name="CMN_CONTROL_TWO"/>
+ <reg32 offset="0x00014" name="CMN_CONTROL_THREE"/>
+ <reg32 offset="0x00018" name="TX_EMP_POST1_LVL"/>
+ <reg32 offset="0x0001C" name="TX_POST2_EMPH"/>
+ <reg32 offset="0x00020" name="TX_BOOST_LVL_UP_DN"/>
+ <reg32 offset="0x00024" name="HP_PD_ENABLES"/>
+ <reg32 offset="0x00028" name="TX_IDLE_LVL_LARGE_AMP"/>
+ <reg32 offset="0x0002C" name="TX_DRV_LVL"/>
+ <reg32 offset="0x00030" name="TX_DRV_LVL_OFFSET"/>
+ <reg32 offset="0x00034" name="RESET_TSYNC_EN"/>
+ <reg32 offset="0x00038" name="PRE_STALL_LDO_BOOST_EN"/>
+ <reg32 offset="0x0003C" name="TX_BAND"/>
+ <reg32 offset="0x00040" name="SLEW_CNTL"/>
+ <reg32 offset="0x00044" name="INTERFACE_SELECT"/>
+ <reg32 offset="0x00048" name="LPB_EN"/>
+ <reg32 offset="0x0004C" name="RES_CODE_LANE_TX"/>
+ <reg32 offset="0x00050" name="RES_CODE_LANE_RX"/>
+ <reg32 offset="0x00054" name="RES_CODE_LANE_OFFSET"/>
+ <reg32 offset="0x00058" name="PERL_LENGTH1"/>
+ <reg32 offset="0x0005C" name="PERL_LENGTH2"/>
+ <reg32 offset="0x00060" name="SERDES_BYP_EN_OUT"/>
+ <reg32 offset="0x00064" name="DEBUG_BUS_SEL"/>
+ <reg32 offset="0x00068" name="HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN"/>
+ <reg32 offset="0x0006C" name="TX_POL_INV"/>
+ <reg32 offset="0x00070" name="PARRATE_REC_DETECT_IDLE_EN"/>
+ <reg32 offset="0x00074" name="BIST_PATTERN1"/>
+ <reg32 offset="0x00078" name="BIST_PATTERN2"/>
+ <reg32 offset="0x0007C" name="BIST_PATTERN3"/>
+ <reg32 offset="0x00080" name="BIST_PATTERN4"/>
+ <reg32 offset="0x00084" name="BIST_PATTERN5"/>
+ <reg32 offset="0x00088" name="BIST_PATTERN6"/>
+ <reg32 offset="0x0008C" name="BIST_PATTERN7"/>
+ <reg32 offset="0x00090" name="BIST_PATTERN8"/>
+ <reg32 offset="0x00094" name="LANE_MODE"/>
+ <reg32 offset="0x00098" name="IDAC_CAL_LANE_MODE"/>
+ <reg32 offset="0x0009C" name="IDAC_CAL_LANE_MODE_CONFIGURATION"/>
+ <reg32 offset="0x000A0" name="ATB_SEL1"/>
+ <reg32 offset="0x000A4" name="ATB_SEL2"/>
+ <reg32 offset="0x000A8" name="RCV_DETECT_LVL"/>
+ <reg32 offset="0x000AC" name="RCV_DETECT_LVL_2"/>
+ <reg32 offset="0x000B0" name="PRBS_SEED1"/>
+ <reg32 offset="0x000B4" name="PRBS_SEED2"/>
+ <reg32 offset="0x000B8" name="PRBS_SEED3"/>
+ <reg32 offset="0x000BC" name="PRBS_SEED4"/>
+ <reg32 offset="0x000C0" name="RESET_GEN"/>
+ <reg32 offset="0x000C4" name="RESET_GEN_MUXES"/>
+ <reg32 offset="0x000C8" name="TRAN_DRVR_EMP_EN"/>
+ <reg32 offset="0x000CC" name="TX_INTERFACE_MODE"/>
+ <reg32 offset="0x000D0" name="PWM_CTRL"/>
+ <reg32 offset="0x000D4" name="PWM_ENCODED_OR_DATA"/>
+ <reg32 offset="0x000D8" name="PWM_GEAR_1_DIVIDER_BAND2"/>
+ <reg32 offset="0x000DC" name="PWM_GEAR_2_DIVIDER_BAND2"/>
+ <reg32 offset="0x000E0" name="PWM_GEAR_3_DIVIDER_BAND2"/>
+ <reg32 offset="0x000E4" name="PWM_GEAR_4_DIVIDER_BAND2"/>
+ <reg32 offset="0x000E8" name="PWM_GEAR_1_DIVIDER_BAND0_1"/>
+ <reg32 offset="0x000EC" name="PWM_GEAR_2_DIVIDER_BAND0_1"/>
+ <reg32 offset="0x000F0" name="PWM_GEAR_3_DIVIDER_BAND0_1"/>
+ <reg32 offset="0x000F4" name="PWM_GEAR_4_DIVIDER_BAND0_1"/>
+ <reg32 offset="0x000F8" name="VMODE_CTRL1"/>
+ <reg32 offset="0x000FC" name="VMODE_CTRL2"/>
+ <reg32 offset="0x00100" name="TX_ALOG_INTF_OBSV_CNTL"/>
+ <reg32 offset="0x00104" name="BIST_STATUS"/>
+ <reg32 offset="0x00108" name="BIST_ERROR_COUNT1"/>
+ <reg32 offset="0x0010C" name="BIST_ERROR_COUNT2"/>
+ <reg32 offset="0x00110" name="TX_ALOG_INTF_OBSV"/>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/display/mdp4.xml b/drivers/gpu/drm/msm/registers/display/mdp4.xml
new file mode 100644
index 000000000000..6abb4a3c04da
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/display/mdp4.xml
@@ -0,0 +1,504 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+<import file="display/mdp_common.xml"/>
+
+<domain name="MDP4" width="32">
+ <enum name="mdp4_pipe">
+ <brief>pipe names, index into PIPE[]</brief>
+ <value name="VG1" value="0"/>
+ <value name="VG2" value="1"/>
+ <value name="RGB1" value="2"/>
+ <value name="RGB2" value="3"/>
+ <value name="RGB3" value="4"/>
+ <value name="VG3" value="5"/>
+ <value name="VG4" value="6"/>
+ </enum>
+
+ <enum name="mdp4_mixer">
+ <value name="MIXER0" value="0"/>
+ <value name="MIXER1" value="1"/>
+ <value name="MIXER2" value="2"/>
+ </enum>
+
+ <enum name="mdp4_intf">
+ <!--
+ A bit confusing the enums for interface selection:
+ enum {
+ LCDC_RGB_INTF, /* 0 */
+ DTV_INTF = LCDC_RGB_INTF, /* 0 */
+ MDDI_LCDC_INTF, /* 1 */
+ MDDI_INTF, /* 2 */
+ EBI2_INTF, /* 3 */
+ TV_INTF = EBI2_INTF, /* 3 */
+ DSI_VIDEO_INTF,
+ DSI_CMD_INTF
+ };
+ there is some overlap, and not all the values end up getting
+ written to hw (mdp4_display_intf_sel() remaps the last two
+ values to MDDI_LCDC_INTF/MDDI_INTF with extra bits set).. so
+ taking some liberties in guessing the actual meanings/names:
+ -->
+ <value name="INTF_LCDC_DTV" value="0"/> <!-- LCDC RGB or DTV (external) -->
+ <value name="INTF_DSI_VIDEO" value="1"/>
+ <value name="INTF_DSI_CMD" value="2"/>
+ <value name="INTF_EBI2_TV" value="3"/> <!-- EBI2 or TV (external) -->
+ </enum>
+ <enum name="mdp4_cursor_format">
+ <value name="CURSOR_ARGB" value="1"/>
+ <value name="CURSOR_XRGB" value="2"/>
+ </enum>
+ <enum name="mdp4_frame_format">
+ <value name="FRAME_LINEAR" value="0"/>
+ <value name="FRAME_TILE_ARGB_4X4" value="1"/>
+ <value name="FRAME_TILE_YCBCR_420" value="2"/>
+ </enum>
+ <enum name="mdp4_scale_unit">
+ <value name="SCALE_FIR" value="0"/>
+ <value name="SCALE_MN_PHASE" value="1"/>
+ <value name="SCALE_PIXEL_RPT" value="2"/>
+ </enum>
+
+ <bitset name="mdp4_layermixer_in_cfg" inline="yes">
+ <brief>appears to map pipe to mixer stage</brief>
+ <bitfield name="PIPE0" low="0" high="2" type="mdp_mixer_stage_id"/>
+ <bitfield name="PIPE0_MIXER1" pos="3" type="boolean"/>
+ <bitfield name="PIPE1" low="4" high="6" type="mdp_mixer_stage_id"/>
+ <bitfield name="PIPE1_MIXER1" pos="7" type="boolean"/>
+ <bitfield name="PIPE2" low="8" high="10" type="mdp_mixer_stage_id"/>
+ <bitfield name="PIPE2_MIXER1" pos="11" type="boolean"/>
+ <bitfield name="PIPE3" low="12" high="14" type="mdp_mixer_stage_id"/>
+ <bitfield name="PIPE3_MIXER1" pos="15" type="boolean"/>
+ <bitfield name="PIPE4" low="16" high="18" type="mdp_mixer_stage_id"/>
+ <bitfield name="PIPE4_MIXER1" pos="19" type="boolean"/>
+ <bitfield name="PIPE5" low="20" high="22" type="mdp_mixer_stage_id"/>
+ <bitfield name="PIPE5_MIXER1" pos="23" type="boolean"/>
+ <bitfield name="PIPE6" low="24" high="26" type="mdp_mixer_stage_id"/>
+ <bitfield name="PIPE6_MIXER1" pos="27" type="boolean"/>
+ <bitfield name="PIPE7" low="28" high="30" type="mdp_mixer_stage_id"/>
+ <bitfield name="PIPE7_MIXER1" pos="31" type="boolean"/>
+ </bitset>
+
+ <bitset name="MDP4_IRQ">
+ <bitfield name="OVERLAY0_DONE" pos="0" type="boolean"/>
+ <bitfield name="OVERLAY1_DONE" pos="1" type="boolean"/>
+ <bitfield name="DMA_S_DONE" pos="2" type="boolean"/>
+ <bitfield name="DMA_E_DONE" pos="3" type="boolean"/>
+ <bitfield name="DMA_P_DONE" pos="4" type="boolean"/>
+ <bitfield name="VG1_HISTOGRAM" pos="5" type="boolean"/>
+ <bitfield name="VG2_HISTOGRAM" pos="6" type="boolean"/>
+ <bitfield name="PRIMARY_VSYNC" pos="7" type="boolean"/>
+ <bitfield name="PRIMARY_INTF_UDERRUN" pos="8" type="boolean"/>
+ <bitfield name="EXTERNAL_VSYNC" pos="9" type="boolean"/>
+ <bitfield name="EXTERNAL_INTF_UDERRUN" pos="10" type="boolean"/>
+ <bitfield name="PRIMARY_RDPTR" pos="11" type="boolean"/> <!-- read pointer -->
+ <bitfield name="DMA_P_HISTOGRAM" pos="17" type="boolean"/>
+ <bitfield name="DMA_S_HISTOGRAM" pos="26" type="boolean"/>
+ <bitfield name="OVERLAY2_DONE" pos="30" type="boolean"/>
+ </bitset>
+
+ <reg32 offset="0x00000" name="VERSION">
+ <!--
+ from mdp_probe() we can see minor rev starts at 16.. assume
+ major is above that.. not sure the rest of bits but doesn't
+ really seem to matter
+ -->
+ <bitfield name="MINOR" low="16" high="23" type="uint"/>
+ <bitfield name="MAJOR" low="24" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00004" name="OVLP0_KICK"/>
+ <reg32 offset="0x00008" name="OVLP1_KICK"/>
+ <reg32 offset="0x000d0" name="OVLP2_KICK"/>
+ <reg32 offset="0x0000c" name="DMA_P_KICK"/>
+ <reg32 offset="0x00010" name="DMA_S_KICK"/>
+ <reg32 offset="0x00014" name="DMA_E_KICK"/>
+ <reg32 offset="0x00018" name="DISP_STATUS"/>
+
+ <reg32 offset="0x00038" name="DISP_INTF_SEL">
+ <bitfield name="PRIM" low="0" high="1" type="mdp4_intf"/>
+ <bitfield name="SEC" low="2" high="3" type="mdp4_intf"/>
+ <bitfield name="EXT" low="4" high="5" type="mdp4_intf"/>
+ <bitfield name="DSI_VIDEO" pos="6" type="boolean"/>
+ <bitfield name="DSI_CMD" pos="7" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0003c" name="RESET_STATUS"/> <!-- only mdp4 >v2.1 -->
+ <reg32 offset="0x0004c" name="READ_CNFG"/> <!-- something about # of pending requests.. -->
+ <reg32 offset="0x00050" name="INTR_ENABLE" type="MDP4_IRQ"/>
+ <reg32 offset="0x00054" name="INTR_STATUS" type="MDP4_IRQ"/>
+ <reg32 offset="0x00058" name="INTR_CLEAR" type="MDP4_IRQ"/>
+ <reg32 offset="0x00060" name="EBI2_LCD0"/>
+ <reg32 offset="0x00064" name="EBI2_LCD1"/>
+ <reg32 offset="0x00070" name="PORTMAP_MODE"/>
+
+ <!-- mdp chip-select controller: -->
+ <reg32 offset="0x000c0" name="CS_CONTROLLER0"/>
+ <reg32 offset="0x000c4" name="CS_CONTROLLER1"/>
+
+ <reg32 offset="0x100f0" name="LAYERMIXER2_IN_CFG" type="mdp4_layermixer_in_cfg"/>
+ <reg32 offset="0x100fc" name="LAYERMIXER_IN_CFG_UPDATE_METHOD"/>
+ <reg32 offset="0x10100" name="LAYERMIXER_IN_CFG" type="mdp4_layermixer_in_cfg"/>
+
+ <reg32 offset="0x30050" name="VG2_SRC_FORMAT"/>
+ <reg32 offset="0x31008" name="VG2_CONST_COLOR"/>
+
+ <reg32 offset="0x18000" name="OVERLAY_FLUSH">
+ <bitfield name="OVLP0" pos="0" type="boolean"/>
+ <bitfield name="OVLP1" pos="1" type="boolean"/>
+ <bitfield name="VG1" pos="2" type="boolean"/>
+ <bitfield name="VG2" pos="3" type="boolean"/>
+ <bitfield name="RGB1" pos="4" type="boolean"/>
+ <bitfield name="RGB2" pos="5" type="boolean"/>
+ </reg32>
+
+ <array offsets="0x10000,0x18000,0x88000" name="OVLP" length="3" stride="0x8000">
+ <reg32 offset="0x0004" name="CFG"/>
+ <reg32 offset="0x0008" name="SIZE" type="reg_wh"/>
+ <reg32 offset="0x000c" name="BASE"/>
+ <reg32 offset="0x0010" name="STRIDE" type="uint"/>
+ <reg32 offset="0x0014" name="OPMODE"/>
+
+ <array offsets="0x0104,0x0124,0x0144,0x0160" name="STAGE" length="4" stride="0x1c">
+ <reg32 offset="0x00" name="OP">
+ <bitfield name="FG_ALPHA" low="0" high="1" type="mdp_alpha_type"/>
+ <bitfield name="FG_INV_ALPHA" pos="2" type="boolean"/>
+ <bitfield name="FG_MOD_ALPHA" pos="3" type="boolean"/>
+ <bitfield name="BG_ALPHA" low="4" high="5" type="mdp_alpha_type"/>
+ <bitfield name="BG_INV_ALPHA" pos="6" type="boolean"/>
+ <bitfield name="BG_MOD_ALPHA" pos="7" type="boolean"/>
+ <bitfield name="FG_TRANSP" pos="8" type="boolean"/>
+ <bitfield name="BG_TRANSP" pos="9" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x04" name="FG_ALPHA"/>
+ <reg32 offset="0x08" name="BG_ALPHA"/>
+ <reg32 offset="0x0c" name="TRANSP_LOW0"/>
+ <reg32 offset="0x10" name="TRANSP_LOW1"/>
+ <reg32 offset="0x14" name="TRANSP_HIGH0"/>
+ <reg32 offset="0x18" name="TRANSP_HIGH1"/>
+ </array>
+
+ <array offsets="0x1004,0x1404,0x1804,0x1b84" name="STAGE_CO3" length="4" stride="4">
+ <reg32 offset="0" name="SEL">
+ <bitfield name="FG_ALPHA" pos="0" type="boolean"/> <!-- otherwise bg alpha -->
+ </reg32>
+ </array>
+
+ <reg32 offset="0x0180" name="TRANSP_LOW0"/>
+ <reg32 offset="0x0184" name="TRANSP_LOW1"/>
+ <reg32 offset="0x0188" name="TRANSP_HIGH0"/>
+ <reg32 offset="0x018c" name="TRANSP_HIGH1"/>
+
+ <reg32 offset="0x0200" name="CSC_CONFIG"/>
+
+ <array offset="0x2000" name="CSC" length="1" stride="0x700">
+ <array offset="0x400" name="MV" length="9" stride="4">
+ <reg32 offset="0" name="VAL"/>
+ </array>
+ <array offset="0x500" name="PRE_BV" length="3" stride="4">
+ <reg32 offset="0" name="VAL"/>
+ </array>
+ <array offset="0x580" name="POST_BV" length="3" stride="4">
+ <reg32 offset="0" name="VAL"/>
+ </array>
+ <array offset="0x600" name="PRE_LV" length="6" stride="4">
+ <reg32 offset="0" name="VAL"/>
+ </array>
+ <array offset="0x680" name="POST_LV" length="6" stride="4">
+ <reg32 offset="0" name="VAL"/>
+ </array>
+ </array>
+ </array>
+
+ <enum name="mdp4_dma">
+ <value name="DMA_P" value="0"/>
+ <value name="DMA_S" value="1"/>
+ <value name="DMA_E" value="2"/>
+ </enum>
+ <reg32 offset="0x90070" name="DMA_P_OP_MODE"/>
+ <array offset="0x94800" name="LUTN" length="2" stride="0x400">
+ <array offset="0" name="LUT" length="0x100" stride="4">
+ <reg32 offset="0" name="VAL"/>
+ </array>
+ </array>
+ <reg32 offset="0xa0028" name="DMA_S_OP_MODE"/>
+ <!-- I guess if DMA_S has an OP_MODE, it must have a LUT too.. -->
+ <reg32 offset="0xb0070" name="DMA_E_QUANT" length="3" stride="4"/>
+ <array offsets="0x90000,0xa0000,0xb0000" name="DMA" length="3" stride="0x10000" index="mdp4_dma">
+ <reg32 offset="0x0000" name="CONFIG">
+ <bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/>
+ <bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/>
+ <bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/>
+ <bitfield name="PACK_ALIGN_MSB" pos="7" type="boolean"/>
+ <bitfield name="PACK" low="8" high="15"/>
+ <!-- bit 24 is DITHER_EN on DMA_P, DEFLKR_EN on DMA_E -->
+ <bitfield name="DEFLKR_EN" pos="24" type="boolean"/>
+ <bitfield name="DITHER_EN" pos="24" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0004" name="SRC_SIZE" type="reg_wh"/>
+ <reg32 offset="0x0008" name="SRC_BASE"/>
+ <reg32 offset="0x000c" name="SRC_STRIDE" type="uint"/>
+ <reg32 offset="0x0010" name="DST_SIZE" type="reg_wh"/>
+
+ <reg32 offset="0x0044" name="CURSOR_SIZE">
+ <!-- seems the limit is 64x64: -->
+ <bitfield name="WIDTH" low="0" high="6" type="uint"/>
+ <bitfield name="HEIGHT" low="16" high="22" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0048" name="CURSOR_BASE"/>
+ <reg32 offset="0x004c" name="CURSOR_POS">
+ <bitfield name="X" low="0" high="15" type="uint"/>
+ <bitfield name="Y" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0060" name="CURSOR_BLEND_CONFIG">
+ <bitfield name="CURSOR_EN" pos="0" type="boolean"/>
+ <bitfield name="FORMAT" low="1" high="2" type="mdp4_cursor_format"/>
+ <bitfield name="TRANSP_EN" pos="3" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0064" name="CURSOR_BLEND_PARAM"/>
+ <reg32 offset="0x0068" name="BLEND_TRANS_LOW"/>
+ <reg32 offset="0x006c" name="BLEND_TRANS_HIGH"/>
+
+ <reg32 offset="0x1004" name="FETCH_CONFIG"/>
+ <array offset="0x3000" name="CSC" length="1" stride="0x700">
+ <array offset="0x400" name="MV" length="9" stride="4">
+ <reg32 offset="0" name="VAL"/>
+ </array>
+ <array offset="0x500" name="PRE_BV" length="3" stride="4">
+ <reg32 offset="0" name="VAL"/>
+ </array>
+ <array offset="0x580" name="POST_BV" length="3" stride="4">
+ <reg32 offset="0" name="VAL"/>
+ </array>
+ <array offset="0x600" name="PRE_LV" length="6" stride="4">
+ <reg32 offset="0" name="VAL"/>
+ </array>
+ <array offset="0x680" name="POST_LV" length="6" stride="4">
+ <reg32 offset="0" name="VAL"/>
+ </array>
+ </array>
+ </array>
+
+ <!--
+ TODO length should be 7, but that would collide w/ OVLP2..!?!
+ this register map is a bit strange..
+ -->
+ <array offset="0x20000" name="PIPE" length="6" stride="0x10000" index="mdp4_pipe">
+ <reg32 offset="0x0000" name="SRC_SIZE" type="reg_wh"/>
+ <reg32 offset="0x0004" name="SRC_XY" type="reg_xy"/>
+ <reg32 offset="0x0008" name="DST_SIZE" type="reg_wh"/>
+ <reg32 offset="0x000c" name="DST_XY" type="reg_xy"/>
+ <reg32 offset="0x0010" name="SRCP0_BASE"/>
+ <reg32 offset="0x0014" name="SRCP1_BASE"/>
+ <reg32 offset="0x0018" name="SRCP2_BASE"/>
+ <reg32 offset="0x001c" name="SRCP3_BASE"/>
+ <reg32 offset="0x0040" name="SRC_STRIDE_A">
+ <bitfield name="P0" low="0" high="15" type="uint"/>
+ <bitfield name="P1" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0044" name="SRC_STRIDE_B">
+ <bitfield name="P2" low="0" high="15" type="uint"/>
+ <bitfield name="P3" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0048" name="SSTILE_FRAME_SIZE" type="reg_wh"/>
+ <reg32 offset="0x0050" name="SRC_FORMAT">
+ <bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/>
+ <bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/>
+ <bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/>
+ <bitfield name="A_BPC" low="6" high="7" type="mdp_bpc_alpha"/>
+ <bitfield name="ALPHA_ENABLE" pos="8" type="boolean"/>
+ <bitfield name="CPP" low="9" high="10" type="uint">
+ <brief>8bit characters per pixel minus 1</brief>
+ </bitfield>
+ <bitfield name="ROTATED_90" pos="12" type="boolean"/>
+ <bitfield name="UNPACK_COUNT" low="13" high="14" type="uint"/>
+ <bitfield name="UNPACK_TIGHT" pos="17" type="boolean"/>
+ <bitfield name="UNPACK_ALIGN_MSB" pos="18" type="boolean"/>
+ <bitfield name="FETCH_PLANES" low="19" high="20" type="uint"/>
+ <bitfield name="SOLID_FILL" pos="22" type="boolean"/>
+ <bitfield name="CHROMA_SAMP" low="26" high="27" type="mdp_chroma_samp_type"/>
+ <bitfield name="FRAME_FORMAT" low="29" high="30" type="mdp4_frame_format"/>
+ </reg32>
+ <reg32 offset="0x0054" name="SRC_UNPACK" type="mdp_unpack_pattern"/>
+ <reg32 offset="0x0058" name="OP_MODE">
+ <bitfield name="SCALEX_EN" pos="0" type="boolean"/>
+ <bitfield name="SCALEY_EN" pos="1" type="boolean"/>
+ <bitfield name="SCALEX_UNIT_SEL" low="2" high="3" type="mdp4_scale_unit"/>
+ <bitfield name="SCALEY_UNIT_SEL" low="4" high="5" type="mdp4_scale_unit"/>
+ <bitfield name="SRC_YCBCR" pos="9" type="boolean"/>
+ <bitfield name="DST_YCBCR" pos="10" type="boolean"/>
+ <bitfield name="CSC_EN" pos="11" type="boolean"/>
+ <bitfield name="FLIP_LR" pos="13" type="boolean"/>
+ <bitfield name="FLIP_UD" pos="14" type="boolean"/>
+ <bitfield name="DITHER_EN" pos="15" type="boolean"/>
+ <bitfield name="IGC_LUT_EN" pos="16" type="boolean"/>
+ <bitfield name="DEINT_EN" pos="18" type="boolean"/>
+ <bitfield name="DEINT_ODD_REF" pos="19" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x005c" name="PHASEX_STEP"/>
+ <reg32 offset="0x0060" name="PHASEY_STEP"/>
+ <reg32 offset="0x1004" name="FETCH_CONFIG"/>
+ <reg32 offset="0x1008" name="SOLID_COLOR"/>
+
+ <array offset="0x4000" name="CSC" length="1" stride="0x700">
+ <array offset="0x400" name="MV" length="9" stride="4">
+ <reg32 offset="0" name="VAL"/>
+ </array>
+ <array offset="0x500" name="PRE_BV" length="3" stride="4">
+ <reg32 offset="0" name="VAL"/>
+ </array>
+ <array offset="0x580" name="POST_BV" length="3" stride="4">
+ <reg32 offset="0" name="VAL"/>
+ </array>
+ <array offset="0x600" name="PRE_LV" length="6" stride="4">
+ <reg32 offset="0" name="VAL"/>
+ </array>
+ <array offset="0x680" name="POST_LV" length="6" stride="4">
+ <reg32 offset="0" name="VAL"/>
+ </array>
+ </array>
+ </array>
+
+ <!--
+ ENCODERS
+ LCDC and DSI seem the same, DTV is just slightly different..
+ -->
+
+ <bitset name="mdp4_ctrl_polarity" inline="yes">
+ <!-- not entirely sure if these bits mean hi or low.. -->
+ <bitfield name="HSYNC_LOW" pos="0" type="boolean"/>
+ <bitfield name="VSYNC_LOW" pos="1" type="boolean"/>
+ <bitfield name="DATA_EN_LOW" pos="2" type="boolean"/>
+ </bitset>
+
+ <bitset name="mdp4_active_hctl" inline="yes">
+ <bitfield name="START" low="0" high="14" type="uint"/>
+ <bitfield name="END" low="16" high="30" type="uint"/>
+ <bitfield name="ACTIVE_START_X" pos="31" type="boolean"/>
+ </bitset>
+
+ <bitset name="mdp4_display_hctl" inline="yes">
+ <bitfield name="START" low="0" high="15" type="uint"/>
+ <bitfield name="END" low="16" high="31" type="uint"/>
+ </bitset>
+
+ <bitset name="mdp4_hsync_ctrl" inline="yes">
+ <bitfield name="PULSEW" low="0" high="15" type="uint"/>
+ <bitfield name="PERIOD" low="16" high="31" type="uint"/>
+ </bitset>
+
+ <bitset name="mdp4_underflow_clr" inline="yes">
+ <bitfield name="COLOR" low="0" high="23"/>
+ <bitfield name="ENABLE_RECOVERY" pos="31" type="boolean"/>
+ </bitset>
+
+ <!-- offset is 0xe0000 on !mdp4.. -->
+ <array offset="0xc0000" name="LCDC" length="1" stride="0x1000">
+ <reg32 offset="0x0000" name="ENABLE"/>
+ <reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/>
+ <reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/>
+ <reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/>
+ <reg32 offset="0x0010" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/>
+ <reg32 offset="0x0014" name="DISPLAY_VSTART" type="uint"/>
+ <reg32 offset="0x0018" name="DISPLAY_VEND" type="uint"/>
+ <reg32 offset="0x001c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/>
+ <reg32 offset="0x0020" name="ACTIVE_VSTART" type="uint"/>
+ <reg32 offset="0x0024" name="ACTIVE_VEND" type="uint"/>
+ <reg32 offset="0x0028" name="BORDER_CLR"/>
+ <reg32 offset="0x002c" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/>
+ <reg32 offset="0x0030" name="HSYNC_SKEW"/>
+ <reg32 offset="0x0034" name="TEST_CNTL"/>
+ <reg32 offset="0x0038" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/>
+ </array>
+
+ <reg32 offset="0xc2000" name="LCDC_LVDS_INTF_CTL">
+ <bitfield name="MODE_SEL" pos="2" type="boolean"/>
+ <bitfield name="RGB_OUT" pos="3" type="boolean"/>
+ <bitfield name="CH_SWAP" pos="4" type="boolean"/>
+ <bitfield name="CH1_RES_BIT" pos="5" type="boolean"/>
+ <bitfield name="CH2_RES_BIT" pos="6" type="boolean"/>
+ <bitfield name="ENABLE" pos="7" type="boolean"/>
+ <bitfield name="CH1_DATA_LANE0_EN" pos="8" type="boolean"/>
+ <bitfield name="CH1_DATA_LANE1_EN" pos="9" type="boolean"/>
+ <bitfield name="CH1_DATA_LANE2_EN" pos="10" type="boolean"/>
+ <bitfield name="CH1_DATA_LANE3_EN" pos="11" type="boolean"/>
+ <bitfield name="CH2_DATA_LANE0_EN" pos="12" type="boolean"/>
+ <bitfield name="CH2_DATA_LANE1_EN" pos="13" type="boolean"/>
+ <bitfield name="CH2_DATA_LANE2_EN" pos="14" type="boolean"/>
+ <bitfield name="CH2_DATA_LANE3_EN" pos="15" type="boolean"/>
+ <bitfield name="CH1_CLK_LANE_EN" pos="16" type="boolean"/>
+ <bitfield name="CH2_CLK_LANE_EN" pos="17" type="boolean"/>
+ </reg32>
+
+ <array offset="0xc2014" name="LCDC_LVDS_MUX_CTL" length="4" stride="0x8">
+ <reg32 offset="0x0" name="3_TO_0">
+ <bitfield name="BIT0" low="0" high="7"/>
+ <bitfield name="BIT1" low="8" high="15"/>
+ <bitfield name="BIT2" low="16" high="23"/>
+ <bitfield name="BIT3" low="24" high="31"/>
+ </reg32>
+ <reg32 offset="0x4" name="6_TO_4">
+ <bitfield name="BIT4" low="0" high="7"/>
+ <bitfield name="BIT5" low="8" high="15"/>
+ <bitfield name="BIT6" low="16" high="23"/>
+ </reg32>
+ </array>
+
+ <reg32 offset="0xc2034" name="LCDC_LVDS_PHY_RESET"/>
+
+ <reg32 offset="0xc3000" name="LVDS_PHY_PLL_CTRL_0"/>
+ <reg32 offset="0xc3004" name="LVDS_PHY_PLL_CTRL_1"/>
+ <reg32 offset="0xc3008" name="LVDS_PHY_PLL_CTRL_2"/>
+ <reg32 offset="0xc300c" name="LVDS_PHY_PLL_CTRL_3"/>
+ <reg32 offset="0xc3014" name="LVDS_PHY_PLL_CTRL_5"/>
+ <reg32 offset="0xc3018" name="LVDS_PHY_PLL_CTRL_6"/>
+ <reg32 offset="0xc301c" name="LVDS_PHY_PLL_CTRL_7"/>
+ <reg32 offset="0xc3020" name="LVDS_PHY_PLL_CTRL_8"/>
+ <reg32 offset="0xc3024" name="LVDS_PHY_PLL_CTRL_9"/>
+ <reg32 offset="0xc3080" name="LVDS_PHY_PLL_LOCKED"/>
+ <reg32 offset="0xc3108" name="LVDS_PHY_CFG2"/>
+
+ <reg32 offset="0xc3100" name="LVDS_PHY_CFG0">
+ <bitfield name="SERIALIZATION_ENBLE" pos="4" type="boolean"/>
+ <bitfield name="CHANNEL0" pos="6" type="boolean"/>
+ <bitfield name="CHANNEL1" pos="7" type="boolean"/>
+ </reg32>
+
+ <array offset="0xd0000" name="DTV" length="1" stride="0x1000">
+ <reg32 offset="0x0000" name="ENABLE"/>
+ <reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/>
+ <reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/>
+ <reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/>
+ <reg32 offset="0x0018" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/>
+ <reg32 offset="0x001c" name="DISPLAY_VSTART" type="uint"/>
+ <reg32 offset="0x0020" name="DISPLAY_VEND" type="uint"/>
+ <reg32 offset="0x002c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/>
+ <reg32 offset="0x0030" name="ACTIVE_VSTART" type="uint"/>
+ <reg32 offset="0x0038" name="ACTIVE_VEND" type="uint"/>
+ <reg32 offset="0x0040" name="BORDER_CLR"/>
+ <reg32 offset="0x0044" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/>
+ <reg32 offset="0x0048" name="HSYNC_SKEW"/>
+ <reg32 offset="0x004c" name="TEST_CNTL"/>
+ <reg32 offset="0x0050" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/>
+ </array>
+
+ <array offset="0xe0000" name="DSI" length="1" stride="0x1000">
+ <reg32 offset="0x0000" name="ENABLE"/>
+ <reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/>
+ <reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/>
+ <reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/>
+ <reg32 offset="0x0010" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/>
+ <reg32 offset="0x0014" name="DISPLAY_VSTART" type="uint"/>
+ <reg32 offset="0x0018" name="DISPLAY_VEND" type="uint"/>
+ <reg32 offset="0x001c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/>
+ <reg32 offset="0x0020" name="ACTIVE_VSTART" type="uint"/>
+ <reg32 offset="0x0024" name="ACTIVE_VEND" type="uint"/>
+ <reg32 offset="0x0028" name="BORDER_CLR"/>
+ <reg32 offset="0x002c" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/>
+ <reg32 offset="0x0030" name="HSYNC_SKEW"/>
+ <reg32 offset="0x0034" name="TEST_CNTL"/>
+ <reg32 offset="0x0038" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/>
+ </array>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/display/mdp5.xml b/drivers/gpu/drm/msm/registers/display/mdp5.xml
new file mode 100644
index 000000000000..92f3263af170
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/display/mdp5.xml
@@ -0,0 +1,806 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+<import file="display/mdp_common.xml"/>
+
+<!-- where does this belong? -->
+<domain name="VBIF" width="32">
+</domain>
+
+<domain name="MDSS" width="32">
+ <reg32 offset="0x00000" name="HW_VERSION">
+ <bitfield name="STEP" low="0" high="15" type="uint"/>
+ <bitfield name="MINOR" low="16" high="27" type="uint"/>
+ <bitfield name="MAJOR" low="28" high="31" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x00010" name="HW_INTR_STATUS">
+ <bitfield name="INTR_MDP" pos="0" type="boolean"/>
+ <bitfield name="INTR_DSI0" pos="4" type="boolean"/>
+ <bitfield name="INTR_DSI1" pos="5" type="boolean"/>
+ <bitfield name="INTR_HDMI" pos="8" type="boolean"/>
+ <bitfield name="INTR_EDP" pos="12" type="boolean"/>
+ </reg32>
+</domain>
+
+<domain name="MDP5" width="32">
+
+ <enum name="mdp5_intf_type">
+ <value name="INTF_DISABLED" value="0x0"/>
+ <value name="INTF_DSI" value="0x1"/>
+ <value name="INTF_HDMI" value="0x3"/>
+ <value name="INTF_LCDC" value="0x5"/>
+ <value name="INTF_eDP" value="0x9"/>
+ <value name="INTF_VIRTUAL" value="0x64"/>
+ <!-- non-display interfaces are listed below: -->
+ <value name="INTF_WB" value="0x65"/>
+ </enum>
+
+ <enum name="mdp5_intfnum">
+ <value name="NO_INTF" value="0"/>
+ <value name="INTF0" value="1"/>
+ <value name="INTF1" value="2"/>
+ <value name="INTF2" value="3"/>
+ <value name="INTF3" value="4"/>
+ </enum>
+
+ <enum name="mdp5_pipe">
+ <value name="SSPP_NONE" value="0"/>
+ <value name="SSPP_VIG0" value="1"/>
+ <value name="SSPP_VIG1" value="2"/>
+ <value name="SSPP_VIG2" value="3"/>
+ <value name="SSPP_RGB0" value="4"/>
+ <value name="SSPP_RGB1" value="5"/>
+ <value name="SSPP_RGB2" value="6"/>
+ <value name="SSPP_DMA0" value="7"/>
+ <value name="SSPP_DMA1" value="8"/>
+ <value name="SSPP_VIG3" value="9"/>
+ <value name="SSPP_RGB3" value="10"/>
+ <value name="SSPP_CURSOR0" value="11"/>
+ <value name="SSPP_CURSOR1" value="12"/>
+ </enum>
+
+ <enum name="mdp5_format">
+ <!-- TODO -->
+ <value name="DUMMY" value="0"/>
+ </enum>
+
+ <enum name="mdp5_ctl_mode">
+ <value name="MODE_NONE" value="0"/>
+ <value name="MODE_WB_0_BLOCK" value="1"/>
+ <value name="MODE_WB_1_BLOCK" value="2"/>
+ <value name="MODE_WB_0_LINE" value="3"/>
+ <value name="MODE_WB_1_LINE" value="4"/>
+ <value name="MODE_WB_2_LINE" value="5"/>
+ </enum>
+
+ <enum name="mdp5_pack_3d">
+ <value name="PACK_3D_FRAME_INT" value="0"/>
+ <value name="PACK_3D_H_ROW_INT" value="1"/>
+ <value name="PACK_3D_V_ROW_INT" value="2"/>
+ <value name="PACK_3D_COL_INT" value="3"/>
+ </enum>
+
+ <enum name="mdp5_scale_filter">
+ <value name="SCALE_FILTER_NEAREST" value="0"/>
+ <value name="SCALE_FILTER_BIL" value="1"/>
+ <value name="SCALE_FILTER_PCMN" value="2"/>
+ <value name="SCALE_FILTER_CA" value="3"/>
+ </enum>
+
+ <enum name="mdp5_pipe_bwc">
+ <value name="BWC_LOSSLESS" value="0"/>
+ <value name="BWC_Q_HIGH" value="1"/>
+ <value name="BWC_Q_MED" value="2"/>
+ </enum>
+
+ <enum name="mdp5_cursor_format">
+ <value name="CURSOR_FMT_ARGB8888" value="0"/>
+ <value name="CURSOR_FMT_ARGB1555" value="2"/>
+ <value name="CURSOR_FMT_ARGB4444" value="4"/>
+ </enum>
+
+ <enum name="mdp5_cursor_alpha">
+ <value name="CURSOR_ALPHA_CONST" value="0"/>
+ <value name="CURSOR_ALPHA_PER_PIXEL" value="2"/>
+ </enum>
+
+ <bitset name="MDP5_IRQ">
+ <bitfield name="WB_0_DONE" pos="0" type="boolean"/>
+ <bitfield name="WB_1_DONE" pos="1" type="boolean"/>
+ <bitfield name="WB_2_DONE" pos="4" type="boolean"/>
+ <bitfield name="PING_PONG_0_DONE" pos="8" type="boolean"/>
+ <bitfield name="PING_PONG_1_DONE" pos="9" type="boolean"/>
+ <bitfield name="PING_PONG_2_DONE" pos="10" type="boolean"/>
+ <bitfield name="PING_PONG_3_DONE" pos="11" type="boolean"/>
+ <bitfield name="PING_PONG_0_RD_PTR" pos="12" type="boolean"/>
+ <bitfield name="PING_PONG_1_RD_PTR" pos="13" type="boolean"/>
+ <bitfield name="PING_PONG_2_RD_PTR" pos="14" type="boolean"/>
+ <bitfield name="PING_PONG_3_RD_PTR" pos="15" type="boolean"/>
+ <bitfield name="PING_PONG_0_WR_PTR" pos="16" type="boolean"/>
+ <bitfield name="PING_PONG_1_WR_PTR" pos="17" type="boolean"/>
+ <bitfield name="PING_PONG_2_WR_PTR" pos="18" type="boolean"/>
+ <bitfield name="PING_PONG_3_WR_PTR" pos="19" type="boolean"/>
+ <bitfield name="PING_PONG_0_AUTO_REF" pos="20" type="boolean"/>
+ <bitfield name="PING_PONG_1_AUTO_REF" pos="21" type="boolean"/>
+ <bitfield name="PING_PONG_2_AUTO_REF" pos="22" type="boolean"/>
+ <bitfield name="PING_PONG_3_AUTO_REF" pos="23" type="boolean"/>
+ <bitfield name="INTF0_UNDER_RUN" pos="24" type="boolean"/>
+ <bitfield name="INTF0_VSYNC" pos="25" type="boolean"/>
+ <bitfield name="INTF1_UNDER_RUN" pos="26" type="boolean"/>
+ <bitfield name="INTF1_VSYNC" pos="27" type="boolean"/>
+ <bitfield name="INTF2_UNDER_RUN" pos="28" type="boolean"/>
+ <bitfield name="INTF2_VSYNC" pos="29" type="boolean"/>
+ <bitfield name="INTF3_UNDER_RUN" pos="30" type="boolean"/>
+ <bitfield name="INTF3_VSYNC" pos="31" type="boolean"/>
+ </bitset>
+
+ <bitset name="mdp5_smp_alloc" inline="yes">
+ <!-- Use "mdp5_cfg->mdp.smp.clients[enum mdp5_pipe]" instead -->
+ <bitfield name="CLIENT0" low="0" high="7" type="uint"/>
+ <bitfield name="CLIENT1" low="8" high="15" type="uint"/>
+ <bitfield name="CLIENT2" low="16" high="23" type="uint"/>
+ </bitset>
+
+ <reg32 offset="0x00000" name="HW_VERSION">
+ <bitfield name="STEP" low="0" high="15" type="uint"/>
+ <bitfield name="MINOR" low="16" high="27" type="uint"/>
+ <bitfield name="MAJOR" low="28" high="31" type="uint"/>
+ </reg32>
+
+ <reg32 offset="0x00004" name="DISP_INTF_SEL">
+ <bitfield name="INTF0" low="0" high="7" type="mdp5_intf_type"/>
+ <bitfield name="INTF1" low="8" high="15" type="mdp5_intf_type"/>
+ <bitfield name="INTF2" low="16" high="23" type="mdp5_intf_type"/>
+ <bitfield name="INTF3" low="24" high="31" type="mdp5_intf_type"/>
+ </reg32>
+ <reg32 offset="0x00010" name="INTR_EN" type="MDP5_IRQ"/>
+ <reg32 offset="0x00014" name="INTR_STATUS" type="MDP5_IRQ"/>
+ <reg32 offset="0x00018" name="INTR_CLEAR" type="MDP5_IRQ"/>
+ <reg32 offset="0x0001C" name="HIST_INTR_EN"/>
+ <reg32 offset="0x00020" name="HIST_INTR_STATUS"/>
+ <reg32 offset="0x00024" name="HIST_INTR_CLEAR"/>
+ <reg32 offset="0x00028" name="SPARE_0">
+ <bitfield name="SPLIT_DPL_SINGLE_FLUSH_EN" pos="0"/>
+ </reg32>
+
+ <array offset="0x00080" name="SMP_ALLOC_W" length="8" stride="4">
+ <reg32 offset="0" name="REG" type="mdp5_smp_alloc"/>
+ </array>
+ <array offset="0x00130" name="SMP_ALLOC_R" length="8" stride="4">
+ <reg32 offset="0" name="REG" type="mdp5_smp_alloc"/>
+ </array>
+
+ <enum name="mdp5_igc_type">
+ <value name="IGC_VIG" value="0"/> <!-- 0x200 -->
+ <value name="IGC_RGB" value="1"/> <!-- 0x210 -->
+ <value name="IGC_DMA" value="2"/> <!-- 0x220 -->
+ <value name="IGC_DSPP" value="3"/> <!-- 0x300 -->
+ </enum>
+ <array offsets="0x00200,0x00210,0x00220,0x00300" name="IGC" length="3" stride="0x10" index="mdp5_igc_type">
+ <array offset="0x00" name="LUT" length="3" stride="4">
+ <reg32 offset="0" name="REG">
+ <bitfield name="VAL" low="0" high="11"/>
+ <bitfield name="INDEX_UPDATE" pos="25" type="boolean"/>
+ <!--
+ not sure about these:
+ /* INDEX_UPDATE */
+ data = (1 << 25) | (((~(1 << blk_idx)) & 0x7) << 28);
+ MDSS_MDP_REG_WRITE(offset, (cfg->c0_c1_data[0] & 0xFFF) | data);
+ -->
+ <bitfield name="DISABLE_PIPE_0" pos="28" type="boolean"/>
+ <bitfield name="DISABLE_PIPE_1" pos="29" type="boolean"/>
+ <bitfield name="DISABLE_PIPE_2" pos="30" type="boolean"/>
+ </reg32>
+ </array>
+ </array>
+ <reg32 offset="0x002f4" name="SPLIT_DPL_EN"/>
+ <reg32 offset="0x002f8" name="SPLIT_DPL_UPPER">
+ <bitfield name="SMART_PANEL" pos="1" type="boolean"/>
+ <bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
+ <bitfield name="INTF1_SW_TRG_MUX" pos="4" type="boolean"/>
+ <bitfield name="INTF2_SW_TRG_MUX" pos="8" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x003f0" name="SPLIT_DPL_LOWER">
+ <bitfield name="SMART_PANEL" pos="1" type="boolean"/>
+ <bitfield name="SMART_PANEL_FREE_RUN" pos="2" type="boolean"/>
+ <bitfield name="INTF1_TG_SYNC" pos="4" type="boolean"/>
+ <bitfield name="INTF2_TG_SYNC" pos="8" type="boolean"/>
+ </reg32>
+
+<!-- check length/index.. -->
+ <array doffsets="mdp5_cfg->ctl.base[0],mdp5_cfg->ctl.base[1],mdp5_cfg->ctl.base[2],mdp5_cfg->ctl.base[3],mdp5_cfg->ctl.base[4]" name="CTL" length="5" stride="0x400">
+ <array offsets="0x000,0x004,0x008,0x00C,0x010,0x024" name="LAYER" length="6" stride="4">
+ <!--
+ NOTE: for backwards compat (from when there were fewer stages),
+ this register has the low three bits of mdp_mixer_stage_id, with
+ the high bit coming from LAYER_EXT
+ -->
+ <reg32 offset="0" name="REG">
+ <bitfield name="VIG0" low="0" high="2" type="uint"/>
+ <bitfield name="VIG1" low="3" high="5" type="uint"/>
+ <bitfield name="VIG2" low="6" high="8" type="uint"/>
+ <bitfield name="RGB0" low="9" high="11" type="uint"/>
+ <bitfield name="RGB1" low="12" high="14" type="uint"/>
+ <bitfield name="RGB2" low="15" high="17" type="uint"/>
+ <bitfield name="DMA0" low="18" high="20" type="uint"/>
+ <bitfield name="DMA1" low="21" high="23" type="uint"/>
+ <bitfield name="BORDER_COLOR" pos="24" type="boolean"/>
+ <bitfield name="CURSOR_OUT" pos="25" type="boolean"/>
+ <bitfield name="VIG3" low="26" high="28" type="uint"/>
+ <bitfield name="RGB3" low="29" high="31" type="uint"/>
+ </reg32>
+ </array>
+ <reg32 offset="0x014" name="OP">
+ <bitfield name="MODE" low="0" high="3" type="mdp5_ctl_mode"/>
+ <bitfield name="INTF_NUM" low="4" high="6" type="mdp5_intfnum"/>
+ <bitfield name="CMD_MODE" pos="17" type="boolean"/>
+ <bitfield name="PACK_3D_ENABLE" pos="19" type="boolean"/>
+ <bitfield name="PACK_3D" low="20" high="21" type="mdp5_pack_3d"/>
+ </reg32>
+ <reg32 offset="0x018" name="FLUSH">
+ <bitfield name="VIG0" pos="0" type="boolean"/>
+ <bitfield name="VIG1" pos="1" type="boolean"/>
+ <bitfield name="VIG2" pos="2" type="boolean"/>
+ <bitfield name="RGB0" pos="3" type="boolean"/>
+ <bitfield name="RGB1" pos="4" type="boolean"/>
+ <bitfield name="RGB2" pos="5" type="boolean"/>
+ <bitfield name="LM0" pos="6" type="boolean"/>
+ <bitfield name="LM1" pos="7" type="boolean"/>
+ <bitfield name="LM2" pos="8" type="boolean"/>
+ <bitfield name="LM3" pos="9" type="boolean"/>
+ <bitfield name="LM4" pos="10" type="boolean"/>
+ <bitfield name="DMA0" pos="11" type="boolean"/>
+ <bitfield name="DMA1" pos="12" type="boolean"/>
+ <bitfield name="DSPP0" pos="13" type="boolean"/>
+ <bitfield name="DSPP1" pos="14" type="boolean"/>
+ <bitfield name="DSPP2" pos="15" type="boolean"/>
+ <bitfield name="WB" pos="16" type="boolean"/>
+ <bitfield name="CTL" pos="17" type="boolean"/>
+ <bitfield name="VIG3" pos="18" type="boolean"/>
+ <bitfield name="RGB3" pos="19" type="boolean"/>
+ <bitfield name="LM5" pos="20" type="boolean"/>
+ <bitfield name="DSPP3" pos="21" type="boolean"/>
+ <bitfield name="CURSOR_0" pos="22" type="boolean"/>
+ <bitfield name="CURSOR_1" pos="23" type="boolean"/>
+ <bitfield name="CHROMADOWN_0" pos="26" type="boolean"/>
+ <bitfield name="TIMING_3" pos="28" type="boolean"/>
+ <bitfield name="TIMING_2" pos="29" type="boolean"/>
+ <bitfield name="TIMING_1" pos="30" type="boolean"/>
+ <bitfield name="TIMING_0" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x01C" name="START"/>
+ <reg32 offset="0x020" name="PACK_3D"/>
+ <array offsets="0x040,0x044,0x048,0x04C,0x050,0x054" name="LAYER_EXT" length="6" stride="4">
+ <reg32 offset="0" name="REG">
+ <bitfield name="VIG0_BIT3" pos="0" type="boolean"/>
+ <bitfield name="VIG1_BIT3" pos="2" type="boolean"/>
+ <bitfield name="VIG2_BIT3" pos="4" type="boolean"/>
+ <bitfield name="VIG3_BIT3" pos="6" type="boolean"/>
+ <bitfield name="RGB0_BIT3" pos="8" type="boolean"/>
+ <bitfield name="RGB1_BIT3" pos="10" type="boolean"/>
+ <bitfield name="RGB2_BIT3" pos="12" type="boolean"/>
+ <bitfield name="RGB3_BIT3" pos="14" type="boolean"/>
+ <bitfield name="DMA0_BIT3" pos="16" type="boolean"/>
+ <bitfield name="DMA1_BIT3" pos="18" type="boolean"/>
+ <bitfield name="CURSOR0" low="20" high="23" type="mdp_mixer_stage_id"/>
+ <bitfield name="CURSOR1" low="26" high="29" type="mdp_mixer_stage_id"/>
+ </reg32>
+ </array>
+ </array>
+
+ <enum name="mdp5_data_format">
+ <value name="DATA_FORMAT_RGB" value="0"/>
+ <value name="DATA_FORMAT_YUV" value="1"/>
+ </enum>
+
+ <array doffsets="INVALID_IDX(idx),mdp5_cfg->pipe_vig.base[0],mdp5_cfg->pipe_vig.base[1],mdp5_cfg->pipe_vig.base[2],mdp5_cfg->pipe_rgb.base[0],mdp5_cfg->pipe_rgb.base[1],mdp5_cfg->pipe_rgb.base[2],mdp5_cfg->pipe_dma.base[0],mdp5_cfg->pipe_dma.base[1],mdp5_cfg->pipe_vig.base[3],mdp5_cfg->pipe_rgb.base[3],mdp5_cfg->pipe_cursor.base[0],mdp5_cfg->pipe_cursor.base[1]" name="PIPE" length="10" stride="0x400" index="mdp5_pipe">
+ <reg32 offset="0x200" name="OP_MODE">
+ <bitfield name="CSC_DST_DATA_FORMAT" pos="19" type="mdp5_data_format"/>
+ <bitfield name="CSC_SRC_DATA_FORMAT" pos="18" type="mdp5_data_format"/>
+ <bitfield name="CSC_1_EN" pos="17" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x2C4" name="HIST_CTL_BASE"/>
+ <reg32 offset="0x2F0" name="HIST_LUT_BASE"/>
+ <reg32 offset="0x300" name="HIST_LUT_SWAP"/>
+ <reg32 offset="0x320" name="CSC_1_MATRIX_COEFF_0">
+ <bitfield name="COEFF_11" low="0" high="12" type="uint"/>
+ <bitfield name="COEFF_12" low="16" high="28" type="uint"/>
+ </reg32>
+ <reg32 offset="0x324" name="CSC_1_MATRIX_COEFF_1">
+ <bitfield name="COEFF_13" low="0" high="12" type="uint"/>
+ <bitfield name="COEFF_21" low="16" high="28" type="uint"/>
+ </reg32>
+ <reg32 offset="0x328" name="CSC_1_MATRIX_COEFF_2">
+ <bitfield name="COEFF_22" low="0" high="12" type="uint"/>
+ <bitfield name="COEFF_23" low="16" high="28" type="uint"/>
+ </reg32>
+ <reg32 offset="0x32c" name="CSC_1_MATRIX_COEFF_3">
+ <bitfield name="COEFF_31" low="0" high="12" type="uint"/>
+ <bitfield name="COEFF_32" low="16" high="28" type="uint"/>
+ </reg32>
+ <reg32 offset="0x330" name="CSC_1_MATRIX_COEFF_4">
+ <bitfield name="COEFF_33" low="0" high="12" type="uint"/>
+ </reg32>
+ <array offset="0x334" name="CSC_1_PRE_CLAMP" length="3" stride="4">
+ <reg32 offset="0" name="REG">
+ <bitfield name="HIGH" low="0" high="7" type="uint"/>
+ <bitfield name="LOW" low="8" high="15" type="uint"/>
+ </reg32>
+ </array>
+ <array offset="0x340" name="CSC_1_POST_CLAMP" length="3" stride="4">
+ <reg32 offset="0" name="REG">
+ <bitfield name="HIGH" low="0" high="7" type="uint"/>
+ <bitfield name="LOW" low="8" high="15" type="uint"/>
+ </reg32>
+ </array>
+ <array offset="0x34c" name="CSC_1_PRE_BIAS" length="3" stride="4">
+ <reg32 offset="0" name="REG">
+ <bitfield name="VALUE" low="0" high="8" type="uint"/>
+ </reg32>
+ </array>
+ <array offset="0x358" name="CSC_1_POST_BIAS" length="3" stride="4">
+ <reg32 offset="0" name="REG">
+ <bitfield name="VALUE" low="0" high="8" type="uint"/>
+ </reg32>
+ </array>
+ <!-- SSPP: -->
+ <reg32 offset="0x000" name="SRC_SIZE" type="reg_wh"/>
+ <reg32 offset="0x004" name="SRC_IMG_SIZE" type="reg_wh"/>
+ <reg32 offset="0x008" name="SRC_XY" type="reg_xy"/>
+ <reg32 offset="0x00C" name="OUT_SIZE" type="reg_wh"/>
+ <reg32 offset="0x010" name="OUT_XY" type="reg_xy"/>
+ <reg32 offset="0x014" name="SRC0_ADDR"/>
+ <reg32 offset="0x018" name="SRC1_ADDR"/>
+ <reg32 offset="0x01C" name="SRC2_ADDR"/>
+ <reg32 offset="0x020" name="SRC3_ADDR"/>
+ <reg32 offset="0x024" name="SRC_STRIDE_A">
+ <bitfield name="P0" low="0" high="15" type="uint"/>
+ <bitfield name="P1" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x028" name="SRC_STRIDE_B">
+ <bitfield name="P2" low="0" high="15" type="uint"/>
+ <bitfield name="P3" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x02C" name="STILE_FRAME_SIZE"/>
+ <reg32 offset="0x030" name="SRC_FORMAT">
+ <bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/>
+ <bitfield name="B_BPC" low="2" high="3" type="mdp_bpc"/>
+ <bitfield name="R_BPC" low="4" high="5" type="mdp_bpc"/>
+ <bitfield name="A_BPC" low="6" high="7" type="mdp_bpc_alpha"/>
+ <bitfield name="ALPHA_ENABLE" pos="8" type="boolean"/>
+ <bitfield name="CPP" low="9" high="10" type="uint">
+ <brief>8bit characters per pixel minus 1</brief>
+ </bitfield>
+ <bitfield name="ROT90" pos="11" type="boolean"/>
+ <bitfield name="UNPACK_COUNT" low="12" high="13" type="uint"/>
+ <bitfield name="UNPACK_TIGHT" pos="17" type="boolean"/>
+ <bitfield name="UNPACK_ALIGN_MSB" pos="18" type="boolean"/>
+ <bitfield name="FETCH_TYPE" low="19" high="20" type="mdp_fetch_type"/>
+ <bitfield name="CHROMA_SAMP" low="23" high="24" type="mdp_chroma_samp_type"/>
+ </reg32>
+ <reg32 offset="0x034" name="SRC_UNPACK" type="mdp_unpack_pattern"/>
+ <reg32 offset="0x038" name="SRC_OP_MODE">
+ <bitfield name="BWC_EN" pos="0" type="boolean"/>
+ <bitfield name="BWC" low="1" high="2" type="mdp5_pipe_bwc"/>
+ <bitfield name="FLIP_LR" pos="13" type="boolean"/>
+ <bitfield name="FLIP_UD" pos="14" type="boolean"/>
+ <bitfield name="IGC_EN" pos="16" type="boolean"/>
+ <bitfield name="IGC_ROM_0" pos="17" type="boolean"/>
+ <bitfield name="IGC_ROM_1" pos="18" type="boolean"/>
+ <bitfield name="DEINTERLACE" pos="22" type="boolean"/>
+ <bitfield name="DEINTERLACE_ODD" pos="23" type="boolean"/>
+ <bitfield name="SW_PIX_EXT_OVERRIDE" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x03c" name="SRC_CONSTANT_COLOR"/>
+ <reg32 offset="0x048" name="FETCH_CONFIG"/>
+ <reg32 offset="0x04c" name="VC1_RANGE"/>
+ <reg32 offset="0x050" name="REQPRIO_FIFO_WM_0"/>
+ <reg32 offset="0x054" name="REQPRIO_FIFO_WM_1"/>
+ <reg32 offset="0x058" name="REQPRIO_FIFO_WM_2"/>
+ <reg32 offset="0x070" name="SRC_ADDR_SW_STATUS"/>
+ <reg32 offset="0x0a4" name="CURRENT_SRC0_ADDR"/>
+ <reg32 offset="0x0a8" name="CURRENT_SRC1_ADDR"/>
+ <reg32 offset="0x0ac" name="CURRENT_SRC2_ADDR"/>
+ <reg32 offset="0x0b0" name="CURRENT_SRC3_ADDR"/>
+ <reg32 offset="0x0b4" name="DECIMATION">
+ <bitfield name="VERT" low="0" high="7" type="uint"/>
+ <bitfield name="HORZ" low="8" high="15" type="uint"/>
+ </reg32>
+ <array offsets="0x100,0x110,0x120" name="SW_PIX_EXT" length="3" stride="0x10" index="mdp_component_type">
+ <!--
+ Notes:
+ o These value only take effect if SW_PIX_EXT_OVERRIDE is set in SRC_OP_MODE register
+ o For signed values (int): + indicates overfetch, - indicates line drop
+ -->
+ <reg32 offset="0x00" name="LR">
+ <bitfield name="LEFT_RPT" low="0" high="7" type="uint"/>
+ <bitfield name="LEFT_OVF" low="8" high="15" type="int"/>
+ <bitfield name="RIGHT_RPT" low="16" high="23" type="uint"/>
+ <bitfield name="RIGHT_OVF" low="24" high="31" type="int"/>
+ </reg32>
+ <reg32 offset="0x04" name="TB">
+ <bitfield name="TOP_RPT" low="0" high="7" type="uint"/>
+ <bitfield name="TOP_OVF" low="8" high="15" type="int"/>
+ <bitfield name="BOTTOM_RPT" low="16" high="23" type="uint"/>
+ <bitfield name="BOTTOM_OVF" low="24" high="31" type="int"/>
+ </reg32>
+ <reg32 offset="0x08" name="REQ_PIXELS">
+ <bitfield name="LEFT_RIGHT" low="0" high="15" type="uint"/>
+ <bitfield name="TOP_BOTTOM" low="16" high="31" type="uint"/>
+ </reg32>
+ </array>
+ <reg32 offset="0x204" name="SCALE_CONFIG">
+ <bitfield name="SCALEX_EN" pos="0" type="boolean"/>
+ <bitfield name="SCALEY_EN" pos="1" type="boolean"/>
+ <bitfield name="SCALEX_FILTER_COMP_0" low="8" high="9" type="mdp5_scale_filter"/>
+ <bitfield name="SCALEY_FILTER_COMP_0" low="10" high="11" type="mdp5_scale_filter"/>
+ <bitfield name="SCALEX_FILTER_COMP_1_2" low="12" high="13" type="mdp5_scale_filter"/>
+ <bitfield name="SCALEY_FILTER_COMP_1_2" low="14" high="15" type="mdp5_scale_filter"/>
+ <bitfield name="SCALEX_FILTER_COMP_3" low="16" high="17" type="mdp5_scale_filter"/>
+ <bitfield name="SCALEY_FILTER_COMP_3" low="18" high="19" type="mdp5_scale_filter"/>
+ </reg32>
+ <reg32 offset="0x210" name="SCALE_PHASE_STEP_X"/>
+ <reg32 offset="0x214" name="SCALE_PHASE_STEP_Y"/>
+ <reg32 offset="0x218" name="SCALE_CR_PHASE_STEP_X"/>
+ <reg32 offset="0x21c" name="SCALE_CR_PHASE_STEP_Y"/>
+ <reg32 offset="0x220" name="SCALE_INIT_PHASE_X"/>
+ <reg32 offset="0x224" name="SCALE_INIT_PHASE_Y"/>
+ </array>
+
+ <array doffsets="mdp5_cfg->lm.base[0],mdp5_cfg->lm.base[1],mdp5_cfg->lm.base[2],mdp5_cfg->lm.base[3],mdp5_cfg->lm.base[4],mdp5_cfg->lm.base[5]" name="LM" length="6" stride="0x400">
+ <reg32 offset="0x000" name="BLEND_COLOR_OUT">
+ <bitfield name="STAGE0_FG_ALPHA" pos="1" type="boolean"/>
+ <bitfield name="STAGE1_FG_ALPHA" pos="2" type="boolean"/>
+ <bitfield name="STAGE2_FG_ALPHA" pos="3" type="boolean"/>
+ <bitfield name="STAGE3_FG_ALPHA" pos="4" type="boolean"/>
+ <bitfield name="STAGE4_FG_ALPHA" pos="5" type="boolean"/>
+ <bitfield name="STAGE5_FG_ALPHA" pos="6" type="boolean"/>
+ <bitfield name="STAGE6_FG_ALPHA" pos="7" type="boolean"/>
+ <bitfield name="SPLIT_LEFT_RIGHT" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x004" name="OUT_SIZE" type="reg_wh"/>
+ <reg32 offset="0x008" name="BORDER_COLOR_0"/>
+ <reg32 offset="0x010" name="BORDER_COLOR_1"/>
+ <array offsets="0x020,0x050,0x080,0x0B0,0x230,0x260,0x290" name="BLEND" length="7" stride="0x30">
+ <reg32 offset="0x00" name="OP_MODE">
+ <bitfield name="FG_ALPHA" low="0" high="1" type="mdp_alpha_type"/>
+ <bitfield name="FG_INV_ALPHA" pos="2" type="boolean"/>
+ <bitfield name="FG_MOD_ALPHA" pos="3" type="boolean"/>
+ <bitfield name="FG_INV_MOD_ALPHA" pos="4" type="boolean"/>
+ <bitfield name="FG_TRANSP_EN" pos="5" type="boolean"/>
+ <bitfield name="BG_ALPHA" low="8" high="9" type="mdp_alpha_type"/>
+ <bitfield name="BG_INV_ALPHA" pos="10" type="boolean"/>
+ <bitfield name="BG_MOD_ALPHA" pos="11" type="boolean"/>
+ <bitfield name="BG_INV_MOD_ALPHA" pos="12" type="boolean"/>
+ <bitfield name="BG_TRANSP_EN" pos="13" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x04" name="FG_ALPHA"/>
+ <reg32 offset="0x08" name="BG_ALPHA"/>
+ <reg32 offset="0x0c" name="FG_TRANSP_LOW0"/>
+ <reg32 offset="0x10" name="FG_TRANSP_LOW1"/>
+ <reg32 offset="0x14" name="FG_TRANSP_HIGH0"/>
+ <reg32 offset="0x18" name="FG_TRANSP_HIGH1"/>
+ <reg32 offset="0x1c" name="BG_TRANSP_LOW0"/>
+ <reg32 offset="0x20" name="BG_TRANSP_LOW1"/>
+ <reg32 offset="0x24" name="BG_TRANSP_HIGH0"/>
+ <reg32 offset="0x28" name="BG_TRANSP_HIGH1"/>
+ </array>
+ <reg32 offset="0x0e0" name="CURSOR_IMG_SIZE">
+ <bitfield name="SRC_W" low="0" high="15" type="uint"/>
+ <bitfield name="SRC_H" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0e4" name="CURSOR_SIZE">
+ <bitfield name="ROI_W" low="0" high="15" type="uint"/>
+ <bitfield name="ROI_H" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0e8" name="CURSOR_XY">
+ <bitfield name="SRC_X" low="0" high="15" type="uint"/>
+ <bitfield name="SRC_Y" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0dc" name="CURSOR_STRIDE">
+ <bitfield name="STRIDE" low="0" high="15" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0ec" name="CURSOR_FORMAT">
+ <bitfield name="FORMAT" low="0" high="2" type="mdp5_cursor_format"/>
+ </reg32>
+ <reg32 offset="0x0f0" name="CURSOR_BASE_ADDR"/>
+ <reg32 offset="0x0f4" name="CURSOR_START_XY">
+ <bitfield name="X_START" low="0" high="15" type="uint"/>
+ <bitfield name="Y_START" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x0f8" name="CURSOR_BLEND_CONFIG">
+ <bitfield name="BLEND_EN" pos="0" type="boolean"/>
+ <bitfield name="BLEND_ALPHA_SEL" low="1" high="2" type="mdp5_cursor_alpha"/>
+ <bitfield name="BLEND_TRANSP_EN" pos="3" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x0fc" name="CURSOR_BLEND_PARAM"/>
+ <reg32 offset="0x100" name="CURSOR_BLEND_TRANSP_LOW0"/>
+ <reg32 offset="0x104" name="CURSOR_BLEND_TRANSP_LOW1"/>
+ <reg32 offset="0x108" name="CURSOR_BLEND_TRANSP_HIGH0"/>
+ <reg32 offset="0x10c" name="CURSOR_BLEND_TRANSP_HIGH1"/>
+ <reg32 offset="0x110" name="GC_LUT_BASE"/>
+ </array>
+
+ <array doffsets="mdp5_cfg->dspp.base[0],mdp5_cfg->dspp.base[1],mdp5_cfg->dspp.base[2],mdp5_cfg->dspp.base[3]" name="DSPP" length="4" stride="0x400">
+ <reg32 offset="0x000" name="OP_MODE">
+ <bitfield name="IGC_LUT_EN" pos="0" type="boolean"/>
+ <bitfield name="IGC_TBL_IDX" low="1" high="3" type="uint"/>
+ <bitfield name="PCC_EN" pos="4" type="boolean"/>
+ <bitfield name="DITHER_EN" pos="8" type="boolean"/>
+ <bitfield name="HIST_EN" pos="16" type="boolean"/>
+ <bitfield name="AUTO_CLEAR" pos="17" type="boolean"/>
+ <bitfield name="HIST_LUT_EN" pos="19" type="boolean"/>
+ <bitfield name="PA_EN" pos="20" type="boolean"/>
+ <bitfield name="GAMUT_EN" pos="23" type="boolean"/>
+ <bitfield name="GAMUT_ORDER" pos="24" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x030" name="PCC_BASE"/>
+ <reg32 offset="0x150" name="DITHER_DEPTH"/>
+ <reg32 offset="0x210" name="HIST_CTL_BASE"/>
+ <reg32 offset="0x230" name="HIST_LUT_BASE"/>
+ <reg32 offset="0x234" name="HIST_LUT_SWAP"/>
+ <reg32 offset="0x238" name="PA_BASE"/>
+ <reg32 offset="0x2dc" name="GAMUT_BASE"/>
+ <reg32 offset="0x2b0" name="GC_BASE"/>
+ </array>
+
+ <array doffsets="mdp5_cfg->pp.base[0],mdp5_cfg->pp.base[1],mdp5_cfg->pp.base[2],mdp5_cfg->pp.base[3]" name="PP" length="4" stride="0x100">
+ <reg32 offset="0x000" name="TEAR_CHECK_EN"/>
+ <reg32 offset="0x004" name="SYNC_CONFIG_VSYNC">
+ <bitfield name="COUNT" low="0" high="18" type="uint"/>
+ <bitfield name="COUNTER_EN" pos="19" type="boolean"/>
+ <bitfield name="IN_EN" pos="20" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x008" name="SYNC_CONFIG_HEIGHT"/>
+ <reg32 offset="0x00c" name="SYNC_WRCOUNT">
+ <bitfield name="LINE_COUNT" low="0" high="15" type="uint"/>
+ <bitfield name="FRAME_COUNT" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x010" name="VSYNC_INIT_VAL"/>
+ <reg32 offset="0x014" name="INT_COUNT_VAL">
+ <bitfield name="LINE_COUNT" low="0" high="15" type="uint"/>
+ <bitfield name="FRAME_COUNT" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x018" name="SYNC_THRESH">
+ <bitfield name="START" low="0" high="15" type="uint"/>
+ <bitfield name="CONTINUE" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x01c" name="START_POS"/>
+ <reg32 offset="0x020" name="RD_PTR_IRQ"/>
+ <reg32 offset="0x024" name="WR_PTR_IRQ"/>
+ <reg32 offset="0x028" name="OUT_LINE_COUNT"/>
+ <reg32 offset="0x02c" name="PP_LINE_COUNT"/>
+ <reg32 offset="0x030" name="AUTOREFRESH_CONFIG"/>
+ <reg32 offset="0x034" name="FBC_MODE"/>
+ <reg32 offset="0x038" name="FBC_BUDGET_CTL"/>
+ <reg32 offset="0x03c" name="FBC_LOSSY_MODE"/>
+ </array>
+
+ <enum name="mdp5_block_size">
+ <value name="BLOCK_SIZE_64" value="0"/>
+ <value name="BLOCK_SIZE_128" value="1"/>
+ </enum>
+
+ <enum name="mdp5_rotate_mode">
+ <value name="ROTATE_0" value="0"/>
+ <value name="ROTATE_90" value="1"/>
+ </enum>
+
+ <enum name="mdp5_chroma_downsample_method">
+ <value name="DS_MTHD_NO_PIXEL_DROP" value="0"/>
+ <value name="DS_MTHD_PIXEL_DROP" value="1"/>
+ </enum>
+
+ <array doffsets="mdp5_cfg->wb.base[0],mdp5_cfg->wb.base[1],mdp5_cfg->wb.base[2],mdp5_cfg->wb.base[3],mdp5_cfg->wb.base[4]" name="WB" length="5" stride="0x400">
+ <reg32 offset="0x000" name="DST_FORMAT">
+ <bitfield name="DSTC0_OUT" low="0" high="1" type="uint"/>
+ <bitfield name="DSTC1_OUT" low="2" high="3" type="uint"/>
+ <bitfield name="DSTC2_OUT" low="4" high="5" type="uint"/>
+ <bitfield name="DSTC3_OUT" low="6" high="7" type="uint"/>
+ <bitfield name="DSTC3_EN" pos="8" type="boolean"/>
+ <bitfield name="DST_BPP" low="9" high="10" type="uint"/>
+ <bitfield name="PACK_COUNT" low="12" high="13" type="uint"/>
+ <bitfield name="DST_ALPHA_X" pos="14" type="boolean"/>
+ <bitfield name="PACK_TIGHT" pos="17" type="boolean"/>
+ <bitfield name="PACK_ALIGN_MSB" pos="18" type="boolean"/>
+ <bitfield name="WRITE_PLANES" low="19" high="20" type="uint"/>
+ <bitfield name="DST_DITHER_EN" pos="22" type="boolean"/>
+ <bitfield name="DST_CHROMA_SAMP" low="23" high="25" type="uint"/>
+ <bitfield name="DST_CHROMA_SITE" low="26" high="29" type="uint"/>
+ <bitfield name="FRAME_FORMAT" low="30" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x004" name="DST_OP_MODE">
+ <bitfield name="BWC_ENC_EN" pos="0" type="boolean"/>
+ <bitfield name="BWC_ENC_OP" low="1" high="2" type="uint"/>
+ <bitfield name="BLOCK_SIZE" low="4" high="4" type="uint"/>
+ <bitfield name="ROT_MODE" low="5" high="5" type="uint"/>
+ <bitfield name="ROT_EN" pos="6" type="boolean"/>
+ <bitfield name="CSC_EN" pos="8" type="boolean"/>
+ <bitfield name="CSC_SRC_DATA_FORMAT" low="9" high="9" type="uint"/>
+ <bitfield name="CSC_DST_DATA_FORMAT" low="10" high="10" type="uint"/>
+ <bitfield name="CHROMA_DWN_SAMPLE_EN" pos="11" type="boolean"/>
+ <bitfield name="CHROMA_DWN_SAMPLE_FORMAT" low="12" high="12" type="uint"/>
+ <bitfield name="CHROMA_DWN_SAMPLE_H_MTHD" low="13" high="13" type="uint"/>
+ <bitfield name="CHROMA_DWN_SAMPLE_V_MTHD" low="14" high="14" type="uint"/>
+ </reg32>
+ <reg32 offset="0x008" name="DST_PACK_PATTERN">
+ <bitfield name="ELEMENT0" low="0" high="1" type="uint"/>
+ <bitfield name="ELEMENT1" low="8" high="9" type="uint"/>
+ <bitfield name="ELEMENT2" low="16" high="17" type="uint"/>
+ <bitfield name="ELEMENT3" low="24" high="25" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00c" name="DST0_ADDR"/>
+ <reg32 offset="0x010" name="DST1_ADDR"/>
+ <reg32 offset="0x014" name="DST2_ADDR"/>
+ <reg32 offset="0x018" name="DST3_ADDR"/>
+ <reg32 offset="0x01c" name="DST_YSTRIDE0">
+ <bitfield name="DST0_YSTRIDE" low="0" high="15" type="uint"/>
+ <bitfield name="DST1_YSTRIDE" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x020" name="DST_YSTRIDE1">
+ <bitfield name="DST2_YSTRIDE" low="0" high="15" type="uint"/>
+ <bitfield name="DST3_YSTRIDE" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x024" name="DST_DITHER_BITDEPTH"/>
+ <reg32 offset="0x030" name="DITHER_MATRIX_ROW0"/>
+ <reg32 offset="0x034" name="DITHER_MATRIX_ROW1"/>
+ <reg32 offset="0x038" name="DITHER_MATRIX_ROW2"/>
+ <reg32 offset="0x03c" name="DITHER_MATRIX_ROW3"/>
+ <reg32 offset="0x048" name="DST_WRITE_CONFIG"/>
+ <reg32 offset="0x050" name="ROTATION_DNSCALER"/>
+ <reg32 offset="0x060" name="N16_INIT_PHASE_X_0_3"/>
+ <reg32 offset="0x064" name="N16_INIT_PHASE_X_1_2"/>
+ <reg32 offset="0x068" name="N16_INIT_PHASE_Y_0_3"/>
+ <reg32 offset="0x06c" name="N16_INIT_PHASE_Y_1_2"/>
+ <reg32 offset="0x074" name="OUT_SIZE">
+ <bitfield name="DST_W" low="0" high="15" type="uint"/>
+ <bitfield name="DST_H" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x078" name="ALPHA_X_VALUE"/>
+ <reg32 offset="0x260" name="CSC_MATRIX_COEFF_0">
+ <bitfield name="COEFF_11" low="0" high="12" type="uint"/>
+ <bitfield name="COEFF_12" low="16" high="28" type="uint"/>
+ </reg32>
+ <reg32 offset="0x264" name="CSC_MATRIX_COEFF_1">
+ <bitfield name="COEFF_13" low="0" high="12" type="uint"/>
+ <bitfield name="COEFF_21" low="16" high="28" type="uint"/>
+ </reg32>
+ <reg32 offset="0x268" name="CSC_MATRIX_COEFF_2">
+ <bitfield name="COEFF_22" low="0" high="12" type="uint"/>
+ <bitfield name="COEFF_23" low="16" high="28" type="uint"/>
+ </reg32>
+ <reg32 offset="0x26c" name="CSC_MATRIX_COEFF_3">
+ <bitfield name="COEFF_31" low="0" high="12" type="uint"/>
+ <bitfield name="COEFF_32" low="16" high="28" type="uint"/>
+ </reg32>
+ <reg32 offset="0x270" name="CSC_MATRIX_COEFF_4">
+ <bitfield name="COEFF_33" low="0" high="12" type="uint"/>
+ </reg32>
+ <array offset="0x274" name="CSC_COMP_PRECLAMP" length="3" stride="4">
+ <reg32 offset="0" name="REG">
+ <bitfield name="HIGH" low="0" high="7" type="uint"/>
+ <bitfield name="LOW" low="8" high="15" type="uint"/>
+ </reg32>
+ </array>
+ <array offset="0x280" name="CSC_COMP_POSTCLAMP" length="3" stride="4">
+ <reg32 offset="0" name="REG">
+ <bitfield name="HIGH" low="0" high="7" type="uint"/>
+ <bitfield name="LOW" low="8" high="15" type="uint"/>
+ </reg32>
+ </array>
+ <array offset="0x28c" name="CSC_COMP_PREBIAS" length="3" stride="4">
+ <reg32 offset="0" name="REG">
+ <bitfield name="VALUE" low="0" high="8" type="uint"/>
+ </reg32>
+ </array>
+ <array offset="0x298" name="CSC_COMP_POSTBIAS" length="3" stride="4">
+ <reg32 offset="0" name="REG">
+ <bitfield name="VALUE" low="0" high="8" type="uint"/>
+ </reg32>
+ </array>
+ </array>
+
+ <array doffsets="mdp5_cfg->intf.base[0],mdp5_cfg->intf.base[1],mdp5_cfg->intf.base[2],mdp5_cfg->intf.base[3],mdp5_cfg->intf.base[4]" name="INTF" length="5" stride="0x200">
+ <reg32 offset="0x000" name="TIMING_ENGINE_EN"/>
+ <reg32 offset="0x004" name="CONFIG"/>
+ <reg32 offset="0x008" name="HSYNC_CTL">
+ <bitfield name="PULSEW" low="0" high="15" type="uint"/>
+ <bitfield name="PERIOD" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x00c" name="VSYNC_PERIOD_F0" type="uint"/>
+ <reg32 offset="0x010" name="VSYNC_PERIOD_F1" type="uint"/>
+ <reg32 offset="0x014" name="VSYNC_LEN_F0" type="uint"/>
+ <reg32 offset="0x018" name="VSYNC_LEN_F1" type="uint"/>
+ <reg32 offset="0x01c" name="DISPLAY_VSTART_F0" type="uint"/>
+ <reg32 offset="0x020" name="DISPLAY_VSTART_F1" type="uint"/>
+ <reg32 offset="0x024" name="DISPLAY_VEND_F0" type="uint"/>
+ <reg32 offset="0x028" name="DISPLAY_VEND_F1" type="uint"/>
+ <reg32 offset="0x02c" name="ACTIVE_VSTART_F0">
+ <bitfield name="VAL" low="0" high="30" type="uint"/>
+ <bitfield name="ACTIVE_V_ENABLE" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x030" name="ACTIVE_VSTART_F1">
+ <bitfield name="VAL" low="0" high="30" type="uint"/>
+ </reg32>
+ <reg32 offset="0x034" name="ACTIVE_VEND_F0" type="uint"/>
+ <reg32 offset="0x038" name="ACTIVE_VEND_F1" type="uint"/>
+ <reg32 offset="0x03c" name="DISPLAY_HCTL">
+ <bitfield name="START" low="0" high="15" type="uint"/>
+ <bitfield name="END" low="16" high="31" type="uint"/>
+ </reg32>
+ <reg32 offset="0x040" name="ACTIVE_HCTL">
+ <bitfield name="START" low="0" high="14" type="uint"/>
+ <bitfield name="END" low="16" high="30" type="uint"/>
+ <bitfield name="ACTIVE_H_ENABLE" pos="31" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x044" name="BORDER_COLOR"/>
+ <reg32 offset="0x048" name="UNDERFLOW_COLOR"/>
+ <reg32 offset="0x04c" name="HSYNC_SKEW"/>
+ <reg32 offset="0x050" name="POLARITY_CTL">
+ <bitfield name="HSYNC_LOW" pos="0" type="boolean"/>
+ <bitfield name="VSYNC_LOW" pos="1" type="boolean"/>
+ <bitfield name="DATA_EN_LOW" pos="2" type="boolean"/>
+ </reg32>
+ <reg32 offset="0x054" name="TEST_CTL"/>
+ <reg32 offset="0x058" name="TP_COLOR0"/>
+ <reg32 offset="0x05c" name="TP_COLOR1"/>
+ <reg32 offset="0x084" name="DSI_CMD_MODE_TRIGGER_EN"/>
+ <reg32 offset="0x090" name="PANEL_FORMAT" type="mdp5_format"/>
+ <reg32 offset="0x0a8" name="FRAME_LINE_COUNT_EN"/>
+ <reg32 offset="0x0ac" name="FRAME_COUNT"/>
+ <reg32 offset="0x0b0" name="LINE_COUNT"/>
+ <reg32 offset="0x0f0" name="DEFLICKER_CONFIG"/>
+ <reg32 offset="0x0f4" name="DEFLICKER_STRNG_COEFF"/>
+ <reg32 offset="0x0f8" name="DEFLICKER_WEAK_COEFF"/>
+ <reg32 offset="0x100" name="TPG_ENABLE"/>
+ <reg32 offset="0x104" name="TPG_MAIN_CONTROL"/>
+ <reg32 offset="0x108" name="TPG_VIDEO_CONFIG"/>
+ <reg32 offset="0x10c" name="TPG_COMPONENT_LIMITS"/>
+ <reg32 offset="0x110" name="TPG_RECTANGLE"/>
+ <reg32 offset="0x114" name="TPG_INITIAL_VALUE"/>
+ <reg32 offset="0x118" name="TPG_BLK_WHITE_PATTERN_FRAME"/>
+ <reg32 offset="0x11c" name="TPG_RGB_MAPPING"/>
+ </array>
+
+ <array doffsets="mdp5_cfg->ad.base[0],mdp5_cfg->ad.base[1]" name="AD" length="2" stride="0x200">
+ <reg32 offset="0x000" name="BYPASS"/>
+ <reg32 offset="0x004" name="CTRL_0"/>
+ <reg32 offset="0x008" name="CTRL_1"/>
+ <reg32 offset="0x00c" name="FRAME_SIZE"/>
+ <reg32 offset="0x010" name="CON_CTRL_0"/>
+ <reg32 offset="0x014" name="CON_CTRL_1"/>
+ <reg32 offset="0x018" name="STR_MAN"/>
+ <reg32 offset="0x01c" name="VAR"/>
+ <reg32 offset="0x020" name="DITH"/>
+ <reg32 offset="0x024" name="DITH_CTRL"/>
+ <reg32 offset="0x028" name="AMP_LIM"/>
+ <reg32 offset="0x02c" name="SLOPE"/>
+ <reg32 offset="0x030" name="BW_LVL"/>
+ <reg32 offset="0x034" name="LOGO_POS"/>
+ <reg32 offset="0x038" name="LUT_FI"/>
+ <reg32 offset="0x07c" name="LUT_CC"/>
+ <reg32 offset="0x0c8" name="STR_LIM"/>
+ <reg32 offset="0x0cc" name="CALIB_AB"/>
+ <reg32 offset="0x0d0" name="CALIB_CD"/>
+ <reg32 offset="0x0d4" name="MODE_SEL"/>
+ <reg32 offset="0x0d8" name="TFILT_CTRL"/>
+ <reg32 offset="0x0dc" name="BL_MINMAX"/>
+ <reg32 offset="0x0e0" name="BL"/>
+ <reg32 offset="0x0e8" name="BL_MAX"/>
+ <reg32 offset="0x0ec" name="AL"/>
+ <reg32 offset="0x0f0" name="AL_MIN"/>
+ <reg32 offset="0x0f4" name="AL_FILT"/>
+ <reg32 offset="0x0f8" name="CFG_BUF"/>
+ <reg32 offset="0x100" name="LUT_AL"/>
+ <reg32 offset="0x144" name="TARG_STR"/>
+ <reg32 offset="0x148" name="START_CALC"/>
+ <reg32 offset="0x14c" name="STR_OUT"/>
+ <reg32 offset="0x154" name="BL_OUT"/>
+ <reg32 offset="0x158" name="CALC_DONE"/>
+ </array>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/display/mdp_common.xml b/drivers/gpu/drm/msm/registers/display/mdp_common.xml
new file mode 100644
index 000000000000..f1b6345c1323
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/display/mdp_common.xml
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+
+
+<!-- random bits that seem same between mdp4 and mdp5 (ie. not much) -->
+
+<enum name="mdp_chroma_samp_type">
+ <value name="CHROMA_FULL" value="0"/>
+ <value name="CHROMA_H2V1" value="1"/>
+ <value name="CHROMA_H1V2" value="2"/>
+ <value name="CHROMA_420" value="3"/>
+</enum>
+
+<enum name="mdp_fetch_type">
+ <value name="MDP_PLANE_INTERLEAVED" value="0"/>
+ <value name="MDP_PLANE_PLANAR" value="1"/>
+ <value name="MDP_PLANE_PSEUDO_PLANAR" value="2"/>
+</enum>
+
+<enum name="mdp_mixer_stage_id">
+ <value name="STAGE_UNUSED" value="0"/>
+ <value name="STAGE_BASE" value="1"/>
+ <value name="STAGE0" value="2"/> <!-- zorder 0 -->
+ <value name="STAGE1" value="3"/> <!-- zorder 1 -->
+ <value name="STAGE2" value="4"/> <!-- zorder 2 -->
+ <value name="STAGE3" value="5"/> <!-- zorder 3 -->
+ <value name="STAGE4" value="6"/> <!-- zorder 4 -->
+ <value name="STAGE5" value="7"/> <!-- zorder 5 -->
+ <value name="STAGE6" value="8"/> <!-- zorder 6 -->
+ <value name="STAGE_MAX" value="8"/> <!-- maximum zorder -->
+</enum>
+
+<enum name="mdp_alpha_type">
+ <value name="FG_CONST" value="0"/>
+ <value name="BG_CONST" value="1"/>
+ <value name="FG_PIXEL" value="2"/>
+ <value name="BG_PIXEL" value="3"/>
+</enum>
+
+<enum name="mdp_component_type">
+ <value name="COMP_0" value="0"/> <!-- Y component -->
+ <value name="COMP_1_2" value="1"/> <!-- Cb/Cr comp. -->
+ <value name="COMP_3" value="2"/> <!-- Trans comp. -->
+ <value name="COMP_MAX" value="3"/>
+</enum>
+
+<enum name="mdp_bpc">
+ <brief>bits per component (non-alpha channel)</brief>
+ <value name="BPC4" value="0"/> <!-- 4 bits -->
+ <value name="BPC5" value="1"/> <!-- 5 bits -->
+ <value name="BPC6" value="2"/> <!-- 6 bits -->
+ <value name="BPC8" value="3"/> <!-- 8 bits -->
+</enum>
+
+<enum name="mdp_bpc_alpha">
+ <brief>bits per component (alpha channel)</brief>
+ <value name="BPC1A" value="0"/> <!-- 1 bit -->
+ <value name="BPC4A" value="1"/> <!-- 4 bits -->
+ <value name="BPC6A" value="2"/> <!-- 6 bits -->
+ <value name="BPC8A" value="3"/> <!-- 8 bits -->
+</enum>
+
+<enum name="mdp_fetch_mode">
+ <value name="MDP_FETCH_LINEAR" value="0"/>
+ <value name="MDP_FETCH_TILE" value="1"/>
+ <value name="MDP_FETCH_UBWC" value="2"/>
+</enum>
+
+<bitset name="reg_wh" inline="yes">
+ <bitfield name="HEIGHT" low="16" high="31" type="uint"/>
+ <bitfield name="WIDTH" low="0" high="15" type="uint"/>
+</bitset>
+
+<bitset name="reg_xy" inline="yes">
+ <bitfield name="Y" low="16" high="31" type="uint"/>
+ <bitfield name="X" low="0" high="15" type="uint"/>
+</bitset>
+
+<bitset name="mdp_unpack_pattern" inline="yes">
+ <bitfield name="ELEM0" low="0" high="7"/>
+ <bitfield name="ELEM1" low="8" high="15"/>
+ <bitfield name="ELEM2" low="16" high="23"/>
+ <bitfield name="ELEM3" low="24" high="31"/>
+</bitset>
+
+</database>
+
diff --git a/drivers/gpu/drm/msm/registers/display/msm.xml b/drivers/gpu/drm/msm/registers/display/msm.xml
new file mode 100644
index 000000000000..429c35b73bad
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/display/msm.xml
@@ -0,0 +1,32 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
+<import file="freedreno_copyright.xml"/>
+
+<doc>
+ Register definitions for the display related hw blocks on
+ msm/snapdragon
+</doc>
+
+<!--
+<enum name="chipset">
+ <value name="MDP40"/>
+ <value name="MDP50"/>
+</enum>
+-->
+
+<import file="mdp4.xml"/>
+<import file="mdp5.xml"/>
+<import file="dsi.xml"/>
+<import file="dsi_phy_28nm_8960.xml"/>
+<import file="dsi_phy_28nm.xml"/>
+<import file="dsi_phy_20nm.xml"/>
+<import file="dsi_phy_14nm.xml"/>
+<import file="dsi_phy_10nm.xml"/>
+<import file="dsi_phy_7nm.xml"/>
+<import file="sfpb.xml"/>
+<import file="hdmi.xml"/>
+<import file="edp.xml"/>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/display/sfpb.xml b/drivers/gpu/drm/msm/registers/display/sfpb.xml
new file mode 100644
index 000000000000..de1cf43c131f
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/display/sfpb.xml
@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+<import file="freedreno_copyright.xml"/>
+
+<domain name="SFPB" width="32">
+ <enum name="sfpb_ahb_arb_master_port_en">
+ <value name="SFPB_MASTER_PORT_ENABLE" value="3"/>
+ <value name="SFPB_MASTER_PORT_DISABLE" value="0"/>
+ </enum>
+ <reg32 offset="0x0058" name="GPREG">
+ <bitfield name="MASTER_PORT_EN" low="11" high="12" type="sfpb_ahb_arb_master_port_en"/>
+ </reg32>
+</domain>
+
+</database>
diff --git a/drivers/gpu/drm/msm/registers/freedreno_copyright.xml b/drivers/gpu/drm/msm/registers/freedreno_copyright.xml
new file mode 100644
index 000000000000..854efdd2e5fc
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/freedreno_copyright.xml
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<database xmlns="http://nouveau.freedesktop.org/"
+xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
+
+<copyright year="2013">
+
+<author name="Rob Clark" email="robdclark@gmail.com"><nick name="robclark"/>
+Initial Author.
+</author>
+
+<author name="Ilia Mirkin" email="imirkin@alum.mit.edu"><nick name="imirkin"/>
+many a3xx/a4xx contributions
+</author>
+
+<license>
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice (including the
+next paragraph) shall be included in all copies or substantial
+portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+</license>
+
+</copyright>
+</database>
+
diff --git a/drivers/gpu/drm/msm/registers/gen_header.py b/drivers/gpu/drm/msm/registers/gen_header.py
new file mode 100644
index 000000000000..fc3bfdc991d2
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/gen_header.py
@@ -0,0 +1,970 @@
+#!/usr/bin/python3
+#
+# Copyright © 2019-2024 Google, Inc.
+#
+# SPDX-License-Identifier: MIT
+
+import xml.parsers.expat
+import sys
+import os
+import collections
+import argparse
+import time
+import datetime
+
+class Error(Exception):
+ def __init__(self, message):
+ self.message = message
+
+class Enum(object):
+ def __init__(self, name):
+ self.name = name
+ self.values = []
+
+ def has_name(self, name):
+ for (n, value) in self.values:
+ if n == name:
+ return True
+ return False
+
+ def names(self):
+ return [n for (n, value) in self.values]
+
+ def dump(self):
+ use_hex = False
+ for (name, value) in self.values:
+ if value > 0x1000:
+ use_hex = True
+
+ print("enum %s {" % self.name)
+ for (name, value) in self.values:
+ if use_hex:
+ print("\t%s = 0x%08x," % (name, value))
+ else:
+ print("\t%s = %d," % (name, value))
+ print("};\n")
+
+ def dump_pack_struct(self):
+ pass
+
+class Field(object):
+ def __init__(self, name, low, high, shr, type, parser):
+ self.name = name
+ self.low = low
+ self.high = high
+ self.shr = shr
+ self.type = type
+
+ builtin_types = [ None, "a3xx_regid", "boolean", "uint", "hex", "int", "fixed", "ufixed", "float", "address", "waddress" ]
+
+ maxpos = parser.current_bitsize - 1
+
+ if low < 0 or low > maxpos:
+ raise parser.error("low attribute out of range: %d" % low)
+ if high < 0 or high > maxpos:
+ raise parser.error("high attribute out of range: %d" % high)
+ if high < low:
+ raise parser.error("low is greater than high: low=%d, high=%d" % (low, high))
+ if self.type == "boolean" and not low == high:
+ raise parser.error("booleans should be 1 bit fields")
+ elif self.type == "float" and not (high - low == 31 or high - low == 15):
+ raise parser.error("floats should be 16 or 32 bit fields")
+ elif not self.type in builtin_types and not self.type in parser.enums:
+ raise parser.error("unknown type '%s'" % self.type)
+
+ def ctype(self, var_name):
+ if self.type == None:
+ type = "uint32_t"
+ val = var_name
+ elif self.type == "boolean":
+ type = "bool"
+ val = var_name
+ elif self.type == "uint" or self.type == "hex" or self.type == "a3xx_regid":
+ type = "uint32_t"
+ val = var_name
+ elif self.type == "int":
+ type = "int32_t"
+ val = var_name
+ elif self.type == "fixed":
+ type = "float"
+ val = "((int32_t)(%s * %d.0))" % (var_name, 1 << self.radix)
+ elif self.type == "ufixed":
+ type = "float"
+ val = "((uint32_t)(%s * %d.0))" % (var_name, 1 << self.radix)
+ elif self.type == "float" and self.high - self.low == 31:
+ type = "float"
+ val = "fui(%s)" % var_name
+ elif self.type == "float" and self.high - self.low == 15:
+ type = "float"
+ val = "_mesa_float_to_half(%s)" % var_name
+ elif self.type in [ "address", "waddress" ]:
+ type = "uint64_t"
+ val = var_name
+ else:
+ type = "enum %s" % self.type
+ val = var_name
+
+ if self.shr > 0:
+ val = "(%s >> %d)" % (val, self.shr)
+
+ return (type, val)
+
+def tab_to(name, value):
+ tab_count = (68 - (len(name) & ~7)) // 8
+ if tab_count <= 0:
+ tab_count = 1
+ print(name + ('\t' * tab_count) + value)
+
+def mask(low, high):
+ return ((0xffffffffffffffff >> (64 - (high + 1 - low))) << low)
+
+def field_name(reg, f):
+ if f.name:
+ name = f.name.lower()
+ else:
+ # We hit this path when a reg is defined with no bitset fields, ie.
+ # <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint"/>
+ name = reg.name.lower()
+
+ if (name in [ "double", "float", "int" ]) or not (name[0].isalpha()):
+ name = "_" + name
+
+ return name
+
+# indices - array of (ctype, stride, __offsets_NAME)
+def indices_varlist(indices):
+ return ", ".join(["i%d" % i for i in range(len(indices))])
+
+def indices_prototype(indices):
+ return ", ".join(["%s i%d" % (ctype, idx)
+ for (idx, (ctype, stride, offset)) in enumerate(indices)])
+
+def indices_strides(indices):
+ return " + ".join(["0x%x*i%d" % (stride, idx)
+ if stride else
+ "%s(i%d)" % (offset, idx)
+ for (idx, (ctype, stride, offset)) in enumerate(indices)])
+
+class Bitset(object):
+ def __init__(self, name, template):
+ self.name = name
+ self.inline = False
+ if template:
+ self.fields = template.fields[:]
+ else:
+ self.fields = []
+
+ # Get address field if there is one in the bitset, else return None:
+ def get_address_field(self):
+ for f in self.fields:
+ if f.type in [ "address", "waddress" ]:
+ return f
+ return None
+
+ def dump_regpair_builder(self, reg):
+ print("#ifndef NDEBUG")
+ known_mask = 0
+ for f in self.fields:
+ known_mask |= mask(f.low, f.high)
+ if f.type in [ "boolean", "address", "waddress" ]:
+ continue
+ type, val = f.ctype("fields.%s" % field_name(reg, f))
+ print(" assert((%-40s & 0x%08x) == 0);" % (val, 0xffffffff ^ mask(0 , f.high - f.low)))
+ print(" assert((%-40s & 0x%08x) == 0);" % ("fields.unknown", known_mask))
+ print("#endif\n")
+
+ print(" return (struct fd_reg_pair) {")
+ if reg.array:
+ print(" .reg = REG_%s(__i)," % reg.full_name)
+ else:
+ print(" .reg = REG_%s," % reg.full_name)
+
+ print(" .value =")
+ for f in self.fields:
+ if f.type in [ "address", "waddress" ]:
+ continue
+ else:
+ type, val = f.ctype("fields.%s" % field_name(reg, f))
+ print(" (%-40s << %2d) |" % (val, f.low))
+ value_name = "dword"
+ if reg.bit_size == 64:
+ value_name = "qword"
+ print(" fields.unknown | fields.%s," % (value_name,))
+
+ address = self.get_address_field()
+ if address:
+ print(" .bo = fields.bo,")
+ print(" .is_address = true,")
+ if f.type == "waddress":
+ print(" .bo_write = true,")
+ print(" .bo_offset = fields.bo_offset,")
+ print(" .bo_shift = %d," % address.shr)
+ print(" .bo_low = %d," % address.low)
+
+ print(" };")
+
+ def dump_pack_struct(self, reg=None):
+ if not reg:
+ return
+
+ prefix = reg.full_name
+
+ print("struct %s {" % prefix)
+ for f in self.fields:
+ if f.type in [ "address", "waddress" ]:
+ tab_to(" __bo_type", "bo;")
+ tab_to(" uint32_t", "bo_offset;")
+ continue
+ name = field_name(reg, f)
+
+ type, val = f.ctype("var")
+
+ tab_to(" %s" % type, "%s;" % name)
+ if reg.bit_size == 64:
+ tab_to(" uint64_t", "unknown;")
+ tab_to(" uint64_t", "qword;")
+ else:
+ tab_to(" uint32_t", "unknown;")
+ tab_to(" uint32_t", "dword;")
+ print("};\n")
+
+ if reg.array:
+ print("static inline struct fd_reg_pair\npack_%s(uint32_t __i, struct %s fields)\n{" %
+ (prefix, prefix))
+ else:
+ print("static inline struct fd_reg_pair\npack_%s(struct %s fields)\n{" %
+ (prefix, prefix))
+
+ self.dump_regpair_builder(reg)
+
+ print("\n}\n")
+
+ if self.get_address_field():
+ skip = ", { .reg = 0 }"
+ else:
+ skip = ""
+
+ if reg.array:
+ print("#define %s(__i, ...) pack_%s(__i, __struct_cast(%s) { __VA_ARGS__ })%s\n" %
+ (prefix, prefix, prefix, skip))
+ else:
+ print("#define %s(...) pack_%s(__struct_cast(%s) { __VA_ARGS__ })%s\n" %
+ (prefix, prefix, prefix, skip))
+
+
+ def dump(self, prefix=None):
+ if prefix == None:
+ prefix = self.name
+ for f in self.fields:
+ if f.name:
+ name = prefix + "_" + f.name
+ else:
+ name = prefix
+
+ if not f.name and f.low == 0 and f.shr == 0 and not f.type in ["float", "fixed", "ufixed"]:
+ pass
+ elif f.type == "boolean" or (f.type == None and f.low == f.high):
+ tab_to("#define %s" % name, "0x%08x" % (1 << f.low))
+ else:
+ tab_to("#define %s__MASK" % name, "0x%08x" % mask(f.low, f.high))
+ tab_to("#define %s__SHIFT" % name, "%d" % f.low)
+ type, val = f.ctype("val")
+
+ print("static inline uint32_t %s(%s val)\n{" % (name, type))
+ if f.shr > 0:
+ print("\tassert(!(val & 0x%x));" % mask(0, f.shr - 1))
+ print("\treturn ((%s) << %s__SHIFT) & %s__MASK;\n}" % (val, name, name))
+ print()
+
+class Array(object):
+ def __init__(self, attrs, domain, variant, parent, index_type):
+ if "name" in attrs:
+ self.local_name = attrs["name"]
+ else:
+ self.local_name = ""
+ self.domain = domain
+ self.variant = variant
+ self.parent = parent
+ if self.parent:
+ self.name = self.parent.name + "_" + self.local_name
+ else:
+ self.name = self.local_name
+ if "offsets" in attrs:
+ self.offsets = map(lambda i: "0x%08x" % int(i, 0), attrs["offsets"].split(","))
+ self.fixed_offsets = True
+ elif "doffsets" in attrs:
+ self.offsets = map(lambda s: "(%s)" % s , attrs["doffsets"].split(","))
+ self.fixed_offsets = True
+ else:
+ self.offset = int(attrs["offset"], 0)
+ self.stride = int(attrs["stride"], 0)
+ self.fixed_offsets = False
+ if "index" in attrs:
+ self.index_type = index_type
+ else:
+ self.index_type = None
+ self.length = int(attrs["length"], 0)
+ if "usage" in attrs:
+ self.usages = attrs["usage"].split(',')
+ else:
+ self.usages = None
+
+ def index_ctype(self):
+ if not self.index_type:
+ return "uint32_t"
+ else:
+ return "enum %s" % self.index_type.name
+
+ # Generate array of (ctype, stride, __offsets_NAME)
+ def indices(self):
+ if self.parent:
+ indices = self.parent.indices()
+ else:
+ indices = []
+ if self.length != 1:
+ if self.fixed_offsets:
+ indices.append((self.index_ctype(), None, "__offset_%s" % self.local_name))
+ else:
+ indices.append((self.index_ctype(), self.stride, None))
+ return indices
+
+ def total_offset(self):
+ offset = 0
+ if not self.fixed_offsets:
+ offset += self.offset
+ if self.parent:
+ offset += self.parent.total_offset()
+ return offset
+
+ def dump(self):
+ proto = indices_varlist(self.indices())
+ strides = indices_strides(self.indices())
+ array_offset = self.total_offset()
+ if self.fixed_offsets:
+ print("static inline uint32_t __offset_%s(%s idx)" % (self.local_name, self.index_ctype()))
+ print("{\n\tswitch (idx) {")
+ if self.index_type:
+ for val, offset in zip(self.index_type.names(), self.offsets):
+ print("\t\tcase %s: return %s;" % (val, offset))
+ else:
+ for idx, offset in enumerate(self.offsets):
+ print("\t\tcase %d: return %s;" % (idx, offset))
+ print("\t\tdefault: return INVALID_IDX(idx);")
+ print("\t}\n}")
+ if proto == '':
+ tab_to("#define REG_%s_%s" % (self.domain, self.name), "0x%08x\n" % array_offset)
+ else:
+ tab_to("#define REG_%s_%s(%s)" % (self.domain, self.name, proto), "(0x%08x + %s )\n" % (array_offset, strides))
+
+ def dump_pack_struct(self):
+ pass
+
+ def dump_regpair_builder(self):
+ pass
+
+class Reg(object):
+ def __init__(self, attrs, domain, array, bit_size):
+ self.name = attrs["name"]
+ self.domain = domain
+ self.array = array
+ self.offset = int(attrs["offset"], 0)
+ self.type = None
+ self.bit_size = bit_size
+ if array:
+ self.name = array.name + "_" + self.name
+ self.full_name = self.domain + "_" + self.name
+ if "stride" in attrs:
+ self.stride = int(attrs["stride"], 0)
+ self.length = int(attrs["length"], 0)
+ else:
+ self.stride = None
+ self.length = None
+
+ # Generate array of (ctype, stride, __offsets_NAME)
+ def indices(self):
+ if self.array:
+ indices = self.array.indices()
+ else:
+ indices = []
+ if self.stride:
+ indices.append(("uint32_t", self.stride, None))
+ return indices
+
+ def total_offset(self):
+ if self.array:
+ return self.array.total_offset() + self.offset
+ else:
+ return self.offset
+
+ def dump(self):
+ proto = indices_prototype(self.indices())
+ strides = indices_strides(self.indices())
+ offset = self.total_offset()
+ if proto == '':
+ tab_to("#define REG_%s" % self.full_name, "0x%08x" % offset)
+ else:
+ print("static inline uint32_t REG_%s(%s) { return 0x%08x + %s; }" % (self.full_name, proto, offset, strides))
+
+ if self.bitset.inline:
+ self.bitset.dump(self.full_name)
+
+ def dump_pack_struct(self):
+ if self.bitset.inline:
+ self.bitset.dump_pack_struct(self)
+
+ def dump_regpair_builder(self):
+ if self.bitset.inline:
+ self.bitset.dump_regpair_builder(self)
+
+ def dump_py(self):
+ print("\tREG_%s = 0x%08x" % (self.full_name, self.offset))
+
+
+class Parser(object):
+ def __init__(self):
+ self.current_array = None
+ self.current_domain = None
+ self.current_prefix = None
+ self.current_prefix_type = None
+ self.current_stripe = None
+ self.current_bitset = None
+ self.current_bitsize = 32
+ # The varset attribute on the domain specifies the enum which
+ # specifies all possible hw variants:
+ self.current_varset = None
+ # Regs that have multiple variants.. we only generated the C++
+ # template based struct-packers for these
+ self.variant_regs = {}
+ # Information in which contexts regs are used, to be used in
+ # debug options
+ self.usage_regs = collections.defaultdict(list)
+ self.bitsets = {}
+ self.enums = {}
+ self.variants = set()
+ self.file = []
+ self.xml_files = []
+ self.copyright_year = None
+ self.authors = []
+ self.license = None
+
+ def error(self, message):
+ parser, filename = self.stack[-1]
+ return Error("%s:%d:%d: %s" % (filename, parser.CurrentLineNumber, parser.CurrentColumnNumber, message))
+
+ def prefix(self, variant=None):
+ if self.current_prefix_type == "variant" and variant:
+ return variant
+ elif self.current_stripe:
+ return self.current_stripe + "_" + self.current_domain
+ elif self.current_prefix:
+ return self.current_prefix + "_" + self.current_domain
+ else:
+ return self.current_domain
+
+ def parse_field(self, name, attrs):
+ try:
+ if "pos" in attrs:
+ high = low = int(attrs["pos"], 0)
+ elif "high" in attrs and "low" in attrs:
+ high = int(attrs["high"], 0)
+ low = int(attrs["low"], 0)
+ else:
+ low = 0
+ high = self.current_bitsize - 1
+
+ if "type" in attrs:
+ type = attrs["type"]
+ else:
+ type = None
+
+ if "shr" in attrs:
+ shr = int(attrs["shr"], 0)
+ else:
+ shr = 0
+
+ b = Field(name, low, high, shr, type, self)
+
+ if type == "fixed" or type == "ufixed":
+ b.radix = int(attrs["radix"], 0)
+
+ self.current_bitset.fields.append(b)
+ except ValueError as e:
+ raise self.error(e)
+
+ def parse_varset(self, attrs):
+ # Inherit the varset from the enclosing domain if not overriden:
+ varset = self.current_varset
+ if "varset" in attrs:
+ varset = self.enums[attrs["varset"]]
+ return varset
+
+ def parse_variants(self, attrs):
+ if not "variants" in attrs:
+ return None
+ variant = attrs["variants"].split(",")[0]
+ if "-" in variant:
+ variant = variant[:variant.index("-")]
+
+ varset = self.parse_varset(attrs)
+
+ assert varset.has_name(variant)
+
+ return variant
+
+ def add_all_variants(self, reg, attrs, parent_variant):
+ # TODO this should really handle *all* variants, including dealing
+ # with open ended ranges (ie. "A2XX,A4XX-") (we have the varset
+ # enum now to make that possible)
+ variant = self.parse_variants(attrs)
+ if not variant:
+ variant = parent_variant
+
+ if reg.name not in self.variant_regs:
+ self.variant_regs[reg.name] = {}
+ else:
+ # All variants must be same size:
+ v = next(iter(self.variant_regs[reg.name]))
+ assert self.variant_regs[reg.name][v].bit_size == reg.bit_size
+
+ self.variant_regs[reg.name][variant] = reg
+
+ def add_all_usages(self, reg, usages):
+ if not usages:
+ return
+
+ for usage in usages:
+ self.usage_regs[usage].append(reg)
+
+ self.variants.add(reg.domain)
+
+ def do_validate(self, schemafile):
+ if self.validate == False:
+ return
+
+ try:
+ from lxml import etree
+
+ parser, filename = self.stack[-1]
+ dirname = os.path.dirname(filename)
+
+ # we expect this to look like <namespace url> schema.xsd.. I think
+ # technically it is supposed to be just a URL, but that doesn't
+ # quite match up to what we do.. Just skip over everything up to
+ # and including the first whitespace character:
+ schemafile = schemafile[schemafile.rindex(" ")+1:]
+
+ # this is a bit cheezy, but the xml file to validate could be
+ # in a child director, ie. we don't really know where the schema
+ # file is, the way the rnn C code does. So if it doesn't exist
+ # just look one level up
+ if not os.path.exists(dirname + "/" + schemafile):
+ schemafile = "../" + schemafile
+
+ if not os.path.exists(dirname + "/" + schemafile):
+ raise self.error("Cannot find schema for: " + filename)
+
+ xmlschema_doc = etree.parse(dirname + "/" + schemafile)
+ xmlschema = etree.XMLSchema(xmlschema_doc)
+
+ xml_doc = etree.parse(filename)
+ if not xmlschema.validate(xml_doc):
+ error_str = str(xmlschema.error_log.filter_from_errors()[0])
+ raise self.error("Schema validation failed for: " + filename + "\n" + error_str)
+ except ImportError as e:
+ if self.validate:
+ raise e
+
+ print("lxml not found, skipping validation", file=sys.stderr)
+
+ def do_parse(self, filename):
+ filepath = os.path.abspath(filename)
+ if filepath in self.xml_files:
+ return
+ self.xml_files.append(filepath)
+ file = open(filename, "rb")
+ parser = xml.parsers.expat.ParserCreate()
+ self.stack.append((parser, filename))
+ parser.StartElementHandler = self.start_element
+ parser.EndElementHandler = self.end_element
+ parser.CharacterDataHandler = self.character_data
+ parser.buffer_text = True
+ parser.ParseFile(file)
+ self.stack.pop()
+ file.close()
+
+ def parse(self, rnn_path, filename, validate):
+ self.path = rnn_path
+ self.stack = []
+ self.validate = validate
+ self.do_parse(filename)
+
+ def parse_reg(self, attrs, bit_size):
+ self.current_bitsize = bit_size
+ if "type" in attrs and attrs["type"] in self.bitsets:
+ bitset = self.bitsets[attrs["type"]]
+ if bitset.inline:
+ self.current_bitset = Bitset(attrs["name"], bitset)
+ self.current_bitset.inline = True
+ else:
+ self.current_bitset = bitset
+ else:
+ self.current_bitset = Bitset(attrs["name"], None)
+ self.current_bitset.inline = True
+ if "type" in attrs:
+ self.parse_field(None, attrs)
+
+ variant = self.parse_variants(attrs)
+ if not variant and self.current_array:
+ variant = self.current_array.variant
+
+ self.current_reg = Reg(attrs, self.prefix(variant), self.current_array, bit_size)
+ self.current_reg.bitset = self.current_bitset
+
+ if len(self.stack) == 1:
+ self.file.append(self.current_reg)
+
+ if variant is not None:
+ self.add_all_variants(self.current_reg, attrs, variant)
+
+ usages = None
+ if "usage" in attrs:
+ usages = attrs["usage"].split(',')
+ elif self.current_array:
+ usages = self.current_array.usages
+
+ self.add_all_usages(self.current_reg, usages)
+
+ def start_element(self, name, attrs):
+ self.cdata = ""
+ if name == "import":
+ filename = attrs["file"]
+ self.do_parse(os.path.join(self.path, filename))
+ elif name == "domain":
+ self.current_domain = attrs["name"]
+ if "prefix" in attrs:
+ self.current_prefix = self.parse_variants(attrs)
+ self.current_prefix_type = attrs["prefix"]
+ else:
+ self.current_prefix = None
+ self.current_prefix_type = None
+ if "varset" in attrs:
+ self.current_varset = self.enums[attrs["varset"]]
+ elif name == "stripe":
+ self.current_stripe = self.parse_variants(attrs)
+ elif name == "enum":
+ self.current_enum_value = 0
+ self.current_enum = Enum(attrs["name"])
+ self.enums[attrs["name"]] = self.current_enum
+ if len(self.stack) == 1:
+ self.file.append(self.current_enum)
+ elif name == "value":
+ if "value" in attrs:
+ value = int(attrs["value"], 0)
+ else:
+ value = self.current_enum_value
+ self.current_enum.values.append((attrs["name"], value))
+ elif name == "reg32":
+ self.parse_reg(attrs, 32)
+ elif name == "reg64":
+ self.parse_reg(attrs, 64)
+ elif name == "array":
+ self.current_bitsize = 32
+ variant = self.parse_variants(attrs)
+ index_type = self.enums[attrs["index"]] if "index" in attrs else None
+ self.current_array = Array(attrs, self.prefix(variant), variant, self.current_array, index_type)
+ if len(self.stack) == 1:
+ self.file.append(self.current_array)
+ elif name == "bitset":
+ self.current_bitset = Bitset(attrs["name"], None)
+ if "inline" in attrs and attrs["inline"] == "yes":
+ self.current_bitset.inline = True
+ self.bitsets[self.current_bitset.name] = self.current_bitset
+ if len(self.stack) == 1 and not self.current_bitset.inline:
+ self.file.append(self.current_bitset)
+ elif name == "bitfield" and self.current_bitset:
+ self.parse_field(attrs["name"], attrs)
+ elif name == "database":
+ self.do_validate(attrs["xsi:schemaLocation"])
+ elif name == "copyright":
+ self.copyright_year = attrs["year"]
+ elif name == "author":
+ self.authors.append(attrs["name"] + " <" + attrs["email"] + "> " + attrs["name"])
+
+ def end_element(self, name):
+ if name == "domain":
+ self.current_domain = None
+ self.current_prefix = None
+ self.current_prefix_type = None
+ elif name == "stripe":
+ self.current_stripe = None
+ elif name == "bitset":
+ self.current_bitset = None
+ elif name == "reg32":
+ self.current_reg = None
+ elif name == "array":
+ self.current_array = self.current_array.parent
+ elif name == "enum":
+ self.current_enum = None
+ elif name == "license":
+ self.license = self.cdata
+
+ def character_data(self, data):
+ self.cdata += data
+
+ def dump_reg_usages(self):
+ d = collections.defaultdict(list)
+ for usage, regs in self.usage_regs.items():
+ for reg in regs:
+ variants = self.variant_regs.get(reg.name)
+ if variants:
+ for variant, vreg in variants.items():
+ if reg == vreg:
+ d[(usage, variant)].append(reg)
+ else:
+ for variant in self.variants:
+ d[(usage, variant)].append(reg)
+
+ print("#ifdef __cplusplus")
+
+ for usage, regs in self.usage_regs.items():
+ print("template<chip CHIP> constexpr inline uint16_t %s_REGS[] = {};" % (usage.upper()))
+
+ for (usage, variant), regs in d.items():
+ offsets = []
+
+ for reg in regs:
+ if reg.array:
+ for i in range(reg.array.length):
+ offsets.append(reg.array.offset + reg.offset + i * reg.array.stride)
+ if reg.bit_size == 64:
+ offsets.append(offsets[-1] + 1)
+ else:
+ offsets.append(reg.offset)
+ if reg.bit_size == 64:
+ offsets.append(offsets[-1] + 1)
+
+ offsets.sort()
+
+ print("template<> constexpr inline uint16_t %s_REGS<%s>[] = {" % (usage.upper(), variant))
+ for offset in offsets:
+ print("\t%s," % hex(offset))
+ print("};")
+
+ print("#endif")
+
+ def dump(self):
+ enums = []
+ bitsets = []
+ regs = []
+ for e in self.file:
+ if isinstance(e, Enum):
+ enums.append(e)
+ elif isinstance(e, Bitset):
+ bitsets.append(e)
+ else:
+ regs.append(e)
+
+ for e in enums + bitsets + regs:
+ e.dump()
+
+ self.dump_reg_usages()
+
+
+ def dump_regs_py(self):
+ regs = []
+ for e in self.file:
+ if isinstance(e, Reg):
+ regs.append(e)
+
+ for e in regs:
+ e.dump_py()
+
+
+ def dump_reg_variants(self, regname, variants):
+ # Don't bother for things that only have a single variant:
+ if len(variants) == 1:
+ return
+ print("#ifdef __cplusplus")
+ print("struct __%s {" % regname)
+ # TODO be more clever.. we should probably figure out which
+ # fields have the same type in all variants (in which they
+ # appear) and stuff everything else in a variant specific
+ # sub-structure.
+ seen_fields = []
+ bit_size = 32
+ array = False
+ address = None
+ for variant in variants.keys():
+ print(" /* %s fields: */" % variant)
+ reg = variants[variant]
+ bit_size = reg.bit_size
+ array = reg.array
+ for f in reg.bitset.fields:
+ fld_name = field_name(reg, f)
+ if fld_name in seen_fields:
+ continue
+ seen_fields.append(fld_name)
+ name = fld_name.lower()
+ if f.type in [ "address", "waddress" ]:
+ if address:
+ continue
+ address = f
+ tab_to(" __bo_type", "bo;")
+ tab_to(" uint32_t", "bo_offset;")
+ continue
+ type, val = f.ctype("var")
+ tab_to(" %s" %type, "%s;" %name)
+ print(" /* fallback fields: */")
+ if bit_size == 64:
+ tab_to(" uint64_t", "unknown;")
+ tab_to(" uint64_t", "qword;")
+ else:
+ tab_to(" uint32_t", "unknown;")
+ tab_to(" uint32_t", "dword;")
+ print("};")
+ # TODO don't hardcode the varset enum name
+ varenum = "chip"
+ print("template <%s %s>" % (varenum, varenum.upper()))
+ print("static inline struct fd_reg_pair")
+ xtra = ""
+ xtravar = ""
+ if array:
+ xtra = "int __i, "
+ xtravar = "__i, "
+ print("__%s(%sstruct __%s fields) {" % (regname, xtra, regname))
+ for variant in variants.keys():
+ print(" if (%s == %s) {" % (varenum.upper(), variant))
+ reg = variants[variant]
+ reg.dump_regpair_builder()
+ print(" } else")
+ print(" assert(!\"invalid variant\");")
+ print("}")
+
+ if bit_size == 64:
+ skip = ", { .reg = 0 }"
+ else:
+ skip = ""
+
+ print("#define %s(VARIANT, %s...) __%s<VARIANT>(%s{__VA_ARGS__})%s" % (regname, xtravar, regname, xtravar, skip))
+ print("#endif /* __cplusplus */")
+
+ def dump_structs(self):
+ for e in self.file:
+ e.dump_pack_struct()
+
+ for regname in self.variant_regs:
+ self.dump_reg_variants(regname, self.variant_regs[regname])
+
+
+def dump_c(args, guard, func):
+ p = Parser()
+
+ try:
+ p.parse(args.rnn, args.xml, args.validate)
+ except Error as e:
+ print(e, file=sys.stderr)
+ exit(1)
+
+ print("#ifndef %s\n#define %s\n" % (guard, guard))
+
+ print("""/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
+http://gitlab.freedesktop.org/mesa/mesa/
+git clone https://gitlab.freedesktop.org/mesa/mesa.git
+
+The rules-ng-ng source files this header was generated from are:
+""")
+ maxlen = 0
+ for filepath in p.xml_files:
+ maxlen = max(maxlen, len(filepath))
+ for filepath in p.xml_files:
+ pad = " " * (maxlen - len(filepath))
+ filesize = str(os.path.getsize(filepath))
+ filesize = " " * (7 - len(filesize)) + filesize
+ filetime = time.ctime(os.path.getmtime(filepath))
+ print("- " + filepath + pad + " (" + filesize + " bytes, from " + filetime + ")")
+ if p.copyright_year:
+ current_year = str(datetime.date.today().year)
+ print()
+ print("Copyright (C) %s-%s by the following authors:" % (p.copyright_year, current_year))
+ for author in p.authors:
+ print("- " + author)
+ if p.license:
+ print(p.license)
+ print("*/")
+
+ print()
+ print("#ifdef __KERNEL__")
+ print("#include <linux/bug.h>")
+ print("#define assert(x) BUG_ON(!(x))")
+ print("#else")
+ print("#include <assert.h>")
+ print("#endif")
+ print()
+
+ print("#ifdef __cplusplus")
+ print("#define __struct_cast(X)")
+ print("#else")
+ print("#define __struct_cast(X) (struct X)")
+ print("#endif")
+ print()
+
+ func(p)
+
+ print("\n#endif /* %s */" % guard)
+
+
+def dump_c_defines(args):
+ guard = str.replace(os.path.basename(args.xml), '.', '_').upper()
+ dump_c(args, guard, lambda p: p.dump())
+
+
+def dump_c_pack_structs(args):
+ guard = str.replace(os.path.basename(args.xml), '.', '_').upper() + '_STRUCTS'
+ dump_c(args, guard, lambda p: p.dump_structs())
+
+
+def dump_py_defines(args):
+ p = Parser()
+
+ try:
+ p.parse(args.rnn, args.xml)
+ except Error as e:
+ print(e, file=sys.stderr)
+ exit(1)
+
+ file_name = os.path.splitext(os.path.basename(args.xml))[0]
+
+ print("from enum import IntEnum")
+ print("class %sRegs(IntEnum):" % file_name.upper())
+
+ os.path.basename(args.xml)
+
+ p.dump_regs_py()
+
+
+def main():
+ parser = argparse.ArgumentParser()
+ parser.add_argument('--rnn', type=str, required=True)
+ parser.add_argument('--xml', type=str, required=True)
+ parser.add_argument('--validate', action=argparse.BooleanOptionalAction)
+
+ subparsers = parser.add_subparsers()
+ subparsers.required = True
+
+ parser_c_defines = subparsers.add_parser('c-defines')
+ parser_c_defines.set_defaults(func=dump_c_defines)
+
+ parser_c_pack_structs = subparsers.add_parser('c-pack-structs')
+ parser_c_pack_structs.set_defaults(func=dump_c_pack_structs)
+
+ parser_py_defines = subparsers.add_parser('py-defines')
+ parser_py_defines.set_defaults(func=dump_py_defines)
+
+ args = parser.parse_args()
+ args.func(args)
+
+
+if __name__ == '__main__':
+ main()
diff --git a/drivers/gpu/drm/msm/registers/rules-fd.xsd b/drivers/gpu/drm/msm/registers/rules-fd.xsd
new file mode 100644
index 000000000000..2eedb099a4eb
--- /dev/null
+++ b/drivers/gpu/drm/msm/registers/rules-fd.xsd
@@ -0,0 +1,404 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<schema xmlns="http://www.w3.org/2001/XMLSchema"
+ targetNamespace="http://nouveau.freedesktop.org/"
+ xmlns:rng="http://nouveau.freedesktop.org/"
+ elementFormDefault="qualified">
+
+ <annotation>
+ <documentation>
+ An updated version of the old rules.xml file from the
+ RivaTV project. Specifications by Pekka Paalanen,
+ preliminary attempt by KoalaBR,
+ first working version by Jakob Bornecrantz.
+ For specifications, see the file rules-ng-format.txt
+ in Nouveau CVS module 'rules-ng'.
+ </documentation>
+ <documentation>Version 0.1</documentation>
+ </annotation>
+
+
+ <!-- Elements -->
+
+ <element name="database" type="rng:databaseType" />
+ <element name="import" type="rng:importType" />
+ <element name="copyright" type="rng:copyrightType" />
+ <element name="domain" type="rng:domainType" />
+ <element name="array" type="rng:arrayType" />
+ <element name="stripe" type="rng:stripeType" />
+ <element name="reg64" type="rng:registerType" />
+ <element name="reg32" type="rng:registerType" />
+ <element name="bitset" type="rng:bitsetType" />
+ <element name="bitfield" type="rng:bitfieldType" />
+ <element name="enum" type="rng:enumType" />
+ <element name="value" type="rng:valueType" />
+
+ <!-- Copyright elements -->
+ <element name="author" type="rng:authorType" />
+ <element name="nick" type="rng:nickType" />
+ <element name="license" type="rng:docType" />
+
+ <!-- Documentation elements -->
+
+ <!-- FIXME: allowed only one per parent element -->
+ <element name="brief" type="rng:briefType" />
+
+ <element name="doc" type="rng:docType" />
+ <element name="b" type="rng:textformatType" />
+ <element name="i" type="rng:textformatType" />
+ <element name="u" type="rng:textformatType" />
+ <element name="code" type="rng:textcodeType" />
+ <element name="ul" type="rng:listType" />
+ <element name="ol" type="rng:listType" />
+ <element name="li" type="rng:listitemType" />
+
+ <!-- Copyright element types -->
+
+ <complexType name="authorType" mixed="true">
+ <annotation>
+ <documentation>
+ register database author
+ </documentation>
+ </annotation>
+ <choice minOccurs="0" maxOccurs="unbounded">
+ <element ref="rng:nick" />
+ </choice>
+ <attribute name="name" type="string" use="required" />
+ <attribute name="email" type="string" use="required" />
+ </complexType>
+
+ <complexType name="nickType">
+ <annotation>
+ <documentation>nickType</documentation>
+ </annotation>
+ <attribute name="name" type="string" use="required" />
+ </complexType>
+
+ <!-- Database element types -->
+
+ <complexType name="databaseType">
+ <annotation>
+ <documentation>databaseType</documentation>
+ </annotation>
+ <choice minOccurs="0" maxOccurs="unbounded">
+ <group ref="rng:docGroup" />
+ <group ref="rng:topGroup" />
+ </choice>
+ </complexType>
+
+ <complexType name="importType">
+ <annotation>
+ <documentation>importType</documentation>
+ </annotation>
+ <attribute name="file" type="string" use="required" />
+ </complexType>
+
+ <complexType name="copyrightType">
+ <annotation>
+ <documentation>copyrightType</documentation>
+ </annotation>
+ <choice minOccurs="0" maxOccurs="unbounded">
+ <group ref="rng:docGroup" />
+ <group ref="rng:topGroup" />
+ <element ref="rng:author" />
+ <element ref="rng:license" />
+ </choice>
+ <attribute name="year" type="nonNegativeInteger" use="optional" />
+ </complexType>
+
+ <complexType name="domainType">
+ <annotation>
+ <documentation>domainType</documentation>
+ </annotation>
+ <choice minOccurs="0" maxOccurs="unbounded">
+ <group ref="rng:docGroup" />
+ <group ref="rng:topGroup" />
+ <group ref="rng:regarrayGroup" />
+ </choice>
+ <attribute name="name" type="NMTOKEN" use="required" />
+ <attribute name="prefix" type="NMTOKENS" use="optional" />
+ <attribute name="width" type="rng:DomainWidth" use="optional" />
+ <attribute name="varset" type="NMTOKEN" use="optional" />
+ <attribute name="variants" type="string" use="optional" />
+ </complexType>
+
+ <complexType name="arrayType">
+ <annotation>
+ <documentation>arrayType</documentation>
+ </annotation>
+ <choice minOccurs="0" maxOccurs="unbounded">
+ <group ref="rng:docGroup" />
+ <group ref="rng:topGroup" />
+ <group ref="rng:regarrayGroup" />
+ </choice>
+ <attribute name="name" type="NMTOKEN" use="optional" />
+ <attribute name="offset" type="rng:HexOrNumber" use="optional" />
+ <attribute name="offsets" type="string" use="optional"/>
+ <attribute name="doffsets" type="string" use="optional"/>
+ <attribute name="index" type="NMTOKENS" use="optional"/>
+ <attribute name="stride" type="rng:HexOrNumber" use="required" />
+ <attribute name="length" type="rng:HexOrNumber" use="required" />
+ <attribute name="varset" type="NMTOKEN" use="optional" />
+ <attribute name="variants" type="string" use="optional" />
+ <attribute name="usage" type="string" use="optional" />
+ </complexType>
+
+ <complexType name="stripeType">
+ <annotation>
+ <documentation>stripeType</documentation>
+ </annotation>
+ <choice minOccurs="0" maxOccurs="unbounded">
+ <group ref="rng:docGroup" />
+ <group ref="rng:topGroup" />
+ <group ref="rng:regarrayGroup" minOccurs="0" />
+ </choice>
+ <attribute name="varset" type="NMTOKEN" use="optional" />
+ <attribute name="variants" type="string" use="optional" />
+ <attribute name="prefix" type="NMTOKENS" use="optional" />
+ </complexType>
+
+ <complexType name="registerType">
+ <annotation>
+ <documentation>
+ registerType used by reg32, reg64
+ </documentation>
+ </annotation>
+ <choice minOccurs="0" maxOccurs="unbounded">
+ <group ref="rng:docGroup" />
+ <group ref="rng:topGroup" />
+ <element ref="rng:value" />
+ <element ref="rng:bitfield" />
+ </choice>
+ <attribute name="name" type="NMTOKEN" use="required" />
+ <attribute name="offset" type="rng:HexOrNumber" use="required" />
+ <attribute name="type" type="NMTOKENS" use="optional" />
+ <attribute name="shr" type="nonNegativeInteger" use="optional" />
+ <attribute name="varset" type="NMTOKEN" use="optional" />
+ <attribute name="variants" type="string" use="optional" />
+ <attribute name="stride" type="rng:HexOrNumber" use="optional" />
+ <attribute name="length" type="rng:HexOrNumber" use="optional" />
+ <attribute name="high" type="nonNegativeInteger" use="optional" />
+ <attribute name="low" type="nonNegativeInteger" use="optional" />
+ <attribute name="pos" type="nonNegativeInteger" use="optional" />
+ <attribute name="align" type="nonNegativeInteger" use="optional" />
+ <attribute name="radix" type="nonNegativeInteger" use="optional" />
+ <attribute name="usage" type="string" use="optional" />
+ </complexType>
+
+ <complexType name="bitsetType">
+ <annotation>
+ <documentation>bitsetType</documentation>
+ </annotation>
+ <choice maxOccurs="unbounded">
+ <element ref="rng:bitfield" />
+ <group ref="rng:docGroup" />
+ <group ref="rng:topGroup" />
+ </choice>
+ <attribute name="name" type="NMTOKEN" use="required" />
+ <attribute name="inline" type="rng:Boolean" use="optional" />
+ <attribute name="varset" type="NMTOKEN" use="optional" />
+ </complexType>
+
+ <complexType name="bitfieldType">
+ <annotation>
+ <documentation>bitfieldType</documentation>
+ </annotation>
+ <choice minOccurs="0" maxOccurs="unbounded">
+ <element ref="rng:value" maxOccurs="unbounded" />
+ <group ref="rng:docGroup" />
+ <group ref="rng:topGroup" />
+ </choice>
+ <attribute name="name" type="NMTOKEN" use="required" />
+ <attribute name="high" type="nonNegativeInteger" use="optional" />
+ <attribute name="low" type="nonNegativeInteger" use="optional" />
+ <attribute name="pos" type="nonNegativeInteger" use="optional" />
+ <attribute name="radix" type="nonNegativeInteger" use="optional" />
+ <attribute name="type" type="NMTOKENS" use="optional" />
+ <attribute name="varset" type="NMTOKEN" use="optional" />
+ <attribute name="variants" type="string" use="optional" />
+ <attribute name="addvariant" type="rng:Boolean" use="optional" />
+ <attribute name="shr" type="nonNegativeInteger" use="optional" />
+ </complexType>
+
+ <complexType name="enumType">
+ <annotation>
+ <documentation>enumType</documentation>
+ </annotation>
+ <choice maxOccurs="unbounded">
+ <element ref="rng:value" />
+ <group ref="rng:docGroup" />
+ <group ref="rng:topGroup" />
+ </choice>
+ <attribute name="name" type="NMTOKEN" use="required" />
+ <attribute name="bare" type="rng:Boolean" use="optional" />
+ <attribute name="prefix" type="NMTOKENS" use="optional" />
+ <attribute name="varset" type="NMTOKEN" use="optional" />
+ </complexType>
+
+ <complexType name="valueType">
+ <annotation>
+ <documentation>valueType</documentation>
+ </annotation>
+ <choice minOccurs="0" maxOccurs="unbounded">
+ <group ref="rng:docGroup" />
+ <group ref="rng:topGroup" />
+ </choice>
+ <attribute name="name" type="NMTOKEN" use="required" />
+ <attribute name="value" type="string" use="optional" />
+ <attribute name="varset" type="NMTOKEN" use="optional" />
+ <attribute name="variants" type="string" use="optional" />
+ </complexType>
+
+ <!-- Documentation element types -->
+
+ <complexType name="briefType">
+ <annotation>
+ <documentation>
+ brief documentation, no markup
+ </documentation>
+ </annotation>
+ <simpleContent>
+ <extension base="string" />
+ </simpleContent>
+ </complexType>
+
+ <complexType name="docType" mixed="true">
+ <annotation>
+ <documentation>
+ root element of documentation sub-tree
+ </documentation>
+ </annotation>
+ <choice minOccurs="0" maxOccurs="unbounded">
+ <group ref="rng:textformatGroup" />
+ <group ref="rng:listGroup" />
+ <element ref="rng:code" />
+ </choice>
+ </complexType>
+
+ <complexType name="textformatType" mixed="true">
+ <annotation>
+ <documentation>
+ for bold, underline, italics
+ </documentation>
+ </annotation>
+ <choice minOccurs="0" maxOccurs="unbounded">
+ <group ref="rng:textformatGroup" />
+ </choice>
+ </complexType>
+
+ <complexType name="textcodeType">
+ <simpleContent>
+ <extension base="string">
+ <attribute name="title" type="string" />
+ </extension>
+ </simpleContent>
+ </complexType>
+
+ <complexType name="listType">
+ <annotation>
+ <documentation>
+ definition of a list, ordered or unordered
+ </documentation>
+ </annotation>
+ <choice minOccurs="0" maxOccurs="unbounded">
+ <element ref="rng:li" />
+ </choice>
+ </complexType>
+
+ <complexType name="listitemType" mixed="true">
+ <annotation>
+ <documentation>
+ items of a list
+ </documentation>
+ </annotation>
+ <choice minOccurs="0" maxOccurs="unbounded">
+ <group ref="rng:textformatGroup" />
+ <group ref="rng:listGroup" />
+ <element ref="rng:code" />
+ </choice>
+ </complexType>
+
+
+
+ <!-- Attribute value types -->
+
+ <simpleType name="Hexadecimal">
+ <restriction base="string">
+ <pattern value="0x[0-9a-f]+" />
+ <pattern value="0x[0-9A-F]+" />
+ <pattern value="[0-9]" />
+ </restriction>
+ </simpleType>
+
+ <simpleType name="HexOrNumber">
+ <annotation>
+ <documentation>HexOrNumber</documentation>
+ </annotation>
+ <union memberTypes="rng:Hexadecimal nonNegativeInteger" />
+ </simpleType>
+
+ <simpleType name="Boolean">
+ <restriction base="string">
+ <enumeration value="true" />
+ <enumeration value="1" />
+ <enumeration value="yes" />
+ <enumeration value="false" />
+ <enumeration value="0" />
+ <enumeration value="no" />
+ </restriction>
+ </simpleType>
+
+ <simpleType name="DomainWidth">
+ <annotation>
+ <documentation>DomainWidth</documentation>
+ </annotation>
+ <restriction base="string">
+ <enumeration value="32" />
+ </restriction>
+ </simpleType>
+
+
+
+ <!-- Element groups -->
+
+ <group name="topGroup">
+ <choice>
+ <element ref="rng:copyright" />
+ <element ref="rng:domain" />
+ <element ref="rng:enum" />
+ <element ref="rng:bitset" />
+ <element ref="rng:import" />
+ </choice>
+ </group>
+
+ <group name="regarrayGroup">
+ <choice>
+ <element ref="rng:reg64" />
+ <element ref="rng:reg32" />
+ <element ref="rng:array" />
+ <element ref="rng:stripe" />
+ </choice>
+ </group>
+
+ <group name="docGroup">
+ <choice>
+ <element ref="rng:brief" />
+ <element ref="rng:doc" />
+ </choice>
+ </group>
+
+ <group name="textformatGroup">
+ <choice>
+ <element ref="rng:b" />
+ <element ref="rng:i" />
+ <element ref="rng:u" />
+ </choice>
+ </group>
+
+ <group name="listGroup">
+ <choice>
+ <element ref="rng:ul" />
+ <element ref="rng:ol" />
+ </choice>
+ </group>
+
+</schema>
diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
index 9818d994c68b..621d0453bf76 100644
--- a/drivers/phy/qualcomm/phy-qcom-edp.c
+++ b/drivers/phy/qualcomm/phy-qcom-edp.c
@@ -14,6 +14,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy/phy.h>
+#include <linux/phy/phy-dp.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
@@ -69,19 +70,21 @@
#define TXn_TRAN_DRVR_EMP_EN 0x0078
-struct qcom_edp_cfg {
- bool is_dp;
-
- /* DP PHY swing and pre_emphasis tables */
+struct qcom_edp_swing_pre_emph_cfg {
const u8 (*swing_hbr_rbr)[4][4];
const u8 (*swing_hbr3_hbr2)[4][4];
const u8 (*pre_emphasis_hbr_rbr)[4][4];
const u8 (*pre_emphasis_hbr3_hbr2)[4][4];
};
+struct qcom_edp_phy_cfg {
+ bool is_edp;
+ const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg;
+};
+
struct qcom_edp {
struct device *dev;
- const struct qcom_edp_cfg *cfg;
+ const struct qcom_edp_phy_cfg *cfg;
struct phy *phy;
@@ -97,6 +100,8 @@ struct qcom_edp {
struct clk_bulk_data clks[2];
struct regulator_bulk_data supplies[2];
+
+ bool is_edp;
};
static const u8 dp_swing_hbr_rbr[4][4] = {
@@ -127,8 +132,7 @@ static const u8 dp_pre_emp_hbr2_hbr3[4][4] = {
{ 0x04, 0xff, 0xff, 0xff }
};
-static const struct qcom_edp_cfg dp_phy_cfg = {
- .is_dp = true,
+static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg = {
.swing_hbr_rbr = &dp_swing_hbr_rbr,
.swing_hbr3_hbr2 = &dp_swing_hbr2_hbr3,
.pre_emphasis_hbr_rbr = &dp_pre_emp_hbr_rbr,
@@ -163,18 +167,28 @@ static const u8 edp_pre_emp_hbr2_hbr3[4][4] = {
{ 0x00, 0xff, 0xff, 0xff }
};
-static const struct qcom_edp_cfg edp_phy_cfg = {
- .is_dp = false,
+static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg = {
.swing_hbr_rbr = &edp_swing_hbr_rbr,
.swing_hbr3_hbr2 = &edp_swing_hbr2_hbr3,
.pre_emphasis_hbr_rbr = &edp_pre_emp_hbr_rbr,
.pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3,
};
+static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = {
+};
+
+static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg = {
+ .swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
+};
+
+static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg = {
+ .is_edp = true,
+ .swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,
+};
+
static int qcom_edp_phy_init(struct phy *phy)
{
struct qcom_edp *edp = phy_get_drvdata(phy);
- const struct qcom_edp_cfg *cfg = edp->cfg;
int ret;
u8 cfg8;
@@ -201,7 +215,12 @@ static int qcom_edp_phy_init(struct phy *phy)
DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
edp->edp + DP_PHY_PD_CTL);
- if (cfg && cfg->is_dp)
+ /*
+ * TODO: Re-work the conditions around setting the cfg8 value
+ * when more information becomes available about why this is
+ * even needed.
+ */
+ if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp)
cfg8 = 0xb7;
else
cfg8 = 0x37;
@@ -235,7 +254,7 @@ out_disable_supplies:
static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configure_opts_dp *dp_opts)
{
- const struct qcom_edp_cfg *cfg = edp->cfg;
+ const struct qcom_edp_swing_pre_emph_cfg *cfg = edp->cfg->swing_pre_emph_cfg;
unsigned int v_level = 0;
unsigned int p_level = 0;
u8 ldo_config;
@@ -246,6 +265,9 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configur
if (!cfg)
return 0;
+ if (edp->is_edp)
+ cfg = &edp_phy_swing_pre_emph_cfg;
+
for (i = 0; i < dp_opts->lanes; i++) {
v_level = max(v_level, dp_opts->voltage[i]);
p_level = max(p_level, dp_opts->pre[i]);
@@ -262,7 +284,7 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_configur
if (swing == 0xff || emph == 0xff)
return -EINVAL;
- ldo_config = (cfg && cfg->is_dp) ? 0x1 : 0x0;
+ ldo_config = edp->is_edp ? 0x0 : 0x1;
writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);
writel(swing, edp->tx0 + TXn_TX_DRV_LVL);
@@ -448,10 +470,9 @@ static int qcom_edp_set_vco_div(const struct qcom_edp *edp, unsigned long *pixel
static int qcom_edp_phy_power_on(struct phy *phy)
{
const struct qcom_edp *edp = phy_get_drvdata(phy);
- const struct qcom_edp_cfg *cfg = edp->cfg;
u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
unsigned long pixel_freq;
- u8 ldo_config;
+ u8 ldo_config = 0x0;
int timeout;
int ret;
u32 val;
@@ -469,7 +490,8 @@ static int qcom_edp_phy_power_on(struct phy *phy)
return timeout;
- ldo_config = (cfg && cfg->is_dp) ? 0x1 : 0x0;
+ if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp)
+ ldo_config = 0x1;
writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG);
writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG);
@@ -590,6 +612,18 @@ static int qcom_edp_phy_power_off(struct phy *phy)
return 0;
}
+static int qcom_edp_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+ struct qcom_edp *edp = phy_get_drvdata(phy);
+
+ if (mode != PHY_MODE_DP)
+ return -EINVAL;
+
+ edp->is_edp = submode == PHY_SUBMODE_EDP;
+
+ return 0;
+}
+
static int qcom_edp_phy_exit(struct phy *phy)
{
struct qcom_edp *edp = phy_get_drvdata(phy);
@@ -605,6 +639,7 @@ static const struct phy_ops qcom_edp_ops = {
.configure = qcom_edp_phy_configure,
.power_on = qcom_edp_phy_power_on,
.power_off = qcom_edp_phy_power_off,
+ .set_mode = qcom_edp_phy_set_mode,
.exit = qcom_edp_phy_exit,
.owner = THIS_MODULE,
};
@@ -782,6 +817,7 @@ static int qcom_edp_phy_probe(struct platform_device *pdev)
edp->dev = dev;
edp->cfg = of_device_get_match_data(&pdev->dev);
+ edp->is_edp = edp->cfg->is_edp;
edp->edp = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(edp->edp))
@@ -840,10 +876,10 @@ static int qcom_edp_phy_probe(struct platform_device *pdev)
}
static const struct of_device_id qcom_edp_phy_match_table[] = {
- { .compatible = "qcom,sc7280-edp-phy" },
- { .compatible = "qcom,sc8180x-edp-phy" },
- { .compatible = "qcom,sc8280xp-dp-phy", .data = &dp_phy_cfg },
- { .compatible = "qcom,sc8280xp-edp-phy", .data = &edp_phy_cfg },
+ { .compatible = "qcom,sc7280-edp-phy", .data = &sc7280_dp_phy_cfg, },
+ { .compatible = "qcom,sc8180x-edp-phy", .data = &sc7280_dp_phy_cfg, },
+ { .compatible = "qcom,sc8280xp-dp-phy", .data = &sc8280xp_dp_phy_cfg, },
+ { .compatible = "qcom,sc8280xp-edp-phy", .data = &sc8280xp_edp_phy_cfg, },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_edp_phy_match_table);
diff --git a/include/linux/phy/phy-dp.h b/include/linux/phy/phy-dp.h
index 18cad23642cd..9cce5766bc0b 100644
--- a/include/linux/phy/phy-dp.h
+++ b/include/linux/phy/phy-dp.h
@@ -8,6 +8,9 @@
#include <linux/types.h>
+#define PHY_SUBMODE_DP 0
+#define PHY_SUBMODE_EDP 1
+
/**
* struct phy_configure_opts_dp - DisplayPort PHY configuration set
*