diff options
| -rw-r--r-- | Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml | 18 | ||||
| -rw-r--r-- | drivers/interconnect/qcom/sm8250.c | 74 | ||||
| -rw-r--r-- | drivers/interconnect/qcom/sm8250.h | 6 | ||||
| -rw-r--r-- | include/dt-bindings/interconnect/qcom,sm8250.h | 7 |
4 files changed, 98 insertions, 7 deletions
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml index 4d93ad415e0b..a46497af1fd8 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml @@ -18,9 +18,6 @@ description: | least one RPMh device child node pertaining to their RSC and each provider can map to multiple RPMh resources. -allOf: - - $ref: qcom,rpmh-common.yaml# - properties: reg: maxItems: 1 @@ -91,6 +88,7 @@ properties: - qcom,sm8250-mc-virt - qcom,sm8250-mmss-noc - qcom,sm8250-npu-noc + - qcom,sm8250-qup-virt - qcom,sm8250-system-noc - qcom,sm8350-aggre1-noc - qcom,sm8350-aggre2-noc @@ -107,7 +105,19 @@ properties: required: - compatible - - reg + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + not: + properties: + compatible: + enum: + - qcom,sm8250-qup-virt + then: + required: + - reg + unevaluatedProperties: false diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c index 069fb463d008..b8d265f2c176 100644 --- a/drivers/interconnect/qcom/sm8250.c +++ b/drivers/interconnect/qcom/sm8250.c @@ -165,6 +165,54 @@ DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8); DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4); DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8); +static struct qcom_icc_node qup0_core_master = { + .name = "qup0_core_master", + .id = SM8250_MASTER_QUP_CORE_0, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_QUP_CORE_0 }, +}; + +static struct qcom_icc_node qup1_core_master = { + .name = "qup1_core_master", + .id = SM8250_MASTER_QUP_CORE_1, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_QUP_CORE_1 }, +}; + +static struct qcom_icc_node qup2_core_master = { + .name = "qup2_core_master", + .id = SM8250_MASTER_QUP_CORE_2, + .channels = 1, + .buswidth = 4, + .num_links = 1, + .links = { SM8250_SLAVE_QUP_CORE_2 }, +}; + +static struct qcom_icc_node qup0_core_slave = { + .name = "qup0_core_slave", + .id = SM8250_SLAVE_QUP_CORE_0, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup1_core_slave = { + .name = "qup1_core_slave", + .id = SM8250_SLAVE_QUP_CORE_1, + .channels = 1, + .buswidth = 4, +}; + +static struct qcom_icc_node qup2_core_slave = { + .name = "qup2_core_slave", + .id = SM8250_SLAVE_QUP_CORE_2, + .channels = 1, + .buswidth = 4, +}; + DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); @@ -173,7 +221,7 @@ DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1); DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu); DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); -DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2, &qhm_qup0); +DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master, &qup2_core_master); DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp); DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps); @@ -194,7 +242,6 @@ DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc); DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc); static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { - &bcm_qup0, &bcm_sn12, }; @@ -223,10 +270,29 @@ static const struct qcom_icc_desc sm8250_aggre1_noc = { static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { &bcm_ce0, - &bcm_qup0, &bcm_sn12, }; +static struct qcom_icc_bcm * const qup_virt_bcms[] = { + &bcm_qup0, +}; + +static struct qcom_icc_node *qup_virt_nodes[] = { + [MASTER_QUP_CORE_0] = &qup0_core_master, + [MASTER_QUP_CORE_1] = &qup1_core_master, + [MASTER_QUP_CORE_2] = &qup2_core_master, + [SLAVE_QUP_CORE_0] = &qup0_core_slave, + [SLAVE_QUP_CORE_1] = &qup1_core_slave, + [SLAVE_QUP_CORE_2] = &qup2_core_slave, +}; + +static const struct qcom_icc_desc sm8250_qup_virt = { + .nodes = qup_virt_nodes, + .num_nodes = ARRAY_SIZE(qup_virt_nodes), + .bcms = qup_virt_bcms, + .num_bcms = ARRAY_SIZE(qup_virt_bcms), +}; + static struct qcom_icc_node * const aggre2_noc_nodes[] = { [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, [MASTER_QDSS_BAM] = &qhm_qdss_bam, @@ -519,6 +585,8 @@ static const struct of_device_id qnoc_of_match[] = { .data = &sm8250_mmss_noc}, { .compatible = "qcom,sm8250-npu-noc", .data = &sm8250_npu_noc}, + { .compatible = "qcom,sm8250-qup-virt", + .data = &sm8250_qup_virt }, { .compatible = "qcom,sm8250-system-noc", .data = &sm8250_system_noc}, { } diff --git a/drivers/interconnect/qcom/sm8250.h b/drivers/interconnect/qcom/sm8250.h index 209ab195f21f..032665093c5b 100644 --- a/drivers/interconnect/qcom/sm8250.h +++ b/drivers/interconnect/qcom/sm8250.h @@ -158,5 +158,11 @@ #define SM8250_SLAVE_VSENSE_CTRL_CFG 147 #define SM8250_SNOC_CNOC_MAS 148 #define SM8250_SNOC_CNOC_SLV 149 +#define SM8250_MASTER_QUP_CORE_0 150 +#define SM8250_MASTER_QUP_CORE_1 151 +#define SM8250_MASTER_QUP_CORE_2 152 +#define SM8250_SLAVE_QUP_CORE_0 153 +#define SM8250_SLAVE_QUP_CORE_1 154 +#define SM8250_SLAVE_QUP_CORE_2 155 #endif diff --git a/include/dt-bindings/interconnect/qcom,sm8250.h b/include/dt-bindings/interconnect/qcom,sm8250.h index a4af5cc19271..2a656c02df4b 100644 --- a/include/dt-bindings/interconnect/qcom,sm8250.h +++ b/include/dt-bindings/interconnect/qcom,sm8250.h @@ -166,4 +166,11 @@ #define SLAVE_QDSS_STM 17 #define SLAVE_TCU 18 +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define MASTER_QUP_CORE_2 2 +#define SLAVE_QUP_CORE_0 3 +#define SLAVE_QUP_CORE_1 4 +#define SLAVE_QUP_CORE_2 5 + #endif |