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-rw-r--r--Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
index 75143db51411..b74ad9a3305c 100644
--- a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
@@ -12,7 +12,7 @@ maintainers:
description:
The Zynq DDR ECC controller has an optional ECC support in half-bus width
- (16-bit) configuration. It is cappable of correcting single bit ECC errors
+ (16-bit) configuration. It is capable of correcting single bit ECC errors
and detecting double bit ECC errors.
properties: