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Diffstat (limited to 'Documentation/devicetree/bindings/pci/layerscape-pci.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/layerscape-pci.txt | 79 |
1 files changed, 0 insertions, 79 deletions
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt deleted file mode 100644 index ee8a4791a78b..000000000000 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ /dev/null @@ -1,79 +0,0 @@ -Freescale Layerscape PCIe controller - -This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in snps,dw-pcie.yaml. - -This controller derives its clocks from the Reset Configuration Word (RCW) -which is used to describe the PLL settings at the time of chip-reset. - -Also as per the available Reference Manuals, there is no specific 'version' -register available in the Freescale PCIe controller register set, -which can allow determining the underlying DesignWare PCIe controller version -information. - -Required properties: -- compatible: should contain the platform identifier such as: - RC mode: - "fsl,ls1021a-pcie" - "fsl,ls2080a-pcie", "fsl,ls2085a-pcie" - "fsl,ls2088a-pcie" - "fsl,ls1088a-pcie" - "fsl,ls1046a-pcie" - "fsl,ls1043a-pcie" - "fsl,ls1012a-pcie" - "fsl,ls1028a-pcie" - EP mode: - "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep" -- reg: base addresses and lengths of the PCIe controller register blocks. -- interrupts: A list of interrupt outputs of the controller. Must contain an - entry for each entry in the interrupt-names property. -- interrupt-names: It could include the following entries: - "aer": Used for interrupt line which reports AER events when - non MSI/MSI-X/INTx mode is used - "pme": Used for interrupt line which reports PME events when - non MSI/MSI-X/INTx mode is used - "intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) - which has a single interrupt line for miscellaneous controller - events(could include AER and PME events). -- fsl,pcie-scfg: Must include two entries. - The first entry must be a link to the SCFG device node - The second entry is the physical PCIe controller index starting from '0'. - This is used to get SCFG PEXN registers -- dma-coherent: Indicates that the hardware IP block can ensure the coherency - of the data transferred from/to the IP block. This can avoid the software - cache flush/invalid actions, and improve the performance significantly. - -Optional properties: -- big-endian: If the PEX_LUT and PF register block is in big-endian, specify - this property. - -Example: - - pcie@3400000 { - compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ - <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ - interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <256>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - }; |