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Diffstat (limited to 'Documentation/devicetree')
143 files changed, 7387 insertions, 2384 deletions
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml new file mode 100644 index 000000000000..cf1002c3efa6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-clock.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Functional Clock Controller for MT8186 + +maintainers: + - Chun-Jie Chen <chun-jie.chen@mediatek.com> + +description: | + The clock architecture in MediaTek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The devices provide clock gate control in different IP blocks. + +properties: + compatible: + items: + - enum: + - mediatek,mt8186-imp_iic_wrap + - mediatek,mt8186-mfgsys + - mediatek,mt8186-wpesys + - mediatek,mt8186-imgsys1 + - mediatek,mt8186-imgsys2 + - mediatek,mt8186-vdecsys + - mediatek,mt8186-vencsys + - mediatek,mt8186-camsys + - mediatek,mt8186-camsys_rawa + - mediatek,mt8186-camsys_rawb + - mediatek,mt8186-mdpsys + - mediatek,mt8186-ipesys + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + imp_iic_wrap: clock-controller@11017000 { + compatible = "mediatek,mt8186-imp_iic_wrap"; + reg = <0x11017000 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml new file mode 100644 index 000000000000..0886e2e335bb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek System Clock Controller for MT8186 + +maintainers: + - Chun-Jie Chen <chun-jie.chen@mediatek.com> + +description: | + The clock architecture in MediaTek like below + PLLs --> + dividers --> + muxes + --> + clock gate + + The apmixedsys provides most of PLLs which generated from SoC 26m. + The topckgen provides dividers and muxes which provide the clock source to other IP blocks. + The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks. + The mcusys provides mux control to select the clock source in AP MCU. + The device nodes also provide the system control capacity for configuration. + +properties: + compatible: + items: + - enum: + - mediatek,mt8186-mcusys + - mediatek,mt8186-topckgen + - mediatek,mt8186-infracfg_ao + - mediatek,mt8186-apmixedsys + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + topckgen: syscon@10000000 { + compatible = "mediatek,mt8186-topckgen", "syscon"; + reg = <0x10000000 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml new file mode 100644 index 000000000000..8c6543b5c0dc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra CPU COMPLEX CLUSTER area device tree bindings + +maintainers: + - Sumit Gupta <sumitg@nvidia.com> + - Mikko Perttunen <mperttunen@nvidia.com> + - Jon Hunter <jonathanh@nvidia.com> + - Thierry Reding <thierry.reding@gmail.com> + +description: |+ + The Tegra CPU COMPLEX CLUSTER area contains memory-mapped + registers that initiate CPU frequency/voltage transitions. + +properties: + $nodename: + pattern: "ccplex@([0-9a-f]+)$" + + compatible: + enum: + - nvidia,tegra186-ccplex-cluster + - nvidia,tegra234-ccplex-cluster + + reg: + maxItems: 1 + + nvidia,bpmp: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Specifies the BPMP node that needs to be queried to get + operating point data for all CPUs. + +additionalProperties: false + +required: + - compatible + - reg + - nvidia,bpmp + - status + +examples: + - | + ccplex@e000000 { + compatible = "nvidia,tegra234-ccplex-cluster"; + reg = <0x0e000000 0x5ffff>; + nvidia,bpmp = <&bpmp>; + status = "okay"; + }; diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml new file mode 100644 index 000000000000..d60e74654809 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/airoha,en7523-scu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EN7523 Clock Device Tree Bindings + +maintainers: + - Felix Fietkau <nbd@nbd.name> + - John Crispin <nbd@nbd.name> + +description: | + This node defines the System Control Unit of the EN7523 SoC, + a collection of registers configuring many different aspects of the SoC. + + The clock driver uses it to read and configure settings of the + PLL controller, which provides clocks for the CPU, the bus and + other SoC internal peripherals. + + Each clock is assigned an identifier and client nodes use this identifier + to specify which clock they consume. + + All these identifiers can be found in: + [1]: <include/dt-bindings/clock/en7523-clk.h>. + + The clocks are provided inside a system controller node. + +properties: + compatible: + items: + - const: airoha,en7523-scu + + reg: + maxItems: 2 + + "#clock-cells": + description: + The first cell indicates the clock number, see [1] for available + clocks. + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/en7523-clk.h> + scu: system-controller@1fa20000 { + compatible = "airoha,en7523-scu"; + reg = <0x1fa20000 0x400>, + <0x1fb00000 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt index f2ea53832ac6..6fe541368889 100644 --- a/Documentation/devicetree/bindings/clock/clock-bindings.txt +++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt @@ -1,186 +1,2 @@ -This binding is a work-in-progress, and are based on some experimental -work by benh[1]. - -Sources of clock signal can be represented by any node in the device -tree. Those nodes are designated as clock providers. Clock consumer -nodes use a phandle and clock specifier pair to connect clock provider -outputs to clock inputs. Similar to the gpio specifiers, a clock -specifier is an array of zero, one or more cells identifying the clock -output on a device. The length of a clock specifier is defined by the -value of a #clock-cells property in the clock provider node. - -[1] https://patchwork.ozlabs.org/patch/31551/ - -==Clock providers== - -Required properties: -#clock-cells: Number of cells in a clock specifier; Typically 0 for nodes - with a single clock output and 1 for nodes with multiple - clock outputs. - -Optional properties: -clock-output-names: Recommended to be a list of strings of clock output signal - names indexed by the first cell in the clock specifier. - However, the meaning of clock-output-names is domain - specific to the clock provider, and is only provided to - encourage using the same meaning for the majority of clock - providers. This format may not work for clock providers - using a complex clock specifier format. In those cases it - is recommended to omit this property and create a binding - specific names property. - - Clock consumer nodes must never directly reference - the provider's clock-output-names property. - -For example: - - oscillator { - #clock-cells = <1>; - clock-output-names = "ckil", "ckih"; - }; - -- this node defines a device with two clock outputs, the first named - "ckil" and the second named "ckih". Consumer nodes always reference - clocks by index. The names should reflect the clock output signal - names for the device. - -clock-indices: If the identifying number for the clocks in the node - is not linear from zero, then this allows the mapping of - identifiers into the clock-output-names array. - -For example, if we have two clocks <&oscillator 1> and <&oscillator 3>: - - oscillator { - compatible = "myclocktype"; - #clock-cells = <1>; - clock-indices = <1>, <3>; - clock-output-names = "clka", "clkb"; - } - - This ensures we do not have any empty strings in clock-output-names - - -==Clock consumers== - -Required properties: -clocks: List of phandle and clock specifier pairs, one pair - for each clock input to the device. Note: if the - clock provider specifies '0' for #clock-cells, then - only the phandle portion of the pair will appear. - -Optional properties: -clock-names: List of clock input name strings sorted in the same - order as the clocks property. Consumers drivers - will use clock-names to match clock input names - with clocks specifiers. -clock-ranges: Empty property indicating that child nodes can inherit named - clocks from this node. Useful for bus nodes to provide a - clock to their children. - -For example: - - device { - clocks = <&osc 1>, <&ref 0>; - clock-names = "baud", "register"; - }; - - -This represents a device with two clock inputs, named "baud" and "register". -The baud clock is connected to output 1 of the &osc device, and the register -clock is connected to output 0 of the &ref. - -==Example== - - /* external oscillator */ - osc: oscillator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32678>; - clock-output-names = "osc"; - }; - - /* phase-locked-loop device, generates a higher frequency clock - * from the external oscillator reference */ - pll: pll@4c000 { - compatible = "vendor,some-pll-interface" - #clock-cells = <1>; - clocks = <&osc 0>; - clock-names = "ref"; - reg = <0x4c000 0x1000>; - clock-output-names = "pll", "pll-switched"; - }; - - /* UART, using the low frequency oscillator for the baud clock, - * and the high frequency switched PLL output for register - * clocking */ - uart@a000 { - compatible = "fsl,imx-uart"; - reg = <0xa000 0x1000>; - interrupts = <33>; - clocks = <&osc 0>, <&pll 1>; - clock-names = "baud", "register"; - }; - -This DT fragment defines three devices: an external oscillator to provide a -low-frequency reference clock, a PLL device to generate a higher frequency -clock signal, and a UART. - -* The oscillator is fixed-frequency, and provides one clock output, named "osc". -* The PLL is both a clock provider and a clock consumer. It uses the clock - signal generated by the external oscillator, and provides two output signals - ("pll" and "pll-switched"). -* The UART has its baud clock connected the external oscillator and its - register clock connected to the PLL clock (the "pll-switched" signal) - -==Assigned clock parents and rates== - -Some platforms may require initial configuration of default parent clocks -and clock frequencies. Such a configuration can be specified in a device tree -node through assigned-clocks, assigned-clock-parents and assigned-clock-rates -properties. The assigned-clock-parents property should contain a list of parent -clocks in the form of a phandle and clock specifier pair and the -assigned-clock-rates property should contain a list of frequencies in Hz. Both -these properties should correspond to the clocks listed in the assigned-clocks -property. - -To skip setting parent or rate of a clock its corresponding entry should be -set to 0, or can be omitted if it is not followed by any non-zero entry. - - uart@a000 { - compatible = "fsl,imx-uart"; - reg = <0xa000 0x1000>; - ... - clocks = <&osc 0>, <&pll 1>; - clock-names = "baud", "register"; - - assigned-clocks = <&clkcon 0>, <&pll 2>; - assigned-clock-parents = <&pll 2>; - assigned-clock-rates = <0>, <460800>; - }; - -In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and -the <&pll 2> clock is assigned a frequency value of 460800 Hz. - -Configuring a clock's parent and rate through the device node that consumes -the clock can be done only for clocks that have a single user. Specifying -conflicting parent or rate configuration in multiple consumer nodes for -a shared clock is forbidden. - -Configuration of common clocks, which affect multiple consumer devices can -be similarly specified in the clock provider node. - -==Protected clocks== - -Some platforms or firmwares may not fully expose all the clocks to the OS, such -as in situations where those clks are used by drivers running in ARM secure -execution levels. Such a configuration can be specified in device tree with the -protected-clocks property in the form of a clock specifier list. This property should -only be specified in the node that is providing the clocks being protected: - - clock-controller@a000f000 { - compatible = "vendor,clk95; - reg = <0xa000f000 0x1000> - #clocks-cells = <1>; - ... - protected-clocks = <UART3_CLK>, <SPI5_CLK>; - }; +This file has moved to the clock binding schema: +https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml index 97936411b6b4..9fafcb080069 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml @@ -20,12 +20,10 @@ description: | See also: - dt-bindings/clock/qcom,gcc-msm8960.h - dt-bindings/reset/qcom,gcc-msm8960.h - - dt-bindings/clock/qcom,gcc-apq8084.h - - dt-bindings/reset/qcom,gcc-apq8084.h properties: compatible: - const: qcom,gcc-apq8084 + const: qcom,gcc-apq8064 nvmem-cells: minItems: 1 diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml new file mode 100644 index 000000000000..397fb918e032 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for APQ8084 + +maintainers: + - Stephen Boyd <sboyd@kernel.org> + - Taniya Das <quic_tdas@quicinc.com> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on APQ8084. + + See also:: + - dt-bindings/clock/qcom,gcc-apq8084.h + - dt-bindings/reset/qcom,gcc-apq8084.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,gcc-apq8084 + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + clock-controller@fc400000 { + compatible = "qcom,gcc-apq8084"; + reg = <0xfc400000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml new file mode 100644 index 000000000000..0bcdc69c6f89 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SC8280xp + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SC8280xp. + + See also: + - include/dt-bindings/clock/qcom,gcc-sc8280xp.h + +properties: + compatible: + const: qcom,gcc-sc8280xp + + clocks: + items: + - description: XO reference clock + - description: Sleep clock + - description: UFS memory first RX symbol clock + - description: UFS memory second RX symbol clock + - description: UFS memory first TX symbol clock + - description: UFS card first RX symbol clock + - description: UFS card second RX symbol clock + - description: UFS card first TX symbol clock + - description: Primary USB SuperSpeed pipe clock + - description: USB4 PHY pipegmux clock source + - description: USB4 PHY DP gmux clock source + - description: USB4 PHY sys piegmux clock source + - description: USB4 PHY PCIe pipe clock + - description: USB4 PHY router max pipe clock + - description: Primary USB4 RX0 clock + - description: Primary USB4 RX1 clock + - description: Secondary USB SuperSpeed pipe clock + - description: Second USB4 PHY pipegmux clock source + - description: Second USB4 PHY DP gmux clock source + - description: Second USB4 PHY sys pipegmux clock source + - description: Second USB4 PHY PCIe pipe clock + - description: Second USB4 PHY router max pipe clock + - description: Secondary USB4 RX0 clock + - description: Secondary USB4 RX1 clock + - description: Multiport USB first SupserSpeed pipe clock + - description: Multiport USB second SuperSpeed pipe clock + - description: PCIe 2a pipe clock + - description: PCIe 2b pipe clock + - description: PCIe 3a pipe clock + - description: PCIe 3b pipe clock + - description: PCIe 4 pipe clock + - description: First EMAC controller reference clock + - description: Second EMAC controller reference clock + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + protected-clocks: + maxItems: 389 + +required: + - compatible + - clocks + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sc8280xp"; + reg = <0x00100000 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&ufs_phy_rx_symbol_0_clk>, + <&ufs_phy_rx_symbol_1_clk>, + <&ufs_phy_tx_symbol_0_clk>, + <&ufs_card_rx_symbol_0_clk>, + <&ufs_card_rx_symbol_1_clk>, + <&ufs_card_tx_symbol_0_clk>, + <&usb_0_ssphy>, + <&gcc_usb4_phy_pipegmux_clk_src>, + <&gcc_usb4_phy_dp_gmux_clk_src>, + <&gcc_usb4_phy_sys_pipegmux_clk_src>, + <&usb4_phy_gcc_usb4_pcie_pipe_clk>, + <&usb4_phy_gcc_usb4rtr_max_pipe_clk>, + <&qusb4phy_gcc_usb4_rx0_clk>, + <&qusb4phy_gcc_usb4_rx1_clk>, + <&usb_1_ssphy>, + <&gcc_usb4_1_phy_pipegmux_clk_src>, + <&gcc_usb4_1_phy_dp_gmux_clk_src>, + <&gcc_usb4_1_phy_sys_pipegmux_clk_src>, + <&usb4_1_phy_gcc_usb4_pcie_pipe_clk>, + <&usb4_1_phy_gcc_usb4rtr_max_pipe_clk>, + <&qusb4phy_1_gcc_usb4_rx0_clk>, + <&qusb4phy_1_gcc_usb4_rx1_clk>, + <&usb_2_ssphy>, + <&usb_3_ssphy>, + <&pcie2a_lane>, + <&pcie2b_lane>, + <&pcie3a_lane>, + <&pcie3b_lane>, + <&pcie4_lane>, + <&rxc0_ref_clk>, + <&rxc1_ref_clk>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt deleted file mode 100644 index da295c3c004b..000000000000 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt +++ /dev/null @@ -1,63 +0,0 @@ -Qualcomm RPM Clock Controller Binding ------------------------------------------------- -The RPM is a dedicated hardware engine for managing the shared -SoC resources in order to keep the lowest power profile. It -communicates with other hardware subsystems via shared memory -and accepts clock requests, aggregates the requests and turns -the clocks on/off or scales them on demand. - -Required properties : -- compatible : shall contain only one of the following. The generic - compatible "qcom,rpmcc" should be also included. - - "qcom,rpmcc-mdm9607", "qcom,rpmcc" - "qcom,rpmcc-msm8660", "qcom,rpmcc" - "qcom,rpmcc-apq8060", "qcom,rpmcc" - "qcom,rpmcc-msm8226", "qcom,rpmcc" - "qcom,rpmcc-msm8916", "qcom,rpmcc" - "qcom,rpmcc-msm8936", "qcom,rpmcc" - "qcom,rpmcc-msm8953", "qcom,rpmcc" - "qcom,rpmcc-msm8974", "qcom,rpmcc" - "qcom,rpmcc-msm8976", "qcom,rpmcc" - "qcom,rpmcc-apq8064", "qcom,rpmcc" - "qcom,rpmcc-ipq806x", "qcom,rpmcc" - "qcom,rpmcc-msm8992",·"qcom,rpmcc" - "qcom,rpmcc-msm8994",·"qcom,rpmcc" - "qcom,rpmcc-msm8996", "qcom,rpmcc" - "qcom,rpmcc-msm8998", "qcom,rpmcc" - "qcom,rpmcc-qcm2290", "qcom,rpmcc" - "qcom,rpmcc-qcs404", "qcom,rpmcc" - "qcom,rpmcc-sdm660", "qcom,rpmcc" - "qcom,rpmcc-sm6115", "qcom,rpmcc" - "qcom,rpmcc-sm6125", "qcom,rpmcc" - -- #clock-cells : shall contain 1 - -The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h> -and come in pairs: FOO_CLK followed by FOO_A_CLK. The latter clock -is an "active" clock, which means that the consumer only care that the -clock is available when the apps CPU subsystem is active, i.e. not -suspended or in deep idle. If it is important that the clock keeps running -during system suspend, you need to specify the non-active clock, the one -not containing *_A_* in the enumerator name. - -Example: - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = <0 168 1>; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests { - compatible = "qcom,rpm-msm8916"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; - #clock-cells = <1>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml new file mode 100644 index 000000000000..9d296b89a8d0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,rpmcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPM Clock Controller + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + +description: | + The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h> and + come in pairs:: FOO_CLK followed by FOO_A_CLK. The latter clock is + an "active" clock, which means that the consumer only care that the clock is + available when the apps CPU subsystem is active, i.e. not suspended or in + deep idle. If it is important that the clock keeps running during system + suspend, you need to specify the non-active clock, the one not containing + *_A_* in the enumerator name. + +properties: + compatible: + items: + - enum: + - qcom,rpmcc-apq8060 + - qcom,rpmcc-apq8064 + - qcom,rpmcc-ipq806x + - qcom,rpmcc-mdm9607 + - qcom,rpmcc-msm8226 + - qcom,rpmcc-msm8660 + - qcom,rpmcc-msm8916 + - qcom,rpmcc-msm8936 + - qcom,rpmcc-msm8953 + - qcom,rpmcc-msm8974 + - qcom,rpmcc-msm8976 + - qcom,rpmcc-msm8992 + - qcom,rpmcc-msm8994 + - qcom,rpmcc-msm8996 + - qcom,rpmcc-msm8998 + - qcom,rpmcc-qcm2290 + - qcom,rpmcc-qcs404 + - qcom,rpmcc-sdm660 + - qcom,rpmcc-sm6115 + - qcom,rpmcc-sm6125 + - const: qcom,rpmcc + + '#clock-cells': + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xo + +required: + - compatible + - '#clock-cells' + +additionalProperties: false + +examples: + - | + rpm { + rpm-requests { + compatible = "qcom,rpm-msm8916"; + qcom,smd-channels = "rpm_requests"; + + clock-controller { + compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; + #clock-cells = <1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml index e0b86214f0f5..e57bc40d307a 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml @@ -49,6 +49,7 @@ properties: - renesas,r8a77995-cpg-mssr # R-Car D3 - renesas,r8a779a0-cpg-mssr # R-Car V3U - renesas,r8a779f0-cpg-mssr # R-Car S4-8 + - renesas,r8a779g0-cpg-mssr # R-Car V4H reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml index 25dbb0fac065..95bf485c6cec 100644 --- a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml @@ -39,6 +39,17 @@ properties: '#power-domain-cells': const: 0 + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +patternProperties: + "^dma-router@[a-f0-9]+$": + type: object + $ref: "../dma/renesas,rzn1-dmamux.yaml#" + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml index bd3af8fc616b..8880b834f264 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml @@ -4,14 +4,15 @@ $id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode +title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode maintainers: - Geert Uytterhoeven <geert+renesas@glider.be> description: | - On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module - Standby Mode share the same register block. + On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module + Standby Mode share the same register block. On RZ/V2M, the functionality is + similar, but does not have Clock Monitor Registers. They provide the following functionalities: - The CPG block generates various core clocks, @@ -23,8 +24,10 @@ description: | properties: compatible: enum: - - renesas,r9a07g044-cpg # RZ/G2{L,LC} - - renesas,r9a07g054-cpg # RZ/V2L + - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} + - renesas,r9a07g044-cpg # RZ/G2{L,LC} + - renesas,r9a07g054-cpg # RZ/V2L + - renesas,r9a09g011-cpg # RZ/V2M reg: maxItems: 1 @@ -42,9 +45,10 @@ properties: description: | - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" and a core clock reference, as defined in - <dt-bindings/clock/r9a07g*-cpg.h> + <dt-bindings/clock/r9a0*-cpg.h> - For module clocks, the two clock specifier cells must be "CPG_MOD" and - a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>. + a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or + <dt-bindings/clock/r9a09g011-cpg.h>. const: 2 '#power-domain-cells': @@ -58,7 +62,7 @@ properties: '#reset-cells': description: The single reset specifier cell must be the module number, as defined in - the <dt-bindings/clock/r9a07g0*-cpg.h>. + the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>. const: 1 required: diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt deleted file mode 100644 index 55e78cddec8c..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt +++ /dev/null @@ -1,70 +0,0 @@ -* Rockchip PX30 Clock and Reset Unit - -The PX30 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: PMU for CRU should be "rockchip,px30-pmu-cru" -- compatible: CRU should be "rockchip,px30-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- clocks: A list of phandle + clock-specifier pairs for the clocks listed - in clock-names -- clock-names: Should contain the following: - - "xin24m" for both PMUCRU and CRU - - "gpll" for CRU (sourced from PMUCRU) -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing, pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "i2sx_clkin" - external I2S clock - optional, - - "gmac_clkin" - external GMAC clock - optional - -Example: Clock controller node: - - pmucru: clock-controller@ff2bc000 { - compatible = "rockchip,px30-pmucru"; - reg = <0x0 0xff2bc000 0x0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - cru: clock-controller@ff2b0000 { - compatible = "rockchip,px30-cru"; - reg = <0x0 0xff2b0000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@ff030000 { - compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff030000 0x0 0x100>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml new file mode 100644 index 000000000000..3eec381c7cf5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,px30-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip PX30 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The PX30 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required + - "xin32k" - rtc clock - optional + - "i2sx_clkin" - external I2S clock - optional + - "gmac_clkin" - external GMAC clock - optional + +properties: + compatible: + enum: + - rockchip,px30-cru + - rockchip,px30-pmucru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + minItems: 1 + items: + - description: Clock for both PMUCRU and CRU + - description: Clock for CRU (sourced from PMUCRU) + + clock-names: + minItems: 1 + items: + - const: xin24m + - const: gpll + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,px30-cru + + then: + properties: + clocks: + minItems: 2 + + clock-names: + minItems: 2 + + else: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/px30-cru.h> + + pmucru: clock-controller@ff2bc000 { + compatible = "rockchip,px30-pmucru"; + reg = <0xff2bc000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@ff2b0000 { + compatible = "rockchip,px30-cru"; + reg = <0xff2b0000 0x1000>; + clocks = <&xin24m>, <&pmucru PLL_GPLL>; + clock-names = "xin24m", "gpll"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt deleted file mode 100644 index 20df350b9ef3..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt +++ /dev/null @@ -1,56 +0,0 @@ -* Rockchip RK3036 Clock and Reset Unit - -The RK3036 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3036-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "ext_i2s" - external I2S clock - optional, - - "rmii_clkin" - external EMAC clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3036-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@20060000 { - compatible = "snps,dw-apb-uart"; - reg = <0x20060000 0x100>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml new file mode 100644 index 000000000000..1376230fede6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3036-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3036 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3036 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required + - "ext_i2s" - external I2S clock - optional + - "rmii_clkin" - external EMAC clock - optional + +properties: + compatible: + enum: + - rockchip,rk3036-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@20000000 { + compatible = "rockchip,rk3036-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt deleted file mode 100644 index 7f368530a2e4..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip RK3188/RK3066 Clock and Reset Unit - -The RK3188/RK3066 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or - "rockchip,rk3066a-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3188-cru.h and -dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. -Similar macros exist for the reset sources in these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "xin27m" - 27mhz crystal input on rk3066 - optional, - - "ext_hsadc" - external HSADC clock - optional, - - "ext_cif0" - external camera clock - optional, - - "ext_rmii" - external RMII clock - optional, - - "ext_jtag" - externalJTAG clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml new file mode 100644 index 000000000000..ddd7e46af0f2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3188-cru.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3188-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3188/RK3066 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3188/RK3066 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3188-cru.h and + dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources. + Similar macros exist for the reset sources in these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required + - "xin32k" - RTC clock - optional + - "xin27m" - 27mhz crystal input on RK3066 - optional + - "ext_hsadc" - external HSADC clock - optional + - "ext_cif0" - external camera clock - optional + - "ext_rmii" - external RMII clock - optional + - "ext_jtag" - external JTAG clock - optional + +properties: + compatible: + enum: + - rockchip,rk3066a-cru + - rockchip,rk3188-cru + - rockchip,rk3188a-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@20000000 { + compatible = "rockchip,rk3188-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt deleted file mode 100644 index f323048127eb..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Rockchip RK3228 Clock and Reset Unit - -The RK3228 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3228-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "ext_i2s" - external I2S clock - optional, - - "ext_gmac" - external GMAC clock - optional - - "ext_hsadc" - external HSADC clock - optional - - "phy_50m_out" - output clock of the pll in the mac phy - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3228-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10110000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10110000 0x100>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml new file mode 100644 index 000000000000..cf7dc01d9478 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3228-cru.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3228 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3228 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required + - "ext_i2s" - external I2S clock - optional + - "ext_gmac" - external GMAC clock - optional + - "ext_hsadc" - external HSADC clock - optional + - "phy_50m_out" - output clock of the pll in the mac phy + +properties: + compatible: + enum: + - rockchip,rk3228-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@20000000 { + compatible = "rockchip,rk3228-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt deleted file mode 100644 index bf3a9ec19241..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Rockchip RK3288 Clock and Reset Unit - -The RK3288 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -A revision of this SoC is available: rk3288w. The clock tree is a bit -different so another dt-compatible is available. Noticed that it is only -setting the difference but there is no automatic revision detection. This -should be performed by bootloaders. - -Required Properties: - -- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in - case of this revision of Rockchip rk3288. -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_hsadc" - external HSADC clock - optional, - - "ext_edp_24m" - external display port clock - optional, - - "ext_vip" - external VIP clock - optional, - - "ext_isp" - external ISP clock - optional, - - "ext_jtag" - external JTAG clock - optional - -Example: Clock controller node: - - cru: cru@20000000 { - compatible = "rockchip,rk3188-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml new file mode 100644 index 000000000000..96bc05749e1a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3288-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3288 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3288 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + + A revision of this SoC is available: rk3288w. The clock tree is a bit + different so another dt-compatible is available. Noticed that it is only + setting the difference but there is no automatic revision detection. This + should be performed by boot loaders. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required, + - "xin32k" - rtc clock - optional, + - "ext_i2s" - external I2S clock - optional, + - "ext_hsadc" - external HSADC clock - optional, + - "ext_edp_24m" - external display port clock - optional, + - "ext_vip" - external VIP clock - optional, + - "ext_isp" - external ISP clock - optional, + - "ext_jtag" - external JTAG clock - optional + +properties: + compatible: + enum: + - rockchip,rk3288-cru + - rockchip,rk3288w-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3288-cru"; + reg = <0xff760000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt deleted file mode 100644 index 9b151c5b0c90..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Rockchip RK3308 Clock and Reset Unit - -The RK3308 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: CRU should be "rockchip,rk3308-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing, pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", "mclk_i2s2_8ch_in", - "mclk_i2s3_8ch_in", "mclk_i2s0_2ch_in", - "mclk_i2s1_2ch_in" - external I2S or SPDIF clock - optional, - - "mac_clkin" - external MAC clock - optional - -Example: Clock controller node: - - cru: clock-controller@ff500000 { - compatible = "rockchip,rk3308-cru"; - reg = <0x0 0xff500000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@ff0a0000 { - compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; - reg = <0x0 0xff0a0000 0x0 0x100>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml new file mode 100644 index 000000000000..523ee578a586 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3308-cru.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3308-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3308 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3308 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required + - "xin32k" - rtc clock - optional + - "mclk_i2s0_8ch_in", "mclk_i2s1_8ch_in", + "mclk_i2s2_8ch_in", "mclk_i2s3_8ch_in", + "mclk_i2s0_2ch_in", "mclk_i2s1_2ch_in" - external I2S or + SPDIF clock - optional + - "mac_clkin" - external MAC clock - optional + +properties: + compatible: + enum: + - rockchip,rk3308-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff500000 { + compatible = "rockchip,rk3308-cru"; + reg = <0xff500000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt deleted file mode 100644 index 7c8bbcfed8d2..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Rockchip RK3368 Clock and Reset Unit - -The RK3368 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rk3368-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing, pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_gmac" - external GMAC clock - optional - - "ext_hsadc" - external HSADC clock - optional, - - "ext_isp" - external ISP clock - optional, - - "ext_jtag" - external JTAG clock - optional - - "ext_vip" - external VIP clock - optional, - - "usbotg_out" - output clock of the pll in the otg phy - -Example: Clock controller node: - - cru: clock-controller@ff760000 { - compatible = "rockchip,rk3368-cru"; - reg = <0x0 0xff760000 0x0 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10124000 { - compatible = "snps,dw-apb-uart"; - reg = <0x10124000 0x400>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <1>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml new file mode 100644 index 000000000000..adb67877720d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3368-cru.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3368-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3368 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RK3368 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required + - "xin32k" - rtc clock - optional + - "ext_i2s" - external I2S clock - optional + - "ext_gmac" - external GMAC clock - optional + - "ext_hsadc" - external HSADC clock - optional + - "ext_isp" - external ISP clock - optional + - "ext_jtag" - external JTAG clock - optional + - "ext_vip" - external VIP clock - optional + - "usbotg_out" - output clock of the pll in the otg phy + +properties: + compatible: + enum: + - rockchip,rk3368-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3368-cru"; + reg = <0xff760000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml index 72b286a1beba..54da1e31ea73 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Rockchip RK3399 Clock and Reset Unit maintainers: - - Xing Zheng <zhengxing@rock-chips.com> + - Elaine Zhang <zhangqing@rock-chips.com> - Heiko Stuebner <heiko@sntech.de> description: | @@ -22,11 +22,11 @@ description: | There are several clocks that are generated outside the SoC. It is expected that they are defined using standard clock bindings with following clock-output-names: - - "xin24m" - crystal input - required, - - "xin32k" - rtc clock - optional, - - "clkin_gmac" - external GMAC clock - optional, - - "clkin_i2s" - external I2S clock - optional, - - "pclkin_cif" - external ISP clock - optional, + - "xin24m" - crystal input - required, + - "xin32k" - rtc clock - optional, + - "clkin_gmac" - external GMAC clock - optional, + - "clkin_i2s" - external I2S clock - optional, + - "pclkin_cif" - external ISP clock - optional, - "clk_usbphy0_480m" - output clock of the pll in the usbphy0 - "clk_usbphy1_480m" - output clock of the pll in the usbphy1 @@ -46,24 +46,15 @@ properties: const: 1 clocks: - minItems: 1 - - assigned-clocks: - minItems: 1 - maxItems: 64 - - assigned-clock-parents: - minItems: 1 - maxItems: 64 + maxItems: 1 - assigned-clock-rates: - minItems: 1 - maxItems: 64 + clock-names: + const: xin24m rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle - description: > - phandle to the syscon managing the "general register files". It is used + description: + Phandle to the syscon managing the "general register files". It is used for GRF muxes, if missing any muxes present in the GRF will not be available. @@ -77,7 +68,7 @@ additionalProperties: false examples: - | - pmucru: pmu-clock-controller@ff750000 { + pmucru: clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0xff750000 0x1000>; #clock-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml index b2c26097827f..fc7546f521c5 100644 --- a/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3568-cru.yaml @@ -34,6 +34,19 @@ properties: "#reset-cells": const: 1 + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt deleted file mode 100644 index 161326a4f9c1..000000000000 --- a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt +++ /dev/null @@ -1,59 +0,0 @@ -* Rockchip RV1108 Clock and Reset Unit - -The RV1108 clock controller generates and supplies clock to various -controllers within the SoC and also implements a reset controller for SoC -peripherals. - -Required Properties: - -- compatible: should be "rockchip,rv1108-cru" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. -- #reset-cells: should be 1. - -Optional Properties: - -- rockchip,grf: phandle to the syscon managing the "general register files" - If missing pll rates are not changeable, due to the missing pll lock status. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. All available clocks are defined as -preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be -used in device tree sources. Similar macros exist for the reset sources in -these files. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xin24m" - crystal input - required, - - "ext_vip" - external VIP clock - optional - - "ext_i2s" - external I2S clock - optional - - "ext_gmac" - external GMAC clock - optional - - "hdmiphy" - external clock input derived from HDMI PHY - optional - - "usbphy" - external clock input derived from USB PHY - optional - -Example: Clock controller node: - - cru: cru@20200000 { - compatible = "rockchip,rv1108-cru"; - reg = <0x20200000 0x1000>; - rockchip,grf = <&grf>; - - #clock-cells = <1>; - #reset-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller: - - uart0: serial@10230000 { - compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; - reg = <0x10230000 0x100>; - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&cru SCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml new file mode 100644 index 000000000000..20421c22f184 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rv1108-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RV1108 Clock and Reset Unit (CRU) + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + +description: | + The RV1108 clock controller generates and supplies clocks to various + controllers within the SoC and also implements a reset controller for SoC + peripherals. + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All available clocks are defined as + preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be + used in device tree sources. Similar macros exist for the reset sources in + these files. + There are several clocks that are generated outside the SoC. It is expected + that they are defined using standard clock bindings with following + clock-output-names: + - "xin24m" - crystal input - required + - "ext_vip" - external VIP clock - optional + - "ext_i2s" - external I2S clock - optional + - "ext_gmac" - external GMAC clock - optional + - "hdmiphy" - external clock input derived from HDMI PHY - optional + - "usbphy" - external clock input derived from USB PHY - optional + +properties: + compatible: + enum: + - rockchip,rv1108-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF), + if missing pll rates are not changeable, due to the missing pll + lock status. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + cru: clock-controller@20200000 { + compatible = "rockchip,rv1108-cru"; + reg = <0x20200000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml index 45b94124366c..f8c474227807 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -41,6 +41,7 @@ description: | The list of valid indices for STM32MP1 is available in: include/dt-bindings/reset-controller/stm32mp1-resets.h + include/dt-bindings/reset-controller/stm32mp13-resets.h This file implements defines like: #define LTDC_R 3072 @@ -57,6 +58,7 @@ properties: - enum: - st,stm32mp1-rcc-secure - st,stm32mp1-rcc + - st,stm32mp13-rcc - const: syscon clocks: true clock-names: true diff --git a/Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml b/Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml index 9bc95a308477..2150307219a0 100644 --- a/Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml +++ b/Documentation/devicetree/bindings/clock/stericsson,u8500-clks.yaml @@ -109,6 +109,25 @@ properties: additionalProperties: false + clkout-clock: + description: A subnode with three clock cells for externally routed clocks, + output clocks. These are two PRCMU-internal clocks that can be divided and + muxed out on the pads of the DB8500 SoC. + type: object + + properties: + '#clock-cells': + description: + The first cell indicates which output clock we are using, + possible values are 0 (CLKOUT1) and 1 (CLKOUT2). + The second cell indicates which clock we want to use as source, + possible values are 0 thru 7, see the defines for the different + source clocks. + The third cell is a divider, legal values are 1 thru 63. + const: 3 + + additionalProperties: false + required: - compatible - reg @@ -119,3 +138,41 @@ required: - smp-twd-clock additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/ste-db8500-clkout.h> + clocks@8012 { + compatible = "stericsson,u8500-clks"; + reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, + <0x8000f000 0x1000>, <0xa03ff000 0x1000>, + <0xa03cf000 0x1000>; + + prcmu_clk: prcmu-clock { + #clock-cells = <1>; + }; + + prcc_pclk: prcc-periph-clock { + #clock-cells = <2>; + }; + + prcc_kclk: prcc-kernel-clock { + #clock-cells = <2>; + }; + + prcc_reset: prcc-reset-controller { + #reset-cells = <2>; + }; + + rtc_clk: rtc32k-clock { + #clock-cells = <0>; + }; + + smp_twd_clk: smp-twd-clock { + #clock-cells = <0>; + }; + + clkout_clk: clkout-clock { + #clock-cells = <3>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml b/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml index 9b537bc876b5..66765116aff5 100644 --- a/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml +++ b/Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml @@ -15,6 +15,7 @@ properties: - enum: - ti,am654-ehrpwm-tbclk - ti,am64-epwm-tbclk + - ti,am62-epwm-tbclk - const: syscon "#clock-cells": diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt index b8233ec91d3d..e0a4ba599abc 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt @@ -20,6 +20,13 @@ Optional properties: Vsram to fit SoC specific needs. When absent, the voltage scaling flow is handled by hardware, hence no software "voltage tracking" is needed. +- mediatek,cci: + Used to confirm the link status between cpufreq and mediatek cci. Because + cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs. + To prevent the issue of high frequency and low voltage, we need to use this + property to make sure mediatek cci is ready. + For details of mediatek cci, please refer to + Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml - #cooling-cells: For details, please refer to Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml diff --git a/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml b/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml index a410d2cedde6..02f47c2e7998 100644 --- a/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml +++ b/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml @@ -15,6 +15,7 @@ properties: - ti,j721e-sa2ul - ti,am654-sa2ul - ti,am64-sa2ul + - ti,am62-sa3ul reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml index b6e1ebfaf366..ff0a5c58d78c 100644 --- a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml +++ b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml @@ -20,9 +20,11 @@ properties: compatible: oneOf: - - const: allwinner,sun50i-a64-dma - - const: allwinner,sun50i-a100-dma - - const: allwinner,sun50i-h6-dma + - enum: + - allwinner,sun20i-d1-dma + - allwinner,sun50i-a64-dma + - allwinner,sun50i-a100-dma + - allwinner,sun50i-h6-dma - items: - const: allwinner,sun8i-r40-dma - const: allwinner,sun50i-a64-dma @@ -58,6 +60,7 @@ if: properties: compatible: enum: + - allwinner,sun20i-d1-dma - allwinner,sun50i-a100-dma - allwinner,sun50i-h6-dma diff --git a/Documentation/devicetree/bindings/dma/altr,msgdma.yaml b/Documentation/devicetree/bindings/dma/altr,msgdma.yaml index b193ee2db4a7..b53ac7631a76 100644 --- a/Documentation/devicetree/bindings/dma/altr,msgdma.yaml +++ b/Documentation/devicetree/bindings/dma/altr,msgdma.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Altera mSGDMA IP core maintainers: - - Olivier Dautricourt <olivier.dautricourt@orolia.com> + - Olivier Dautricourt <olivierdautricourt@gmail.com> description: | Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) diff --git a/Documentation/devicetree/bindings/dma/arm,pl330.yaml b/Documentation/devicetree/bindings/dma/arm,pl330.yaml index decab185cf4d..2bec69b308f8 100644 --- a/Documentation/devicetree/bindings/dma/arm,pl330.yaml +++ b/Documentation/devicetree/bindings/dma/arm,pl330.yaml @@ -55,6 +55,9 @@ properties: dma-coherent: true + power-domains: + maxItems: 1 + resets: minItems: 1 maxItems: 2 diff --git a/Documentation/devicetree/bindings/dma/mmp-dma.txt b/Documentation/devicetree/bindings/dma/mmp-dma.txt index 8f7364a7b349..ec18bf0a802a 100644 --- a/Documentation/devicetree/bindings/dma/mmp-dma.txt +++ b/Documentation/devicetree/bindings/dma/mmp-dma.txt @@ -10,10 +10,12 @@ Required properties: or one irq for pdma device Optional properties: -- #dma-channels: Number of DMA channels supported by the controller (defaults +- dma-channels: Number of DMA channels supported by the controller (defaults to 32 when not specified) -- #dma-requests: Number of DMA requestor lines supported by the controller +- #dma-channels: deprecated +- dma-requests: Number of DMA requestor lines supported by the controller (defaults to 32 when not specified) +- #dma-requests: deprecated "marvell,pdma-1.0" Used platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688. @@ -33,7 +35,7 @@ pdma: dma-controller@d4000000 { reg = <0xd4000000 0x10000>; interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; interrupt-parent = <&intcmux32>; - #dma-channels = <16>; + dma-channels = <16>; }; /* @@ -45,7 +47,7 @@ pdma: dma-controller@d4000000 { compatible = "marvell,pdma-1.0"; reg = <0xd4000000 0x10000>; interrupts = <47>; - #dma-channels = <16>; + dma-channels = <16>; }; diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml new file mode 100644 index 000000000000..9dd1476d1849 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings + +description: | + The Tegra General Purpose Central (GPC) DMA controller is used for faster + data transfers between memory to memory, memory to device and device to + memory. + +maintainers: + - Jon Hunter <jonathanh@nvidia.com> + - Rajesh Gumasta <rgumasta@nvidia.com> + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + oneOf: + - const: nvidia,tegra186-gpcdma + - items: + - const: nvidia,tegra194-gpcdma + - const: nvidia,tegra186-gpcdma + + "#dma-cells": + const: 1 + + reg: + maxItems: 1 + + interrupts: + description: + Should contain all of the per-channel DMA interrupts in + ascending order with respect to the DMA channel index. + minItems: 1 + maxItems: 31 + + resets: + maxItems: 1 + + reset-names: + const: gpcdma + + iommus: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + - resets + - reset-names + - "#dma-cells" + - iommus + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/memory/tegra186-mc.h> + #include <dt-bindings/reset/tegra186-reset.h> + + dma-controller@2600000 { + compatible = "nvidia,tegra186-gpcdma"; + reg = <0x2600000 0x210000>; + resets = <&bpmp TEGRA186_RESET_GPCDMA>; + reset-names = "gpcdma"; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + iommus = <&smmu TEGRA186_SID_GPCDMA_0>; + dma-coherent; + }; +... diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index d09d79d7406a..7d2fc4eb5530 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -19,9 +19,12 @@ allOf: properties: compatible: enum: + - qcom,sc7280-gpi-dma - qcom,sdm845-gpi-dma - qcom,sm8150-gpi-dma - qcom,sm8250-gpi-dma + - qcom,sm8350-gpi-dma + - qcom,sm8450-gpi-dma reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml index 7c6badf39921..7202cd68e759 100644 --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml @@ -42,11 +42,10 @@ properties: - const: renesas,rcar-dmac - items: - - const: renesas,dmac-r8a779a0 # R-Car V3U - - - items: - - const: renesas,dmac-r8a779f0 # R-Car S4-8 - - const: renesas,rcar-gen4-dmac + - enum: + - renesas,dmac-r8a779a0 # R-Car V3U + - renesas,dmac-r8a779f0 # R-Car S4-8 + - const: renesas,rcar-gen4-dmac # R-Car Gen4 reg: true @@ -121,7 +120,6 @@ if: compatible: contains: enum: - - renesas,dmac-r8a779a0 - renesas,rcar-gen4-dmac then: properties: diff --git a/Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml b/Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml new file mode 100644 index 000000000000..d83013b0dd74 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/renesas,rzn1-dmamux.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/renesas,rzn1-dmamux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 DMA mux + +maintainers: + - Miquel Raynal <miquel.raynal@bootlin.com> + +allOf: + - $ref: "dma-router.yaml#" + +properties: + compatible: + const: renesas,rzn1-dmamux + + reg: + maxItems: 1 + description: DMA mux first register offset within the system control parent. + + '#dma-cells': + const: 6 + description: + The first four cells are dedicated to the master DMA controller. The fifth + cell gives the DMA mux bit index that must be set starting from 0. The + sixth cell gives the binary value that must be written there, ie. 0 or 1. + + dma-masters: + minItems: 1 + maxItems: 2 + + dma-requests: + const: 32 + +required: + - reg + - dma-requests + +additionalProperties: false + +examples: + - | + dma-router@a0 { + compatible = "renesas,rzn1-dmamux"; + reg = <0xa0 4>; + #dma-cells = <6>; + dma-masters = <&dma0 &dma1>; + dma-requests = <32>; + }; diff --git a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml index 47c46af25536..3271755787b4 100644 --- a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml @@ -28,7 +28,15 @@ allOf: properties: compatible: items: - - const: sifive,fu540-c000-pdma + - enum: + - sifive,fu540-c000-pdma + - const: sifive,pdma0 + description: + Should be "sifive,<chip>-pdma" and "sifive,pdma<version>". + Supported compatible strings are - + "sifive,fu540-c000-pdma" for the SiFive PDMA v0 as integrated onto the + SiFive FU540 chip resp and "sifive,pdma0" for the SiFive PDMA v0 IP block + with no chip integration tweaks. reg: maxItems: 1 @@ -37,6 +45,12 @@ properties: minItems: 1 maxItems: 8 + dma-channels: + description: For backwards-compatibility, the default value is 4 + minimum: 1 + maximum: 4 + default: 4 + '#dma-cells': const: 1 @@ -50,8 +64,9 @@ unevaluatedProperties: false examples: - | dma-controller@3000000 { - compatible = "sifive,fu540-c000-pdma"; + compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; reg = <0x3000000 0x8000>; + dma-channels = <4>; interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>; #dma-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml b/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml index 6b35089ac017..c13649bf7f19 100644 --- a/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml @@ -15,7 +15,13 @@ allOf: properties: compatible: - const: snps,dma-spear1340 + oneOf: + - const: snps,dma-spear1340 + - items: + - enum: + - renesas,r9a06g032-dma + - const: renesas,rzn1-dma + "#dma-cells": minimum: 3 diff --git a/Documentation/devicetree/bindings/dma/sprd-dma.txt b/Documentation/devicetree/bindings/dma/sprd-dma.txt index adccea9941f1..c7e9b5fd50e7 100644 --- a/Documentation/devicetree/bindings/dma/sprd-dma.txt +++ b/Documentation/devicetree/bindings/dma/sprd-dma.txt @@ -8,10 +8,13 @@ Required properties: - interrupts: Should contain one interrupt shared by all channel. - #dma-cells: must be <1>. Used to represent the number of integer cells in the dmas property of client device. -- #dma-channels : Number of DMA channels supported. Should be 32. +- dma-channels : Number of DMA channels supported. Should be 32. - clock-names: Should contain the clock of the DMA controller. - clocks: Should contain a clock specifier for each entry in clock-names. +Deprecated properties: +- #dma-channels : Number of DMA channels supported. Should be 32. + Example: Controller: @@ -20,7 +23,7 @@ apdma: dma-controller@20100000 { reg = <0x20100000 0x4000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; - #dma-channels = <32>; + dma-channels = <32>; clock-names = "enable"; clocks = <&clk_ap_ahb_gates 5>; }; diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index 325aca52cd43..d1700a5c36bf 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -110,7 +110,11 @@ axi_vdma_0: axivdma@40030000 { Required properties: - dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs, where Channel ID is '0' for write/tx and '1' for read/rx - channel. + channel. For MCMDA, MM2S channel(write/tx) ID start from + '0' and is in [0-15] range. S2MM channel(read/rx) ID start + from '16' and is in [16-31] range. These channels ID are + fixed irrespective of IP configuration. + - dma-names: a list of DMA channel names, one per "dmas" entry Example: diff --git a/Documentation/devicetree/bindings/gpio/gpio-consumer-common.yaml b/Documentation/devicetree/bindings/gpio/gpio-consumer-common.yaml new file mode 100644 index 000000000000..40d0be31e200 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-consumer-common.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/gpio-consumer-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common GPIO lines + +maintainers: + - Bartosz Golaszewski <brgl@bgdev.pl> + - Linus Walleij <linus.walleij@linaro.org> + +description: + Pay attention to using proper GPIO flag (e.g. GPIO_ACTIVE_LOW) for the GPIOs + using inverted signal (e.g. RESETN). + +select: true + +properties: + enable-gpios: + maxItems: 1 + description: + GPIO connected to the enable control pin. + + reset-gpios: + description: + GPIO (or GPIOs for power sequence) connected to the device reset pin + (e.g. RESET or RESETN). + + powerdown-gpios: + maxItems: 1 + description: + GPIO connected to the power down pin (hardware power down or power cut, + e.g. PD or PWDN). + + pwdn-gpios: + maxItems: 1 + description: Use powerdown-gpios + deprecated: true + + wakeup-gpios: + maxItems: 1 + description: + GPIO connected to the pin waking up the device from suspend or other + power-saving modes. + +allOf: + - if: + properties: + compatible: + contains: + enum: + - mmc-pwrseq-simple + then: + properties: + reset-gpios: + minItems: 1 + maxItems: 32 + else: + properties: + reset-gpios: + maxItems: 1 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml index dc0fc8fc4839..977b14db09b0 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml @@ -30,6 +30,7 @@ properties: - maxim,max7325 - maxim,max7326 - maxim,max7327 + - nxp,pca6408 - nxp,pca6416 - nxp,pca9505 - nxp,pca9506 diff --git a/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml b/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml index 100f20cebd76..39fd959c45d2 100644 --- a/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/realtek,otto-gpio.yaml @@ -28,10 +28,11 @@ properties: - enum: - realtek,rtl8380-gpio - realtek,rtl8390-gpio + - realtek,rtl9300-gpio + - realtek,rtl9310-gpio - const: realtek,otto-gpio - reg: - maxItems: 1 + reg: true "#gpio-cells": const: 2 @@ -50,6 +51,23 @@ properties: interrupts: maxItems: 1 +if: + properties: + compatible: + contains: + const: realtek,rtl9300-gpio +then: + properties: + reg: + items: + - description: GPIO and interrupt control + - description: interrupt CPU map +else: + properties: + reg: + items: + - description: GPIO and interrupt control + required: - compatible - reg @@ -74,5 +92,17 @@ examples: interrupt-parent = <&rtlintc>; interrupts = <23>; }; + - | + gpio@3300 { + compatible = "realtek,rtl9300-gpio", "realtek,otto-gpio"; + reg = <0x3300 0x1c>, <0x3338 0x8>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <24>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&rtlintc>; + interrupts = <13>; + }; ... diff --git a/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml b/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml index f2541739ee3b..0681a4790cd6 100644 --- a/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml @@ -51,6 +51,11 @@ properties: - items: - const: renesas,gpio-r8a779a0 # R-Car V3U + - items: + - enum: + - renesas,gpio-r8a779f0 # R-Car S4-8 + - const: renesas,rcar-gen4-gpio # R-Car Gen4 + reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml b/Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml index bcafa494ed7a..228fa27ffdc3 100644 --- a/Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml @@ -52,6 +52,23 @@ properties: <child-interrupt-base parent-interrupt-base length> triplets. $ref: /schemas/types.yaml#/definitions/uint32-matrix +patternProperties: + "^.+-hog(-[0-9]+)?$": + type: object + properties: + gpio-hog: true + gpios: true + input: true + output-high: true + output-low: true + line-name: true + + required: + - gpio-hog + - gpios + + additionalProperties: false + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml b/Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml index c30107833a51..f9929578c761 100644 --- a/Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml @@ -46,11 +46,11 @@ properties: - renesas,i2c-r8a77980 # R-Car V3H - renesas,i2c-r8a77990 # R-Car E3 - renesas,i2c-r8a77995 # R-Car D3 - - renesas,i2c-r8a779a0 # R-Car V3U - const: renesas,rcar-gen3-i2c # R-Car Gen3 and RZ/G2 - items: - enum: + - renesas,i2c-r8a779a0 # R-Car V3U - renesas,i2c-r8a779f0 # R-Car S4-8 - const: renesas,rcar-gen4-i2c # R-Car Gen4 diff --git a/Documentation/devicetree/bindings/i3c/cdns,i3c-master.txt b/Documentation/devicetree/bindings/i3c/cdns,i3c-master.txt deleted file mode 100644 index 3716589d6999..000000000000 --- a/Documentation/devicetree/bindings/i3c/cdns,i3c-master.txt +++ /dev/null @@ -1,43 +0,0 @@ -Bindings for cadence I3C master block -===================================== - -Required properties: --------------------- -- compatible: shall be "cdns,i3c-master" -- clocks: shall reference the pclk and sysclk -- clock-names: shall contain "pclk" and "sysclk" -- interrupts: the interrupt line connected to this I3C master -- reg: I3C master registers - -Mandatory properties defined by the generic binding (see -Documentation/devicetree/bindings/i3c/i3c.yaml for more details): - -- #address-cells: shall be set to 1 -- #size-cells: shall be set to 0 - -Optional properties defined by the generic binding (see -Documentation/devicetree/bindings/i3c/i3c.yaml for more details): - -- i2c-scl-hz -- i3c-scl-hz - -I3C device connected on the bus follow the generic description (see -Documentation/devicetree/bindings/i3c/i3c.yaml for more details). - -Example: - - i3c-master@0d040000 { - compatible = "cdns,i3c-master"; - clocks = <&coreclock>, <&i3csysclock>; - clock-names = "pclk", "sysclk"; - interrupts = <3 0>; - reg = <0x0d040000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - i2c-scl-hz = <100000>; - - nunchuk: nunchuk@52 { - compatible = "nintendo,nunchuk"; - reg = <0x52 0x0 0x10>; - }; - }; diff --git a/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml b/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml new file mode 100644 index 000000000000..cc40d25358ec --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i3c/cdns,i3c-master.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence I3C master block + +maintainers: + - Boris Brezillon <bbrezillon@kernel.org> + +allOf: + - $ref: i3c.yaml# + +properties: + compatible: + const: cdns,i3c-master + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: pclk + - const: sysclk + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +unevaluatedProperties: false + +examples: + - | + i3c-master@d040000 { + compatible = "cdns,i3c-master"; + clocks = <&coreclock>, <&i3csysclock>; + clock-names = "pclk", "sysclk"; + interrupts = <3 0>; + reg = <0x0d040000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + i2c-scl-hz = <100000>; + + eeprom@57{ + compatible = "atmel,24c01"; + reg = <0x57 0x0 0x10>; + pagesize = <0x8>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.txt b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.txt deleted file mode 100644 index 07f35f36085d..000000000000 --- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.txt +++ /dev/null @@ -1,41 +0,0 @@ -Bindings for Synopsys DesignWare I3C master block -================================================= - -Required properties: --------------------- -- compatible: shall be "snps,dw-i3c-master-1.00a" -- clocks: shall reference the core_clk -- interrupts: the interrupt line connected to this I3C master -- reg: Offset and length of I3C master registers - -Mandatory properties defined by the generic binding (see -Documentation/devicetree/bindings/i3c/i3c.yaml for more details): - -- #address-cells: shall be set to 3 -- #size-cells: shall be set to 0 - -Optional properties defined by the generic binding (see -Documentation/devicetree/bindings/i3c/i3c.yaml for more details): - -- i2c-scl-hz -- i3c-scl-hz - -I3C device connected on the bus follow the generic description (see -Documentation/devicetree/bindings/i3c/i3c.yaml for more details). - -Example: - - i3c-master@2000 { - compatible = "snps,dw-i3c-master-1.00a"; - #address-cells = <3>; - #size-cells = <0>; - reg = <0x02000 0x1000>; - interrupts = <0>; - clocks = <&i3cclk>; - - eeprom@57{ - compatible = "atmel,24c01"; - reg = <0x57 0x0 0x10>; - pagesize = <0x8>; - }; - }; diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml new file mode 100644 index 000000000000..7a76fd32962a --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i3c/snps,dw-i3c-master.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare I3C master block + +maintainers: + - Alexandre Belloni <alexandre.belloni@bootlin.com> + +allOf: + - $ref: i3c.yaml# + +properties: + compatible: + const: snps,dw-i3c-master-1.00a + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +unevaluatedProperties: false + +examples: + - | + i3c-master@2000 { + compatible = "snps,dw-i3c-master-1.00a"; + #address-cells = <3>; + #size-cells = <0>; + reg = <0x02000 0x1000>; + interrupts = <0>; + clocks = <&i3cclk>; + + eeprom@57{ + compatible = "atmel,24c01"; + reg = <0x57 0x0 0x10>; + pagesize = <0x8>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml index d74f2002409e..3399fc288afb 100644 --- a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml +++ b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml @@ -18,10 +18,20 @@ properties: - items: - const: allwinner,sun50i-a64-lradc - const: allwinner,sun8i-a83t-r-lradc + - const: allwinner,sun50i-r329-lradc + - items: + - const: allwinner,sun20i-d1-lradc + - const: allwinner,sun50i-r329-lradc reg: maxItems: 1 + clocks: + maxItems: 1 + + resets: + maxItems: 1 + interrupts: maxItems: 1 @@ -68,6 +78,18 @@ required: - interrupts - vref-supply +if: + properties: + compatible: + contains: + enum: + - allwinner,sun50i-r329-lradc + +then: + required: + - clocks + - resets + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/input/azoteq,iqs7222.yaml b/Documentation/devicetree/bindings/input/azoteq,iqs7222.yaml new file mode 100644 index 000000000000..a3a1e5a65306 --- /dev/null +++ b/Documentation/devicetree/bindings/input/azoteq,iqs7222.yaml @@ -0,0 +1,960 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/azoteq,iqs7222.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Azoteq IQS7222A/B/C Capacitive Touch Controller + +maintainers: + - Jeff LaBundy <jeff@labundy.com> + +description: | + The Azoteq IQS7222A, IQS7222B and IQS7222C are multichannel capacitive touch + controllers that feature additional sensing capabilities. + + Link to datasheets: https://www.azoteq.com/ + +properties: + compatible: + enum: + - azoteq,iqs7222a + - azoteq,iqs7222b + - azoteq,iqs7222c + + reg: + maxItems: 1 + + irq-gpios: + maxItems: 1 + description: + Specifies the GPIO connected to the device's active-low RDY output. + + reset-gpios: + maxItems: 1 + description: + Specifies the GPIO connected to the device's active-low MCLR input. The + device is temporarily held in hardware reset prior to initialization if + this property is present. + + azoteq,rf-filt-enable: + type: boolean + description: Enables the device's internal RF filter. + + azoteq,max-counts: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + description: | + Specifies the maximum number of conversion periods (counts) that can be + reported as follows: + 0: 1023 + 1: 2047 + 2: 4095 + 3: 16384 + + azoteq,auto-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + description: | + Specifies the number of conversions to occur before an interrupt is + generated as follows: + 0: 4 + 1: 8 + 2: 16 + 3: 32 + + azoteq,ati-frac-div-fine: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: Specifies the preloaded ATI fine fractional divider. + + azoteq,ati-frac-div-coarse: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: Specifies the preloaded ATI coarse fractional divider. + + azoteq,ati-comp-select: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 1023 + description: Specifies the preloaded ATI compensation selection. + + azoteq,lta-beta-lp: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: + Specifies the long-term average filter damping factor to be applied during + low-power mode. + + azoteq,lta-beta-np: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: + Specifies the long-term average filter damping factor to be applied during + normal-power mode. + + azoteq,counts-beta-lp: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: + Specifies the counts filter damping factor to be applied during low-power + mode. + + azoteq,counts-beta-np: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: + Specifies the counts filter damping factor to be applied during normal- + power mode. + + azoteq,lta-fast-beta-lp: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: + Specifies the long-term average filter fast damping factor to be applied + during low-power mode. + + azoteq,lta-fast-beta-np: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: + Specifies the long-term average filter fast damping factor to be applied + during normal-power mode. + + azoteq,timeout-ati-ms: + multipleOf: 500 + minimum: 0 + maximum: 32767500 + description: + Specifies the delay (in ms) before ATI is retried following an ATI error. + + azoteq,rate-ati-ms: + minimum: 0 + maximum: 65535 + description: Specifies the rate (in ms) at which ATI status is evaluated. + + azoteq,timeout-np-ms: + minimum: 0 + maximum: 65535 + description: + Specifies the length of time (in ms) to wait for an event before moving + from normal-power mode to low-power mode. + + azoteq,rate-np-ms: + minimum: 0 + maximum: 3000 + description: Specifies the report rate (in ms) during normal-power mode. + + azoteq,timeout-lp-ms: + minimum: 0 + maximum: 65535 + description: + Specifies the length of time (in ms) to wait for an event before moving + from low-power mode to ultra-low-power mode. + + azoteq,rate-lp-ms: + minimum: 0 + maximum: 3000 + description: Specifies the report rate (in ms) during low-power mode. + + azoteq,timeout-ulp-ms: + minimum: 0 + maximum: 65535 + description: + Specifies the rate (in ms) at which channels not regularly sampled during + ultra-low-power mode are updated. + + azoteq,rate-ulp-ms: + minimum: 0 + maximum: 3000 + description: Specifies the report rate (in ms) during ultra-low-power mode. + +patternProperties: + "^cycle-[0-9]$": + type: object + description: Represents a conversion cycle serving two sensing channels. + + properties: + azoteq,conv-period: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 255 + description: Specifies the cycle's conversion period. + + azoteq,conv-frac: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 255 + description: Specifies the cycle's conversion frequency fraction. + + azoteq,tx-enable: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 9 + items: + minimum: 0 + maximum: 8 + description: Specifies the CTx pin(s) associated with the cycle. + + azoteq,rx-float-inactive: + type: boolean + description: Floats any inactive CRx pins instead of grounding them. + + azoteq,dead-time-enable: + type: boolean + description: + Increases the denominator of the conversion frequency formula by one. + + azoteq,tx-freq-fosc: + type: boolean + description: + Fixes the conversion frequency to that of the device's core clock. + + azoteq,vbias-enable: + type: boolean + description: Enables the bias voltage for use during inductive sensing. + + azoteq,sense-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + description: | + Specifies the cycle's sensing mode as follows: + 0: None + 1: Self capacitive + 2: Mutual capacitive + 3: Inductive + + Note that in the case of IQS7222A, cycles 5 and 6 are restricted to + Hall-effect sensing. + + azoteq,iref-enable: + type: boolean + description: + Enables the current reference for use during various sensing modes. + + azoteq,iref-level: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: Specifies the cycle's current reference level. + + azoteq,iref-trim: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: Specifies the cycle's current reference trim. + + dependencies: + azoteq,iref-level: ["azoteq,iref-enable"] + azoteq,iref-trim: ["azoteq,iref-enable"] + + additionalProperties: false + + "^channel-([0-9]|1[0-9])$": + type: object + description: + Represents a single sensing channel. A channel is active if defined and + inactive otherwise. + + Note that in the case of IQS7222A, channels 10 and 11 are restricted to + Hall-effect sensing with events reported on channel 10 only. + + properties: + azoteq,ulp-allow: + type: boolean + description: + Permits the device to enter ultra-low-power mode while the channel + lies in a state of touch or proximity. + + azoteq,ref-select: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 9 + description: Specifies a separate reference channel to be followed. + + azoteq,ref-weight: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 65535 + description: Specifies the relative weight of the reference channel. + + azoteq,use-prox: + type: boolean + description: + Activates the reference channel in response to proximity events + instead of touch events. + + azoteq,ati-band: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + description: | + Specifies the channel's ATI band as a fraction of its ATI target as + follows: + 0: 1/16 + 1: 1/8 + 2: 1/4 + 3: 1/2 + + azoteq,global-halt: + type: boolean + description: + Specifies that the channel's long-term average is to freeze if any + other participating channel lies in a proximity or touch state. + + azoteq,invert-enable: + type: boolean + description: + Inverts the polarity of the states reported for proximity and touch + events relative to their respective thresholds. + + azoteq,dual-direction: + type: boolean + description: + Specifies that the channel's long-term average is to freeze in the + presence of either increasing or decreasing counts, thereby permit- + ting events to be reported in either direction. + + azoteq,rx-enable: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + items: + minimum: 0 + maximum: 7 + description: Specifies the CRx pin(s) associated with the channel. + + azoteq,samp-cap-double: + type: boolean + description: Doubles the sampling capacitance from 40 pF to 80 pF. + + azoteq,vref-half: + type: boolean + description: Halves the discharge threshold from 1.0 V to 0.5 V. + + azoteq,proj-bias: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + description: | + Specifies the bias current applied during mutual (projected) + capacitive sensing as follows: + 0: 2 uA + 1: 5 uA + 2: 7 uA + 3: 10 uA + + azoteq,ati-target: + $ref: /schemas/types.yaml#/definitions/uint32 + multipleOf: 8 + minimum: 0 + maximum: 2040 + description: Specifies the channel's ATI target. + + azoteq,ati-base: + $ref: /schemas/types.yaml#/definitions/uint32 + multipleOf: 16 + minimum: 0 + maximum: 496 + description: Specifies the channel's ATI base. + + azoteq,ati-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5] + description: | + Specifies the channel's ATI mode as follows: + 0: Disabled + 1: Compensation + 2: Compensation divider + 3: Fine fractional divider + 4: Coarse fractional divider + 5: Full + + azoteq,ati-frac-div-fine: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: Specifies the channel's ATI fine fractional divider. + + azoteq,ati-frac-mult-coarse: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: Specifies the channel's ATI coarse fractional multiplier. + + azoteq,ati-frac-div-coarse: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: Specifies the channel's ATI coarse fractional divider. + + azoteq,ati-comp-div: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: Specifies the channel's ATI compensation divider. + + azoteq,ati-comp-select: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 1023 + description: Specifies the channel's ATI compensation selection. + + azoteq,debounce-enter: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: Specifies the channel's debounce entrance factor. + + azoteq,debounce-exit: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: Specifies the channel's debounce exit factor. + + patternProperties: + "^event-(prox|touch)$": + type: object + description: + Represents a proximity or touch event reported by the channel. + + properties: + azoteq,gpio-select: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 3 + items: + minimum: 0 + maximum: 2 + description: | + Specifies one or more GPIO mapped to the event as follows: + 0: GPIO0 + 1: GPIO3 (IQS7222C only) + 2: GPIO4 (IQS7222C only) + + Note that although multiple events can be mapped to a single + GPIO, they must all be of the same type (proximity, touch or + slider gesture). + + azoteq,thresh: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Specifies the threshold for the event. Valid entries range from + 0-127 and 0-255 for proximity and touch events, respectively. + + azoteq,hyst: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 255 + description: + Specifies the hysteresis for the event (touch events only). + + azoteq,timeout-press-ms: + multipleOf: 500 + minimum: 0 + maximum: 127500 + description: + Specifies the length of time (in ms) to wait before automatically + releasing a press event. Specify zero to allow the press state to + persist indefinitely. + + The IQS7222B does not feature channel-specific timeouts; the time- + out specified for any one channel applies to all channels. + + linux,code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Numeric key or switch code associated with the event. Specify + KEY_RESERVED (0) to opt out of event reporting. + + linux,input-type: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 5] + default: 1 + description: + Specifies whether the event is to be interpreted as a key (1) + or a switch (5). + + required: + - linux,code + + additionalProperties: false + + dependencies: + azoteq,ref-weight: ["azoteq,ref-select"] + azoteq,use-prox: ["azoteq,ref-select"] + + additionalProperties: false + + "^slider-[0-1]$": + type: object + description: Represents a slider comprising three or four channels. + + properties: + azoteq,channel-select: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + maxItems: 4 + items: + minimum: 0 + maximum: 9 + description: + Specifies the order of the channels that participate in the slider. + + azoteq,slider-size: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 65535 + description: + Specifies the slider's one-dimensional resolution, equal to the + maximum coordinate plus one. + + azoteq,lower-cal: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 255 + description: Specifies the slider's lower starting point. + + azoteq,upper-cal: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 255 + description: Specifies the slider's upper starting point. + + azoteq,top-speed: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 65535 + description: + Specifies the speed of movement after which coordinate filtering is + no longer applied. + + azoteq,bottom-speed: + $ref: /schemas/types.yaml#/definitions/uint32 + multipleOf: 4 + minimum: 0 + maximum: 1020 + description: + Specifies the speed of movement after which coordinate filtering is + linearly reduced. + + azoteq,bottom-beta: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + description: + Specifies the coordinate filter damping factor to be applied + while the speed of movement is below that which is specified + by azoteq,bottom-speed. + + azoteq,static-beta: + type: boolean + description: + Applies the coordinate filter damping factor specified by + azoteq,bottom-beta regardless of the speed of movement. + + azoteq,use-prox: + type: boolean + description: + Directs the slider to respond to the proximity states of the selected + channels instead of their corresponding touch states. Note the slider + cannot report granular coordinates during a state of proximity. + + linux,axis: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Specifies the absolute axis to which coordinates are mapped. Specify + ABS_WHEEL to operate the slider as a wheel (IQS7222C only). + + patternProperties: + "^event-(press|tap|(swipe|flick)-(pos|neg))$": + type: object + description: + Represents a press or gesture (IQS7222A only) event reported by + the slider. + + properties: + linux,code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Numeric key code associated with the event. + + azoteq,gesture-max-ms: + multipleOf: 4 + minimum: 0 + maximum: 1020 + description: + Specifies the length of time (in ms) within which a tap, swipe + or flick gesture must be completed in order to be acknowledged + by the device. The number specified for any one swipe or flick + gesture applies to all remaining swipe or flick gestures. + + azoteq,gesture-min-ms: + multipleOf: 4 + minimum: 0 + maximum: 124 + description: + Specifies the length of time (in ms) for which a tap gesture must + be held in order to be acknowledged by the device. + + azoteq,gesture-dist: + $ref: /schemas/types.yaml#/definitions/uint32 + multipleOf: 16 + minimum: 0 + maximum: 4080 + description: + Specifies the distance across which a swipe or flick gesture must + travel in order to be acknowledged by the device. The number spec- + ified for any one swipe or flick gesture applies to all remaining + swipe or flick gestures. + + azoteq,gpio-select: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 1 + items: + minimum: 0 + maximum: 0 + description: | + Specifies an individual GPIO mapped to a tap, swipe or flick + gesture as follows: + 0: GPIO0 + 1: GPIO3 (reserved) + 2: GPIO4 (reserved) + + Note that although multiple events can be mapped to a single + GPIO, they must all be of the same type (proximity, touch or + slider gesture). + + required: + - linux,code + + additionalProperties: false + + required: + - azoteq,channel-select + + additionalProperties: false + + "^gpio-[0-2]$": + type: object + description: | + Represents a GPIO mapped to one or more events as follows: + gpio-0: GPIO0 + gpio-1: GPIO3 (IQS7222C only) + gpio-2: GPIO4 (IQS7222C only) + + allOf: + - $ref: ../pinctrl/pincfg-node.yaml# + + properties: + drive-open-drain: true + + additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: azoteq,iqs7222b + + then: + patternProperties: + "^cycle-[0-9]$": + properties: + azoteq,iref-enable: false + + "^channel-([0-9]|1[0-9])$": + properties: + azoteq,ref-select: false + + patternProperties: + "^event-(prox|touch)$": + properties: + azoteq,gpio-select: false + + "^slider-[0-1]$": false + + "^gpio-[0-2]$": false + + - if: + properties: + compatible: + contains: + const: azoteq,iqs7222a + + then: + patternProperties: + "^channel-([0-9]|1[0-9])$": + patternProperties: + "^event-(prox|touch)$": + properties: + azoteq,gpio-select: + maxItems: 1 + items: + maximum: 0 + + "^slider-[0-1]$": + properties: + azoteq,slider-size: + multipleOf: 16 + maximum: 4080 + + azoteq,top-speed: + multipleOf: 4 + maximum: 1020 + + else: + patternProperties: + "^channel-([0-9]|1[0-9])$": + properties: + azoteq,ulp-allow: false + + "^slider-[0-1]$": + patternProperties: + "^event-(press|tap|(swipe|flick)-(pos|neg))$": + properties: + azoteq,gesture-max-ms: false + + azoteq,gesture-min-ms: false + + azoteq,gesture-dist: false + + azoteq,gpio-select: false + +required: + - compatible + - reg + - irq-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/input/input.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + iqs7222a@44 { + compatible = "azoteq,iqs7222a"; + reg = <0x44>; + irq-gpios = <&gpio 4 GPIO_ACTIVE_LOW>; + azoteq,lta-beta-lp = <7>; + azoteq,lta-beta-np = <8>; + azoteq,counts-beta-lp = <2>; + azoteq,counts-beta-np = <3>; + azoteq,lta-fast-beta-lp = <3>; + azoteq,lta-fast-beta-np = <4>; + + cycle-0 { + azoteq,conv-period = <5>; + azoteq,conv-frac = <127>; + azoteq,tx-enable = <1>, <2>, <4>, <5>; + azoteq,dead-time-enable; + azoteq,sense-mode = <2>; + }; + + cycle-1 { + azoteq,conv-period = <5>; + azoteq,conv-frac = <127>; + azoteq,tx-enable = <5>; + azoteq,dead-time-enable; + azoteq,sense-mode = <2>; + }; + + cycle-2 { + azoteq,conv-period = <5>; + azoteq,conv-frac = <127>; + azoteq,tx-enable = <4>; + azoteq,dead-time-enable; + azoteq,sense-mode = <2>; + }; + + cycle-3 { + azoteq,conv-period = <5>; + azoteq,conv-frac = <127>; + azoteq,tx-enable = <2>; + azoteq,dead-time-enable; + azoteq,sense-mode = <2>; + }; + + cycle-4 { + azoteq,conv-period = <5>; + azoteq,conv-frac = <127>; + azoteq,tx-enable = <1>; + azoteq,dead-time-enable; + azoteq,sense-mode = <2>; + }; + + cycle-5 { + azoteq,conv-period = <2>; + azoteq,conv-frac = <0>; + }; + + cycle-6 { + azoteq,conv-period = <2>; + azoteq,conv-frac = <0>; + }; + + channel-0 { + azoteq,ulp-allow; + azoteq,global-halt; + azoteq,invert-enable; + azoteq,rx-enable = <3>; + azoteq,ati-target = <800>; + azoteq,ati-base = <208>; + azoteq,ati-mode = <5>; + }; + + channel-1 { + azoteq,global-halt; + azoteq,invert-enable; + azoteq,rx-enable = <3>; + azoteq,ati-target = <496>; + azoteq,ati-base = <208>; + azoteq,ati-mode = <5>; + }; + + channel-2 { + azoteq,global-halt; + azoteq,invert-enable; + azoteq,rx-enable = <3>; + azoteq,ati-target = <496>; + azoteq,ati-base = <208>; + azoteq,ati-mode = <5>; + }; + + channel-3 { + azoteq,global-halt; + azoteq,invert-enable; + azoteq,rx-enable = <3>; + azoteq,ati-target = <496>; + azoteq,ati-base = <208>; + azoteq,ati-mode = <5>; + }; + + channel-4 { + azoteq,global-halt; + azoteq,invert-enable; + azoteq,rx-enable = <3>; + azoteq,ati-target = <496>; + azoteq,ati-base = <208>; + azoteq,ati-mode = <5>; + }; + + channel-5 { + azoteq,ulp-allow; + azoteq,global-halt; + azoteq,invert-enable; + azoteq,rx-enable = <6>; + azoteq,ati-target = <800>; + azoteq,ati-base = <144>; + azoteq,ati-mode = <5>; + }; + + channel-6 { + azoteq,global-halt; + azoteq,invert-enable; + azoteq,rx-enable = <6>; + azoteq,ati-target = <496>; + azoteq,ati-base = <160>; + azoteq,ati-mode = <5>; + + event-touch { + linux,code = <KEY_MUTE>; + }; + }; + + channel-7 { + azoteq,global-halt; + azoteq,invert-enable; + azoteq,rx-enable = <6>; + azoteq,ati-target = <496>; + azoteq,ati-base = <160>; + azoteq,ati-mode = <5>; + + event-touch { + linux,code = <KEY_VOLUMEDOWN>; + }; + }; + + channel-8 { + azoteq,global-halt; + azoteq,invert-enable; + azoteq,rx-enable = <6>; + azoteq,ati-target = <496>; + azoteq,ati-base = <160>; + azoteq,ati-mode = <5>; + + event-touch { + linux,code = <KEY_VOLUMEUP>; + }; + }; + + channel-9 { + azoteq,global-halt; + azoteq,invert-enable; + azoteq,rx-enable = <6>; + azoteq,ati-target = <496>; + azoteq,ati-base = <160>; + azoteq,ati-mode = <5>; + + event-touch { + linux,code = <KEY_POWER>; + }; + }; + + channel-10 { + azoteq,ulp-allow; + azoteq,ati-target = <496>; + azoteq,ati-base = <112>; + + event-touch { + linux,code = <SW_LID>; + linux,input-type = <EV_SW>; + }; + }; + + channel-11 { + azoteq,ati-target = <496>; + azoteq,ati-base = <112>; + }; + + slider-0 { + azoteq,channel-select = <1>, <2>, <3>, <4>; + azoteq,slider-size = <4080>; + azoteq,upper-cal = <50>; + azoteq,lower-cal = <30>; + azoteq,top-speed = <200>; + azoteq,bottom-speed = <1>; + azoteq,bottom-beta = <3>; + + event-tap { + linux,code = <KEY_PLAYPAUSE>; + azoteq,gesture-max-ms = <600>; + azoteq,gesture-min-ms = <24>; + }; + + event-flick-pos { + linux,code = <KEY_NEXTSONG>; + azoteq,gesture-max-ms = <600>; + azoteq,gesture-dist = <816>; + }; + + event-flick-neg { + linux,code = <KEY_PREVIOUSSONG>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/input/google,cros-ec-keyb.yaml b/Documentation/devicetree/bindings/input/google,cros-ec-keyb.yaml index aa61fe64be63..e05690b3e963 100644 --- a/Documentation/devicetree/bindings/input/google,cros-ec-keyb.yaml +++ b/Documentation/devicetree/bindings/input/google,cros-ec-keyb.yaml @@ -15,14 +15,16 @@ description: | Google's ChromeOS EC Keyboard is a simple matrix keyboard implemented on a separate EC (Embedded Controller) device. It provides a message for reading key scans from the EC. These are then converted - into keycodes for processing by the kernel. - -allOf: - - $ref: "/schemas/input/matrix-keymap.yaml#" + into keycodes for processing by the kernel. This device also supports + switches/buttons like power and volume buttons. properties: compatible: - const: google,cros-ec-keyb + oneOf: + - description: ChromeOS EC with only buttons/switches + const: google,cros-ec-keyb-switches + - description: ChromeOS EC with keyboard and possibly buttons/switches + const: google,cros-ec-keyb google,needs-ghost-filter: description: @@ -42,15 +44,31 @@ properties: where the lower 16 bits are reserved. This property is specified only when the keyboard has a custom design for the top row keys. +dependencies: + function-row-phsymap: [ 'linux,keymap' ] + google,needs-ghost-filter: [ 'linux,keymap' ] + required: - compatible +if: + properties: + compatible: + contains: + const: google,cros-ec-keyb +then: + $ref: "/schemas/input/matrix-keymap.yaml#" + required: + - keypad,num-rows + - keypad,num-columns + - linux,keymap + unevaluatedProperties: false examples: - | #include <dt-bindings/input/input.h> - cros-ec-keyb { + keyboard-controller { compatible = "google,cros-ec-keyb"; keypad,num-rows = <8>; keypad,num-columns = <13>; @@ -114,3 +132,9 @@ examples: /* UP LEFT */ 0x070b0067 0x070c0069>; }; + - | + /* No matrix keyboard, just buttons/switches */ + keyboard-controller { + compatible = "google,cros-ec-keyb-switches"; + }; +... diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt index 3b7b1134dea9..159a423e5586 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt @@ -22,6 +22,7 @@ Properties: - "qcom,sc7280-pdc": For SC7280 - "qcom,sdm845-pdc": For SDM845 - "qcom,sm6350-pdc": For SM6350 + - "qcom,sm8150-pdc": For SM8150 - "qcom,sm8250-pdc": For SM8250 - "qcom,sm8350-pdc": For SM8350 diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index da5381c8ee11..76fc2c0f4d54 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -37,8 +37,10 @@ properties: - qcom,sc7180-smmu-500 - qcom,sc7280-smmu-500 - qcom,sc8180x-smmu-500 + - qcom,sc8280xp-smmu-500 - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 + - qcom,sdx65-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 @@ -62,8 +64,9 @@ properties: for improved performance. items: - enum: - - nvidia,tegra194-smmu - nvidia,tegra186-smmu + - nvidia,tegra194-smmu + - nvidia,tegra234-smmu - const: nvidia,smmu-500 - items: - const: arm,mmu-500 @@ -157,6 +160,17 @@ properties: power-domains: maxItems: 1 + nvidia,memory-controller: + description: | + A phandle to the memory controller on NVIDIA Tegra186 and later SoCs. + The memory controller needs to be programmed with a mapping of memory + client IDs to ARM SMMU stream IDs. + + If this property is absent, the mapping programmed by early firmware + will be used and it is not guaranteed that IOMMU translations will be + enabled for any given device. + $ref: /schemas/types.yaml#/definitions/phandle + required: - compatible - reg @@ -172,13 +186,20 @@ allOf: compatible: contains: enum: - - nvidia,tegra194-smmu - nvidia,tegra186-smmu + - nvidia,tegra194-smmu + - nvidia,tegra234-smmu then: properties: reg: minItems: 1 maxItems: 2 + + # The reference to the memory controller is required to ensure that the + # memory client to stream ID mapping can be done synchronously with the + # IOMMU attachment. + required: + - nvidia,memory-controller else: properties: reg: diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index 97e8c471a5e8..2ae3bbad7f1a 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -76,7 +76,11 @@ properties: - mediatek,mt8167-m4u # generation two - mediatek,mt8173-m4u # generation two - mediatek,mt8183-m4u # generation two + - mediatek,mt8186-iommu-mm # generation two - mediatek,mt8192-m4u # generation two + - mediatek,mt8195-iommu-vdo # generation two + - mediatek,mt8195-iommu-vpp # generation two + - mediatek,mt8195-iommu-infra # generation two - description: mt7623 generation one items: @@ -119,7 +123,9 @@ properties: dt-binding/memory/mt8167-larb-port.h for mt8167, dt-binding/memory/mt8173-larb-port.h for mt8173, dt-binding/memory/mt8183-larb-port.h for mt8183, + dt-binding/memory/mt8186-memory-port.h for mt8186, dt-binding/memory/mt8192-larb-port.h for mt8192. + dt-binding/memory/mt8195-memory-port.h for mt8195. power-domains: maxItems: 1 @@ -128,7 +134,6 @@ required: - compatible - reg - interrupts - - mediatek,larbs - '#iommu-cells' allOf: @@ -140,7 +145,10 @@ allOf: - mediatek,mt2701-m4u - mediatek,mt2712-m4u - mediatek,mt8173-m4u + - mediatek,mt8186-iommu-mm - mediatek,mt8192-m4u + - mediatek,mt8195-iommu-vdo + - mediatek,mt8195-iommu-vpp then: required: @@ -150,12 +158,26 @@ allOf: properties: compatible: enum: + - mediatek,mt8186-iommu-mm - mediatek,mt8192-m4u + - mediatek,mt8195-iommu-vdo + - mediatek,mt8195-iommu-vpp then: required: - power-domains + - if: # The IOMMUs don't have larbs. + not: + properties: + compatible: + contains: + const: mediatek,mt8195-iommu-infra + + then: + required: + - mediatek,larbs + additionalProperties: false examples: @@ -173,13 +195,3 @@ examples: <&larb3>, <&larb4>, <&larb5>; #iommu-cells = <1>; }; - - - | - #include <dt-bindings/memory/mt8173-larb-port.h> - - /* Example for a client device */ - display { - compatible = "mediatek,mt8173-disp"; - iommus = <&iommu M4U_PORT_DISP_OVL0>, - <&iommu M4U_PORT_DISP_RDMA0>; - }; diff --git a/Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml b/Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml index 783c6b37c9f0..672a0beea600 100644 --- a/Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml +++ b/Documentation/devicetree/bindings/iommu/samsung,sysmmu.yaml @@ -86,16 +86,6 @@ examples: - | #include <dt-bindings/clock/exynos5250.h> - gsc_0: scaler@13e00000 { - compatible = "samsung,exynos5-gsc"; - reg = <0x13e00000 0x1000>; - interrupts = <0 85 0>; - power-domains = <&pd_gsc>; - clocks = <&clock CLK_GSCL0>; - clock-names = "gscl"; - iommus = <&sysmmu_gsc0>; - }; - sysmmu_gsc0: iommu@13e80000 { compatible = "samsung,exynos-sysmmu"; reg = <0x13E80000 0x1000>; diff --git a/Documentation/devicetree/bindings/leds/kinetic,ktd2692.yaml b/Documentation/devicetree/bindings/leds/kinetic,ktd2692.yaml new file mode 100644 index 000000000000..bac95a51afa1 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/kinetic,ktd2692.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/kinetic,ktd2692.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: KTD2692 Flash LED Driver from Kinetic Technologies + +maintainers: + - Markuss Broks <markuss.broks@gmail.com> + +description: | + KTD2692 is the ideal power solution for high-power flash LEDs. + It uses ExpressWire single-wire programming for maximum flexibility. + + The ExpressWire interface through CTRL pin can control LED on/off and + enable/disable the IC, Movie(max 1/3 of Flash current) / Flash mode current, + Flash timeout, LVP(low voltage protection). + + Also, When the AUX pin is pulled high while CTRL pin is high, + LED current will be ramped up to the flash-mode current level. + +properties: + compatible: + const: kinetic,ktd2692 + + ctrl-gpios: + maxItems: 1 + description: Specifier of the GPIO connected to CTRL pin. + + aux-gpios: + maxItems: 1 + description: Specifier of the GPIO connected to CTRL pin. + + vin-supply: + description: LED supply (2.7V to 5.5V). + + led: + type: object + $ref: common.yaml# + description: Properties for the LED. + properties: + function: true + color: true + flash-max-timeout-us: + description: Flash LED maximum timeout. + + led-max-microamp: + maximum: 300000 + description: Minimum Threshold for Timer protection + is defined internally (Maximum 300mA). + + flash-max-microamp: + maximum: 300000 + description: Flash LED maximum current + Formula - I(uA) = 15000000 / Rset. + + additionalProperties: false + +required: + - compatible + - ctrl-gpios + - led + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/leds/common.h> + + ktd2692 { + compatible = "kinetic,ktd2692"; + ctrl-gpios = <&gpc0 1 0>; + aux-gpios = <&gpc0 2 0>; + vin-supply = <&vbat>; + + led { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; + flash-max-timeout-us = <250000>; + flash-max-microamp = <150000>; + led-max-microamp = <25000>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml b/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml index 37445c68cdef..f41d021ed677 100644 --- a/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml +++ b/Documentation/devicetree/bindings/leds/leds-class-multicolor.yaml @@ -20,7 +20,7 @@ description: | within this documentation directory. patternProperties: - "^multi-led@([0-9a-f])$": + "^multi-led(@[0-9a-f])?$": type: object description: Represents the LEDs that are to be grouped. properties: diff --git a/Documentation/devicetree/bindings/leds/leds-ktd2692.txt b/Documentation/devicetree/bindings/leds/leds-ktd2692.txt deleted file mode 100644 index 853737452580..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-ktd2692.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Kinetic Technologies - KTD2692 Flash LED Driver - -KTD2692 is the ideal power solution for high-power flash LEDs. -It uses ExpressWire single-wire programming for maximum flexibility. - -The ExpressWire interface through CTRL pin can control LED on/off and -enable/disable the IC, Movie(max 1/3 of Flash current) / Flash mode current, -Flash timeout, LVP(low voltage protection). - -Also, When the AUX pin is pulled high while CTRL pin is high, -LED current will be ramped up to the flash-mode current level. - -Required properties: -- compatible : Should be "kinetic,ktd2692". -- ctrl-gpios : Specifier of the GPIO connected to CTRL pin. -- aux-gpios : Specifier of the GPIO connected to AUX pin. - -Optional properties: -- vin-supply : "vin" LED supply (2.7V to 5.5V). - See Documentation/devicetree/bindings/regulator/regulator.txt - -A discrete LED element connected to the device must be represented by a child -node - See Documentation/devicetree/bindings/leds/common.txt - -Required properties for flash LED child nodes: - See Documentation/devicetree/bindings/leds/common.txt -- led-max-microamp : Minimum Threshold for Timer protection - is defined internally (Maximum 300mA). -- flash-max-microamp : Flash LED maximum current - Formula : I(mA) = 15000 / Rset. -- flash-max-timeout-us : Flash LED maximum timeout. - -Optional properties for flash LED child nodes: -- label : See Documentation/devicetree/bindings/leds/common.txt - -Example: - -ktd2692 { - compatible = "kinetic,ktd2692"; - ctrl-gpios = <&gpc0 1 0>; - aux-gpios = <&gpc0 2 0>; - vin-supply = <&vbat>; - - flash-led { - label = "ktd2692-flash"; - led-max-microamp = <300000>; - flash-max-microamp = <1500000>; - flash-max-timeout-us = <1835000>; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-pwm-multicolor.yaml b/Documentation/devicetree/bindings/leds/leds-pwm-multicolor.yaml new file mode 100644 index 000000000000..6625a528f727 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/leds-pwm-multicolor.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/leds-pwm-multicolor.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Multi-color LEDs connected to PWM + +maintainers: + - Sven Schwermer <sven.schwermer@disruptive-technologies.com> + +description: | + This driver combines several monochrome PWM LEDs into one multi-color + LED using the multicolor LED class. + +properties: + compatible: + const: pwm-leds-multicolor + + multi-led: + type: object + + patternProperties: + "^led-[0-9a-z]+$": + type: object + $ref: common.yaml# + + additionalProperties: false + + properties: + pwms: + maxItems: 1 + + pwm-names: true + + color: true + + required: + - pwms + - color + +required: + - compatible + +allOf: + - $ref: leds-class-multicolor.yaml# + +additionalProperties: false + +examples: + - | + #include <dt-bindings/leds/common.h> + + led-controller { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_INDICATOR; + max-brightness = <65535>; + + led-red { + pwms = <&pwm1 0 1000000>; + color = <LED_COLOR_ID_RED>; + }; + + led-green { + pwms = <&pwm2 0 1000000>; + color = <LED_COLOR_ID_GREEN>; + }; + + led-blue { + pwms = <&pwm3 0 1000000>; + color = <LED_COLOR_ID_BLUE>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml b/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml new file mode 100644 index 000000000000..409a4c7298e1 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/leds-qcom-lpg.yaml @@ -0,0 +1,174 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/leds-qcom-lpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Light Pulse Generator + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: > + The Qualcomm Light Pulse Generator consists of three different hardware blocks; + a ramp generator with lookup table, the light pulse generator and a three + channel current sink. These blocks are found in a wide range of Qualcomm PMICs. + +properties: + compatible: + enum: + - qcom,pm8150b-lpg + - qcom,pm8150l-lpg + - qcom,pm8350c-pwm + - qcom,pm8916-pwm + - qcom,pm8941-lpg + - qcom,pm8994-lpg + - qcom,pmc8180c-lpg + - qcom,pmi8994-lpg + - qcom,pmi8998-lpg + + "#pwm-cells": + const: 2 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + qcom,power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + power-source used to drive the output, as defined in the datasheet. + Should be specified if the TRILED block is present + enum: [0, 1, 3] + + qcom,dtest: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: > + A list of integer pairs, where each pair represent the dtest line the + particular channel should be connected to and the flags denoting how the + value should be outputed, as defined in the datasheet. The number of + pairs should be the same as the number of channels. + items: + items: + - description: dtest line to attach + - description: flags for the attachment + + multi-led: + type: object + $ref: leds-class-multicolor.yaml# + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^led@[0-9a-f]$": + type: object + $ref: common.yaml# + +patternProperties: + "^led@[0-9a-f]$": + type: object + $ref: common.yaml# + + properties: + reg: true + + required: + - reg + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include <dt-bindings/leds/common.h> + + led-controller { + compatible = "qcom,pmi8994-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,power-source = <1>; + + qcom,dtest = <0 0>, + <0 0>, + <0 0>, + <4 1>; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <0>; + default-state = "on"; + }; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + }; + + led@4 { + reg = <4>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <3>; + }; + }; + - | + #include <dt-bindings/leds/common.h> + + led-controller { + compatible = "qcom,pmi8994-lpg"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,power-source = <1>; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_RED>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_BLUE>; + }; + }; + }; + - | + pwm-controller { + compatible = "qcom,pm8916-pwm"; + #pwm-cells = <2>; + }; +... diff --git a/Documentation/devicetree/bindings/leds/regulator-led.yaml b/Documentation/devicetree/bindings/leds/regulator-led.yaml new file mode 100644 index 000000000000..3e020d700c00 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/regulator-led.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/regulator-led.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Device Tree Bindings for Regulator LEDs + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +description: | + Regulator LEDs are powered by a single regulator such that they can + be turned on or off by enabling or disabling the regulator. The available + brightness settings will be inferred from the available voltages on the + regulator, and any constraints on the voltage or current will need to be + specified on the regulator. + +allOf: + - $ref: common.yaml# + +properties: + $nodename: + pattern: '^led.*$' + + compatible: + const: regulator-led + + vled-supply: + description: + The regulator controlling the current to the LED. + + function: true + color: true + linux,default-trigger: true + default-state: true + +required: + - compatible + - vled-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/leds/common.h> + + led-heartbeat { + compatible = "regulator-led"; + vled-supply = <®ulator>; + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_BLUE>; + linux,default-trigger = "heartbeat"; + }; +... diff --git a/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml index fe454a1fba17..72c1d9e82c89 100644 --- a/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/mtk,adsp-mbox.yaml @@ -11,14 +11,15 @@ maintainers: description: | The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC - to ommunicate with ADSP by passing messages through two mailbox channels. + to communicate with ADSP by passing messages through two mailbox channels. The MTK ADSP mailbox IPC also provides the ability for one processor to signal the other processor using interrupts. properties: compatible: - items: - - const: mediatek,mt8195-adsp-mbox + enum: + - mediatek,mt8195-adsp-mbox + - mediatek,mt8186-adsp-mbox "#mbox-cells": const: 0 diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml index 9f7a7296b57f..a3e87516d637 100644 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml @@ -26,6 +26,15 @@ description: | second cell is used to identify the mailbox that the client is going to use. + For shared mailboxes, the first cell composed of two fields: + - bits 15..8: + A bit mask of flags that further specifies the type of shared + mailbox to be used (based on the data size). If no flag is + specified then, 32-bit shared mailbox is used. + - bits 7..0: + Defines the type of the mailbox to be used. This field should be + TEGRA_HSP_MBOX_TYPE_SM for shared mailboxes. + For doorbells, the second cell specifies the index of the doorbell to use. diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml index c57dd423e98c..1994be858940 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -62,23 +62,14 @@ additionalProperties: false examples: - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - #include <dt-bindings/mailbox/qcom-ipcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> - mailbox@408000 { - compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; - reg = <0x408000 0x1000>; - interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - }; - - smp2p-modem { - compatible = "qcom,smp2p"; - interrupts-extended = <&ipcc_mproc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; - - /* Other SMP2P fields */ - }; + mailbox@408000 { + compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; + reg = <0x408000 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml index 8eb4bf52ea27..2c8b47285aa3 100644 --- a/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml @@ -30,15 +30,11 @@ properties: items: - description: rx channel occupied - description: tx channel free - - description: wakeup source - minItems: 2 interrupt-names: items: - const: rx - const: tx - - const: wakeup - minItems: 2 wakeup-source: true @@ -70,10 +66,9 @@ examples: #mbox-cells = <1>; reg = <0x4c001000 0x400>; st,proc-id = <0>; - interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>, - <&intc GIC_SPI 101 IRQ_TYPE_NONE>, - <&aiec 62 1>; - interrupt-names = "rx", "tx", "wakeup"; + interrupts-extended = <&exti 61 1>, + <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; clocks = <&rcc_clk IPCC>; wakeup-source; }; diff --git a/Documentation/devicetree/bindings/mfd/da9063.txt b/Documentation/devicetree/bindings/mfd/da9063.txt index 91b79a21d403..aa8b800cc4ad 100644 --- a/Documentation/devicetree/bindings/mfd/da9063.txt +++ b/Documentation/devicetree/bindings/mfd/da9063.txt @@ -64,10 +64,13 @@ Sub-nodes: and KEY_SLEEP. - watchdog : This node defines settings for the Watchdog timer associated - with the DA9063 and DA9063L. There are currently no entries in this - binding, however compatible = "dlg,da9063-watchdog" should be added - if a node is created. + with the DA9063 and DA9063L. The node should contain the compatible property + with the value "dlg,da9063-watchdog". + Optional watchdog properties: + - dlg,use-sw-pm: Add this property to disable the watchdog during suspend. + Only use this option if you can't use the watchdog automatic suspend + function during a suspend (see register CONTROL_B). Example: diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml index afec0bd2f1de..e25caf8ef9f4 100644 --- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml +++ b/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml @@ -57,7 +57,7 @@ properties: mediatek,rpmsg-name: description: Must be defined if the cros-ec is a rpmsg device for a Mediatek - ARM Cortex M4 Co-processor. Contains the name pf the rpmsg + ARM Cortex M4 Co-processor. Contains the name of the rpmsg device. Used to match the subnode to the rpmsg device announced by the SCP. $ref: "/schemas/types.yaml#/definitions/string" diff --git a/Documentation/devicetree/bindings/mfd/rk808.txt b/Documentation/devicetree/bindings/mfd/rk808.txt deleted file mode 100644 index 23a17a6663ec..000000000000 --- a/Documentation/devicetree/bindings/mfd/rk808.txt +++ /dev/null @@ -1,465 +0,0 @@ -RK8XX Power Management Integrated Circuit - -The rk8xx family current members: -rk805 -rk808 -rk809 -rk817 -rk818 - -Required properties: -- compatible: "rockchip,rk805" -- compatible: "rockchip,rk808" -- compatible: "rockchip,rk809" -- compatible: "rockchip,rk817" -- compatible: "rockchip,rk818" -- reg: I2C slave address -- interrupts: the interrupt outputs of the controller. -- #clock-cells: from common clock binding; shall be set to 1 (multiple clock - outputs). See <dt-bindings/clock/rockchip,rk808.h> for clock IDs. - -Optional properties: -- clock-output-names: From common clock binding to override the - default output clock name -- rockchip,system-power-controller: Telling whether or not this pmic is controlling - the system power. -- wakeup-source: Device can be used as a wakeup source. - -Optional RK805 properties: -- vcc1-supply: The input supply for DCDC_REG1 -- vcc2-supply: The input supply for DCDC_REG2 -- vcc3-supply: The input supply for DCDC_REG3 -- vcc4-supply: The input supply for DCDC_REG4 -- vcc5-supply: The input supply for LDO_REG1 and LDO_REG2 -- vcc6-supply: The input supply for LDO_REG3 - -Optional RK808 properties: -- vcc1-supply: The input supply for DCDC_REG1 -- vcc2-supply: The input supply for DCDC_REG2 -- vcc3-supply: The input supply for DCDC_REG3 -- vcc4-supply: The input supply for DCDC_REG4 -- vcc6-supply: The input supply for LDO_REG1 and LDO_REG2 -- vcc7-supply: The input supply for LDO_REG3 and LDO_REG7 -- vcc8-supply: The input supply for SWITCH_REG1 -- vcc9-supply: The input supply for LDO_REG4 and LDO_REG5 -- vcc10-supply: The input supply for LDO_REG6 -- vcc11-supply: The input supply for LDO_REG8 -- vcc12-supply: The input supply for SWITCH_REG2 -- dvs-gpios: buck1/2 can be controlled by gpio dvs, this is GPIO specifiers - for 2 host gpio's used for dvs. The format of the gpio specifier depends in - the gpio controller. If DVS GPIOs aren't present, voltage changes will happen - very quickly with no slow ramp time. - -Optional shared RK809 and RK817 properties: -- vcc1-supply: The input supply for DCDC_REG1 -- vcc2-supply: The input supply for DCDC_REG2 -- vcc3-supply: The input supply for DCDC_REG3 -- vcc4-supply: The input supply for DCDC_REG4 -- vcc5-supply: The input supply for LDO_REG1, LDO_REG2, LDO_REG3 -- vcc6-supply: The input supply for LDO_REG4, LDO_REG5, LDO_REG6 -- vcc7-supply: The input supply for LDO_REG7, LDO_REG8, LDO_REG9 - -Optional RK809 properties: -- vcc8-supply: The input supply for SWITCH_REG1 -- vcc9-supply: The input supply for DCDC_REG5, SWITCH_REG2 - -Optional RK817 properties: -- clocks: The input clock for the audio codec -- clock-names: The clock name for the codec clock. Should be "mclk". -- #sound-dai-cells: Needed for the interpretation of sound dais. Should be 0. - -- vcc8-supply: The input supply for BOOST -- vcc9-supply: The input supply for OTG_SWITCH -- codec: The child node for the codec to hold additional properties. - If no additional properties are required for the codec, this - node can be omitted. - -- rockchip,mic-in-differential: Telling if the microphone uses differential - mode. Should be under the codec child node. - -Optional RK818 properties: -- vcc1-supply: The input supply for DCDC_REG1 -- vcc2-supply: The input supply for DCDC_REG2 -- vcc3-supply: The input supply for DCDC_REG3 -- vcc4-supply: The input supply for DCDC_REG4 -- boost-supply: The input supply for DCDC_BOOST -- vcc6-supply: The input supply for LDO_REG1 and LDO_REG2 -- vcc7-supply: The input supply for LDO_REG3, LDO_REG5 and LDO_REG7 -- vcc8-supply: The input supply for LDO_REG4, LDO_REG6 and LDO_REG8 -- vcc9-supply: The input supply for LDO_REG9 and SWITCH_REG -- h_5v-supply: The input supply for HDMI_SWITCH -- usb-supply: The input supply for OTG_SWITCH - -Regulators: All the regulators of RK8XX to be instantiated shall be -listed in a child node named 'regulators'. Each regulator is represented -by a child node of the 'regulators' node. - - regulator-name { - /* standard regulator bindings here */ - }; - -Following regulators of the RK805 PMIC regulators are supported. Note that -the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO -number as described in RK805 datasheet. - - - DCDC_REGn - - valid values for n are 1 to 4. - - LDO_REGn - - valid values for n are 1 to 3 - -Following regulators of the RK808 PMIC block are supported. Note that -the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO -number as described in RK808 datasheet. - - - DCDC_REGn - - valid values for n are 1 to 4. - - LDO_REGn - - valid values for n are 1 to 8. - - SWITCH_REGn - - valid values for n are 1 to 2 - -Following regulators of the RK809 and RK817 PMIC blocks are supported. Note that -the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO -number as described in RK809 and RK817 datasheets. - - - DCDC_REGn - - valid values for n are 1 to 5 for RK809. - - valid values for n are 1 to 4 for RK817. - - LDO_REGn - - valid values for n are 1 to 9 for RK809. - - valid values for n are 1 to 9 for RK817. - - SWITCH_REGn - - valid values for n are 1 to 2 for RK809. - - BOOST for RK817 - - OTG_SWITCH for RK817 - -Following regulators of the RK818 PMIC block are supported. Note that -the 'n' in regulator name, as in DCDC_REGn or LDOn, represents the DCDC or LDO -number as described in RK818 datasheet. - - - DCDC_REGn - - valid values for n are 1 to 4. - - LDO_REGn - - valid values for n are 1 to 9. - - SWITCH_REG - - HDMI_SWITCH - - OTG_SWITCH - -It is necessary to configure three pins for both the RK809 and RK817, the three -pins are "gpio_ts" "gpio_gt" "gpio_slp". - The gpio_gt and gpio_ts pins support the gpio function. - The gpio_slp pin is for controlling the pmic states, as below: - - reset - - power down - - sleep - -Standard regulator bindings are used inside regulator subnodes. Check - Documentation/devicetree/bindings/regulator/regulator.txt -for more details - -Example: - rk808: pmic@1b { - compatible = "rockchip,rk808"; - clock-output-names = "xin32k", "rk808-clkout2"; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int &dvs_1 &dvs_2>; - dvs-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>, - <&gpio7 15 GPIO_ACTIVE_HIGH>; - reg = <0x1b>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - - vcc8-supply = <&vcc_18>; - vcc9-supply = <&vcc_io>; - vcc10-supply = <&vcc_io>; - vcc12-supply = <&vcc_io>; - vddio-supply = <&vccio_pmu>; - - regulators { - vdd_cpu: DCDC_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vdd_arm"; - }; - - vdd_gpu: DCDC_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd_gpu"; - }; - - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_ddr"; - }; - - vcc_io: DCDC_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_io"; - }; - - vccio_pmu: LDO_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_pmu"; - }; - - vcc_tp: LDO_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc_tp"; - }; - - vdd_10: LDO_REG3 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd_10"; - }; - - vcc18_lcd: LDO_REG4 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc18_lcd"; - }; - - vccio_sd: LDO_REG5 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - }; - - vdd10_lcd: LDO_REG6 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-name = "vdd10_lcd"; - }; - - vcc_18: LDO_REG7 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_18"; - }; - - vcca_codec: LDO_REG8 { - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcca_codec"; - }; - - vcc_wl: SWITCH_REG1 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_wl"; - }; - - vcc_lcd: SWITCH_REG2 { - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_lcd"; - }; - }; - }; - - rk817: pmic@20 { - compatible = "rockchip,rk817"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>; - clock-output-names = "rk808-clkout1", "xin32k"; - clock-names = "mclk"; - clocks = <&cru SCLK_I2S1_OUT>; - pinctrl-names = "default"; - pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>; - wakeup-source; - #clock-cells = <1>; - #sound-dai-cells = <0>; - - vcc1-supply = <&vccsys>; - vcc2-supply = <&vccsys>; - vcc3-supply = <&vccsys>; - vcc4-supply = <&vccsys>; - vcc5-supply = <&vccsys>; - vcc6-supply = <&vccsys>; - vcc7-supply = <&vccsys>; - - regulators { - vdd_logic: DCDC_REG1 { - regulator-name = "vdd_logic"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1150000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vdd_arm: DCDC_REG2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1350000>; - regulator-ramp-delay = <6001>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <950000>; - }; - }; - - vcc_ddr: DCDC_REG3 { - regulator-name = "vcc_ddr"; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - }; - }; - - vcc_3v3: DCDC_REG4 { - regulator-name = "vcc_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_1v8: LDO_REG2 { - regulator-name = "vcc_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - - vdd_1v0: LDO_REG3 { - regulator-name = "vdd_1v0"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1000000>; - }; - }; - - vcc3v3_pmu: LDO_REG4 { - regulator-name = "vcc3v3_pmu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vccio_sd: LDO_REG5 { - regulator-name = "vccio_sd"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_sd: LDO_REG6 { - regulator-name = "vcc_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - - regulator-state-mem { - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_bl: LDO_REG7 { - regulator-name = "vcc_bl"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - - vcc_lcd: LDO_REG8 { - regulator-name = "vcc_lcd"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <2800000>; - }; - }; - - vcc_cam: LDO_REG9 { - regulator-name = "vcc_cam"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - - regulator-state-mem { - regulator-off-in-suspend; - regulator-suspend-microvolt = <3000000>; - }; - }; - }; - - rk817_codec: codec { - rockchip,mic-in-differential; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/rockchip,rk805.yaml b/Documentation/devicetree/bindings/mfd/rockchip,rk805.yaml new file mode 100644 index 000000000000..4992f71b6fc3 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/rockchip,rk805.yaml @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/rockchip,rk805.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RK805 Power Management Integrated Circuit + +maintainers: + - Chris Zhong <zyw@rock-chips.com> + - Zhang Qing <zhangqing@rock-chips.com> + +description: | + Rockchip RK805 series PMIC. This device consists of an i2c controlled MFD + that includes multiple switchable regulators. + +properties: + compatible: + enum: + - rockchip,rk805 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#clock-cells': + description: + See <dt-bindings/clock/rockchip,rk808.h> for clock IDs. + minimum: 0 + maximum: 1 + + clock-output-names: + description: + From common clock binding to override the default output clock name. + + gpio-controller: true + + '#gpio-cells': + const: 2 + + rockchip,system-power-controller: + type: boolean + description: + Telling whether or not this PMIC is controlling the system power. + + wakeup-source: + type: boolean + description: + Device can be used as a wakeup source. + + vcc1-supply: + description: + The input supply for DCDC_REG1. + + vcc2-supply: + description: + The input supply for DCDC_REG2. + + vcc3-supply: + description: + The input supply for DCDC_REG3. + + vcc4-supply: + description: + The input supply for DCDC_REG4. + + vcc5-supply: + description: + The input supply for LDO_REG1 and LDO_REG2. + + vcc6-supply: + description: + The input supply for LDO_REG3. + + regulators: + type: object + patternProperties: + "^(DCDC_REG[1-4]|LDO_REG[1-3])$": + type: object + $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false + +allOf: + - if: + properties: + '#clock-cells': + const: 0 + + then: + properties: + clock-output-names: + maxItems: 1 + + else: + properties: + clock-output-names: + maxItems: 2 + +required: + - compatible + - reg + - interrupts + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/rockchip.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <RK_PA6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <0>; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_18: LDO_REG1 { + regulator-name = "vdd_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_11: LDO_REG3 { + regulator-name = "vdd_11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/rockchip,rk808.yaml b/Documentation/devicetree/bindings/mfd/rockchip,rk808.yaml new file mode 100644 index 000000000000..f5908fa01a61 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/rockchip,rk808.yaml @@ -0,0 +1,257 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/rockchip,rk808.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RK808 Power Management Integrated Circuit + +maintainers: + - Chris Zhong <zyw@rock-chips.com> + - Zhang Qing <zhangqing@rock-chips.com> + +description: | + Rockchip RK808 series PMIC. This device consists of an i2c controlled MFD + that includes regulators, an RTC, and a power button. + +properties: + compatible: + enum: + - rockchip,rk808 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#clock-cells': + description: + See <dt-bindings/clock/rockchip,rk808.h> for clock IDs. + const: 1 + + clock-output-names: + description: + From common clock binding to override the default output clock name. + maxItems: 2 + + rockchip,system-power-controller: + type: boolean + description: + Telling whether or not this PMIC is controlling the system power. + + wakeup-source: + type: boolean + description: + Device can be used as a wakeup source. + + vcc1-supply: + description: + The input supply for DCDC_REG1. + + vcc2-supply: + description: + The input supply for DCDC_REG2. + + vcc3-supply: + description: + The input supply for DCDC_REG3. + + vcc4-supply: + description: + The input supply for DCDC_REG4. + + vcc6-supply: + description: + The input supply for LDO_REG1 and LDO_REG2. + + vcc7-supply: + description: + The input supply for LDO_REG3 and LDO_REG7. + + vcc8-supply: + description: + The input supply for SWITCH_REG1. + + vcc9-supply: + description: + The input supply for LDO_REG4 and LDO_REG5. + + vcc10-supply: + description: + The input supply for LDO_REG6. + + vcc11-supply: + description: + The input supply for LDO_REG8. + + vcc12-supply: + description: + The input supply for SWITCH_REG2. + + vddio-supply: + description: + The input supply for digital IO. + + dvs-gpios: + description: | + buck1/2 can be controlled by gpio dvs, this is GPIO specifiers for + 2 host gpio's used for dvs. The format of the gpio specifier + depends in the gpio controller. If DVS GPIOs aren't present, + voltage changes will happen very quickly with no slow ramp time. + maxItems: 2 + + regulators: + type: object + patternProperties: + "^(DCDC_REG[1-4]|LDO_REG[1-8]|SWITCH_REG[1-2])$": + type: object + $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/rockchip.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + clock-output-names = "xin32k", "rk808-clkout2"; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &dvs_1 &dvs_2>; + dvs-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>, + <&gpio7 15 GPIO_ACTIVE_HIGH>; + reg = <0x1b>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + + vcc8-supply = <&vcc_18>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc_io>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vccio_pmu>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vdd_arm"; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + }; + + vccio_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_pmu"; + }; + + vcc_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_tp"; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + }; + + vcc18_lcd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + }; + + vcca_codec: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_codec"; + }; + + vcc_wl: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_wl"; + }; + + vcc_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lcd"; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/rockchip,rk809.yaml b/Documentation/devicetree/bindings/mfd/rockchip,rk809.yaml new file mode 100644 index 000000000000..7fb849ac74a7 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/rockchip,rk809.yaml @@ -0,0 +1,284 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RK809 Power Management Integrated Circuit + +maintainers: + - Chris Zhong <zyw@rock-chips.com> + - Zhang Qing <zhangqing@rock-chips.com> + +description: | + Rockchip RK809 series PMIC. This device consists of an i2c controlled MFD + that includes regulators, an RTC, and power button. + +properties: + compatible: + enum: + - rockchip,rk809 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#clock-cells': + description: | + See <dt-bindings/clock/rockchip,rk808.h> for clock IDs. + minimum: 0 + maximum: 1 + + clock-output-names: + description: + From common clock binding to override the default output clock name. + + rockchip,system-power-controller: + type: boolean + description: + Telling whether or not this PMIC is controlling the system power. + + wakeup-source: + type: boolean + description: + Device can be used as a wakeup source. + + vcc1-supply: + description: + The input supply for DCDC_REG1. + + vcc2-supply: + description: + The input supply for DCDC_REG2. + + vcc3-supply: + description: + The input supply for DCDC_REG3. + + vcc4-supply: + description: + The input supply for DCDC_REG4. + + vcc5-supply: + description: + The input supply for LDO_REG1, LDO_REG2, and LDO_REG3. + + vcc6-supply: + description: + The input supply for LDO_REG4, LDO_REG5, and LDO_REG6. + + vcc7-supply: + description: + The input supply for LDO_REG7, LDO_REG8, and LDO_REG9. + + vcc8-supply: + description: + The input supply for SWITCH_REG1. + + vcc9-supply: + description: + The input supply for DCDC_REG5 and SWITCH_REG2. + + regulators: + type: object + patternProperties: + "^(LDO_REG[1-9]|DCDC_REG[1-5]|SWITCH_REG[1-2])$": + type: object + $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false + +allOf: + - if: + properties: + '#clock-cells': + const: 0 + + then: + properties: + clock-output-names: + maxItems: 1 + + else: + properties: + clock-output-names: + maxItems: 2 + +required: + - compatible + - reg + - interrupts + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/rockchip.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + interrupt-parent = <&gpio3>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l_pin>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sysin>; + vcc2-supply = <&vcc_sysin>; + vcc3-supply = <&vcc_sysin>; + vcc4-supply = <&vcc_sysin>; + vcc6-supply = <&vcc_sysin>; + vcc7-supply = <&vcc_sysin>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sysin>; + vcc10-supply = <&vcc_sysin>; + vcc11-supply = <&vcc_sysin>; + vcc12-supply = <&vcc3v3_sys>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: vcc_wl: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_pmupll: LDO_REG3 { + regulator-name = "vcc1v8_pmupll"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/rockchip,rk817.yaml b/Documentation/devicetree/bindings/mfd/rockchip,rk817.yaml new file mode 100644 index 000000000000..bfc1720adc43 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/rockchip,rk817.yaml @@ -0,0 +1,330 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/rockchip,rk817.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RK817 Power Management Integrated Circuit + +maintainers: + - Chris Zhong <zyw@rock-chips.com> + - Zhang Qing <zhangqing@rock-chips.com> + +description: | + Rockchip RK817 series PMIC. This device consists of an i2c controlled MFD + that includes regulators, an RTC, a power button, an audio codec, and a + battery charger manager. + +properties: + compatible: + enum: + - rockchip,rk817 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#clock-cells': + description: + See <dt-bindings/clock/rockchip,rk808.h> for clock IDs. + minimum: 0 + maximum: 1 + + clock-output-names: + description: + From common clock binding to override the default output clock name. + + rockchip,system-power-controller: + type: boolean + description: + Telling whether or not this PMIC is controlling the system power. + + wakeup-source: + type: boolean + description: + Device can be used as a wakeup source. + + vcc1-supply: + description: + The input supply for DCDC_REG1. + + vcc2-supply: + description: + The input supply for DCDC_REG2. + + vcc3-supply: + description: + The input supply for DCDC_REG3. + + vcc4-supply: + description: + The input supply for DCDC_REG4. + + vcc5-supply: + description: + The input supply for LDO_REG1, LDO_REG2, and LDO_REG3. + + vcc6-supply: + description: + The input supply for LDO_REG4, LDO_REG5, and LDO_REG6. + + vcc7-supply: + description: + The input supply for LDO_REG7, LDO_REG8, and LDO_REG9. + + vcc8-supply: + description: + The input supply for BOOST. + + vcc9-supply: + description: + The input supply for OTG_SWITCH. + + regulators: + type: object + patternProperties: + "^(LDO_REG[1-9]|DCDC_REG[1-4]|BOOST|OTG_SWITCH)$": + type: object + $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false + + clocks: + description: + The input clock for the audio codec. + + clock-names: + description: + The clock name for the codec clock. + items: + - const: mclk + + '#sound-dai-cells': + description: + Needed for the interpretation of sound dais. + const: 0 + + codec: + description: | + The child node for the codec to hold additional properties. If no + additional properties are required for the codec, this node can be + omitted. + type: object + properties: + rockchip,mic-in-differential: + type: boolean + description: + Describes if the microphone uses differential mode. + +allOf: + - if: + properties: + '#clock-cells': + const: 0 + + then: + properties: + clock-output-names: + maxItems: 1 + + else: + properties: + clock-output-names: + maxItems: 2 + +required: + - compatible + - reg + - interrupts + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/px30-cru.h> + #include <dt-bindings/pinctrl/rockchip.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>; + clock-output-names = "rk808-clkout1", "xin32k"; + clock-names = "mclk"; + clocks = <&cru SCLK_I2S1_OUT>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>; + wakeup-source; + #clock-cells = <1>; + #sound-dai-cells = <0>; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vccsys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v3_pmu: LDO_REG4 { + regulator-name = "vcc3v3_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_bl: LDO_REG7 { + regulator-name = "vcc_bl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_lcd: LDO_REG8 { + regulator-name = "vcc_lcd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc_cam: LDO_REG9 { + regulator-name = "vcc_cam"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + }; + + rk817_codec: codec { + rockchip,mic-in-differential; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/rockchip,rk818.yaml b/Documentation/devicetree/bindings/mfd/rockchip,rk818.yaml new file mode 100644 index 000000000000..b57c4b005cf4 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/rockchip,rk818.yaml @@ -0,0 +1,282 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/rockchip,rk818.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RK818 Power Management Integrated Circuit + +maintainers: + - Chris Zhong <zyw@rock-chips.com> + - Zhang Qing <zhangqing@rock-chips.com> + +description: | + Rockchip RK818 series PMIC. This device consists of an i2c controlled MFD + that includes regulators, an RTC, and a power button. + +properties: + compatible: + enum: + - rockchip,rk818 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#clock-cells': + description: | + See <dt-bindings/clock/rockchip,rk808.h> for clock IDs. + const: 1 + + clock-output-names: + description: + From common clock binding to override the default output clock name. + maxItems: 2 + + rockchip,system-power-controller: + type: boolean + description: + Telling whether or not this PMIC is controlling the system power. + + wakeup-source: + type: boolean + description: + Device can be used as a wakeup source. + + vcc1-supply: + description: + The input supply for DCDC_REG1. + + vcc2-supply: + description: + The input supply for DCDC_REG2. + + vcc3-supply: + description: + The input supply for DCDC_REG3. + + vcc4-supply: + description: + The input supply for DCDC_REG4. + + boost-supply: + description: + The input supply for DCDC_BOOST + + vcc6-supply: + description: + The input supply for LDO_REG1 and LDO_REG2. + + vcc7-supply: + description: + The input supply for LDO_REG3, LDO_REG5, and LDO_REG7. + + vcc8-supply: + description: + The input supply for LDO_REG4, LDO_REG6, and LDO_REG8. + + vcc9-supply: + description: + The input supply for LDO_REG9 and SWITCH_REG. + + vddio-supply: + description: + The input supply for digital IO. + + h_5v-supply: + description: + The input supply for HDMI_SWITCH. + + usb-supply: + description: + The input supply for OTG_SWITCH. + + regulators: + type: object + patternProperties: + "^(DCDC_REG[1-4]|DCDC_BOOST|LDO_REG[1-9]|SWITCH_REG|HDMI_SWITCH|OTG_SWITCH)$": + type: object + $ref: ../regulator/regulator.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/px30-cru.h> + #include <dt-bindings/pinctrl/rockchip.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rk818: pmic@1c { + compatible = "rockchip,rk818"; + reg = <0x1c>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + + vcc1-supply = <&vdd_sys>; + vcc2-supply = <&vdd_sys>; + vcc3-supply = <&vdd_sys>; + vcc4-supply = <&vdd_sys>; + boost-supply = <&vdd_in_otg_out>; + vcc6-supply = <&vdd_sys>; + vcc7-supply = <&vdd_misc_1v8>; + vcc8-supply = <&vdd_misc_1v8>; + vcc9-supply = <&vdd_3v3_io>; + vddio-supply = <&vdd_3v3_io>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_3v3_io: DCDC_REG4 { + regulator-name = "vdd_3v3_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_sys: DCDC_BOOST { + regulator-name = "vdd_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + + vdd_sd: SWITCH_REG { + regulator-name = "vdd_sd"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_eth_2v5: LDO_REG2 { + regulator-name = "vdd_eth_2v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2500000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_1v8_lcd_ldo: LDO_REG4 { + regulator-name = "vdd_1v8_lcd_ldo"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0_lcd: LDO_REG6 { + regulator-name = "vdd_1v0_lcd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_1v8_ldo: LDO_REG7 { + regulator-name = "vdd_1v8_ldo"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_io_sd: LDO_REG9 { + regulator-name = "vdd_io_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.yaml b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.yaml index f7bb67d10eff..b97b06848729 100644 --- a/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.yaml +++ b/Documentation/devicetree/bindings/mfd/samsung,exynos5433-lpass.yaml @@ -79,8 +79,8 @@ examples: clocks = <&cmu_aud CLK_ACLK_DMAC>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; + dma-channels = <8>; + dma-requests = <32>; power-domains = <&pd_aud>; }; diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 13baa452cc9d..fb784045013f 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -100,12 +100,4 @@ examples: compatible = "allwinner,sun8i-h3-system-controller", "syscon"; reg = <0x01c00000 0x1000>; }; - - - | - gpr: iomuxc-gpr@20e0000 { - compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; - reg = <0x020e0000 0x38>; - hwlocks = <&hwlock1 1>; - }; - ... diff --git a/Documentation/devicetree/bindings/mfd/wlf,arizona.yaml b/Documentation/devicetree/bindings/mfd/wlf,arizona.yaml index 9e762d474218..ea3337dafaf5 100644 --- a/Documentation/devicetree/bindings/mfd/wlf,arizona.yaml +++ b/Documentation/devicetree/bindings/mfd/wlf,arizona.yaml @@ -14,6 +14,7 @@ description: | range of analogue I/O. allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml - $ref: /schemas/sound/wlf,arizona.yaml# - $ref: /schemas/regulator/wlf,arizona.yaml# - $ref: /schemas/extcon/wlf,arizona.yaml# diff --git a/Documentation/devicetree/bindings/mux/reg-mux.yaml b/Documentation/devicetree/bindings/mux/reg-mux.yaml index 3b030b8fb47c..dfd9ea582bb7 100644 --- a/Documentation/devicetree/bindings/mux/reg-mux.yaml +++ b/Documentation/devicetree/bindings/mux/reg-mux.yaml @@ -100,7 +100,6 @@ examples: #include <dt-bindings/mux/mux.h> syscon@1000 { - compatible = "fsl,imx7d-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; reg = <0x1000 0x100>; mux2: mux-controller { diff --git a/Documentation/devicetree/bindings/net/adi,adin.yaml b/Documentation/devicetree/bindings/net/adi,adin.yaml index 77750df0c2c4..929cf8c0b0fd 100644 --- a/Documentation/devicetree/bindings/net/adi,adin.yaml +++ b/Documentation/devicetree/bindings/net/adi,adin.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices ADIN1200/ADIN1300 PHY maintainers: - - Alexandru Ardelean <alexandru.ardelean@analog.com> + - Alexandru Tachici <alexandru.tachici@analog.com> description: | Bindings for Analog Devices Industrial Ethernet PHYs @@ -37,7 +37,8 @@ properties: default: 8 adi,phy-output-clock: - description: Select clock output on GP_CLK pin. Two clocks are available: + description: | + Select clock output on GP_CLK pin. Two clocks are available: A 25MHz reference and a free-running 125MHz. The phy can alternatively automatically switch between the reference and the 125MHz clocks based on its internal state. diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml index 8c2e9ac5f68d..30f7b596d609 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml @@ -17,10 +17,10 @@ description: | the CPU frequencies subset and voltage value of each OPP varies based on the silicon variant in use. Qualcomm Technologies, Inc. Process Voltage Scaling Tables - defines the voltage and frequency value based on the msm-id in SMEM - and speedbin blown in the efuse combination. - The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC - to provide the OPP framework with required information (existing HW bitmap). + defines the voltage and frequency value based on the speedbin blown in + the efuse combination. + The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide + the OPP framework with required information (existing HW bitmap). This is used to determine the voltage and frequency value for each OPP of operating-points-v2 table when it is parsed by the OPP framework. @@ -50,15 +50,11 @@ patternProperties: description: | A single 32 bit bitmap value, representing compatible HW. Bitmap: - 0: MSM8996 V3, speedbin 0 - 1: MSM8996 V3, speedbin 1 - 2: MSM8996 V3, speedbin 2 - 3: unused - 4: MSM8996 SG, speedbin 0 - 5: MSM8996 SG, speedbin 1 - 6: MSM8996 SG, speedbin 2 - 7-31: unused - maximum: 0x77 + 0: MSM8996, speedbin 0 + 1: MSM8996, speedbin 1 + 2: MSM8996, speedbin 2 + 3-31: unused + maximum: 0x7 clock-latency-ns: true @@ -184,19 +180,19 @@ examples: opp-307200000 { opp-hz = /bits/ 64 <307200000>; opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; - opp-1593600000 { - opp-hz = /bits/ 64 <1593600000>; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x71>; + opp-supported-hw = <0x5>; clock-latency-ns = <200000>; }; - opp-2188800000 { - opp-hz = /bits/ 64 <2188800000>; + opp-1593600000 { + opp-hz = /bits/ 64 <1593600000>; opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x10>; + opp-supported-hw = <0x1>; clock-latency-ns = <200000>; }; }; @@ -209,25 +205,25 @@ examples: opp-307200000 { opp-hz = /bits/ 64 <307200000>; opp-microvolt = <905000 905000 1140000>; - opp-supported-hw = <0x77>; + opp-supported-hw = <0x7>; clock-latency-ns = <200000>; }; - opp-1593600000 { - opp-hz = /bits/ 64 <1593600000>; + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x70>; + opp-supported-hw = <0x6>; clock-latency-ns = <200000>; }; - opp-2150400000 { - opp-hz = /bits/ 64 <2150400000>; + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x31>; + opp-supported-hw = <0x4>; clock-latency-ns = <200000>; }; - opp-2342400000 { - opp-hz = /bits/ 64 <2342400000>; + opp-2150400000 { + opp-hz = /bits/ 64 <2150400000>; opp-microvolt = <1140000 905000 1140000>; - opp-supported-hw = <0x10>; + opp-supported-hw = <0x1>; clock-latency-ns = <200000>; }; }; diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index f36efa73a470..ee8a4791a78b 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -23,6 +23,7 @@ Required properties: "fsl,ls1012a-pcie" "fsl,ls1028a-pcie" EP mode: + "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep" "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep" "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep" @@ -30,39 +31,49 @@ Required properties: - reg: base addresses and lengths of the PCIe controller register blocks. - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. -- interrupt-names: Must include the following entries: - "intr": The interrupt that is asserted for controller interrupts +- interrupt-names: It could include the following entries: + "aer": Used for interrupt line which reports AER events when + non MSI/MSI-X/INTx mode is used + "pme": Used for interrupt line which reports PME events when + non MSI/MSI-X/INTx mode is used + "intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) + which has a single interrupt line for miscellaneous controller + events(could include AER and PME events). - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node - The second entry must be '0' or '1' based on physical PCIe controller index. + The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers - dma-coherent: Indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. +Optional properties: +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify + this property. + Example: - pcie@3400000 { - compatible = "fsl,ls1021a-pcie"; - reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; - fsl,pcie-scfg = <&scfg 0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000 /* prefetchable memory */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - }; + pcie@3400000 { + compatible = "fsl,ls1088a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-viewport = <256>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt deleted file mode 100644 index 0adb56d5645e..000000000000 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ /dev/null @@ -1,397 +0,0 @@ -* Qualcomm PCI express root complex - -- compatible: - Usage: required - Value type: <stringlist> - Definition: Value should contain - - "qcom,pcie-ipq8064" for ipq8064 - - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065 - - "qcom,pcie-apq8064" for apq8064 - - "qcom,pcie-apq8084" for apq8084 - - "qcom,pcie-msm8996" for msm8996 or apq8096 - - "qcom,pcie-ipq4019" for ipq4019 - - "qcom,pcie-ipq8074" for ipq8074 - - "qcom,pcie-qcs404" for qcs404 - - "qcom,pcie-sc8180x" for sc8180x - - "qcom,pcie-sdm845" for sdm845 - - "qcom,pcie-sm8250" for sm8250 - - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450 - - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450 - - "qcom,pcie-ipq6018" for ipq6018 - -- reg: - Usage: required - Value type: <prop-encoded-array> - Definition: Register ranges as listed in the reg-names property - -- reg-names: - Usage: required - Value type: <stringlist> - Definition: Must include the following entries - - "parf" Qualcomm specific registers - - "dbi" DesignWare PCIe registers - - "elbi" External local bus interface registers - - "config" PCIe configuration space - - "atu" ATU address space (optional) - -- device_type: - Usage: required - Value type: <string> - Definition: Should be "pci". As specified in snps,dw-pcie.yaml - -- #address-cells: - Usage: required - Value type: <u32> - Definition: Should be 3. As specified in snps,dw-pcie.yaml - -- #size-cells: - Usage: required - Value type: <u32> - Definition: Should be 2. As specified in snps,dw-pcie.yaml - -- ranges: - Usage: required - Value type: <prop-encoded-array> - Definition: As specified in snps,dw-pcie.yaml - -- interrupts: - Usage: required - Value type: <prop-encoded-array> - Definition: MSI interrupt - -- interrupt-names: - Usage: required - Value type: <stringlist> - Definition: Should contain "msi" - -- #interrupt-cells: - Usage: required - Value type: <u32> - Definition: Should be 1. As specified in snps,dw-pcie.yaml - -- interrupt-map-mask: - Usage: required - Value type: <prop-encoded-array> - Definition: As specified in snps,dw-pcie.yaml - -- interrupt-map: - Usage: required - Value type: <prop-encoded-array> - Definition: As specified in snps,dw-pcie.yaml - -- clocks: - Usage: required - Value type: <prop-encoded-array> - Definition: List of phandle and clock specifier pairs as listed - in clock-names property - -- clock-names: - Usage: required - Value type: <stringlist> - Definition: Should contain the following entries - - "iface" Configuration AHB clock - -- clock-names: - Usage: required for ipq/apq8064 - Value type: <stringlist> - Definition: Should contain the following entries - - "core" Clocks the pcie hw block - - "phy" Clocks the pcie PHY block - - "aux" Clocks the pcie AUX block - - "ref" Clocks the pcie ref block -- clock-names: - Usage: required for apq8084/ipq4019 - Value type: <stringlist> - Definition: Should contain the following entries - - "aux" Auxiliary (AUX) clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - -- clock-names: - Usage: required for msm8996/apq8096 - Value type: <stringlist> - Definition: Should contain the following entries - - "pipe" Pipe Clock driving internal logic - - "aux" Auxiliary (AUX) clock - - "cfg" Configuration clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - -- clock-names: - Usage: required for ipq8074 - Value type: <stringlist> - Definition: Should contain the following entries - - "iface" PCIe to SysNOC BIU clock - - "axi_m" AXI Master clock - - "axi_s" AXI Slave clock - - "ahb" AHB clock - - "aux" Auxiliary clock - -- clock-names: - Usage: required for ipq6018 - Value type: <stringlist> - Definition: Should contain the following entries - - "iface" PCIe to SysNOC BIU clock - - "axi_m" AXI Master clock - - "axi_s" AXI Slave clock - - "axi_bridge" AXI bridge clock - - "rchng" - -- clock-names: - Usage: required for qcs404 - Value type: <stringlist> - Definition: Should contain the following entries - - "iface" AHB clock - - "aux" Auxiliary clock - - "master_bus" AXI Master clock - - "slave_bus" AXI Slave clock - -- clock-names: - Usage: required for sdm845 - Value type: <stringlist> - Definition: Should contain the following entries - - "aux" Auxiliary clock - - "cfg" Configuration clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - - "slave_q2a" Slave Q2A clock - - "tbu" PCIe TBU clock - - "pipe" PIPE clock - -- clock-names: - Usage: required for sc8180x and sm8250 - Value type: <stringlist> - Definition: Should contain the following entries - - "aux" Auxiliary clock - - "cfg" Configuration clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - - "slave_q2a" Slave Q2A clock - - "tbu" PCIe TBU clock - - "ddrss_sf_tbu" PCIe SF TBU clock - - "pipe" PIPE clock - -- clock-names: - Usage: required for sm8450-pcie0 and sm8450-pcie1 - Value type: <stringlist> - Definition: Should contain the following entries - - "aux" Auxiliary clock - - "cfg" Configuration clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - - "slave_q2a" Slave Q2A clock - - "tbu" PCIe TBU clock - - "ddrss_sf_tbu" PCIe SF TBU clock - - "pipe" PIPE clock - - "pipe_mux" PIPE MUX - - "phy_pipe" PIPE output clock - - "ref" REFERENCE clock - - "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0 - - "aggre1" Aggre NoC PCIe1 AXI clock - -- resets: - Usage: required - Value type: <prop-encoded-array> - Definition: List of phandle and reset specifier pairs as listed - in reset-names property - -- reset-names: - Usage: required for ipq/apq8064 - Value type: <stringlist> - Definition: Should contain the following entries - - "axi" AXI reset - - "ahb" AHB reset - - "por" POR reset - - "pci" PCI reset - - "phy" PHY reset - -- reset-names: - Usage: required for apq8084 - Value type: <stringlist> - Definition: Should contain the following entries - - "core" Core reset - -- reset-names: - Usage: required for ipq/apq8064 - Value type: <stringlist> - Definition: Should contain the following entries - - "axi_m" AXI master reset - - "axi_s" AXI slave reset - - "pipe" PIPE reset - - "axi_m_vmid" VMID reset - - "axi_s_xpu" XPU reset - - "parf" PARF reset - - "phy" PHY reset - - "axi_m_sticky" AXI sticky reset - - "pipe_sticky" PIPE sticky reset - - "pwr" PWR reset - - "ahb" AHB reset - - "phy_ahb" PHY AHB reset - - "ext" EXT reset - -- reset-names: - Usage: required for ipq8074 - Value type: <stringlist> - Definition: Should contain the following entries - - "pipe" PIPE reset - - "sleep" Sleep reset - - "sticky" Core Sticky reset - - "axi_m" AXI Master reset - - "axi_s" AXI Slave reset - - "ahb" AHB Reset - - "axi_m_sticky" AXI Master Sticky reset - -- reset-names: - Usage: required for ipq6018 - Value type: <stringlist> - Definition: Should contain the following entries - - "pipe" PIPE reset - - "sleep" Sleep reset - - "sticky" Core Sticky reset - - "axi_m" AXI Master reset - - "axi_s" AXI Slave reset - - "ahb" AHB Reset - - "axi_m_sticky" AXI Master Sticky reset - - "axi_s_sticky" AXI Slave Sticky reset - -- reset-names: - Usage: required for qcs404 - Value type: <stringlist> - Definition: Should contain the following entries - - "axi_m" AXI Master reset - - "axi_s" AXI Slave reset - - "axi_m_sticky" AXI Master Sticky reset - - "pipe_sticky" PIPE sticky reset - - "pwr" PWR reset - - "ahb" AHB reset - -- reset-names: - Usage: required for sc8180x, sdm845, sm8250 and sm8450 - Value type: <stringlist> - Definition: Should contain the following entries - - "pci" PCIe core reset - -- power-domains: - Usage: required for apq8084 and msm8996/apq8096 - Value type: <prop-encoded-array> - Definition: A phandle and power domain specifier pair to the - power domain which is responsible for collapsing - and restoring power to the peripheral - -- vdda-supply: - Usage: required - Value type: <phandle> - Definition: A phandle to the core analog power supply - -- vdda_phy-supply: - Usage: required for ipq/apq8064 - Value type: <phandle> - Definition: A phandle to the analog power supply for PHY - -- vdda_refclk-supply: - Usage: required for ipq/apq8064 - Value type: <phandle> - Definition: A phandle to the analog power supply for IC which generates - reference clock -- vddpe-3v3-supply: - Usage: optional - Value type: <phandle> - Definition: A phandle to the PCIe endpoint power supply - -- phys: - Usage: required for apq8084 and qcs404 - Value type: <phandle> - Definition: List of phandle(s) as listed in phy-names property - -- phy-names: - Usage: required for apq8084 and qcs404 - Value type: <stringlist> - Definition: Should contain "pciephy" - -- <name>-gpios: - Usage: optional - Value type: <prop-encoded-array> - Definition: List of phandle and GPIO specifier pairs. Should contain - - "perst-gpios" PCIe endpoint reset signal line - - "wake-gpios" PCIe endpoint wake signal line - -* Example for ipq/apq8064 - pcie@1b500000 { - compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie"; - reg = <0x1b500000 0x1000 - 0x1b502000 0x80 - 0x1b600000 0x100 - 0x0ff00000 0x100000>; - reg-names = "dbi", "elbi", "parf", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ - 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */ - interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc PCIE_A_CLK>, - <&gcc PCIE_H_CLK>, - <&gcc PCIE_PHY_CLK>, - <&gcc PCIE_AUX_CLK>, - <&gcc PCIE_ALT_REF_CLK>; - clock-names = "core", "iface", "phy", "aux", "ref"; - resets = <&gcc PCIE_ACLK_RESET>, - <&gcc PCIE_HCLK_RESET>, - <&gcc PCIE_POR_RESET>, - <&gcc PCIE_PCI_RESET>, - <&gcc PCIE_PHY_RESET>, - <&gcc PCIE_EXT_RESET>; - reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; - pinctrl-0 = <&pcie_pins_default>; - pinctrl-names = "default"; - }; - -* Example for apq8084 - pcie0@fc520000 { - compatible = "qcom,pcie-apq8084", "snps,dw-pcie"; - reg = <0xfc520000 0x2000>, - <0xff000000 0x1000>, - <0xff001000 0x1000>, - <0xff002000 0x2000>; - reg-names = "parf", "dbi", "elbi", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */ - 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */ - interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>; - clock-names = "iface", "master_bus", "slave_bus", "aux"; - resets = <&gcc GCC_PCIE_0_BCR>; - reset-names = "core"; - power-domains = <&gcc PCIE0_GDSC>; - vdda-supply = <&pma8084_l3>; - phys = <&pciephy0>; - phy-names = "pciephy"; - perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_pins_default>; - pinctrl-names = "default"; - }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml new file mode 100644 index 000000000000..0b69b12b849e --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -0,0 +1,714 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PCI express root complex + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + - Stanimir Varbanov <svarbanov@mm-sol.com> + +description: | + Qualcomm PCIe root complex controller is bansed on the Synopsys DesignWare + PCIe IP. + +properties: + compatible: + enum: + - qcom,pcie-ipq8064 + - qcom,pcie-ipq8064-v2 + - qcom,pcie-apq8064 + - qcom,pcie-apq8084 + - qcom,pcie-msm8996 + - qcom,pcie-ipq4019 + - qcom,pcie-ipq8074 + - qcom,pcie-qcs404 + - qcom,pcie-sc7280 + - qcom,pcie-sc8180x + - qcom,pcie-sdm845 + - qcom,pcie-sm8150 + - qcom,pcie-sm8250 + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + - qcom,pcie-ipq6018 + + reg: + minItems: 4 + maxItems: 5 + + reg-names: + minItems: 4 + maxItems: 5 + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: msi + + # Common definitions for clocks, clock-names and reset. + # Platform constraints are described later. + clocks: + minItems: 3 + maxItems: 12 + + clock-names: + minItems: 3 + maxItems: 12 + + resets: + minItems: 1 + maxItems: 12 + + resets-names: + minItems: 1 + maxItems: 12 + + vdda-supply: + description: A phandle to the core analog power supply + + vdda_phy-supply: + description: A phandle to the core analog power supply for PHY + + vdda_refclk-supply: + description: A phandle to the core analog power supply for IC which generates reference clock + + vddpe-3v3-supply: + description: A phandle to the PCIe endpoint power supply + + phys: + maxItems: 1 + + phy-names: + items: + - const: pciephy + + power-domains: + maxItems: 1 + + perst-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + wake-gpios: + description: GPIO controlled connection to WAKE# signal + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + - clocks + - clock-names + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-apq8064 + - qcom,pcie-ipq4019 + - qcom,pcie-ipq8064 + - qcom,pcie-ipq8064v2 + - qcom,pcie-ipq8074 + - qcom,pcie-qcs404 + then: + properties: + reg: + minItems: 4 + maxItems: 4 + reg-names: + items: + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: parf # Qualcomm specific registers + - const: config # PCIe configuration space + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq6018 + then: + properties: + reg: + minItems: 5 + maxItems: 5 + reg-names: + items: + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: parf # Qualcomm specific registers + - const: config # PCIe configuration space + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-apq8084 + - qcom,pcie-msm8996 + - qcom,pcie-sdm845 + then: + properties: + reg: + minItems: 4 + maxItems: 4 + reg-names: + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: config # PCIe configuration space + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc7280 + - qcom,pcie-sc8180x + - qcom,pcie-sm8250 + - qcom,pcie-sm8450-pcie0 + - qcom,pcie-sm8450-pcie1 + then: + properties: + reg: + minItems: 5 + maxItems: 5 + reg-names: + items: + - const: parf # Qualcomm specific registers + - const: dbi # DesignWare PCIe registers + - const: elbi # External local bus interface registers + - const: atu # ATU address space + - const: config # PCIe configuration space + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-apq8064 + - qcom,pcie-ipq8064 + - qcom,pcie-ipq8064v2 + then: + properties: + clocks: + minItems: 3 + maxItems: 5 + clock-names: + minItems: 3 + items: + - const: core # Clocks the pcie hw block + - const: iface # Configuration AHB clock + - const: phy # Clocks the pcie PHY block + - const: aux # Clocks the pcie AUX block, not on apq8064 + - const: ref # Clocks the pcie ref block, not on apq8064 + resets: + minItems: 5 + maxItems: 6 + reset-names: + minItems: 5 + items: + - const: axi # AXI reset + - const: ahb # AHB reset + - const: por # POR reset + - const: pci # PCI reset + - const: phy # PHY reset + - const: ext # EXT reset, not on apq8064 + required: + - vdda-supply + - vdda_phy-supply + - vdda_refclk-supply + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-apq8084 + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: iface # Configuration AHB clock + - const: master_bus # Master AXI clock + - const: slave_bus # Slave AXI clock + - const: aux # Auxiliary (AUX) clock + resets: + maxItems: 1 + reset-names: + items: + - const: core # Core reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq4019 + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: aux # Auxiliary (AUX) clock + - const: master_bus # Master AXI clock + - const: slave_bus # Slave AXI clock + resets: + minItems: 12 + maxItems: 12 + reset-names: + items: + - const: axi_m # AXI master reset + - const: axi_s # AXI slave reset + - const: pipe # PIPE reset + - const: axi_m_vmid # VMID reset + - const: axi_s_xpu # XPU reset + - const: parf # PARF reset + - const: phy # PHY reset + - const: axi_m_sticky # AXI sticky reset + - const: pipe_sticky # PIPE sticky reset + - const: pwr # PWR reset + - const: ahb # AHB reset + - const: phy_ahb # PHY AHB reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-msm8996 + then: + oneOf: + - properties: + clock-names: + items: + - const: pipe # Pipe Clock driving internal logic + - const: aux # Auxiliary (AUX) clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - properties: + clock-names: + items: + - const: pipe # Pipe Clock driving internal logic + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: cfg # Configuration clock + - const: aux # Auxiliary (AUX) clock + properties: + clocks: + minItems: 5 + maxItems: 5 + resets: false + reset-names: false + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq8074 + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + clock-names: + items: + - const: iface # PCIe to SysNOC BIU clock + - const: axi_m # AXI Master clock + - const: axi_s # AXI Slave clock + - const: ahb # AHB clock + - const: aux # Auxiliary clock + resets: + minItems: 7 + maxItems: 7 + reset-names: + items: + - const: pipe # PIPE reset + - const: sleep # Sleep reset + - const: sticky # Core Sticky reset + - const: axi_m # AXI Master reset + - const: axi_s # AXI Slave reset + - const: ahb # AHB Reset + - const: axi_m_sticky # AXI Master Sticky reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq6018 + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + clock-names: + items: + - const: iface # PCIe to SysNOC BIU clock + - const: axi_m # AXI Master clock + - const: axi_s # AXI Slave clock + - const: axi_bridge # AXI bridge clock + - const: rchng + resets: + minItems: 8 + maxItems: 8 + reset-names: + items: + - const: pipe # PIPE reset + - const: sleep # Sleep reset + - const: sticky # Core Sticky reset + - const: axi_m # AXI Master reset + - const: axi_s # AXI Slave reset + - const: ahb # AHB Reset + - const: axi_m_sticky # AXI Master Sticky reset + - const: axi_s_sticky # AXI Slave Sticky reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-qcs404 + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: iface # AHB clock + - const: aux # Auxiliary clock + - const: master_bus # AXI Master clock + - const: slave_bus # AXI Slave clock + resets: + minItems: 6 + maxItems: 6 + reset-names: + items: + - const: axi_m # AXI Master reset + - const: axi_s # AXI Slave reset + - const: axi_m_sticky # AXI Master Sticky reset + - const: pipe_sticky # PIPE sticky reset + - const: pwr # PWR reset + - const: ahb # AHB reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc7280 + then: + properties: + clocks: + minItems: 11 + maxItems: 11 + clock-names: + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sdm845 + then: + oneOf: + # Unfortunately the "optional" ref clock is used in the middle of the list + - properties: + clocks: + minItems: 8 + maxItems: 8 + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ref # REFERENCE clock + - const: tbu # PCIe TBU clock + - properties: + clocks: + minItems: 7 + maxItems: 7 + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + properties: + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc8180x + - qcom,pcie-sm8150 + - qcom,pcie-sm8250 + then: + oneOf: + # Unfortunately the "optional" ref clock is used in the middle of the list + - properties: + clocks: + minItems: 9 + maxItems: 9 + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ref # REFERENCE clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - properties: + clocks: + minItems: 8 + maxItems: 8 + clock-names: + items: + - const: pipe # PIPE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + properties: + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sm8450-pcie0 + then: + properties: + clocks: + minItems: 12 + maxItems: 12 + clock-names: + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre0 # Aggre NoC PCIe0 AXI clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sm8450-pcie1 + then: + properties: + clocks: + minItems: 11 + maxItems: 11 + clock-names: + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + - const: aggre1 # Aggre NoC PCIe1 AXI clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + + - if: + not: + properties: + compatible: + contains: + enum: + - qcom,pcie-apq8064 + - qcom,pcie-ipq4019 + - qcom,pcie-ipq8064 + - qcom,pcie-ipq8064v2 + - qcom,pcie-ipq8074 + - qcom,pcie-qcs404 + then: + required: + - power-domains + + - if: + not: + properties: + compatibles: + contains: + enum: + - qcom,pcie-msm8996 + then: + required: + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + pcie@1b500000 { + compatible = "qcom,pcie-ipq8064"; + reg = <0x1b500000 0x1000>, + <0x1b502000 0x80>, + <0x1b600000 0x100>, + <0x0ff00000 0x100000>; + reg-names = "dbi", "elbi", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>, + <0x82000000 0 0 0x08000000 0 0x07e00000>; + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc 41>, + <&gcc 43>, + <&gcc 44>, + <&gcc 42>, + <&gcc 248>; + clock-names = "core", "iface", "phy", "aux", "ref"; + resets = <&gcc 27>, + <&gcc 26>, + <&gcc 25>, + <&gcc 24>, + <&gcc 23>, + <&gcc 22>; + reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; + pinctrl-0 = <&pcie_pins_default>; + pinctrl-names = "default"; + vdda-supply = <&pm8921_s3>; + vdda_phy-supply = <&pm8921_lvs6>; + vdda_refclk-supply = <&ext_3p3v>; + }; + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/gpio/gpio.h> + pcie@fc520000 { + compatible = "qcom,pcie-apq8084"; + reg = <0xfc520000 0x2000>, + <0xff000000 0x1000>, + <0xff001000 0x1000>, + <0xff002000 0x2000>; + reg-names = "parf", "dbi", "elbi", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0 0xff200000 0 0x00100000>, + <0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc 324>, + <&gcc 325>, + <&gcc 327>, + <&gcc 323>; + clock-names = "iface", "master_bus", "slave_bus", "aux"; + resets = <&gcc 81>; + reset-names = "core"; + power-domains = <&gcc 1>; + vdda-supply = <&pma8084_l3>; + phys = <&pciephy0>; + phy-names = "pciephy"; + perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie0_pins_default>; + pinctrl-names = "default"; + }; +... diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 142bbe577763..bc0a9d1db750 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -19,20 +19,10 @@ description: |+ allOf: - $ref: /schemas/pci/pci-bus.yaml# -# We need a select here so we don't match all nodes with 'snps,dw-pcie' -select: - properties: - compatible: - contains: - const: rockchip,rk3568-pcie - required: - - compatible - properties: compatible: items: - const: rockchip,rk3568-pcie - - const: snps,dw-pcie reg: items: @@ -110,7 +100,7 @@ examples: #size-cells = <2>; pcie3x2: pcie@fe280000 { - compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; + compatible = "rockchip,rk3568-pcie"; reg = <0x3 0xc0800000 0x0 0x390000>, <0x0 0xfe280000 0x0 0x10000>, <0x3 0x80000000 0x0 0x100000>; diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml index 7c25c8d51116..9db904a528ee 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml @@ -76,73 +76,24 @@ additionalProperties: false examples: - | #include <dt-bindings/clock/aspeed-clock.h> - apb { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - syscon: scu@1e6e2000 { - compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; - reg = <0x1e6e2000 0x1a8>; - #clock-cells = <1>; - #reset-cells = <1>; - - pinctrl: pinctrl { - compatible = "aspeed,ast2500-pinctrl"; - aspeed,external-nodes = <&gfx>, <&lhc>; - - pinctrl_i2c3_default: i2c3_default { - function = "I2C3"; - groups = "I2C3"; - }; - - pinctrl_gpioh0_unbiased_default: gpioh0 { - pins = "A18"; - bias-disable; - }; + scu@1e6e2000 { + compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; + reg = <0x1e6e2000 0x1a8>; + #clock-cells = <1>; + #reset-cells = <1>; + + pinctrl: pinctrl { + compatible = "aspeed,ast2500-pinctrl"; + aspeed,external-nodes = <&gfx>, <&lhc>; + + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; }; - }; - - gfx: display@1e6e6000 { - compatible = "aspeed,ast2500-gfx", "syscon"; - reg = <0x1e6e6000 0x1000>; - reg-io-width = <4>; - clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; - resets = <&syscon ASPEED_RESET_CRT1>; - interrupts = <0x19>; - syscon = <&syscon>; - memory-region = <&gfx_memory>; - }; - }; - - lpc: lpc@1e789000 { - compatible = "aspeed,ast2500-lpc", "simple-mfd"; - reg = <0x1e789000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x1e789000 0x1000>; - - lpc_host: lpc-host@80 { - compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon"; - reg = <0x80 0x1e0>; - reg-io-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x80 0x1e0>; - - lhc: lhc@20 { - compatible = "aspeed,ast2500-lhc"; - reg = <0x20 0x24>, <0x48 0x8>; + pinctrl_gpioh0_unbiased_default: gpioh0 { + pins = "A18"; + bias-disable; }; }; }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt deleted file mode 100644 index bfab5ca49fd1..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +++ /dev/null @@ -1,87 +0,0 @@ -* Freescale i.MX7 Dual IOMUX Controller - -iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar -as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low -power state retention capabilities on gpios that are part of iomuxc-lpsr -(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for -mux and pad control settings, it shares the input select register from main -iomuxc controller for daisy chain settings, the fsl,input-sel property extends -fsl,imx-pinctrl driver to support iomuxc-lpsr controller. - -iomuxc_lpsr: iomuxc-lpsr@302c0000 { - compatible = "fsl,imx7d-iomuxc-lpsr"; - reg = <0x302c0000 0x10000>; - fsl,input-sel = <&iomuxc>; -}; - -iomuxc: iomuxc@30330000 { - compatible = "fsl,imx7d-iomuxc"; - reg = <0x30330000 0x10000>; -}; - -Peripherals using pads from iomuxc-lpsr support low state retention power -state, under LPSR mode GPIO's state of pads are retain. - -Please refer to fsl,imx-pinctrl.txt in this directory for common binding part -and usage. - -Required properties: -- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or - "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller. -- fsl,pins: each entry consists of 6 integers and represents the mux and config - setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val - input_val> are specified using a PIN_FUNC_ID macro, which can be found in - imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is - the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual - Reference Manual for detailed CONFIG settings. -- fsl,input-sel: required property for iomuxc-lpsr controller, this property is - a phandle for main iomuxc controller which shares the input select register for - daisy chain settings. - -CONFIG bits definition: -PAD_CTL_PUS_100K_DOWN (0 << 5) -PAD_CTL_PUS_5K_UP (1 << 5) -PAD_CTL_PUS_47K_UP (2 << 5) -PAD_CTL_PUS_100K_UP (3 << 5) -PAD_CTL_PUE (1 << 4) -PAD_CTL_HYS (1 << 3) -PAD_CTL_SRE_SLOW (1 << 2) -PAD_CTL_SRE_FAST (0 << 2) -PAD_CTL_DSE_X1 (0 << 0) -PAD_CTL_DSE_X4 (1 << 0) -PAD_CTL_DSE_X2 (2 << 0) -PAD_CTL_DSE_X6 (3 << 0) - -Examples: -While iomuxc-lpsr is intended to be used by dedicated peripherals to take -advantages of LPSR power mode, is also possible that an IP to use pads from -any of the iomux controllers. For example the I2C1 IP can use SCL pad from -iomuxc-lpsr controller and SDA pad from iomuxc controller as: - -i2c1: i2c@30a20000 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1_1>, <&pinctrl_i2c1_2>; -}; - -iomuxc-lpsr@302c0000 { - compatible = "fsl,imx7d-iomuxc-lpsr"; - reg = <0x302c0000 0x10000>; - fsl,input-sel = <&iomuxc>; - - pinctrl_i2c1_1: i2c1grp-1 { - fsl,pins = < - MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f - >; - }; -}; - -iomuxc@30330000 { - compatible = "fsl,imx7d-iomuxc"; - reg = <0x30330000 0x10000>; - - pinctrl_i2c1_2: i2c1grp-2 { - fsl,pins = < - MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f - >; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml new file mode 100644 index 000000000000..621038662188 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx7d-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX7D IOMUX Controller + +maintainers: + - Dong Aisheng <aisheng.dong@nxp.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + oneOf: + - enum: + - fsl,imx7d-iomuxc + - fsl,imx7d-iomuxc-lpsr + + reg: + maxItems: 1 + + fsl,input-sel: + description: + phandle for main iomuxc controller which shares the input select + register for daisy chain settings. + $ref: /schemas/types.yaml#/definitions/phandle + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm/boot/dts/imx7d-pinfunc.h>. The last integer + CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX7D Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + required: + - fsl,pins + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + - reg + +if: + properties: + compatible: + contains: + enum: + - fsl,imx7d-iomuxc-lpsr + +then: + required: + - fsl,input-sel + +additionalProperties: false + +examples: + - | + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_uart5: uart5grp { + fsl,pins = + <0x0160 0x03D0 0x0714 0x1 0x0 0x7e>, + <0x0164 0x03D4 0x0000 0x1 0x0 0x76>; + }; + }; + - | + iomuxc_lpsr: pinctrl@302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; + + pinctrl_gpio_lpsr: gpio1-grp { + fsl,pins = + <0x0008 0x0038 0x0000 0x0 0x0 0x59>, + <0x000C 0x003C 0x0000 0x0 0x0 0x59>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml new file mode 100644 index 000000000000..2e880b3e537c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1170.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MXRT1170 IOMUX Controller + +maintainers: + - Giulio Benetti <giulio.benetti@benettiengineering.com> + - Jesse Taube <Mr.Bossman075@gmail.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + const: fsl,imxrt1170-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm/boot/dts/imxrt1170-pinfunc.h>. The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MXRT1170 Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + iomuxc: iomuxc@400e8000 { + compatible = "fsl,imxrt1170-iomuxc"; + reg = <0x400e8000 0x4000>; + pinctrl_lpuart1: lpuart1grp { + fsl,pins = + <0x16C 0x3B0 0x620 0x0 0x0 0xf1>, + <0x170 0x3B4 0x61C 0x0 0x0 0xf1>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml new file mode 100644 index 000000000000..a651b2744caf --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,ac5-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell AC5 pin controller + +maintainers: + - Chris Packham <chris.packham@alliedtelesis.co.nz> + +description: + Bindings for Marvell's AC5 memory-mapped pin controller. + +properties: + compatible: + items: + - const: marvell,ac5-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + + properties: + marvell,function: + $ref: "/schemas/types.yaml#/definitions/string" + description: + Indicates the function to select. + enum: [ dev_init_done, ge, gpio, i2c0, i2c1, int_out, led, nand, pcie, ptp, sdio, + spi0, spi1, synce, tsen_int, uart0, uart1, uart2, uart3, uartsd, wd_int, xg ] + + marvell,pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Array of MPP pins to be used for the given function. + minItems: 1 + items: + enum: [ mpp0, mpp1, mpp2, mpp3, mpp4, mpp5, mpp6, mpp7, mpp8, mpp9, + mpp10, mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, mpp18, mpp19, + mpp20, mpp21, mpp22, mpp23, mpp24, mpp25, mpp26, mpp27, mpp28, mpp29, + mpp30, mpp31, mpp32, mpp33, mpp34, mpp35, mpp36, mpp37, mpp38, mpp39, + mpp40, mpp41, mpp42, mpp43, mpp44, mpp45 ] + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@80020100 { + compatible = "marvell,ac5-pinctrl"; + reg = <0x80020100 0x20>; + + i2c0_pins: i2c0-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c0"; + }; + + i2c0_gpio: i2c0-gpio-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "gpio"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml new file mode 100644 index 000000000000..73ae6e11410b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,pinctrl-mt6795.yaml @@ -0,0 +1,224 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,pinctrl-mt6795.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT6795 Pin Controller + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + - Sean Wang <sean.wang@kernel.org> + +description: | + The Mediatek's Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt6795-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: | + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + const: 2 + + gpio-ranges: + description: GPIO valid number range. + maxItems: 1 + + reg: + description: + Physical address base for gpio base and eint registers. + minItems: 2 + + reg-names: + items: + - const: base + - const: eint + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: The interrupt outputs to sysirq. + maxItems: 1 + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + patternProperties: + '^pins': + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and + input schmitt. + An example of using macro: + pincontroller { + /* GPIO0 set as multifunction GPIO0 */ + gpio-pins { + pins { + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; + } + }; + /* GPIO45 set as multifunction SDA0 */ + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO45__FUNC_SDA0>; + } + }; + }; + $ref: "pinmux-node.yaml" + + properties: + pinmux: + description: | + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h + directly. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt6795 pull down PUPD/R0/R1 type define value. + description: | + For normal pull down type, it is not necessary to specify R1R0 + values; When pull down type is PUPD/R0/R1, adding R1R0 defines + will set different resistance values. + + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt6795 pull up PUPD/R0/R1 type define value. + description: | + For normal pull up type, it is not necessary to specify R1R0 + values; When pull up type is PUPD/R0/R1, adding R1R0 defines + will set different resistance values. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + mediatek,pull-up-adv: + description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + required: + - pinmux + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/pinctrl/mt6795-pinfunc.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6795-pinctrl"; + reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; + reg-names = "base", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 196>; + interrupt-controller; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + + i2c0-pins { + pins-sda-scl { + pinmux = <PINMUX_GPIO45__FUNC_SDA0>, + <PINMUX_GPIO46__FUNC_SCL0>; + }; + }; + + mmc0-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO155__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO156__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO157__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO158__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO159__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO160__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO161__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO162__FUNC_MSDC0_CMD>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt deleted file mode 100644 index 5d84fd299ccf..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ /dev/null @@ -1,42 +0,0 @@ -Microsemi Ocelot pin controller Device Tree Bindings ----------------------------------------------------- - -Required properties: - - compatible : Should be "mscc,ocelot-pinctrl", - "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl", - "mscc,luton-pinctrl", "mscc,serval-pinctrl", - "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl" - - reg : Address and length of the register set for the device - - gpio-controller : Indicates this device is a GPIO controller - - #gpio-cells : Must be 2. - The first cell is the pin number and the - second cell specifies GPIO flags, as defined in - <dt-bindings/gpio/gpio.h>. - - gpio-ranges : Range of pins managed by the GPIO controller. - - -The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin -configuration documented in pinctrl-bindings.txt. - -The following generic properties are supported: - - function - - pins - -Example: - gpio: pinctrl@71070034 { - compatible = "mscc,ocelot-pinctrl"; - reg = <0x71070034 0x28>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&gpio 0 0 22>; - - uart_pins: uart-pins { - pins = "GPIO_6", "GPIO_7"; - function = "uart"; - }; - - uart2_pins: uart2-pins { - pins = "GPIO_12", "GPIO_13"; - function = "uart2"; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml new file mode 100644 index 000000000000..98d547c34ef3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microsemi Ocelot pin controller + +maintainers: + - Alexandre Belloni <alexandre.belloni@bootlin.com> + - Lars Povlsen <lars.povlsen@microchip.com> + +properties: + compatible: + enum: + - microchip,lan966x-pinctrl + - microchip,sparx5-pinctrl + - mscc,jaguar2-pinctrl + - mscc,luton-pinctrl + - mscc,ocelot-pinctrl + - mscc,serval-pinctrl + - mscc,servalt-pinctrl + + reg: + items: + - description: Base address + - description: Extended pin configuration registers + minItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: true + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + resets: + maxItems: 1 + + reset-names: + description: Optional shared switch reset. + items: + - const: switch + +patternProperties: + '-pins$': + type: object + allOf: + - $ref: "pinmux-node.yaml" + - $ref: "pincfg-node.yaml" + + properties: + function: true + pins: true + output-high: true + output-low: true + drive-strength: true + + required: + - function + - pins + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +allOf: + - $ref: "pinctrl.yaml#" + - if: + properties: + compatible: + contains: + enum: + - microchip,lan966x-pinctrl + - microchip,sparx5-pinctrl + then: + properties: + reg: + minItems: 2 + +additionalProperties: false + +examples: + - | + gpio: pinctrl@71070034 { + compatible = "mscc,ocelot-pinctrl"; + reg = <0x71070034 0x28>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 22>; + + uart_pins: uart-pins { + pins = "GPIO_6", "GPIO_7"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_12", "GPIO_13"; + function = "uart2"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml index 3c84676a167d..c90a132fbc79 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml @@ -29,6 +29,8 @@ properties: description: gpio valid number range. maxItems: 1 + gpio-line-names: true + reg: description: | Physical address base for gpio base registers. There are 11 GPIO @@ -51,62 +53,92 @@ properties: #PIN CONFIGURATION NODES patternProperties: - '^pins': + '-pins$': type: object - description: | - A pinctrl node should contain at least one subnodes representing the - pinctrl groups available on the machine. Each subnode will list the - pins it needs, and how they should be configured, with regard to muxer - configuration, pullups, drive strength, input enable/disable and - input schmitt. - An example of using macro: - pincontroller { - /* GPIO0 set as multifunction GPIO0 */ - state_0_node_a { - pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; - }; - /* GPIO1 set as multifunction PWM */ - state_0_node_b { - pinmux = <PINMUX_GPIO1__FUNC_PWM_1>; - }; - }; - $ref: "pinmux-node.yaml" - - properties: - pinmux: - description: | - Integer array, represents gpio pin number and mux setting. - Supported pin number and mux varies for different SoCs, and are defined - as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly. - - drive-strength: - description: | - It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See - dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192. - enum: [2, 4, 6, 8, 10, 12, 14, 16] - - bias-pull-down: true - - bias-pull-up: true - - bias-disable: true - - output-high: true - - output-low: true - - input-enable: true - - input-disable: true - - input-schmitt-enable: true - - input-schmitt-disable: true - - required: - - pinmux - additionalProperties: false + patternProperties: + '^pins': + type: object + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and + input schmitt. + $ref: "pinmux-node.yaml" + + properties: + pinmux: + description: | + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined + as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly. + + drive-strength: + description: | + It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See + dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192. + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + mediatek,drive-strength-adv: + description: | + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only support + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they + can support 0.125/0.25/0.5/1mA adjustment. If we enable specific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=0/E0=0, the strength is 0.125mA. + When E1=0/E0=1, the strength is 0.25mA. + When E1=1/E0=0, the strength is 0.5mA. + When E1=1/E0=1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) = (0, 0, 0) + 1: (E1, E0, EN) = (0, 0, 1) + 2: (E1, E0, EN) = (0, 1, 0) + 3: (E1, E0, EN) = (0, 1, 1) + 4: (E1, E0, EN) = (1, 0, 0) + 5: (E1, E0, EN) = (1, 0, 1) + 6: (E1, E0, EN) = (1, 1, 0) + 7: (E1, E0, EN) = (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + mediatek,pull-up-adv: + description: | + Pull up settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false allOf: - $ref: "pinctrl.yaml#" @@ -151,8 +183,17 @@ examples: interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; #interrupt-cells = <2>; - pins { - pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; - output-low; + spi1-default-pins { + pins-cs-mosi-clk { + pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, + <PINMUX_GPIO159__FUNC_SPI1_A_MO>, + <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; + bias-disable; + }; + + pins-miso { + pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; + bias-pull-down; + }; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index fe2bcf0694d9..6f2efc3772cb 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -20,6 +20,7 @@ properties: - qcom,pm2250-gpio - qcom,pm660-gpio - qcom,pm660l-gpio + - qcom,pm6125-gpio - qcom,pm6150-gpio - qcom,pm6150l-gpio - qcom,pm6350-gpio @@ -32,6 +33,7 @@ properties: - qcom,pm8058-gpio - qcom,pm8150-gpio - qcom,pm8150b-gpio + - qcom,pm8150l-gpio - qcom,pm8226-gpio - qcom,pm8350-gpio - qcom,pm8350b-gpio @@ -49,10 +51,12 @@ properties: - qcom,pmi8994-gpio - qcom,pmi8998-gpio - qcom,pmk8350-gpio + - qcom,pmm8155au-gpio - qcom,pmr735a-gpio - qcom,pmr735b-gpio - qcom,pms405-gpio - qcom,pmx55-gpio + - qcom,pmx65-gpio - enum: - qcom,spmi-gpio @@ -71,6 +75,16 @@ properties: gpio-ranges: maxItems: 1 + gpio-line-names: + minItems: 2 + maxItems: 44 + + gpio-reserved-ranges: + minItems: 1 + # maxItems as half of total number of GPIOs, as there has to be at + # least one usable GPIO between each reserved range. + maxItems: 22 + '#gpio-cells': const: 2 description: @@ -87,13 +101,278 @@ required: - gpio-ranges - interrupt-controller +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8008-gpio + - qcom,pmi8950-gpio + then: + properties: + gpio-line-names: + minItems: 2 + maxItems: 2 + gpio-reserved-ranges: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8005-gpio + - qcom,pm8450-gpio + - qcom,pm8916-gpio + - qcom,pmk8350-gpio + - qcom,pmr735a-gpio + - qcom,pmr735b-gpio + then: + properties: + gpio-line-names: + minItems: 4 + maxItems: 4 + gpio-reserved-ranges: + minItems: 1 + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8018-gpio + - qcom,pm8019-gpio + then: + properties: + gpio-line-names: + minItems: 6 + maxItems: 6 + gpio-reserved-ranges: + minItems: 1 + maxItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8350b-gpio + - qcom,pm8950-gpio + then: + properties: + gpio-line-names: + minItems: 8 + maxItems: 8 + gpio-reserved-ranges: + minItems: 1 + maxItems: 4 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm6350-gpio + - qcom,pm8350c-gpio + then: + properties: + gpio-line-names: + minItems: 9 + maxItems: 9 + gpio-reserved-ranges: + minItems: 1 + maxItems: 5 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm2250-gpio + - qcom,pm6150-gpio + - qcom,pm7325-gpio + - qcom,pm8150-gpio + - qcom,pm8350-gpio + - qcom,pmc8180-gpio + - qcom,pmi8994-gpio + - qcom,pmm8155au-gpio + then: + properties: + gpio-line-names: + minItems: 10 + maxItems: 10 + gpio-reserved-ranges: + minItems: 1 + maxItems: 5 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pmx55-gpio + then: + properties: + gpio-line-names: + minItems: 11 + maxItems: 11 + gpio-reserved-ranges: + minItems: 1 + maxItems: 6 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm660l-gpio + - qcom,pm6150l-gpio + - qcom,pm8038-gpio + - qcom,pm8150b-gpio + - qcom,pm8150l-gpio + - qcom,pmc8180c-gpio + - qcom,pms405-gpio + then: + properties: + gpio-line-names: + minItems: 12 + maxItems: 12 + gpio-reserved-ranges: + minItems: 1 + maxItems: 6 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm660-gpio + then: + properties: + gpio-line-names: + minItems: 13 + maxItems: 13 + gpio-reserved-ranges: + minItems: 1 + maxItems: 7 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pmi8998-gpio + then: + properties: + gpio-line-names: + minItems: 14 + maxItems: 14 + gpio-reserved-ranges: + minItems: 1 + maxItems: 7 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pmx65-gpio + then: + properties: + gpio-line-names: + minItems: 16 + maxItems: 16 + gpio-reserved-ranges: + minItems: 1 + maxItems: 8 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8994-gpio + - qcom,pma8084-gpio + then: + properties: + gpio-line-names: + minItems: 22 + maxItems: 22 + gpio-reserved-ranges: + minItems: 1 + maxItems: 11 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8998-gpio + then: + properties: + gpio-line-names: + minItems: 26 + maxItems: 26 + gpio-reserved-ranges: + minItems: 1 + maxItems: 13 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8941-gpio + then: + properties: + gpio-line-names: + minItems: 36 + maxItems: 36 + gpio-reserved-ranges: + minItems: 1 + maxItems: 18 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8917-gpio + then: + properties: + gpio-line-names: + minItems: 38 + maxItems: 38 + gpio-reserved-ranges: + minItems: 1 + maxItems: 19 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8058-gpio + - qcom,pm8921-gpio + then: + properties: + gpio-line-names: + minItems: 44 + maxItems: 44 + gpio-reserved-ranges: + minItems: 1 + maxItems: 22 + patternProperties: '-state$': oneOf: - $ref: "#/$defs/qcom-pmic-gpio-state" - patternProperties: - ".*": + "(pinconf|-pins)$": $ref: "#/$defs/qcom-pmic-gpio-state" + additionalProperties: false $defs: qcom-pmic-gpio-state: @@ -106,6 +385,7 @@ $defs: description: List of gpio pins affected by the properties specified in this subnode. Valid pins are + - gpio1-gpio9 for pm6125 - gpio1-gpio10 for pm6150 - gpio1-gpio12 for pm6150l - gpio1-gpio9 for pm6350 @@ -134,12 +414,14 @@ $defs: - gpio1-gpio2 for pmi8950 - gpio1-gpio10 for pmi8994 - gpio1-gpio4 for pmk8350 + - gpio1-gpio10 for pmm8155au - gpio1-gpio4 for pmr735a - gpio1-gpio4 for pmr735b - gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10) - gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10 and gpio11) + - gpio1-gpio16 for pmx65 items: pattern: "^gpio([0-9]+)$" @@ -174,6 +456,7 @@ $defs: bias-high-impedance: true input-enable: true + input-disable: true output-high: true output-low: true output-enable: true @@ -232,7 +515,7 @@ examples: #gpio-cells = <2>; pm8921_gpio_keys: gpio-keys-state { - volume-keys { + volume-keys-pins { pins = "gpio20", "gpio21"; function = "normal"; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml index 206f4f238736..3f4f1c0360b5 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-pinctrl.yaml @@ -42,8 +42,7 @@ properties: gpio-ranges: maxItems: 1 - wakeup-parent: - maxItems: 1 + wakeup-parent: true #PIN CONFIGURATION NODES patternProperties: diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..d32ee32776e8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) + Low Power Island (LPI) TLMM block + +maintainers: + - Srinivasa Rao Mandadapu <srivasam@codeaurora.org> + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + LPASS LPI IP on most Qualcomm SoCs + +properties: + compatible: + const: qcom,sc7280-lpass-lpi-pinctrl + + reg: + minItems: 2 + maxItems: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9])$" + minItems: 1 + maxItems: 15 + + function: + enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws, + qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk, + dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data, + i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk, + dmic3_data, i2s2_data ] + description: + Specify the alternative function to be configured for the specified + pins. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sc7280-lpass-lpi-pinctrl"; + reg = <0x33c0000 0x20000>, + <0x3550000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml index 6c7c3f6a140e..2d228164357c 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml @@ -42,8 +42,7 @@ properties: gpio-ranges: maxItems: 1 - wakeup-parent: - maxItems: 1 + wakeup-parent: true #PIN CONFIGURATION NODES patternProperties: diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml index cfcde405d30a..a7a2bb8bff46 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-pinctrl.yaml @@ -49,8 +49,7 @@ properties: gpio-ranges: maxItems: 1 - wakeup-parent: - maxItems: 1 + wakeup-parent: true #PIN CONFIGURATION NODES patternProperties: diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml index 5c5542f1627c..06efb1382876 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-pinctrl.yaml# +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml index cfa2c50fdb93..15bb1018cf21 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -49,8 +49,7 @@ properties: gpio-ranges: maxItems: 1 - wakeup-parent: - maxItems: 1 + wakeup-parent: true #PIN CONFIGURATION NODES patternProperties: diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml index 780f15bb5e40..c88c8dcb69d9 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml @@ -42,7 +42,6 @@ properties: description: Specifying the interrupt-controller used to wake up the system when the TLMM block has been powered down. - maxItems: 1 gpio-reserved-ranges: description: diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml new file mode 100644 index 000000000000..4d820df24b89 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7620-pinctrl.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,mt7620-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink MT7620 Pin Controller + +maintainers: + - Arınç ÃœNAL <arinc.unal@arinc9.com> + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: + Ralink MT7620 pin controller for MT7620, MT7628 and MT7688 SoCs. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,mt7620-pinctrl + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + + properties: + groups: + description: The pin group to select. + enum: [ + # For MT7620 SoC + ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, spi, spi refclk, + uartf, uartlite, wdt, wled, + + # For MT7628 and MT7688 SoCs + gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an, + p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, perst, pwm0, + pwm1, refclk, sdmode, spi, spi cs1, spis, uart0, uart1, uart2, + wdt, wled_an, wled_kn, + ] + + function: + description: The mux function to select. + enum: [ + # For MT7620 SoC + ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, mdio, nand, pa, + pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, refclk, + rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlite, wdt refclk, + wdt rst, wled, + + # For MT7628 and MT7688 SoCs + antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0led_kn, + p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn, + p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, pwm_uart2, + refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, spi, spi cs1, + spis, sw_r, uart0, uart1, uart2, utif, wdt, wled_an, wled_kn, -, + ] + + required: + - groups + - function + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + +additionalProperties: false + +examples: + # Pinmux controller node + - | + pinctrl { + compatible = "ralink,mt7620-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml index 9de8b0c075e2..61e5c847e8c8 100644 --- a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/ralink,mt7621-pinctrl.yaml @@ -1,21 +1,23 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinmux.yaml# +$id: http://devicetree.org/schemas/pinctrl/ralink,mt7621-pinctrl.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Ralink rt2880 pinmux controller +title: Ralink MT7621 Pin Controller maintainers: + - Arınç ÃœNAL <arinc.unal@arinc9.com> - Sergio Paracuellos <sergio.paracuellos@gmail.com> description: - The rt2880 pinmux can only set the muxing of pin groups. Muxing indiviual pins - is not supported. There is no pinconf support. + Ralink MT7621 pin controller for MT7621 SoC. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. properties: compatible: - const: ralink,rt2880-pinmux + const: ralink,mt7621-pinctrl patternProperties: '-pins$': @@ -28,14 +30,15 @@ patternProperties: properties: groups: - description: Name of the pin group to use for the functions. - enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi, - uart1, uart2, uart3, wdt] + description: The pin group to select. + enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi, uart1, + uart2, uart3, wdt] + function: - description: The mux function to select + description: The mux function to select. enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk, - pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3, - spi, uart1, uart2, uart3, wdt refclk, wdt rst] + pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3, spi, + uart1, uart2, uart3, wdt refclk, wdt rst] required: - groups @@ -57,7 +60,7 @@ examples: # Pinmux controller node - | pinctrl { - compatible = "ralink,rt2880-pinmux"; + compatible = "ralink,mt7621-pinctrl"; i2c_pins: i2c0-pins { pinmux { diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml new file mode 100644 index 000000000000..56e5becabcfd --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink RT2880 Pin Controller + +maintainers: + - Arınç ÃœNAL <arinc.unal@arinc9.com> + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: + Ralink RT2880 pin controller for RT2880 SoC. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,rt2880-pinctrl + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + + properties: + groups: + description: The pin group to select. + enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci] + + function: + description: The mux function to select. + enum: [gpio, i2c, spi, uartlite, jtag, mdio, sdram, pci] + + required: + - groups + - function + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + +additionalProperties: false + +examples: + # Pinmux controller node + - | + pinctrl { + compatible = "ralink,rt2880-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml new file mode 100644 index 000000000000..425401c54269 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,rt305x-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink RT305X Pin Controller + +maintainers: + - Arınç ÃœNAL <arinc.unal@arinc9.com> + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: + Ralink RT305X pin controller for RT3050, RT3052, RT3350, RT3352 and RT5350 + SoCs. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,rt305x-pinctrl + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + + properties: + groups: + description: The pin group to select. + enum: [ + # For RT3050, RT3052 and RT3350 SoCs + i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartlite, + + # For RT3352 SoC + i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs1, uartf, + uartlite, + + # For RT5350 SoC + i2c, jtag, led, spi, spi_cs1, uartf, uartlite, + ] + + function: + description: The mux function to select. + enum: [ + # For RT3050, RT3052 and RT3350 SoCs + gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio, pcm gpio, + pcm i2s, pcm uartf, rgmii, sdram, spi, uartf, uartlite, + + # For RT3352 SoC + gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, lna, mdio, + pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi_cs1, uartf, + uartlite, wdg_cs1, + + # For RT5350 SoC + gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, pcm gpio, + pcm i2s, pcm uartf, spi, spi_cs1, uartf, uartlite, wdg_cs1, + ] + + required: + - groups + - function + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + +additionalProperties: false + +examples: + # Pinmux controller node + - | + pinctrl { + compatible = "ralink,rt305x-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml new file mode 100644 index 000000000000..feb6e66dcb61 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,rt3883-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink RT3883 Pin Controller + +maintainers: + - Arınç ÃœNAL <arinc.unal@arinc9.com> + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: + Ralink RT3883 pin controller for RT3883 SoC. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,rt3883-pinctrl + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + + properties: + groups: + description: The pin group to select. + enum: [ge1, ge2, i2c, jtag, lna a, lna g, mdio, pci, spi, uartf, + uartlite] + + function: + description: The mux function to select. + enum: [ge1, ge2, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, + lna a, lna g, mdio, pci-dev, pci-fnc, pci-host1, pci-host2, + pcm gpio, pcm i2s, pcm uartf, spi, uartf, uartlite] + + required: + - groups + - function + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + +additionalProperties: false + +examples: + # Pinmux controller node + - | + pinctrl { + compatible = "ralink,rt3883-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 9ccf54870aa4..52df1b146174 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -11,8 +11,8 @@ maintainers: - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> description: - The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO - controller. + The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and + GPIO controller. Pin multiplexing and GPIO configuration is performed on a per-pin basis. Each port features up to 8 pins, each of them configurable for GPIO function (port mode) or in alternate function mode. @@ -23,6 +23,7 @@ properties: oneOf: - items: - enum: + - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - items: diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml index b0eae3a67ab1..677a285ca416 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -33,6 +33,7 @@ properties: enum: - rockchip,px30-pinctrl - rockchip,rk2928-pinctrl + - rockchip,rk3036-pinctrl - rockchip,rk3066a-pinctrl - rockchip,rk3066b-pinctrl - rockchip,rk3128-pinctrl @@ -44,6 +45,7 @@ properties: - rockchip,rk3368-pinctrl - rockchip,rk3399-pinctrl - rockchip,rk3568-pinctrl + - rockchip,rk3588-pinctrl - rockchip,rv1108-pinctrl rockchip,grf: @@ -129,7 +131,7 @@ additionalProperties: description: Pin bank index. - minimum: 0 - maximum: 6 + maximum: 10 description: Mux 0 means GPIO and mux 1 to N means the specific device function. diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt b/Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt deleted file mode 100644 index 781955f5217d..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Freescale PQ3 and QorIQ based Cache SRAM - -Freescale's mpc85xx and some QorIQ platforms provide an -option of configuring a part of (or full) cache memory -as SRAM. This cache SRAM representation in the device -tree should be done as under:- - -Required properties: - -- compatible : should be "fsl,p2020-cache-sram" -- fsl,cache-sram-ctlr-handle : points to the L2 controller -- reg : offset and length of the cache-sram. - -Example: - -cache-sram@fff00000 { - fsl,cache-sram-ctlr-handle = <&L2>; - reg = <0 0xfff00000 0 0x10000>; - compatible = "fsl,p2020-cache-sram"; -}; diff --git a/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml b/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml new file mode 100644 index 000000000000..ab45df80345d --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/atmel,at91sam-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel/Microchip PWM controller + +maintainers: + - Claudiu Beznea <claudiu.beznea@microchip.com> + +allOf: + - $ref: "pwm.yaml#" + +properties: + compatible: + oneOf: + - items: + - enum: + - atmel,at91sam9rl-pwm + - atmel,sama5d3-pwm + - atmel,sama5d2-pwm + - microchip,sam9x60-pwm + - items: + - const: microchip,sama7g5-pwm + - const: atmel,sama5d2-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + pwm0: pwm@f8034000 { + compatible = "atmel,at91sam9rl-pwm"; + reg = <0xf8034000 0x400>; + #pwm-cells = <3>; + }; diff --git a/Documentation/devicetree/bindings/pwm/atmel-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-pwm.txt deleted file mode 100644 index fbb5325be1f0..000000000000 --- a/Documentation/devicetree/bindings/pwm/atmel-pwm.txt +++ /dev/null @@ -1,35 +0,0 @@ -Atmel PWM controller - -Required properties: - - compatible: should be one of: - - "atmel,at91sam9rl-pwm" - - "atmel,sama5d3-pwm" - - "atmel,sama5d2-pwm" - - "microchip,sam9x60-pwm" - - reg: physical base address and length of the controller's registers - - #pwm-cells: Should be 3. See pwm.yaml in this directory for a - description of the cells format. - -Example: - - pwm0: pwm@f8034000 { - compatible = "atmel,at91sam9rl-pwm"; - reg = <0xf8034000 0x400>; - #pwm-cells = <3>; - }; - - pwmleds { - compatible = "pwm-leds"; - - d1 { - label = "d1"; - pwms = <&pwm0 3 5000 0> - max-brightness = <255>; - }; - - d2 { - label = "d2"; - pwms = <&pwm0 1 5000 1> - max-brightness = <255>; - }; - }; diff --git a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml index 7ab6912a845f..c8577bdf6c94 100644 --- a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml @@ -21,7 +21,14 @@ allOf: properties: compatible: - const: google,cros-ec-pwm + oneOf: + - description: PWM controlled using EC_PWM_TYPE_GENERIC channels. + items: + - const: google,cros-ec-pwm + - description: PWM controlled using CROS_EC_PWM_DT_<...> types. + items: + - const: google,cros-ec-pwm-type + "#pwm-cells": description: The cell specifies the PWM index. const: 1 diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml new file mode 100644 index 000000000000..e4fe2d1bfef5 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek DISP_PWM Controller Device Tree Bindings + +maintainers: + - Jitao Shi <jitao.shi@mediatek.com> + - Xinlei Lee <xinlei.lee@mediatek.com> + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2701-disp-pwm + - mediatek,mt6595-disp-pwm + - mediatek,mt8173-disp-pwm + - mediatek,mt8183-disp-pwm + - items: + - const: mediatek,mt8167-disp-pwm + - const: mediatek,mt8173-disp-pwm + - items: + - enum: + - mediatek,mt8186-disp-pwm + - mediatek,mt8192-disp-pwm + - mediatek,mt8195-disp-pwm + - const: mediatek,mt8183-disp-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 2 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Main Clock + - description: Mm Clock + + clock-names: + items: + - const: main + - const: mm + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mt8173-clk.h> + #include <dt-bindings/interrupt-controller/irq.h> + + pwm0: pwm@1401e000 { + compatible = "mediatek,mt8173-disp-pwm"; + reg = <0x1401e000 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_DISP_PWM026M>, + <&mmsys CLK_MM_DISP_PWM0MM>; + clock-names = "main", "mm"; + }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt index 25ed214473d7..033d1fc0f405 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt @@ -3,6 +3,7 @@ MediaTek PWM controller Required properties: - compatible: should be "mediatek,<name>-pwm": - "mediatek,mt2712-pwm": found on mt2712 SoC. + - "mediatek,mt6795-pwm": found on mt6795 SoC. - "mediatek,mt7622-pwm": found on mt7622 SoC. - "mediatek,mt7623-pwm": found on mt7623 SoC. - "mediatek,mt7628-pwm": found on mt7628 SoC. diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt deleted file mode 100644 index 691e58b6c223..000000000000 --- a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt +++ /dev/null @@ -1,45 +0,0 @@ -MediaTek display PWM controller - -Required properties: - - compatible: should be "mediatek,<name>-disp-pwm": - - "mediatek,mt2701-disp-pwm": found on mt2701 SoC. - - "mediatek,mt6595-disp-pwm": found on mt6595 SoC. - - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC. - - "mediatek,mt8173-disp-pwm": found on mt8173 SoC. - - "mediatek,mt8183-disp-pwm": found on mt8183 SoC.$ - - reg: physical base address and length of the controller's registers. - - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of - the cell format. - - clocks: phandle and clock specifier of the PWM reference clock. - - clock-names: must contain the following: - - "main": clock used to generate PWM signals. - - "mm": sync signals from the modules of mmsys. - - pinctrl-names: Must contain a "default" entry. - - pinctrl-0: One property must exist for each entry in pinctrl-names. - See pinctrl/pinctrl-bindings.txt for details of the property values. - -Example: - pwm0: pwm@1401e000 { - compatible = "mediatek,mt8173-disp-pwm", - "mediatek,mt6595-disp-pwm"; - reg = <0 0x1401e000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&mmsys CLK_MM_DISP_PWM026M>, - <&mmsys CLK_MM_DISP_PWM0MM>; - clock-names = "main", "mm"; - pinctrl-names = "default"; - pinctrl-0 = <&disp_pwm0_pins>; - }; - - backlight_lcd: backlight_lcd { - compatible = "pwm-backlight"; - pwms = <&pwm0 0 1000000>; - brightness-levels = < - 0 16 32 48 64 80 96 112 - 128 144 160 176 192 208 224 240 - 255 - >; - default-brightness-level = <9>; - power-supply = <&mt6397_vio18_reg>; - enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>; - }; diff --git a/Documentation/devicetree/bindings/pwm/sunplus,sp7021-pwm.yaml b/Documentation/devicetree/bindings/pwm/sunplus,sp7021-pwm.yaml new file mode 100644 index 000000000000..d4fc9e8db1d1 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/sunplus,sp7021-pwm.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/sunplus,sp7021-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SoC SP7021 PWM Controller + +maintainers: + - Hammer Hsieh <hammerh0314@gmail.com> + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: sunplus,sp7021-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#pwm-cells': + const: 2 + +unevaluatedProperties: false + +required: + - reg + - clocks + +examples: + - | + pwm: pwm@9c007a00 { + compatible = "sunplus,sp7021-pwm"; + reg = <0x9c007a00 0x80>; + clocks = <&clkc 0xa2>; + #pwm-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml index fc16d903353e..3a1f59ad79e2 100644 --- a/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml @@ -15,14 +15,15 @@ maintainers: properties: compatible: enum: - - fsl,imx8mq-cm4 + - fsl,imx6sx-cm4 + - fsl,imx7d-cm4 + - fsl,imx7ulp-cm4 - fsl,imx8mm-cm4 - fsl,imx8mn-cm7 - fsl,imx8mp-cm7 + - fsl,imx8mq-cm4 - fsl,imx8ulp-cm33 - - fsl,imx7d-cm4 - - fsl,imx7ulp-cm4 - - fsl,imx6sx-cm4 + - fsl,imx93-cm33 clocks: maxItems: 1 diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml index 5b693a2d049c..eec3b9c4c713 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml @@ -23,11 +23,13 @@ properties: reg: description: - Should contain the address ranges for memory regions SRAM, CFG, and - L1TCM. + Should contain the address ranges for memory regions SRAM, CFG, and, + on some platforms, L1TCM. + minItems: 2 maxItems: 3 reg-names: + minItems: 2 items: - const: sram - const: cfg @@ -42,21 +44,48 @@ properties: clock-names: const: main + interrupts: + maxItems: 1 + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + If present, name (or relative path) of the file within the + firmware search path containing the firmware image used when + initializing SCP. + + memory-region: + maxItems: 1 + required: - compatible - reg - reg-names -if: - properties: - compatible: - enum: - - mediatek,mt8183-scp - - mediatek,mt8192-scp -then: - required: - - clocks - - clock-names +allOf: + - if: + properties: + compatible: + enum: + - mediatek,mt8183-scp + - mediatek,mt8192-scp + then: + required: + - clocks + - clock-names + + - if: + properties: + compatible: + enum: + - mediatek,mt8183-scp + - mediatek,mt8186-scp + then: + properties: + reg: + maxItems: 2 + reg-names: + maxItems: 2 additionalProperties: type: object @@ -76,10 +105,10 @@ additionalProperties: examples: - | - #include <dt-bindings/clock/mt8183-clk.h> + #include <dt-bindings/clock/mt8192-clk.h> scp@10500000 { - compatible = "mediatek,mt8183-scp"; + compatible = "mediatek,mt8192-scp"; reg = <0x10500000 0x80000>, <0x10700000 0x8000>, <0x10720000 0xe0000>; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml index a4409c398193..947f94548d0e 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml @@ -16,6 +16,7 @@ description: properties: compatible: enum: + - qcom,msm8226-adsp-pil - qcom,msm8974-adsp-pil - qcom,msm8996-adsp-pil - qcom,msm8996-slpi-pil @@ -29,6 +30,9 @@ properties: - qcom,sc8180x-adsp-pas - qcom,sc8180x-cdsp-pas - qcom,sc8180x-mpss-pas + - qcom,sc8280xp-adsp-pas + - qcom,sc8280xp-nsp0-pas + - qcom,sc8280xp-nsp1-pas - qcom,sdm660-adsp-pas - qcom,sdm845-adsp-pas - qcom,sdm845-cdsp-pas @@ -159,6 +163,7 @@ allOf: compatible: contains: enum: + - qcom,msm8226-adsp-pil - qcom,msm8974-adsp-pil - qcom,msm8996-adsp-pil - qcom,msm8996-slpi-pil @@ -169,6 +174,9 @@ allOf: - qcom,sc8180x-adsp-pas - qcom,sc8180x-cdsp-pas - qcom,sc8180x-mpss-pas + - qcom,sc8280xp-adsp-pas + - qcom,sc8280xp-nsp0-pas + - qcom,sc8280xp-nsp1-pas - qcom,sdm845-adsp-pas - qcom,sdm845-cdsp-pas - qcom,sm6350-adsp-pas @@ -274,6 +282,7 @@ allOf: compatible: contains: enum: + - qcom,msm8226-adsp-pil - qcom,msm8974-adsp-pil - qcom,msm8996-adsp-pil - qcom,msm8996-slpi-pil @@ -284,6 +293,9 @@ allOf: - qcom,qcs404-wcss-pas - qcom,sc8180x-adsp-pas - qcom,sc8180x-cdsp-pas + - qcom,sc8280xp-adsp-pas + - qcom,sc8280xp-nsp0-pas + - qcom,sc8280xp-nsp1-pas - qcom,sdm845-adsp-pas - qcom,sdm845-cdsp-pas - qcom,sm6350-adsp-pas @@ -364,6 +376,7 @@ allOf: compatible: contains: enum: + - qcom,msm8226-adsp-pil - qcom,msm8996-adsp-pil - qcom,msm8998-adsp-pas then: @@ -471,6 +484,7 @@ allOf: enum: - qcom,sc8180x-adsp-pas - qcom,sc8180x-cdsp-pas + - qcom,sc8280xp-adsp-pas - qcom,sm6350-adsp-pas - qcom,sm8150-slpi-pas - qcom,sm8250-adsp-pas @@ -513,6 +527,22 @@ allOf: compatible: contains: enum: + - qcom,sc8280xp-nsp0-pas + - qcom,sc8280xp-nsp1-pas + then: + properties: + power-domains: + items: + - description: NSP power domain + power-domain-names: + items: + - const: nsp + + - if: + properties: + compatible: + contains: + enum: - qcom,qcs404-cdsp-pas then: properties: @@ -546,6 +576,7 @@ allOf: compatible: contains: enum: + - qcom,msm8226-adsp-pil - qcom,msm8974-adsp-pil - qcom,msm8996-adsp-pil - qcom,msm8996-slpi-pil diff --git a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml index be3d9b0e876b..da50f0e99fe2 100644 --- a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml @@ -43,8 +43,8 @@ properties: items: - items: - description: Phandle of syscon block - - description: FIXME - - description: FIXME + - description: The offset of the trust zone setting register + - description: The field mask of the trust zone state interrupts: description: Should contain the WWDG1 watchdog reset interrupt @@ -101,8 +101,8 @@ properties: items: - items: - description: Phandle of syscon block - - description: FIXME - - description: FIXME + - description: The offset of the power setting register + - description: The field mask of the PDDS selection st,syscfg-m4-state: $ref: "/schemas/types.yaml#/definitions/phandle-array" @@ -111,8 +111,8 @@ properties: items: - items: - description: Phandle of syscon block with the tamp register - - description: FIXME - - description: FIXME + - description: The offset of the tamp register + - description: The field mask of the Cortex-M4 state st,syscfg-rsc-tbl: $ref: "/schemas/types.yaml#/definitions/phandle-array" @@ -122,8 +122,8 @@ properties: items: - items: - description: Phandle of syscon block with the tamp register - - description: FIXME - - description: FIXME + - description: The offset of the tamp register + - description: The field mask of the Cortex-M4 resource table address st,auto-boot: $ref: /schemas/types.yaml#/definitions/flag diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf85063.txt b/Documentation/devicetree/bindings/rtc/nxp,pcf85063.txt index 6439682c9319..217b7cd06c11 100644 --- a/Documentation/devicetree/bindings/rtc/nxp,pcf85063.txt +++ b/Documentation/devicetree/bindings/rtc/nxp,pcf85063.txt @@ -2,6 +2,7 @@ Required properties: - compatible: Should one of contain: + "nxp,pca85073a", "nxp,pcf85063", "nxp,pcf85063a", "nxp,pcf85063tp", diff --git a/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml new file mode 100644 index 000000000000..2d4741f51663 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/renesas,rzn1-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 SoCs Real-Time Clock DT bindings + +maintainers: + - Miquel Raynal <miquel.raynal@bootlin.com> + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-rtc + - const: renesas,rzn1-rtc + + reg: + maxItems: 1 + + interrupts: + minItems: 3 + maxItems: 3 + + interrupt-names: + items: + - const: alarm + - const: timer + - const: pps + + clocks: + maxItems: 1 + + clock-names: + const: hclk + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/r9a06g032-sysctrl.h> + rtc@40006000 { + compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; + reg = <0x40006000 0x1000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "alarm", "timer", "pps"; + clocks = <&sysctrl R9A06G032_HCLK_RTC>; + clock-names = "hclk"; + power-domains = <&sysctrl>; + start-year = <2000>; + }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index 2a4b6c06e7c9..f0f1bf06aea6 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -47,6 +47,10 @@ properties: - qcom,rpm-qcm2290 - qcom,rpm-qcs404 + clock-controller: + $ref: /schemas/clock/qcom,rpmcc.yaml# + unevaluatedProperties: false + qcom,smd-channels: $ref: /schemas/types.yaml#/definitions/string-array description: Channel name used for the RPM communication diff --git a/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml b/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml new file mode 100644 index 000000000000..dd168d41d2e0 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding + +maintainers: + - Sean Anderson <sean.anderson@seco.com> + +properties: + compatible: + contains: + const: xlnx,xps-timer-1.00.a + + clocks: + maxItems: 1 + + clock-names: + const: s_axi_aclk + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + '#pwm-cells': true + + xlnx,count-width: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16, 32] + default: 32 + description: + The width of the counter(s), in bits. + + xlnx,one-timer-only: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + description: + Whether only one timer is present in this block. + +required: + - compatible + - reg + - xlnx,one-timer-only + +allOf: + - if: + required: + - '#pwm-cells' + then: + allOf: + - required: + - clocks + - properties: + xlnx,one-timer-only: + const: 0 + else: + required: + - interrupts + - if: + required: + - clocks + then: + required: + - clock-names + +additionalProperties: false + +examples: + - | + timer@800e0000 { + clock-names = "s_axi_aclk"; + clocks = <&zynqmp_clk 71>; + compatible = "xlnx,xps-timer-1.00.a"; + reg = <0x800e0000 0x10000>; + interrupts = <0 39 2>; + xlnx,count-width = <16>; + xlnx,one-timer-only = <0x0>; + }; + + timer@800f0000 { + #pwm-cells = <0>; + clock-names = "s_axi_aclk"; + clocks = <&zynqmp_clk 71>; + compatible = "xlnx,xps-timer-1.00.a"; + reg = <0x800e0000 0x10000>; + xlnx,count-width = <32>; + xlnx,one-timer-only = <0x0>; + }; diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 05f01f4acca8..6aafa71806a3 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -47,7 +47,9 @@ properties: - at,24c08 # i2c trusted platform module (TPM) - atmel,at97sc3204t - # i2c h/w symmetric crypto module + # ATSHA204 - i2c h/w symmetric crypto module + - atmel,atsha204 + # ATSHA204A - i2c h/w symmetric crypto module - atmel,atsha204a # i2c h/w elliptic curve crypto module - atmel,atecc508a diff --git a/Documentation/devicetree/bindings/watchdog/da9062-wdt.txt b/Documentation/devicetree/bindings/watchdog/da9062-wdt.txt index 950e4fba8dbc..354314d854ef 100644 --- a/Documentation/devicetree/bindings/watchdog/da9062-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/da9062-wdt.txt @@ -10,6 +10,12 @@ Optional properties: - dlg,use-sw-pm: Add this property to disable the watchdog during suspend. Only use this option if you can't use the watchdog automatic suspend function during a suspend (see register CONTROL_B). +- dlg,wdt-sd: Set what happens on watchdog timeout. If this bit is set the + watchdog timeout triggers SHUTDOWN, if cleared the watchdog triggers + POWERDOWN. Can be 0 or 1. Only use this option if you want to change the + default chip's OTP setting for WATCHDOG_SD bit. If this property is NOT + set the WATCHDOG_SD bit and on timeout watchdog behavior will match the + chip's OTP settings. Example: DA9062 diff --git a/Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.txt b/Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.txt deleted file mode 100644 index 9ecdb502e605..000000000000 --- a/Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.txt +++ /dev/null @@ -1,22 +0,0 @@ -Faraday Technology FTWDT010 watchdog - -This is an IP part from Faraday Technology found in the Gemini -SoCs and others. - -Required properties: -- compatible : must be one of - "faraday,ftwdt010" - "cortina,gemini-watchdog", "faraday,ftwdt010" -- reg : shall contain base register location and length -- interrupts : shall contain the interrupt for the watchdog - -Optional properties: -- timeout-sec : the default watchdog timeout in seconds. - -Example: - -watchdog@41000000 { - compatible = "faraday,ftwdt010"; - reg = <0x41000000 0x1000>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.yaml b/Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.yaml new file mode 100644 index 000000000000..ca9e1beff76b --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/faraday,ftwdt010.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Faraday Technology FTWDT010 watchdog + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + - Corentin Labbe <clabbe@baylibre.com> + +description: | + This is an IP part from Faraday Technology found in the Gemini + SoCs and others. + +allOf: + - $ref: "watchdog.yaml#" + +properties: + compatible: + oneOf: + - const: faraday,ftwdt010 + - items: + - enum: + - cortina,gemini-watchdog + - moxa,moxart-watchdog + - const: faraday,ftwdt010 + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: PCLK + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + watchdog@41000000 { + compatible = "faraday,ftwdt010"; + reg = <0x41000000 0x1000>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + timeout-secs = <5>; + }; + - | + watchdog: watchdog@98500000 { + compatible = "moxa,moxart-watchdog", "faraday,ftwdt010"; + reg = <0x98500000 0x10>; + clocks = <&clk_apb>; + clock-names = "PCLK"; + }; +... diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml index 4ca8a31359a5..8562978aa0c8 100644 --- a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.yaml @@ -19,6 +19,7 @@ properties: - items: - const: fsl,imx8ulp-wdt - const: fsl,imx7ulp-wdt + - const: fsl,imx93-wdt reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index a97418c74f6b..762c62e428ef 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -16,6 +16,7 @@ Required properties: "mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629 "mediatek,mt7986-wdt", "mediatek,mt6589-wdt": for MT7986 "mediatek,mt8183-wdt": for MT8183 + "mediatek,mt8186-wdt", "mediatek,mt6589-wdt": for MT8186 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 "mediatek,mt8192-wdt": for MT8192 "mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195 diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml index 16c6f82a13ca..2bd6b4a52637 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml @@ -14,22 +14,29 @@ allOf: properties: compatible: - enum: - - qcom,apss-wdt-qcs404 - - qcom,apss-wdt-sc7180 - - qcom,apss-wdt-sc7280 - - qcom,apss-wdt-sdm845 - - qcom,apss-wdt-sdx55 - - qcom,apss-wdt-sm6350 - - qcom,apss-wdt-sm8150 - - qcom,apss-wdt-sm8250 - - qcom,kpss-timer - - qcom,kpss-wdt - - qcom,kpss-wdt-apq8064 - - qcom,kpss-wdt-ipq4019 - - qcom,kpss-wdt-ipq8064 - - qcom,kpss-wdt-msm8960 - - qcom,scss-timer + oneOf: + - items: + - enum: + - qcom,apss-wdt-qcs404 + - qcom,apss-wdt-sc7180 + - qcom,apss-wdt-sc7280 + - qcom,apss-wdt-sc8180x + - qcom,apss-wdt-sc8280xp + - qcom,apss-wdt-sdm845 + - qcom,apss-wdt-sdx55 + - qcom,apss-wdt-sm6350 + - qcom,apss-wdt-sm8150 + - qcom,apss-wdt-sm8250 + - const: qcom,kpss-wdt + - items: + - enum: + - qcom,kpss-wdt + - qcom,kpss-timer + - qcom,kpss-wdt-apq8064 + - qcom,kpss-wdt-ipq4019 + - qcom,kpss-wdt-ipq8064 + - qcom,kpss-wdt-msm8960 + - qcom,scss-timer reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml index d060438e1402..a8d7dde5271b 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml @@ -21,8 +21,15 @@ properties: - items: - enum: + - renesas,r9a06g032-wdt # RZ/N1D + - const: renesas,rzn1-wdt # RZ/N1 + + - items: + - enum: + - renesas,r9a07g043-wdt # RZ/G2UL - renesas,r9a07g044-wdt # RZ/G2{L,LC} - - const: renesas,rzg2l-wdt # RZ/G2L + - renesas,r9a07g054-wdt # RZ/V2L + - const: renesas,rzg2l-wdt - items: - enum: @@ -52,11 +59,11 @@ properties: - renesas,r8a77980-wdt # R-Car V3H - renesas,r8a77990-wdt # R-Car E3 - renesas,r8a77995-wdt # R-Car D3 - - renesas,r8a779a0-wdt # R-Car V3U - const: renesas,rcar-gen3-wdt # R-Car Gen3 and RZ/G2 - items: - enum: + - renesas,r8a779a0-wdt # R-Car V3U - renesas,r8a779f0-wdt # R-Car S4-8 - const: renesas,rcar-gen4-wdt # R-Car Gen4 @@ -94,6 +101,7 @@ allOf: contains: enum: - renesas,rza-wdt + - renesas,rzn1-wdt then: required: - power-domains diff --git a/Documentation/devicetree/bindings/watchdog/socionext,uniphier-wdt.yaml b/Documentation/devicetree/bindings/watchdog/socionext,uniphier-wdt.yaml index a059d16cb4f2..90698cfa8f94 100644 --- a/Documentation/devicetree/bindings/watchdog/socionext,uniphier-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/socionext,uniphier-wdt.yaml @@ -19,7 +19,7 @@ properties: required: - compatible -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/watchdog/sunplus,sp7021-wdt.yaml b/Documentation/devicetree/bindings/watchdog/sunplus,sp7021-wdt.yaml new file mode 100644 index 000000000000..d90271013191 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/sunplus,sp7021-wdt.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/sunplus,sp7021-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SoCs Watchdog + +maintainers: + - XianTao Hu <xt.hu@cqplus1.com> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + const: sunplus,sp7021-wdt + + reg: + items: + - description: watchdog registers regions + - description: miscellaneous control registers regions + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - resets + +additionalProperties: false + +examples: + - | + watchdog: watchdog@9c000630 { + compatible = "sunplus,sp7021-wdt"; + reg = <0x9c000630 0x08>, <0x9c000274 0x04>; + clocks = <&clkc 0x24>; + resets = <&rstc 0x14>; + }; +... |