diff options
Diffstat (limited to 'arch/arm/boot/dts/imx6q.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6q.dtsi | 136 |
1 files changed, 108 insertions, 28 deletions
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index bc581aa5cf17..8381d24eff7d 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -1,12 +1,6 @@ - -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2013 Freescale Semiconductor, Inc. #include <dt-bindings/interrupt-controller/irq.h> #include "imx6q-pinfunc.h" @@ -44,6 +38,7 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6QDL_CLK_ARM>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, @@ -56,25 +51,106 @@ soc-supply = <®_soc>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <2>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <3>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 852000 1250000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_STEP>, + <&clks IMX6QDL_CLK_PLL1_SW>, + <&clks IMX6QDL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; }; @@ -87,7 +163,7 @@ aips-bus@2000000 { /* AIPS1 */ spba-bus@2000000 { - ecspi5: ecspi@2018000 { + ecspi5: spi@2018000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; @@ -96,7 +172,7 @@ clocks = <&clks IMX6Q_CLK_ECSPI5>, <&clks IMX6Q_CLK_ECSPI5>; clock-names = "ipg", "per"; - dmas = <&sdma 11 7 1>, <&sdma 12 7 2>; + dmas = <&sdma 11 8 1>, <&sdma 12 8 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -162,22 +238,27 @@ #size-cells = <0>; reg = <2>; - ipu2_di0_disp0: disp0-endpoint { + ipu2_di0_disp0: endpoint@0 { + reg = <0>; }; - ipu2_di0_hdmi: hdmi-endpoint { + ipu2_di0_hdmi: endpoint@1 { + reg = <1>; remote-endpoint = <&hdmi_mux_2>; }; - ipu2_di0_mipi: mipi-endpoint { + ipu2_di0_mipi: endpoint@2 { + reg = <2>; remote-endpoint = <&mipi_mux_2>; }; - ipu2_di0_lvds0: lvds0-endpoint { + ipu2_di0_lvds0: endpoint@3 { + reg = <3>; remote-endpoint = <&lvds0_mux_2>; }; - ipu2_di0_lvds1: lvds1-endpoint { + ipu2_di0_lvds1: endpoint@4 { + reg = <4>; remote-endpoint = <&lvds1_mux_2>; }; }; @@ -187,19 +268,23 @@ #size-cells = <0>; reg = <3>; - ipu2_di1_hdmi: hdmi-endpoint { + ipu2_di1_hdmi: endpoint@1 { + reg = <1>; remote-endpoint = <&hdmi_mux_3>; }; - ipu2_di1_mipi: mipi-endpoint { + ipu2_di1_mipi: endpoint@2 { + reg = <2>; remote-endpoint = <&mipi_mux_3>; }; - ipu2_di1_lvds0: lvds0-endpoint { + ipu2_di1_lvds0: endpoint@3 { + reg = <3>; remote-endpoint = <&lvds0_mux_3>; }; - ipu2_di1_lvds1: lvds1-endpoint { + ipu2_di1_lvds1: endpoint@4 { + reg = <4>; remote-endpoint = <&lvds1_mux_3>; }; }; @@ -215,11 +300,6 @@ compatible = "fsl,imx-display-subsystem"; ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; }; - - gpu-subsystem { - compatible = "fsl,imx-gpu-subsystem"; - cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>; - }; }; &gpio1 { |