diff options
Diffstat (limited to 'arch/arm/boot/dts/imx6ul.dtsi')
-rw-r--r-- | arch/arm/boot/dts/imx6ul.dtsi | 116 |
1 files changed, 87 insertions, 29 deletions
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 5d6c3ba36cd1..083d3446c41d 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -1,10 +1,6 @@ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2015 Freescale Semiconductor, Inc. #include <dt-bindings/clock/imx6ul-clock.h> #include <dt-bindings/gpio/gpio.h> @@ -22,7 +18,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; reg = <0 0>; }; + memory { device_type = "memory"; }; aliases { ethernet0 = &fec1; @@ -66,6 +62,7 @@ device_type = "cpu"; reg = <0>; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; operating-points = < /* kHz uV */ 696000 1275000 @@ -86,30 +83,39 @@ <&clks IMX6UL_CA7_SECONDARY_SEL>, <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_PLL1_SW>, - <&clks IMX6UL_CLK_PLL1_SYS>, - <&clks IMX6UL_PLL1_BYPASS>, - <&clks IMX6UL_CLK_PLL1>, - <&clks IMX6UL_PLL1_BYPASS_SRC>, - <&clks IMX6UL_CLK_OSC>; + <&clks IMX6UL_CLK_PLL1_SYS>; clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", "secondary_sel", "step", "pll1_sw", - "pll1_sys", "pll1_bypass", "pll1", - "pll1_bypass_src", "osc"; + "pll1_sys"; arm-supply = <®_arm>; soc-supply = <®_soc>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; }; }; intc: interrupt-controller@a01000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; #interrupt-cells = <3>; interrupt-controller; + interrupt-parent = <&intc>; reg = <0x00a01000 0x1000>, <0x00a02000 0x2000>, <0x00a04000 0x2000>, <0x00a06000 0x2000>; }; + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-parent = <&intc>; + status = "disabled"; + }; + ckil: clock-cli { compatible = "fixed-clock"; #clock-cells = <0>; @@ -152,7 +158,6 @@ compatible = "arm,cortex-a7-pmu"; interrupt-parent = <&gpc>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; }; soc { @@ -214,7 +219,7 @@ reg = <0x02000000 0x40000>; ranges; - ecspi1: ecspi@2008000 { + ecspi1: spi@2008000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; @@ -226,7 +231,7 @@ status = "disabled"; }; - ecspi2: ecspi@200c000 { + ecspi2: spi@200c000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; @@ -238,7 +243,7 @@ status = "disabled"; }; - ecspi3: ecspi@2010000 { + ecspi3: spi@2010000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; @@ -250,7 +255,7 @@ status = "disabled"; }; - ecspi4: ecspi@2014000 { + ecspi4: spi@2014000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; @@ -430,6 +435,7 @@ reg = <0x0209c000 0x4000>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_GPIO1>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -443,6 +449,7 @@ reg = <0x020a0000 0x4000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_GPIO2>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -455,6 +462,7 @@ reg = <0x020a4000 0x4000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_GPIO3>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -467,6 +475,7 @@ reg = <0x020a8000 0x4000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_GPIO4>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -479,6 +488,7 @@ reg = <0x020ac000 0x4000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_GPIO5>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -544,11 +554,8 @@ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - reg_3p0: regulator-3p0@20c8110 { - reg = <0x20c8110>; + reg_3p0: regulator-3p0 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; regulator-min-microvolt = <2625000>; @@ -562,8 +569,7 @@ anatop-enable-bit = <0>; }; - reg_arm: regulator-vddcore@20c8140 { - reg = <0x20c8140>; + reg_arm: regulator-vddcore { compatible = "fsl,anatop-regulator"; regulator-name = "cpu"; regulator-min-microvolt = <725000>; @@ -580,8 +586,7 @@ anatop-max-voltage = <1450000>; }; - reg_soc: regulator-vddsoc@20c8140 { - reg = <0x20c8140>; + reg_soc: regulator-vddsoc { compatible = "fsl,anatop-regulator"; regulator-name = "vddsoc"; regulator-min-microvolt = <725000>; @@ -762,6 +767,36 @@ reg = <0x02100000 0x100000>; ranges; + crypto: caam@2140000 { + compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x2140000 0x3c000>; + ranges = <0 0x2140000 0x3c000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>, + <&clks IMX6UL_CLK_CAAM_MEM>; + clock-names = "ipg", "aclk", "mem"; + + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr2@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + usbotg1: usb@2184000 { compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; @@ -884,6 +919,17 @@ reg = <0x021b0000 0x4000>; }; + weim: weim@21b8000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; + reg = <0x021b8000 0x4000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_EIM>; + fsl,weim-cs-gpr = <&gpr>; + status = "disabled"; + }; + ocotp: ocotp-ctrl@21bc000 { #address-cells = <1>; #size-cells = <1>; @@ -898,6 +944,10 @@ tempmon_temp_grade: temp-grade@20 { reg = <0x20 4>; }; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; }; lcdif: lcdif@21c8000 { @@ -911,7 +961,7 @@ status = "disabled"; }; - qspi: qspi@21e0000 { + qspi: spi@21e0000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; @@ -924,6 +974,14 @@ status = "disabled"; }; + wdog3: wdog@21e4000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x021e4000 0x4000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_WDOG3>; + status = "disabled"; + }; + uart2: serial@21e8000 { compatible = "fsl,imx6ul-uart", "fsl,imx6q-uart"; |