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Diffstat (limited to 'arch/arm/boot/dts/qcom-apq8064.dtsi')
-rw-r--r--arch/arm/boot/dts/qcom-apq8064.dtsi192
1 files changed, 134 insertions, 58 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 3ca96e361878..48c3cf427610 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -316,6 +316,23 @@
};
};
+
+ /*
+ * These channels from the ADC are simply hardware monitors.
+ * That is why the ADC is referred to as "HKADC" - HouseKeeping
+ * ADC.
+ */
+ iio-hwmon {
+ compatible = "iio-hwmon";
+ io-channels = <&xoadc 0x00 0x01>, /* Battery */
+ <&xoadc 0x00 0x02>, /* DC in (charger) */
+ <&xoadc 0x00 0x04>, /* VPH the main system voltage */
+ <&xoadc 0x00 0x0b>, /* Die temperature */
+ <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
+ <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
+ <&xoadc 0x00 0x0e>; /* Charger temperature */
+ };
+
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -427,7 +444,7 @@
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x12450000 0x100>,
<0x12400000 0x03>;
- interrupts = <0 193 0x0>;
+ interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
@@ -439,11 +456,12 @@
pinctrl-1 = <&i2c1_pins_sleep>;
pinctrl-names = "default", "sleep";
reg = <0x12460000 0x1000>;
- interrupts = <0 194 IRQ_TYPE_NONE>;
+ interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
};
@@ -467,11 +485,12 @@
pinctrl-0 = <&i2c2_pins>;
pinctrl-1 = <&i2c2_pins_sleep>;
pinctrl-names = "default", "sleep";
- interrupts = <0 196 IRQ_TYPE_NONE>;
+ interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
};
@@ -491,12 +510,13 @@
pinctrl-1 = <&i2c3_pins_sleep>;
pinctrl-names = "default", "sleep";
reg = <0x16280000 0x1000>;
- interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI3_QUP_CLK>,
<&gcc GSBI3_H_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
};
@@ -517,10 +537,11 @@
pinctrl-1 = <&i2c4_pins_sleep>;
pinctrl-names = "default", "sleep";
reg = <0x16380000 0x1000>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI4_QUP_CLK>,
<&gcc GSBI4_H_CLK>;
clock-names = "core", "iface";
+ status = "disabled";
};
};
@@ -539,7 +560,7 @@
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x1a240000 0x100>,
<0x1a200000 0x03>;
- interrupts = <0 154 0x0>;
+ interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
@@ -548,7 +569,7 @@
gsbi5_spi: spi@1a280000 {
compatible = "qcom,spi-qup-v1.1.1";
reg = <0x1a280000 0x1000>;
- interrupts = <0 155 0>;
+ interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&spi5_default>;
pinctrl-1 = <&spi5_sleep>;
pinctrl-names = "default", "sleep";
@@ -575,7 +596,7 @@
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16540000 0x100>,
<0x16500000 0x03>;
- interrupts = <0 156 0x0>;
+ interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
@@ -587,7 +608,7 @@
pinctrl-1 = <&i2c6_pins_sleep>;
pinctrl-names = "default", "sleep";
reg = <0x16580000 0x1000>;
- interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI6_QUP_CLK>,
<&gcc GSBI6_H_CLK>;
clock-names = "core", "iface";
@@ -611,7 +632,7 @@
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
reg = <0x16640000 0x1000>,
<0x16600000 0x1000>;
- interrupts = <0 158 0x0>;
+ interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
@@ -623,7 +644,7 @@
pinctrl-1 = <&i2c7_pins_sleep>;
pinctrl-names = "default", "sleep";
reg = <0x16680000 0x1000>;
- interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI7_QUP_CLK>,
<&gcc GSBI7_H_CLK>;
clock-names = "core", "iface";
@@ -770,6 +791,52 @@
debounce = <15625>;
pull-up;
};
+
+ xoadc: xoadc@197 {
+ compatible = "qcom,pm8921-adc";
+ reg = <197>;
+ interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ #io-channel-cells = <2>;
+
+ vcoin: adc-channel@00 {
+ reg = <0x00 0x00>;
+ };
+ vbat: adc-channel@01 {
+ reg = <0x00 0x01>;
+ };
+ dcin: adc-channel@02 {
+ reg = <0x00 0x02>;
+ };
+ vph_pwr: adc-channel@04 {
+ reg = <0x00 0x04>;
+ };
+ batt_therm: adc-channel@08 {
+ reg = <0x00 0x08>;
+ };
+ batt_id: adc-channel@09 {
+ reg = <0x00 0x09>;
+ };
+ usb_vbus: adc-channel@0a {
+ reg = <0x00 0x0a>;
+ };
+ die_temp: adc-channel@0b {
+ reg = <0x00 0x0b>;
+ };
+ ref_625mv: adc-channel@0c {
+ reg = <0x00 0x0c>;
+ };
+ ref_1250mv: adc-channel@0d {
+ reg = <0x00 0x0d>;
+ };
+ chg_temp: adc-channel@0e {
+ reg = <0x00 0x0e>;
+ };
+ ref_muxoff: adc-channel@0f {
+ reg = <0x00 0x0f>;
+ };
+ };
};
};
@@ -993,7 +1060,7 @@
compatible = "qcom,apq8064-ahci", "generic-ahci";
status = "disabled";
reg = <0x29000000 0x180>;
- interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SFAB_SATA_S_H_CLK>,
<&gcc SATA_H_CLK>,
@@ -1019,7 +1086,7 @@
sdcc1bam:dma@12402000{
compatible = "qcom,bam-v1.3.0";
reg = <0x12402000 0x8000>;
- interrupts = <0 98 0>;
+ interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC1_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -1029,7 +1096,7 @@
sdcc3bam:dma@12182000{
compatible = "qcom,bam-v1.3.0";
reg = <0x12182000 0x8000>;
- interrupts = <0 96 0>;
+ interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC3_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -1039,7 +1106,7 @@
sdcc4bam:dma@121c2000{
compatible = "qcom,bam-v1.3.0";
reg = <0x121c2000 0x8000>;
- interrupts = <0 95 0>;
+ interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc SDC4_H_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -1118,7 +1185,7 @@
compatible = "qcom,adreno-3xx";
reg = <0x04300000 0x20000>;
reg-names = "kgsl_3d0_reg_memory";
- interrupts = <GIC_SPI 80 0>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "kgsl_3d0_irq";
clock-names =
"core_clk",
@@ -1218,7 +1285,7 @@
label = "MDSS DSI CTRL->0";
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 82 0>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x04700000 0x200>;
reg-names = "dsi_ctrl";
@@ -1287,8 +1354,8 @@
<&mmcc MDP_AXI_CLK>;
reg = <0x07500000 0x100000>;
interrupts =
- <GIC_SPI 63 0>,
- <GIC_SPI 64 0>;
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
qcom,ncb = <2>;
};
@@ -1303,8 +1370,8 @@
<&mmcc MDP_AXI_CLK>;
reg = <0x07600000 0x100000>;
interrupts =
- <GIC_SPI 61 0>,
- <GIC_SPI 62 0>;
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
qcom,ncb = <2>;
};
@@ -1319,8 +1386,8 @@
<&mmcc GFX3D_AXI_CLK>;
reg = <0x07c00000 0x100000>;
interrupts =
- <GIC_SPI 69 0>,
- <GIC_SPI 70 0>;
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
qcom,ncb = <3>;
};
@@ -1335,8 +1402,8 @@
<&mmcc GFX3D_AXI_CLK>;
reg = <0x07d00000 0x100000>;
interrupts =
- <GIC_SPI 210 0>,
- <GIC_SPI 211 0>;
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
qcom,ncb = <3>;
};
@@ -1354,8 +1421,8 @@
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
- 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
- interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
+ 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@@ -1544,10 +1611,11 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- port {
- etb_in: endpoint {
- slave-mode;
- remote-endpoint = <&replicator_out0>;
+ in-ports {
+ port {
+ etb_in: endpoint {
+ remote-endpoint = <&replicator_out0>;
+ };
};
};
};
@@ -1559,10 +1627,11 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- port {
- tpiu_in: endpoint {
- slave-mode;
- remote-endpoint = <&replicator_out1>;
+ in-ports {
+ port {
+ tpiu_in: endpoint {
+ remote-endpoint = <&replicator_out1>;
+ };
};
};
};
@@ -1573,7 +1642,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- ports {
+ out-ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1589,10 +1658,11 @@
remote-endpoint = <&tpiu_in>;
};
};
- port@2 {
- reg = <0>;
+ };
+
+ in-ports {
+ port {
replicator_in: endpoint {
- slave-mode;
remote-endpoint = <&funnel_out>;
};
};
@@ -1606,7 +1676,7 @@
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
- ports {
+ in-ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1620,33 +1690,31 @@
port@0 {
reg = <0>;
funnel_in0: endpoint {
- slave-mode;
remote-endpoint = <&etm0_out>;
};
};
port@1 {
reg = <1>;
funnel_in1: endpoint {
- slave-mode;
remote-endpoint = <&etm1_out>;
};
};
port@4 {
reg = <4>;
funnel_in4: endpoint {
- slave-mode;
remote-endpoint = <&etm2_out>;
};
};
port@5 {
reg = <5>;
funnel_in5: endpoint {
- slave-mode;
remote-endpoint = <&etm3_out>;
};
};
- port@8 {
- reg = <0>;
+ };
+
+ out-ports {
+ port {
funnel_out: endpoint {
remote-endpoint = <&replicator_in>;
};
@@ -1663,9 +1731,11 @@
cpu = <&CPU0>;
- port {
- etm0_out: endpoint {
- remote-endpoint = <&funnel_in0>;
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint = <&funnel_in0>;
+ };
};
};
};
@@ -1679,9 +1749,11 @@
cpu = <&CPU1>;
- port {
- etm1_out: endpoint {
- remote-endpoint = <&funnel_in1>;
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint = <&funnel_in1>;
+ };
};
};
};
@@ -1695,9 +1767,11 @@
cpu = <&CPU2>;
- port {
- etm2_out: endpoint {
- remote-endpoint = <&funnel_in4>;
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint = <&funnel_in4>;
+ };
};
};
};
@@ -1711,9 +1785,11 @@
cpu = <&CPU3>;
- port {
- etm3_out: endpoint {
- remote-endpoint = <&funnel_in5>;
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint = <&funnel_in5>;
+ };
};
};
};
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-11 17:10:00 +0300