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-rw-r--r--arch/arm/boot/dts/am33xx-l4.dtsi6
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi20
-rw-r--r--arch/arm/boot/dts/am3517.dtsi24
-rw-r--r--arch/arm/boot/dts/am4372.dtsi20
-rw-r--r--arch/arm/boot/dts/am437x-l4.dtsi7
-rw-r--r--arch/arm/boot/dts/dm814x.dtsi74
-rw-r--r--arch/arm/boot/dts/dm816x.dtsi78
-rw-r--r--arch/arm/boot/dts/dra7-l4.dtsi7
-rw-r--r--arch/arm/boot/dts/dra7.dtsi10
-rw-r--r--arch/arm/boot/dts/omap2.dtsi31
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi68
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi68
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts33
-rw-r--r--arch/arm/boot/dts/omap3-devkit8000.dts33
-rw-r--r--arch/arm/boot/dts/omap3.dtsi134
-rw-r--r--arch/arm/boot/dts/omap4-l4.dtsi4
-rw-r--r--arch/arm/boot/dts/omap4.dtsi10
-rw-r--r--arch/arm/boot/dts/omap5-l4.dtsi4
-rw-r--r--arch/arm/boot/dts/omap5.dtsi10
19 files changed, 542 insertions, 99 deletions
diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi
index 5ed7f3c58c0f..7ff11d6bf0f2 100644
--- a/arch/arm/boot/dts/am33xx-l4.dtsi
+++ b/arch/arm/boot/dts/am33xx-l4.dtsi
@@ -330,9 +330,8 @@
};
};
- target-module@31000 { /* 0x44e31000, ap 25 40.0 */
+ timer1_target: target-module@31000 { /* 0x44e31000, ap 25 40.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
- ti,hwmods = "timer1";
reg = <0x31000 0x4>,
<0x31010 0x4>,
<0x31014 0x4>;
@@ -1117,9 +1116,8 @@
};
};
- target-module@40000 { /* 0x48040000, ap 22 1e.0 */
+ timer2_target: target-module@40000 { /* 0x48040000, ap 22 1e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer2";
reg = <0x40000 0x4>,
<0x40010 0x4>,
<0x40014 0x4>;
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index a35f5052d76f..3b177c9c4412 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -619,3 +619,23 @@
#reset-cells = <1>;
};
};
+
+/* Preferred always-on timer for clocksource */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&timer1_fck>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+ };
+};
+
+/* Preferred timer for clockevent */
+&timer2_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&timer2_fck>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index e0b5a00e2078..dc8927f14b6c 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -169,5 +169,25 @@
status = "disabled";
};
-/include/ "am35xx-clocks.dtsi"
-/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+#include "am35xx-clocks.dtsi"
+#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
+
+/* Preferred always-on timer for clocksource */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&gpt1_fck>;
+ assigned-clock-parents = <&sys_ck>;
+ };
+};
+
+/* Preferred timer for clockevent */
+&timer2_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&gpt2_fck>;
+ assigned-clock-parents = <&sys_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index dba87bfaf33e..b4861f70f178 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -553,3 +553,23 @@
#reset-cells = <1>;
};
};
+
+/* Preferred always-on timer for clocksource */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&timer1_fck>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+ };
+};
+
+/* Preferred timer for clockevent */
+&timer2_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&timer2_fck>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi
index 49c6a872052e..0d0f9fe4a882 100644
--- a/arch/arm/boot/dts/am437x-l4.dtsi
+++ b/arch/arm/boot/dts/am437x-l4.dtsi
@@ -328,9 +328,8 @@
};
};
- target-module@31000 { /* 0x44e31000, ap 24 40.0 */
+ timer1_target: target-module@31000 { /* 0x44e31000, ap 24 40.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
- ti,hwmods = "timer1";
reg = <0x31000 0x4>,
<0x31010 0x4>,
<0x31014 0x4>;
@@ -450,7 +449,6 @@
target-module@86000 { /* 0x44e86000, ap 40 70.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "counter_32k";
reg = <0x86000 0x4>,
<0x86004 0x4>;
reg-names = "rev", "sysc";
@@ -868,9 +866,8 @@
};
};
- target-module@40000 { /* 0x48040000, ap 18 1e.0 */
+ timer2_target: target-module@40000 { /* 0x48040000, ap 18 1e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer2";
reg = <0x40000 0x4>,
<0x40010 0x4>,
<0x40014 0x4>;
diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi
index c28ca0540f03..7702e048e110 100644
--- a/arch/arm/boot/dts/dm814x.dtsi
+++ b/arch/arm/boot/dts/dm814x.dtsi
@@ -308,14 +308,30 @@
ti,hwmods = "mcspi4";
};
- timer1: timer@2e000 {
- compatible = "ti,dm814-timer";
- reg = <0x2e000 0x2000>;
- interrupts = <67>;
- ti,hwmods = "timer1";
- ti,timer-alwon;
+ timer1_target: target-module@2e000 {
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x2e000 0x4>,
+ <0x2e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
clocks = <&timer1_fck>;
clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x2e000 0x1000>;
+
+ timer1: timer@0 {
+ compatible = "ti,am335x-timer-1ms";
+ reg = <0x0 0x400>;
+ interrupts = <67>;
+ ti,timer-alwon;
+ clocks = <&timer1_fck>;
+ clock-names = "fck";
+ };
};
uart1: uart@20000 {
@@ -348,13 +364,29 @@
dma-names = "tx", "rx";
};
- timer2: timer@40000 {
- compatible = "ti,dm814-timer";
- reg = <0x40000 0x2000>;
- interrupts = <68>;
- ti,hwmods = "timer2";
+ timer2_target: target-module@40000 {
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x40000 0x4>,
+ <0x40010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
clocks = <&timer2_fck>;
clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x40000 0x1000>;
+
+ timer2: timer@0 {
+ compatible = "ti,dm814-timer";
+ reg = <0 0x1000>;
+ interrupts = <68>;
+ clocks = <&timer2_fck>;
+ clock-names = "fck";
+ };
};
timer3: timer@42000 {
@@ -735,3 +767,23 @@
};
#include "dm814x-clocks.dtsi"
+
+/* Preferred always-on timer for clocksource */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&timer1_fck>;
+ assigned-clock-parents = <&devosc_ck>;
+ };
+};
+
+/* Preferred timer for clockevent */
+&timer2_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&timer2_fck>;
+ assigned-clock-parents = <&devosc_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index 2a4934b60ded..3551a64963f8 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -440,23 +440,55 @@
dma-names = "tx", "rx";
};
- timer1: timer@4802e000 {
- compatible = "ti,dm816-timer";
- reg = <0x4802e000 0x2000>;
- interrupts = <67>;
- ti,hwmods = "timer1";
- ti,timer-alwon;
- clocks = <&timer1_fck>;
+ timer1_target: target-module@4802e000 {
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x4802e000 0x4>,
+ <0x4802e010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4802e000 0x1000>;
+
+ timer1: timer@0 {
+ compatible = "ti,dm816-timer";
+ reg = <0 0x1000>;
+ interrupts = <67>;
+ ti,timer-alwon;
+ clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
+ clock-names = "fck";
+ };
};
- timer2: timer@48040000 {
- compatible = "ti,dm816-timer";
- reg = <0x48040000 0x2000>;
- interrupts = <68>;
- ti,hwmods = "timer2";
- clocks = <&timer2_fck>;
+ timer2_target: target-module@48040000 {
+ compatible = "ti,sysc-omap4-timer", "ti,sysc";
+ reg = <0x48040000 0x4>,
+ <0x48040010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x48040000 0x1000>;
+
+ timer2: timer@0 {
+ compatible = "ti,dm816-timer";
+ reg = <0 0x1000>;
+ interrupts = <68>;
+ clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
+ clock-names = "fck";
+ };
};
timer3: timer@48042000 {
@@ -642,3 +674,23 @@
};
#include "dm816x-clocks.dtsi"
+
+/* Preferred always-on timer for clocksource */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&timer1_fck>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+ };
+};
+
+/* Preferred timer for clockevent */
+&timer2_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&timer2_fck>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
index 2119a78e9c15..fc728c606eef 100644
--- a/arch/arm/boot/dts/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -1143,7 +1143,6 @@
target-module@32000 { /* 0x48032000, ap 5 3e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer2";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
@@ -1171,7 +1170,6 @@
target-module@34000 { /* 0x48034000, ap 7 46.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer3";
reg = <0x34000 0x4>,
<0x34010 0x4>;
reg-names = "rev", "sysc";
@@ -1199,7 +1197,6 @@
target-module@36000 { /* 0x48036000, ap 9 4e.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer4";
reg = <0x36000 0x4>,
<0x36010 0x4>;
reg-names = "rev", "sysc";
@@ -4295,7 +4292,6 @@
target-module@4000 { /* 0x4ae04000, ap 15 40.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "counter_32k";
reg = <0x4000 0x4>,
<0x4010 0x4>;
reg-names = "rev", "sysc";
@@ -4430,9 +4426,8 @@
};
};
- target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
+ timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer1";
reg = <0x8000 0x4>,
<0x8010 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 7191ee6a1b82..15225a39b28c 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1044,3 +1044,13 @@
reg = <0x1c00 0x60>;
};
};
+
+/* Preferred always-on timer for clockevent */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
+ assigned-clock-parents = <&sys_32k_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 0e453fec2e3a..8a5cb44bfe2f 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -201,11 +201,32 @@
clock-frequency = <48000000>;
};
- timer2: timer@4802a000 {
- compatible = "ti,omap2420-timer";
- reg = <0x4802a000 0x400>;
- interrupts = <38>;
- ti,hwmods = "timer2";
+ timer2_target: target-module@4802a000 {
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x4802a000 0x4>,
+ <0x4802a010 0x4>,
+ <0x4802a014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&gpt2_fck>, <&gpt2_ick>;
+ clock-names = "fck", "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4802a000 0x1000>;
+
+ timer2: timer@0 {
+ compatible = "ti,omap2420-timer";
+ reg = <0 0x400>;
+ interrupts = <38>;
+ };
};
timer3: timer@48078000 {
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index aba542d63d6d..6c5c7c0e8b94 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -68,10 +68,23 @@
};
};
- counter32k: counter@4000 {
- compatible = "ti,omap-counter32k";
- reg = <0x4000 0x20>;
- ti,hwmods = "counter_32k";
+ target-module@4000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x4000 0x4>,
+ <0x4004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ clocks = <&func_32k_ck>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x4000 0x1000>;
+
+ counter32k: counter@0 {
+ compatible = "ti,omap-counter32k";
+ reg = <0 0x20>;
+ };
};
};
@@ -194,12 +207,33 @@
};
};
- timer1: timer@48028000 {
- compatible = "ti,omap2420-timer";
- reg = <0x48028000 0x400>;
- interrupts = <37>;
- ti,hwmods = "timer1";
- ti,timer-alwon;
+ timer1_target: target-module@48028000 {
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x48028000 0x4>,
+ <0x48028010 0x4>,
+ <0x48028014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&gpt1_fck>, <&gpt1_ick>;
+ clock-names = "fck", "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x48028000 0x1000>;
+
+ timer1: timer@0 {
+ compatible = "ti,omap2420-timer";
+ reg = <0 0x400>;
+ interrupts = <37>;
+ ti,timer-alwon;
+ };
};
wd_timer2: wdt@48022000 {
@@ -218,5 +252,15 @@
compatible = "ti,omap2420-i2c";
};
-/include/ "omap24xx-clocks.dtsi"
-/include/ "omap2420-clocks.dtsi"
+#include "omap24xx-clocks.dtsi"
+#include "omap2420-clocks.dtsi"
+
+/* Preferred always-on timer for clockevent */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&gpt1_fck>;
+ assigned-clock-parents = <&func_32k_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 15ef7593be12..6a1f5bb3c06a 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -81,10 +81,23 @@
};
};
- counter32k: counter@20000 {
- compatible = "ti,omap-counter32k";
- reg = <0x20000 0x20>;
- ti,hwmods = "counter_32k";
+ target-module@20000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x20000 0x4>,
+ <0x20004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ clocks = <&func_32k_ck>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x20000 0x1000>;
+
+ counter32k: counter@0 {
+ compatible = "ti,omap-counter32k";
+ reg = <0 0x20>;
+ };
};
};
@@ -277,12 +290,33 @@
};
};
- timer1: timer@49018000 {
- compatible = "ti,omap2420-timer";
- reg = <0x49018000 0x400>;
- interrupts = <37>;
- ti,hwmods = "timer1";
- ti,timer-alwon;
+ timer1_target: target-module@49018000 {
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x49018000 0x4>,
+ <0x49018010 0x4>,
+ <0x49018014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&gpt1_fck>, <&gpt1_ick>;
+ clock-names = "fck", "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49018000 0x1000>;
+
+ timer1: timer@0 {
+ compatible = "ti,omap2420-timer";
+ reg = <0 0x400>;
+ interrupts = <37>;
+ ti,timer-alwon;
+ };
};
mcspi3: spi@480b8000 {
@@ -321,5 +355,15 @@
compatible = "ti,omap2430-i2c";
};
-/include/ "omap24xx-clocks.dtsi"
-/include/ "omap2430-clocks.dtsi"
+#include "omap24xx-clocks.dtsi"
+#include "omap2430-clocks.dtsi"
+
+/* Preferred always-on timer for clockevent */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&gpt1_fck>;
+ assigned-clock-parents = <&func_32k_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 4ed3f93f5841..dfa158647d91 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -304,6 +304,39 @@
phys = <0 &hsusb2_phy>;
};
+/* Unusable as clocksource because of unreliable oscillator */
+&counter32k {
+ status = "disabled";
+};
+
+/* Unusable as clockevent because if unreliable oscillator, allow to idle */
+&timer1_target {
+ /delete-property/ti,no-reset-on-init;
+ /delete-property/ti,no-idle;
+ timer@0 {
+ /delete-property/ti,timer-alwon;
+ };
+};
+
+/* Preferred always-on timer for clocksource */
+&timer12_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ /* Always clocked by secure_32k_fck */
+ };
+};
+
+/* Preferred timer for clockevent */
+&timer2_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&gpt2_fck>;
+ assigned-clock-parents = <&sys_ck>;
+ };
+};
+
&twl_gpio {
ti,use-leds;
/* pullups: BIT(1) */
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 162d0726b008..c2995a280729 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -14,3 +14,36 @@
display2 = &tv0;
};
};
+
+/* Unusable as clocksource because of unreliable oscillator */
+&counter32k {
+ status = "disabled";
+};
+
+/* Unusable as clockevent because if unreliable oscillator, allow to idle */
+&timer1_target {
+ /delete-property/ti,no-reset-on-init;
+ /delete-property/ti,no-idle;
+ timer@0 {
+ /delete-property/ti,timer-alwon;
+ };
+};
+
+/* Preferred always-on timer for clocksource */
+&timer12_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ /* Always clocked by secure_32k_fck */
+ };
+};
+
+/* Preferred timer for clockevent */
+&timer2_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&gpt2_fck>;
+ assigned-clock-parents = <&sys_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 634ea16a711e..1296d0643943 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -193,10 +193,23 @@
};
};
- counter32k: counter@48320000 {
- compatible = "ti,omap-counter32k";
- reg = <0x48320000 0x20>;
- ti,hwmods = "counter_32k";
+ target-module@48320000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x48320000 0x4>,
+ <0x48320004 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>;
+ clocks = <&wkup_32k_fck>, <&omap_32ksync_ick>;
+ clock-names = "fck", "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x48320000 0x1000>;
+
+ counter32k: counter@0 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x0 0x20>;
+ };
};
intc: interrupt-controller@48200000 {
@@ -637,19 +650,63 @@
dma-names = "rx";
};
- timer1: timer@48318000 {
- compatible = "ti,omap3430-timer";
- reg = <0x48318000 0x400>;
- interrupts = <37>;
- ti,hwmods = "timer1";
- ti,timer-alwon;
+ timer1_target: target-module@48318000 {
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x48318000 0x4>,
+ <0x48318010 0x4>,
+ <0x48318014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&gpt1_fck>, <&gpt1_ick>;
+ clock-names = "fck", "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x48318000 0x1000>;
+
+ timer1: timer@0 {
+ compatible = "ti,omap3430-timer";
+ reg = <0x0 0x80>;
+ clocks = <&gpt1_fck>;
+ clock-names = "fck";
+ interrupts = <37>;
+ ti,timer-alwon;
+ };
};
- timer2: timer@49032000 {
- compatible = "ti,omap3430-timer";
- reg = <0x49032000 0x400>;
- interrupts = <38>;
- ti,hwmods = "timer2";
+ timer2_target: target-module@49032000 {
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x49032000 0x4>,
+ <0x49032010 0x4>,
+ <0x49032014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&gpt2_fck>, <&gpt2_ick>;
+ clock-names = "fck", "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x49032000 0x1000>;
+
+ timer2: timer@0 {
+ compatible = "ti,omap3430-timer";
+ reg = <0 0x400>;
+ interrupts = <38>;
+ };
};
timer3: timer@49034000 {
@@ -723,13 +780,34 @@
ti,timer-pwm;
};
- timer12: timer@48304000 {
- compatible = "ti,omap3430-timer";
- reg = <0x48304000 0x400>;
- interrupts = <95>;
- ti,hwmods = "timer12";
- ti,timer-alwon;
- ti,timer-secure;
+ timer12_target: target-module@48304000 {
+ compatible = "ti,sysc-omap2-timer", "ti,sysc";
+ reg = <0x48304000 0x4>,
+ <0x48304010 0x4>,
+ <0x48304014 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_EMUFREE |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&gpt12_fck>, <&gpt12_ick>;
+ clock-names = "fck", "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x48304000 0x1000>;
+
+ timer12: timer@0 {
+ compatible = "ti,omap3430-timer";
+ reg = <0 0x400>;
+ interrupts = <95>;
+ ti,timer-alwon;
+ ti,timer-secure;
+ };
};
usbhstll: usbhstll@48062000 {
@@ -886,4 +964,14 @@
};
};
-/include/ "omap3xxx-clocks.dtsi"
+#include "omap3xxx-clocks.dtsi"
+
+/* Preferred always-on timer for clockevent. Some boards must use dmtimer12 */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&gpt1_fck>;
+ assigned-clock-parents = <&omap_32k_fck>;
+ };
+};
diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi
index ef59e4e97d7c..fcc52121ff09 100644
--- a/arch/arm/boot/dts/omap4-l4.dtsi
+++ b/arch/arm/boot/dts/omap4-l4.dtsi
@@ -974,7 +974,6 @@
target-module@4000 { /* 0x4a304000, ap 17 24.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "counter_32k";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
@@ -1139,9 +1138,8 @@
};
};
- target-module@8000 { /* 0x4a318000, ap 9 1c.0 */
+ timer1_target: target-module@8000 { /* 0x4a318000, ap 9 1c.0 */
compatible = "ti,sysc-omap2-timer", "ti,sysc";
- ti,hwmods = "timer1";
reg = <0x8000 0x4>,
<0x8010 0x4>,
<0x8014 0x4>;
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 763bdea8c829..6c2b07f0704d 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -655,3 +655,13 @@
#reset-cells = <1>;
};
};
+
+/* Preferred always-on timer for clockevent */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
+ assigned-clock-parents = <&sys_clkin_ck>;
+ };
+};
diff --git a/arch/arm/boot/dts/omap5-l4.dtsi b/arch/arm/boot/dts/omap5-l4.dtsi
index f68740abb8aa..a7e718c4ccea 100644
--- a/arch/arm/boot/dts/omap5-l4.dtsi
+++ b/arch/arm/boot/dts/omap5-l4.dtsi
@@ -2150,7 +2150,6 @@
target-module@4000 { /* 0x4ae04000, ap 17 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "counter_32k";
reg = <0x4000 0x4>,
<0x4010 0x4>;
reg-names = "rev", "sysc";
@@ -2336,9 +2335,8 @@
};
};
- target-module@8000 { /* 0x4ae18000, ap 9 18.0 */
+ timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 18.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer1";
reg = <0x8000 0x4>,
<0x8010 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 2ac7f021c284..e30a556f7c18 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -581,3 +581,13 @@
#reset-cells = <1>;
};
};
+
+/* Preferred always-on timer for clockevent */
+&timer1_target {
+ ti,no-reset-on-init;
+ ti,no-idle;
+ timer@0 {
+ assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
+ assigned-clock-parents = <&sys_32k_ck>;
+ };
+};
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-12 03:52:31 +0300