diff options
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt8195.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8195.dtsi | 233 |
1 files changed, 229 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 905d1a90b406..5d31536f4c48 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/phy/phy.h> #include <dt-bindings/pinctrl/mt8195-pinfunc.h> #include <dt-bindings/power/mt8195-power.h> +#include <dt-bindings/reset/mt8195-resets.h> / { compatible = "mediatek,mt8195"; @@ -36,7 +37,7 @@ enable-method = "psci"; performance-domains = <&performance 0>; clock-frequency = <1701000000>; - capacity-dmips-mhz = <578>; + capacity-dmips-mhz = <308>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; next-level-cache = <&l2_0>; #cooling-cells = <2>; @@ -49,7 +50,7 @@ enable-method = "psci"; performance-domains = <&performance 0>; clock-frequency = <1701000000>; - capacity-dmips-mhz = <578>; + capacity-dmips-mhz = <308>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; next-level-cache = <&l2_0>; #cooling-cells = <2>; @@ -62,7 +63,7 @@ enable-method = "psci"; performance-domains = <&performance 0>; clock-frequency = <1701000000>; - capacity-dmips-mhz = <578>; + capacity-dmips-mhz = <308>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; next-level-cache = <&l2_0>; #cooling-cells = <2>; @@ -75,7 +76,7 @@ enable-method = "psci"; performance-domains = <&performance 0>; clock-frequency = <1701000000>; - capacity-dmips-mhz = <578>; + capacity-dmips-mhz = <308>; cpu-idle-states = <&cpu_off_l &cluster_off_l>; next-level-cache = <&l2_0>; #cooling-cells = <2>; @@ -213,16 +214,19 @@ l2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l2_1: l2-cache1 { compatible = "cache"; + cache-level = <2>; next-level-cache = <&l3_0>; }; l3_0: l3-cache { compatible = "cache"; + cache-level = <3>; }; }; @@ -1182,6 +1186,110 @@ status = "disabled"; }; + pcie0: pcie@112f0000 { + compatible = "mediatek,mt8195-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x112f0000 0 0x4000>; + reg-names = "pcie-mac"; + interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x20000000 + 0x0 0x20000000 0 0x200000>, + <0x82000000 0 0x20200000 + 0x0 0x20200000 0 0x3e00000>; + + iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; + iommu-map-mask = <0x0>; + + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + clock-names = "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + assigned-clocks = <&topckgen CLK_TOP_TL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; + + phys = <&pciephy>; + phy-names = "pcie-phy"; + + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; + + resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; + reset-names = "mac"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + status = "disabled"; + + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@112f8000 { + compatible = "mediatek,mt8195-pcie", + "mediatek,mt8192-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0 0x112f8000 0 0x4000>; + reg-names = "pcie-mac"; + interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x24000000 + 0x0 0x24000000 0 0x200000>, + <0x82000000 0 0x24200000 + 0x0 0x24200000 0 0x3e00000>; + + iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; + iommu-map-mask = <0x0>; + + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + /* Designer has connect pcie1 with peri_mem_p0 clock */ + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + clock-names = "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + assigned-clocks = <&topckgen CLK_TOP_TL_P1>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; + + phys = <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; + + resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; + reset-names = "mac"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + status = "disabled"; + + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + nor_flash: spi@1132c000 { compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor"; @@ -1241,6 +1349,37 @@ reg = <0x189 0x2>; bits = <7 5>; }; + pciephy_rx_ln1: pciephy-rx-ln1@190,1 { + reg = <0x190 0x1>; + bits = <0 4>; + }; + pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { + reg = <0x190 0x1>; + bits = <4 4>; + }; + pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { + reg = <0x191 0x1>; + bits = <0 4>; + }; + pciephy_rx_ln0: pciephy-rx-ln0@191,2 { + reg = <0x191 0x1>; + bits = <4 4>; + }; + pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { + reg = <0x192 0x1>; + bits = <0 4>; + }; + pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { + reg = <0x192 0x1>; + bits = <4 4>; + }; + pciephy_glb_intr: pciephy-glb-intr@193 { + reg = <0x193 0x1>; + bits = <0 4>; + }; + dp_calibration: dp-data@1ac { + reg = <0x1ac 0x10>; + }; }; u3phy2: t-phy@11c40000 { @@ -1461,6 +1600,23 @@ }; }; + pciephy: phy@11e80000 { + compatible = "mediatek,mt8195-pcie-phy"; + reg = <0 0x11e80000 0 0x10000>; + reg-names = "sif"; + nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, + <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, + <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, + <&pciephy_rx_ln1>; + nvmem-cell-names = "glb_intr", "tx_ln0_pmos", + "tx_ln0_nmos", "rx_ln0", + "tx_ln1_pmos", "tx_ln1_nmos", + "rx_ln1"; + power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; + #phy-cells = <0>; + status = "disabled"; + }; + ufsphy: ufs-phy@11fa0000 { compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; reg = <0 0x11fa0000 0 0xc000>; @@ -1959,6 +2115,30 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; }; + venc: video-codec@1a020000 { + compatible = "mediatek,mt8195-vcodec-enc"; + reg = <0 0x1a020000 0 0x10000>; + iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, + <&iommu_vdo M4U_PORT_L19_VENC_REC>, + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; + interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; + mediatek,scp = <&scp>; + clocks = <&vencsys CLK_VENC_VENC>; + clock-names = "venc_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + }; + vencsys_core1: clock-controller@1b000000 { compatible = "mediatek,mt8195-vencsys_core1"; reg = <0 0x1b000000 0 0x1000>; @@ -2067,6 +2247,17 @@ mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; }; + dp_intf0: dp-intf@1c015000 { + compatible = "mediatek,mt8195-dp-intf"; + reg = <0 0x1c015000 0 0x1000>; + interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, + <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, + <&apmixedsys CLK_APMIXED_TVDPLL1>; + clock-names = "engine", "pixel", "pll"; + status = "disabled"; + }; + mutex: mutex@1c016000 { compatible = "mediatek,mt8195-disp-mutex"; reg = <0 0x1c016000 0 0x1000>; @@ -2155,5 +2346,39 @@ clock-names = "apb", "smi", "gals"; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; }; + + dp_intf1: dp-intf@1c113000 { + compatible = "mediatek,mt8195-dp-intf"; + reg = <0 0x1c113000 0 0x1000>; + interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, + <&vdosys1 CLK_VDO1_DPINTF>, + <&apmixedsys CLK_APMIXED_TVDPLL2>; + clock-names = "engine", "pixel", "pll"; + status = "disabled"; + }; + + edp_tx: edp-tx@1c500000 { + compatible = "mediatek,mt8195-edp-tx"; + reg = <0 0x1c500000 0 0x8000>; + nvmem-cells = <&dp_calibration>; + nvmem-cell-names = "dp_calibration_data"; + power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; + interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; + max-linkrate-mhz = <8100>; + status = "disabled"; + }; + + dp_tx: dp-tx@1c600000 { + compatible = "mediatek,mt8195-dp-tx"; + reg = <0 0x1c600000 0 0x8000>; + nvmem-cells = <&dp_calibration>; + nvmem-cell-names = "dp_calibration_data"; + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; + max-linkrate-mhz = <8100>; + status = "disabled"; + }; }; }; |