diff options
Diffstat (limited to 'arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi | 27 |
1 files changed, 7 insertions, 20 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi index e9b57b87e42e..e2584a5efe34 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) Siemens AG, 2021 + * Copyright (c) Siemens AG, 2021-2023 * * Authors: * Chao Zeng <chao.zeng@siemens.com> @@ -9,6 +9,11 @@ * Common bits of the IOT2050 Basic and Advanced variants, PG2 */ +&mcu_r5fss0 { + /* lock-step mode not supported on PG2 boards */ + ti,cluster-mode = <0>; +}; + &main_pmx0 { cp2102n_reset_pin_default: cp2102n-reset-default-pins { pinctrl-single,pins = < @@ -33,21 +38,3 @@ /* Workaround needed to get DP clock of 154Mhz */ assigned-clocks = <&k3_clks 67 0>; }; - -&serdes0 { - assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; - assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; -}; - -&dwc3_0 { - assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ - <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ - phys = <&serdes0 PHY_TYPE_USB3 0>; - phy-names = "usb3-phy"; -}; - -&usb0 { - maximum-speed = "super-speed"; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; -}; |