diff options
Diffstat (limited to 'drivers/clk/microchip/clk-mpfs.c')
| -rw-r--r-- | drivers/clk/microchip/clk-mpfs.c | 375 |
1 files changed, 185 insertions, 190 deletions
diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index b6b89413e090..4f0a19db7ed7 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -1,14 +1,17 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Daire McNamara,<daire.mcnamara@microchip.com> - * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. + * PolarFire SoC MSS/core complex clock control + * + * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. */ +#include <linux/auxiliary_bus.h> #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <dt-bindings/clock/microchip,mpfs-clock.h> +#include <soc/microchip/mpfs.h> /* address offset of control registers */ #define REG_MSSPLL_REF_CR 0x08u @@ -28,6 +31,7 @@ #define MSSPLL_FIXED_DIV 4u struct mpfs_clock_data { + struct device *dev; void __iomem *base; void __iomem *msspll_base; struct clk_hw_onecell_data hw_data; @@ -46,37 +50,18 @@ struct mpfs_msspll_hw_clock { #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) -struct mpfs_cfg_clock { - const struct clk_div_table *table; - unsigned int id; - u32 reg_offset; - u8 shift; - u8 width; - u8 flags; -}; - struct mpfs_cfg_hw_clock { - struct mpfs_cfg_clock cfg; - void __iomem *sys_base; - struct clk_hw hw; + struct clk_divider cfg; struct clk_init_data init; -}; - -#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw) - -struct mpfs_periph_clock { unsigned int id; - u8 shift; + u32 reg_offset; }; struct mpfs_periph_hw_clock { - struct mpfs_periph_clock periph; - void __iomem *sys_base; - struct clk_hw hw; + struct clk_gate periph; + unsigned int id; }; -#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw) - /* * mpfs_clk_lock prevents anything else from writing to the * mpfs clk block while a software locked register is being written. @@ -126,8 +111,62 @@ static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned lon return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); } +static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) +{ + struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); + void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; + void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; + u32 mult, ref_div; + unsigned long rate_before_ctrl; + + mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; + mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); + ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; + ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); + + rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; + + return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, + msspll_hw->flags); +} + +static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) +{ + struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); + void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; + void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; + void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; + u32 mult, ref_div, postdiv; + int divider_setting; + unsigned long rate_before_ctrl, flags; + + mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; + mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); + ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; + ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); + + rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; + divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, + msspll_hw->flags); + + if (divider_setting < 0) + return divider_setting; + + spin_lock_irqsave(&mpfs_clk_lock, flags); + + postdiv = readl_relaxed(postdiv_addr); + postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); + writel_relaxed(postdiv, postdiv_addr); + + spin_unlock_irqrestore(&mpfs_clk_lock, flags); + + return 0; +} + static const struct clk_ops mpfs_clk_msspll_ops = { .recalc_rate = mpfs_clk_msspll_recalc_rate, + .round_rate = mpfs_clk_msspll_round_rate, + .set_rate = mpfs_clk_msspll_set_rate, }; #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ @@ -144,25 +183,17 @@ static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), }; -static int mpfs_clk_register_msspll(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hw, - void __iomem *base) -{ - msspll_hw->base = base; - - return devm_clk_hw_register(dev, &msspll_hw->hw); -} - static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws, unsigned int num_clks, struct mpfs_clock_data *data) { - void __iomem *base = data->msspll_base; unsigned int i; int ret; for (i = 0; i < num_clks; i++) { struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i]; - ret = mpfs_clk_register_msspll(dev, msspll_hw, base); + msspll_hw->base = data->msspll_base; + ret = devm_clk_hw_register(dev, &msspll_hw->hw); if (ret) return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", CLK_MSSPLL); @@ -177,66 +208,15 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c * "CFG" clocks */ -static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) -{ - struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); - struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - void __iomem *base_addr = cfg_hw->sys_base; - u32 val; - - val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift; - val &= clk_div_mask(cfg->width); - - return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width); -} - -static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) -{ - struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); - struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - - return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0); -} - -static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) -{ - struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw); - struct mpfs_cfg_clock *cfg = &cfg_hw->cfg; - void __iomem *base_addr = cfg_hw->sys_base; - unsigned long flags; - u32 val; - int divider_setting; - - divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0); - - if (divider_setting < 0) - return divider_setting; - - spin_lock_irqsave(&mpfs_clk_lock, flags); - val = readl_relaxed(base_addr + cfg->reg_offset); - val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); - val |= divider_setting << cfg->shift; - writel_relaxed(val, base_addr + cfg->reg_offset); - - spin_unlock_irqrestore(&mpfs_clk_lock, flags); - - return 0; -} - -static const struct clk_ops mpfs_clk_cfg_ops = { - .recalc_rate = mpfs_cfg_clk_recalc_rate, - .round_rate = mpfs_cfg_clk_round_rate, - .set_rate = mpfs_cfg_clk_set_rate, -}; - #define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \ - .cfg.id = _id, \ + .id = _id, \ .cfg.shift = _shift, \ .cfg.width = _width, \ .cfg.table = _table, \ - .cfg.reg_offset = _offset, \ + .reg_offset = _offset, \ .cfg.flags = _flags, \ - .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \ + .cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ + .cfg.lock = &mpfs_clk_lock, \ } #define CLK_CPU_OFFSET 0u @@ -252,42 +232,34 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = { CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0, REG_CLOCK_CONFIG_CR), { - .cfg.id = CLK_RTCREF, + .id = CLK_RTCREF, .cfg.shift = 0, .cfg.width = 12, .cfg.table = mpfs_div_rtcref_table, - .cfg.reg_offset = REG_RTC_CLOCK_CR, + .reg_offset = REG_RTC_CLOCK_CR, .cfg.flags = CLK_DIVIDER_ONE_BASED, - .hw.init = - CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0), + .cfg.hw.init = + CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0), } }; -static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw, - void __iomem *sys_base) -{ - cfg_hw->sys_base = sys_base; - - return devm_clk_hw_register(dev, &cfg_hw->hw); -} - static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws, unsigned int num_clks, struct mpfs_clock_data *data) { - void __iomem *sys_base = data->base; unsigned int i, id; int ret; for (i = 0; i < num_clks; i++) { struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i]; - ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base); + cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset; + ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", - cfg_hw->cfg.id); + cfg_hw->id); - id = cfg_hw->cfg.id; - data->hw_data.hws[id] = &cfg_hw->hw; + id = cfg_hw->id; + data->hw_data.hws[id] = &cfg_hw->cfg.hw; } return 0; @@ -297,77 +269,15 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock * * peripheral clocks - devices connected to axi or ahb buses. */ -static int mpfs_periph_clk_enable(struct clk_hw *hw) -{ - struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); - struct mpfs_periph_clock *periph = &periph_hw->periph; - void __iomem *base_addr = periph_hw->sys_base; - u32 reg, val; - unsigned long flags; - - spin_lock_irqsave(&mpfs_clk_lock, flags); - - reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); - val = reg & ~(1u << periph->shift); - writel_relaxed(val, base_addr + REG_SUBBLK_RESET_CR); - - reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); - val = reg | (1u << periph->shift); - writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); - - spin_unlock_irqrestore(&mpfs_clk_lock, flags); - - return 0; -} - -static void mpfs_periph_clk_disable(struct clk_hw *hw) -{ - struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); - struct mpfs_periph_clock *periph = &periph_hw->periph; - void __iomem *base_addr = periph_hw->sys_base; - u32 reg, val; - unsigned long flags; - - spin_lock_irqsave(&mpfs_clk_lock, flags); - - reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); - val = reg & ~(1u << periph->shift); - writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); - - spin_unlock_irqrestore(&mpfs_clk_lock, flags); -} - -static int mpfs_periph_clk_is_enabled(struct clk_hw *hw) -{ - struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw); - struct mpfs_periph_clock *periph = &periph_hw->periph; - void __iomem *base_addr = periph_hw->sys_base; - u32 reg; - - reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); - if ((reg & (1u << periph->shift)) == 0u) { - reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); - if (reg & (1u << periph->shift)) - return 1; - } - - return 0; -} - -static const struct clk_ops mpfs_periph_clk_ops = { - .enable = mpfs_periph_clk_enable, - .disable = mpfs_periph_clk_disable, - .is_enabled = mpfs_periph_clk_is_enabled, -}; - #define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \ - .periph.id = _id, \ - .periph.shift = _shift, \ - .hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \ + .id = _id, \ + .periph.bit_idx = _shift, \ + .periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \ _flags), \ + .periph.lock = &mpfs_clk_lock, \ } -#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].hw) +#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw) /* * Critical clocks: @@ -415,36 +325,116 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = { CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0), }; -static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw, - void __iomem *sys_base) -{ - periph_hw->sys_base = sys_base; - - return devm_clk_hw_register(dev, &periph_hw->hw); -} - static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws, int num_clks, struct mpfs_clock_data *data) { - void __iomem *sys_base = data->base; unsigned int i, id; int ret; for (i = 0; i < num_clks; i++) { struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i]; - ret = mpfs_clk_register_periph(dev, periph_hw, sys_base); + periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR; + ret = devm_clk_hw_register(dev, &periph_hw->periph.hw); if (ret) return dev_err_probe(dev, ret, "failed to register clock id: %d\n", - periph_hw->periph.id); + periph_hw->id); + + id = periph_hws[i].id; + data->hw_data.hws[id] = &periph_hw->periph.hw; + } + + return 0; +} - id = periph_hws[i].periph.id; - data->hw_data.hws[id] = &periph_hw->hw; +/* + * Peripheral clock resets + */ + +#if IS_ENABLED(CONFIG_RESET_CONTROLLER) + +u32 mpfs_reset_read(struct device *dev) +{ + struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); + + return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR); +} +EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS); + +void mpfs_reset_write(struct device *dev, u32 val) +{ + struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); + + writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR); +} +EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS); + +static void mpfs_reset_unregister_adev(void *_adev) +{ + struct auxiliary_device *adev = _adev; + + auxiliary_device_delete(adev); +} + +static void mpfs_reset_adev_release(struct device *dev) +{ + struct auxiliary_device *adev = to_auxiliary_dev(dev); + + auxiliary_device_uninit(adev); + + kfree(adev); +} + +static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data) +{ + struct auxiliary_device *adev; + int ret; + + adev = kzalloc(sizeof(*adev), GFP_KERNEL); + if (!adev) + return ERR_PTR(-ENOMEM); + + adev->name = "reset-mpfs"; + adev->dev.parent = clk_data->dev; + adev->dev.release = mpfs_reset_adev_release; + adev->id = 666u; + + ret = auxiliary_device_init(adev); + if (ret) { + kfree(adev); + return ERR_PTR(ret); + } + + return adev; +} + +static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) +{ + struct auxiliary_device *adev; + int ret; + + adev = mpfs_reset_adev_alloc(clk_data); + if (IS_ERR(adev)) + return PTR_ERR(adev); + + ret = auxiliary_device_add(adev); + if (ret) { + auxiliary_device_uninit(adev); + return ret; } + return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev); +} + +#else /* !CONFIG_RESET_CONTROLLER */ + +static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) +{ return 0; } +#endif /* !CONFIG_RESET_CONTROLLER */ + static int mpfs_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -469,6 +459,8 @@ static int mpfs_clk_probe(struct platform_device *pdev) return PTR_ERR(clk_data->msspll_base); clk_data->hw_data.num = num_clks; + clk_data->dev = dev; + dev_set_drvdata(dev, clk_data); ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks), clk_data); @@ -488,14 +480,14 @@ static int mpfs_clk_probe(struct platform_device *pdev) if (ret) return ret; - return ret; + return mpfs_reset_controller_register(clk_data); } static const struct of_device_id mpfs_clk_of_match_table[] = { { .compatible = "microchip,mpfs-clkcfg", }, {} }; -MODULE_DEVICE_TABLE(of, mpfs_clk_match_table); +MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table); static struct platform_driver mpfs_clk_driver = { .probe = mpfs_clk_probe, @@ -518,4 +510,7 @@ static void __exit clk_mpfs_exit(void) module_exit(clk_mpfs_exit); MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver"); -MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Padmarao Begari <padmarao.begari@microchip.com>"); +MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>"); +MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>"); +MODULE_LICENSE("GPL"); |