diff options
Diffstat (limited to 'drivers/clk/sifive/fu540-prci.c')
| -rw-r--r-- | drivers/clk/sifive/fu540-prci.c | 29 |
1 files changed, 12 insertions, 17 deletions
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index 9e13119066eb..672c782ad604 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2018-2019 SiFive, Inc. + * Copyright (C) 2018-2022 SiFive, Inc. * Copyright (C) 2018-2019 Wesley Terpstra * Copyright (C) 2018-2019 Paul Walmsley - * Copyright (C) 2020 Zong Li + * Copyright (C) 2020-2022 Zong Li * * The FU540 PRCI implements clock and reset control for the SiFive * FU540-C000 chip. This driver assumes that it has sole control @@ -22,26 +22,21 @@ #include "sifive-prci.h" -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_TLCLK 3 - /* PRCI integration data for each WRPLL instance */ -static struct __prci_wrpll_data __prci_corepll_data = { +static struct __prci_wrpll_data sifive_fu540_prci_corepll_data = { .cfg0_offs = PRCI_COREPLLCFG0_OFFSET, .cfg1_offs = PRCI_COREPLLCFG1_OFFSET, .enable_bypass = sifive_prci_coreclksel_use_hfclk, .disable_bypass = sifive_prci_coreclksel_use_corepll, }; -static struct __prci_wrpll_data __prci_ddrpll_data = { +static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data = { .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET, .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET, }; -static struct __prci_wrpll_data __prci_gemgxlpll_data = { +static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data = { .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, }; @@ -67,25 +62,25 @@ static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops = { /* List of clock controls provided by the PRCI */ struct __prci_clock __prci_init_clocks_fu540[] = { - [PRCI_CLK_COREPLL] = { + [FU540_PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, - .pwd = &__prci_corepll_data, + .pwd = &sifive_fu540_prci_corepll_data, }, - [PRCI_CLK_DDRPLL] = { + [FU540_PRCI_CLK_DDRPLL] = { .name = "ddrpll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_ro_clk_ops, - .pwd = &__prci_ddrpll_data, + .pwd = &sifive_fu540_prci_ddrpll_data, }, - [PRCI_CLK_GEMGXLPLL] = { + [FU540_PRCI_CLK_GEMGXLPLL] = { .name = "gemgxlpll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, - .pwd = &__prci_gemgxlpll_data, + .pwd = &sifive_fu540_prci_gemgxlpll_data, }, - [PRCI_CLK_TLCLK] = { + [FU540_PRCI_CLK_TLCLK] = { .name = "tlclk", .parent_name = "corepll", .ops = &sifive_fu540_prci_tlclksel_clk_ops, |